Revision 162:e13f6fdb2ac4, committed 2017-04-12

Comitter:

<>

Date:

Wed Apr 12 16:21:43 2017 +0100

Parent:

161:2cc1468da177

Child:

163:74e0ce7f98e8

Commit message:

This updates the lib to the mbed lib v140

Changed in this revision

--- a/hal/mbed_ticker_api.c	Thu Mar 30 13:45:57 2017 +0100
+++ b/hal/mbed_ticker_api.c	Wed Apr 12 16:21:43 2017 +0100
@@ -74,6 +74,10 @@
         prev = p;
         p = p->next;
     }
+    
+    /* if we're at the end p will be NULL, which is correct */
+    obj->next = p;
+
     /* if prev is NULL we're at the head */
     if (prev == NULL) {
         data->queue->head = obj;
@@ -81,8 +85,6 @@
     } else {
         prev->next = obj;
     }
-    /* if we're at the end p will be NULL, which is correct */
-    obj->next = p;
 
     core_util_critical_section_exit();
 }

--- a/mbed.h	Thu Mar 30 13:45:57 2017 +0100
+++ b/mbed.h	Wed Apr 12 16:21:43 2017 +0100
@@ -16,13 +16,13 @@
 #ifndef MBED_H
 #define MBED_H
 
-#define MBED_LIBRARY_VERSION 139
+#define MBED_LIBRARY_VERSION 140
 
 #if MBED_CONF_RTOS_PRESENT
 // RTOS present, this is valid only for mbed OS 5
 #define MBED_MAJOR_VERSION 5
 #define MBED_MINOR_VERSION 4
-#define MBED_PATCH_VERSION 2
+#define MBED_PATCH_VERSION 3
 
 #else
 // mbed 2

--- a/platform/mbed_semihost_api.c	Thu Mar 30 13:45:57 2017 +0100
+++ b/platform/mbed_semihost_api.c	Wed Apr 12 16:21:43 2017 +0100
@@ -152,10 +152,11 @@
 #endif
 
 int semihost_disabledebug(void) {
+    uint32_t args[1];
 #if !(DEVICE_DEBUG_AWARENESS)
     is_debugger_attached = 0;
 #endif
-    return __semihost(USR_DISABLEDEBUG, NULL);
+    return __semihost(USR_DISABLEDEBUG, &args);
 }
 
 #endif

--- a/targets/TARGET_Freescale/TARGET_KLXX/us_ticker.c	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_KLXX/us_ticker.c	Wed Apr 12 16:21:43 2017 +0100
@@ -187,11 +187,11 @@
 void us_ticker_set_interrupt(timestamp_t timestamp) {
     int delta = (int)((uint32_t)timestamp - us_ticker_read());
     if (delta <= 0) {
-        // This event was in the past:
-        us_ticker_irq_handler();
-        return;
-    }
-    
+        // This event was in the past.  Force it into the very near
+	// future instead.
+	delta = 1;
+    } 
+	
     us_ticker_int_counter   = (uint32_t)(delta >> 16);
     us_ticker_int_remainder = (uint16_t)(0xFFFF & delta);
     if (us_ticker_int_counter > 0) {

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/MK66FN2M0xxx18.ld	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/MK66FN2M0xxx18.ld	Wed Apr 12 16:21:43 2017 +0100
@@ -50,9 +50,15 @@
 
 __ram_vector_table__ = 1;
 
-/* Heap 1/4 of ram and stack 1/8 */
-__stack_size__ = 0x8000;
-__heap_size__ = 0x10000;
+/* With the RTOS in use, this does not affect the main stack size. The size of
+ * the stack where main runs is determined via the RTOS. */
+__stack_size__ = 0x400;
+
+/* This is the guaranteed minimum available heap size for an application. When
+ * uVisor is enabled, this is also the maximum available heap size. The
+ * HEAP_SIZE value is set by uVisor porters to balance the size of the legacy
+ * heap and the page heap in uVisor applications. */
+__heap_size__ = 0x6000;
 
 HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
 STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
@@ -223,7 +229,7 @@
     . = ALIGN(4);
     __bss_end__ = .;
     __END_BSS = .;
-  } > m_data
+  } > m_data_2
 
   .heap :
   {

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/device/TOOLCHAIN_GCC_ARM/MK82FN256xxx15.ld	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/device/TOOLCHAIN_GCC_ARM/MK82FN256xxx15.ld	Wed Apr 12 16:21:43 2017 +0100
@@ -52,9 +52,15 @@
 
 __ram_vector_table__ = 1;
 
-/* Heap 1/4 of ram and stack 1/8 */
-__stack_size__ = 0x8000;
-__heap_size__ = 0x10000;
+/* With the RTOS in use, this does not affect the main stack size. The size of
+ * the stack where main runs is determined via the RTOS. */
+__stack_size__ = 0x400;
+
+/* This is the guaranteed minimum available heap size for an application. When
+ * uVisor is enabled, this is also the maximum available heap size. The
+ * HEAP_SIZE value is set by uVisor porters to balance the size of the legacy
+ * heap and the page heap in uVisor applications. */
+__heap_size__ = 0x6000;
 
 HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
 STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/device/TOOLCHAIN_GCC_ARM/MKL27Z64xxx4.ld	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/device/TOOLCHAIN_GCC_ARM/MKL27Z64xxx4.ld	Wed Apr 12 16:21:43 2017 +0100
@@ -53,9 +53,11 @@
 
 __ram_vector_table__ = 1;
 
-/* Heap 1/4 of ram and stack 1/8 */
-__stack_size__ = 0x800;
-__heap_size__ = 0x1000;
+/* With the RTOS in use, this does not affect the main stack size. The size of
+ * the stack where main runs is determined via the RTOS. */
+__stack_size__ = 0x400;
+/* With the RTOS in use, this does not affect the main heap size. */
+__heap_size__ = 0x0;
 
 HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
 STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_GCC_ARM/MKL43Z256xxx4.ld	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_GCC_ARM/MKL43Z256xxx4.ld	Wed Apr 12 16:21:43 2017 +0100
@@ -50,8 +50,14 @@
 
 __ram_vector_table__ = 1;
 
-/* Heap 1/4 of ram and stack 1/8 */
-__stack_size__ = 0x1000;
+/* With the RTOS in use, this does not affect the main stack size. The size of
+ * the stack where main runs is determined via the RTOS. */
+__stack_size__ = 0x400;
+
+/* This is the guaranteed minimum available heap size for an application. When
+ * uVisor is enabled, this is also the maximum available heap size. The
+ * HEAP_SIZE value is set by uVisor porters to balance the size of the legacy
+ * heap and the page heap in uVisor applications. */
 __heap_size__ = 0x2800;
 
 HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_GCC_ARM/MKL82Z128xxx7.ld	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_GCC_ARM/MKL82Z128xxx7.ld	Wed Apr 12 16:21:43 2017 +0100
@@ -53,8 +53,14 @@
 
 __ram_vector_table__ = 1;
 
-/* Heap 1/4 of ram and stack 1/8 */
-__stack_size__ = 0x3000;
+/* With the RTOS in use, this does not affect the main stack size. The size of
+ * the stack where main runs is determined via the RTOS. */
+__stack_size__ = 0x400;
+
+/* This is the guaranteed minimum available heap size for an application. When
+ * uVisor is enabled, this is also the maximum available heap size. The
+ * HEAP_SIZE value is set by uVisor porters to balance the size of the legacy
+ * heap and the page heap in uVisor applications. */
 __heap_size__ = 0x6000;
 
 HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/PeripheralPins.c	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
@@ -57,14 +57,14 @@
     {PTA2,  UART_0, 2},
     {PTD7,  UART_0, 3},
     {PTC4,  UART_1, 3},
-    {PTE0,  UART_1, 3},    
+    {PTE0,  UART_1, 3},
     {PTD3,  UART_2, 3},
     {PTE16, UART_2, 3},
     {NC   , NC    , 0}
 };
 
 const PinMap PinMap_UART_RX[] = {
-    {PTA1,  UART_0, 2},    
+    {PTA1,  UART_0, 2},
     {PTD6,  UART_0, 3},
     {PTE1,  UART_1, 3},
     {PTD2,  UART_2, 3},
@@ -92,6 +92,7 @@
 
 /************SPI***************/
 const PinMap PinMap_SPI_SCLK[] = {
+    {PTB11, SPI_1, 2},
     {PTC5,  SPI_0, 2},
     {PTD1,  SPI_0, 2},
     {PTE2,  SPI_1, 2},
@@ -100,6 +101,7 @@
 };
 
 const PinMap PinMap_SPI_MOSI[] = {
+    {PTB16, SPI_1, 2},
     {PTC6,  SPI_0, 2},
     {PTD2,  SPI_0, 2},
     {PTE1,  SPI_1, 2},
@@ -109,6 +111,7 @@
 };
 
 const PinMap PinMap_SPI_MISO[] = {
+    {PTB17, SPI_1, 2},
     {PTC7,  SPI_0, 2},
     {PTD3,  SPI_0, 2},
     {PTE1,  SPI_1, 7},
@@ -118,6 +121,7 @@
 };
 
 const PinMap PinMap_SPI_SSEL[] = {
+    {PTB10, SPI_1, 2},
     {PTC4,  SPI_0, 2},
     {PTE4,  SPI_1, 2},
     {PTE16, SPI_0, 2},

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/PinNames.h	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/TARGET_FRDM/PinNames.h	Wed Apr 12 16:21:43 2017 +0100
@@ -87,11 +87,16 @@
     USBTX = PTE0,
     USBRX = PTE1,
 
+    // Not connected
+    NC = (int)0xFFFFFFFF,
+
     // Arduino Headers
     D0 = PTD7,
     D1 = PTD6,
     D2 = PTD5,
     D3 = PTD4,
+    D4 = NC,
+    D5 = NC,
     D6 = PTE4,
     D7 = PTD1,
     D8 = PTA19,
@@ -106,8 +111,12 @@
     I2C_SCL = D15,
     I2C_SDA = D14,
 
-    // Not connected
-    NC = (int)0xFFFFFFFF
+    A0 = NC,
+    A1 = NC,
+    A2 = NC,
+    A3 = NC,
+    A4 = NC,
+    A5 = NC
 } PinName;
 
 

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_GCC_ARM/MKW24D512xxx5.ld	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_GCC_ARM/MKW24D512xxx5.ld	Wed Apr 12 16:21:43 2017 +0100
@@ -48,8 +48,14 @@
 
 __ram_vector_table__ = 1;
 
-/* Heap 1/4 of ram and stack 1/8 */
-__stack_size__ = 0x2000;
+/* With the RTOS in use, this does not affect the main stack size. The size of
+ * the stack where main runs is determined via the RTOS. */
+__stack_size__ = 0x400;
+
+/* This is the guaranteed minimum available heap size for an application. When
+ * uVisor is enabled, this is also the maximum available heap size. The
+ * HEAP_SIZE value is set by uVisor porters to balance the size of the legacy
+ * heap and the page heap in uVisor applications. */
 __heap_size__ = 0x4000;
 
 HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/TOOLCHAIN_GCC_ARM/MKW41Z512xxx4.ld	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/TOOLCHAIN_GCC_ARM/MKW41Z512xxx4.ld	Wed Apr 12 16:21:43 2017 +0100
@@ -48,9 +48,15 @@
 
 __ram_vector_table__ = 1;
 
-/* Heap 1/4 of ram and stack 1/8 */
-__stack_size__ = 0x4000;
-__heap_size__ = 0x8000;
+/* With the RTOS in use, this does not affect the main stack size. The size of
+ * the stack where main runs is determined via the RTOS. */
+__stack_size__ = 0x400;
+
+/* This is the guaranteed minimum available heap size for an application. When
+ * uVisor is enabled, this is also the maximum available heap size. The
+ * HEAP_SIZE value is set by uVisor porters to balance the size of the legacy
+ * heap and the page heap in uVisor applications. */
+__heap_size__ = 0x6000;
 
 HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x0400;
 STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;

--- a/targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c	Wed Apr 12 16:21:43 2017 +0100
@@ -199,12 +199,13 @@
 
     #if DEVICE_SERIAL_ASYNCH
         if (UART_CB.tx_active) {
-            if (++UART_CB.tx_pos <= UART_CB.tx_length) {
+            if (UART_CB.tx_pos < UART_CB.tx_length) {
                 // When there is still something to send, clear the TXDRDY event
                 // and put next byte to transmitter.
                 nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_TXDRDY);
                 nrf_uart_txd_set(UART_INSTANCE,
                     UART_CB.tx_buffer[UART_CB.tx_pos]);
+                UART_CB.tx_pos++;
             }
             else {
                 // When the TXDRDY event is set after the last byte to be sent

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/PeripheralNames.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,86 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define STDIO_UART_TX     TX_PIN_NUMBER
+#define STDIO_UART_RX     RX_PIN_NUMBER
+#define STDIO_UART        UART_0
+
+typedef enum
+{
+    UART_0 = (int)NRF_UART0_BASE
+} UARTName;
+
+
+typedef enum
+{
+    SPI_0 = (int)NRF_SPI0_BASE,
+    SPI_1 = (int)NRF_SPI1_BASE,
+    SPIS = (int)NRF_SPIS1_BASE
+} SPIName;
+
+typedef enum
+{
+    PWM_1 = 0,
+    PWM_2
+} PWMName;
+
+typedef enum
+{
+    I2C_0 = (int)NRF_TWI0_BASE,
+    I2C_1 = (int)NRF_TWI1_BASE
+} I2CName;
+
+typedef enum
+{
+    ADC0_0 = (int)0
+} ADCName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/PortNames.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,55 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum
+{
+    Port0 = 0, //GPIO pins 0-31 -> 0.0-0.31
+    Port1 = 1  //GPIO pins 32-47 -> 1.0-1.15
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/TARGET_NRF52840_DK/PinNames.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,241 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "nrf_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  3
+
+///> define macro producing for example Px_y = NRF_GPIO_PIN_MAP(x, y)
+#define PinDef(port_num, pin_num) P##port_num##_##pin_num = NRF_GPIO_PIN_MAP(port_num, pin_num)
+
+
+typedef enum {    
+    PinDef(0 , 0), // P0_0 = 0...
+    PinDef(0 , 1),
+    PinDef(0 , 2),
+    PinDef(0 , 3),
+    PinDef(0 , 4),
+    PinDef(0 , 5),
+    PinDef(0 , 6),
+    PinDef(0 , 7),
+    PinDef(0 , 8),
+    PinDef(0 , 9),
+    PinDef(0 , 10),
+    PinDef(0 , 11),
+    PinDef(0 , 12),
+    PinDef(0 , 13),
+    PinDef(0 , 14),
+    PinDef(0 , 15),
+    PinDef(0 , 16),
+    PinDef(0 , 17),
+    PinDef(0 , 18),
+    PinDef(0 , 19),
+    PinDef(0 , 20),
+    PinDef(0 , 21),
+    PinDef(0 , 22),
+    PinDef(0 , 23),
+    PinDef(0 , 24),
+    PinDef(0 , 25),
+    PinDef(0 , 26),
+    PinDef(0 , 27),
+    PinDef(0 , 28),
+    PinDef(0 , 29),
+    PinDef(0 , 30),
+    PinDef(0 , 31),    
+    
+    PinDef(1 , 0), //P1_1 = 32...
+	PinDef(1 , 1),
+	PinDef(1 , 2),
+	PinDef(1 , 3),
+	PinDef(1 , 4),
+	PinDef(1 , 5),
+	PinDef(1 , 6),
+	PinDef(1 , 7),
+	PinDef(1 , 8),
+	PinDef(1 , 9),
+	PinDef(1 , 10),
+	PinDef(1 , 11),
+	PinDef(1 , 12),
+	PinDef(1 , 13),
+	PinDef(1 , 14),
+	PinDef(1 , 15),
+    
+    // Port0
+    p0  = P0_0,
+    p1  = P0_1,
+    p2  = P0_2,
+    p3  = P0_3,
+    p4  = P0_4,
+    p5  = P0_5,
+    p6  = P0_6,
+    p7  = P0_7,
+    p8  = P0_8,
+    p9  = P0_9,
+    p10 = P0_10,
+    p11 = P0_11,
+    p12 = P0_12,
+    p13 = P0_13,
+    p14 = P0_14,
+    p15 = P0_15,
+    p16 = P0_16,
+    p17 = P0_17,
+    p18 = P0_18,
+    p19 = P0_19,
+    p20 = P0_20,
+    p21 = P0_21,
+    p22 = P0_22,
+    p23 = P0_23,
+    p24 = P0_24,
+    p25 = P0_25,
+    p26 = P0_26,
+    p27 = P0_27,
+    p28 = P0_28,
+    p29 = P0_29,
+    p30 = P0_30,
+    p31 = P0_31,
+    
+    // Port1
+    p32 = P1_0,
+    p33 = P1_1,
+    p34 = P1_2,
+    p35 = P1_3,
+    p36 = P1_4,
+    p37 = P1_5,
+    p38 = P1_6,
+    p39 = P1_7,
+    p40 = P1_8,
+    p41 = P1_9,
+    p42 = P1_10,
+    p43 = P1_11,
+    p44 = P1_12,
+    p45 = P1_13,
+    p46 = P1_14,
+    p47 = P1_15,
+    
+    LED1    = p13,
+    LED2    = p14,
+    LED3    = p15,
+    LED4    = p16,
+
+    BUTTON1 = p11,
+    BUTTON2 = p12,
+    BUTTON3 = p24,
+    BUTTON4 = p25,
+
+    RX_PIN_NUMBER  = p8,
+    TX_PIN_NUMBER  = p6,
+    CTS_PIN_NUMBER = p7,
+    RTS_PIN_NUMBER = p5,
+
+    // mBed interface Pins
+    USBTX = TX_PIN_NUMBER,
+    USBRX = RX_PIN_NUMBER,
+
+    SPI_PSELMOSI0 = P1_13,
+    SPI_PSELMISO0 = P1_14,
+    SPI_PSELSS0   = P1_12,
+    SPI_PSELSCK0  = P1_15,
+
+    SPI_PSELMOSI1 = P1_2,
+    SPI_PSELMISO1 = P1_3,
+    SPI_PSELSS1   = P1_1,
+    SPI_PSELSCK1  = P1_4,
+
+    SPIS_PSELMOSI = P1_2,
+    SPIS_PSELMISO = P1_3,
+    SPIS_PSELSS   = P1_1,
+    SPIS_PSELSCK  = P1_4,
+
+    I2C_SDA0 = p26,
+    I2C_SCL0 = p27,
+
+    D0 = P1_1,
+    D1 = P1_2,
+    D2 = P1_3,
+    D3 = P1_4,
+    D4 = P1_5,
+    D5 = P1_6,
+    D6 = P1_7,
+    D7 = P1_8,
+
+    D8  = P1_10,
+    D9  = P1_11,
+    D10 = P1_12,
+    D11 = P1_13,
+    D12 = P1_14,
+    D13 = P1_15,
+
+    D14 = p26,
+    D15 = p27,
+
+    A0 = p3,
+    A1 = p4,
+    A2 = p28,
+    A3 = p29,
+    A4 = p30,
+    A5 = p31,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullNone = 0,
+    PullDown = 1,
+    PullUp = 3,
+    PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/TARGET_NRF52840_DK/device.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,38 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#include "objects.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52832.sct	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,13 @@
+LR_IROM1 0x21000 0x00DF000  {
+  ER_IROM1 0x21000 0x00DF000  {
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM0 0x20003288 UNINIT 0x000000F8  { ;no init section
+        *(noinit)
+  }
+  RW_IRAM1 0x20003380 0x0003cc80  {
+   .ANY (+RW +ZI)
+  }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/startup_nrf52832.s	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,269 @@
+;/* Copyright (c) 2012 ARM LIMITED
+;
+;   All rights reserved.
+;   Redistribution and use in source and binary forms, with or without
+;   modification, are permitted provided that the following conditions are met:
+;   - Redistributions of source code must retain the above copyright
+;     notice, this list of conditions and the following disclaimer.
+;   - Redistributions in binary form must reproduce the above copyright
+;     notice, this list of conditions and the following disclaimer in the
+;     documentation and/or other materials provided with the distribution.
+;   - Neither the name of ARM nor the names of its contributors may be used
+;     to endorse or promote products derived from this software without
+;     specific prior written permission.
+;   *
+;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;   POSSIBILITY OF SUCH DAMAGE.
+;   ---------------------------------------------------------------------------*/
+
+__initial_sp	EQU     0x20040000
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler
+                DCD     NMI_Handler
+                DCD     HardFault_Handler
+                DCD     MemoryManagement_Handler
+                DCD     BusFault_Handler
+                DCD     UsageFault_Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler
+                DCD     DebugMonitor_Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler
+                DCD     SysTick_Handler
+
+                ; External Interrupts
+                DCD     POWER_CLOCK_IRQHandler
+                DCD     RADIO_IRQHandler
+                DCD     UARTE0_UART0_IRQHandler_v
+                DCD     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v
+                DCD     SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v
+                DCD     NFCT_IRQHandler_v
+                DCD     GPIOTE_IRQHandler_v
+                DCD     SAADC_IRQHandler_v
+                DCD     TIMER0_IRQHandler_v
+                DCD     TIMER1_IRQHandler_v
+                DCD     TIMER2_IRQHandler_v
+                DCD     RTC0_IRQHandler
+                DCD     TEMP_IRQHandler_v
+                DCD     RNG_IRQHandler
+                DCD     ECB_IRQHandler
+                DCD     CCM_AAR_IRQHandler
+                DCD     WDT_IRQHandler_v
+                DCD     RTC1_IRQHandler_v
+                DCD     QDEC_IRQHandler_v
+                DCD     COMP_LPCOMP_IRQHandler_v
+                DCD     SWI0_EGU0_IRQHandler_v
+                DCD     SWI1_EGU1_IRQHandler_v
+                DCD     SWI2_EGU2_IRQHandler_v
+                DCD     SWI3_EGU3_IRQHandler_v
+                DCD     SWI4_EGU4_IRQHandler
+                DCD     SWI5_EGU5_IRQHandler
+                DCD     TIMER3_IRQHandler_v
+                DCD     TIMER4_IRQHandler_v
+                DCD     PWM0_IRQHandler_v
+                DCD     PDM_IRQHandler_v
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     MWU_IRQHandler
+                DCD     PWM1_IRQHandler_v
+                DCD     PWM2_IRQHandler_v
+                DCD     SPIM2_SPIS2_SPI2_IRQHandler_v
+                DCD     RTC2_IRQHandler_v
+                DCD     I2S_IRQHandler_v
+                DCD     FPU_IRQHandler_v
+                DCD     USBD_IRQHandler_v
+                DCD     UARTE1_IRQHandler_v
+                DCD     QSPI_IRQHandler_v
+                DCD     CRYPTOCELL_IRQHandler_v
+                DCD     SPIM3_IRQHandler_v       
+                DCD     0                         ; Reserved                
+                DCD     PWM3_IRQHandler_v
+
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                IMPORT  nrf_reloc_vector_table
+                
+                
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =nrf_reloc_vector_table
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemoryManagement_Handler\
+                PROC
+                EXPORT  MemoryManagement_Handler  [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMonitor_Handler\
+                PROC
+                EXPORT  DebugMonitor_Handler      [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT   POWER_CLOCK_IRQHandler [WEAK]
+                EXPORT   RADIO_IRQHandler [WEAK]
+                EXPORT   UARTE0_UART0_IRQHandler_v [WEAK]
+                EXPORT   SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v [WEAK]
+                EXPORT   SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v [WEAK]
+                EXPORT   NFCT_IRQHandler_v [WEAK]
+                EXPORT   GPIOTE_IRQHandler_v [WEAK]
+                EXPORT   SAADC_IRQHandler_v [WEAK]
+                EXPORT   TIMER0_IRQHandler_v [WEAK]
+                EXPORT   TIMER1_IRQHandler_v [WEAK]
+                EXPORT   TIMER2_IRQHandler_v [WEAK]
+                EXPORT   RTC0_IRQHandler [WEAK]
+                EXPORT   TEMP_IRQHandler_v [WEAK]
+                EXPORT   RNG_IRQHandler [WEAK]
+                EXPORT   ECB_IRQHandler [WEAK]
+                EXPORT   CCM_AAR_IRQHandler [WEAK]
+                EXPORT   WDT_IRQHandler_v [WEAK]
+                EXPORT   RTC1_IRQHandler_v [WEAK]
+                EXPORT   QDEC_IRQHandler_v [WEAK]
+                EXPORT   COMP_LPCOMP_IRQHandler_v [WEAK]
+                EXPORT   SWI0_EGU0_IRQHandler_v [WEAK]
+                EXPORT   SWI1_EGU1_IRQHandler_v [WEAK]
+                EXPORT   SWI2_EGU2_IRQHandler_v [WEAK]
+                EXPORT   SWI3_EGU3_IRQHandler_v [WEAK]
+                EXPORT   SWI4_EGU4_IRQHandler [WEAK]
+                EXPORT   SWI5_EGU5_IRQHandler [WEAK]
+                EXPORT   TIMER3_IRQHandler_v [WEAK]
+                EXPORT   TIMER4_IRQHandler_v [WEAK]
+                EXPORT   PWM0_IRQHandler_v [WEAK]
+                EXPORT   PDM_IRQHandler_v [WEAK]
+                EXPORT   MWU_IRQHandler [WEAK]
+                EXPORT   PWM1_IRQHandler_v [WEAK]
+                EXPORT   PWM2_IRQHandler_v [WEAK]
+                EXPORT   SPIM2_SPIS2_SPI2_IRQHandler_v [WEAK]
+                EXPORT   RTC2_IRQHandler_v [WEAK]
+                EXPORT   I2S_IRQHandler_v [WEAK]
+                EXPORT   FPU_IRQHandler_v [WEAK]
+                EXPORT   USBD_IRQHandler_v [WEAK]
+                EXPORT   UARTE1_IRQHandler_v [WEAK]
+                EXPORT   QSPI_IRQHandler_v [WEAK]
+                EXPORT   CRYPTOCELL_IRQHandler_v [WEAK]
+                EXPORT   SPIM3_IRQHandler_v [WEAK]
+                EXPORT   PWM3_IRQHandler_v [WEAK]
+                
+                
+                
+                
+POWER_CLOCK_IRQHandler
+RADIO_IRQHandler
+UARTE0_UART0_IRQHandler_v
+SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v
+SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v
+NFCT_IRQHandler_v
+GPIOTE_IRQHandler_v
+SAADC_IRQHandler_v
+TIMER0_IRQHandler_v
+TIMER1_IRQHandler_v
+TIMER2_IRQHandler_v
+RTC0_IRQHandler
+TEMP_IRQHandler_v
+RNG_IRQHandler
+ECB_IRQHandler
+CCM_AAR_IRQHandler
+WDT_IRQHandler_v
+RTC1_IRQHandler_v
+QDEC_IRQHandler_v
+COMP_LPCOMP_IRQHandler_v
+SWI0_EGU0_IRQHandler_v
+SWI1_EGU1_IRQHandler_v
+SWI2_EGU2_IRQHandler_v
+SWI3_EGU3_IRQHandler_v
+SWI4_EGU4_IRQHandler
+SWI5_EGU5_IRQHandler
+TIMER3_IRQHandler_v
+TIMER4_IRQHandler_v
+PWM0_IRQHandler_v
+PDM_IRQHandler_v
+MWU_IRQHandler
+PWM1_IRQHandler_v
+PWM2_IRQHandler_v
+SPIM2_SPIS2_SPI2_IRQHandler_v
+RTC2_IRQHandler_v
+I2S_IRQHandler_v
+FPU_IRQHandler_v
+USBD_IRQHandler_v
+UARTE1_IRQHandler_v
+QSPI_IRQHandler_v
+CRYPTOCELL_IRQHandler_v
+SPIM3_IRQHandler_v     
+PWM3_IRQHandler_v
+
+                B .
+                ENDP
+                ALIGN
+                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/sys.cpp	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * Setup a fixed single stack/heap memory model, 
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Linker script to configure memory regions. */
+
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x21000, LENGTH = 0xDF000
+  RAM (rwx) :  ORIGIN = 0x20003288, LENGTH = 0x3cd78
+}
+
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with the other linker script that defines memory regions FLASH and RAM.
+ * It references the following symbols that must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines the following symbols that the code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.Vectors))
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        . = ALIGN(4);
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        . = ALIGN(4);
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        . = ALIGN(4);
+        PROVIDE(__start_fs_data = .);
+        KEEP(*(.fs_data))
+        PROVIDE(__stop_fs_data = .);
+        
+        *(.jcr)
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    __edata = .;
+
+    .noinit :
+    {
+      PROVIDE(__start_noinit = .);
+      KEEP(*(.noinit))
+      PROVIDE(__stop_noinit = .);
+    } > RAM
+    
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (NOLOAD):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*);
+
+        /* Expand the heap to reach the stack boundary. */
+        ASSERT(. <= (ORIGIN(RAM) + LENGTH(RAM) - 0x800), "heap region overflowed into stack");
+        . += (ORIGIN(RAM) + LENGTH(RAM) - 0x800) - .;
+    } > RAM
+    PROVIDE(__heap_start = ADDR(.heap));
+    PROVIDE(__heap_size = SIZEOF(.heap));
+    PROVIDE(__mbed_sbrk_start = ADDR(.heap));
+    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
+
+    /* .stack_dummy section does not contain any symbols. It is only
+     * used for the linker script to calculate the size of stack sections
+     * and assign values to stack symbols later. */
+    .stack (NOLOAD):
+    {
+        __StackLimit = .;
+        *(.stack*)
+        . += (ORIGIN(RAM) + LENGTH(RAM) - .);
+    } > RAM
+
+    /* Set the stack top to the end of RAM and move down the stack limit by
+     * the size of the stack_dummy section. */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack);
+    PROVIDE(__stack = __StackTop);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/startup_NRF52832.S	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,283 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+    .syntax unified
+    .arch armv7e-m
+
+    .section .Vectors
+    .align 2
+    .globl __Vectors
+__Vectors:
+    .long   __StackTop                  /* Top of Stack */
+    .long   Reset_Handler
+    .long   NMI_Handler
+    .long   HardFault_Handler
+    .long   MemoryManagement_Handler
+    .long   BusFault_Handler
+    .long   UsageFault_Handler
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   SVC_Handler
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   PendSV_Handler
+    .long   SysTick_Handler
+
+  /* External Interrupts */
+    .long   POWER_CLOCK_IRQHandler
+    .long   RADIO_IRQHandler
+    .long   UARTE0_UART0_IRQHandler_v
+    .long   SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v
+    .long   SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v
+    .long   NFCT_IRQHandler_v
+    .long   GPIOTE_IRQHandler_v
+    .long   SAADC_IRQHandler_v
+    .long   TIMER0_IRQHandler_v
+    .long   TIMER1_IRQHandler_v
+    .long   TIMER2_IRQHandler_v
+    .long   RTC0_IRQHandler
+    .long   TEMP_IRQHandler_v
+    .long   RNG_IRQHandler
+    .long   ECB_IRQHandler
+    .long   CCM_AAR_IRQHandler
+    .long   WDT_IRQHandler_v
+    .long   RTC1_IRQHandler_v
+    .long   QDEC_IRQHandler_v
+    .long   COMP_LPCOMP_IRQHandler_v
+    .long   SWI0_EGU0_IRQHandler_v
+    .long   SWI1_EGU1_IRQHandler_v
+    .long   SWI2_EGU2_IRQHandler_v
+    .long   SWI3_EGU3_IRQHandler_v
+    .long   SWI4_EGU4_IRQHandler
+    .long   SWI5_EGU5_IRQHandler
+    .long   TIMER3_IRQHandler_v
+    .long   TIMER4_IRQHandler_v
+    .long   PWM0_IRQHandler_v
+    .long   PDM_IRQHandler_v
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   MWU_IRQHandler
+    .long   PWM1_IRQHandler_v
+    .long   PWM2_IRQHandler_v
+    .long   SPIM2_SPIS2_SPI2_IRQHandler_v
+    .long   RTC2_IRQHandler_v
+    .long   I2S_IRQHandler_v
+    .long   FPU_IRQHandler_v
+    .long   USBD_IRQHandler_v
+    .long   UARTE1_IRQHandler_v
+    .long   QSPI_IRQHandler_v
+    .long   CRYPTOCELL_IRQHandler_v
+    .long   SPIM3_IRQHandler_v
+    .long   0                           /*Reserved */
+    .long   PWM3_IRQHandler_v
+
+
+    .size    __Vectors, . - __Vectors
+
+/* Reset Handler */
+
+    .text
+    .thumb
+    .thumb_func
+    .align 1
+    .globl    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    .fnstart
+
+
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+    subs    r3, r2
+    ble     .LC0
+
+.LC1:
+    subs    r3, 4
+    ldr    r0, [r1,r3]
+    str    r0, [r2,r3]
+    bgt    .LC1
+.LC0:
+
+    LDR     R0, =SystemInit
+    BLX     R0
+    LDR     R0, =nrf_reloc_vector_table
+    BLX     R0
+    LDR     R0, =_start
+    BX      R0
+
+    .pool
+    .cantunwind
+    .fnend
+    .size   Reset_Handler,.-Reset_Handler
+
+    .section ".text"
+
+
+/* Dummy Exception Handlers (infinite loops which can be modified) */
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+
+    .weak   MemoryManagement_Handler
+    .type   MemoryManagement_Handler, %function
+MemoryManagement_Handler:
+    B       .
+    .size   MemoryManagement_Handler, . - MemoryManagement_Handler
+
+
+    .weak   BusFault_Handler
+    .type   BusFault_Handler, %function
+BusFault_Handler:
+    B       .
+    .size   BusFault_Handler, . - BusFault_Handler
+
+
+    .weak   UsageFault_Handler
+    .type   UsageFault_Handler, %function
+UsageFault_Handler:
+    B       .
+    .size   UsageFault_Handler, . - UsageFault_Handler
+
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ  POWER_CLOCK_IRQHandler                          /* restricted */
+    IRQ  RADIO_IRQHandler                                /* blocked    */
+    IRQ  UARTE0_UART0_IRQHandler_v
+    IRQ  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v
+    IRQ  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v
+    IRQ  NFCT_IRQHandler_v
+    IRQ  GPIOTE_IRQHandler_v
+    IRQ  SAADC_IRQHandler_v
+    IRQ  TIMER0_IRQHandler_v
+    IRQ  TIMER1_IRQHandler_v
+    IRQ  TIMER2_IRQHandler_v
+    IRQ  RTC0_IRQHandler                                 /* blocked    */
+    IRQ  TEMP_IRQHandler_v
+    IRQ  RNG_IRQHandler                                  /* restricted */
+    IRQ  ECB_IRQHandler                                  /* restricted */
+    IRQ  CCM_AAR_IRQHandler                              /* blocked    */
+    IRQ  WDT_IRQHandler_v
+    IRQ  RTC1_IRQHandler_v
+    IRQ  QDEC_IRQHandler_v
+    IRQ  COMP_LPCOMP_IRQHandler_v
+    IRQ  SWI0_EGU0_IRQHandler_v
+    IRQ  SWI1_EGU1_IRQHandler_v                          /* restricted for Radio Notification */
+    IRQ  SWI2_EGU2_IRQHandler_v                          /* blocked for SoftDevice Event */
+    IRQ  SWI3_EGU3_IRQHandler_v
+    IRQ  SWI4_EGU4_IRQHandler                            /* blocked    */
+    IRQ  SWI5_EGU5_IRQHandler                            /* blocked    */
+    IRQ  TIMER3_IRQHandler_v
+    IRQ  TIMER4_IRQHandler_v
+    IRQ  PWM0_IRQHandler_v
+    IRQ  PDM_IRQHandler_v
+    IRQ  MWU_IRQHandler                                  /* restricted */
+    IRQ  PWM1_IRQHandler_v
+    IRQ  PWM2_IRQHandler_v
+    IRQ  SPIM2_SPIS2_SPI2_IRQHandler_v
+    IRQ  RTC2_IRQHandler_v
+    IRQ  I2S_IRQHandler_v
+    IRQ  FPU_IRQHandler_v
+    IRQ  USBD_IRQHandler_v
+    IRQ  UARTE1_IRQHandler_v
+    IRQ  QSPI_IRQHandler_v
+    IRQ  CRYPTOCELL_IRQHandler_v
+    IRQ  SPIM3_IRQHandler_v               
+    IRQ  PWM3_IRQHandler_v
+    
+  .end

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52832.icf	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,46 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x21000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x21000;
+define symbol __ICFEDIT_region_ROM_end__     = 0xfffff;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20003288;
+define symbol __ICFEDIT_region_RAM_end__     = 0x2003ffff;
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__   = 0x800;
+define symbol __ICFEDIT_size_heap__     = 0x3000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __code_start_soft_device__ = 0x0;
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+keep { section .intvec };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block HEAP,
+                        block CSTACK };
+
+/*This is used for mbed applications build inside the Embedded workbench
+Applications build with the python scritps use a hex merge so need to merge it
+inside the linker. The linker can only use binary files so the hex merge is not possible
+through the linker. That is why a binary is used instead of a hex image for the embedded project.
+*/
+if(isdefinedsymbol(SOFT_DEVICE_BIN))
+{
+  place at address mem:__code_start_soft_device__ { section .noinit_softdevice };
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.s	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,417 @@
+;/* Copyright (c) 2012 ARM LIMITED
+;
+;   All rights reserved.
+;   Redistribution and use in source and binary forms, with or without
+;   modification, are permitted provided that the following conditions are met:
+;   - Redistributions of source code must retain the above copyright
+;     notice, this list of conditions and the following disclaimer.
+;   - Redistributions in binary form must reproduce the above copyright
+;     notice, this list of conditions and the following disclaimer in the
+;     documentation and/or other materials provided with the distribution.
+;   - Neither the name of ARM nor the names of its contributors may be used
+;     to endorse or promote products derived from this software without
+;     specific prior written permission.
+;   *
+;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;   POSSIBILITY OF SUCH DAMAGE.
+;   ---------------------------------------------------------------------------*/
+
+
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+
+
+
+        MODULE  ?cstartup
+
+        ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW.
+        ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW.
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        EXTERN  nrf_reloc_vector_table
+        PUBLIC  __vector_table
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemoryManagement_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler
+        DCD     DebugMonitor_Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+        DCD     POWER_CLOCK_IRQHandler
+        DCD     RADIO_IRQHandler
+        DCD     UARTE0_UART0_IRQHandler_v
+        DCD     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v
+        DCD     SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v
+        DCD     NFCT_IRQHandler_v
+        DCD     GPIOTE_IRQHandler_v
+        DCD     SAADC_IRQHandler_v
+        DCD     TIMER0_IRQHandler_v
+        DCD     TIMER1_IRQHandler_v
+        DCD     TIMER2_IRQHandler_v
+        DCD     RTC0_IRQHandler
+        DCD     TEMP_IRQHandler_v
+        DCD     RNG_IRQHandler
+        DCD     ECB_IRQHandler
+        DCD     CCM_AAR_IRQHandler
+        DCD     WDT_IRQHandler_v
+        DCD     RTC1_IRQHandler_v
+        DCD     QDEC_IRQHandler_v
+        DCD     COMP_LPCOMP_IRQHandler_v
+        DCD     SWI0_EGU0_IRQHandler_v
+        DCD     SWI1_EGU1_IRQHandler_v
+        DCD     SWI2_EGU2_IRQHandler_v
+        DCD     SWI3_EGU3_IRQHandler_v
+        DCD     SWI4_EGU4_IRQHandler
+        DCD     SWI5_EGU5_IRQHandler
+        DCD     TIMER3_IRQHandler_v
+        DCD     TIMER4_IRQHandler_v
+        DCD     PWM0_IRQHandler_v
+        DCD     PDM_IRQHandler_v
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     MWU_IRQHandler
+        DCD     PWM1_IRQHandler_v
+        DCD     PWM2_IRQHandler_v
+        DCD     SPIM2_SPIS2_SPI2_IRQHandler_v
+        DCD     RTC2_IRQHandler_v
+        DCD     I2S_IRQHandler_v
+        DCD     FPU_IRQHandler_v
+        DCD     USBD_IRQHandler_v
+        DCD     UARTE1_IRQHandler_v
+        DCD     QSPI_IRQHandler_v
+        DCD     CRYPTOCELL_IRQHandler_v
+        DCD     SPIM3_IRQHandler_v
+        DCD     0                           /*Reserved */
+        DCD     PWM3_IRQHandler_v
+
+__Vectors_End
+__Vectors                           EQU   __vector_table
+__Vectors_Size                      EQU   __Vectors_End - __Vectors
+
+
+; Default handlers.
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =nrf_reloc_vector_table
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        ; Dummy exception handlers
+        
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK MemoryManagement_Handler
+        SECTION .text:CODE:NOROOT(1)
+MemoryManagement_Handler
+        B .
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT(1)
+BusFault_Handler
+        B .
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT(1)
+UsageFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK DebugMonitor_Handler
+        SECTION .text:CODE:NOROOT(1)
+DebugMonitor_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT(1)
+SysTick_Handler
+        B .
+
+
+       ; Dummy interrupt handlers
+
+        PUBWEAK  POWER_CLOCK_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+POWER_CLOCK_IRQHandler
+        B .
+
+        PUBWEAK  RADIO_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+RADIO_IRQHandler
+        B .
+
+        PUBWEAK  UARTE0_UART0_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+UARTE0_UART0_IRQHandler_v
+        B .
+
+        PUBWEAK  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v
+        B .
+
+        PUBWEAK  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v
+        B .
+
+        PUBWEAK  NFCT_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+NFCT_IRQHandler_v
+        B .
+
+        PUBWEAK  GPIOTE_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+GPIOTE_IRQHandler_v
+        B .
+
+        PUBWEAK  SAADC_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+SAADC_IRQHandler_v
+        B .
+
+        PUBWEAK  TIMER0_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+TIMER0_IRQHandler_v
+        B .
+
+        PUBWEAK  TIMER1_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+TIMER1_IRQHandler_v
+        B .
+
+        PUBWEAK  TIMER2_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+TIMER2_IRQHandler_v
+        B .
+
+        PUBWEAK  RTC0_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+RTC0_IRQHandler
+        B .
+
+        PUBWEAK  TEMP_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+TEMP_IRQHandler_v
+        B .
+
+        PUBWEAK  RNG_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+RNG_IRQHandler
+        B .
+
+        PUBWEAK  ECB_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+ECB_IRQHandler
+        B .
+
+        PUBWEAK  CCM_AAR_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+CCM_AAR_IRQHandler
+        B .
+
+        PUBWEAK  WDT_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+WDT_IRQHandler_v
+        B .
+
+        PUBWEAK  RTC1_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+RTC1_IRQHandler_v
+        B .
+
+        PUBWEAK  QDEC_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+QDEC_IRQHandler_v
+        B .
+
+        PUBWEAK  COMP_LPCOMP_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+COMP_LPCOMP_IRQHandler_v
+        B .
+
+        PUBWEAK  SWI0_EGU0_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+SWI0_EGU0_IRQHandler_v
+        B .
+
+        PUBWEAK  SWI1_EGU1_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+SWI1_EGU1_IRQHandler_v
+        B .
+
+        PUBWEAK  SWI2_EGU2_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+SWI2_EGU2_IRQHandler_v
+        B .
+
+        PUBWEAK  SWI3_EGU3_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+SWI3_EGU3_IRQHandler_v
+        B .
+
+        PUBWEAK  SWI4_EGU4_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+SWI4_EGU4_IRQHandler
+        B .
+
+        PUBWEAK  SWI5_EGU5_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+SWI5_EGU5_IRQHandler
+        B .
+
+        PUBWEAK  TIMER3_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+TIMER3_IRQHandler_v
+        B .
+
+        PUBWEAK  TIMER4_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+TIMER4_IRQHandler_v
+        B .
+
+        PUBWEAK  PWM0_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+PWM0_IRQHandler_v
+        B .
+
+        PUBWEAK  PDM_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+PDM_IRQHandler_v
+        B .
+
+        PUBWEAK  MWU_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+MWU_IRQHandler
+        B .
+
+        PUBWEAK  PWM1_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+PWM1_IRQHandler_v
+        B .
+
+        PUBWEAK  PWM2_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+PWM2_IRQHandler_v
+        B .
+
+        PUBWEAK  SPIM2_SPIS2_SPI2_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+SPIM2_SPIS2_SPI2_IRQHandler_v
+        B .
+
+        PUBWEAK  RTC2_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+RTC2_IRQHandler_v
+        B .
+
+        PUBWEAK  I2S_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+I2S_IRQHandler_v
+        B .
+
+        PUBWEAK  FPU_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+FPU_IRQHandler_v
+        B .
+
+        PUBWEAK  USBD_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+USBD_IRQHandler_v
+        B .
+        
+        PUBWEAK  UARTE1_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+UARTE1_IRQHandler_v
+        B .
+
+        PUBWEAK  QSPI_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+QSPI_IRQHandler_v
+        B .
+
+        PUBWEAK  CRYPTOCELL_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+CRYPTOCELL_IRQHandler_v
+        B .
+
+        PUBWEAK  SPIM3_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+SPIM3_IRQHandler_v
+        B .
+
+        PUBWEAK  PWM3_IRQHandler_v
+        SECTION .text:CODE:NOROOT(1)
+PWM3_IRQHandler_v
+        B .
+        
+
+        END
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/cmsis.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,24 @@
+/*
+ * PackageLicenseDeclared: Apache-2.0
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "nrf.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/cmsis_nvic.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,43 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2016 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+extern uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS];
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    nrf_dispatch_vector[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+    return nrf_dispatch_vector[IRQn + NVIC_USER_IRQ_OFFSET];
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/cmsis_nvic.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,53 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2016 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS      (16 + 46)   // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET  16
+
+#include "nrf.h"
+#include "cmsis.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/system_nrf52840.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,209 @@
+/* Copyright (c) 2012 ARM LIMITED
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of ARM nor the names of its contributors may be used to
+ *     endorse or promote products derived from this software without specific
+ *     prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf.h"
+#include "system_nrf52840.h"
+
+/*lint ++flb "Enter library region" */
+
+#define __SYSTEM_CLOCK_64M      (64000000UL)
+
+static bool errata_36(void);
+static bool errata_98(void);
+static bool errata_103(void);
+static bool errata_115(void);
+static bool errata_120(void);
+
+
+#if defined ( __CC_ARM )
+    uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
+#elif defined ( __ICCARM__ )
+    __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
+#elif defined ( __GNUC__ )
+    uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
+#endif
+
+void SystemCoreClockUpdate(void)
+{
+    SystemCoreClock = __SYSTEM_CLOCK_64M;
+}
+
+void SystemInit(void)
+{
+    /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_36()){
+        NRF_CLOCK->EVENTS_DONE = 0;
+        NRF_CLOCK->EVENTS_CTTO = 0;
+        NRF_CLOCK->CTIV = 0;
+    }
+    
+    /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_98()){
+        *(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
+    }
+    
+    /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_103()){
+        NRF_CCM->MAXPACKETSIZE = 0xFBul;
+    }
+    
+    /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_115()){
+        *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
+    }
+    
+    /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_120()){
+        *(volatile uint32_t *)0x40029640ul = 0x200ul;
+    }
+    
+    /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
+     * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
+     * operations are not used in your code. */
+    #if (__FPU_USED == 1)
+        SCB->CPACR |= (3UL << 20) | (3UL << 22);
+        __DSB();
+        __ISB();
+    #endif
+
+    /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
+       two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
+       normal GPIOs. */
+    #if defined (CONFIG_NFCT_PINS_AS_GPIOS)
+        if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
+            NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NVIC_SystemReset();
+        }
+    #endif
+
+    /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
+      defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
+      reserved for PinReset and not available as normal GPIO. */
+    #if defined (CONFIG_GPIO_AS_PINRESET)
+        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+            ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
+            NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_UICR->PSELRESET[0] = 18;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_UICR->PSELRESET[1] = 18;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NVIC_SystemReset();
+        }
+    #endif
+
+    /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
+       Specification to see which one). */
+    #if defined (ENABLE_SWO)
+        CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+        NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
+        NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+    #endif
+
+    /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
+       Specification to see which ones). */
+    #if defined (ENABLE_TRACE)
+        CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+        NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
+        NRF_P0->PIN_CNF[7]  = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+        NRF_P1->PIN_CNF[0]  = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+        NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+        NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+        NRF_P1->PIN_CNF[9]  = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+    #endif
+
+    SystemCoreClockUpdate();
+}
+
+
+static bool errata_36(void)
+{
+    if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
+        return true;
+    }
+    
+    return false;
+}
+
+
+static bool errata_98(void)
+{
+    if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
+        return true;
+    }
+    
+    return false;
+}
+
+
+static bool errata_103(void)
+{
+    if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
+        return true;
+    }
+    
+    return false;
+}
+
+
+static bool errata_115(void)
+{
+    if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
+        return true;
+    }
+    
+    return false;
+}
+
+
+static bool errata_120(void)
+{
+    if ((*(uint32_t *)0x10000130ul == 0x8ul) && (*(uint32_t *)0x10000134ul == 0x0ul)){
+        return true;
+    }
+    
+    return false;
+}
+
+/*lint --flb "Leave library region" */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/system_nrf52840.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,69 @@
+/* Copyright (c) 2012 ARM LIMITED
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of ARM nor the names of its contributors may be used to
+ *     endorse or promote products derived from this software without specific
+ *     prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+ 
+#ifndef SYSTEM_NRF52840_H
+#define SYSTEM_NRF52840_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+extern uint32_t SystemCoreClock;    /*!< System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock 
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_NRF52840_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/sdk_config.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,3659 @@
+
+
+#ifndef SDK_CONFIG_H
+#define SDK_CONFIG_H
+// <<< Use Configuration Wizard in Context Menu >>>\n
+#ifdef USE_APP_CONFIG
+#include "app_config.h"
+#endif
+// <h> Application 
+
+//==========================================================
+// <o> NRF_BLE_CENTRAL_LINK_COUNT - Number of central links 
+#ifndef NRF_BLE_CENTRAL_LINK_COUNT
+#define NRF_BLE_CENTRAL_LINK_COUNT 0
+#endif
+
+// <o> NRF_BLE_CENTRAL_LINK_COUNT - Number of central links 
+#ifndef NRF_BLE_CENTRAL_LINK_COUNT
+#define NRF_BLE_CENTRAL_LINK_COUNT 0
+#endif
+
+// <o> NRF_BLE_PERIPHERAL_LINK_COUNT - Number of peripheral links 
+#ifndef NRF_BLE_PERIPHERAL_LINK_COUNT
+#define NRF_BLE_PERIPHERAL_LINK_COUNT 1
+#endif
+
+// <o> NRF_BLE_PERIPHERAL_LINK_COUNT - Number of peripheral links 
+#ifndef NRF_BLE_PERIPHERAL_LINK_COUNT
+#define NRF_BLE_PERIPHERAL_LINK_COUNT 1
+#endif
+
+// </h> 
+//==========================================================
+
+// <h> nRF_BLE 
+
+//==========================================================
+// <q> BLE_ADVERTISING_ENABLED  - ble_advertising - Advertising module
+ 
+
+#ifndef BLE_ADVERTISING_ENABLED
+#define BLE_ADVERTISING_ENABLED 1
+#endif
+
+// <q> BLE_DTM_ENABLED  - ble_dtm - Module for testing RF/PHY using DTM commands
+ 
+
+#ifndef BLE_DTM_ENABLED
+#define BLE_DTM_ENABLED 0
+#endif
+
+// <q> BLE_RACP_ENABLED  - ble_racp - Record Access Control Point library
+ 
+
+#ifndef BLE_RACP_ENABLED
+#define BLE_RACP_ENABLED 0
+#endif
+
+// <e> NRF_BLE_GATT_ENABLED - nrf_ble_gatt - GATT module
+//==========================================================
+#ifndef NRF_BLE_GATT_ENABLED
+#define NRF_BLE_GATT_ENABLED 1
+#endif
+#if  NRF_BLE_GATT_ENABLED
+// <o> NRF_BLE_GATT_MAX_MTU_SIZE - Static maximum MTU size that is passed to the @ref sd_ble_enable function. 
+#ifndef NRF_BLE_GATT_MAX_MTU_SIZE
+#define NRF_BLE_GATT_MAX_MTU_SIZE 158
+#endif
+
+#endif //NRF_BLE_GATT_ENABLED
+// </e>
+
+// <q> NRF_BLE_QWR_ENABLED  - nrf_ble_qwr - Queued writes support module (prepare/execute write)
+ 
+
+#ifndef NRF_BLE_QWR_ENABLED
+#define NRF_BLE_QWR_ENABLED 0
+#endif
+
+// <q> PEER_MANAGER_ENABLED  - peer_manager - Peer Manager
+ 
+
+#ifndef PEER_MANAGER_ENABLED
+#define PEER_MANAGER_ENABLED 1
+#endif
+
+// </h> 
+//==========================================================
+
+// <h> nRF_Drivers 
+
+//==========================================================
+// <e> APP_USBD_ENABLED - app_usbd - USB Device library
+//==========================================================
+#ifndef APP_USBD_ENABLED
+#define APP_USBD_ENABLED 0
+#endif
+#if  APP_USBD_ENABLED
+// <s> APP_USBD_VID - Vendor ID
+
+// <i> Vendor ID ordered from USB IF: http://www.usb.org/developers/vendor/
+#ifndef APP_USBD_VID
+#define APP_USBD_VID 0x1915
+#endif
+
+// <s> APP_USBD_PID - Product ID
+
+// <i> Selected Product ID
+#ifndef APP_USBD_PID
+#define APP_USBD_PID 0x520C
+#endif
+
+// <o> APP_USBD_DEVICE_VER_MAJOR - Device version, major part  <0-99> 
+
+
+// <i> Device version, will be converted automatically to BCD notation. Use just decimal values.
+
+#ifndef APP_USBD_DEVICE_VER_MAJOR
+#define APP_USBD_DEVICE_VER_MAJOR 1
+#endif
+
+// <o> APP_USBD_DEVICE_VER_MINOR - Device version, minor part  <0-99> 
+
+
+// <i> Device version, will be converted automatically to BCD notation. Use just decimal values.
+
+#ifndef APP_USBD_DEVICE_VER_MINOR
+#define APP_USBD_DEVICE_VER_MINOR 0
+#endif
+
+#endif //APP_USBD_ENABLED
+// </e>
+
+// <e> CLOCK_ENABLED - nrf_drv_clock - CLOCK peripheral driver
+//==========================================================
+#ifndef CLOCK_ENABLED
+#define CLOCK_ENABLED 1
+#endif
+#if  CLOCK_ENABLED
+// <o> CLOCK_CONFIG_XTAL_FREQ  - HF XTAL Frequency
+ 
+// <0=> Default (64 MHz) 
+
+#ifndef CLOCK_CONFIG_XTAL_FREQ
+#define CLOCK_CONFIG_XTAL_FREQ 0
+#endif
+
+// <o> CLOCK_CONFIG_LF_SRC  - LF Clock Source
+ 
+// <0=> RC 
+// <1=> XTAL 
+// <2=> Synth 
+
+#ifndef CLOCK_CONFIG_LF_SRC
+#define CLOCK_CONFIG_LF_SRC 1
+#endif
+
+// <o> CLOCK_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef CLOCK_CONFIG_IRQ_PRIORITY
+#define CLOCK_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <e> CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef CLOCK_CONFIG_LOG_ENABLED
+#define CLOCK_CONFIG_LOG_ENABLED 0
+#endif
+#if  CLOCK_CONFIG_LOG_ENABLED
+// <o> CLOCK_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef CLOCK_CONFIG_LOG_LEVEL
+#define CLOCK_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> CLOCK_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef CLOCK_CONFIG_INFO_COLOR
+#define CLOCK_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> CLOCK_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef CLOCK_CONFIG_DEBUG_COLOR
+#define CLOCK_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //CLOCK_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //CLOCK_ENABLED
+// </e>
+
+// <e> COMP_ENABLED - nrf_drv_comp - COMP peripheral driver
+//==========================================================
+#ifndef COMP_ENABLED
+#define COMP_ENABLED 0
+#endif
+#if  COMP_ENABLED
+// <o> COMP_CONFIG_REF  - Reference voltage
+ 
+// <0=> Internal 1.2V 
+// <1=> Internal 1.8V 
+// <2=> Internal 2.4V 
+// <4=> VDD 
+// <7=> ARef 
+
+#ifndef COMP_CONFIG_REF
+#define COMP_CONFIG_REF 1
+#endif
+
+// <o> COMP_CONFIG_MAIN_MODE  - Main mode
+ 
+// <0=> Single ended 
+// <1=> Differential 
+
+#ifndef COMP_CONFIG_MAIN_MODE
+#define COMP_CONFIG_MAIN_MODE 0
+#endif
+
+// <o> COMP_CONFIG_SPEED_MODE  - Speed mode
+ 
+// <0=> Low power 
+// <1=> Normal 
+// <2=> High speed 
+
+#ifndef COMP_CONFIG_SPEED_MODE
+#define COMP_CONFIG_SPEED_MODE 2
+#endif
+
+// <o> COMP_CONFIG_HYST  - Hystheresis
+ 
+// <0=> No 
+// <1=> 50mV 
+
+#ifndef COMP_CONFIG_HYST
+#define COMP_CONFIG_HYST 0
+#endif
+
+// <o> COMP_CONFIG_ISOURCE  - Current Source
+ 
+// <0=> Off 
+// <1=> 2.5 uA 
+// <2=> 5 uA 
+// <3=> 10 uA 
+
+#ifndef COMP_CONFIG_ISOURCE
+#define COMP_CONFIG_ISOURCE 0
+#endif
+
+// <o> COMP_CONFIG_INPUT  - Analog input
+ 
+// <0=> 0 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef COMP_CONFIG_INPUT
+#define COMP_CONFIG_INPUT 0
+#endif
+
+// <o> COMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef COMP_CONFIG_IRQ_PRIORITY
+#define COMP_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <e> COMP_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef COMP_CONFIG_LOG_ENABLED
+#define COMP_CONFIG_LOG_ENABLED 0
+#endif
+#if  COMP_CONFIG_LOG_ENABLED
+// <o> COMP_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef COMP_CONFIG_LOG_LEVEL
+#define COMP_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> COMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef COMP_CONFIG_INFO_COLOR
+#define COMP_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> COMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef COMP_CONFIG_DEBUG_COLOR
+#define COMP_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //COMP_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //COMP_ENABLED
+// </e>
+
+// <e> EGU_ENABLED - nrf_drv_swi - SWI(EGU) peripheral driver
+//==========================================================
+#ifndef EGU_ENABLED
+#define EGU_ENABLED 1
+#endif
+#if  EGU_ENABLED
+// <e> SWI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef SWI_CONFIG_LOG_ENABLED
+#define SWI_CONFIG_LOG_ENABLED 0
+#endif
+#if  SWI_CONFIG_LOG_ENABLED
+// <o> SWI_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef SWI_CONFIG_LOG_LEVEL
+#define SWI_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> SWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef SWI_CONFIG_INFO_COLOR
+#define SWI_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> SWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef SWI_CONFIG_DEBUG_COLOR
+#define SWI_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //SWI_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //EGU_ENABLED
+// </e>
+
+// <e> GPIOTE_ENABLED - nrf_drv_gpiote - GPIOTE peripheral driver
+//==========================================================
+#ifndef GPIOTE_ENABLED
+#define GPIOTE_ENABLED 1
+#endif
+#if  GPIOTE_ENABLED
+// <o> GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins 
+#ifndef GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
+#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 4
+#endif
+
+// <o> GPIOTE_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef GPIOTE_CONFIG_IRQ_PRIORITY
+#define GPIOTE_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <e> GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef GPIOTE_CONFIG_LOG_ENABLED
+#define GPIOTE_CONFIG_LOG_ENABLED 0
+#endif
+#if  GPIOTE_CONFIG_LOG_ENABLED
+// <o> GPIOTE_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef GPIOTE_CONFIG_LOG_LEVEL
+#define GPIOTE_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> GPIOTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef GPIOTE_CONFIG_INFO_COLOR
+#define GPIOTE_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> GPIOTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef GPIOTE_CONFIG_DEBUG_COLOR
+#define GPIOTE_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //GPIOTE_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //GPIOTE_ENABLED
+// </e>
+
+// <e> I2S_ENABLED - nrf_drv_i2s - I2S peripheral driver
+//==========================================================
+#ifndef I2S_ENABLED
+#define I2S_ENABLED 0
+#endif
+#if  I2S_ENABLED
+// <o> I2S_CONFIG_SCK_PIN - SCK pin  <0-31> 
+
+
+#ifndef I2S_CONFIG_SCK_PIN
+#define I2S_CONFIG_SCK_PIN 31
+#endif
+
+// <o> I2S_CONFIG_LRCK_PIN - LRCK pin  <1-31> 
+
+
+#ifndef I2S_CONFIG_LRCK_PIN
+#define I2S_CONFIG_LRCK_PIN 30
+#endif
+
+// <o> I2S_CONFIG_MCK_PIN - MCK pin 
+#ifndef I2S_CONFIG_MCK_PIN
+#define I2S_CONFIG_MCK_PIN 255
+#endif
+
+// <o> I2S_CONFIG_SDOUT_PIN - SDOUT pin  <0-31> 
+
+
+#ifndef I2S_CONFIG_SDOUT_PIN
+#define I2S_CONFIG_SDOUT_PIN 29
+#endif
+
+// <o> I2S_CONFIG_SDIN_PIN - SDIN pin  <0-31> 
+
+
+#ifndef I2S_CONFIG_SDIN_PIN
+#define I2S_CONFIG_SDIN_PIN 28
+#endif
+
+// <o> I2S_CONFIG_MASTER  - Mode
+ 
+// <0=> Master 
+// <1=> Slave 
+
+#ifndef I2S_CONFIG_MASTER
+#define I2S_CONFIG_MASTER 0
+#endif
+
+// <o> I2S_CONFIG_FORMAT  - Format
+ 
+// <0=> I2S 
+// <1=> Aligned 
+
+#ifndef I2S_CONFIG_FORMAT
+#define I2S_CONFIG_FORMAT 0
+#endif
+
+// <o> I2S_CONFIG_ALIGN  - Alignment
+ 
+// <0=> Left 
+// <1=> Right 
+
+#ifndef I2S_CONFIG_ALIGN
+#define I2S_CONFIG_ALIGN 0
+#endif
+
+// <o> I2S_CONFIG_SWIDTH  - Sample width (bits)
+ 
+// <0=> 8 
+// <1=> 16 
+// <2=> 24 
+
+#ifndef I2S_CONFIG_SWIDTH
+#define I2S_CONFIG_SWIDTH 1
+#endif
+
+// <o> I2S_CONFIG_CHANNELS  - Channels
+ 
+// <0=> Stereo 
+// <1=> Left 
+// <2=> Right 
+
+#ifndef I2S_CONFIG_CHANNELS
+#define I2S_CONFIG_CHANNELS 1
+#endif
+
+// <o> I2S_CONFIG_MCK_SETUP  - MCK behavior
+ 
+// <0=> Disabled 
+// <2147483648=> 32MHz/2 
+// <1342177280=> 32MHz/3 
+// <1073741824=> 32MHz/4 
+// <805306368=> 32MHz/5 
+// <671088640=> 32MHz/6 
+// <536870912=> 32MHz/8 
+// <402653184=> 32MHz/10 
+// <369098752=> 32MHz/11 
+// <285212672=> 32MHz/15 
+// <268435456=> 32MHz/16 
+// <201326592=> 32MHz/21 
+// <184549376=> 32MHz/23 
+// <142606336=> 32MHz/30 
+// <138412032=> 32MHz/31 
+// <134217728=> 32MHz/32 
+// <100663296=> 32MHz/42 
+// <68157440=> 32MHz/63 
+// <34340864=> 32MHz/125 
+
+#ifndef I2S_CONFIG_MCK_SETUP
+#define I2S_CONFIG_MCK_SETUP 536870912
+#endif
+
+// <o> I2S_CONFIG_RATIO  - MCK/LRCK ratio
+ 
+// <0=> 32x 
+// <1=> 48x 
+// <2=> 64x 
+// <3=> 96x 
+// <4=> 128x 
+// <5=> 192x 
+// <6=> 256x 
+// <7=> 384x 
+// <8=> 512x 
+
+#ifndef I2S_CONFIG_RATIO
+#define I2S_CONFIG_RATIO 2000
+#endif
+
+// <o> I2S_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef I2S_CONFIG_IRQ_PRIORITY
+#define I2S_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <e> I2S_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef I2S_CONFIG_LOG_ENABLED
+#define I2S_CONFIG_LOG_ENABLED 0
+#endif
+#if  I2S_CONFIG_LOG_ENABLED
+// <o> I2S_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef I2S_CONFIG_LOG_LEVEL
+#define I2S_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> I2S_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef I2S_CONFIG_INFO_COLOR
+#define I2S_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> I2S_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef I2S_CONFIG_DEBUG_COLOR
+#define I2S_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //I2S_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //I2S_ENABLED
+// </e>
+
+// <e> LPCOMP_ENABLED - nrf_drv_lpcomp - LPCOMP peripheral driver
+//==========================================================
+#ifndef LPCOMP_ENABLED
+#define LPCOMP_ENABLED 0
+#endif
+#if  LPCOMP_ENABLED
+// <o> LPCOMP_CONFIG_REFERENCE  - Reference voltage
+ 
+// <0=> Supply 1/8 
+// <1=> Supply 2/8 
+// <2=> Supply 3/8 
+// <3=> Supply 4/8 
+// <4=> Supply 5/8 
+// <5=> Supply 6/8 
+// <6=> Supply 7/8 
+// <8=> Supply 1/16 (nRF52) 
+// <9=> Supply 3/16 (nRF52) 
+// <10=> Supply 5/16 (nRF52) 
+// <11=> Supply 7/16 (nRF52) 
+// <12=> Supply 9/16 (nRF52) 
+// <13=> Supply 11/16 (nRF52) 
+// <14=> Supply 13/16 (nRF52) 
+// <15=> Supply 15/16 (nRF52) 
+// <7=> External Ref 0 
+// <65543=> External Ref 1 
+
+#ifndef LPCOMP_CONFIG_REFERENCE
+#define LPCOMP_CONFIG_REFERENCE 3
+#endif
+
+// <o> LPCOMP_CONFIG_DETECTION  - Detection
+ 
+// <0=> Crossing 
+// <1=> Up 
+// <2=> Down 
+
+#ifndef LPCOMP_CONFIG_DETECTION
+#define LPCOMP_CONFIG_DETECTION 2
+#endif
+
+// <o> LPCOMP_CONFIG_INPUT  - Analog input
+ 
+// <0=> 0 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef LPCOMP_CONFIG_INPUT
+#define LPCOMP_CONFIG_INPUT 0
+#endif
+
+// <q> LPCOMP_CONFIG_HYST  - Hysteresis
+ 
+
+#ifndef LPCOMP_CONFIG_HYST
+#define LPCOMP_CONFIG_HYST 0
+#endif
+
+// <o> LPCOMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef LPCOMP_CONFIG_IRQ_PRIORITY
+#define LPCOMP_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <e> LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef LPCOMP_CONFIG_LOG_ENABLED
+#define LPCOMP_CONFIG_LOG_ENABLED 0
+#endif
+#if  LPCOMP_CONFIG_LOG_ENABLED
+// <o> LPCOMP_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef LPCOMP_CONFIG_LOG_LEVEL
+#define LPCOMP_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> LPCOMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef LPCOMP_CONFIG_INFO_COLOR
+#define LPCOMP_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> LPCOMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef LPCOMP_CONFIG_DEBUG_COLOR
+#define LPCOMP_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //LPCOMP_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //LPCOMP_ENABLED
+// </e>
+
+// <e> PDM_ENABLED - nrf_drv_pdm - PDM peripheral driver
+//==========================================================
+#ifndef PDM_ENABLED
+#define PDM_ENABLED 0
+#endif
+#if  PDM_ENABLED
+// <o> PDM_CONFIG_MODE  - Mode
+ 
+// <0=> Stereo 
+// <1=> Mono 
+
+#ifndef PDM_CONFIG_MODE
+#define PDM_CONFIG_MODE 1
+#endif
+
+// <o> PDM_CONFIG_EDGE  - Edge
+ 
+// <0=> Left falling 
+// <1=> Left rising 
+
+#ifndef PDM_CONFIG_EDGE
+#define PDM_CONFIG_EDGE 0
+#endif
+
+// <o> PDM_CONFIG_CLOCK_FREQ  - Clock frequency
+ 
+// <134217728=> 1000k 
+// <138412032=> 1032k (default) 
+// <142606336=> 1067k 
+
+#ifndef PDM_CONFIG_CLOCK_FREQ
+#define PDM_CONFIG_CLOCK_FREQ 138412032
+#endif
+
+// <o> PDM_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef PDM_CONFIG_IRQ_PRIORITY
+#define PDM_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <e> PDM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef PDM_CONFIG_LOG_ENABLED
+#define PDM_CONFIG_LOG_ENABLED 0
+#endif
+#if  PDM_CONFIG_LOG_ENABLED
+// <o> PDM_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef PDM_CONFIG_LOG_LEVEL
+#define PDM_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> PDM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef PDM_CONFIG_INFO_COLOR
+#define PDM_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> PDM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef PDM_CONFIG_DEBUG_COLOR
+#define PDM_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //PDM_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //PDM_ENABLED
+// </e>
+
+// <e> PERIPHERAL_RESOURCE_SHARING_ENABLED - nrf_drv_common - Peripheral drivers common module
+//==========================================================
+#ifndef PERIPHERAL_RESOURCE_SHARING_ENABLED
+#define PERIPHERAL_RESOURCE_SHARING_ENABLED 1
+#endif
+#if  PERIPHERAL_RESOURCE_SHARING_ENABLED
+// <e> COMMON_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef COMMON_CONFIG_LOG_ENABLED
+#define COMMON_CONFIG_LOG_ENABLED 0
+#endif
+#if  COMMON_CONFIG_LOG_ENABLED
+// <o> COMMON_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef COMMON_CONFIG_LOG_LEVEL
+#define COMMON_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> COMMON_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef COMMON_CONFIG_INFO_COLOR
+#define COMMON_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> COMMON_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef COMMON_CONFIG_DEBUG_COLOR
+#define COMMON_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //COMMON_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //PERIPHERAL_RESOURCE_SHARING_ENABLED
+// </e>
+
+// <e> POWER_ENABLED - nrf_drv_power - POWER peripheral driver
+//==========================================================
+#ifndef POWER_ENABLED
+#define POWER_ENABLED 1
+#endif
+#if  POWER_ENABLED
+// <o> POWER_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef POWER_CONFIG_IRQ_PRIORITY
+#define POWER_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <q> POWER_CONFIG_DEFAULT_DCDCEN  - The default configuration of main DCDC regulator
+ 
+
+// <i> This settings means only that components for DCDC regulator are installed and it can be enabled.
+
+#ifndef POWER_CONFIG_DEFAULT_DCDCEN
+#define POWER_CONFIG_DEFAULT_DCDCEN 0
+#endif
+
+// <q> POWER_CONFIG_DEFAULT_DCDCENHV  - The default configuration of High Voltage DCDC regulator
+ 
+
+// <i> This settings means only that components for DCDC regulator are installed and it can be enabled.
+
+#ifndef POWER_CONFIG_DEFAULT_DCDCENHV
+#define POWER_CONFIG_DEFAULT_DCDCENHV 0
+#endif
+
+#endif //POWER_ENABLED
+// </e>
+
+// <e> PPI_ENABLED - nrf_drv_ppi - PPI peripheral driver
+//==========================================================
+#ifndef PPI_ENABLED
+#define PPI_ENABLED 1
+#endif
+#if  PPI_ENABLED
+// <e> PPI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef PPI_CONFIG_LOG_ENABLED
+#define PPI_CONFIG_LOG_ENABLED 0
+#endif
+#if  PPI_CONFIG_LOG_ENABLED
+// <o> PPI_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef PPI_CONFIG_LOG_LEVEL
+#define PPI_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> PPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef PPI_CONFIG_INFO_COLOR
+#define PPI_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> PPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef PPI_CONFIG_DEBUG_COLOR
+#define PPI_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //PPI_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //PPI_ENABLED
+// </e>
+
+// <e> PWM_ENABLED - nrf_drv_pwm - PWM peripheral driver
+//==========================================================
+#ifndef PWM_ENABLED
+#define PWM_ENABLED 1
+#endif
+#if  PWM_ENABLED
+// <o> PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin  <0-31> 
+
+
+#ifndef PWM_DEFAULT_CONFIG_OUT0_PIN
+#define PWM_DEFAULT_CONFIG_OUT0_PIN 31
+#endif
+
+// <o> PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin  <0-31> 
+
+
+#ifndef PWM_DEFAULT_CONFIG_OUT1_PIN
+#define PWM_DEFAULT_CONFIG_OUT1_PIN 31
+#endif
+
+// <o> PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin  <0-31> 
+
+
+#ifndef PWM_DEFAULT_CONFIG_OUT2_PIN
+#define PWM_DEFAULT_CONFIG_OUT2_PIN 31
+#endif
+
+// <o> PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin  <0-31> 
+
+
+#ifndef PWM_DEFAULT_CONFIG_OUT3_PIN
+#define PWM_DEFAULT_CONFIG_OUT3_PIN 31
+#endif
+
+// <o> PWM_DEFAULT_CONFIG_BASE_CLOCK  - Base clock
+ 
+// <0=> 16 MHz 
+// <1=> 8 MHz 
+// <2=> 4 MHz 
+// <3=> 2 MHz 
+// <4=> 1 MHz 
+// <5=> 500 kHz 
+// <6=> 250 kHz 
+// <7=> 125 MHz 
+
+#ifndef PWM_DEFAULT_CONFIG_BASE_CLOCK
+#define PWM_DEFAULT_CONFIG_BASE_CLOCK 4
+#endif
+
+// <o> PWM_DEFAULT_CONFIG_COUNT_MODE  - Count mode
+ 
+// <0=> Up 
+// <1=> Up and Down 
+
+#ifndef PWM_DEFAULT_CONFIG_COUNT_MODE
+#define PWM_DEFAULT_CONFIG_COUNT_MODE 0
+#endif
+
+// <o> PWM_DEFAULT_CONFIG_TOP_VALUE - Top value 
+#ifndef PWM_DEFAULT_CONFIG_TOP_VALUE
+#define PWM_DEFAULT_CONFIG_TOP_VALUE 1000
+#endif
+
+// <o> PWM_DEFAULT_CONFIG_LOAD_MODE  - Load mode
+ 
+// <0=> Common 
+// <1=> Grouped 
+// <2=> Individual 
+// <3=> Waveform 
+
+#ifndef PWM_DEFAULT_CONFIG_LOAD_MODE
+#define PWM_DEFAULT_CONFIG_LOAD_MODE 0
+#endif
+
+// <o> PWM_DEFAULT_CONFIG_STEP_MODE  - Step mode
+ 
+// <0=> Auto 
+// <1=> Triggered 
+
+#ifndef PWM_DEFAULT_CONFIG_STEP_MODE
+#define PWM_DEFAULT_CONFIG_STEP_MODE 0
+#endif
+
+// <o> PWM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <q> PWM0_ENABLED  - Enable PWM0 instance
+ 
+
+#ifndef PWM0_ENABLED
+#define PWM0_ENABLED 1
+#endif
+
+// <q> PWM1_ENABLED  - Enable PWM1 instance
+ 
+
+#ifndef PWM1_ENABLED
+#define PWM1_ENABLED 1
+#endif
+
+// <q> PWM2_ENABLED  - Enable PWM2 instance
+ 
+
+#ifndef PWM2_ENABLED
+#define PWM2_ENABLED 1
+#endif
+
+// <q> PWM3_ENABLED  - Enable PWM3 instance
+ 
+
+#ifndef PWM3_ENABLED
+#define PWM3_ENABLED 1
+#endif
+
+// <e> PWM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef PWM_CONFIG_LOG_ENABLED
+#define PWM_CONFIG_LOG_ENABLED 0
+#endif
+#if  PWM_CONFIG_LOG_ENABLED
+// <o> PWM_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef PWM_CONFIG_LOG_LEVEL
+#define PWM_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> PWM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef PWM_CONFIG_INFO_COLOR
+#define PWM_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> PWM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef PWM_CONFIG_DEBUG_COLOR
+#define PWM_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //PWM_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //PWM_ENABLED
+// </e>
+
+// <e> QDEC_ENABLED - nrf_drv_qdec - QDEC peripheral driver
+//==========================================================
+#ifndef QDEC_ENABLED
+#define QDEC_ENABLED 0
+#endif
+#if  QDEC_ENABLED
+// <o> QDEC_CONFIG_REPORTPER  - Report period
+ 
+// <0=> 10 Samples 
+// <1=> 40 Samples 
+// <2=> 80 Samples 
+// <3=> 120 Samples 
+// <4=> 160 Samples 
+// <5=> 200 Samples 
+// <6=> 240 Samples 
+// <7=> 280 Samples 
+
+#ifndef QDEC_CONFIG_REPORTPER
+#define QDEC_CONFIG_REPORTPER 0
+#endif
+
+// <o> QDEC_CONFIG_SAMPLEPER  - Sample period
+ 
+// <0=> 128 us 
+// <1=> 256 us 
+// <2=> 512 us 
+// <3=> 1024 us 
+// <4=> 2048 us 
+// <5=> 4096 us 
+// <6=> 8192 us 
+// <7=> 16384 us 
+
+#ifndef QDEC_CONFIG_SAMPLEPER
+#define QDEC_CONFIG_SAMPLEPER 7
+#endif
+
+// <o> QDEC_CONFIG_PIO_A - A pin  <0-31> 
+
+
+#ifndef QDEC_CONFIG_PIO_A
+#define QDEC_CONFIG_PIO_A 31
+#endif
+
+// <o> QDEC_CONFIG_PIO_B - B pin  <0-31> 
+
+
+#ifndef QDEC_CONFIG_PIO_B
+#define QDEC_CONFIG_PIO_B 31
+#endif
+
+// <o> QDEC_CONFIG_PIO_LED - LED pin  <0-31> 
+
+
+#ifndef QDEC_CONFIG_PIO_LED
+#define QDEC_CONFIG_PIO_LED 31
+#endif
+
+// <o> QDEC_CONFIG_LEDPRE - LED pre 
+#ifndef QDEC_CONFIG_LEDPRE
+#define QDEC_CONFIG_LEDPRE 511
+#endif
+
+// <o> QDEC_CONFIG_LEDPOL  - LED polarity
+ 
+// <0=> Active low 
+// <1=> Active high 
+
+#ifndef QDEC_CONFIG_LEDPOL
+#define QDEC_CONFIG_LEDPOL 1
+#endif
+
+// <q> QDEC_CONFIG_DBFEN  - Debouncing enable
+ 
+
+#ifndef QDEC_CONFIG_DBFEN
+#define QDEC_CONFIG_DBFEN 0
+#endif
+
+// <q> QDEC_CONFIG_SAMPLE_INTEN  - Sample ready interrupt enable
+ 
+
+#ifndef QDEC_CONFIG_SAMPLE_INTEN
+#define QDEC_CONFIG_SAMPLE_INTEN 0
+#endif
+
+// <o> QDEC_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef QDEC_CONFIG_IRQ_PRIORITY
+#define QDEC_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <e> QDEC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef QDEC_CONFIG_LOG_ENABLED
+#define QDEC_CONFIG_LOG_ENABLED 0
+#endif
+#if  QDEC_CONFIG_LOG_ENABLED
+// <o> QDEC_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef QDEC_CONFIG_LOG_LEVEL
+#define QDEC_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> QDEC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef QDEC_CONFIG_INFO_COLOR
+#define QDEC_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> QDEC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef QDEC_CONFIG_DEBUG_COLOR
+#define QDEC_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //QDEC_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //QDEC_ENABLED
+// </e>
+
+// <e> RNG_ENABLED - nrf_drv_rng - RNG peripheral driver
+//==========================================================
+#ifndef RNG_ENABLED
+#define RNG_ENABLED 1
+#endif
+#if  RNG_ENABLED
+// <q> RNG_CONFIG_ERROR_CORRECTION  - Error correction
+ 
+
+#ifndef RNG_CONFIG_ERROR_CORRECTION
+#define RNG_CONFIG_ERROR_CORRECTION 0
+#endif
+
+// <o> RNG_CONFIG_POOL_SIZE - Pool size 
+#ifndef RNG_CONFIG_POOL_SIZE
+#define RNG_CONFIG_POOL_SIZE 32
+#endif
+
+// <o> RNG_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef RNG_CONFIG_IRQ_PRIORITY
+#define RNG_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <e> RNG_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef RNG_CONFIG_LOG_ENABLED
+#define RNG_CONFIG_LOG_ENABLED 0
+#endif
+#if  RNG_CONFIG_LOG_ENABLED
+// <o> RNG_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef RNG_CONFIG_LOG_LEVEL
+#define RNG_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> RNG_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef RNG_CONFIG_INFO_COLOR
+#define RNG_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> RNG_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef RNG_CONFIG_DEBUG_COLOR
+#define RNG_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //RNG_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //RNG_ENABLED
+// </e>
+
+// <e> RTC_ENABLED - nrf_drv_rtc - RTC peripheral driver
+//==========================================================
+#ifndef RTC_ENABLED
+#define RTC_ENABLED 1
+#endif
+#if  RTC_ENABLED
+// <o> RTC_DEFAULT_CONFIG_FREQUENCY - Frequency  <16-32768> 
+
+
+#ifndef RTC_DEFAULT_CONFIG_FREQUENCY
+#define RTC_DEFAULT_CONFIG_FREQUENCY 32768
+#endif
+
+// <q> RTC_DEFAULT_CONFIG_RELIABLE  - Ensures safe compare event triggering
+ 
+
+#ifndef RTC_DEFAULT_CONFIG_RELIABLE
+#define RTC_DEFAULT_CONFIG_RELIABLE 0
+#endif
+
+// <o> RTC_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <q> RTC0_ENABLED  - Enable RTC0 instance
+ 
+
+#ifndef RTC0_ENABLED
+#define RTC0_ENABLED 1
+#endif
+
+// <q> RTC1_ENABLED  - Enable RTC1 instance
+ 
+
+#ifndef RTC1_ENABLED
+#define RTC1_ENABLED 0
+#endif
+
+// <q> RTC2_ENABLED  - Enable RTC2 instance
+ 
+
+#ifndef RTC2_ENABLED
+#define RTC2_ENABLED 1
+#endif
+
+// <o> NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt 
+#ifndef NRF_MAXIMUM_LATENCY_US
+#define NRF_MAXIMUM_LATENCY_US 2000
+#endif
+
+// <e> RTC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef RTC_CONFIG_LOG_ENABLED
+#define RTC_CONFIG_LOG_ENABLED 0
+#endif
+#if  RTC_CONFIG_LOG_ENABLED
+// <o> RTC_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef RTC_CONFIG_LOG_LEVEL
+#define RTC_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> RTC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef RTC_CONFIG_INFO_COLOR
+#define RTC_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> RTC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef RTC_CONFIG_DEBUG_COLOR
+#define RTC_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //RTC_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //RTC_ENABLED
+// </e>
+
+// <e> SAADC_ENABLED - nrf_drv_saadc - SAADC peripheral driver
+//==========================================================
+#ifndef SAADC_ENABLED
+#define SAADC_ENABLED 1
+#endif
+#if  SAADC_ENABLED
+// <o> SAADC_CONFIG_RESOLUTION  - Resolution
+ 
+// <0=> 8 bit 
+// <1=> 10 bit 
+// <2=> 12 bit 
+// <3=> 14 bit 
+
+#ifndef SAADC_CONFIG_RESOLUTION
+#define SAADC_CONFIG_RESOLUTION 1
+#endif
+
+// <o> SAADC_CONFIG_OVERSAMPLE  - Sample period
+ 
+// <0=> Disabled 
+// <1=> 2x 
+// <2=> 4x 
+// <3=> 8x 
+// <4=> 16x 
+// <5=> 32x 
+// <6=> 64x 
+// <7=> 128x 
+// <8=> 256x 
+
+#ifndef SAADC_CONFIG_OVERSAMPLE
+#define SAADC_CONFIG_OVERSAMPLE 0
+#endif
+
+// <q> SAADC_CONFIG_LP_MODE  - Enabling low power mode
+ 
+
+#ifndef SAADC_CONFIG_LP_MODE
+#define SAADC_CONFIG_LP_MODE 0
+#endif
+
+// <o> SAADC_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef SAADC_CONFIG_IRQ_PRIORITY
+#define SAADC_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <e> SAADC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef SAADC_CONFIG_LOG_ENABLED
+#define SAADC_CONFIG_LOG_ENABLED 0
+#endif
+#if  SAADC_CONFIG_LOG_ENABLED
+// <o> SAADC_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef SAADC_CONFIG_LOG_LEVEL
+#define SAADC_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> SAADC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef SAADC_CONFIG_INFO_COLOR
+#define SAADC_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> SAADC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef SAADC_CONFIG_DEBUG_COLOR
+#define SAADC_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //SAADC_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //SAADC_ENABLED
+// </e>
+
+// <e> SPIS_ENABLED - nrf_drv_spis - SPI Slave driver
+//==========================================================
+#ifndef SPIS_ENABLED
+#define SPIS_ENABLED 1
+#endif
+#if  SPIS_ENABLED
+// <o> SPIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <o> SPIS_DEFAULT_MODE  - Mode
+ 
+// <0=> MODE_0 
+// <1=> MODE_1 
+// <2=> MODE_2 
+// <3=> MODE_3 
+
+#ifndef SPIS_DEFAULT_MODE
+#define SPIS_DEFAULT_MODE 0
+#endif
+
+// <o> SPIS_DEFAULT_BIT_ORDER  - SPIS default bit order
+ 
+// <0=> MSB first 
+// <1=> LSB first 
+
+#ifndef SPIS_DEFAULT_BIT_ORDER
+#define SPIS_DEFAULT_BIT_ORDER 0
+#endif
+
+// <o> SPIS_DEFAULT_DEF - SPIS default DEF character  <0-255> 
+
+
+#ifndef SPIS_DEFAULT_DEF
+#define SPIS_DEFAULT_DEF 255
+#endif
+
+// <o> SPIS_DEFAULT_ORC - SPIS default ORC character  <0-255> 
+
+
+#ifndef SPIS_DEFAULT_ORC
+#define SPIS_DEFAULT_ORC 255
+#endif
+
+// <q> SPIS0_ENABLED  - Enable SPIS0 instance
+ 
+
+#ifndef SPIS0_ENABLED
+#define SPIS0_ENABLED 1
+#endif
+
+// <q> SPIS1_ENABLED  - Enable SPIS1 instance
+ 
+
+#ifndef SPIS1_ENABLED
+#define SPIS1_ENABLED 1
+#endif
+
+// <q> SPIS2_ENABLED  - Enable SPIS2 instance
+ 
+
+#ifndef SPIS2_ENABLED
+#define SPIS2_ENABLED 1
+#endif
+
+// <e> SPIS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef SPIS_CONFIG_LOG_ENABLED
+#define SPIS_CONFIG_LOG_ENABLED 0
+#endif
+#if  SPIS_CONFIG_LOG_ENABLED
+// <o> SPIS_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef SPIS_CONFIG_LOG_LEVEL
+#define SPIS_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> SPIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef SPIS_CONFIG_INFO_COLOR
+#define SPIS_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> SPIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef SPIS_CONFIG_DEBUG_COLOR
+#define SPIS_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //SPIS_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //SPIS_ENABLED
+// </e>
+
+// <e> SPI_ENABLED - nrf_drv_spi - SPI/SPIM peripheral driver
+//==========================================================
+#ifndef SPI_ENABLED
+#define SPI_ENABLED 1
+#endif
+#if  SPI_ENABLED
+// <o> SPI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef SPI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <e> SPI0_ENABLED - Enable SPI0 instance
+//==========================================================
+#ifndef SPI0_ENABLED
+#define SPI0_ENABLED 1
+#endif
+#if  SPI0_ENABLED
+// <q> SPI0_USE_EASY_DMA  - Use EasyDMA
+ 
+
+#ifndef SPI0_USE_EASY_DMA
+#define SPI0_USE_EASY_DMA 1
+#endif
+
+// <o> SPI0_DEFAULT_FREQUENCY  - SPI frequency
+ 
+// <33554432=> 125 kHz 
+// <67108864=> 250 kHz 
+// <134217728=> 500 kHz 
+// <268435456=> 1 MHz 
+// <536870912=> 2 MHz 
+// <1073741824=> 4 MHz 
+// <2147483648=> 8 MHz 
+
+#ifndef SPI0_DEFAULT_FREQUENCY
+#define SPI0_DEFAULT_FREQUENCY 1073741824
+#endif
+
+#endif //SPI0_ENABLED
+// </e>
+
+// <e> SPI1_ENABLED - Enable SPI1 instance
+//==========================================================
+#ifndef SPI1_ENABLED
+#define SPI1_ENABLED 1
+#endif
+#if  SPI1_ENABLED
+// <q> SPI1_USE_EASY_DMA  - Use EasyDMA
+ 
+
+#ifndef SPI1_USE_EASY_DMA
+#define SPI1_USE_EASY_DMA 1
+#endif
+
+// <o> SPI1_DEFAULT_FREQUENCY  - SPI frequency
+ 
+// <33554432=> 125 kHz 
+// <67108864=> 250 kHz 
+// <134217728=> 500 kHz 
+// <268435456=> 1 MHz 
+// <536870912=> 2 MHz 
+// <1073741824=> 4 MHz 
+// <2147483648=> 8 MHz 
+
+#ifndef SPI1_DEFAULT_FREQUENCY
+#define SPI1_DEFAULT_FREQUENCY 1073741824
+#endif
+
+#endif //SPI1_ENABLED
+// </e>
+
+// <e> SPI2_ENABLED - Enable SPI2 instance
+//==========================================================
+#ifndef SPI2_ENABLED
+#define SPI2_ENABLED 1
+#endif
+#if  SPI2_ENABLED
+// <q> SPI2_USE_EASY_DMA  - Use EasyDMA
+ 
+
+#ifndef SPI2_USE_EASY_DMA
+#define SPI2_USE_EASY_DMA 1
+#endif
+
+// <q> SPI2_DEFAULT_FREQUENCY  - Use EasyDMA
+ 
+
+#ifndef SPI2_DEFAULT_FREQUENCY
+#define SPI2_DEFAULT_FREQUENCY 1
+#endif
+
+#endif //SPI2_ENABLED
+// </e>
+
+// <e> SPI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef SPI_CONFIG_LOG_ENABLED
+#define SPI_CONFIG_LOG_ENABLED 0
+#endif
+#if  SPI_CONFIG_LOG_ENABLED
+// <o> SPI_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef SPI_CONFIG_LOG_LEVEL
+#define SPI_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> SPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef SPI_CONFIG_INFO_COLOR
+#define SPI_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> SPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef SPI_CONFIG_DEBUG_COLOR
+#define SPI_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //SPI_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //SPI_ENABLED
+// </e>
+
+// <q> SYSTICK_ENABLED  - nrf_drv_systick - SysTick driver
+ 
+
+#ifndef SYSTICK_ENABLED
+#define SYSTICK_ENABLED 1
+#endif
+
+// <e> TIMER_ENABLED - nrf_drv_timer - TIMER periperal driver
+//==========================================================
+#ifndef TIMER_ENABLED
+#define TIMER_ENABLED 1
+#endif
+#if  TIMER_ENABLED
+// <o> TIMER_DEFAULT_CONFIG_FREQUENCY  - Timer frequency if in Timer mode
+ 
+// <0=> 16 MHz 
+// <1=> 8 MHz 
+// <2=> 4 MHz 
+// <3=> 2 MHz 
+// <4=> 1 MHz 
+// <5=> 500 kHz 
+// <6=> 250 kHz 
+// <7=> 125 kHz 
+// <8=> 62.5 kHz 
+// <9=> 31.25 kHz 
+
+#ifndef TIMER_DEFAULT_CONFIG_FREQUENCY
+#define TIMER_DEFAULT_CONFIG_FREQUENCY 0
+#endif
+
+// <o> TIMER_DEFAULT_CONFIG_MODE  - Timer mode or operation
+ 
+// <0=> Timer 
+// <1=> Counter 
+
+#ifndef TIMER_DEFAULT_CONFIG_MODE
+#define TIMER_DEFAULT_CONFIG_MODE 0
+#endif
+
+// <o> TIMER_DEFAULT_CONFIG_BIT_WIDTH  - Timer counter bit width
+ 
+// <0=> 16 bit 
+// <1=> 8 bit 
+// <2=> 24 bit 
+// <3=> 32 bit 
+
+#ifndef TIMER_DEFAULT_CONFIG_BIT_WIDTH
+#define TIMER_DEFAULT_CONFIG_BIT_WIDTH 0
+#endif
+
+// <o> TIMER_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+#define TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <q> TIMER0_ENABLED  - Enable TIMER0 instance
+ 
+
+#ifndef TIMER0_ENABLED
+#define TIMER0_ENABLED 1
+#endif
+
+// <q> TIMER1_ENABLED  - Enable TIMER1 instance
+ 
+
+#ifndef TIMER1_ENABLED
+#define TIMER1_ENABLED 1
+#endif
+
+// <q> TIMER2_ENABLED  - Enable TIMER2 instance
+ 
+
+#ifndef TIMER2_ENABLED
+#define TIMER2_ENABLED 1
+#endif
+
+// <q> TIMER3_ENABLED  - Enable TIMER3 instance
+ 
+
+#ifndef TIMER3_ENABLED
+#define TIMER3_ENABLED 1
+#endif
+
+// <q> TIMER4_ENABLED  - Enable TIMER4 instance
+ 
+
+#ifndef TIMER4_ENABLED
+#define TIMER4_ENABLED 1
+#endif
+
+// <e> TIMER_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef TIMER_CONFIG_LOG_ENABLED
+#define TIMER_CONFIG_LOG_ENABLED 0
+#endif
+#if  TIMER_CONFIG_LOG_ENABLED
+// <o> TIMER_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef TIMER_CONFIG_LOG_LEVEL
+#define TIMER_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> TIMER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef TIMER_CONFIG_INFO_COLOR
+#define TIMER_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> TIMER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef TIMER_CONFIG_DEBUG_COLOR
+#define TIMER_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //TIMER_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //TIMER_ENABLED
+// </e>
+
+// <e> TWIS_ENABLED - nrf_drv_twis - TWIS peripheral driver
+//==========================================================
+#ifndef TWIS_ENABLED
+#define TWIS_ENABLED 1
+#endif
+#if  TWIS_ENABLED
+// <o> TWIS_DEFAULT_CONFIG_ADDR0 - Address0 
+#ifndef TWIS_DEFAULT_CONFIG_ADDR0
+#define TWIS_DEFAULT_CONFIG_ADDR0 0
+#endif
+
+// <o> TWIS_DEFAULT_CONFIG_ADDR1 - Address1 
+#ifndef TWIS_DEFAULT_CONFIG_ADDR1
+#define TWIS_DEFAULT_CONFIG_ADDR1 0
+#endif
+
+// <o> TWIS_DEFAULT_CONFIG_SCL_PULL  - SCL pin pull configuration
+ 
+// <0=> Disabled 
+// <1=> Pull down 
+// <3=> Pull up 
+
+#ifndef TWIS_DEFAULT_CONFIG_SCL_PULL
+#define TWIS_DEFAULT_CONFIG_SCL_PULL 0
+#endif
+
+// <o> TWIS_DEFAULT_CONFIG_SDA_PULL  - SDA pin pull configuration
+ 
+// <0=> Disabled 
+// <1=> Pull down 
+// <3=> Pull up 
+
+#ifndef TWIS_DEFAULT_CONFIG_SDA_PULL
+#define TWIS_DEFAULT_CONFIG_SDA_PULL 0
+#endif
+
+// <o> TWIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <q> TWIS0_ENABLED  - Enable TWIS0 instance
+ 
+
+#ifndef TWIS0_ENABLED
+#define TWIS0_ENABLED 1
+#endif
+
+// <q> TWIS1_ENABLED  - Enable TWIS1 instance
+ 
+
+#ifndef TWIS1_ENABLED
+#define TWIS1_ENABLED 1
+#endif
+
+// <q> TWIS_ASSUME_INIT_AFTER_RESET_ONLY  - Assume that any instance would be initialized only once
+ 
+
+// <i> Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code.
+
+#ifndef TWIS_ASSUME_INIT_AFTER_RESET_ONLY
+#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+#endif
+
+// <q> TWIS_NO_SYNC_MODE  - Remove support for synchronous mode
+ 
+
+// <i> Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources.
+
+#ifndef TWIS_NO_SYNC_MODE
+#define TWIS_NO_SYNC_MODE 0
+#endif
+
+// <e> TWIS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef TWIS_CONFIG_LOG_ENABLED
+#define TWIS_CONFIG_LOG_ENABLED 0
+#endif
+#if  TWIS_CONFIG_LOG_ENABLED
+// <o> TWIS_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef TWIS_CONFIG_LOG_LEVEL
+#define TWIS_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> TWIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef TWIS_CONFIG_INFO_COLOR
+#define TWIS_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> TWIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef TWIS_CONFIG_DEBUG_COLOR
+#define TWIS_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //TWIS_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //TWIS_ENABLED
+// </e>
+
+// <e> TWI_ENABLED - nrf_drv_twi - TWI/TWIM peripheral driver
+//==========================================================
+#ifndef TWI_ENABLED
+#define TWI_ENABLED 1
+#endif
+#if  TWI_ENABLED
+// <o> TWI_DEFAULT_CONFIG_FREQUENCY  - Frequency
+ 
+// <26738688=> 100k 
+// <67108864=> 250k 
+// <104857600=> 400k 
+
+#ifndef TWI_DEFAULT_CONFIG_FREQUENCY
+#define TWI_DEFAULT_CONFIG_FREQUENCY 26738688
+#endif
+
+// <q> TWI_DEFAULT_CONFIG_CLR_BUS_INIT  - Enables bus clearing procedure during init
+ 
+
+#ifndef TWI_DEFAULT_CONFIG_CLR_BUS_INIT
+#define TWI_DEFAULT_CONFIG_CLR_BUS_INIT 0
+#endif
+
+// <q> TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT  - Enables bus holding after uninit
+ 
+
+#ifndef TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT
+#define TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
+#endif
+
+// <o> TWI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef TWI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define TWI_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <e> TWI0_ENABLED - Enable TWI0 instance
+//==========================================================
+#ifndef TWI0_ENABLED
+#define TWI0_ENABLED 1
+#endif
+#if  TWI0_ENABLED
+// <q> TWI0_USE_EASY_DMA  - Use EasyDMA (if present)
+ 
+
+#ifndef TWI0_USE_EASY_DMA
+#define TWI0_USE_EASY_DMA 0
+#endif
+
+#endif //TWI0_ENABLED
+// </e>
+
+// <e> TWI1_ENABLED - Enable TWI1 instance
+//==========================================================
+#ifndef TWI1_ENABLED
+#define TWI1_ENABLED 1
+#endif
+#if  TWI1_ENABLED
+// <q> TWI1_USE_EASY_DMA  - Use EasyDMA (if present)
+ 
+
+#ifndef TWI1_USE_EASY_DMA
+#define TWI1_USE_EASY_DMA 0
+#endif
+
+#endif //TWI1_ENABLED
+// </e>
+
+// <e> TWI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef TWI_CONFIG_LOG_ENABLED
+#define TWI_CONFIG_LOG_ENABLED 0
+#endif
+#if  TWI_CONFIG_LOG_ENABLED
+// <o> TWI_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef TWI_CONFIG_LOG_LEVEL
+#define TWI_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> TWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef TWI_CONFIG_INFO_COLOR
+#define TWI_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> TWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef TWI_CONFIG_DEBUG_COLOR
+#define TWI_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //TWI_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //TWI_ENABLED
+// </e>
+
+// <e> UART_ENABLED - nrf_drv_uart - UART/UARTE peripheral driver
+//==========================================================
+#ifndef UART_ENABLED
+#define UART_ENABLED 1
+#endif
+#if  UART_ENABLED
+// <o> UART_DEFAULT_CONFIG_HWFC  - Hardware Flow Control
+ 
+// <0=> Disabled 
+// <1=> Enabled 
+
+#ifndef UART_DEFAULT_CONFIG_HWFC
+#define UART_DEFAULT_CONFIG_HWFC 1
+#endif
+
+// <o> UART_DEFAULT_CONFIG_PARITY  - Parity
+ 
+// <0=> Excluded 
+// <14=> Included 
+
+#ifndef UART_DEFAULT_CONFIG_PARITY
+#define UART_DEFAULT_CONFIG_PARITY 0
+#endif
+
+// <o> UART_DEFAULT_CONFIG_BAUDRATE  - Default Baudrate
+ 
+// <323584=> 1200 baud 
+// <643072=> 2400 baud 
+// <1290240=> 4800 baud 
+// <2576384=> 9600 baud 
+// <3862528=> 14400 baud 
+// <5152768=> 19200 baud 
+// <7716864=> 28800 baud 
+// <10289152=> 38400 baud 
+// <15400960=> 57600 baud 
+// <20615168=> 76800 baud 
+// <30801920=> 115200 baud 
+// <61865984=> 230400 baud 
+// <67108864=> 250000 baud 
+// <121634816=> 460800 baud 
+// <251658240=> 921600 baud 
+// <268435456=> 57600 baud 
+
+#ifndef UART_DEFAULT_CONFIG_BAUDRATE
+#define UART_DEFAULT_CONFIG_BAUDRATE 2576384
+#endif
+
+// <o> UART_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef UART_DEFAULT_CONFIG_IRQ_PRIORITY
+#define UART_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <q> UART_EASY_DMA_SUPPORT  - Driver supporting EasyDMA
+ 
+
+#ifndef UART_EASY_DMA_SUPPORT
+#define UART_EASY_DMA_SUPPORT 1
+#endif
+
+// <q> UART_LEGACY_SUPPORT  - Driver supporting Legacy mode
+ 
+
+#ifndef UART_LEGACY_SUPPORT
+#define UART_LEGACY_SUPPORT 1
+#endif
+
+// <e> UART0_ENABLED - Enable UART0 instance
+//==========================================================
+#ifndef UART0_ENABLED
+#define UART0_ENABLED 1
+#endif
+#if  UART0_ENABLED
+// <q> UART0_CONFIG_USE_EASY_DMA  - Default setting for using EasyDMA
+ 
+
+#ifndef UART0_CONFIG_USE_EASY_DMA
+#define UART0_CONFIG_USE_EASY_DMA 1
+#endif
+
+#endif //UART0_ENABLED
+// </e>
+
+// <e> UART1_ENABLED - Enable UART1 instance
+//==========================================================
+#ifndef UART1_ENABLED
+#define UART1_ENABLED 0
+#endif
+#if  UART1_ENABLED
+// <q> UART1_CONFIG_USE_EASY_DMA  - Default setting for using EasyDMA
+ 
+
+#ifndef UART1_CONFIG_USE_EASY_DMA
+#define UART1_CONFIG_USE_EASY_DMA 1
+#endif
+
+#endif //UART1_ENABLED
+// </e>
+
+// <e> UART_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef UART_CONFIG_LOG_ENABLED
+#define UART_CONFIG_LOG_ENABLED 0
+#endif
+#if  UART_CONFIG_LOG_ENABLED
+// <o> UART_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef UART_CONFIG_LOG_LEVEL
+#define UART_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef UART_CONFIG_INFO_COLOR
+#define UART_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef UART_CONFIG_DEBUG_COLOR
+#define UART_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //UART_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //UART_ENABLED
+// </e>
+
+// <e> USBD_ENABLED - nrf_drv_usbd - USB driver
+//==========================================================
+#ifndef USBD_ENABLED
+#define USBD_ENABLED 0
+#endif
+#if  USBD_ENABLED
+// <o> USBD_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef USBD_CONFIG_IRQ_PRIORITY
+#define USBD_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <o> NRF_DRV_USBD_DMASCHEDULER_MODE  - USBD SMA scheduler working scheme
+ 
+// <0=> Prioritized access 
+// <1=> Round Robin 
+
+#ifndef NRF_DRV_USBD_DMASCHEDULER_MODE
+#define NRF_DRV_USBD_DMASCHEDULER_MODE 0
+#endif
+
+// <q> NRF_USBD_DRV_LOG_ENABLED  - Enable logging.
+ 
+
+#ifndef NRF_USBD_DRV_LOG_ENABLED
+#define NRF_USBD_DRV_LOG_ENABLED 0
+#endif
+
+#endif //USBD_ENABLED
+// </e>
+
+// <e> WDT_ENABLED - nrf_drv_wdt - WDT peripheral driver
+//==========================================================
+#ifndef WDT_ENABLED
+#define WDT_ENABLED 0
+#endif
+#if  WDT_ENABLED
+// <o> WDT_CONFIG_BEHAVIOUR  - WDT behavior in CPU SLEEP or HALT mode
+ 
+// <1=> Run in SLEEP, Pause in HALT 
+// <8=> Pause in SLEEP, Run in HALT 
+// <9=> Run in SLEEP and HALT 
+// <0=> Pause in SLEEP and HALT 
+
+#ifndef WDT_CONFIG_BEHAVIOUR
+#define WDT_CONFIG_BEHAVIOUR 1
+#endif
+
+// <o> WDT_CONFIG_RELOAD_VALUE - Reload value  <15-4294967295> 
+
+
+#ifndef WDT_CONFIG_RELOAD_VALUE
+#define WDT_CONFIG_RELOAD_VALUE 2000
+#endif
+
+// <o> WDT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+ 
+
+// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest) 
+// <1=> 1 
+// <2=> 2 
+// <3=> 3 
+// <4=> 4 
+// <5=> 5 
+// <6=> 6 
+// <7=> 7 
+
+#ifndef WDT_CONFIG_IRQ_PRIORITY
+#define WDT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+// <e> WDT_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef WDT_CONFIG_LOG_ENABLED
+#define WDT_CONFIG_LOG_ENABLED 0
+#endif
+#if  WDT_CONFIG_LOG_ENABLED
+// <o> WDT_CONFIG_LOG_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef WDT_CONFIG_LOG_LEVEL
+#define WDT_CONFIG_LOG_LEVEL 3
+#endif
+
+// <o> WDT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef WDT_CONFIG_INFO_COLOR
+#define WDT_CONFIG_INFO_COLOR 0
+#endif
+
+// <o> WDT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef WDT_CONFIG_DEBUG_COLOR
+#define WDT_CONFIG_DEBUG_COLOR 0
+#endif
+
+#endif //WDT_CONFIG_LOG_ENABLED
+// </e>
+
+#endif //WDT_ENABLED
+// </e>
+
+// </h> 
+//==========================================================
+
+// <h> nRF_Libraries 
+
+//==========================================================
+// <q> APP_FIFO_ENABLED  - app_fifo - Software FIFO implementation
+ 
+
+#ifndef APP_FIFO_ENABLED
+#define APP_FIFO_ENABLED 0
+#endif
+
+// <q> APP_GPIOTE_ENABLED  - app_gpiote - GPIOTE events dispatcher
+ 
+
+#ifndef APP_GPIOTE_ENABLED
+#define APP_GPIOTE_ENABLED 0
+#endif
+
+// <q> APP_PWM_ENABLED  - app_pwm - PWM functionality
+ 
+
+#ifndef APP_PWM_ENABLED
+#define APP_PWM_ENABLED 0
+#endif
+
+// <e> APP_SCHEDULER_ENABLED - app_scheduler - Events scheduler
+//==========================================================
+#ifndef APP_SCHEDULER_ENABLED
+#define APP_SCHEDULER_ENABLED 1
+#endif
+#if  APP_SCHEDULER_ENABLED
+// <q> APP_SCHEDULER_WITH_PAUSE  - Enabling pause feature
+ 
+
+#ifndef APP_SCHEDULER_WITH_PAUSE
+#define APP_SCHEDULER_WITH_PAUSE 0
+#endif
+
+// <q> APP_SCHEDULER_WITH_PROFILER  - Enabling scheduler profiling
+ 
+
+#ifndef APP_SCHEDULER_WITH_PROFILER
+#define APP_SCHEDULER_WITH_PROFILER 0
+#endif
+
+#endif //APP_SCHEDULER_ENABLED
+// </e>
+
+// <e> APP_TIMER_ENABLED - app_timer - Application timer functionality
+//==========================================================
+#ifndef APP_TIMER_ENABLED
+#define APP_TIMER_ENABLED 1
+#endif
+#if  APP_TIMER_ENABLED
+// <q> APP_TIMER_WITH_PROFILER  - Enable app_timer profiling
+ 
+
+#ifndef APP_TIMER_WITH_PROFILER
+#define APP_TIMER_WITH_PROFILER 0
+#endif
+
+// <q> APP_TIMER_KEEPS_RTC_ACTIVE  - Enable RTC always on
+ 
+
+// <i> If option is enabled RTC is kept running even if there is no active timers.
+// <i> This option can be used when app_timer is used for timestamping.
+
+#ifndef APP_TIMER_KEEPS_RTC_ACTIVE
+#define APP_TIMER_KEEPS_RTC_ACTIVE 0
+#endif
+
+#endif //APP_TIMER_ENABLED
+// </e>
+
+// <q> APP_TWI_ENABLED  - app_twi - TWI transaction manager
+ 
+
+#ifndef APP_TWI_ENABLED
+#define APP_TWI_ENABLED 0
+#endif
+
+// <e> APP_UART_ENABLED - app_uart - UART driver
+//==========================================================
+#ifndef APP_UART_ENABLED
+#define APP_UART_ENABLED 1
+#endif
+#if  APP_UART_ENABLED
+// <o> APP_UART_DRIVER_INSTANCE  - UART instance used
+ 
+// <0=> 0 
+
+#ifndef APP_UART_DRIVER_INSTANCE
+#define APP_UART_DRIVER_INSTANCE 0
+#endif
+
+#endif //APP_UART_ENABLED
+// </e>
+
+// <q> APP_USBD_CLASS_AUDIO_ENABLED  - app_usbd_audio - USB AUDIO class
+ 
+
+#ifndef APP_USBD_CLASS_AUDIO_ENABLED
+#define APP_USBD_CLASS_AUDIO_ENABLED 0
+#endif
+
+// <q> APP_USBD_CLASS_HID_ENABLED  - app_usbd_hid - USB HID class
+ 
+
+#ifndef APP_USBD_CLASS_HID_ENABLED
+#define APP_USBD_CLASS_HID_ENABLED 1
+#endif
+
+// <q> APP_USBD_HID_GENERIC_ENABLED  - app_usbd_hid_generic - USB HID generic
+ 
+
+#ifndef APP_USBD_HID_GENERIC_ENABLED
+#define APP_USBD_HID_GENERIC_ENABLED 1
+#endif
+
+// <q> APP_USBD_HID_KBD_ENABLED  - app_usbd_hid_kbd - USB HID keyboard
+ 
+
+#ifndef APP_USBD_HID_KBD_ENABLED
+#define APP_USBD_HID_KBD_ENABLED 0
+#endif
+
+// <q> APP_USBD_HID_MOUSE_ENABLED  - app_usbd_hid_mouse - USB HID mouse
+ 
+
+#ifndef APP_USBD_HID_MOUSE_ENABLED
+#define APP_USBD_HID_MOUSE_ENABLED 1
+#endif
+
+// <q> BUTTON_ENABLED  - app_button - buttons handling module
+ 
+
+#ifndef BUTTON_ENABLED
+#define BUTTON_ENABLED 0
+#endif
+
+// <q> CRC16_ENABLED  - crc16 - CRC16 calculation routines
+ 
+
+#ifndef CRC16_ENABLED
+#define CRC16_ENABLED 1
+#endif
+
+// <q> CRC32_ENABLED  - crc32 - CRC32 calculation routines
+ 
+
+#ifndef CRC32_ENABLED
+#define CRC32_ENABLED 1
+#endif
+
+// <e> FDS_ENABLED - fds - Flash data storage module
+//==========================================================
+#ifndef FDS_ENABLED
+#define FDS_ENABLED 1
+#endif
+#if  FDS_ENABLED
+// <o> FDS_OP_QUEUE_SIZE - Size of the internal queue. 
+#ifndef FDS_OP_QUEUE_SIZE
+#define FDS_OP_QUEUE_SIZE 4
+#endif
+
+// <o> FDS_CHUNK_QUEUE_SIZE - Determines how many @ref fds_record_chunk_t structures can be buffered at any time. 
+#ifndef FDS_CHUNK_QUEUE_SIZE
+#define FDS_CHUNK_QUEUE_SIZE 8
+#endif
+
+// <o> FDS_MAX_USERS - Maximum number of callbacks that can be registered. 
+#ifndef FDS_MAX_USERS
+#define FDS_MAX_USERS 8
+#endif
+
+// <o> FDS_VIRTUAL_PAGES - Number of virtual flash pages to use. 
+// <i> One of the virtual pages is reserved by the system for garbage collection.
+// <i> Therefore, the minimum is two virtual pages: one page to store data and
+// <i> one page to be used by the system for garbage collection. The total amount
+// <i> of flash memory that is used by FDS amounts to @ref FDS_VIRTUAL_PAGES
+// <i> @ref FDS_VIRTUAL_PAGE_SIZE * 4 bytes.
+
+#ifndef FDS_VIRTUAL_PAGES
+#define FDS_VIRTUAL_PAGES 3
+#endif
+
+// <o> FDS_VIRTUAL_PAGE_SIZE  - The size of a virtual page of flash memory, expressed in number of 4-byte words.
+ 
+
+// <i> By default, a virtual page is the same size as a physical page.
+// <i> The size of a virtual page must be a multiple of the size of a physical page.
+// <1024=> 1024 
+// <2048=> 2048 
+
+#ifndef FDS_VIRTUAL_PAGE_SIZE
+#define FDS_VIRTUAL_PAGE_SIZE 1024
+#endif
+
+#endif //FDS_ENABLED
+// </e>
+
+// <e> FSTORAGE_ENABLED - fstorage - Flash storage module
+//==========================================================
+#ifndef FSTORAGE_ENABLED
+#define FSTORAGE_ENABLED 1
+#endif
+#if  FSTORAGE_ENABLED
+// <o> FS_QUEUE_SIZE - Configures the size of the internal queue. 
+// <i> Increase this if there are many users, or if it is likely that many
+// <i> operation will be queued at once without waiting for the previous operations
+// <i> to complete. In general, increase the queue size if you frequently receive
+// <i> @ref FS_ERR_QUEUE_FULL errors when calling @ref fs_store or @ref fs_erase.
+
+#ifndef FS_QUEUE_SIZE
+#define FS_QUEUE_SIZE 4
+#endif
+
+// <o> FS_OP_MAX_RETRIES - Number attempts to execute an operation if the SoftDevice fails. 
+// <i> Increase this value if events return the @ref FS_ERR_OPERATION_TIMEOUT
+// <i> error often. The SoftDevice may fail to schedule flash access due to high BLE activity.
+
+#ifndef FS_OP_MAX_RETRIES
+#define FS_OP_MAX_RETRIES 3
+#endif
+
+// <o> FS_MAX_WRITE_SIZE_WORDS - Maximum number of words to be written to flash in a single operation. 
+// <i> Tweaking this value can increase the chances of the SoftDevice being
+// <i> able to fit flash operations in between radio activity. This value is bound by the
+// <i> maximum number of words which the SoftDevice can write to flash in a single call to
+// <i> @ref sd_flash_write, which is 256 words for nRF51 ICs and 1024 words for nRF52 ICs.
+
+#ifndef FS_MAX_WRITE_SIZE_WORDS
+#define FS_MAX_WRITE_SIZE_WORDS 1024
+#endif
+
+#endif //FSTORAGE_ENABLED
+// </e>
+
+// <q> ECC_ENABLED  - ecc - Elliptic Curve Cryptography Library
+ 
+
+#ifndef ECC_ENABLED
+#define ECC_ENABLED 0
+#endif
+
+// <q> HARDFAULT_HANDLER_ENABLED  - hardfault_default - HardFault default handler for debugging and release
+ 
+
+#ifndef HARDFAULT_HANDLER_ENABLED
+#define HARDFAULT_HANDLER_ENABLED 1
+#endif
+
+// <e> HCI_MEM_POOL_ENABLED - hci_mem_pool - memory pool implementation used by HCI
+//==========================================================
+#ifndef HCI_MEM_POOL_ENABLED
+#define HCI_MEM_POOL_ENABLED 0
+#endif
+#if  HCI_MEM_POOL_ENABLED
+// <o> HCI_TX_BUF_SIZE - TX buffer size in bytes. 
+#ifndef HCI_TX_BUF_SIZE
+#define HCI_TX_BUF_SIZE 600
+#endif
+
+// <o> HCI_RX_BUF_SIZE - RX buffer size in bytes. 
+#ifndef HCI_RX_BUF_SIZE
+#define HCI_RX_BUF_SIZE 600
+#endif
+
+// <o> HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size. 
+#ifndef HCI_RX_BUF_QUEUE_SIZE
+#define HCI_RX_BUF_QUEUE_SIZE 4
+#endif
+
+#endif //HCI_MEM_POOL_ENABLED
+// </e>
+
+// <e> HCI_SLIP_ENABLED - hci_slip - SLIP protocol implementation used by HCI
+//==========================================================
+#ifndef HCI_SLIP_ENABLED
+#define HCI_SLIP_ENABLED 0
+#endif
+#if  HCI_SLIP_ENABLED
+// <o> HCI_UART_BAUDRATE  - Default Baudrate
+ 
+// <323584=> 1200 baud 
+// <643072=> 2400 baud 
+// <1290240=> 4800 baud 
+// <2576384=> 9600 baud 
+// <3862528=> 14400 baud 
+// <5152768=> 19200 baud 
+// <7716864=> 28800 baud 
+// <10289152=> 38400 baud 
+// <15400960=> 57600 baud 
+// <20615168=> 76800 baud 
+// <30801920=> 115200 baud 
+// <61865984=> 230400 baud 
+// <67108864=> 250000 baud 
+// <121634816=> 460800 baud 
+// <251658240=> 921600 baud 
+// <268435456=> 57600 baud 
+
+#ifndef HCI_UART_BAUDRATE
+#define HCI_UART_BAUDRATE 30801920
+#endif
+
+// <o> HCI_UART_FLOW_CONTROL  - Hardware Flow Control
+ 
+// <0=> Disabled 
+// <1=> Enabled 
+
+#ifndef HCI_UART_FLOW_CONTROL
+#define HCI_UART_FLOW_CONTROL 0
+#endif
+
+// <o> HCI_UART_RX_PIN - UART RX pin 
+#ifndef HCI_UART_RX_PIN
+#define HCI_UART_RX_PIN 8
+#endif
+
+// <o> HCI_UART_TX_PIN - UART TX pin 
+#ifndef HCI_UART_TX_PIN
+#define HCI_UART_TX_PIN 6
+#endif
+
+// <o> HCI_UART_RTS_PIN - UART RTS pin 
+#ifndef HCI_UART_RTS_PIN
+#define HCI_UART_RTS_PIN 5
+#endif
+
+// <o> HCI_UART_CTS_PIN - UART CTS pin 
+#ifndef HCI_UART_CTS_PIN
+#define HCI_UART_CTS_PIN 7
+#endif
+
+#endif //HCI_SLIP_ENABLED
+// </e>
+
+// <e> HCI_TRANSPORT_ENABLED - hci_transport - HCI transport
+//==========================================================
+#ifndef HCI_TRANSPORT_ENABLED
+#define HCI_TRANSPORT_ENABLED 0
+#endif
+#if  HCI_TRANSPORT_ENABLED
+// <o> HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits. 
+#ifndef HCI_MAX_PACKET_SIZE_IN_BITS
+#define HCI_MAX_PACKET_SIZE_IN_BITS 8000
+#endif
+
+#endif //HCI_TRANSPORT_ENABLED
+// </e>
+
+// <q> LED_SOFTBLINK_ENABLED  - led_softblink - led_softblink module
+ 
+
+#ifndef LED_SOFTBLINK_ENABLED
+#define LED_SOFTBLINK_ENABLED 0
+#endif
+
+// <q> LOW_POWER_PWM_ENABLED  - low_power_pwm - low_power_pwm module
+ 
+
+#ifndef LOW_POWER_PWM_ENABLED
+#define LOW_POWER_PWM_ENABLED 0
+#endif
+
+// <e> MEM_MANAGER_ENABLED - mem_manager - Dynamic memory allocator
+//==========================================================
+#ifndef MEM_MANAGER_ENABLED
+#define MEM_MANAGER_ENABLED 0
+#endif
+#if  MEM_MANAGER_ENABLED
+// <o> MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block.  <0-255> 
+
+
+#ifndef MEMORY_MANAGER_SMALL_BLOCK_COUNT
+#define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1
+#endif
+
+// <o> MEMORY_MANAGER_SMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'small' block. 
+// <i>  Size of each memory blocks identified as 'small' block. Memory block are recommended to be word-sized.
+
+#ifndef MEMORY_MANAGER_SMALL_BLOCK_SIZE
+#define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32
+#endif
+
+// <o> MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block.  <0-255> 
+
+
+#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_COUNT
+#define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0
+#endif
+
+// <o> MEMORY_MANAGER_MEDIUM_BLOCK_SIZE -  Size of each memory blocks identified as 'medium' block. 
+// <i>  Size of each memory blocks identified as 'medium' block. Memory block are recommended to be word-sized.
+
+#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_SIZE
+#define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256
+#endif
+
+// <o> MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block.  <0-255> 
+
+
+#ifndef MEMORY_MANAGER_LARGE_BLOCK_COUNT
+#define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0
+#endif
+
+// <o> MEMORY_MANAGER_LARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'large' block. 
+// <i>  Size of each memory blocks identified as 'large' block. Memory block are recommended to be word-sized.
+
+#ifndef MEMORY_MANAGER_LARGE_BLOCK_SIZE
+#define MEMORY_MANAGER_LARGE_BLOCK_SIZE 256
+#endif
+
+// <q> MEM_MANAGER_ENABLE_LOGS  - Enable debug trace in the module.
+ 
+
+#ifndef MEM_MANAGER_ENABLE_LOGS
+#define MEM_MANAGER_ENABLE_LOGS 0
+#endif
+
+// <q> MEM_MANAGER_DISABLE_API_PARAM_CHECK  - Disable API parameter checks in the module.
+ 
+
+#ifndef MEM_MANAGER_DISABLE_API_PARAM_CHECK
+#define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0
+#endif
+
+#endif //MEM_MANAGER_ENABLED
+// </e>
+
+// <e> NRF_CSENSE_ENABLED - nrf_csense - nrf_csense module
+//==========================================================
+#ifndef NRF_CSENSE_ENABLED
+#define NRF_CSENSE_ENABLED 0
+#endif
+#if  NRF_CSENSE_ENABLED
+// <o> NRF_CSENSE_PAD_HYSTERESIS - Minimal value of change to decide that pad was touched. 
+#ifndef NRF_CSENSE_PAD_HYSTERESIS
+#define NRF_CSENSE_PAD_HYSTERESIS 15
+#endif
+
+// <o> NRF_CSENSE_PAD_DEVIATION - Minimal value measured on pad to take its value while calculating step. 
+#ifndef NRF_CSENSE_PAD_DEVIATION
+#define NRF_CSENSE_PAD_DEVIATION 70
+#endif
+
+// <o> NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on pad to take its value into account. 
+#ifndef NRF_CSENSE_MIN_PAD_VALUE
+#define NRF_CSENSE_MIN_PAD_VALUE 20
+#endif
+
+// <o> NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance. 
+#ifndef NRF_CSENSE_MAX_PADS_NUMBER
+#define NRF_CSENSE_MAX_PADS_NUMBER 20
+#endif
+
+// <o> NRF_CSENSE_MAX_VALUE - Maximum normalized value got from measurement. 
+#ifndef NRF_CSENSE_MAX_VALUE
+#define NRF_CSENSE_MAX_VALUE 1000
+#endif
+
+// <o> NRF_CSENSE_OUTPUT_PIN - Output pin used by lower module. 
+// <i> This is only used when running on NRF51.
+
+#ifndef NRF_CSENSE_OUTPUT_PIN
+#define NRF_CSENSE_OUTPUT_PIN 30
+#endif
+
+#endif //NRF_CSENSE_ENABLED
+// </e>
+
+// <e> NRF_DRV_CSENSE_ENABLED - nrf_drv_csense - Capacitive sensor module
+//==========================================================
+#ifndef NRF_DRV_CSENSE_ENABLED
+#define NRF_DRV_CSENSE_ENABLED 0
+#endif
+#if  NRF_DRV_CSENSE_ENABLED
+// <o> TIMER0_FOR_CSENSE - First TIMER instance used by the driver (except nRF51) 
+#ifndef TIMER0_FOR_CSENSE
+#define TIMER0_FOR_CSENSE 1
+#endif
+
+// <o> TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (except nRF51) 
+#ifndef TIMER1_FOR_CSENSE
+#define TIMER1_FOR_CSENSE 2
+#endif
+
+// <o> MEASUREMENT_PERIOD - Single measurement period. 
+// <i> Time of single measurement can be calculated as T = (1/2)*MEASUREMENT_PERIOD*(1/f_OSC) where f_OSC = I_SOURCE / (2C*(VUP-VDOWN) ). I_SOURCE, VUP and VDOWN are values used to initialize COMP and C is capacitance of used pad.
+
+#ifndef MEASUREMENT_PERIOD
+#define MEASUREMENT_PERIOD 20
+#endif
+
+#endif //NRF_DRV_CSENSE_ENABLED
+// </e>
+
+// <q> NRF_QUEUE_ENABLED  - nrf_queue - Queue module
+ 
+
+#ifndef NRF_QUEUE_ENABLED
+#define NRF_QUEUE_ENABLED 1
+#endif
+
+// <q> SLIP_ENABLED  - slip - SLIP encoding decoding
+ 
+
+#ifndef SLIP_ENABLED
+#define SLIP_ENABLED 0
+#endif
+
+// <h> app_usbd_cdc_acm - USB CDC ACM class
+
+//==========================================================
+// <q> APP_USBD_CLASS_CDC_ACM_ENABLED  - Enabling USBD CDC ACM Class library
+ 
+
+#ifndef APP_USBD_CLASS_CDC_ACM_ENABLED
+#define APP_USBD_CLASS_CDC_ACM_ENABLED 0
+#endif
+
+// <q> APP_USBD_CDC_ACM_LOG_ENABLED  - Enables logging in the module.
+ 
+
+#ifndef APP_USBD_CDC_ACM_LOG_ENABLED
+#define APP_USBD_CDC_ACM_LOG_ENABLED 0
+#endif
+
+// </h> 
+//==========================================================
+
+// <h> app_usbd_msc - USB MSC class
+
+//==========================================================
+// <q> APP_USBD_CLASS_MSC_ENABLED  - Enabling USBD MSC Class library
+ 
+
+#ifndef APP_USBD_CLASS_MSC_ENABLED
+#define APP_USBD_CLASS_MSC_ENABLED 0
+#endif
+
+// <q> APP_USBD_MSC_CLASS_LOG_ENABLED  - Enables logging in the module.
+ 
+
+#ifndef APP_USBD_MSC_CLASS_LOG_ENABLED
+#define APP_USBD_MSC_CLASS_LOG_ENABLED 0
+#endif
+
+// </h> 
+//==========================================================
+
+// </h> 
+//==========================================================
+
+// <h> nRF_Log 
+
+//==========================================================
+// <e> NRF_LOG_ENABLED - nrf_log - Logging
+//==========================================================
+#ifndef NRF_LOG_ENABLED
+#define NRF_LOG_ENABLED 0
+#endif
+#if  NRF_LOG_ENABLED
+// <e> NRF_LOG_USES_COLORS - If enabled then ANSI escape code for colors is prefixed to every string
+//==========================================================
+#ifndef NRF_LOG_USES_COLORS
+#define NRF_LOG_USES_COLORS 0
+#endif
+#if  NRF_LOG_USES_COLORS
+// <o> NRF_LOG_COLOR_DEFAULT  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef NRF_LOG_COLOR_DEFAULT
+#define NRF_LOG_COLOR_DEFAULT 0
+#endif
+
+// <o> NRF_LOG_ERROR_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef NRF_LOG_ERROR_COLOR
+#define NRF_LOG_ERROR_COLOR 0
+#endif
+
+// <o> NRF_LOG_WARNING_COLOR  - ANSI escape code prefix.
+ 
+// <0=> Default 
+// <1=> Black 
+// <2=> Red 
+// <3=> Green 
+// <4=> Yellow 
+// <5=> Blue 
+// <6=> Magenta 
+// <7=> Cyan 
+// <8=> White 
+
+#ifndef NRF_LOG_WARNING_COLOR
+#define NRF_LOG_WARNING_COLOR 0
+#endif
+
+#endif //NRF_LOG_USES_COLORS
+// </e>
+
+// <o> NRF_LOG_DEFAULT_LEVEL  - Default Severity level
+ 
+// <0=> Off 
+// <1=> Error 
+// <2=> Warning 
+// <3=> Info 
+// <4=> Debug 
+
+#ifndef NRF_LOG_DEFAULT_LEVEL
+#define NRF_LOG_DEFAULT_LEVEL 3
+#endif
+
+// <e> NRF_LOG_DEFERRED - Enable deffered logger.
+
+// <i> Log data is buffered and can be processed in idle.
+//==========================================================
+#ifndef NRF_LOG_DEFERRED
+#define NRF_LOG_DEFERRED 1
+#endif
+#if  NRF_LOG_DEFERRED
+// <o> NRF_LOG_DEFERRED_BUFSIZE - Size of the buffer for logs in words. 
+// <i> Must be power of 2
+
+#ifndef NRF_LOG_DEFERRED_BUFSIZE
+#define NRF_LOG_DEFERRED_BUFSIZE 256
+#endif
+
+#endif //NRF_LOG_DEFERRED
+// </e>
+
+// <q> NRF_LOG_USES_TIMESTAMP  - Enable timestamping
+ 
+
+// <i> Function for getting the timestamp is provided by the user
+
+#ifndef NRF_LOG_USES_TIMESTAMP
+#define NRF_LOG_USES_TIMESTAMP 0
+#endif
+
+#endif //NRF_LOG_ENABLED
+// </e>
+
+// <h> nrf_log_backend - Logging sink
+
+//==========================================================
+// <o> NRF_LOG_BACKEND_MAX_STRING_LENGTH - Buffer for storing single output string 
+// <i> Logger backend RAM usage is determined by this value.
+
+#ifndef NRF_LOG_BACKEND_MAX_STRING_LENGTH
+#define NRF_LOG_BACKEND_MAX_STRING_LENGTH 256
+#endif
+
+// <o> NRF_LOG_TIMESTAMP_DIGITS - Number of digits for timestamp 
+// <i> If higher resolution timestamp source is used it might be needed to increase that
+
+#ifndef NRF_LOG_TIMESTAMP_DIGITS
+#define NRF_LOG_TIMESTAMP_DIGITS 8
+#endif
+
+// <e> NRF_LOG_BACKEND_SERIAL_USES_UART - If enabled data is printed over UART
+//==========================================================
+#ifndef NRF_LOG_BACKEND_SERIAL_USES_UART
+#define NRF_LOG_BACKEND_SERIAL_USES_UART 1
+#endif
+#if  NRF_LOG_BACKEND_SERIAL_USES_UART
+// <o> NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE  - Default Baudrate
+ 
+// <323584=> 1200 baud 
+// <643072=> 2400 baud 
+// <1290240=> 4800 baud 
+// <2576384=> 9600 baud 
+// <3862528=> 14400 baud 
+// <5152768=> 19200 baud 
+// <7716864=> 28800 baud 
+// <10289152=> 38400 baud 
+// <15400960=> 57600 baud 
+// <20615168=> 76800 baud 
+// <30801920=> 115200 baud 
+// <61865984=> 230400 baud 
+// <67108864=> 250000 baud 
+// <121634816=> 460800 baud 
+// <251658240=> 921600 baud 
+// <268435456=> 57600 baud 
+
+#ifndef NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE
+#define NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE 30801920
+#endif
+
+// <o> NRF_LOG_BACKEND_SERIAL_UART_TX_PIN - UART TX pin 
+#ifndef NRF_LOG_BACKEND_SERIAL_UART_TX_PIN
+#define NRF_LOG_BACKEND_SERIAL_UART_TX_PIN 6
+#endif
+
+// <o> NRF_LOG_BACKEND_SERIAL_UART_RX_PIN - UART RX pin 
+#ifndef NRF_LOG_BACKEND_SERIAL_UART_RX_PIN
+#define NRF_LOG_BACKEND_SERIAL_UART_RX_PIN 8
+#endif
+
+// <o> NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN - UART RTS pin 
+#ifndef NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN
+#define NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN 5
+#endif
+
+// <o> NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN - UART CTS pin 
+#ifndef NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN
+#define NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN 7
+#endif
+
+// <o> NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL  - Hardware Flow Control
+ 
+// <0=> Disabled 
+// <1=> Enabled 
+
+#ifndef NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL
+#define NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL 0
+#endif
+
+// <o> NRF_LOG_BACKEND_UART_INSTANCE  - UART instance used
+ 
+// <0=> 0 
+
+#ifndef NRF_LOG_BACKEND_UART_INSTANCE
+#define NRF_LOG_BACKEND_UART_INSTANCE 0
+#endif
+
+#endif //NRF_LOG_BACKEND_SERIAL_USES_UART
+// </e>
+
+// <e> NRF_LOG_BACKEND_SERIAL_USES_RTT - If enabled data is printed using RTT
+//==========================================================
+#ifndef NRF_LOG_BACKEND_SERIAL_USES_RTT
+#define NRF_LOG_BACKEND_SERIAL_USES_RTT 0
+#endif
+#if  NRF_LOG_BACKEND_SERIAL_USES_RTT
+// <o> NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE - RTT output buffer size. 
+// <i> Should be equal or bigger than \ref NRF_LOG_BACKEND_MAX_STRING_LENGTH.
+// <i> This value is used in Segger RTT configuration to set the buffer size
+// <i> if it is bigger than default RTT buffer size.
+
+#ifndef NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE
+#define NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE 512
+#endif
+
+#endif //NRF_LOG_BACKEND_SERIAL_USES_RTT
+// </e>
+
+// </h> 
+//==========================================================
+
+// </h> 
+//==========================================================
+
+// <h> nRF_Segger_RTT 
+
+//==========================================================
+// <h> segger_rtt - SEGGER RTT
+
+//==========================================================
+// <o> SEGGER_RTT_CONFIG_BUFFER_SIZE_UP - Size of upstream buffer. 
+// <i> Note that either @ref NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE
+// <i> or this value is actually used. It depends on which one is bigger.
+
+#ifndef SEGGER_RTT_CONFIG_BUFFER_SIZE_UP
+#define SEGGER_RTT_CONFIG_BUFFER_SIZE_UP 64
+#endif
+
+// <o> SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS - Size of upstream buffer. 
+#ifndef SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS
+#define SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS 2
+#endif
+
+// <o> SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN - Size of upstream buffer. 
+#ifndef SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN
+#define SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN 16
+#endif
+
+// <o> SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS - Size of upstream buffer. 
+#ifndef SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS
+#define SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS 2
+#endif
+
+// <o> SEGGER_RTT_CONFIG_DEFAULT_MODE  - RTT behavior if the buffer is full.
+ 
+
+// <i> The following modes are supported:
+// <i> - SKIP  - Do not block, output nothing.
+// <i> - TRIM  - Do not block, output as much as fits.
+// <i> - BLOCK - Wait until there is space in the buffer.
+// <0=> SKIP 
+// <1=> TRIM 
+// <2=> BLOCK_IF_FIFO_FULL 
+
+#ifndef SEGGER_RTT_CONFIG_DEFAULT_MODE
+#define SEGGER_RTT_CONFIG_DEFAULT_MODE 0
+#endif
+
+// </h> 
+//==========================================================
+
+// </h> 
+//==========================================================
+
+// <<< end of configuration section >>>
+#endif //SDK_CONFIG_H
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,689 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+  @addtogroup BLE_COMMON BLE SoftDevice Common
+  @{
+  @defgroup ble_api Events, type definitions and API calls
+  @{
+
+  @brief Module independent events, type definitions and API calls for the BLE SoftDevice.
+
+ */
+
+#ifndef BLE_H__
+#define BLE_H__
+
+#include "ble_ranges.h"
+#include "ble_types.h"
+#include "ble_gap.h"
+#include "ble_l2cap.h"
+#include "ble_gatt.h"
+#include "ble_gattc.h"
+#include "ble_gatts.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup BLE_COMMON_ENUMERATIONS Enumerations
+ * @{ */
+
+/**
+ * @brief Common API SVC numbers.
+ */
+enum BLE_COMMON_SVCS
+{
+  SD_BLE_ENABLE = BLE_SVC_BASE,         /**< Enable and initialize the BLE stack */
+  SD_BLE_EVT_GET,                       /**< Get an event from the pending events queue. */
+  SD_BLE_TX_PACKET_COUNT_GET,           /**< Get the total number of available application transmission packets for a particular connection. */
+  SD_BLE_UUID_VS_ADD,                   /**< Add a Vendor Specific UUID. */
+  SD_BLE_UUID_DECODE,                   /**< Decode UUID bytes. */
+  SD_BLE_UUID_ENCODE,                   /**< Encode UUID bytes. */
+  SD_BLE_VERSION_GET,                   /**< Get the local version information (company id, Link Layer Version, Link Layer Subversion). */
+  SD_BLE_USER_MEM_REPLY,                /**< User Memory Reply. */
+  SD_BLE_OPT_SET,                       /**< Set a BLE option. */
+  SD_BLE_OPT_GET,                       /**< Get a BLE option. */
+};
+
+  /**
+   * @brief BLE Module Independent Event IDs.
+   */
+enum BLE_COMMON_EVTS
+{
+  BLE_EVT_TX_COMPLETE  = BLE_EVT_BASE,  /**< Transmission Complete. @ref ble_evt_tx_complete_t */
+  BLE_EVT_USER_MEM_REQUEST,             /**< User Memory request. @ref ble_evt_user_mem_request_t */
+  BLE_EVT_USER_MEM_RELEASE,             /**< User Memory release. @ref ble_evt_user_mem_release_t */
+  BLE_EVT_DATA_LENGTH_CHANGED           /**< Link layer PDU length changed. @ref ble_evt_data_length_changed_t. */
+};
+
+/**@brief BLE connection bandwidth types.
+ * Bandwidth types supported by the SoftDevice. The bandwidth type dictates the maximum number of full length packets per connection interval.
+ */
+enum BLE_CONN_BWS
+{
+  BLE_CONN_BW_INVALID = 0,              /**< Invalid connection bandwidth. */
+  BLE_CONN_BW_LOW,                      /**< Low connection bandwidth. */
+  BLE_CONN_BW_MID,                      /**< Medium connection bandwidth. */
+  BLE_CONN_BW_HIGH                      /**< High connection bandwidth. */
+};
+
+/**@brief Common Option IDs.
+ * IDs that uniquely identify a common option.
+ */
+enum BLE_COMMON_OPTS
+{
+  BLE_COMMON_OPT_CONN_BW = BLE_OPT_BASE,     /**< Bandwidth configuration @ref ble_common_opt_conn_bw_t */
+  BLE_COMMON_OPT_PA_LNA,                     /**< PA and LNA options */
+  BLE_COMMON_OPT_CONN_EVT_EXT,               /**< Extended connection events option */
+};
+
+/** @} */
+
+/** @addtogroup BLE_COMMON_DEFINES Defines
+ * @{ */
+
+/** @brief  Required pointer alignment for BLE Events.
+*/
+#define BLE_EVT_PTR_ALIGNMENT    4
+
+/** @brief  Leaves the maximum of the two arguments.
+*/
+#define BLE_MAX(a, b) ((a) < (b) ? (b) : (a))
+
+/** @brief  Maximum possible length for BLE Events.
+ * @note Value of @ref ble_gatt_enable_params_t::att_mtu shall be used as a parameter.
+ * If that value is set to 0 then @ref BLE_GATT_MTU_SIZE_DEFAULT must be used instead.
+*/
+#define BLE_EVT_LEN_MAX(ATT_MTU) (BLE_MAX( \
+  sizeof(ble_evt_t), \
+  BLE_MAX( \
+    offsetof(ble_evt_t, evt.gattc_evt.params.rel_disc_rsp.includes) + ((ATT_MTU) - 2) / 6 * sizeof(ble_gattc_include_t), \
+    offsetof(ble_evt_t, evt.gattc_evt.params.attr_info_disc_rsp.info.attr_info16) + ((ATT_MTU) - 2) / 4 * sizeof(ble_gattc_attr_info16_t) \
+  ) \
+))
+
+/** @defgroup BLE_USER_MEM_TYPES User Memory Types
+ * @{ */
+#define BLE_USER_MEM_TYPE_INVALID               0x00  /**< Invalid User Memory Types. */
+#define BLE_USER_MEM_TYPE_GATTS_QUEUED_WRITES   0x01  /**< User Memory for GATTS queued writes. */
+/** @} */
+
+/** @defgroup BLE_UUID_VS_COUNTS Vendor Specific UUID counts
+ * @{
+ */
+#define BLE_UUID_VS_COUNT_MIN         1    /**< Minimum VS UUID count. */
+#define BLE_UUID_VS_COUNT_DEFAULT     0    /**< Use the default VS UUID count (10 for this version of the SoftDevice). */
+/** @} */
+
+/** @} */
+
+/** @addtogroup BLE_COMMON_STRUCTURES Structures
+ * @{ */
+
+/**@brief User Memory Block. */
+typedef struct
+{
+  uint8_t          *p_mem;      /**< Pointer to the start of the user memory block. */
+  uint16_t          len;        /**< Length in bytes of the user memory block. */
+} ble_user_mem_block_t;
+
+/**
+ * @brief Event structure for @ref BLE_EVT_TX_COMPLETE.
+ */
+typedef struct
+{
+  uint8_t count;                        /**< Number of packets transmitted. */
+} ble_evt_tx_complete_t;
+
+/**@brief Event structure for @ref BLE_EVT_USER_MEM_REQUEST. */
+typedef struct
+{
+  uint8_t                     type;     /**< User memory type, see @ref BLE_USER_MEM_TYPES. */
+} ble_evt_user_mem_request_t;
+
+/**@brief Event structure for @ref BLE_EVT_USER_MEM_RELEASE. */
+typedef struct
+{
+  uint8_t                     type;       /**< User memory type, see @ref BLE_USER_MEM_TYPES. */
+  ble_user_mem_block_t        mem_block;  /**< User memory block */
+} ble_evt_user_mem_release_t;
+
+/**@brief Event structure for @ref BLE_EVT_DATA_LENGTH_CHANGED. */
+typedef struct
+{
+  uint16_t max_tx_octets;                 /**< The maximum number of payload octets in a Link Layer Data Channel PDU that the local Controller will send. Range: 27-251 */
+  uint16_t max_tx_time;                   /**< The maximum time (in microseconds) that the local Controller will take to send a Link Layer Data Channel PDU. Range: 328-2120  */
+  uint16_t max_rx_octets;                 /**< The maximum number of payload octets in a Link Layer Data Channel PDU that the local controller expects to receive. Range: 27-251 */
+  uint16_t max_rx_time;                   /**< The maximum time (in microseconds) that the local Controller expects to take to receive a Link Layer Data Channel PDU. Range: 328-2120 */
+} ble_evt_data_length_changed_t;
+
+/**@brief Event structure for events not associated with a specific function module. */
+typedef struct
+{
+  uint16_t conn_handle;                                 /**< Connection Handle on which this event occurred. */
+  union
+  {
+    ble_evt_tx_complete_t           tx_complete;         /**< Transmission Complete. */
+    ble_evt_user_mem_request_t      user_mem_request;    /**< User Memory Request Event Parameters. */
+    ble_evt_user_mem_release_t      user_mem_release;    /**< User Memory Release Event Parameters. */
+    ble_evt_data_length_changed_t   data_length_changed; /**< Data Length Changed Event Parameters. */
+  } params;                                              /**< Event parameter union. */
+} ble_common_evt_t;
+
+/**@brief BLE Event header. */
+typedef struct
+{
+  uint16_t evt_id;                /**< Value from a BLE_<module>_EVT series. */
+  uint16_t evt_len;               /**< Length in octets including this header. */
+} ble_evt_hdr_t;
+
+/**@brief Common BLE Event type, wrapping the module specific event reports. */
+typedef struct
+{
+  ble_evt_hdr_t header;           /**< Event header. */
+  union
+  {
+    ble_common_evt_t  common_evt; /**< Common Event, evt_id in BLE_EVT_* series. */
+    ble_gap_evt_t     gap_evt;    /**< GAP originated event, evt_id in BLE_GAP_EVT_* series. */
+    ble_l2cap_evt_t   l2cap_evt;  /**< L2CAP originated event, evt_id in BLE_L2CAP_EVT* series. */
+    ble_gattc_evt_t   gattc_evt;  /**< GATT client originated event, evt_id in BLE_GATTC_EVT* series. */
+    ble_gatts_evt_t   gatts_evt;  /**< GATT server originated event, evt_id in BLE_GATTS_EVT* series. */
+  } evt;                          /**< Event union. */
+} ble_evt_t;
+
+
+/**
+ * @brief Version Information.
+ */
+typedef struct
+{
+  uint8_t   version_number;    /**< Link Layer Version number for BT 4.1 spec is 7 (https://www.bluetooth.org/en-us/specification/assigned-numbers/link-layer). */
+  uint16_t  company_id;        /**< Company ID, Nordic Semiconductor's company ID is 89 (0x0059) (https://www.bluetooth.org/apps/content/Default.aspx?doc_id=49708). */
+  uint16_t  subversion_number; /**< Link Layer Sub Version number, corresponds to the SoftDevice Config ID or Firmware ID (FWID). */
+} ble_version_t;
+
+/**
+ * @brief Configuration parameters for the PA and LNA.
+ */
+typedef struct
+{
+     uint8_t enable :1;      /**< Enable toggling for this amplifier */
+     uint8_t active_high :1; /**< Set the pin to be active high */
+     uint8_t gpio_pin :6;    /**< The GPIO pin to toggle for this amplifier */
+} ble_pa_lna_cfg_t;
+
+/**
+ * @brief PA & LNA GPIO toggle configuration
+ *
+ * This option configures the SoftDevice to toggle pins when the radio is active for use with a power amplifier and/or
+ * a low noise amplifier.
+ *
+ * Toggling the pins is achieved by using two PPI channels and a GPIOTE channel. The hardware channel IDs are provided
+ * by the application and should be regarded as reserved as long as any PA/LNA toggling is enabled.
+ *
+ * @note  @ref sd_ble_opt_get is not supported for this option.
+ * @note  This feature is only supported for nRF52, on nRF51 @ref NRF_ERROR_NOT_SUPPORTED will always be returned.
+ * @note  Setting this option while the radio is in use (i.e. any of the roles are active) may have undefined consequences
+ * and must be avoided by the application.
+ */
+typedef struct
+{
+   ble_pa_lna_cfg_t pa_cfg;   /**< Power Amplifier configuration */
+   ble_pa_lna_cfg_t lna_cfg;  /**< Low Noise Amplifier configuration */
+
+   uint8_t ppi_ch_id_set;     /**< PPI channel used for radio pin setting */
+   uint8_t ppi_ch_id_clr;     /**< PPI channel used for radio pin clearing */
+   uint8_t gpiote_ch_id;      /**< GPIOTE channel used for radio pin toggling */
+} ble_common_opt_pa_lna_t;
+
+/**
+ * @brief BLE connection bandwidth configuration parameters
+ */
+typedef struct
+{
+  uint8_t conn_bw_tx;   /**< Connection bandwidth configuration for transmission, see @ref BLE_CONN_BWS.*/
+  uint8_t conn_bw_rx;   /**< Connection bandwidth configuration for reception, see @ref BLE_CONN_BWS.*/
+} ble_conn_bw_t;
+
+/**@brief BLE connection specific bandwidth configuration parameters.
+ *
+ * This can be used with @ref sd_ble_opt_set to set the bandwidth configuration to be used when creating connections.
+ *
+ * Call @ref sd_ble_opt_set with this option prior to calling @ref sd_ble_gap_adv_start or @ref sd_ble_gap_connect.
+ *
+ * The bandwidth configurations set via @ref sd_ble_opt_set are maintained separately for central and peripheral
+ * connections. The given configurations are used for all future connections of the role indicated in this structure
+ * unless they are changed by subsequent @ref sd_ble_opt_set calls.
+ *
+ * @note When this option is not used, the SoftDevice will use the default options:
+ * - @ref BLE_CONN_BW_HIGH for @ref BLE_GAP_ROLE_PERIPH connections (both transmission and reception).
+ * - @ref BLE_CONN_BW_MID for @ref BLE_GAP_ROLE_CENTRAL connections (both transmisison and reception).
+ * This option allows the application to selectively override these defaults for each role.
+ *
+ * @note The global memory pool configuration can be set with the @ref ble_conn_bw_counts_t configuration parameter, which
+ * is provided to @ref sd_ble_enable.
+ *
+ * @note @ref sd_ble_opt_get is not supported for this option.
+ * @note Please refer to SoftDevice Specification for more information on bandwidth configuration.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_COMMON_CONF_BW}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Set successfully.
+ * @retval ::BLE_ERROR_INVALID_ROLE The role is invalid.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid bandwidth configuration parameters.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED If the combination of role and bandwidth configuration is not supported.
+ */
+typedef struct
+{
+  uint8_t            role;     /**< BLE role of the connection, see @ref BLE_GAP_ROLES. */
+  ble_conn_bw_t      conn_bw;  /**< Bandwidth configuration parameters. */
+} ble_common_opt_conn_bw_t;
+
+/**
+ * @brief Configuration of extended BLE connection events.
+ *
+ * When enabled the SoftDevice will dynamically extend the connection event when possible.
+ *
+ * The connection event length is controlled by the bandwidth configuration as set by @ref ble_common_opt_conn_bw_t.
+ * The connection event can be extended if there is time to send another packet pair before the start of the next connection interval,
+ * and if there are no conflicts with other BLE roles requesting radio time.
+ *
+ * @note @ref sd_ble_opt_get is not supported for this option.
+ */
+typedef struct
+{
+   uint8_t enable : 1; /**< Enable extended BLE connection events, disabled by default. */
+} ble_common_opt_conn_evt_ext_t;
+
+/**@brief Option structure for common options. */
+typedef union
+{
+  ble_common_opt_conn_bw_t      conn_bw;       /**< Parameters for the connection bandwidth option. */
+  ble_common_opt_pa_lna_t       pa_lna;        /**< Parameters for controlling PA and LNA pin toggling. */
+  ble_common_opt_conn_evt_ext_t conn_evt_ext;  /**< Parameters for enabling extended connection events. */
+} ble_common_opt_t;
+
+/**@brief Common BLE Option type, wrapping the module specific options. */
+typedef union
+{
+  ble_common_opt_t  common_opt;         /**< COMMON options, opt_id in @ref BLE_COMMON_OPTS series. */
+  ble_gap_opt_t     gap_opt;            /**< GAP option, opt_id in @ref BLE_GAP_OPTS series. */
+} ble_opt_t;
+
+/**
+ * @brief BLE bandwidth count parameters
+ *
+ * These parameters are used to configure the memory pools allocated within the SoftDevice for application packets
+ * (both transmission and reception) for all connections.
+ *
+ * @note The sum of all three counts must add up to the sum of @ref ble_gap_enable_params_t::central_conn_count and
+ * @ref ble_gap_enable_params_t::periph_conn_count in @ref ble_gap_enable_params_t.
+ */
+typedef struct {
+  uint8_t high_count;   /**< Total number of high bandwidth TX or RX memory pools available to the application at runtime for all active connections. */
+  uint8_t mid_count;    /**< Total number of medium bandwidth TX or RX memory pools available to the application at runtime for all active connections. */
+  uint8_t low_count;    /**< Total number of low bandwidth TX or RX memory pools available to the application at runtime for all active connections. */
+} ble_conn_bw_count_t;
+
+/**
+ * @brief BLE bandwidth global memory pool configuration parameters
+ *
+ * These configuration parameters are used to set the amount of memory dedicated to application packets for
+ * all connections. The application should specify the most demanding configuration for the intended use.
+ *
+ * Please refer to the SoftDevice Specification for more information on bandwidth configuration.
+ *
+ * @note Each connection created at runtime requires both a TX and an RX memory pool. By the use of these configuration
+ * parameters, the application can decide the size and total number of the global memory pools that will be later
+ * available for connection creation.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_COMMON_CONF_BW}
+ * @endmscs
+ *
+ */
+typedef struct {
+  ble_conn_bw_count_t tx_counts;   /**< Global memory pool configuration for transmission.*/
+  ble_conn_bw_count_t rx_counts;   /**< Global memory pool configuration for reception.*/
+} ble_conn_bw_counts_t;
+
+/**
+ * @brief BLE Common Initialization parameters.
+ *
+ * @note If @ref p_conn_bw_counts is NULL the SoftDevice will assume default bandwidth configuration for all connections.
+ * To fit a custom bandwidth configuration requirement, the application developer may have to specify a custom memory
+ * pool configuration here. See @ref ble_common_opt_conn_bw_t for bandwidth configuration of individual connections.
+ * Please refer to the SoftDevice Specification for more information on bandwidth configuration.
+ */
+typedef struct
+{
+  uint16_t                  vs_uuid_count;     /**< Maximum number of 128-bit, Vendor Specific UUID bases to allocate. */
+  ble_conn_bw_counts_t      *p_conn_bw_counts; /**< Bandwidth configuration parameters or NULL for defaults. */
+} ble_common_enable_params_t;
+
+/**
+ * @brief BLE Initialization parameters.
+ */
+typedef struct
+{
+  ble_common_enable_params_t        common_enable_params;  /**< Common init parameters @ref ble_common_enable_params_t. */
+  ble_gap_enable_params_t           gap_enable_params;     /**< GAP init parameters @ref ble_gap_enable_params_t. */
+  ble_gatt_enable_params_t          gatt_enable_params;    /**< GATT init parameters @ref ble_gatt_enable_params_t. */
+  ble_gatts_enable_params_t         gatts_enable_params;   /**< GATTS init parameters @ref ble_gatts_enable_params_t. */
+} ble_enable_params_t;
+
+/** @} */
+
+/** @addtogroup BLE_COMMON_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Enable the BLE stack
+ *
+ * @param[in, out] p_ble_enable_params Pointer to ble_enable_params_t
+ * @param[in, out] p_app_ram_base      Pointer to a variable containing the start address of the application RAM region
+ * (APP_RAM_BASE). On return, this will contain the minimum start address of the application RAM region required by the
+ * SoftDevice for this configuration. Calling @ref sd_ble_enable() with *p_app_ram_base set to 0 can be used during
+ * development to find out how much memory a specific configuration will need.
+ *
+ * @note The memory requirement for a specific configuration will not increase between SoftDevices with the same major
+ * version number.
+ *
+ * @note At runtime the IC's RAM is split into 2 regions: The SoftDevice RAM region is located between 0x20000000 and
+ *       APP_RAM_BASE-1 and the application's RAM region is located between APP_RAM_BASE and the start of the call stack.
+ *
+ * @details This call initializes the BLE stack, no other BLE related function can be called before this one.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_COMMON_ENABLE}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS              The BLE stack has been initialized successfully.
+ * @retval ::NRF_ERROR_INVALID_STATE  The BLE stack had already been initialized and cannot be reinitialized.
+ * @retval ::NRF_ERROR_INVALID_ADDR   Invalid or not sufficiently aligned pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_LENGTH One or more of the following is true:
+ *                                    - The specified Attribute Table size is too small.
+ *                                      The minimum acceptable size is defined by @ref BLE_GATTS_ATTR_TAB_SIZE_MIN.
+ *                                    - The specified Attribute Table size is not a multiple of 4.
+ *                                    - The device name length is invalid (must be between 0 and @ref BLE_GAP_DEVNAME_MAX_LEN).
+ *                                    - The device name length is too long for the given Attribute Table.
+ * @retval ::NRF_ERROR_INVALID_PARAM  One or more of the following is true:
+ *                                    - Incorrectly configured VS UUID count.
+ *                                    - Invalid connection count parameters.
+ *                                    - Invalid device name location (vloc).
+ *                                    - Invalid device name security mode.
+ *                                    - Invalid maximum ATT_MTU size, see @ref ble_gatt_enable_params_t::att_mtu.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED  Device name security mode is not supported.
+ * @retval ::NRF_ERROR_NO_MEM         The amount of memory assigned to the SoftDevice by *p_app_ram_base is not
+ *                                    large enough to fit this configuration's memory requirement. Check *p_app_ram_base
+ *                                    and set the start address of the application RAM region accordingly.
+ * @retval ::NRF_ERROR_CONN_COUNT     The requested number of connections exceeds the maximum supported by the SoftDevice.
+ *                                    Please refer to the SoftDevice Specification for more information on role configuration.
+ */
+SVCALL(SD_BLE_ENABLE, uint32_t, sd_ble_enable(ble_enable_params_t * p_ble_enable_params, uint32_t * p_app_ram_base));
+
+/**@brief Get an event from the pending events queue.
+ *
+ * @param[out] p_dest Pointer to buffer to be filled in with an event, or NULL to retrieve the event length.
+ *                    This buffer <b>must be aligned to the extend defined by @ref BLE_EVT_PTR_ALIGNMENT</b>.
+ *                    The buffer should be interpreted as a @ref ble_evt_t struct.
+ * @param[in, out] p_len Pointer the length of the buffer, on return it is filled with the event length.
+ *
+ * @details This call allows the application to pull a BLE event from the BLE stack. The application is signaled that
+ * an event is available from the BLE stack by the triggering of the SD_EVT_IRQn interrupt.
+ * The application is free to choose whether to call this function from thread mode (main context) or directly from the
+ * Interrupt Service Routine that maps to SD_EVT_IRQn. In any case however, and because the BLE stack runs at a higher
+ * priority than the application, this function should be called in a loop (until @ref NRF_ERROR_NOT_FOUND is returned)
+ * every time SD_EVT_IRQn is raised to ensure that all available events are pulled from the BLE stack. Failure to do so
+ * could potentially leave events in the internal queue without the application being aware of this fact.
+ *
+ * Sizing the p_dest buffer is equally important, since the application needs to provide all the memory necessary for the event to
+ * be copied into application memory. If the buffer provided is not large enough to fit the entire contents of the event,
+ * @ref NRF_ERROR_DATA_SIZE will be returned and the application can then call again with a larger buffer size.
+ * The maximum possible event length is defined by @ref BLE_EVT_LEN_MAX. The application may also "peek" the event length
+ * by providing p_dest as a NULL pointer and inspecting the value of *p_len upon return:
+ *
+ *     \code
+ *     uint16_t len;
+ *     errcode = sd_ble_evt_get(NULL, &len);
+ *     \endcode
+ *
+ * @mscs
+ * @mmsc{@ref BLE_COMMON_IRQ_EVT_MSC}
+ * @mmsc{@ref BLE_COMMON_THREAD_EVT_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Event pulled and stored into the supplied buffer.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid or not sufficiently aligned pointer supplied.
+ * @retval ::NRF_ERROR_NOT_FOUND No events ready to be pulled.
+ * @retval ::NRF_ERROR_DATA_SIZE Event ready but could not fit into the supplied buffer.
+ */
+SVCALL(SD_BLE_EVT_GET, uint32_t, sd_ble_evt_get(uint8_t *p_dest, uint16_t *p_len));
+
+
+/**@brief Get the total number of available guaranteed application transmission packets for a particular connection.
+ *
+ * @details This call allows the application to obtain the total number of guaranteed application transmission packets
+ * available for a connection. Please note that this does not return the number of free packets, but rather the total
+ * amount of them for that particular connection. The application has two options to handle transmitting application packets:
+ * - Use a simple arithmetic calculation: after connection creation time the application should use this function to
+ * find out the total amount of guaranteed packets available to it and store it in a variable.
+ * Every time a packet is successfully queued for a transmission on this connection using any of the exposed functions in
+ * this  BLE API, the application should decrement that variable. Conversely, whenever a @ref BLE_EVT_TX_COMPLETE event
+ * with the conn_handle matching the particular connection is received by the application, it should retrieve the count
+ * field in such event and add that number to the same variable storing the number of available guaranteed packets. This
+ * mechanism allows the application to be aware at any time of the number of guaranteed application packets available for
+ * each of the active connections, and therefore it can know with certainty whether it is possible to send more data or
+ * it has to wait for a @ref BLE_EVT_TX_COMPLETE event before it proceeds.
+ * The application can still pursue transmissions when the number of guaranteed application packets available is smaller
+ * than or equal to zero, but successful queuing of the tranmsission is not guaranteed.
+ * - Choose to simply not keep track of available packets at all, and instead handle the @ref BLE_ERROR_NO_TX_PACKETS error
+ * by queueing the packet to be transmitted and try again as soon as a @ref BLE_EVT_TX_COMPLETE event arrives.
+ *
+ * The API functions that <b>may</b> consume an application packet depending on the parameters supplied to them can be found below:
+ * - @ref sd_ble_gattc_write (write without response only)
+ * - @ref sd_ble_gatts_hvx (notifications only)
+ * - @ref sd_ble_l2cap_tx (all packets)
+ *
+ * @param[in]  conn_handle Connection handle.
+ * @param[out] p_count Pointer to a uint8_t which will contain the number of application transmission packets upon
+ *                     successful return.
+ * @mscs
+ * @mmsc{@ref BLE_COMMON_APP_BUFF_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Number of application transmission packets retrieved successfully.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ */
+SVCALL(SD_BLE_TX_PACKET_COUNT_GET, uint32_t, sd_ble_tx_packet_count_get(uint16_t conn_handle, uint8_t *p_count));
+
+
+/**@brief Add a Vendor Specific base UUID.
+ *
+ * @details This call enables the application to add a vendor specific base UUID to the BLE stack's table, for later
+ * use with all other modules and APIs. This then allows the application to use the shorter, 24-bit @ref ble_uuid_t
+ * format when dealing with both 16-bit and 128-bit UUIDs without having to check for lengths and having split code
+ * paths. This is accomplished by extending the grouping mechanism that the Bluetooth SIG standard base UUID uses
+ * for all other 128-bit UUIDs. The type field in the @ref ble_uuid_t structure is an index (relative to
+ * @ref BLE_UUID_TYPE_VENDOR_BEGIN) to the table populated by multiple calls to this function, and the uuid field
+ * in the same structure contains the 2 bytes at indices 12 and 13. The number of possible 128-bit UUIDs available to
+ * the application is therefore the number of Vendor Specific UUIDs added with the help of this function times 65536,
+ * although restricted to modifying bytes 12 and 13 for each of the entries in the supplied array.
+ *
+ * @note Bytes 12 and 13 of the provided UUID will not be used internally, since those are always replaced by
+ * the 16-bit uuid field in @ref ble_uuid_t.
+ *
+ * @note If a UUID is already present in the BLE stack's internal table, the corresponding index will be returned in
+ * p_uuid_type along with an NRF_SUCCESS error code.
+ *
+ * @param[in]  p_vs_uuid    Pointer to a 16-octet (128-bit) little endian Vendor Specific UUID disregarding
+ *                          bytes 12 and 13.
+ * @param[out] p_uuid_type  Pointer to a uint8_t where the type field in @ref ble_uuid_t corresponding to this UUID will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully added the Vendor Specific UUID.
+ * @retval ::NRF_ERROR_INVALID_ADDR If p_vs_uuid or p_uuid_type is NULL or invalid.
+ * @retval ::NRF_ERROR_NO_MEM If there are no more free slots for VS UUIDs.
+ */
+SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_vs_uuid, uint8_t *p_uuid_type));
+
+
+/** @brief Decode little endian raw UUID bytes (16-bit or 128-bit) into a 24 bit @ref ble_uuid_t structure.
+ *
+ * @details The raw UUID bytes excluding bytes 12 and 13 (i.e. bytes 0-11 and 14-15) of p_uuid_le are compared
+ * to the corresponding ones in each entry of the table of vendor specific UUIDs populated with @ref sd_ble_uuid_vs_add
+ * to look for a match. If there is such a match, bytes 12 and 13 are returned as p_uuid->uuid and the index
+ * relative to @ref BLE_UUID_TYPE_VENDOR_BEGIN as p_uuid->type.
+ *
+ * @note If the UUID length supplied is 2, then the type set by this call will always be @ref BLE_UUID_TYPE_BLE.
+ *
+ * @param[in]   uuid_le_len Length in bytes of the buffer pointed to by p_uuid_le (must be 2 or 16 bytes).
+ * @param[in]   p_uuid_le   Pointer pointing to little endian raw UUID bytes.
+ * @param[out]  p_uuid      Pointer to a @ref ble_uuid_t structure to be filled in.
+ *
+ * @retval ::NRF_SUCCESS Successfully decoded into the @ref ble_uuid_t structure.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_LENGTH Invalid UUID length.
+ * @retval ::NRF_ERROR_NOT_FOUND For a 128-bit UUID, no match in the populated table of UUIDs.
+ */
+SVCALL(SD_BLE_UUID_DECODE, uint32_t, sd_ble_uuid_decode(uint8_t uuid_le_len, uint8_t const *p_uuid_le, ble_uuid_t *p_uuid));
+
+
+/** @brief Encode a @ref ble_uuid_t structure into little endian raw UUID bytes (16-bit or 128-bit).
+ *
+ * @note The pointer to the destination buffer p_uuid_le may be NULL, in which case only the validity and size of p_uuid is computed.
+ *
+ * @param[in]   p_uuid        Pointer to a @ref ble_uuid_t structure that will be encoded into bytes.
+ * @param[out]  p_uuid_le_len Pointer to a uint8_t that will be filled with the encoded length (2 or 16 bytes).
+ * @param[out]  p_uuid_le     Pointer to a buffer where the little endian raw UUID bytes (2 or 16) will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully encoded into the buffer.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid UUID type.
+ */
+SVCALL(SD_BLE_UUID_ENCODE, uint32_t, sd_ble_uuid_encode(ble_uuid_t const *p_uuid, uint8_t *p_uuid_le_len, uint8_t *p_uuid_le));
+
+
+/**@brief Get Version Information.
+ *
+ * @details This call allows the application to get the BLE stack version information.
+ *
+ * @param[out] p_version Pointer to a ble_version_t structure to be filled in.
+ *
+ * @retval ::NRF_SUCCESS  Version information stored successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_BUSY The BLE stack is busy (typically doing a locally-initiated disconnection procedure).
+ */
+SVCALL(SD_BLE_VERSION_GET, uint32_t, sd_ble_version_get(ble_version_t *p_version));
+
+
+/**@brief Provide a user memory block.
+ *
+ * @note This call can only be used as a response to a @ref BLE_EVT_USER_MEM_REQUEST event issued to the application.
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in,out] p_block Pointer to a user memory block structure.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_PEER_CANCEL_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_AUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_AUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_NOAUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Successfully queued a response to the peer.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection state or no execute write request pending.
+ * @retval ::NRF_ERROR_BUSY The BLE stack is busy. Retry at later time.
+ */
+SVCALL(SD_BLE_USER_MEM_REPLY, uint32_t, sd_ble_user_mem_reply(uint16_t conn_handle, ble_user_mem_block_t const *p_block));
+
+/**@brief Set a BLE option.
+ *
+ * @details This call allows the application to set the value of an option.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_BONDING_STATIC_PK_MSC}
+ * @mmsc{@ref BLE_COMMON_CONF_BW}
+ * @endmscs
+ *
+ * @param[in] opt_id Option ID, see @ref BLE_COMMON_OPTS and @ref BLE_GAP_OPTS.
+ * @param[in] p_opt Pointer to a ble_opt_t structure containing the option value.
+ *
+ * @retval ::NRF_SUCCESS  Option set successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints.
+ * @retval ::NRF_ERROR_INVALID_STATE Unable to set the parameter at this time.
+ * @retval ::NRF_ERROR_BUSY The BLE stack is busy or the previous procedure has not completed.
+ */
+SVCALL(SD_BLE_OPT_SET, uint32_t, sd_ble_opt_set(uint32_t opt_id, ble_opt_t const *p_opt));
+
+
+/**@brief Get a BLE option.
+ *
+ * @details This call allows the application to retrieve the value of an option.
+ *
+ * @param[in] opt_id Option ID, see @ref BLE_COMMON_OPTS and @ref BLE_GAP_OPTS.
+ * @param[out] p_opt Pointer to a ble_opt_t structure to be filled in.
+ *
+ * @retval ::NRF_SUCCESS  Option retrieved successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints.
+ * @retval ::NRF_ERROR_INVALID_STATE Unable to retrieve the parameter at this time.
+ * @retval ::NRF_ERROR_BUSY The BLE stack is busy or the previous procedure has not completed.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED This option is not supported.
+ *
+ */
+SVCALL(SD_BLE_OPT_GET, uint32_t, sd_ble_opt_get(uint32_t opt_id, ble_opt_t *p_opt));
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+#endif /* BLE_H__ */
+
+/**
+  @}
+  @}
+*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_err.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,93 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+  @addtogroup BLE_COMMON
+  @{
+  @addtogroup  nrf_error
+  @{
+    @ingroup BLE_COMMON
+  @}
+
+  @defgroup ble_err General error codes
+  @{
+
+  @brief General error code definitions for the BLE API.
+
+  @ingroup BLE_COMMON
+*/
+#ifndef NRF_BLE_ERR_H__
+#define NRF_BLE_ERR_H__
+
+#include "nrf_error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* @defgroup BLE_ERRORS Error Codes
+ * @{ */
+#define BLE_ERROR_NOT_ENABLED            (NRF_ERROR_STK_BASE_NUM+0x001) /**< @ref sd_ble_enable has not been called. */
+#define BLE_ERROR_INVALID_CONN_HANDLE    (NRF_ERROR_STK_BASE_NUM+0x002) /**< Invalid connection handle. */
+#define BLE_ERROR_INVALID_ATTR_HANDLE    (NRF_ERROR_STK_BASE_NUM+0x003) /**< Invalid attribute handle. */
+#define BLE_ERROR_NO_TX_PACKETS          (NRF_ERROR_STK_BASE_NUM+0x004) /**< Not enough application packets available on this connection. */
+#define BLE_ERROR_INVALID_ROLE           (NRF_ERROR_STK_BASE_NUM+0x005) /**< Invalid role. */
+#define BLE_ERROR_BLOCKED_BY_OTHER_LINKS (NRF_ERROR_STK_BASE_NUM+0x006) /**< The attempt to change link settings failed due to the scheduling of other links. */
+/** @} */
+
+
+/** @defgroup BLE_ERROR_SUBRANGES Module specific error code subranges
+ *  @brief Assignment of subranges for module specific error codes.
+ *  @note For specific error codes, see ble_<module>.h or ble_error_<module>.h.
+ * @{ */
+#define NRF_L2CAP_ERR_BASE             (NRF_ERROR_STK_BASE_NUM+0x100) /**< L2CAP specific errors. */
+#define NRF_GAP_ERR_BASE               (NRF_ERROR_STK_BASE_NUM+0x200) /**< GAP specific errors. */
+#define NRF_GATTC_ERR_BASE             (NRF_ERROR_STK_BASE_NUM+0x300) /**< GATT client specific errors. */
+#define NRF_GATTS_ERR_BASE             (NRF_ERROR_STK_BASE_NUM+0x400) /**< GATT server specific errors. */
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+
+/**
+  @}
+  @}
+*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_gap.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,2027 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+  @addtogroup BLE_GAP Generic Access Profile (GAP)
+  @{
+  @brief Definitions and prototypes for the GAP interface.
+ */
+
+#ifndef BLE_GAP_H__
+#define BLE_GAP_H__
+
+#include "ble_types.h"
+#include "ble_ranges.h"
+#include "nrf_svc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@addtogroup BLE_GAP_ENUMERATIONS Enumerations
+ * @{ */
+
+/**@brief GAP API SVC numbers.
+ */
+enum BLE_GAP_SVCS
+{
+  SD_BLE_GAP_ADDR_SET = BLE_GAP_SVC_BASE,       /**< Set own Bluetooth Address. */
+  SD_BLE_GAP_ADDR_GET,                          /**< Get own Bluetooth Address. */
+  SD_BLE_GAP_WHITELIST_SET,                     /**< Set active whitelist. */
+  SD_BLE_GAP_DEVICE_IDENTITIES_SET,             /**< Set device identity list. */
+  SD_BLE_GAP_PRIVACY_SET,                       /**< Set Privacy settings*/
+  SD_BLE_GAP_PRIVACY_GET,                       /**< Get Privacy settings*/
+  SD_BLE_GAP_ADV_DATA_SET,                      /**< Set Advertising Data. */
+  SD_BLE_GAP_ADV_START,                         /**< Start Advertising. */
+  SD_BLE_GAP_ADV_STOP,                          /**< Stop Advertising. */
+  SD_BLE_GAP_CONN_PARAM_UPDATE,                 /**< Connection Parameter Update. */
+  SD_BLE_GAP_DISCONNECT,                        /**< Disconnect. */
+  SD_BLE_GAP_TX_POWER_SET,                      /**< Set TX Power. */
+  SD_BLE_GAP_APPEARANCE_SET,                    /**< Set Appearance. */
+  SD_BLE_GAP_APPEARANCE_GET,                    /**< Get Appearance. */
+  SD_BLE_GAP_PPCP_SET,                          /**< Set PPCP. */
+  SD_BLE_GAP_PPCP_GET,                          /**< Get PPCP. */
+  SD_BLE_GAP_DEVICE_NAME_SET,                   /**< Set Device Name. */
+  SD_BLE_GAP_DEVICE_NAME_GET,                   /**< Get Device Name. */
+  SD_BLE_GAP_AUTHENTICATE,                      /**< Initiate Pairing/Bonding. */
+  SD_BLE_GAP_SEC_PARAMS_REPLY,                  /**< Reply with Security Parameters. */
+  SD_BLE_GAP_AUTH_KEY_REPLY,                    /**< Reply with an authentication key. */
+  SD_BLE_GAP_LESC_DHKEY_REPLY,                  /**< Reply with an LE Secure Connections DHKey. */
+  SD_BLE_GAP_KEYPRESS_NOTIFY,                   /**< Notify of a keypress during an authentication procedure. */
+  SD_BLE_GAP_LESC_OOB_DATA_GET,                 /**< Get the local LE Secure Connections OOB data. */
+  SD_BLE_GAP_LESC_OOB_DATA_SET,                 /**< Set the remote LE Secure Connections OOB data. */
+  SD_BLE_GAP_ENCRYPT,                           /**< Initiate encryption procedure. */
+  SD_BLE_GAP_SEC_INFO_REPLY,                    /**< Reply with Security Information. */
+  SD_BLE_GAP_CONN_SEC_GET,                      /**< Obtain connection security level. */
+  SD_BLE_GAP_RSSI_START,                        /**< Start reporting of changes in RSSI. */
+  SD_BLE_GAP_RSSI_STOP,                         /**< Stop reporting of changes in RSSI. */
+  SD_BLE_GAP_SCAN_START,                        /**< Start Scanning. */
+  SD_BLE_GAP_SCAN_STOP,                         /**< Stop Scanning. */
+  SD_BLE_GAP_CONNECT,                           /**< Connect. */
+  SD_BLE_GAP_CONNECT_CANCEL,                    /**< Cancel ongoing connection procedure. */
+  SD_BLE_GAP_RSSI_GET,                          /**< Get the last RSSI sample. */
+  SD_BLE_GAP_PHY_REQUEST,                       /**< Initiate PHY Update procedure. */
+};
+
+/**@brief GAP Event IDs.
+ * IDs that uniquely identify an event coming from the stack to the application.
+ */
+enum BLE_GAP_EVTS
+{
+  BLE_GAP_EVT_CONNECTED  = BLE_GAP_EVT_BASE,    /**< Connection established.                         \n See @ref ble_gap_evt_connected_t.            */
+  BLE_GAP_EVT_DISCONNECTED,                     /**< Disconnected from peer.                         \n See @ref ble_gap_evt_disconnected_t.         */
+  BLE_GAP_EVT_CONN_PARAM_UPDATE,                /**< Connection Parameters updated.                  \n See @ref ble_gap_evt_conn_param_update_t.    */
+  BLE_GAP_EVT_SEC_PARAMS_REQUEST,               /**< Request to provide security parameters.         \n Reply with @ref sd_ble_gap_sec_params_reply.  \n See @ref ble_gap_evt_sec_params_request_t. */
+  BLE_GAP_EVT_SEC_INFO_REQUEST,                 /**< Request to provide security information.        \n Reply with @ref sd_ble_gap_sec_info_reply.    \n See @ref ble_gap_evt_sec_info_request_t.   */
+  BLE_GAP_EVT_PASSKEY_DISPLAY,                  /**< Request to display a passkey to the user.       \n In LESC Numeric Comparison, reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_passkey_display_t. */
+  BLE_GAP_EVT_KEY_PRESSED,                      /**< Notification of a keypress on the remote device.\n See @ref ble_gap_evt_key_pressed_t           */
+  BLE_GAP_EVT_AUTH_KEY_REQUEST,                 /**< Request to provide an authentication key.       \n Reply with @ref sd_ble_gap_auth_key_reply.    \n See @ref ble_gap_evt_auth_key_request_t.   */
+  BLE_GAP_EVT_LESC_DHKEY_REQUEST,               /**< Request to calculate an LE Secure Connections DHKey. \n Reply with @ref sd_ble_gap_lesc_dhkey_reply.  \n See @ref ble_gap_evt_lesc_dhkey_request_t */
+  BLE_GAP_EVT_AUTH_STATUS,                      /**< Authentication procedure completed with status. \n See @ref ble_gap_evt_auth_status_t.          */
+  BLE_GAP_EVT_CONN_SEC_UPDATE,                  /**< Connection security updated.                    \n See @ref ble_gap_evt_conn_sec_update_t.      */
+  BLE_GAP_EVT_TIMEOUT,                          /**< Timeout expired.                                \n See @ref ble_gap_evt_timeout_t.              */
+  BLE_GAP_EVT_RSSI_CHANGED,                     /**< RSSI report.                                    \n See @ref ble_gap_evt_rssi_changed_t.         */
+  BLE_GAP_EVT_ADV_REPORT,                       /**< Advertising report.                             \n See @ref ble_gap_evt_adv_report_t.           */
+  BLE_GAP_EVT_SEC_REQUEST,                      /**< Security Request.                               \n See @ref ble_gap_evt_sec_request_t.          */
+  BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST,        /**< Connection Parameter Update Request.            \n Reply with @ref sd_ble_gap_conn_param_update. \n See @ref ble_gap_evt_conn_param_update_request_t. */
+  BLE_GAP_EVT_SCAN_REQ_REPORT,                  /**< Scan request report.                            \n See @ref ble_gap_evt_scan_req_report_t.      */
+  BLE_GAP_EVT_PHY_UPDATE,                       /**< PHY have been updated                           \n See @ref ble_gap_evt_phy_update_t.           */
+};
+
+/**@brief GAP Option IDs.
+ * IDs that uniquely identify a GAP option.
+ */
+enum BLE_GAP_OPTS
+{
+  BLE_GAP_OPT_CH_MAP  = BLE_GAP_OPT_BASE,       /**< Channel Map. @ref ble_gap_opt_ch_map_t  */
+  BLE_GAP_OPT_LOCAL_CONN_LATENCY,               /**< Local connection latency. @ref ble_gap_opt_local_conn_latency_t */
+  BLE_GAP_OPT_PASSKEY,                          /**< Set passkey. @ref ble_gap_opt_passkey_t */
+  BLE_GAP_OPT_SCAN_REQ_REPORT,                  /**< Scan request report. @ref ble_gap_opt_scan_req_report_t */
+  BLE_GAP_OPT_COMPAT_MODE,                      /**< Compatibility mode. @ref ble_gap_opt_compat_mode_t */
+  BLE_GAP_OPT_AUTH_PAYLOAD_TIMEOUT,             /**< Set Authenticated payload timeout. @ref ble_gap_opt_auth_payload_timeout_t */
+  BLE_GAP_OPT_EXT_LEN,                          /**< Extended length packets. @ref ble_gap_opt_ext_len_t */
+  BLE_GAP_OPT_PREFERRED_PHYS_SET,               /**< Set the preferred PHYs for all new connections. @ref ble_gap_opt_preferred_phys_t */
+};
+
+/** @} */
+
+/**@addtogroup BLE_GAP_DEFINES Defines
+ * @{ */
+
+/**@defgroup BLE_ERRORS_GAP SVC return values specific to GAP
+ * @{ */
+#define BLE_ERROR_GAP_UUID_LIST_MISMATCH            (NRF_GAP_ERR_BASE + 0x000)  /**< UUID list does not contain an integral number of UUIDs. */
+#define BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST   (NRF_GAP_ERR_BASE + 0x001)  /**< Use of Whitelist not permitted with discoverable advertising. */
+#define BLE_ERROR_GAP_INVALID_BLE_ADDR              (NRF_GAP_ERR_BASE + 0x002)  /**< The upper two bits of the address do not correspond to the specified address type. */
+#define BLE_ERROR_GAP_WHITELIST_IN_USE              (NRF_GAP_ERR_BASE + 0x003)  /**< Attempt to modify the whitelist while already in use by another operation. */
+#define BLE_ERROR_GAP_DEVICE_IDENTITIES_IN_USE      (NRF_GAP_ERR_BASE + 0x004)  /**< Attempt to modify the device identity list while already in use by another operation. */
+#define BLE_ERROR_GAP_DEVICE_IDENTITIES_DUPLICATE   (NRF_GAP_ERR_BASE + 0x005)  /**< The device identity list contains entries with duplicate identity addresses. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_ROLES GAP Roles
+ * @note Not explicitly used in peripheral API, but will be relevant for central API.
+ * @{ */
+#define BLE_GAP_ROLE_INVALID     0x0            /**< Invalid Role. */
+#define BLE_GAP_ROLE_PERIPH      0x1            /**< Peripheral Role. */
+#define BLE_GAP_ROLE_CENTRAL     0x2            /**< Central Role. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_TIMEOUT_SOURCES GAP Timeout sources
+ * @{ */
+#define BLE_GAP_TIMEOUT_SRC_ADVERTISING                0x00 /**< Advertising timeout. */
+#define BLE_GAP_TIMEOUT_SRC_SECURITY_REQUEST           0x01 /**< Security request timeout. */
+#define BLE_GAP_TIMEOUT_SRC_SCAN                       0x02 /**< Scanning timeout. */
+#define BLE_GAP_TIMEOUT_SRC_CONN                       0x03 /**< Connection timeout. */
+#define BLE_GAP_TIMEOUT_SRC_AUTH_PAYLOAD               0x04 /**< Authenticated payload timeout. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_ADDR_TYPES GAP Address types
+ * @{ */
+#define BLE_GAP_ADDR_TYPE_PUBLIC                        0x00 /**< Public address. */
+#define BLE_GAP_ADDR_TYPE_RANDOM_STATIC                 0x01 /**< Random static address. */
+#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE     0x02 /**< Random private resolvable address. */
+#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE 0x03 /**< Random private non-resolvable address. */
+/**@} */
+
+
+/**@brief The default interval in seconds at which a private address is refreshed.  */
+#define BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S (900) /* 15 minutes. */
+/**@brief The maximum interval in seconds at which a private address can be refreshed.  */
+#define BLE_GAP_MAX_PRIVATE_ADDR_CYCLE_INTERVAL_S     (41400) /* 11 hours 30 minutes. */
+
+
+/** @brief BLE address length. */
+#define BLE_GAP_ADDR_LEN (6)
+
+
+/**@defgroup BLE_GAP_PRIVACY_MODES Privacy modes
+ * @{ */
+#define BLE_GAP_PRIVACY_MODE_OFF                       0x00 /**< Device will send and accept its identity address for its own address. */
+#define BLE_GAP_PRIVACY_MODE_DEVICE_PRIVACY            0x01 /**< Device will send and accept only private addresses for its own address. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_AD_TYPE_DEFINITIONS GAP Advertising and Scan Response Data format
+ * @note Found at https://www.bluetooth.org/Technical/AssignedNumbers/generic_access_profile.htm
+ * @{ */
+#define BLE_GAP_AD_TYPE_FLAGS                               0x01 /**< Flags for discoverability. */
+#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE   0x02 /**< Partial list of 16 bit service UUIDs. */
+#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE         0x03 /**< Complete list of 16 bit service UUIDs. */
+#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_MORE_AVAILABLE   0x04 /**< Partial list of 32 bit service UUIDs. */
+#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_COMPLETE         0x05 /**< Complete list of 32 bit service UUIDs. */
+#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE  0x06 /**< Partial list of 128 bit service UUIDs. */
+#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE        0x07 /**< Complete list of 128 bit service UUIDs. */
+#define BLE_GAP_AD_TYPE_SHORT_LOCAL_NAME                    0x08 /**< Short local device name. */
+#define BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME                 0x09 /**< Complete local device name. */
+#define BLE_GAP_AD_TYPE_TX_POWER_LEVEL                      0x0A /**< Transmit power level. */
+#define BLE_GAP_AD_TYPE_CLASS_OF_DEVICE                     0x0D /**< Class of device. */
+#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C               0x0E /**< Simple Pairing Hash C. */
+#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R         0x0F /**< Simple Pairing Randomizer R. */
+#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_TK_VALUE           0x10 /**< Security Manager TK Value. */
+#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_OOB_FLAGS          0x11 /**< Security Manager Out Of Band Flags. */
+#define BLE_GAP_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE     0x12 /**< Slave Connection Interval Range. */
+#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT       0x14 /**< List of 16-bit Service Solicitation UUIDs. */
+#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT      0x15 /**< List of 128-bit Service Solicitation UUIDs. */
+#define BLE_GAP_AD_TYPE_SERVICE_DATA                        0x16 /**< Service Data - 16-bit UUID. */
+#define BLE_GAP_AD_TYPE_PUBLIC_TARGET_ADDRESS               0x17 /**< Public Target Address. */
+#define BLE_GAP_AD_TYPE_RANDOM_TARGET_ADDRESS               0x18 /**< Random Target Address. */
+#define BLE_GAP_AD_TYPE_APPEARANCE                          0x19 /**< Appearance. */
+#define BLE_GAP_AD_TYPE_ADVERTISING_INTERVAL                0x1A /**< Advertising Interval. */
+#define BLE_GAP_AD_TYPE_LE_BLUETOOTH_DEVICE_ADDRESS         0x1B /**< LE Bluetooth Device Address. */
+#define BLE_GAP_AD_TYPE_LE_ROLE                             0x1C /**< LE Role. */
+#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C256            0x1D /**< Simple Pairing Hash C-256. */
+#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R256      0x1E /**< Simple Pairing Randomizer R-256. */
+#define BLE_GAP_AD_TYPE_SERVICE_DATA_32BIT_UUID             0x20 /**< Service Data - 32-bit UUID. */
+#define BLE_GAP_AD_TYPE_SERVICE_DATA_128BIT_UUID            0x21 /**< Service Data - 128-bit UUID. */
+#define BLE_GAP_AD_TYPE_URI                                 0x24 /**< URI */
+#define BLE_GAP_AD_TYPE_3D_INFORMATION_DATA                 0x3D /**< 3D Information Data. */
+#define BLE_GAP_AD_TYPE_MANUFACTURER_SPECIFIC_DATA          0xFF /**< Manufacturer Specific Data. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_ADV_FLAGS GAP Advertisement Flags
+ * @{ */
+#define BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE         (0x01)   /**< LE Limited Discoverable Mode. */
+#define BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE         (0x02)   /**< LE General Discoverable Mode. */
+#define BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED         (0x04)   /**< BR/EDR not supported. */
+#define BLE_GAP_ADV_FLAG_LE_BR_EDR_CONTROLLER         (0x08)   /**< Simultaneous LE and BR/EDR, Controller. */
+#define BLE_GAP_ADV_FLAG_LE_BR_EDR_HOST               (0x10)   /**< Simultaneous LE and BR/EDR, Host. */
+#define BLE_GAP_ADV_FLAGS_LE_ONLY_LIMITED_DISC_MODE   (BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED)   /**< LE Limited Discoverable Mode, BR/EDR not supported. */
+#define BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE   (BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED)   /**< LE General Discoverable Mode, BR/EDR not supported. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_ADV_INTERVALS GAP Advertising interval max and min
+ * @{ */
+#define BLE_GAP_ADV_INTERVAL_MIN        0x0020 /**< Minimum Advertising interval in 625 us units, i.e. 20 ms. */
+#define BLE_GAP_ADV_NONCON_INTERVAL_MIN 0x00A0 /**< Minimum Advertising interval in 625 us units for non connectable mode, i.e. 100 ms. */
+#define BLE_GAP_ADV_INTERVAL_MAX        0x4000 /**< Maximum Advertising interval in 625 us units, i.e. 10.24 s. */
+ /**@}  */
+
+
+/**@defgroup BLE_GAP_SCAN_INTERVALS GAP Scan interval max and min
+ * @{ */
+#define BLE_GAP_SCAN_INTERVAL_MIN       0x0004 /**< Minimum Scan interval in 625 us units, i.e. 2.5 ms. */
+#define BLE_GAP_SCAN_INTERVAL_MAX       0x4000 /**< Maximum Scan interval in 625 us units, i.e. 10.24 s. */
+ /** @}  */
+
+
+/**@defgroup BLE_GAP_SCAN_WINDOW GAP Scan window max and min
+ * @{ */
+#define BLE_GAP_SCAN_WINDOW_MIN         0x0004 /**< Minimum Scan window in 625 us units, i.e. 2.5 ms. */
+#define BLE_GAP_SCAN_WINDOW_MAX         0x4000 /**< Maximum Scan window in 625 us units, i.e. 10.24 s. */
+ /** @}  */
+
+
+/**@defgroup BLE_GAP_SCAN_TIMEOUT GAP Scan timeout max and min
+ * @{ */
+#define BLE_GAP_SCAN_TIMEOUT_MIN        0x0001 /**< Minimum Scan timeout in seconds. */
+#define BLE_GAP_SCAN_TIMEOUT_MAX        0xFFFF /**< Maximum Scan timeout in seconds. */
+ /** @}  */
+
+
+/**@brief Maximum size of advertising data in octets. */
+#define BLE_GAP_ADV_MAX_SIZE            (31)
+
+
+/**@defgroup BLE_GAP_ADV_TYPES GAP Advertising types
+ * @{ */
+#define BLE_GAP_ADV_TYPE_ADV_IND          0x00   /**< Connectable undirected. */
+#define BLE_GAP_ADV_TYPE_ADV_DIRECT_IND   0x01   /**< Connectable directed. */
+#define BLE_GAP_ADV_TYPE_ADV_SCAN_IND     0x02   /**< Scannable undirected. */
+#define BLE_GAP_ADV_TYPE_ADV_NONCONN_IND  0x03   /**< Non connectable undirected. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_ADV_FILTER_POLICIES GAP Advertising filter policies
+ * @{ */
+#define BLE_GAP_ADV_FP_ANY                0x00   /**< Allow scan requests and connect requests from any device. */
+#define BLE_GAP_ADV_FP_FILTER_SCANREQ     0x01   /**< Filter scan requests with whitelist. */
+#define BLE_GAP_ADV_FP_FILTER_CONNREQ     0x02   /**< Filter connect requests with whitelist. */
+#define BLE_GAP_ADV_FP_FILTER_BOTH        0x03   /**< Filter both scan and connect requests with whitelist. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_ADV_TIMEOUT_VALUES GAP Advertising timeout values
+ * @{ */
+#define BLE_GAP_ADV_TIMEOUT_LIMITED_MAX       (180) /**< Maximum advertising time in limited discoverable mode (TGAP(lim_adv_timeout) = 180s). */
+#define BLE_GAP_ADV_TIMEOUT_GENERAL_UNLIMITED (0)   /**< Unlimited advertising in general discoverable mode. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_DISC_MODES GAP Discovery modes
+ * @{ */
+#define BLE_GAP_DISC_MODE_NOT_DISCOVERABLE  0x00   /**< Not discoverable discovery Mode. */
+#define BLE_GAP_DISC_MODE_LIMITED           0x01   /**< Limited Discovery Mode. */
+#define BLE_GAP_DISC_MODE_GENERAL           0x02   /**< General Discovery Mode. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_IO_CAPS GAP IO Capabilities
+ * @{ */
+#define BLE_GAP_IO_CAPS_DISPLAY_ONLY      0x00   /**< Display Only. */
+#define BLE_GAP_IO_CAPS_DISPLAY_YESNO     0x01   /**< Display and Yes/No entry. */
+#define BLE_GAP_IO_CAPS_KEYBOARD_ONLY     0x02   /**< Keyboard Only. */
+#define BLE_GAP_IO_CAPS_NONE              0x03   /**< No I/O capabilities. */
+#define BLE_GAP_IO_CAPS_KEYBOARD_DISPLAY  0x04   /**< Keyboard and Display. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_AUTH_KEY_TYPES GAP Authentication Key Types
+ * @{ */
+#define BLE_GAP_AUTH_KEY_TYPE_NONE        0x00   /**< No key (may be used to reject). */
+#define BLE_GAP_AUTH_KEY_TYPE_PASSKEY     0x01   /**< 6-digit Passkey. */
+#define BLE_GAP_AUTH_KEY_TYPE_OOB         0x02   /**< Out Of Band data. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_KP_NOT_TYPES GAP Keypress Notification Types
+ * @{ */
+#define BLE_GAP_KP_NOT_TYPE_PASSKEY_START       0x00   /**< Passkey entry started. */
+#define BLE_GAP_KP_NOT_TYPE_PASSKEY_DIGIT_IN    0x01   /**< Passkey digit entered. */
+#define BLE_GAP_KP_NOT_TYPE_PASSKEY_DIGIT_OUT   0x02   /**< Passkey digit erased. */
+#define BLE_GAP_KP_NOT_TYPE_PASSKEY_CLEAR       0x03   /**< Passkey cleared. */
+#define BLE_GAP_KP_NOT_TYPE_PASSKEY_END         0x04   /**< Passkey entry completed. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_SEC_STATUS GAP Security status
+ * @{ */
+#define BLE_GAP_SEC_STATUS_SUCCESS                0x00  /**< Procedure completed with success. */
+#define BLE_GAP_SEC_STATUS_TIMEOUT                0x01  /**< Procedure timed out. */
+#define BLE_GAP_SEC_STATUS_PDU_INVALID            0x02  /**< Invalid PDU received. */
+#define BLE_GAP_SEC_STATUS_RFU_RANGE1_BEGIN       0x03  /**< Reserved for Future Use range #1 begin. */
+#define BLE_GAP_SEC_STATUS_RFU_RANGE1_END         0x80  /**< Reserved for Future Use range #1 end. */
+#define BLE_GAP_SEC_STATUS_PASSKEY_ENTRY_FAILED   0x81  /**< Passkey entry failed (user cancelled or other). */
+#define BLE_GAP_SEC_STATUS_OOB_NOT_AVAILABLE      0x82  /**< Out of Band Key not available. */
+#define BLE_GAP_SEC_STATUS_AUTH_REQ               0x83  /**< Authentication requirements not met. */
+#define BLE_GAP_SEC_STATUS_CONFIRM_VALUE          0x84  /**< Confirm value failed. */
+#define BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP       0x85  /**< Pairing not supported.  */
+#define BLE_GAP_SEC_STATUS_ENC_KEY_SIZE           0x86  /**< Encryption key size. */
+#define BLE_GAP_SEC_STATUS_SMP_CMD_UNSUPPORTED    0x87  /**< Unsupported SMP command. */
+#define BLE_GAP_SEC_STATUS_UNSPECIFIED            0x88  /**< Unspecified reason. */
+#define BLE_GAP_SEC_STATUS_REPEATED_ATTEMPTS      0x89  /**< Too little time elapsed since last attempt. */
+#define BLE_GAP_SEC_STATUS_INVALID_PARAMS         0x8A  /**< Invalid parameters. */
+#define BLE_GAP_SEC_STATUS_DHKEY_FAILURE          0x8B  /**< DHKey check failure. */
+#define BLE_GAP_SEC_STATUS_NUM_COMP_FAILURE       0x8C  /**< Numeric Comparison failure. */
+#define BLE_GAP_SEC_STATUS_BR_EDR_IN_PROG         0x8D  /**< BR/EDR pairing in progress. */
+#define BLE_GAP_SEC_STATUS_X_TRANS_KEY_DISALLOWED 0x8E  /**< BR/EDR Link Key cannot be used for LE keys. */
+#define BLE_GAP_SEC_STATUS_RFU_RANGE2_BEGIN       0x8F  /**< Reserved for Future Use range #2 begin. */
+#define BLE_GAP_SEC_STATUS_RFU_RANGE2_END         0xFF  /**< Reserved for Future Use range #2 end. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_SEC_STATUS_SOURCES GAP Security status sources
+ * @{ */
+#define BLE_GAP_SEC_STATUS_SOURCE_LOCAL           0x00  /**< Local failure. */
+#define BLE_GAP_SEC_STATUS_SOURCE_REMOTE          0x01  /**< Remote failure. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_CP_LIMITS GAP Connection Parameters Limits
+ * @{ */
+#define BLE_GAP_CP_MIN_CONN_INTVL_NONE           0xFFFF  /**< No new minimum connection interval specified in connect parameters. */
+#define BLE_GAP_CP_MIN_CONN_INTVL_MIN            0x0006  /**< Lowest minimum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */
+#define BLE_GAP_CP_MIN_CONN_INTVL_MAX            0x0C80  /**< Highest minimum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */
+#define BLE_GAP_CP_MAX_CONN_INTVL_NONE           0xFFFF  /**< No new maximum connection interval specified in connect parameters. */
+#define BLE_GAP_CP_MAX_CONN_INTVL_MIN            0x0006  /**< Lowest maximum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */
+#define BLE_GAP_CP_MAX_CONN_INTVL_MAX            0x0C80  /**< Highest maximum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */
+#define BLE_GAP_CP_SLAVE_LATENCY_MAX             0x01F3  /**< Highest slave latency permitted, in connection events. */
+#define BLE_GAP_CP_CONN_SUP_TIMEOUT_NONE         0xFFFF  /**< No new supervision timeout specified in connect parameters. */
+#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MIN          0x000A  /**< Lowest supervision timeout permitted, in units of 10 ms, i.e. 100 ms. */
+#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MAX          0x0C80  /**< Highest supervision timeout permitted, in units of 10 ms, i.e. 32 s. */
+/**@} */
+
+
+/**@brief GAP device name defines. */
+#define BLE_GAP_DEVNAME_DEFAULT                  "nRF5x" /**< Default device name value. */
+#define BLE_GAP_DEVNAME_DEFAULT_LEN              31      /**< Default number of octets in device name. */
+#define BLE_GAP_DEVNAME_MAX_LEN                  248     /**< Maximum number of octets in device name. */
+
+
+/**@brief Disable RSSI events for connections */
+#define BLE_GAP_RSSI_THRESHOLD_INVALID 0xFF
+
+/**@defgroup BLE_GAP_PHYS GAP PHYs
+ * @{ */
+#define BLE_GAP_PHY_1MBPS                        0x01    /**< 1 Mbps PHY. */
+#define BLE_GAP_PHY_2MBPS                        0x02    /**< 2 Mbps PHY. */
+#define BLE_GAP_PHY_CODED                        0x04    /**< Coded PHY. */
+/**@} */
+
+/**@defgroup BLE_GAP_CONN_SEC_MODE_SET_MACROS GAP attribute security requirement setters
+ *
+ * See @ref ble_gap_conn_sec_mode_t.
+ * @{ */
+/**@brief Set sec_mode pointed to by ptr to have no access rights.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(ptr)          do {(ptr)->sm = 0; (ptr)->lv = 0;} while(0)
+/**@brief Set sec_mode pointed to by ptr to require no protection, open link.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_OPEN(ptr)               do {(ptr)->sm = 1; (ptr)->lv = 1;} while(0)
+/**@brief Set sec_mode pointed to by ptr to require encryption, but no MITM protection.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(ptr)        do {(ptr)->sm = 1; (ptr)->lv = 2;} while(0)
+/**@brief Set sec_mode pointed to by ptr to require encryption and MITM protection.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(ptr)      do {(ptr)->sm = 1; (ptr)->lv = 3;} while(0)
+/**@brief Set sec_mode pointed to by ptr to require LESC encryption and MITM protection.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_LESC_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 4;} while(0)
+/**@brief Set sec_mode pointed to by ptr to require signing or encryption, no MITM protection needed.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(ptr)     do {(ptr)->sm = 2; (ptr)->lv = 1;} while(0)
+/**@brief Set sec_mode pointed to by ptr to require signing or encryption with MITM protection.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(ptr)   do {(ptr)->sm = 2; (ptr)->lv = 2;} while(0)
+/**@} */
+
+
+/**@brief GAP Security Random Number Length. */
+#define BLE_GAP_SEC_RAND_LEN 8
+
+
+/**@brief GAP Security Key Length. */
+#define BLE_GAP_SEC_KEY_LEN 16
+
+
+/**@brief GAP LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key Length. */
+#define BLE_GAP_LESC_P256_PK_LEN 64
+
+
+/**@brief GAP LE Secure Connections Elliptic Curve Diffie-Hellman DHKey Length. */
+#define BLE_GAP_LESC_DHKEY_LEN   32
+
+
+/**@brief GAP Passkey Length. */
+#define BLE_GAP_PASSKEY_LEN 6
+
+
+/**@brief Maximum amount of addresses in the whitelist. */
+#define BLE_GAP_WHITELIST_ADDR_MAX_COUNT (8)
+
+
+/**@brief Maximum amount of identities in the device identities list. */
+#define BLE_GAP_DEVICE_IDENTITIES_MAX_COUNT (8)
+
+
+/**@defgroup GAP_SEC_MODES GAP Security Modes
+ * @{ */
+#define BLE_GAP_SEC_MODE 0x00 /**< No key (may be used to reject). */
+/**@} */
+/** @} */
+
+
+/**@addtogroup BLE_GAP_STRUCTURES Structures
+ * @{ */
+
+/**@brief Bluetooth Low Energy address. */
+typedef struct
+{
+  uint8_t addr_id_peer : 1;       /**< Only valid for peer addresses.
+                                       Reference to peer in device identities list (as set with @ref sd_ble_gap_device_identities_set) when peer is using privacy. */
+  uint8_t addr_type    : 7;       /**< See @ref BLE_GAP_ADDR_TYPES. */
+  uint8_t addr[BLE_GAP_ADDR_LEN]; /**< 48-bit address, LSB format. */
+} ble_gap_addr_t;
+
+
+/**@brief GAP connection parameters.
+ *
+ * @note  When ble_conn_params_t is received in an event, both min_conn_interval and
+ *        max_conn_interval will be equal to the connection interval set by the central.
+ *
+ * @note If both conn_sup_timeout and max_conn_interval are specified, then the following constraint applies:
+ *       conn_sup_timeout * 4 > (1 + slave_latency) * max_conn_interval
+ *       that corresponds to the following Bluetooth Spec requirement:
+ *       The Supervision_Timeout in milliseconds shall be larger than
+ *       (1 + Conn_Latency) * Conn_Interval_Max * 2, where Conn_Interval_Max is given in milliseconds.
+ */
+typedef struct
+{
+  uint16_t min_conn_interval;         /**< Minimum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/
+  uint16_t max_conn_interval;         /**< Maximum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/
+  uint16_t slave_latency;             /**< Slave Latency in number of connection events, see @ref BLE_GAP_CP_LIMITS.*/
+  uint16_t conn_sup_timeout;          /**< Connection Supervision Timeout in 10 ms units, see @ref BLE_GAP_CP_LIMITS.*/
+} ble_gap_conn_params_t;
+
+
+/**@brief GAP connection security modes.
+ *
+ * Security Mode 0 Level 0: No access permissions at all (this level is not defined by the Bluetooth Core specification).\n
+ * Security Mode 1 Level 1: No security is needed (aka open link).\n
+ * Security Mode 1 Level 2: Encrypted link required, MITM protection not necessary.\n
+ * Security Mode 1 Level 3: MITM protected encrypted link required.\n
+ * Security Mode 1 Level 4: LESC MITM protected encrypted link required.\n
+ * Security Mode 2 Level 1: Signing or encryption required, MITM protection not necessary.\n
+ * Security Mode 2 Level 2: MITM protected signing required, unless link is MITM protected encrypted.\n
+ */
+typedef struct
+{
+  uint8_t sm : 4;                     /**< Security Mode (1 or 2), 0 for no permissions at all. */
+  uint8_t lv : 4;                     /**< Level (1, 2, 3 or 4), 0 for no permissions at all. */
+
+} ble_gap_conn_sec_mode_t;
+
+
+/**@brief GAP connection security status.*/
+typedef struct
+{
+  ble_gap_conn_sec_mode_t sec_mode;           /**< Currently active security mode for this connection.*/
+  uint8_t                 encr_key_size;      /**< Length of currently active encryption key, 7 to 16 octets (only applicable for bonding procedures). */
+} ble_gap_conn_sec_t;
+
+
+/**
+ * @brief Device name and its properties
+ * @note If @ref max_len is more than @ref BLE_GAP_DEVNAME_DEFAULT_LEN and vloc is set to @ref BLE_GATTS_VLOC_STACK, the attribute table size must be increased to have room for the longer device name (see @ref ble_gatts_enable_params_t).
+ */
+typedef struct
+{
+  ble_gap_conn_sec_mode_t  write_perm;   /**< Write permissions. */
+  uint8_t                  vloc:2;       /**< Value location, see @ref BLE_GATTS_VLOCS.*/
+  uint8_t                 *p_value;      /**< Pointer to where the value (device name) is stored or will be stored.*/
+  uint16_t                 current_len;  /**< Current length in bytes of the memory pointed to by p_value.*/
+  uint16_t                 max_len;      /**< Maximum length in bytes of the memory pointed to by p_value.*/
+} ble_gap_device_name_t;
+
+
+/**
+ * @brief BLE GAP initialization parameters.
+ */
+typedef struct
+{
+  uint8_t                      periph_conn_count;  /**< Number of connections acting as a peripheral  */
+  uint8_t                      central_conn_count; /**< Number of connections acting as a central */
+  uint8_t                      central_sec_count;  /**< Number of SMP instances for all connections acting as a central. */
+  ble_gap_device_name_t const *p_device_name;      /**< Pointer to device name instance. If NULL, @ref sd_ble_enable() will set the device name to @ref BLE_GAP_DEVNAME_DEFAULT. */
+} ble_gap_enable_params_t;
+
+
+/**@brief Identity Resolving Key. */
+typedef struct
+{
+  uint8_t irk[BLE_GAP_SEC_KEY_LEN];   /**< Array containing IRK. */
+} ble_gap_irk_t;
+
+
+/**@brief Channel mask for RF channels used in advertising. */
+typedef struct
+{
+  uint8_t ch_37_off : 1;  /**< Setting this bit to 1 will turn off advertising on channel 37 */
+  uint8_t ch_38_off : 1;  /**< Setting this bit to 1 will turn off advertising on channel 38 */
+  uint8_t ch_39_off : 1;  /**< Setting this bit to 1 will turn off advertising on channel 39 */
+} ble_gap_adv_ch_mask_t;
+
+
+/**@brief GAP advertising parameters. */
+typedef struct
+{
+  uint8_t               type;                 /**< See @ref BLE_GAP_ADV_TYPES. */
+  ble_gap_addr_t const *p_peer_addr;          /**< Address of a known peer.
+                                                   - When privacy is enabled and the local device use @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE addresses, the device identity list is searched for a matching
+                                                     entry. If the local IRK for that device identity is set, the local IRK for that device will be used to generate the advertiser address field in the advertise packet.
+                                                   - If type is @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND, this must be set to the targeted initiator. If the initiator is in the device identity list,
+                                                     the peer IRK for that device will be used to generate the initiator address field in the ADV_DIRECT_IND packet. */
+  uint8_t               fp;                   /**< Filter Policy, see @ref BLE_GAP_ADV_FILTER_POLICIES. */
+  uint16_t              interval;             /**< Advertising interval between 0x0020 and 0x4000 in 0.625 ms units (20ms to 10.24s), see @ref BLE_GAP_ADV_INTERVALS.
+                                                   - If type equals @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND, this parameter must be set to 0 for high duty cycle directed advertising.
+                                                   - If type equals @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND, set @ref BLE_GAP_ADV_INTERVAL_MIN <= interval <= @ref BLE_GAP_ADV_INTERVAL_MAX for low duty cycle advertising.*/
+  uint16_t              timeout;              /**< Advertising timeout between 0x0001 and 0x3FFF in seconds, 0x0000 disables timeout. See also @ref BLE_GAP_ADV_TIMEOUT_VALUES. If type equals @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND, this parameter must be set to 0 for High duty cycle directed advertising. */
+  ble_gap_adv_ch_mask_t channel_mask;         /**< Advertising channel mask. See @ref ble_gap_adv_ch_mask_t. */
+} ble_gap_adv_params_t;
+
+
+/**@brief GAP scanning parameters. */
+typedef struct
+{
+  uint8_t  active         : 1;  /**< If 1, perform active scanning (scan requests). */
+  uint8_t  use_whitelist  : 1;  /**< If 1, filter advertisers using current active whitelist. */
+  uint8_t  adv_dir_report : 1;  /**< If 1, also report directed advertisements where the initiator field is set to a private resolvable address,
+                                     even if the address did not resolve to an entry in the device identity list. A report will be generated
+                                     even if the peer is not in the whitelist. */
+  uint16_t interval;            /**< Scan interval between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */
+  uint16_t window;              /**< Scan window between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */
+  uint16_t timeout;             /**< Scan timeout between 0x0001 and 0xFFFF in seconds, 0x0000 disables timeout. */
+} ble_gap_scan_params_t;
+
+
+/**@brief Device Privacy.
+ *
+ *        The privacy feature provides a way for the device to avoid being tracked over a period of time.
+ *        The privacy feature, when enabled, hides the local device identity and replaces it with a private address
+ *        that is automatically refreshed at a specified interval.
+ *
+ *        If a device still wants to be recognized by other peers, it needs to share it's Identity Resolving Key (IRK).
+ *        With this key, a device can generate a random private address that can only be recognized by peers in possession of that key,
+ *        and devices can establish connections without revealing their real identities.
+ *
+ * @note  If the device IRK is updated, the new IRK becomes the one to be distributed in all
+ *        bonding procedures performed after @ref sd_ble_gap_privacy_set returns.
+ *        The IRK distributed during bonding procedure is the device IRK that is active when @ref sd_ble_gap_sec_params_reply is called.
+ */
+typedef struct
+{
+  uint8_t        privacy_mode;         /**< Privacy mode, see @ref BLE_GAP_PRIVACY_MODES. Default is @ref BLE_GAP_PRIVACY_MODE_OFF. */
+  uint8_t        private_addr_type;    /**< The private address type must be either @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE or @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE. */
+  uint16_t       private_addr_cycle_s; /**< Private address cycle interval in seconds. Providing an address cycle value of 0 will use the default value defined by @ref BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S. */
+  ble_gap_irk_t *p_device_irk;         /**< When used as input, pointer to IRK structure that will be used as the default IRK. If NULL, the device default IRK will be used.
+                                            When used as output, pointer to IRK structure where the current default IRK will be written to. If NULL, this argument is ignored.
+                                            By default, the default IRK is used to generate random private resolvable addresses for the local device unless instructed otherwise. */
+} ble_gap_privacy_params_t;
+
+
+/**@brief Physical Layer configuration
+ * @note      tx_phys and rx_phys are bitfields, to indicate multiple preferred PHYs for each direction they can be ORed together.
+ * @code
+ * p_gap_phys->tx_phys = BLE_GAP_PHY_1MBPS | BLE_GAP_PHY_2MBPS;
+ * p_gap_phys->rx_phys = BLE_GAP_PHY_1MBPS | BLE_GAP_PHY_2MBPS;
+ * @endcode
+ *
+ */
+typedef struct
+{
+  uint8_t tx_phys;     /**< Preferred transmit PHYs, see @ref BLE_GAP_PHYS. */
+  uint8_t rx_phys;     /**< Preferred receive PHYs, see @ref BLE_GAP_PHYS. */
+} ble_gap_phys_t;
+
+/** @brief Keys that can be exchanged during a bonding procedure. */
+typedef struct
+{
+  uint8_t enc     : 1;                        /**< Long Term Key and Master Identification. */
+  uint8_t id      : 1;                        /**< Identity Resolving Key and Identity Address Information. */
+  uint8_t sign    : 1;                        /**< Connection Signature Resolving Key. */
+  uint8_t link    : 1;                        /**< Derive the Link Key from the LTK. */
+} ble_gap_sec_kdist_t;
+
+
+/**@brief GAP security parameters. */
+typedef struct
+{
+  uint8_t               bond      : 1;             /**< Perform bonding. */
+  uint8_t               mitm      : 1;             /**< Enable Man In The Middle protection. */
+  uint8_t               lesc      : 1;             /**< Enable LE Secure Connection pairing. */
+  uint8_t               keypress  : 1;             /**< Enable generation of keypress notifications. */
+  uint8_t               io_caps   : 3;             /**< IO capabilities, see @ref BLE_GAP_IO_CAPS. */
+  uint8_t               oob       : 1;             /**< The OOB data flag.
+                                                        - In LE legacy pairing, this flag is set if a device has out of band authentication data.
+                                                          The OOB method is used if both of the devices have out of band authentication data.
+                                                        - In LE Secure Connections pairing, this flag is set if a device has the peer device's out of band authentication data.
+                                                          The OOB method is used if at least one device has the peer device's OOB data available. */
+  uint8_t               min_key_size;              /**< Minimum encryption key size in octets between 7 and 16. If 0 then not applicable in this instance. */
+  uint8_t               max_key_size;              /**< Maximum encryption key size in octets between min_key_size and 16. */
+  ble_gap_sec_kdist_t   kdist_own;                 /**< Key distribution bitmap: keys that the local device will distribute. */
+  ble_gap_sec_kdist_t   kdist_peer;                /**< Key distribution bitmap: keys that the remote device will distribute. */
+} ble_gap_sec_params_t;
+
+
+/**@brief GAP Encryption Information. */
+typedef struct
+{
+  uint8_t   ltk[BLE_GAP_SEC_KEY_LEN];   /**< Long Term Key. */
+  uint8_t   lesc : 1;                   /**< Key generated using LE Secure Connections. */
+  uint8_t   auth : 1;                   /**< Authenticated Key. */
+  uint8_t   ltk_len : 6;                /**< LTK length in octets. */
+} ble_gap_enc_info_t;
+
+
+/**@brief GAP Master Identification. */
+typedef struct
+{
+  uint16_t  ediv;                       /**< Encrypted Diversifier. */
+  uint8_t   rand[BLE_GAP_SEC_RAND_LEN]; /**< Random Number. */
+} ble_gap_master_id_t;
+
+
+/**@brief GAP Signing Information. */
+typedef struct
+{
+  uint8_t   csrk[BLE_GAP_SEC_KEY_LEN];        /**< Connection Signature Resolving Key. */
+} ble_gap_sign_info_t;
+
+
+/**@brief GAP LE Secure Connections P-256 Public Key. */
+typedef struct
+{
+  uint8_t   pk[BLE_GAP_LESC_P256_PK_LEN];        /**< LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key. Stored in the standard SMP protocol format: {X,Y} both in little-endian. */
+} ble_gap_lesc_p256_pk_t;
+
+
+/**@brief GAP LE Secure Connections DHKey. */
+typedef struct
+{
+  uint8_t   key[BLE_GAP_LESC_DHKEY_LEN];        /**< LE Secure Connections Elliptic Curve Diffie-Hellman Key. Stored in little-endian. */
+} ble_gap_lesc_dhkey_t;
+
+
+/**@brief GAP LE Secure Connections OOB data. */
+typedef struct
+{
+  ble_gap_addr_t  addr;                          /**< Bluetooth address of the device. */
+  uint8_t         r[BLE_GAP_SEC_KEY_LEN];        /**< Random Number. */
+  uint8_t         c[BLE_GAP_SEC_KEY_LEN];        /**< Confirm Value. */
+} ble_gap_lesc_oob_data_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_CONNECTED. */
+typedef struct
+{
+  ble_gap_addr_t        peer_addr;              /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1
+                                                     and the address is the device's identity address. */
+  uint8_t               role;                   /**< BLE role for this connection, see @ref BLE_GAP_ROLES */
+  ble_gap_conn_params_t conn_params;            /**< GAP Connection Parameters. */
+} ble_gap_evt_connected_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_DISCONNECTED. */
+typedef struct
+{
+  uint8_t reason;                               /**< HCI error code, see @ref BLE_HCI_STATUS_CODES. */
+} ble_gap_evt_disconnected_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE. */
+typedef struct
+{
+  ble_gap_conn_params_t conn_params;            /**<  GAP Connection Parameters. */
+} ble_gap_evt_conn_param_update_t;
+
+/**@brief Event Structure for @ref BLE_GAP_EVT_PHY_UPDATE. */
+typedef struct
+{
+  uint8_t status;                               /**< Status of the procedure, see @ref BLE_HCI_STATUS_CODES */
+  uint8_t tx_phy;                               /**< TX PHY for this connection, see @ref BLE_GAP_PHYS. */
+  uint8_t rx_phy;                               /**< RX PHY for this connection, see @ref BLE_GAP_PHYS. */
+} ble_gap_evt_phy_update_t;
+
+/**@brief Event structure for @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST. */
+typedef struct
+{
+  ble_gap_sec_params_t peer_params;             /**< Initiator Security Parameters. */
+} ble_gap_evt_sec_params_request_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_SEC_INFO_REQUEST. */
+typedef struct
+{
+  ble_gap_addr_t      peer_addr;                     /**< Bluetooth address of the peer device. */
+  ble_gap_master_id_t master_id;                     /**< Master Identification for LTK lookup. */
+  uint8_t             enc_info  : 1;                 /**< If 1, Encryption Information required. */
+  uint8_t             id_info   : 1;                 /**< If 1, Identity Information required. */
+  uint8_t             sign_info : 1;                 /**< If 1, Signing Information required. */
+} ble_gap_evt_sec_info_request_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_PASSKEY_DISPLAY. */
+typedef struct
+{
+  uint8_t passkey[BLE_GAP_PASSKEY_LEN];         /**< 6-digit passkey in ASCII ('0'-'9' digits only). */
+  uint8_t match_request : 1;                    /**< If 1 requires the application to report the match using @ref sd_ble_gap_auth_key_reply
+                                                     with either @ref BLE_GAP_AUTH_KEY_TYPE_NONE if there is no match or
+                                                     @ref BLE_GAP_AUTH_KEY_TYPE_PASSKEY if there is a match. */
+} ble_gap_evt_passkey_display_t;
+
+/**@brief Event structure for @ref BLE_GAP_EVT_KEY_PRESSED. */
+typedef struct
+{
+  uint8_t kp_not;         /**< Keypress notification type, see @ref BLE_GAP_KP_NOT_TYPES. */
+} ble_gap_evt_key_pressed_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_AUTH_KEY_REQUEST. */
+typedef struct
+{
+  uint8_t key_type;                             /**< See @ref BLE_GAP_AUTH_KEY_TYPES. */
+} ble_gap_evt_auth_key_request_t;
+
+/**@brief Event structure for @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST. */
+typedef struct
+{
+  ble_gap_lesc_p256_pk_t *p_pk_peer;  /**< LE Secure Connections remote P-256 Public Key. This will point to the application-supplied memory
+                                           inside the keyset during the call to @ref sd_ble_gap_sec_params_reply. */
+  uint8_t oobd_req       :1;          /**< LESC OOB data required. A call to @ref sd_ble_gap_lesc_oob_data_set is required to complete the procedure. */
+} ble_gap_evt_lesc_dhkey_request_t;
+
+
+/**@brief Security levels supported.
+ * @note See Bluetooth Specification Version 4.2 Volume 3, Part C, Chapter 10, Section 10.2.1.
+*/
+typedef struct
+{
+  uint8_t lv1 : 1;                              /**< If 1: Level 1 is supported. */
+  uint8_t lv2 : 1;                              /**< If 1: Level 2 is supported. */
+  uint8_t lv3 : 1;                              /**< If 1: Level 3 is supported. */
+  uint8_t lv4 : 1;                              /**< If 1: Level 4 is supported. */
+} ble_gap_sec_levels_t;
+
+
+/**@brief Encryption Key. */
+typedef struct
+{
+  ble_gap_enc_info_t    enc_info;             /**< Encryption Information. */
+  ble_gap_master_id_t   master_id;            /**< Master Identification. */
+} ble_gap_enc_key_t;
+
+
+/**@brief Identity Key. */
+typedef struct
+{
+  ble_gap_irk_t         id_info;              /**< Identity Resolving Key. */
+  ble_gap_addr_t        id_addr_info;         /**< Identity Address. */
+} ble_gap_id_key_t;
+
+
+/**@brief Security Keys. */
+typedef struct
+{
+  ble_gap_enc_key_t      *p_enc_key;           /**< Encryption Key, or NULL. */
+  ble_gap_id_key_t       *p_id_key;            /**< Identity Key, or NULL. */
+  ble_gap_sign_info_t    *p_sign_key;          /**< Signing Key, or NULL. */
+  ble_gap_lesc_p256_pk_t *p_pk;                /**< LE Secure Connections P-256 Public Key. When in debug mode the application must use the value defined
+                                                    in the Core Bluetooth Specification v4.2 Vol.3, Part H, Section 2.3.5.6.1 */
+} ble_gap_sec_keys_t;
+
+
+/**@brief Security key set for both local and peer keys. */
+typedef struct
+{
+  ble_gap_sec_keys_t            keys_own;     /**< Keys distributed by the local device. For LE Secure Connections the encryption key will be generated locally and will always be stored if bonding. */
+  ble_gap_sec_keys_t            keys_peer;    /**< Keys distributed by the remote device. For LE Secure Connections, p_enc_key must always be NULL. */
+} ble_gap_sec_keyset_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_AUTH_STATUS. */
+typedef struct
+{
+  uint8_t               auth_status;            /**< Authentication status, see @ref BLE_GAP_SEC_STATUS. */
+  uint8_t               error_src : 2;          /**< On error, source that caused the failure, see @ref BLE_GAP_SEC_STATUS_SOURCES. */
+  uint8_t               bonded : 1;             /**< Procedure resulted in a bond. */
+  ble_gap_sec_levels_t  sm1_levels;             /**< Levels supported in Security Mode 1. */
+  ble_gap_sec_levels_t  sm2_levels;             /**< Levels supported in Security Mode 2. */
+  ble_gap_sec_kdist_t   kdist_own;              /**< Bitmap stating which keys were exchanged (distributed) by the local device. If bonding with LE Secure Connections, the enc bit will be always set. */
+  ble_gap_sec_kdist_t   kdist_peer;             /**< Bitmap stating which keys were exchanged (distributed) by the remote device. If bonding with LE Secure Connections, the enc bit will never be set. */
+} ble_gap_evt_auth_status_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_CONN_SEC_UPDATE. */
+typedef struct
+{
+  ble_gap_conn_sec_t conn_sec;                  /**< Connection security level. */
+} ble_gap_evt_conn_sec_update_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_TIMEOUT. */
+typedef struct
+{
+  uint8_t src;                                  /**< Source of timeout event, see @ref BLE_GAP_TIMEOUT_SOURCES. */
+} ble_gap_evt_timeout_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_RSSI_CHANGED. */
+typedef struct
+{
+  int8_t  rssi;                               /**< Received Signal Strength Indication in dBm. */
+} ble_gap_evt_rssi_changed_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_ADV_REPORT. */
+typedef struct
+{
+  ble_gap_addr_t peer_addr;                     /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1
+                                                     and the address is the device's identity address. */
+  ble_gap_addr_t direct_addr;                   /**< Set when the scanner is unable to resolve the private resolvable address of the initiator
+                                                     field of a directed advertisement packet and the scanner has been enabled to report this in @ref ble_gap_scan_params_t::adv_dir_report. */
+  int8_t         rssi;                          /**< Received Signal Strength Indication in dBm. */
+  uint8_t        scan_rsp : 1;                  /**< If 1, the report corresponds to a scan response and the type field may be ignored. */
+  uint8_t        type     : 2;                  /**< See @ref BLE_GAP_ADV_TYPES. Only valid if the scan_rsp field is 0. */
+  uint8_t        dlen     : 5;                  /**< Advertising or scan response data length. */
+  uint8_t        data[BLE_GAP_ADV_MAX_SIZE];    /**< Advertising or scan response data. */
+} ble_gap_evt_adv_report_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_SEC_REQUEST. */
+typedef struct
+{
+  uint8_t    bond       : 1;                       /**< Perform bonding. */
+  uint8_t    mitm       : 1;                       /**< Man In The Middle protection requested. */
+  uint8_t    lesc       : 1;                       /**< LE Secure Connections requested. */
+  uint8_t    keypress   : 1;                       /**< Generation of keypress notifications requested. */
+} ble_gap_evt_sec_request_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST. */
+typedef struct
+{
+  ble_gap_conn_params_t conn_params;            /**<  GAP Connection Parameters. */
+} ble_gap_evt_conn_param_update_request_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_SCAN_REQ_REPORT. */
+typedef struct
+{
+  int8_t                  rssi;              /**< Received Signal Strength Indication in dBm. */
+  ble_gap_addr_t          peer_addr;         /**< Bluetooth address of the peer device. If the peer_addr resolved: @ref ble_gap_addr_t::addr_id_peer is set to 1
+                                                  and the address is the device's identity address. */
+} ble_gap_evt_scan_req_report_t;
+
+
+/**@brief GAP event structure. */
+typedef struct
+{
+  uint16_t conn_handle;                                     /**< Connection Handle on which event occurred. */
+  union                                                     /**< union alternative identified by evt_id in enclosing struct. */
+  {
+    ble_gap_evt_connected_t                   connected;                    /**< Connected Event Parameters. */
+    ble_gap_evt_disconnected_t                disconnected;                 /**< Disconnected Event Parameters. */
+    ble_gap_evt_conn_param_update_t           conn_param_update;            /**< Connection Parameter Update Parameters. */
+    ble_gap_evt_sec_params_request_t          sec_params_request;           /**< Security Parameters Request Event Parameters. */
+    ble_gap_evt_sec_info_request_t            sec_info_request;             /**< Security Information Request Event Parameters. */
+    ble_gap_evt_passkey_display_t             passkey_display;              /**< Passkey Display Event Parameters. */
+    ble_gap_evt_key_pressed_t                 key_pressed;                  /**< Key Pressed Event Parameters. */
+    ble_gap_evt_auth_key_request_t            auth_key_request;             /**< Authentication Key Request Event Parameters. */
+    ble_gap_evt_lesc_dhkey_request_t          lesc_dhkey_request;           /**< LE Secure Connections DHKey calculation request. */
+    ble_gap_evt_auth_status_t                 auth_status;                  /**< Authentication Status Event Parameters. */
+    ble_gap_evt_conn_sec_update_t             conn_sec_update;              /**< Connection Security Update Event Parameters. */
+    ble_gap_evt_timeout_t                     timeout;                      /**< Timeout Event Parameters. */
+    ble_gap_evt_rssi_changed_t                rssi_changed;                 /**< RSSI Event Parameters. */
+    ble_gap_evt_adv_report_t                  adv_report;                   /**< Advertising Report Event Parameters. */
+    ble_gap_evt_sec_request_t                 sec_request;                  /**< Security Request Event Parameters. */
+    ble_gap_evt_conn_param_update_request_t   conn_param_update_request;    /**< Connection Parameter Update Parameters. */
+    ble_gap_evt_scan_req_report_t             scan_req_report;              /**< Scan Request Report Parameters. */
+    ble_gap_evt_phy_update_t                  phy_update;                   /**< PHY Update Parameters. */
+  } params;                                                                 /**< Event Parameters. */
+} ble_gap_evt_t;
+
+
+/**@brief Channel Map option.
+ *        Used with @ref sd_ble_opt_get to get the current channel map
+ *        or @ref sd_ble_opt_set to set a new channel map. When setting the
+ *        channel map, it applies to all current and future connections. When getting the
+ *        current channel map, it applies to a single connection and the connection handle
+ *        must be supplied.
+ *
+ * @note  Setting the channel map may take some time, depending on connection parameters.
+ *        The time taken may be different for each connection and the get operation will
+ *        return the previous channel map until the new one has taken effect.
+ *
+ * @note  After setting the channel map, by spec it can not be set again until at least 1 s has passed.
+ *        See Bluetooth Specification Version 4.1 Volume 2, Part E, Section 7.3.46.
+ *
+ * @retval ::NRF_SUCCESS Get or set successful.
+ * @retval ::NRF_ERROR_BUSY Channel map was set again before enough time had passed.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied for get.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Returned by sd_ble_opt_set in peripheral-only SoftDevices.
+ *
+ */
+typedef struct
+{
+  uint16_t conn_handle;                   /**< Connection Handle (only applicable for get) */
+  uint8_t ch_map[5];                      /**< Channel Map (37-bit). */
+} ble_gap_opt_ch_map_t;
+
+
+/**@brief Local connection latency option.
+ *
+ *        Local connection latency is a feature which enables the slave to improve
+ *        current consumption by ignoring the slave latency set by the peer. The
+ *        local connection latency can only be set to a multiple of the slave latency,
+ *        and cannot be longer than half of the supervision timeout.
+ *
+ *        Used with @ref sd_ble_opt_set to set the local connection latency. The
+ *        @ref sd_ble_opt_get is not supported for this option, but the actual
+ *        local connection latency (unless set to NULL) is set as a return parameter
+ *        when setting the option.
+ *
+ * @note  The latency set will be truncated down to the closest slave latency event
+ *        multiple, or the nearest multiple before half of the supervision timeout.
+ *
+ * @note  The local connection latency is disabled by default, and needs to be enabled for new
+ *        connections and whenever the connection is updated.
+ *
+ * @retval ::NRF_SUCCESS Set successfully.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Get is not supported.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter.
+ */
+typedef struct
+{
+  uint16_t   conn_handle;                       /**< Connection Handle */
+  uint16_t   requested_latency;                 /**< Requested local connection latency. */
+  uint16_t * p_actual_latency;                  /**< Pointer to storage for the actual local connection latency (can be set to NULL to skip return value). */
+} ble_gap_opt_local_conn_latency_t;
+
+
+/**@brief Passkey Option.
+ *
+ *        Structure containing the passkey to be used during pairing. This can be used with @ref
+ *        sd_ble_opt_set to make the SoftDevice use a pre-programmed passkey for authentication
+ *        instead of generating a random one.
+ *
+ * @note  Repeated pairing attempts using the same pre-programmed passkey makes pairing vulnerable to MITM attacks.
+ *
+ * @note  @ref sd_ble_opt_get is not supported for this option.
+ *
+ */
+typedef struct
+{
+  uint8_t * p_passkey;                          /**< Pointer to 6-digit ASCII string (digit 0..9 only, no NULL termination) passkey to be used during pairing. If this is NULL, the SoftDevice will generate a random passkey if required.*/
+} ble_gap_opt_passkey_t;
+
+
+/**@brief Scan request report option.
+ *
+ *        This can be used with @ref sd_ble_opt_set to make the SoftDevice send
+ *        @ref BLE_GAP_EVT_SCAN_REQ_REPORT events.
+ *
+ *  @note   Due to the limited space reserved for scan request report events,
+ *          not all received scan requests will be reported.
+ *
+ *  @note   If whitelisting is used, only whitelisted requests are reported.
+ *
+ *  @retval ::NRF_SUCCESS Set successfully.
+ *  @retval ::NRF_ERROR_INVALID_STATE When advertising is ongoing while the option is set.
+ */
+typedef struct
+{
+   uint8_t enable : 1;                           /**< Enable scan request reports. */
+} ble_gap_opt_scan_req_report_t;
+
+
+/**@brief Compatibility mode option.
+ *
+ *        This can be used with @ref sd_ble_opt_set to enable and disable
+ *        compatibility modes. Compatibility modes are disabled by default.
+ *
+ *  @note  Compatibility mode 1 enables interoperability with devices that do not support
+ *         a value of 0 for the WinOffset parameter in the Link Layer CONNECT_REQ packet.
+ *
+ *  @retval ::NRF_SUCCESS Set successfully.
+ *  @retval ::NRF_ERROR_INVALID_STATE When connection creation is ongoing while mode 1 is set.
+ */
+typedef struct
+{
+   uint8_t mode_1_enable : 1;                           /**< Enable compatibility mode 1.*/
+} ble_gap_opt_compat_mode_t;
+
+/**@brief Data length extension option.
+ *
+ *        This can be used with @ref sd_ble_opt_set to enable longer data packets.
+ *
+ * @note  An rxtx_max_pdu_payload_size of 0 will result in the default minimum payload size of 27.
+ * @note  Not supported by SoftDevices for nRF51 Series devices.
+ * @note  The parameters for a connection are applied when a connection complete
+ *        event is generated for the host.
+ *
+ *
+ *  @retval ::NRF_SUCCESS Set successfully.
+ *  @retval ::NRF_ERROR_INVALID_PARAM If the payload size is not 0 or a valid link layer PDU payload size.
+ *  @retval ::NRF_ERROR_NOT_SUPPORTED If called on a SoftDevice designed for nRF51 (e.g. s130).
+ */
+typedef struct
+{
+  uint8_t  rxtx_max_pdu_payload_size;      /**< Max PDU payload size (in octets). */
+} ble_gap_opt_ext_len_t;
+
+
+
+/**@brief Authenticated payload timeout option.
+ *
+ * This can be used with @ref sd_ble_opt_set to change the Authenticated payload timeout to a value other than the default of 8 minutes.
+ *
+ * @note The authenticated payload timeout event ::BLE_GAP_TIMEOUT_SRC_AUTH_PAYLOAD will be generated
+ * if auth_payload_timeout time has elapsed without receiving a packet with a valid MIC on an encrypted
+ * link.
+ *
+ * @note  The LE ping procedure will be initiated before the timer expires to give the peer a chance
+ * to reset the timer. In addition the stack will try to prioritize running of LE ping over other
+ * activities to increase chances of finishing LE ping before timer expires. To avoid side-effects
+ * on other activities, it is recommended to use high timeout values.
+ * Recommended timeout > 2*(connInterval * (6 + connSlaveLatency)).
+ *
+ * @retval ::NRF_SUCCESS Set successfully.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. auth_payload_timeout was outside of allowed range.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter.
+ */
+typedef struct
+{
+  uint16_t   conn_handle;                       /**< Connection Handle */
+  uint16_t   auth_payload_timeout;              /**< Requested timeout in 10 ms unit. Maximum is 48 000 (=480 000 ms =8 min). Minimum is 1 (=10ms). */
+} ble_gap_opt_auth_payload_timeout_t;
+
+/**@brief Preferred PHY option
+ *
+ * @details This can be used with @ref sd_ble_opt_set to change the preferred PHYs. Before this function is called the PHYs
+ * for peer initiated PHY Update procedure is @ref BLE_GAP_PHY_1MBPS. If @ref ble_gap_opt_preferred_phys_t::tx_phys or
+ * @ref ble_gap_opt_preferred_phys_t::rx_phys is 0, then the stack will select PHYs based on the peer requirements on that specific direction.
+ *
+ * @note The preferred PHYs are only valid for newly created connections after this option is called. If the PHYs should be
+ * changed for an existing link the @ref sd_ble_gap_phy_request would have to be called, and that would try to update the
+ * PHYs for the given link.
+ *
+ * @note tx_phys and rx_phys are bitfields, to indicate multiple preferred PHYs for each direction they can be ORed together.
+ * @code
+ * tx_phys = BLE_GAP_PHY_1MBPS | BLE_GAP_PHY_2MBPS;
+ * rx_phys = BLE_GAP_PHY_1MBPS | BLE_GAP_PHY_2MBPS;
+ * @endcode
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_PHY_UPDATE, Result of the PHY Update if initiated by peer.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CENTRAL_PHY_REQUEST}
+ * @mmsc{@ref BLE_GAP_PERIPHERAL_PHY_REQUEST}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Set successfully.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ */
+typedef struct
+{
+  uint8_t  tx_phys;     /**< Preferred transmit PHYs, see @ref BLE_GAP_PHYS. */
+  uint8_t  rx_phys;     /**< Preferred receive PHYs, see @ref BLE_GAP_PHYS. */
+} ble_gap_opt_preferred_phys_t;
+
+/**@brief Option structure for GAP options. */
+typedef union
+{
+  ble_gap_opt_ch_map_t                  ch_map;                    /**< Parameters for the Channel Map option. */
+  ble_gap_opt_local_conn_latency_t      local_conn_latency;        /**< Parameters for the Local connection latency option */
+  ble_gap_opt_passkey_t                 passkey;                   /**< Parameters for the Passkey option.*/
+  ble_gap_opt_scan_req_report_t         scan_req_report;           /**< Parameters for the scan request report option.*/
+  ble_gap_opt_compat_mode_t             compat_mode;               /**< Parameters for the compatibility mode option.*/
+  ble_gap_opt_ext_len_t                 ext_len;                   /**< Parameters for the extended length option. */
+  ble_gap_opt_auth_payload_timeout_t    auth_payload_timeout;      /**< Parameters for the authenticated payload timeout option.*/
+  ble_gap_opt_preferred_phys_t          preferred_phys;            /**< Parameters for the preferred PHYs option. */
+} ble_gap_opt_t;
+/**@} */
+
+
+/**@addtogroup BLE_GAP_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Set the local Bluetooth identity address.
+ *
+ * The local Bluetooth identity address is the address that identifies this device to other peers.
+ * The address type must be either @ref BLE_GAP_ADDR_TYPE_PUBLIC or @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC.
+ * The identity address cannot be changed while roles are running.
+ *
+ * @note This address will be distributed to the peer during bonding.
+ * If the address changes, the address stored in the peer device will not be valid and the ability to
+ * reconnect using the old address will be lost.
+ *
+ * @note By default the SoftDevice will set an address of type @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC upon being
+ * enabled. The address is a random number populated during the IC manufacturing process and remains unchanged
+ * for the lifetime of each IC.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_ADV_MSC}
+ * @endmscs
+ *
+ * @param[in] p_addr Pointer to address structure.
+ *
+ * @retval ::NRF_SUCCESS Address successfully set.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address.
+ * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
+ * @retval ::NRF_ERROR_INVALID_STATE The identity address cannot be changed while the roles are running.
+ */
+SVCALL(SD_BLE_GAP_ADDR_SET, uint32_t, sd_ble_gap_addr_set(ble_gap_addr_t const *p_addr));
+
+
+/**@brief Get local Bluetooth identity address.
+ *
+ * @note This will always return the identity address irrespective of the privacy settings,
+ * i.e. the address type will always be either @ref BLE_GAP_ADDR_TYPE_PUBLIC or @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC.
+ *
+ * @param[out] p_addr Pointer to address structure to be filled in.
+ *
+ * @retval ::NRF_SUCCESS Address successfully retrieved.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid or NULL pointer supplied.
+ */
+SVCALL(SD_BLE_GAP_ADDR_GET, uint32_t, sd_ble_gap_addr_get(ble_gap_addr_t *p_addr));
+
+
+/**@brief Set the active whitelist in the SoftDevice.
+ *
+ * @note Only one whitelist can be used at a time and the whitelist is shared between the BLE roles.
+ *       The whitelist cannot be set if a BLE role is using the whitelist.
+ *
+ * @note If an address is resolved using the information in the device identity list, then the whitelist
+ *       filter policy applies to the peer identity address and not the resolvable address sent on air.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_PRIVATE_SCAN_MSC}
+ * @endmscs
+ *
+ * @param[in] pp_wl_addrs Pointer to a whitelist of peer addresses, if NULL the whitelist will be cleared.
+ * @param[in] len         Length of the whitelist, maximum @ref BLE_GAP_WHITELIST_ADDR_MAX_COUNT.
+ *
+ * @retval ::NRF_SUCCESS The whitelist is successfully set/cleared.
+ * @retval ::NRF_ERROR_INVALID_ADDR The whitelist (or one of its entries) provided is invalid.
+ * @retval ::BLE_ERROR_GAP_WHITELIST_IN_USE The whitelist is in use by a BLE role and cannot be set or cleared.
+ * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address type is supplied.
+ * @retval ::NRF_ERROR_DATA_SIZE The given whitelist size is invalid (zero or too large); this can only return when
+ *                               pp_wl_addrs is not NULL.
+ */
+SVCALL(SD_BLE_GAP_WHITELIST_SET, uint32_t, sd_ble_gap_whitelist_set(ble_gap_addr_t const * const * pp_wl_addrs, uint8_t len));
+
+
+/**@brief Set device identity list.
+ *
+ * @note Only one device identity list can be used at a time and the list is shared between the BLE roles.
+ *       The device identity list cannot be set if a BLE role is using the list.
+ *
+ * @param[in] pp_id_keys     Pointer to an array of peer identity addresses and peer IRKs, if NULL the device identity list will be cleared.
+ * @param[in] pp_local_irks  Pointer to an array of local IRKs. Each entry in the array maps to the entry in pp_id_keys at the same index.
+ *                           To fill in the list with the currently set device IRK for all peers, set to NULL.
+ * @param[in] len            Length of the device identity list, maximum @ref BLE_GAP_DEVICE_IDENTITIES_MAX_COUNT.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PRIVACY_ADV_MSC}
+ * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_MSC}
+ * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_PRIVATE_SCAN_MSC}
+ * @mmsc{@ref BLE_GAP_PRIVACY_ADV_DIR_PRIV_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_CONN_PRIV_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_CONN_PRIV_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS The device identity list successfully set/cleared.
+ * @retval ::NRF_ERROR_INVALID_ADDR The device identity list (or one of its entries) provided is invalid.
+                                    This code may be returned if the local IRK list also has an invalid entry.
+ * @retval ::BLE_ERROR_GAP_DEVICE_IDENTITIES_IN_USE The device identity list is in use and cannot be set or cleared.
+ * @retval ::BLE_ERROR_GAP_DEVICE_IDENTITIES_DUPLICATE The device identity list contains multiple entries with the same identity address.
+ * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address type is supplied.
+ * @retval ::NRF_ERROR_DATA_SIZE The given device identity list size invalid (zero or too large); this can
+ *                               only return when pp_id_keys is not NULL.
+ */
+SVCALL(SD_BLE_GAP_DEVICE_IDENTITIES_SET, uint32_t, sd_ble_gap_device_identities_set(ble_gap_id_key_t const * const * pp_id_keys, ble_gap_irk_t const * const * pp_local_irks, uint8_t len));
+
+
+/**@brief Set privacy settings.
+ *
+ * @note Privacy settings cannot be set while BLE roles are running.
+ *
+ * @param[in] p_privacy_params Privacy settings.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PRIVACY_ADV_MSC}
+ * @mmsc{@ref BLE_GAP_PRIVACY_SCAN_MSC}
+ * @mmsc{@ref BLE_GAP_PRIVACY_ADV_DIR_PRIV_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Set successfully.
+ * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
+ * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address type is supplied.
+ * @retval ::NRF_ERROR_INVALID_ADDR The pointer to privacy settings is NULL or invalid.
+                                    Otherwise, the p_device_irk pointer in privacy parameter is an invalid pointer.
+ * @retval ::NRF_ERROR_INVALID_PARAM Out of range parameters are provided.
+ * @retval ::NRF_ERROR_INVALID_STATE Privacy settings cannot be changed while BLE roles using privacy are enabled.
+  */
+SVCALL(SD_BLE_GAP_PRIVACY_SET, uint32_t, sd_ble_gap_privacy_set(ble_gap_privacy_params_t const *p_privacy_params));
+
+
+/**@brief Get privacy settings.
+ *
+ * @note The privacy settings returned include the current device irk as well.
+ *
+ * @param[in] p_privacy_params Privacy settings.
+ *
+ * @retval ::NRF_SUCCESS            Privacy settings read.
+ * @retval ::NRF_ERROR_INVALID_ADDR The pointer given for returning the privacy settings may be NULL or invalid.
+                                    Otherwise, the p_device_irk pointer in privacy parameter is an invalid pointer.
+ */
+SVCALL(SD_BLE_GAP_PRIVACY_GET, uint32_t, sd_ble_gap_privacy_get(ble_gap_privacy_params_t *p_privacy_params));
+
+
+/**@brief Set, clear or update advertising and scan response data.
+ *
+ * @note The format of the advertising data will be checked by this call to ensure interoperability.
+ *       Limitations imposed by this API call to the data provided include having a flags data type in the scan response data and
+ *       duplicating the local name in the advertising data and scan response data.
+ *
+ * @note To clear the advertising data and set it to a 0-length packet, simply provide a valid pointer (p_data/p_sr_data) with its corresponding
+ *        length (dlen/srdlen) set to 0.
+ *
+ * @note The call will fail if p_data and p_sr_data are both NULL since this would have no effect.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_ADV_MSC}
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @endmscs
+ *
+ * @param[in] p_data    Raw data to be placed in advertising packet. If NULL, no changes are made to the current advertising packet data.
+ * @param[in] dlen      Data length for p_data. Max size: @ref BLE_GAP_ADV_MAX_SIZE octets. Should be 0 if p_data is NULL, can be 0 if p_data is not NULL.
+ * @param[in] p_sr_data Raw data to be placed in scan response packet. If NULL, no changes are made to the current scan response packet data.
+ * @param[in] srdlen    Data length for p_sr_data. Max size: @ref BLE_GAP_ADV_MAX_SIZE octets. Should be 0 if p_sr_data is NULL, can be 0 if p_data is not NULL.
+ *
+ * @retval ::NRF_SUCCESS Advertising data successfully updated or cleared.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, both p_data and p_sr_data cannot be NULL.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_FLAGS Invalid combination of advertising flags supplied.
+ * @retval ::NRF_ERROR_INVALID_DATA Invalid data type(s) supplied, check the advertising data format specification.
+ * @retval ::NRF_ERROR_INVALID_LENGTH Invalid data length(s) supplied.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Unsupported data type.
+ * @retval ::BLE_ERROR_GAP_UUID_LIST_MISMATCH Invalid UUID list supplied.
+ */
+SVCALL(SD_BLE_GAP_ADV_DATA_SET, uint32_t, sd_ble_gap_adv_data_set(uint8_t const *p_data, uint8_t dlen, uint8_t const *p_sr_data, uint8_t srdlen));
+
+
+/**@brief Start advertising (GAP Discoverable, Connectable modes, Broadcast Procedure).
+ *
+ * @note An application can start an advertising procedure for broadcasting purposes while a connection
+ *       is active. After a @ref BLE_GAP_EVT_CONNECTED event is received, this function may therefore
+ *       be called to start a broadcast advertising procedure. The advertising procedure
+ *       cannot however be connectable (it must be of type @ref BLE_GAP_ADV_TYPE_ADV_SCAN_IND or
+ *       @ref BLE_GAP_ADV_TYPE_ADV_NONCONN_IND). @note Only one advertiser may be active at any time.
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_CONNECTED, Generated after connection has been established through connectable advertising.}
+ * @event{@ref BLE_GAP_EVT_TIMEOUT, Advertisement has timed out.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_ADV_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_CONN_PRIV_MSC}
+ * @mmsc{@ref BLE_GAP_PRIVACY_ADV_DIR_PRIV_MSC}
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @endmscs
+ *
+ * @param[in] p_adv_params Pointer to advertising parameters structure.
+ *
+ * @retval ::NRF_SUCCESS The BLE stack has started advertising.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::NRF_ERROR_CONN_COUNT The limit of available connections has been reached; connectable advertiser cannot be started.
+ * @retval ::NRF_ERROR_NO_MEM The configured memory pools (see @ref ble_conn_bw_counts_t) are not large enough for the
+ *                            bandwidth selected for this connection.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check the accepted ranges and limits.
+ * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid Bluetooth address supplied.
+ * @retval ::BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST Discoverable mode and whitelist incompatible.
+ * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
+ * @retval ::NRF_ERROR_RESOURCES Not enough BLE role slots available.
+ *                               Stop one or more currently active roles (Central, Peripheral or Observer) and try again
+ */
+SVCALL(SD_BLE_GAP_ADV_START, uint32_t, sd_ble_gap_adv_start(ble_gap_adv_params_t const *p_adv_params));
+
+
+/**@brief Stop advertising (GAP Discoverable, Connectable modes, Broadcast Procedure).
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_ADV_MSC}
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS The BLE stack has stopped advertising.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation (most probably not in advertising state).
+ */
+SVCALL(SD_BLE_GAP_ADV_STOP, uint32_t, sd_ble_gap_adv_stop(void));
+
+
+/**@brief Update connection parameters.
+ *
+ * @details In the central role this will initiate a Link Layer connection parameter update procedure,
+ *          otherwise in the peripheral role, this will send the corresponding L2CAP request and wait for
+ *          the central to perform the procedure. In both cases, and regardless of success or failure, the application
+ *          will be informed of the result with a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE event.
+ *
+ * @details This function can be used as a central both to reply to a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST or to start the procedure unrequested.
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_CONN_PARAM_UPDATE, Result of the connection parameter update procedure.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CPU_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC}
+ * @mmsc{@ref BLE_GAP_MULTILINK_CPU_MSC}
+ * @mmsc{@ref BLE_GAP_MULTILINK_CTRL_PROC_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_CPU_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] p_conn_params  Pointer to desired connection parameters. If NULL is provided on a peripheral role,
+ *                           the parameters in the PPCP characteristic of the GAP service will be used instead.
+ *                           If NULL is provided on a central role and in response to a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST, the peripheral request will be rejected
+ *
+ * @retval ::NRF_SUCCESS The Connection Update procedure has been started successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::NRF_ERROR_BUSY Procedure already in progress or not allowed at this time, process pending events and wait for pending procedures to complete and retry.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ */
+SVCALL(SD_BLE_GAP_CONN_PARAM_UPDATE, uint32_t, sd_ble_gap_conn_param_update(uint16_t conn_handle, ble_gap_conn_params_t const *p_conn_params));
+
+
+/**@brief Disconnect (GAP Link Termination).
+ *
+ * @details This call initiates the disconnection procedure, and its completion will be communicated to the application
+ *          with a @ref BLE_GAP_EVT_DISCONNECTED event.
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_DISCONNECTED, Generated when disconnection procedure is complete.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CONN_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] hci_status_code HCI status code, see @ref BLE_HCI_STATUS_CODES (accepted values are @ref BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION and @ref BLE_HCI_CONN_INTERVAL_UNACCEPTABLE).
+ *
+ * @retval ::NRF_SUCCESS The disconnection procedure has been started successfully.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation (disconnection is already in progress).
+ */
+SVCALL(SD_BLE_GAP_DISCONNECT, uint32_t, sd_ble_gap_disconnect(uint16_t conn_handle, uint8_t hci_status_code));
+
+
+/**@brief Set the radio's transmit power.
+ *
+ * @param[in] tx_power Radio transmit power in dBm (accepted values are -40, -20, -16, -12, -8, -4, 0, 2, 3, 4, 5, 6, 7, 8 and 9 dBm).
+ *
+ * @note The -40dBm, -20dBm, -16dBm, -12dBm, -8dBm, -4dBm, 0dBm, +2dBm, +3dBm, +4dBm, +5dBm, +6dBm, +7dBm, +8dBm and +9dBm settings are available on nRF52840 series ICs.
+ * @note The -40dBm, -20dBm, -16dBm, -12dBm, -8dBm, -4dBm, 0dBm, +3dBm and +4dBm settings are available on nRF52 series ICs.
+ *
+ * @retval ::NRF_SUCCESS Successfully changed the transmit power.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ */
+SVCALL(SD_BLE_GAP_TX_POWER_SET, uint32_t, sd_ble_gap_tx_power_set(int8_t tx_power));
+
+
+/**@brief Set GAP Appearance value.
+ *
+ * @param[in] appearance Appearance (16-bit), see @ref BLE_APPEARANCES.
+ *
+ * @retval ::NRF_SUCCESS  Appearance value set successfully.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ */
+SVCALL(SD_BLE_GAP_APPEARANCE_SET, uint32_t, sd_ble_gap_appearance_set(uint16_t appearance));
+
+
+/**@brief Get GAP Appearance value.
+ *
+ * @param[out] p_appearance Pointer to appearance (16-bit) to be filled in, see @ref BLE_APPEARANCES.
+ *
+ * @retval ::NRF_SUCCESS Appearance value retrieved successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ */
+SVCALL(SD_BLE_GAP_APPEARANCE_GET, uint32_t, sd_ble_gap_appearance_get(uint16_t *p_appearance));
+
+
+/**@brief Set GAP Peripheral Preferred Connection Parameters.
+ *
+ * @param[in] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure with the desired parameters.
+ *
+ * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters set successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ */
+SVCALL(SD_BLE_GAP_PPCP_SET, uint32_t, sd_ble_gap_ppcp_set(ble_gap_conn_params_t const *p_conn_params));
+
+
+/**@brief Get GAP Peripheral Preferred Connection Parameters.
+ *
+ * @param[out] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure where the parameters will be stored.
+ *
+ * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters retrieved successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ */
+SVCALL(SD_BLE_GAP_PPCP_GET, uint32_t, sd_ble_gap_ppcp_get(ble_gap_conn_params_t *p_conn_params));
+
+
+/**@brief Set GAP device name.
+ *
+ * @param[in] p_write_perm Write permissions for the Device Name characteristic, see @ref ble_gap_conn_sec_mode_t.
+ * @param[in] p_dev_name Pointer to a UTF-8 encoded, <b>non NULL-terminated</b> string.
+ * @param[in] len Length of the UTF-8, <b>non NULL-terminated</b> string pointed to by p_dev_name in octets (must be smaller or equal than @ref BLE_GAP_DEVNAME_MAX_LEN).
+ *
+ * @note If the device name is located in application flash memory (see @ref ble_gap_device_name_t), it cannot be changed. Then @ref NRF_ERROR_FORBIDDEN will be returned.
+ *
+ * @retval ::NRF_SUCCESS GAP device name and permissions set successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
+ * @retval ::NRF_ERROR_FORBIDDEN Device name is not writable.
+ */
+SVCALL(SD_BLE_GAP_DEVICE_NAME_SET, uint32_t, sd_ble_gap_device_name_set(ble_gap_conn_sec_mode_t const *p_write_perm, uint8_t const *p_dev_name, uint16_t len));
+
+
+/**@brief Get GAP device name.
+ *
+ * @note          If the device name is longer than the size of the supplied buffer,
+ *                p_len will return the complete device name length,
+ *                and not the number of bytes actually returned in p_dev_name.
+ *                The application may use this information to allocate a suitable buffer size.
+ *
+ * @param[out]    p_dev_name Pointer to an empty buffer where the UTF-8 <b>non NULL-terminated</b> string will be placed. Set to NULL to obtain the complete device name length.
+ * @param[in,out] p_len      Length of the buffer pointed by p_dev_name, complete device name length on output.
+ *
+ * @retval ::NRF_SUCCESS GAP device name retrieved successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
+ */
+SVCALL(SD_BLE_GAP_DEVICE_NAME_GET, uint32_t, sd_ble_gap_device_name_get(uint8_t *p_dev_name, uint16_t *p_len));
+
+
+/**@brief Initiate the GAP Authentication procedure.
+ *
+ * @details In the central role, this function will send an SMP Pairing Request (or an SMP Pairing Failed if rejected),
+ *          otherwise in the peripheral role, an SMP Security Request will be sent.
+ *
+ * @events
+ * @event{Depending on the security parameters set and the packet exchanges with the peer\, the following events may be generated:}
+ * @event{@ref BLE_GAP_EVT_SEC_PARAMS_REQUEST}
+ * @event{@ref BLE_GAP_EVT_SEC_INFO_REQUEST}
+ * @event{@ref BLE_GAP_EVT_PASSKEY_DISPLAY}
+ * @event{@ref BLE_GAP_EVT_KEY_PRESSED}
+ * @event{@ref BLE_GAP_EVT_AUTH_KEY_REQUEST}
+ * @event{@ref BLE_GAP_EVT_LESC_DHKEY_REQUEST}
+ * @event{@ref BLE_GAP_EVT_CONN_SEC_UPDATE}
+ * @event{@ref BLE_GAP_EVT_AUTH_STATUS}
+ * @event{@ref BLE_GAP_EVT_TIMEOUT}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_SEC_REQ_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_SEC_REQ_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] p_sec_params Pointer to the @ref ble_gap_sec_params_t structure with the security parameters to be used during the pairing or bonding procedure.
+ *                         In the peripheral role, only the bond, mitm, lesc and keypress fields of this structure are used.
+ *                         In the central role, this pointer may be NULL to reject a Security Request.
+ *
+ * @retval ::NRF_SUCCESS Successfully initiated authentication procedure.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
+ * @retval ::NRF_ERROR_NO_MEM The maximum number of authentication procedures that can run in parallel for the given role is reached.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Setting of sign or link fields in @ref ble_gap_sec_kdist_t not supported.
+ * @retval ::NRF_ERROR_TIMEOUT A SMP timeout has occurred, and further SMP operations on this link is prohibited.
+ */
+SVCALL(SD_BLE_GAP_AUTHENTICATE, uint32_t, sd_ble_gap_authenticate(uint16_t conn_handle, ble_gap_sec_params_t const *p_sec_params));
+
+
+/**@brief Reply with GAP security parameters.
+ *
+ * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE.
+ * @note    If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
+ *
+ * @events
+ * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_BONDING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_PERIPH_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_CENTRAL_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_BONDING_STATIC_PK_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_CONFIRM_FAIL_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_PD_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_KS_TOO_SMALL_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_APP_ERROR_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_REMOTE_PAIRING_FAIL_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_TIMEOUT_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] sec_status Security status, see @ref BLE_GAP_SEC_STATUS.
+ * @param[in] p_sec_params Pointer to a @ref ble_gap_sec_params_t security parameters structure. In the central role this must be set to NULL, as the parameters have
+ *                         already been provided during a previous call to @ref sd_ble_gap_authenticate.
+ * @param[in,out] p_sec_keyset Pointer to a @ref ble_gap_sec_keyset_t security keyset structure. Any keys generated and/or distributed as a result of the ongoing security procedure
+ *                         will be stored into the memory referenced by the pointers inside this structure. The keys will be stored and available to the application
+ *                         upon reception of a @ref BLE_GAP_EVT_AUTH_STATUS event.
+ *                         Note that the SoftDevice expects the application to provide memory for storing the
+ *                         peer's keys. So it must be ensured that the relevant pointers inside this structure are not NULL. The pointers to the local key
+ *                         can, however, be NULL, in which case, the local key data will not be available to the application upon reception of the
+ *                         @ref BLE_GAP_EVT_AUTH_STATUS event.
+ *
+ * @retval ::NRF_SUCCESS Successfully accepted security parameter from the application.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Setting of sign or link fields in @ref ble_gap_sec_kdist_t not supported.
+ */
+SVCALL(SD_BLE_GAP_SEC_PARAMS_REPLY, uint32_t, sd_ble_gap_sec_params_reply(uint16_t conn_handle, uint8_t sec_status, ble_gap_sec_params_t const *p_sec_params, ble_gap_sec_keyset_t const *p_sec_keyset));
+
+
+/**@brief Reply with an authentication key.
+ *
+ * @details This function is only used to reply to a @ref BLE_GAP_EVT_AUTH_KEY_REQUEST or a @ref BLE_GAP_EVT_PASSKEY_DISPLAY, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE.
+ * @note    If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
+ *
+ * @events
+ * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_CENTRAL_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] key_type See @ref BLE_GAP_AUTH_KEY_TYPES.
+ * @param[in] p_key If key type is @ref BLE_GAP_AUTH_KEY_TYPE_NONE, then NULL.
+ *                  If key type is @ref BLE_GAP_AUTH_KEY_TYPE_PASSKEY, then a 6-byte ASCII string (digit 0..9 only, no NULL termination)
+ *                     or NULL when confirming LE Secure Connections Numeric Comparison.
+ *                  If key type is @ref BLE_GAP_AUTH_KEY_TYPE_OOB, then a 16-byte OOB key value in Little Endian format.
+ *
+ * @retval ::NRF_SUCCESS Authentication key successfully set.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_AUTH_KEY_REPLY, uint32_t, sd_ble_gap_auth_key_reply(uint16_t conn_handle, uint8_t key_type, uint8_t const *p_key));
+
+/**@brief Reply with an LE Secure connections DHKey.
+ *
+ * @details This function is only used to reply to a @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE.
+ * @note    If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
+ *
+ * @events
+ * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_PD_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] p_dhkey LE Secure Connections DHKey.
+ *
+ * @retval ::NRF_SUCCESS DHKey successfully set.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_LESC_DHKEY_REPLY, uint32_t, sd_ble_gap_lesc_dhkey_reply(uint16_t conn_handle, ble_gap_lesc_dhkey_t const *p_dhkey));
+
+/**@brief Notify the peer of a local keypress.
+ *
+ * @details This function can only be used when an authentication procedure using LE Secure Connection is in progress. Calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] kp_not See @ref BLE_GAP_KP_NOT_TYPES.
+ *
+ * @retval ::NRF_SUCCESS Keypress notification successfully queued for transmission.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either not entering a passkey or keypresses have not been enabled by both peers.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_BUSY The BLE stack is busy. Retry at later time.
+ */
+SVCALL(SD_BLE_GAP_KEYPRESS_NOTIFY, uint32_t, sd_ble_gap_keypress_notify(uint16_t conn_handle, uint8_t kp_not));
+
+/**@brief Generate a set of OOB data to send to a peer out of band.
+ *
+ * @note The @ref ble_gap_addr_t included in the OOB data returned will be the currently active one (or, if a connection has already been established,
+ *       the one used during connection setup). The application may manually overwrite it with an updated value.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle. Can be BLE_CONN_HANDLE_INVALID if a BLE connection has not been established yet.
+ * @param[in] p_pk_own LE Secure Connections local P-256 Public Key.
+ * @param[out] p_oobd_own The OOB data to be sent out of band to a peer.
+ *
+ * @retval ::NRF_SUCCESS OOB data successfully generated.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_LESC_OOB_DATA_GET, uint32_t, sd_ble_gap_lesc_oob_data_get(uint16_t conn_handle, ble_gap_lesc_p256_pk_t const *p_pk_own, ble_gap_lesc_oob_data_t *p_oobd_own));
+
+/**@brief Provide the OOB data sent/received out of band.
+ *
+ * @note An authentication procedure with OOB selected as an algorithm must be in progress when calling this function.
+ * @note A @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST event with the oobd_req set to 1 must have been received prior to calling this function.
+ *
+ * @events
+ * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] p_oobd_own The OOB data sent out of band to a peer or NULL if the peer has not received OOB data.
+ *                       Must correspond to @ref ble_gap_sec_params_t::oob flag in @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST.
+ * @param[in] p_oobd_peer The OOB data received out of band from a peer or NULL if none received.
+ *                        Must correspond to @ref ble_gap_sec_params_t::oob flag in @ref sd_ble_gap_authenticate in the central role
+ *                        or @ref sd_ble_gap_sec_params_reply in the peripheral role.
+ *
+ * @retval ::NRF_SUCCESS OOB data accepted.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_LESC_OOB_DATA_SET, uint32_t, sd_ble_gap_lesc_oob_data_set(uint16_t conn_handle, ble_gap_lesc_oob_data_t const *p_oobd_own, ble_gap_lesc_oob_data_t const *p_oobd_peer));
+
+/**@brief Initiate GAP Encryption procedure.
+ *
+ * @details In the central role, this function will initiate the encryption procedure using the encryption information provided.
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_CONN_SEC_UPDATE, The connection security has been updated.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_ENC_MSC}
+ * @mmsc{@ref BLE_GAP_MULTILINK_CTRL_PROC_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_SEC_REQ_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] p_master_id Pointer to a @ref ble_gap_master_id_t master identification structure.
+ * @param[in] p_enc_info  Pointer to a @ref ble_gap_enc_info_t encryption information structure.
+ *
+ * @retval ::NRF_SUCCESS Successfully initiated authentication procedure.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::BLE_ERROR_INVALID_ROLE Operation is not supported in the Peripheral role.
+ * @retval ::NRF_ERROR_BUSY Procedure already in progress or not allowed at this time, wait for pending procedures to complete and retry.
+ */
+SVCALL(SD_BLE_GAP_ENCRYPT, uint32_t, sd_ble_gap_encrypt(uint16_t conn_handle, ble_gap_master_id_t const *p_master_id, ble_gap_enc_info_t const *p_enc_info));
+
+
+/**@brief Reply with GAP security information.
+ *
+ * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_INFO_REQUEST, calling it at other times will result in @ref NRF_ERROR_INVALID_STATE.
+ * @note    If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
+ * @note    Data signing is not yet supported, and p_sign_info must therefore be NULL.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_ENC_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] p_enc_info Pointer to a @ref ble_gap_enc_info_t encryption information structure. May be NULL to signal none is available.
+ * @param[in] p_id_info Pointer to a @ref ble_gap_irk_t identity information structure. May be NULL to signal none is available.
+ * @param[in] p_sign_info Pointer to a @ref ble_gap_sign_info_t signing information structure. May be NULL to signal none is available.
+ *
+ * @retval ::NRF_SUCCESS Successfully accepted security information.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_SEC_INFO_REPLY, uint32_t, sd_ble_gap_sec_info_reply(uint16_t conn_handle, ble_gap_enc_info_t const *p_enc_info, ble_gap_irk_t const *p_id_info, ble_gap_sign_info_t const *p_sign_info));
+
+
+/**@brief Get the current connection security.
+ *
+ * @param[in]  conn_handle Connection handle.
+ * @param[out] p_conn_sec  Pointer to a @ref ble_gap_conn_sec_t structure to be filled in.
+ *
+ * @retval ::NRF_SUCCESS Current connection security successfully retrieved.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_CONN_SEC_GET, uint32_t, sd_ble_gap_conn_sec_get(uint16_t conn_handle, ble_gap_conn_sec_t *p_conn_sec));
+
+
+/**@brief Start reporting the received signal strength to the application.
+ *
+ * A new event is reported whenever the RSSI value changes, until @ref sd_ble_gap_rssi_stop is called.
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_RSSI_CHANGED, New RSSI data available. How often the event is generated is
+                                         dependent on the settings of the <code>threshold_dbm</code>
+                                         and <code>skip_count</code> input parameters.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC}
+ * @mmsc{@ref BLE_GAP_RSSI_FILT_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle        Connection handle.
+ * @param[in] threshold_dbm      Minimum change in dBm before triggering the @ref BLE_GAP_EVT_RSSI_CHANGED event. Events are disabled if threshold_dbm equals @ref BLE_GAP_RSSI_THRESHOLD_INVALID.
+ * @param[in] skip_count         Number of RSSI samples with a change of threshold_dbm or more before sending a new @ref BLE_GAP_EVT_RSSI_CHANGED event.
+ *
+ * @retval ::NRF_SUCCESS                   Successfully activated RSSI reporting.
+ * @retval ::NRF_ERROR_INVALID_STATE       Disconnection in progress. Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_RSSI_START, uint32_t, sd_ble_gap_rssi_start(uint16_t conn_handle, uint8_t threshold_dbm, uint8_t skip_count));
+
+
+/**@brief Stop reporting the received signal strength.
+ *
+ * @note An RSSI change detected before the call but not yet received by the application
+ * may be reported after @ref sd_ble_gap_rssi_stop has been called.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC}
+ * @mmsc{@ref BLE_GAP_RSSI_FILT_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ *
+ * @retval ::NRF_SUCCESS                   Successfully deactivated RSSI reporting.
+ * @retval ::NRF_ERROR_INVALID_STATE       Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_RSSI_STOP, uint32_t, sd_ble_gap_rssi_stop(uint16_t conn_handle));
+
+
+/**@brief Get the received signal strength for the last connection event.
+ *
+ * @ref sd_ble_gap_rssi_start must be called to start reporting RSSI before using this function. @ref NRF_ERROR_NOT_FOUND
+ * will be returned until RSSI was sampled for the first time after calling @ref sd_ble_gap_rssi_start.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC}
+ * @endmscs
+ *
+ * @param[in]  conn_handle Connection handle.
+ * @param[out] p_rssi      Pointer to the location where the RSSI measurement shall be stored.
+ *
+ * @retval ::NRF_SUCCESS                   Successfully read the RSSI.
+ * @retval ::NRF_ERROR_NOT_FOUND           No sample is available.
+ * @retval ::NRF_ERROR_INVALID_ADDR        Invalid pointer supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE       RSSI reporting is not ongoing, or disconnection in progress.
+ */
+SVCALL(SD_BLE_GAP_RSSI_GET, uint32_t, sd_ble_gap_rssi_get(uint16_t conn_handle, int8_t *p_rssi));
+
+
+/**@brief Start scanning (GAP Discovery procedure, Observer Procedure).
+ *
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_ADV_REPORT, An advertising or scan response packet has been received.}
+ * @event{@ref BLE_GAP_EVT_TIMEOUT, Scanner has timed out.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_SCAN_MSC}
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @endmscs
+ *
+ * @param[in] p_scan_params Pointer to scan parameters structure.
+ *
+ * @retval ::NRF_SUCCESS Successfully initiated scanning procedure.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
+ * @retval ::NRF_ERROR_RESOURCES Not enough BLE role slots available.
+ *                               Stop one or more currently active roles (Central, Peripheral or Broadcaster) and try again
+ */
+SVCALL(SD_BLE_GAP_SCAN_START, uint32_t, sd_ble_gap_scan_start(ble_gap_scan_params_t const *p_scan_params));
+
+
+/**@brief Stop scanning (GAP Discovery procedure, Observer Procedure).
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_SCAN_MSC}
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Successfully stopped scanning procedure.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation (most probably not in scanning state).
+ */
+SVCALL(SD_BLE_GAP_SCAN_STOP, uint32_t, sd_ble_gap_scan_stop(void));
+
+
+/**@brief Create a connection (GAP Link Establishment).
+ *
+ * @note If a scanning procedure is currently in progress it will be automatically stopped when calling this function.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_CONN_PRIV_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_CONN_MSC}
+ * @endmscs
+ *
+ * @param[in] p_peer_addr   Pointer to peer address. If the use_whitelist bit is set in @ref ble_gap_scan_params_t, then this is ignored.
+ *                          If @ref ble_gap_addr_t::addr_id_peer is set then p_peer_addr must be present in the device identity list
+ *                          see @ref sd_ble_gap_device_identities_set.
+ * @param[in] p_scan_params Pointer to scan parameters structure.
+ * @param[in] p_conn_params Pointer to desired connection parameters.
+ *
+ * @retval ::NRF_SUCCESS Successfully initiated connection procedure.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid parameter(s) pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+                                     - Invalid parameter(s) in p_scan_params or p_conn_params.
+                                     - Use of whitelist requested but whitelist has not been set, see @ref sd_ble_gap_whitelist_set.
+                                     - Peer address was not present in the device identity list, see @ref sd_ble_gap_device_identities_set.
+ * @retval ::NRF_ERROR_INVALID_STATE The SoftDevice is in an invalid state to perform this operation. This may be due to an
+ *                                   existing locally initiated connect procedure, which must complete before initiating again.
+ * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid Peer address.
+ * @retval ::NRF_ERROR_CONN_COUNT The limit of available connections has been reached.
+ * @retval ::NRF_ERROR_NO_MEM The configured memory pool (see @ref ble_conn_bw_counts_t) is not large enough for the
+ *                            bandwidth selected for this connection.
+ * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. If another connection is being established
+ *                          wait for the corresponding @ref BLE_GAP_EVT_CONNECTED event before calling again.
+ * @retval ::NRF_ERROR_RESOURCES Not enough BLE role slots available.
+ *                               Stop one or more currently active roles (Central, Peripheral or Broadcaster) and try again
+ */
+SVCALL(SD_BLE_GAP_CONNECT, uint32_t, sd_ble_gap_connect(ble_gap_addr_t const *p_peer_addr, ble_gap_scan_params_t const *p_scan_params, ble_gap_conn_params_t const *p_conn_params));
+
+
+/**@brief Cancel a connection establishment.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CENTRAL_CONN_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Successfully cancelled an ongoing connection procedure.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ */
+SVCALL(SD_BLE_GAP_CONNECT_CANCEL, uint32_t, sd_ble_gap_connect_cancel(void));
+
+
+/**@brief PHY Update Request
+ *
+ * @details   This function is used to request a new PHY configuration for a central or a peripheral connection. It will always generate a
+ *            @ref BLE_GAP_EVT_PHY_UPDATE event if successfully executed. If @ref ble_gap_phys_t::tx_phys or @ref ble_gap_phys_t::rx_phys
+ *            is 0, then the stack will select PHYs based on the peer requirements on that specific direction. If the peer does not support
+ *            the PHY Update procedure, then the resulting @ref BLE_GAP_EVT_PHY_UPDATE event will have a status different from 
+ *            @ref BLE_HCI_STATUS_CODE_SUCCESS.
+ *
+ * @note      The requested PHYs does not have to be within the set of the preferred PHYs.
+ *
+ * @note      If the @ref ble_gap_opt_preferred_phys_t have not been configured with @ref BLE_GAP_PHY_CODED, then this call might return
+ *            @ref BLE_ERROR_BLOCKED_BY_OTHER_LINKS if there are multiple devices connected.
+ *
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_PHY_UPDATE, Result of the PHY Update procedure procedure.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CENTRAL_PHY_REQUEST}
+ * @mmsc{@ref BLE_GAP_PERIPHERAL_PHY_REQUEST}
+ * @endmscs
+ *
+ * @param[in] conn_handle   Connection handle to indicate the connection for which the PHY Update is requested.
+ * @param[in] p_gap_phys    Pointer to PHY structure.
+ *
+ * @retval ::NRF_SUCCESS Successfully requested a PHY Update.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Unsupported PHYs supplied to the call.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_BLOCKED_BY_OTHER_LINKS Other connections may block the scheduling of the current link.
+ * @retval ::NRF_ERROR_BUSY Procedure is already in progress or not allowed at this time. Process pending events and wait for the pending procedure to complete and retry.
+ *
+ */
+SVCALL(SD_BLE_GAP_PHY_REQUEST, uint32_t, sd_ble_gap_phy_request(uint16_t conn_handle, ble_gap_phys_t const *p_gap_phys));
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // BLE_GAP_H__
+
+/**
+  @}
+*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_gatt.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,222 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+  @addtogroup BLE_GATT Generic Attribute Profile (GATT) Common
+  @{
+  @brief  Common definitions and prototypes for the GATT interfaces.
+ */
+
+#ifndef BLE_GATT_H__
+#define BLE_GATT_H__
+
+#include "ble_types.h"
+#include "ble_ranges.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup BLE_GATT_DEFINES Defines
+ * @{ */
+
+/** @brief Default MTU size, in bytes. */
+#define BLE_GATT_MTU_SIZE_DEFAULT 23
+
+/**@brief Invalid Attribute Handle. */
+#define BLE_GATT_HANDLE_INVALID            0x0000
+
+/**@brief First Attribute Handle. */
+#define BLE_GATT_HANDLE_START              0x0001
+
+/**@brief Last Attribute Handle. */
+#define BLE_GATT_HANDLE_END                0xFFFF
+
+/** @defgroup BLE_GATT_TIMEOUT_SOURCES GATT Timeout sources
+ * @{ */
+#define BLE_GATT_TIMEOUT_SRC_PROTOCOL      0x00  /**< ATT Protocol timeout. */
+/** @} */
+
+/** @defgroup BLE_GATT_WRITE_OPS GATT Write operations
+ * @{ */
+#define BLE_GATT_OP_INVALID                0x00  /**< Invalid Operation. */
+#define BLE_GATT_OP_WRITE_REQ              0x01  /**< Write Request. */
+#define BLE_GATT_OP_WRITE_CMD              0x02  /**< Write Command. */
+#define BLE_GATT_OP_SIGN_WRITE_CMD         0x03  /**< Signed Write Command. */
+#define BLE_GATT_OP_PREP_WRITE_REQ         0x04  /**< Prepare Write Request. */
+#define BLE_GATT_OP_EXEC_WRITE_REQ         0x05  /**< Execute Write Request. */
+/** @} */
+
+/** @defgroup BLE_GATT_EXEC_WRITE_FLAGS GATT Execute Write flags
+ * @{ */
+#define BLE_GATT_EXEC_WRITE_FLAG_PREPARED_CANCEL 0x00   /**< Cancel prepared write. */
+#define BLE_GATT_EXEC_WRITE_FLAG_PREPARED_WRITE  0x01   /**< Execute prepared write. */
+/** @} */
+
+/** @defgroup BLE_GATT_HVX_TYPES GATT Handle Value operations
+ * @{ */
+#define BLE_GATT_HVX_INVALID               0x00  /**< Invalid Operation. */
+#define BLE_GATT_HVX_NOTIFICATION          0x01  /**< Handle Value Notification. */
+#define BLE_GATT_HVX_INDICATION            0x02  /**< Handle Value Indication. */
+/** @} */
+
+/** @defgroup BLE_GATT_STATUS_CODES GATT Status Codes
+ * @{ */
+#define BLE_GATT_STATUS_SUCCESS                           0x0000  /**< Success. */
+#define BLE_GATT_STATUS_UNKNOWN                           0x0001  /**< Unknown or not applicable status. */
+#define BLE_GATT_STATUS_ATTERR_INVALID                    0x0100  /**< ATT Error: Invalid Error Code. */
+#define BLE_GATT_STATUS_ATTERR_INVALID_HANDLE             0x0101  /**< ATT Error: Invalid Attribute Handle. */
+#define BLE_GATT_STATUS_ATTERR_READ_NOT_PERMITTED         0x0102  /**< ATT Error: Read not permitted. */
+#define BLE_GATT_STATUS_ATTERR_WRITE_NOT_PERMITTED        0x0103  /**< ATT Error: Write not permitted. */
+#define BLE_GATT_STATUS_ATTERR_INVALID_PDU                0x0104  /**< ATT Error: Used in ATT as Invalid PDU. */
+#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHENTICATION       0x0105  /**< ATT Error: Authenticated link required. */
+#define BLE_GATT_STATUS_ATTERR_REQUEST_NOT_SUPPORTED      0x0106  /**< ATT Error: Used in ATT as Request Not Supported. */
+#define BLE_GATT_STATUS_ATTERR_INVALID_OFFSET             0x0107  /**< ATT Error: Offset specified was past the end of the attribute. */
+#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHORIZATION        0x0108  /**< ATT Error: Used in ATT as Insufficient Authorisation. */
+#define BLE_GATT_STATUS_ATTERR_PREPARE_QUEUE_FULL         0x0109  /**< ATT Error: Used in ATT as Prepare Queue Full. */
+#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND        0x010A  /**< ATT Error: Used in ATT as Attribute not found. */
+#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_LONG         0x010B  /**< ATT Error: Attribute cannot be read or written using read/write blob requests. */
+#define BLE_GATT_STATUS_ATTERR_INSUF_ENC_KEY_SIZE         0x010C  /**< ATT Error: Encryption key size used is insufficient. */
+#define BLE_GATT_STATUS_ATTERR_INVALID_ATT_VAL_LENGTH     0x010D  /**< ATT Error: Invalid value size. */
+#define BLE_GATT_STATUS_ATTERR_UNLIKELY_ERROR             0x010E  /**< ATT Error: Very unlikely error. */
+#define BLE_GATT_STATUS_ATTERR_INSUF_ENCRYPTION           0x010F  /**< ATT Error: Encrypted link required. */
+#define BLE_GATT_STATUS_ATTERR_UNSUPPORTED_GROUP_TYPE     0x0110  /**< ATT Error: Attribute type is not a supported grouping attribute. */
+#define BLE_GATT_STATUS_ATTERR_INSUF_RESOURCES            0x0111  /**< ATT Error: Encrypted link required. */
+#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_BEGIN           0x0112  /**< ATT Error: Reserved for Future Use range #1 begin. */
+#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_END             0x017F  /**< ATT Error: Reserved for Future Use range #1 end. */
+#define BLE_GATT_STATUS_ATTERR_APP_BEGIN                  0x0180  /**< ATT Error: Application range begin. */
+#define BLE_GATT_STATUS_ATTERR_APP_END                    0x019F  /**< ATT Error: Application range end. */
+#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_BEGIN           0x01A0  /**< ATT Error: Reserved for Future Use range #2 begin. */
+#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_END             0x01DF  /**< ATT Error: Reserved for Future Use range #2 end. */
+#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_BEGIN           0x01E0  /**< ATT Error: Reserved for Future Use range #3 begin. */
+#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_END             0x01FC  /**< ATT Error: Reserved for Future Use range #3 end. */
+#define BLE_GATT_STATUS_ATTERR_CPS_CCCD_CONFIG_ERROR      0x01FD  /**< ATT Common Profile and Service Error: Client Characteristic Configuration Descriptor improperly configured. */
+#define BLE_GATT_STATUS_ATTERR_CPS_PROC_ALR_IN_PROG       0x01FE  /**< ATT Common Profile and Service Error: Procedure Already in Progress. */
+#define BLE_GATT_STATUS_ATTERR_CPS_OUT_OF_RANGE           0x01FF  /**< ATT Common Profile and Service Error: Out Of Range. */
+/** @} */
+
+
+/** @defgroup BLE_GATT_CPF_FORMATS Characteristic Presentation Formats
+ *  @note Found at http://developer.bluetooth.org/gatt/descriptors/Pages/DescriptorViewer.aspx?u=org.bluetooth.descriptor.gatt.characteristic_presentation_format.xml
+ * @{ */
+#define BLE_GATT_CPF_FORMAT_RFU                 0x00 /**< Reserved For Future Use. */
+#define BLE_GATT_CPF_FORMAT_BOOLEAN             0x01 /**< Boolean. */
+#define BLE_GATT_CPF_FORMAT_2BIT                0x02 /**< Unsigned 2-bit integer. */
+#define BLE_GATT_CPF_FORMAT_NIBBLE              0x03 /**< Unsigned 4-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT8               0x04 /**< Unsigned 8-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT12              0x05 /**< Unsigned 12-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT16              0x06 /**< Unsigned 16-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT24              0x07 /**< Unsigned 24-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT32              0x08 /**< Unsigned 32-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT48              0x09 /**< Unsigned 48-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT64              0x0A /**< Unsigned 64-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT128             0x0B /**< Unsigned 128-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT8               0x0C /**< Signed 2-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT12              0x0D /**< Signed 12-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT16              0x0E /**< Signed 16-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT24              0x0F /**< Signed 24-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT32              0x10 /**< Signed 32-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT48              0x11 /**< Signed 48-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT64              0x12 /**< Signed 64-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT128             0x13 /**< Signed 128-bit integer. */
+#define BLE_GATT_CPF_FORMAT_FLOAT32             0x14 /**< IEEE-754 32-bit floating point. */
+#define BLE_GATT_CPF_FORMAT_FLOAT64             0x15 /**< IEEE-754 64-bit floating point. */
+#define BLE_GATT_CPF_FORMAT_SFLOAT              0x16 /**< IEEE-11073 16-bit SFLOAT. */
+#define BLE_GATT_CPF_FORMAT_FLOAT               0x17 /**< IEEE-11073 32-bit FLOAT. */
+#define BLE_GATT_CPF_FORMAT_DUINT16             0x18 /**< IEEE-20601 format. */
+#define BLE_GATT_CPF_FORMAT_UTF8S               0x19 /**< UTF-8 string. */
+#define BLE_GATT_CPF_FORMAT_UTF16S              0x1A /**< UTF-16 string. */
+#define BLE_GATT_CPF_FORMAT_STRUCT              0x1B /**< Opaque Structure. */
+/** @} */
+
+/** @defgroup BLE_GATT_CPF_NAMESPACES GATT Bluetooth Namespaces
+ * @{
+ */
+#define BLE_GATT_CPF_NAMESPACE_BTSIG            0x01 /**< Bluetooth SIG defined Namespace. */
+#define BLE_GATT_CPF_NAMESPACE_DESCRIPTION_UNKNOWN 0x0000 /**< Namespace Description Unknown. */
+/** @} */
+
+/** @} */
+
+/** @addtogroup BLE_GATT_STRUCTURES Structures
+ * @{ */
+
+/**
+ * @brief BLE GATT initialization parameters.
+ */
+typedef struct
+{
+  uint16_t  att_mtu;          /**< Maximum size of ATT packet the SoftDevice can send or receive.
+                                   If it is 0 then @ref BLE_GATT_MTU_SIZE_DEFAULT will be used.
+                                   Otherwise @ref BLE_GATT_MTU_SIZE_DEFAULT is the minimum value.
+                                   @mscs
+                                   @mmsc{@ref BLE_GATTC_MTU_EXCHANGE}
+                                   @mmsc{@ref BLE_GATTS_MTU_EXCHANGE}
+                                   @endmscs
+                              */
+} ble_gatt_enable_params_t;
+
+/**@brief GATT Characteristic Properties. */
+typedef struct
+{
+  /* Standard properties */
+  uint8_t broadcast       :1; /**< Broadcasting of the value permitted. */
+  uint8_t read            :1; /**< Reading the value permitted. */
+  uint8_t write_wo_resp   :1; /**< Writing the value with Write Command permitted. */
+  uint8_t write           :1; /**< Writing the value with Write Request permitted. */
+  uint8_t notify          :1; /**< Notications of the value permitted. */
+  uint8_t indicate        :1; /**< Indications of the value permitted. */
+  uint8_t auth_signed_wr  :1; /**< Writing the value with Signed Write Command permitted. */
+} ble_gatt_char_props_t;
+
+/**@brief GATT Characteristic Extended Properties. */
+typedef struct
+{
+  /* Extended properties */
+  uint8_t reliable_wr     :1; /**< Writing the value with Queued Write operations permitted. */
+  uint8_t wr_aux          :1; /**< Writing the Characteristic User Description descriptor permitted. */
+} ble_gatt_char_ext_props_t;
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // BLE_GATT_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_gattc.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,669 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+  @addtogroup BLE_GATTC Generic Attribute Profile (GATT) Client
+  @{
+  @brief  Definitions and prototypes for the GATT Client interface.
+ */
+
+#ifndef BLE_GATTC_H__
+#define BLE_GATTC_H__
+
+#include "ble_gatt.h"
+#include "ble_types.h"
+#include "ble_ranges.h"
+#include "nrf_svc.h"
+#include "nrf_error.h"
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup BLE_GATTC_ENUMERATIONS Enumerations
+ * @{ */
+
+/**@brief GATTC API SVC numbers. */
+enum BLE_GATTC_SVCS
+{
+  SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER = BLE_GATTC_SVC_BASE, /**< Primary Service Discovery. */
+  SD_BLE_GATTC_RELATIONSHIPS_DISCOVER,                         /**< Relationship Discovery. */
+  SD_BLE_GATTC_CHARACTERISTICS_DISCOVER,                       /**< Characteristic Discovery. */
+  SD_BLE_GATTC_DESCRIPTORS_DISCOVER,                           /**< Characteristic Descriptor Discovery. */
+  SD_BLE_GATTC_ATTR_INFO_DISCOVER,                             /**< Attribute Information Discovery. */
+  SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ,                        /**< Read Characteristic Value by UUID. */
+  SD_BLE_GATTC_READ,                                           /**< Generic read. */
+  SD_BLE_GATTC_CHAR_VALUES_READ,                               /**< Read multiple Characteristic Values. */
+  SD_BLE_GATTC_WRITE,                                          /**< Generic write. */
+  SD_BLE_GATTC_HV_CONFIRM,                                     /**< Handle Value Confirmation. */
+  SD_BLE_GATTC_EXCHANGE_MTU_REQUEST,                           /**< Exchange MTU Request. */
+};
+
+/**
+ * @brief GATT Client Event IDs.
+ */
+enum BLE_GATTC_EVTS
+{
+  BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP = BLE_GATTC_EVT_BASE,  /**< Primary Service Discovery Response event.      \n See @ref ble_gattc_evt_prim_srvc_disc_rsp_t.          */
+  BLE_GATTC_EVT_REL_DISC_RSP,                             /**< Relationship Discovery Response event.         \n See @ref ble_gattc_evt_rel_disc_rsp_t.                */
+  BLE_GATTC_EVT_CHAR_DISC_RSP,                            /**< Characteristic Discovery Response event.       \n See @ref ble_gattc_evt_char_disc_rsp_t.               */
+  BLE_GATTC_EVT_DESC_DISC_RSP,                            /**< Descriptor Discovery Response event.           \n See @ref ble_gattc_evt_desc_disc_rsp_t.               */
+  BLE_GATTC_EVT_ATTR_INFO_DISC_RSP,                       /**< Attribute Information Response event.          \n See @ref ble_gattc_evt_attr_info_disc_rsp_t. */
+  BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP,                /**< Read By UUID Response event.                   \n See @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t.   */
+  BLE_GATTC_EVT_READ_RSP,                                 /**< Read Response event.                           \n See @ref ble_gattc_evt_read_rsp_t.                    */
+  BLE_GATTC_EVT_CHAR_VALS_READ_RSP,                       /**< Read multiple Response event.                  \n See @ref ble_gattc_evt_char_vals_read_rsp_t.          */
+  BLE_GATTC_EVT_WRITE_RSP,                                /**< Write Response event.                          \n See @ref ble_gattc_evt_write_rsp_t.                   */
+  BLE_GATTC_EVT_HVX,                                      /**< Handle Value Notification or Indication event. \n Confirm indication with @ref sd_ble_gattc_hv_confirm.  \n See @ref ble_gattc_evt_hvx_t. */
+  BLE_GATTC_EVT_EXCHANGE_MTU_RSP,                         /**< Exchange MTU Response event.                   \n See @ref ble_gattc_evt_exchange_mtu_rsp_t.            */
+  BLE_GATTC_EVT_TIMEOUT                                   /**< Timeout event.                                 \n See @ref ble_gattc_evt_timeout_t.                     */
+};
+
+/** @} */
+
+/** @addtogroup BLE_GATTC_DEFINES Defines
+ * @{ */
+
+/** @defgroup BLE_ERRORS_GATTC SVC return values specific to GATTC
+ * @{ */
+#define BLE_ERROR_GATTC_PROC_NOT_PERMITTED    (NRF_GATTC_ERR_BASE + 0x000) /**< Procedure not Permitted. */
+/** @} */
+
+/** @defgroup BLE_GATTC_ATTR_INFO_FORMAT Attribute Information Formats
+ * @{ */
+#define BLE_GATTC_ATTR_INFO_FORMAT_16BIT    1 /**< 16-bit Attribute Information Format. */
+#define BLE_GATTC_ATTR_INFO_FORMAT_128BIT   2 /**< 128-bit Attribute Information Format. */
+/** @} */
+
+/** @} */
+
+/** @addtogroup BLE_GATTC_STRUCTURES Structures
+ * @{ */
+
+/**@brief Operation Handle Range. */
+typedef struct
+{
+  uint16_t          start_handle; /**< Start Handle. */
+  uint16_t          end_handle;   /**< End Handle. */
+} ble_gattc_handle_range_t;
+
+
+/**@brief GATT service. */
+typedef struct
+{
+  ble_uuid_t               uuid;          /**< Service UUID. */
+  ble_gattc_handle_range_t handle_range;  /**< Service Handle Range. */
+} ble_gattc_service_t;
+
+
+/**@brief  GATT include. */
+typedef struct
+{
+  uint16_t            handle;           /**< Include Handle. */
+  ble_gattc_service_t included_srvc;    /**< Handle of the included service. */
+} ble_gattc_include_t;
+
+
+/**@brief GATT characteristic. */
+typedef struct
+{
+  ble_uuid_t              uuid;                 /**< Characteristic UUID. */
+  ble_gatt_char_props_t   char_props;           /**< Characteristic Properties. */
+  uint8_t                 char_ext_props : 1;   /**< Extended properties present. */
+  uint16_t                handle_decl;          /**< Handle of the Characteristic Declaration. */
+  uint16_t                handle_value;         /**< Handle of the Characteristic Value. */
+} ble_gattc_char_t;
+
+
+/**@brief GATT descriptor. */
+typedef struct
+{
+  uint16_t          handle;         /**< Descriptor Handle. */
+  ble_uuid_t        uuid;           /**< Descriptor UUID. */
+} ble_gattc_desc_t;
+
+
+/**@brief Write Parameters. */
+typedef struct
+{
+  uint8_t        write_op;             /**< Write Operation to be performed, see @ref BLE_GATT_WRITE_OPS. */
+  uint8_t        flags;                /**< Flags, see @ref BLE_GATT_EXEC_WRITE_FLAGS. */
+  uint16_t       handle;               /**< Handle to the attribute to be written. */
+  uint16_t       offset;               /**< Offset in bytes. @note For WRITE_CMD and WRITE_REQ, offset must be 0. */
+  uint16_t       len;                  /**< Length of data in bytes. */
+  uint8_t const *p_value;              /**< Pointer to the value data. */
+} ble_gattc_write_params_t;
+
+/**@brief Attribute Information for 16-bit Attribute UUID. */
+typedef struct
+{
+  uint16_t       handle;               /**< Attribute handle. */
+  ble_uuid_t     uuid;                 /**< 16-bit Attribute UUID. */
+} ble_gattc_attr_info16_t;
+
+/**@brief Attribute Information for 128-bit Attribute UUID. */
+typedef struct
+{
+  uint16_t       handle;               /**< Attribute handle. */
+  ble_uuid128_t  uuid;                 /**< 128-bit Attribute UUID. */
+} ble_gattc_attr_info128_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP. */
+typedef struct
+{
+  uint16_t             count;           /**< Service count. */
+  ble_gattc_service_t services[1];      /**< Service data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                             See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_prim_srvc_disc_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_REL_DISC_RSP. */
+typedef struct
+{
+  uint16_t             count;           /**< Include count. */
+  ble_gattc_include_t includes[1];      /**< Include data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                             See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_rel_disc_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_DISC_RSP. */
+typedef struct
+{
+  uint16_t            count;          /**< Characteristic count. */
+  ble_gattc_char_t    chars[1];       /**< Characteristic data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_char_disc_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_DESC_DISC_RSP. */
+typedef struct
+{
+  uint16_t            count;          /**< Descriptor count. */
+  ble_gattc_desc_t    descs[1];       /**< Descriptor data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_desc_disc_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_ATTR_INFO_DISC_RSP. */
+typedef struct
+{
+  uint16_t                     count;            /**< Attribute count. */
+  uint8_t                      format;           /**< Attribute information format, see @ref BLE_GATTC_ATTR_INFO_FORMAT. */
+  union {
+    ble_gattc_attr_info16_t  attr_info16[1];     /**< Attribute information for 16-bit Attribute UUID.
+                                                      @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                                      See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+    ble_gattc_attr_info128_t attr_info128[1];    /**< Attribute information for 128-bit Attribute UUID.
+                                                      @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                                      See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+  } info;                                        /**< Attribute information union. */
+} ble_gattc_evt_attr_info_disc_rsp_t;
+
+/**@brief GATT read by UUID handle value pair. */
+typedef struct
+{
+  uint16_t            handle;          /**< Attribute Handle. */
+  uint8_t            *p_value;         /**< Pointer to the Attribute Value, length is available in @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t::value_len. */
+} ble_gattc_handle_value_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP. */
+typedef struct
+{
+  uint16_t                  count;            /**< Handle-Value Pair Count. */
+  uint16_t                  value_len;        /**< Length of the value in Handle-Value(s) list. */
+  uint8_t                   handle_value[1];  /**< Handle-Value(s) list. To iterate through the list use @ref sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter.
+                                                   @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                                   See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_char_val_by_uuid_read_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_READ_RSP. */
+typedef struct
+{
+  uint16_t            handle;         /**< Attribute Handle. */
+  uint16_t            offset;         /**< Offset of the attribute data. */
+  uint16_t            len;            /**< Attribute data length. */
+  uint8_t             data[1];        /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_read_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VALS_READ_RSP. */
+typedef struct
+{
+  uint16_t            len;            /**< Concatenated Attribute values length. */
+  uint8_t             values[1];      /**< Attribute values. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_char_vals_read_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_WRITE_RSP. */
+typedef struct
+{
+  uint16_t            handle;           /**< Attribute Handle. */
+  uint8_t             write_op;         /**< Type of write operation, see @ref BLE_GATT_WRITE_OPS. */
+  uint16_t            offset;           /**< Data offset. */
+  uint16_t            len;              /**< Data length. */
+  uint8_t             data[1];          /**< Data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                             See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_write_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_HVX. */
+typedef struct
+{
+  uint16_t            handle;         /**< Handle to which the HVx operation applies. */
+  uint8_t             type;           /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */
+  uint16_t            len;            /**< Attribute data length. */
+  uint8_t             data[1];        /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_hvx_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_EXCHANGE_MTU_RSP. */
+typedef struct
+{
+  uint16_t          server_rx_mtu;            /**< Server RX MTU size. */
+} ble_gattc_evt_exchange_mtu_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_TIMEOUT. */
+typedef struct
+{
+  uint8_t          src;                       /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */
+} ble_gattc_evt_timeout_t;
+
+/**@brief GATTC event structure. */
+typedef struct
+{
+  uint16_t            conn_handle;                /**< Connection Handle on which event occured. */
+  uint16_t            gatt_status;                /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */
+  uint16_t            error_handle;               /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */
+  union
+  {
+    ble_gattc_evt_prim_srvc_disc_rsp_t          prim_srvc_disc_rsp;         /**< Primary Service Discovery Response Event Parameters. */
+    ble_gattc_evt_rel_disc_rsp_t                rel_disc_rsp;               /**< Relationship Discovery Response Event Parameters. */
+    ble_gattc_evt_char_disc_rsp_t               char_disc_rsp;              /**< Characteristic Discovery Response Event Parameters. */
+    ble_gattc_evt_desc_disc_rsp_t               desc_disc_rsp;              /**< Descriptor Discovery Response Event Parameters. */
+    ble_gattc_evt_char_val_by_uuid_read_rsp_t   char_val_by_uuid_read_rsp;  /**< Characteristic Value Read by UUID Response Event Parameters. */
+    ble_gattc_evt_read_rsp_t                    read_rsp;                   /**< Read Response Event Parameters. */
+    ble_gattc_evt_char_vals_read_rsp_t          char_vals_read_rsp;         /**< Characteristic Values Read Response Event Parameters. */
+    ble_gattc_evt_write_rsp_t                   write_rsp;                  /**< Write Response Event Parameters. */
+    ble_gattc_evt_hvx_t                         hvx;                        /**< Handle Value Notification/Indication Event Parameters. */
+    ble_gattc_evt_exchange_mtu_rsp_t            exchange_mtu_rsp;           /**< Exchange MTU Response Event Parameters. */
+    ble_gattc_evt_timeout_t                     timeout;                    /**< Timeout Event Parameters. */
+    ble_gattc_evt_attr_info_disc_rsp_t          attr_info_disc_rsp;         /**< Attribute Information Discovery Event Parameters. */
+  } params;                                                                 /**< Event Parameters. @note Only valid if @ref gatt_status == @ref BLE_GATT_STATUS_SUCCESS. */
+} ble_gattc_evt_t;
+/** @} */
+
+/** @addtogroup BLE_GATTC_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Initiate or continue a GATT Primary Service Discovery procedure.
+ *
+ * @details This function initiates or resumes a Primary Service discovery procedure, starting from the supplied handle.
+ *          If the last service has not been reached, this function must be called again with an updated start handle value to continue the search.
+ *
+ * @note If any of the discovered services have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with
+ *       type @ref BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_PRIM_SRVC_DISC_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] start_handle Handle to start searching from.
+ * @param[in] p_srvc_uuid Pointer to the service UUID to be found. If it is NULL, all primary services will be returned.
+ *
+ * @retval ::NRF_SUCCESS Successfully started or resumed the Primary Service Discovery procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER, uint32_t, sd_ble_gattc_primary_services_discover(uint16_t conn_handle, uint16_t start_handle, ble_uuid_t const *p_srvc_uuid));
+
+
+/**@brief Initiate or continue a GATT Relationship Discovery procedure.
+ *
+ * @details This function initiates or resumes the Find Included Services sub-procedure. If the last included service has not been reached,
+ *          this must be called again with an updated handle range to continue the search.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_REL_DISC_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_REL_DISC_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on.
+ *
+ * @retval ::NRF_SUCCESS Successfully started or resumed the Relationship Discovery procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, uint32_t, sd_ble_gattc_relationships_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range));
+
+
+/**@brief Initiate or continue a GATT Characteristic Discovery procedure.
+ *
+ * @details This function initiates or resumes a Characteristic discovery procedure. If the last Characteristic has not been reached,
+ *          this must be called again with an updated handle range to continue the discovery.
+ *
+ * @note If any of the discovered characteristics have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with
+ *       type @ref BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_CHAR_DISC_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_CHAR_DISC_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on.
+ *
+ * @retval ::NRF_SUCCESS Successfully started or resumed the Characteristic Discovery procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, uint32_t, sd_ble_gattc_characteristics_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range));
+
+
+/**@brief Initiate or continue a GATT Characteristic Descriptor Discovery procedure.
+ *
+ * @details This function initiates or resumes a Characteristic Descriptor discovery procedure. If the last Descriptor has not been reached,
+ *          this must be called again with an updated handle range to continue the discovery.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_DESC_DISC_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_DESC_DISC_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_handle_range A pointer to the range of handles of the Characteristic to perform this procedure on.
+ *
+ * @retval ::NRF_SUCCESS Successfully started or resumed the Descriptor Discovery procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_DESCRIPTORS_DISCOVER, uint32_t, sd_ble_gattc_descriptors_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range));
+
+
+/**@brief Initiate or continue a GATT Read using Characteristic UUID procedure.
+ *
+ * @details This function initiates or resumes a Read using Characteristic UUID procedure. If the last Characteristic has not been reached,
+ *          this must be called again with an updated handle range to continue the discovery.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_READ_UUID_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_uuid Pointer to a Characteristic value UUID to read.
+ * @param[in] p_handle_range A pointer to the range of handles to perform this procedure on.
+ *
+ * @retval ::NRF_SUCCESS Successfully started or resumed the Read using Characteristic UUID procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, uint32_t, sd_ble_gattc_char_value_by_uuid_read(uint16_t conn_handle, ble_uuid_t const *p_uuid, ble_gattc_handle_range_t const *p_handle_range));
+
+
+/**@brief Initiate or continue a GATT Read (Long) Characteristic or Descriptor procedure.
+ *
+ * @details This function initiates or resumes a GATT Read (Long) Characteristic or Descriptor procedure. If the Characteristic or Descriptor
+ *          to be read is longer than ATT_MTU - 1, this function must be called multiple times with appropriate offset to read the
+ *          complete value.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_READ_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_VALUE_READ_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] handle The handle of the attribute to be read.
+ * @param[in] offset Offset into the attribute value to be read.
+ *
+ * @retval ::NRF_SUCCESS Successfully started or resumed the Read (Long) procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_READ, uint32_t, sd_ble_gattc_read(uint16_t conn_handle, uint16_t handle, uint16_t offset));
+
+
+/**@brief Initiate a GATT Read Multiple Characteristic Values procedure.
+ *
+ * @details This function initiates a GATT Read Multiple Characteristic Values procedure.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_CHAR_VALS_READ_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_READ_MULT_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_handles A pointer to the handle(s) of the attribute(s) to be read.
+ * @param[in] handle_count The number of handles in p_handles.
+ *
+ * @retval ::NRF_SUCCESS Successfully started the Read Multiple Characteristic Values procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_CHAR_VALUES_READ, uint32_t, sd_ble_gattc_char_values_read(uint16_t conn_handle, uint16_t const *p_handles, uint16_t handle_count));
+
+
+/**@brief Perform a Write (Characteristic Value or Descriptor, with or without response, signed or not, long or reliable) procedure.
+ *
+ * @details This function can perform all write procedures described in GATT.
+ *
+ * @note    It is important to note that a write without response will <b>consume an application buffer</b>, and will therefore
+ *          generate a @ref BLE_EVT_TX_COMPLETE event when the packet has been transmitted. A write (with response) on the other hand will use the
+ *          standard client internal buffer and thus will only generate a @ref BLE_GATTC_EVT_WRITE_RSP event as soon as the write response
+ *          has been received from the peer. Please see the documentation of @ref sd_ble_tx_packet_count_get for more details.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_WRITE_RSP, Generated when using write request or queued writes.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_VALUE_WRITE_MSC}
+ * @mmsc{@ref BLE_GATTC_VALUE_LONG_WRITE_MSC}
+ * @mmsc{@ref BLE_GATTC_VALUE_RELIABLE_WRITE_MSC}
+ * @mmsc{@ref BLE_COMMON_APP_BUFF_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_write_params A pointer to a write parameters structure.
+ *
+ * @retval ::NRF_SUCCESS Successfully started the Write procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
+ * @retval ::NRF_ERROR_BUSY Procedure already in progress.
+ * @retval ::BLE_ERROR_NO_TX_PACKETS No available application packets for this connection.
+ */
+SVCALL(SD_BLE_GATTC_WRITE, uint32_t, sd_ble_gattc_write(uint16_t conn_handle, ble_gattc_write_params_t const *p_write_params));
+
+
+/**@brief Send a Handle Value Confirmation to the GATT Server.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_HVI_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] handle The handle of the attribute in the indication.
+ *
+ * @retval ::NRF_SUCCESS Successfully queued the Handle Value Confirmation for transmission.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or no Indication pending to be confirmed.
+ * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle.
+ */
+SVCALL(SD_BLE_GATTC_HV_CONFIRM, uint32_t, sd_ble_gattc_hv_confirm(uint16_t conn_handle, uint16_t handle));
+
+/**@brief Discovers information about a range of attributes on a GATT server.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_ATTR_INFO_DISC_RSP, Generated when information about a range of attributes has been received.}
+ * @endevents
+ *
+ * @param[in] conn_handle    The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_handle_range The range of handles to request information about.
+ *
+ * @retval ::NRF_SUCCESS Successfully started an attribute information discovery procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid connection state
+ * @retval ::NRF_ERROR_INVALID_ADDR  Invalid pointer supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_ATTR_INFO_DISCOVER, uint32_t, sd_ble_gattc_attr_info_discover(uint16_t conn_handle, ble_gattc_handle_range_t const * p_handle_range));
+
+/**@brief Start an ATT_MTU exchange by sending an Exchange MTU Request to the server.
+ *
+ * @details The SoftDevice sets ATT_MTU to the minimum of:
+ *          - The Client RX MTU value, and
+ *          - The Server RX MTU value from @ref BLE_GATTC_EVT_EXCHANGE_MTU_RSP.
+ *
+ *          However, the SoftDevice never sets ATT_MTU lower than @ref BLE_GATT_MTU_SIZE_DEFAULT.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_EXCHANGE_MTU_RSP}
+ * @event{@ref BLE_EVT_DATA_LENGTH_CHANGED, Generated if a data length update procedure is performed after the ATT_MTU exchange.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_MTU_EXCHANGE}
+ * @endmscs
+ *
+ * @param[in] conn_handle    The connection handle identifying the connection to perform this procedure on.
+ * @param[in] client_rx_mtu  Client RX MTU size.
+ *                           - The minimum value is @ref BLE_GATT_MTU_SIZE_DEFAULT.
+ *                           - The maximum value is @ref ble_gatt_enable_params_t::att_mtu.
+ *                           - The value must be equal to Server RX MTU size given in @ref sd_ble_gatts_exchange_mtu_reply
+ *                             if an ATT_MTU exchange has already been performed in the other direction.
+ *
+ * @retval ::NRF_SUCCESS Successfully sent request to the server.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid connection state or an ATT_MTU exchange was already requested once.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid Client RX MTU size supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_EXCHANGE_MTU_REQUEST, uint32_t, sd_ble_gattc_exchange_mtu_request(uint16_t conn_handle, uint16_t client_rx_mtu));
+
+/**@brief Iterate through Handle-Value(s) list in @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP event.
+ *
+ * @param[in] p_gattc_evt  Pointer to event buffer containing @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP event.
+ *                         @note If the buffer contains different event, behavior is undefined.
+ * @param[in,out] p_iter   Iterator, points to @ref ble_gattc_handle_value_t structure that will be filled in with
+ *                         the next Handle-Value pair in each iteration. If the function returns other than
+ *                         @ref NRF_SUCCESS, it will not be changed.
+ *                         - To start iteration, initialize the structure to zero.
+ *                         - To continue, pass the value from previous iteration.
+ *
+ * \code
+ * ble_gattc_handle_value_t iter;
+ * memset(&iter, 0, sizeof(ble_gattc_handle_value_t));
+ * while (sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(&ble_evt.evt.gattc_evt, &iter) == NRF_SUCCESS)
+ * {
+ *   app_handle = iter.handle;
+ *   memcpy(app_value, iter.p_value, ble_evt.evt.gattc_evt.params.char_val_by_uuid_read_rsp.value_len);
+ * }
+ * \endcode
+ *
+ * @retval ::NRF_SUCCESS Successfully retrieved the next Handle-Value pair.
+ * @retval ::NRF_ERROR_NOT_FOUND No more Handle-Value pairs available in the list.
+ */
+__STATIC_INLINE uint32_t sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(ble_gattc_evt_t *p_gattc_evt, ble_gattc_handle_value_t *p_iter);
+
+/** @} */
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE uint32_t sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(ble_gattc_evt_t *p_gattc_evt, ble_gattc_handle_value_t *p_iter)
+{
+  uint32_t value_len = p_gattc_evt->params.char_val_by_uuid_read_rsp.value_len;
+  uint8_t *p_first = p_gattc_evt->params.char_val_by_uuid_read_rsp.handle_value;
+  uint8_t *p_next = p_iter->p_value ? p_iter->p_value + value_len : p_first;
+
+  if ((p_next - p_first) / (sizeof(uint16_t) + value_len) < p_gattc_evt->params.char_val_by_uuid_read_rsp.count)
+  {
+    p_iter->handle = (uint16_t)p_next[1] << 8 | p_next[0];
+    p_iter->p_value = p_next + sizeof(uint16_t);
+    return NRF_SUCCESS;
+  }
+  else
+  {
+    return NRF_ERROR_NOT_FOUND;
+  }
+}
+
+#endif /* SUPPRESS_INLINE_IMPLEMENTATION */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BLE_GATTC_H__ */
+
+/**
+  @}
+*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_gatts.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,778 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+  @addtogroup BLE_GATTS Generic Attribute Profile (GATT) Server
+  @{
+  @brief  Definitions and prototypes for the GATTS interface.
+ */
+
+#ifndef BLE_GATTS_H__
+#define BLE_GATTS_H__
+
+#include "ble_types.h"
+#include "ble_ranges.h"
+#include "ble_l2cap.h"
+#include "ble_gap.h"
+#include "ble_gatt.h"
+#include "nrf_svc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup BLE_GATTS_ENUMERATIONS Enumerations
+ * @{ */
+
+/**
+ * @brief GATTS API SVC numbers.
+ */
+enum BLE_GATTS_SVCS
+{
+  SD_BLE_GATTS_SERVICE_ADD = BLE_GATTS_SVC_BASE, /**< Add a service. */
+  SD_BLE_GATTS_INCLUDE_ADD,                      /**< Add an included service. */
+  SD_BLE_GATTS_CHARACTERISTIC_ADD,               /**< Add a characteristic. */
+  SD_BLE_GATTS_DESCRIPTOR_ADD,                   /**< Add a generic attribute. */
+  SD_BLE_GATTS_VALUE_SET,                        /**< Set an attribute value. */
+  SD_BLE_GATTS_VALUE_GET,                        /**< Get an attribute value. */
+  SD_BLE_GATTS_HVX,                              /**< Handle Value Notification or Indication. */
+  SD_BLE_GATTS_SERVICE_CHANGED,                  /**< Perform a Service Changed Indication to one or more peers. */
+  SD_BLE_GATTS_RW_AUTHORIZE_REPLY,               /**< Reply to an authorization request for a read or write operation on one or more attributes. */
+  SD_BLE_GATTS_SYS_ATTR_SET,                     /**< Set the persistent system attributes for a connection. */
+  SD_BLE_GATTS_SYS_ATTR_GET,                     /**< Retrieve the persistent system attributes. */
+  SD_BLE_GATTS_INITIAL_USER_HANDLE_GET,          /**< Retrieve the first valid user handle. */
+  SD_BLE_GATTS_ATTR_GET,                         /**< Retrieve the UUID and/or metadata of an attribute. */
+  SD_BLE_GATTS_EXCHANGE_MTU_REPLY                /**< Reply to Exchange MTU Request. */
+};
+
+/**
+ * @brief GATT Server Event IDs.
+ */
+enum BLE_GATTS_EVTS
+{
+  BLE_GATTS_EVT_WRITE = BLE_GATTS_EVT_BASE,       /**< Write operation performed.                                           \n See @ref ble_gatts_evt_write_t.                 */
+  BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST,             /**< Read/Write Authorization request.                                    \n Reply with @ref sd_ble_gatts_rw_authorize_reply. \n See @ref ble_gatts_evt_rw_authorize_request_t. */
+  BLE_GATTS_EVT_SYS_ATTR_MISSING,                 /**< A persistent system attribute access is pending.                     \n Respond with @ref sd_ble_gatts_sys_attr_set.     \n See @ref ble_gatts_evt_sys_attr_missing_t.     */
+  BLE_GATTS_EVT_HVC,                              /**< Handle Value Confirmation.                                           \n See @ref ble_gatts_evt_hvc_t.                   */
+  BLE_GATTS_EVT_SC_CONFIRM,                       /**< Service Changed Confirmation. No additional event structure applies.                                                    */
+  BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST,             /**< Exchange MTU Request.                                                \n Reply with @ref sd_ble_gatts_exchange_mtu_reply. \n See @ref ble_gatts_evt_exchange_mtu_request_t. */
+  BLE_GATTS_EVT_TIMEOUT                           /**< Peer failed to resonpond to an ATT request in time.                  \n See @ref ble_gatts_evt_timeout_t.               */
+};
+/** @} */
+
+/** @addtogroup BLE_GATTS_DEFINES Defines
+ * @{ */
+
+/** @defgroup BLE_ERRORS_GATTS SVC return values specific to GATTS
+ * @{ */
+#define BLE_ERROR_GATTS_INVALID_ATTR_TYPE   (NRF_GATTS_ERR_BASE + 0x000) /**< Invalid attribute type. */
+#define BLE_ERROR_GATTS_SYS_ATTR_MISSING    (NRF_GATTS_ERR_BASE + 0x001) /**< System Attributes missing. */
+/** @} */
+
+/** @defgroup BLE_GATTS_ATTR_LENS_MAX Maximum attribute lengths
+ * @{ */
+#define BLE_GATTS_FIX_ATTR_LEN_MAX (510)  /**< Maximum length for fixed length Attribute Values. */
+#define BLE_GATTS_VAR_ATTR_LEN_MAX (512)  /**< Maximum length for variable length Attribute Values. */
+/** @} */
+
+/** @defgroup BLE_GATTS_SRVC_TYPES GATT Server Service Types
+ * @{ */
+#define BLE_GATTS_SRVC_TYPE_INVALID          0x00  /**< Invalid Service Type. */
+#define BLE_GATTS_SRVC_TYPE_PRIMARY          0x01  /**< Primary Service. */
+#define BLE_GATTS_SRVC_TYPE_SECONDARY        0x02  /**< Secondary Type. */
+/** @} */
+
+
+/** @defgroup BLE_GATTS_ATTR_TYPES GATT Server Attribute Types
+ * @{ */
+#define BLE_GATTS_ATTR_TYPE_INVALID         0x00  /**< Invalid Attribute Type. */
+#define BLE_GATTS_ATTR_TYPE_PRIM_SRVC_DECL  0x01  /**< Primary Service Declaration. */
+#define BLE_GATTS_ATTR_TYPE_SEC_SRVC_DECL   0x02  /**< Secondary Service Declaration. */
+#define BLE_GATTS_ATTR_TYPE_INC_DECL        0x03  /**< Include Declaration. */
+#define BLE_GATTS_ATTR_TYPE_CHAR_DECL       0x04  /**< Characteristic Declaration. */
+#define BLE_GATTS_ATTR_TYPE_CHAR_VAL        0x05  /**< Characteristic Value. */
+#define BLE_GATTS_ATTR_TYPE_DESC            0x06  /**< Descriptor. */
+#define BLE_GATTS_ATTR_TYPE_OTHER           0x07  /**< Other, non-GATT specific type. */
+/** @} */
+
+
+/** @defgroup BLE_GATTS_OPS GATT Server Operations
+ * @{ */
+#define BLE_GATTS_OP_INVALID                0x00  /**< Invalid Operation. */
+#define BLE_GATTS_OP_WRITE_REQ              0x01  /**< Write Request. */
+#define BLE_GATTS_OP_WRITE_CMD              0x02  /**< Write Command. */
+#define BLE_GATTS_OP_SIGN_WRITE_CMD         0x03  /**< Signed Write Command. */
+#define BLE_GATTS_OP_PREP_WRITE_REQ         0x04  /**< Prepare Write Request. */
+#define BLE_GATTS_OP_EXEC_WRITE_REQ_CANCEL  0x05  /**< Execute Write Request: Cancel all prepared writes. */
+#define BLE_GATTS_OP_EXEC_WRITE_REQ_NOW     0x06  /**< Execute Write Request: Immediately execute all prepared writes. */
+/** @} */
+
+/** @defgroup BLE_GATTS_VLOCS GATT Value Locations
+ * @{ */
+#define BLE_GATTS_VLOC_INVALID       0x00  /**< Invalid Location. */
+#define BLE_GATTS_VLOC_STACK         0x01  /**< Attribute Value is located in stack memory, no user memory is required. */
+#define BLE_GATTS_VLOC_USER          0x02  /**< Attribute Value is located in user memory. This requires the user to maintain a valid buffer through the lifetime of the attribute, since the stack
+                                                will read and write directly to the memory using the pointer provided in the APIs. There are no alignment requirements for the buffer. */
+/** @} */
+
+/** @defgroup BLE_GATTS_AUTHORIZE_TYPES GATT Server Authorization Types
+ * @{ */
+#define BLE_GATTS_AUTHORIZE_TYPE_INVALID    0x00  /**< Invalid Type. */
+#define BLE_GATTS_AUTHORIZE_TYPE_READ       0x01  /**< Authorize a Read Operation. */
+#define BLE_GATTS_AUTHORIZE_TYPE_WRITE      0x02  /**< Authorize a Write Request Operation. */
+/** @} */
+
+/** @defgroup BLE_GATTS_SYS_ATTR_FLAGS System Attribute Flags
+ * @{ */
+#define BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS (1 << 0)  /**< Restrict system attributes to system services only. */
+#define BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS (1 << 1)  /**< Restrict system attributes to user services only. */
+/** @} */
+
+/** @defgroup BLE_GATTS_ATTR_TAB_SIZE Attribute Table size
+ * @{
+ */
+#define BLE_GATTS_ATTR_TAB_SIZE_MIN         248    /**< Minimum Attribute Table size */
+#define BLE_GATTS_ATTR_TAB_SIZE_DEFAULT     0x0000 /**< Default Attribute Table size (0x580 bytes for this version of the SoftDevice). */
+/** @} */
+
+/** @} */
+
+/** @addtogroup BLE_GATTS_STRUCTURES Structures
+ * @{ */
+
+/**
+ * @brief BLE GATTS initialization parameters.
+ */
+typedef struct
+{
+  uint8_t                  service_changed:1; /**< Include the Service Changed characteristic in the Attribute Table. */
+  uint32_t                 attr_tab_size;     /**< Attribute Table size in bytes. The size must be a multiple of 4. @ref BLE_GATTS_ATTR_TAB_SIZE_DEFAULT is used to set the default size. */
+} ble_gatts_enable_params_t;
+
+/**@brief Attribute metadata. */
+typedef struct
+{
+  ble_gap_conn_sec_mode_t read_perm;       /**< Read permissions. */
+  ble_gap_conn_sec_mode_t write_perm;      /**< Write permissions. */
+  uint8_t                 vlen       :1;   /**< Variable length attribute. */
+  uint8_t                 vloc       :2;   /**< Value location, see @ref BLE_GATTS_VLOCS.*/
+  uint8_t                 rd_auth    :1;   /**< Read authorization and value will be requested from the application on every read operation. */
+  uint8_t                 wr_auth    :1;   /**< Write authorization will be requested from the application on every Write Request operation (but not Write Command). */
+} ble_gatts_attr_md_t;
+
+
+/**@brief GATT Attribute. */
+typedef struct
+{
+  ble_uuid_t          *p_uuid;          /**< Pointer to the attribute UUID. */
+  ble_gatts_attr_md_t *p_attr_md;       /**< Pointer to the attribute metadata structure. */
+  uint16_t             init_len;        /**< Initial attribute value length in bytes. */
+  uint16_t             init_offs;       /**< Initial attribute value offset in bytes. If different from zero, the first init_offs bytes of the attribute value will be left uninitialized. */
+  uint16_t             max_len;         /**< Maximum attribute value length in bytes, see @ref BLE_GATTS_ATTR_LENS_MAX for maximum values. */
+  uint8_t*             p_value;         /**< Pointer to the attribute data. Please note that if the @ref BLE_GATTS_VLOC_USER value location is selected in the attribute metadata, this will have to point to a buffer
+                                             that remains valid through the lifetime of the attribute. This excludes usage of automatic variables that may go out of scope or any other temporary location.
+                                             The stack may access that memory directly without the application's knowledge. For writable characteristics, this value must not be a location in flash memory.*/
+} ble_gatts_attr_t;
+
+/**@brief GATT Attribute Value. */
+typedef struct
+{
+  uint16_t  len;        /**< Length in bytes to be written or read. Length in bytes written or read after successful return.*/
+  uint16_t  offset;     /**< Attribute value offset. */
+  uint8_t   *p_value;   /**< Pointer to where value is stored or will be stored.
+                             If value is stored in user memory, only the attribute length is updated when p_value == NULL.
+                             Set to NULL when reading to obtain the complete length of the attribute value */
+} ble_gatts_value_t;
+
+
+/**@brief GATT Characteristic Presentation Format. */
+typedef struct
+{
+  uint8_t          format;      /**< Format of the value, see @ref BLE_GATT_CPF_FORMATS. */
+  int8_t           exponent;    /**< Exponent for integer data types. */
+  uint16_t         unit;        /**< Unit from Bluetooth Assigned Numbers. */
+  uint8_t          name_space;  /**< Namespace from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */
+  uint16_t         desc;        /**< Namespace description from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */
+} ble_gatts_char_pf_t;
+
+
+/**@brief GATT Characteristic metadata. */
+typedef struct
+{
+  ble_gatt_char_props_t       char_props;               /**< Characteristic Properties. */
+  ble_gatt_char_ext_props_t   char_ext_props;           /**< Characteristic Extended Properties. */
+  uint8_t                    *p_char_user_desc;         /**< Pointer to a UTF-8 encoded string (non-NULL terminated), NULL if the descriptor is not required. */
+  uint16_t                    char_user_desc_max_size;  /**< The maximum size in bytes of the user description descriptor. */
+  uint16_t                    char_user_desc_size;      /**< The size of the user description, must be smaller or equal to char_user_desc_max_size. */
+  ble_gatts_char_pf_t*        p_char_pf;                /**< Pointer to a presentation format structure or NULL if the CPF descriptor is not required. */
+  ble_gatts_attr_md_t*        p_user_desc_md;           /**< Attribute metadata for the User Description descriptor, or NULL for default values. */
+  ble_gatts_attr_md_t*        p_cccd_md;                /**< Attribute metadata for the Client Characteristic Configuration Descriptor, or NULL for default values. */
+  ble_gatts_attr_md_t*        p_sccd_md;                /**< Attribute metadata for the Server Characteristic Configuration Descriptor, or NULL for default values. */
+} ble_gatts_char_md_t;
+
+
+/**@brief GATT Characteristic Definition Handles. */
+typedef struct
+{
+  uint16_t          value_handle;       /**< Handle to the characteristic value. */
+  uint16_t          user_desc_handle;   /**< Handle to the User Description descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */
+  uint16_t          cccd_handle;        /**< Handle to the Client Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */
+  uint16_t          sccd_handle;        /**< Handle to the Server Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */
+} ble_gatts_char_handles_t;
+
+
+/**@brief GATT HVx parameters. */
+typedef struct
+{
+  uint16_t          handle;             /**< Characteristic Value Handle. */
+  uint8_t           type;               /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */
+  uint16_t          offset;             /**< Offset within the attribute value. */
+  uint16_t         *p_len;              /**< Length in bytes to be written, length in bytes written after successful return. */
+  uint8_t          *p_data;             /**< Actual data content, use NULL to use the current attribute value. */
+} ble_gatts_hvx_params_t;
+
+/**@brief GATT Authorization parameters. */
+typedef struct
+{
+  uint16_t          gatt_status;        /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */
+  uint8_t           update : 1;         /**< If set, data supplied in p_data will be used to update the attribute value.
+                                             Please note that for @ref BLE_GATTS_AUTHORIZE_TYPE_WRITE operations this bit must always be set,
+                                             as the data to be written needs to be stored and later provided by the application. */
+  uint16_t          offset;             /**< Offset of the attribute value being updated. */
+  uint16_t          len;                /**< Length in bytes of the value in p_data pointer, see @ref BLE_GATTS_ATTR_LENS_MAX. */
+  const uint8_t    *p_data;             /**< Pointer to new value used to update the attribute value. */
+} ble_gatts_authorize_params_t;
+
+/**@brief GATT Read or Write Authorize Reply parameters. */
+typedef struct
+{
+  uint8_t                               type;   /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */
+  union {
+    ble_gatts_authorize_params_t        read;   /**< Read authorization parameters. */
+    ble_gatts_authorize_params_t        write;  /**< Write authorization parameters. */
+  } params;                                     /**< Reply Parameters. */
+} ble_gatts_rw_authorize_reply_params_t;
+
+
+
+/**@brief Event structure for @ref BLE_GATTS_EVT_WRITE. */
+typedef struct
+{
+  uint16_t                    handle;             /**< Attribute Handle. */
+  ble_uuid_t                  uuid;               /**< Attribute UUID. */
+  uint8_t                     op;                 /**< Type of write operation, see @ref BLE_GATTS_OPS. */
+  uint8_t                     auth_required;      /**< Writing operation deferred due to authorization requirement. Application may use @ref sd_ble_gatts_value_set to finalise the writing operation. */
+  uint16_t                    offset;             /**< Offset for the write operation. */
+  uint16_t                    len;                /**< Length of the received data. */
+  uint8_t                     data[1];            /**< Received data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                                       See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gatts_evt_write_t;
+
+/**@brief Event substructure for authorized read requests, see @ref ble_gatts_evt_rw_authorize_request_t. */
+typedef struct
+{
+  uint16_t                    handle;             /**< Attribute Handle. */
+  ble_uuid_t                  uuid;               /**< Attribute UUID. */
+  uint16_t                    offset;             /**< Offset for the read operation. */
+} ble_gatts_evt_read_t;
+
+/**@brief Event structure for @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST. */
+typedef struct
+{
+  uint8_t                     type;             /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */
+  union {
+    ble_gatts_evt_read_t      read;             /**< Attribute Read Parameters. */
+    ble_gatts_evt_write_t     write;            /**< Attribute Write Parameters. */
+  } request;                                    /**< Request Parameters. */
+} ble_gatts_evt_rw_authorize_request_t;
+
+/**@brief Event structure for @ref BLE_GATTS_EVT_SYS_ATTR_MISSING. */
+typedef struct
+{
+  uint8_t hint;                                 /**< Hint (currently unused). */
+} ble_gatts_evt_sys_attr_missing_t;
+
+
+/**@brief Event structure for @ref BLE_GATTS_EVT_HVC. */
+typedef struct
+{
+  uint16_t          handle;                       /**< Attribute Handle. */
+} ble_gatts_evt_hvc_t;
+
+/**@brief Event structure for @ref BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST. */
+typedef struct
+{
+  uint16_t          client_rx_mtu;              /**< Client RX MTU size. */
+} ble_gatts_evt_exchange_mtu_request_t;
+
+/**@brief Event structure for @ref BLE_GATTS_EVT_TIMEOUT. */
+typedef struct
+{
+  uint8_t          src;                       /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */
+} ble_gatts_evt_timeout_t;
+
+
+/**@brief GATTS event structure. */
+typedef struct
+{
+  uint16_t conn_handle;                                       /**< Connection Handle on which the event occurred. */
+  union
+  {
+    ble_gatts_evt_write_t                 write;                 /**< Write Event Parameters. */
+    ble_gatts_evt_rw_authorize_request_t  authorize_request;     /**< Read or Write Authorize Request Parameters. */
+    ble_gatts_evt_sys_attr_missing_t      sys_attr_missing;      /**< System attributes missing. */
+    ble_gatts_evt_hvc_t                   hvc;                   /**< Handle Value Confirmation Event Parameters. */
+    ble_gatts_evt_exchange_mtu_request_t  exchange_mtu_request;  /**< Exchange MTU Request Event Parameters. */
+    ble_gatts_evt_timeout_t               timeout;               /**< Timeout Event. */
+  } params;                                                      /**< Event Parameters. */
+} ble_gatts_evt_t;
+
+/** @} */
+
+/** @addtogroup BLE_GATTS_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Add a service declaration to the Attribute Table.
+ *
+ * @note Secondary Services are only relevant in the context of the entity that references them, it is therefore forbidden to
+ *       add a secondary service declaration that is not referenced by another service later in the Attribute Table.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC}
+ * @endmscs
+ *
+ * @param[in] type      Toggles between primary and secondary services, see @ref BLE_GATTS_SRVC_TYPES.
+ * @param[in] p_uuid    Pointer to service UUID.
+ * @param[out] p_handle Pointer to a 16-bit word where the assigned handle will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully added a service declaration.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, Vendor Specific UUIDs need to be present in the table.
+ * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ */
+SVCALL(SD_BLE_GATTS_SERVICE_ADD, uint32_t, sd_ble_gatts_service_add(uint8_t type, ble_uuid_t const *p_uuid, uint16_t *p_handle));
+
+
+/**@brief Add an include declaration to the Attribute Table.
+ *
+ * @note It is currently only possible to add an include declaration to the last added service (i.e. only sequential population is supported at this time).
+ *
+ * @note The included service must already be present in the Attribute Table prior to this call.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC}
+ * @endmscs
+ *
+ * @param[in] service_handle    Handle of the service where the included service is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially.
+ * @param[in] inc_srvc_handle   Handle of the included service.
+ * @param[out] p_include_handle Pointer to a 16-bit word where the assigned handle will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully added an include declaration.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, handle values need to match previously added services.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Feature is not supported, service_handle must be that of the last added service.
+ * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, self inclusions are not allowed.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
+ */
+SVCALL(SD_BLE_GATTS_INCLUDE_ADD, uint32_t, sd_ble_gatts_include_add(uint16_t service_handle, uint16_t inc_srvc_handle, uint16_t *p_include_handle));
+
+
+/**@brief Add a characteristic declaration, a characteristic value declaration and optional characteristic descriptor declarations to the Attribute Table.
+ *
+ * @note It is currently only possible to add a characteristic to the last added service (i.e. only sequential population is supported at this time).
+ *
+ * @note Several restrictions apply to the parameters, such as matching permissions between the user description descriptor and the writeable auxiliaries bits,
+ *       readable (no security) and writeable (selectable) CCCDs and SCCDs and valid presentation format values.
+ *
+ * @note If no metadata is provided for the optional descriptors, their permissions will be derived from the characteristic permissions.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC}
+ * @endmscs
+ *
+ * @param[in] service_handle    Handle of the service where the characteristic is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially.
+ * @param[in] p_char_md         Characteristic metadata.
+ * @param[in] p_attr_char_value Pointer to the attribute structure corresponding to the characteristic value.
+ * @param[out] p_handles        Pointer to the structure where the assigned handles will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully added a characteristic.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, service handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a service context is required.
+ * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX.
+ */
+SVCALL(SD_BLE_GATTS_CHARACTERISTIC_ADD, uint32_t, sd_ble_gatts_characteristic_add(uint16_t service_handle, ble_gatts_char_md_t const *p_char_md, ble_gatts_attr_t const *p_attr_char_value, ble_gatts_char_handles_t *p_handles));
+
+
+/**@brief Add a descriptor to the Attribute Table.
+ *
+ * @note It is currently only possible to add a descriptor to the last added characteristic (i.e. only sequential population is supported at this time).
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC}
+ * @endmscs
+ *
+ * @param[in] char_handle   Handle of the characteristic where the descriptor is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially.
+ * @param[in] p_attr        Pointer to the attribute structure.
+ * @param[out] p_handle     Pointer to a 16-bit word where the assigned handle will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully added a descriptor.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, characteristic handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a characteristic context is required.
+ * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX.
+ */
+SVCALL(SD_BLE_GATTS_DESCRIPTOR_ADD, uint32_t, sd_ble_gatts_descriptor_add(uint16_t char_handle, ble_gatts_attr_t const *p_attr, uint16_t *p_handle));
+
+/**@brief Set the value of a given attribute.
+ *
+ * @note Values other than system attributes can be set at any time, regardless of wheter any active connections exist.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle  Connection handle. Ignored if the value does not belong to a system attribute.
+ * @param[in] handle       Attribute handle.
+ * @param[in,out] p_value  Attribute value information.
+ *
+ * @retval ::NRF_SUCCESS Successfully set the value of the attribute.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
+ * @retval ::NRF_ERROR_FORBIDDEN Forbidden handle supplied, certain attributes are not modifiable by the application.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied on a system attribute.
+ */
+SVCALL(SD_BLE_GATTS_VALUE_SET, uint32_t, sd_ble_gatts_value_set(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value));
+
+/**@brief Get the value of a given attribute.
+ *
+ * @note                 If the attribute value is longer than the size of the supplied buffer,
+ *                       p_len will return the total attribute value length (excluding offset),
+ *                       and not the number of bytes actually returned in p_data.
+ *                       The application may use this information to allocate a suitable buffer size.
+ *
+ * @note                 When retrieving system attribute values with this function, the connection handle
+ *                       may refer to an already disconnected connection. Refer to the documentation of
+ *                       @ref sd_ble_gatts_sys_attr_get for further information.
+ *
+ * @param[in] conn_handle  Connection handle. Ignored if the value does not belong to a system attribute.
+ * @param[in] handle       Attribute handle.
+ * @param[in,out] p_value  Attribute value information.
+ *
+ * @retval ::NRF_SUCCESS Successfully retrieved the value of the attribute.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid attribute offset supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied on a system attribute.
+ * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value.
+ */
+SVCALL(SD_BLE_GATTS_VALUE_GET, uint32_t, sd_ble_gatts_value_get(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value));
+
+/**@brief Notify or Indicate an attribute value.
+ *
+ * @details This function checks for the relevant Client Characteristic Configuration descriptor value to verify that the relevant operation
+ *          (notification or indication) has been enabled by the client. It is also able to update the attribute value before issuing the PDU, so that
+ *          the application can atomically perform a value update and a server initiated transaction with a single API call.
+ *          If the application chooses to indicate an attribute value, a @ref BLE_GATTS_EVT_HVC event will be issued as soon as the confirmation arrives from
+ *          the peer.
+ *
+ * @note    The local attribute value may be updated even if an outgoing packet is not sent to the peer due to an error during execution.
+ *          The Attribute Table has been updated if one of the following error codes is returned: @ref NRF_ERROR_INVALID_STATE, @ref NRF_ERROR_BUSY,
+ *          @ref NRF_ERROR_FORBIDDEN, @ref BLE_ERROR_GATTS_SYS_ATTR_MISSING and @ref BLE_ERROR_NO_TX_PACKETS.
+ *          The caller can check whether the value has been updated by looking at the contents of *(p_hvx_params->p_len).
+ *
+ * @note    It is important to note that a notification will <b>consume an application buffer</b>, and will therefore
+ *          generate a @ref BLE_EVT_TX_COMPLETE event when the packet has been transmitted. An indication on the other hand will use the
+ *          standard server internal buffer and thus will only generate a @ref BLE_GATTS_EVT_HVC event as soon as the confirmation
+ *          has been received from the peer. Please see the documentation of @ref sd_ble_tx_packet_count_get for more details.
+ *
+ * @events
+ * @event{@ref BLE_EVT_TX_COMPLETE, Transmission complete.}
+ * @event{@ref BLE_GATTS_EVT_HVC, Confirmation received from peer.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_HVX_SYS_ATTRS_MISSING_MSC}
+ * @mmsc{@ref BLE_GATTS_HVN_MSC}
+ * @mmsc{@ref BLE_GATTS_HVI_MSC}
+ * @mmsc{@ref BLE_GATTS_HVX_DISABLED_MSC}
+ * @mmsc{@ref BLE_COMMON_APP_BUFF_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle  Connection handle.
+ * @param[in] p_hvx_params Pointer to an HVx parameters structure. If the p_data member contains a non-NULL pointer the attribute value will be updated with
+ *                         the contents pointed by it before sending the notification or indication.
+ *
+ * @retval ::NRF_SUCCESS Successfully queued a notification or indication for transmission, and optionally updated the attribute value.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE One or more of the following is true:
+ *                                   - Invalid Connection State
+ *                                   - Notifications and/or indications not enabled in the CCCD
+ *                                   - An ATT_MTU exchange is ongoing
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied. Only attributes added directly by the application are available to notify and indicate.
+ * @retval ::BLE_ERROR_GATTS_INVALID_ATTR_TYPE Invalid attribute type(s) supplied, only characteristic values may be notified and indicated.
+ * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
+ * @retval ::NRF_ERROR_FORBIDDEN The connection's current security level is lower than the one required by the write permissions of the CCCD associated with this characteristic.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
+ * @retval ::NRF_ERROR_BUSY Procedure already in progress.
+ * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value.
+ * @retval ::BLE_ERROR_NO_TX_PACKETS  No available application packets for this connection, applies only to notifications.
+ */
+SVCALL(SD_BLE_GATTS_HVX, uint32_t, sd_ble_gatts_hvx(uint16_t conn_handle, ble_gatts_hvx_params_t const *p_hvx_params));
+
+/**@brief Indicate the Service Changed attribute value.
+ *
+ * @details This call will send a Handle Value Indication to one or more peers connected to inform them that the Attribute
+ *          Table layout has changed. As soon as the peer has confirmed the indication, a @ref BLE_GATTS_EVT_SC_CONFIRM event will
+ *          be issued.
+ *
+ * @note    Some of the restrictions and limitations that apply to @ref sd_ble_gatts_hvx also apply here.
+ *
+ * @events
+ * @event{@ref BLE_GATTS_EVT_SC_CONFIRM, Confirmation of attribute table change received from peer.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_SC_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle  Connection handle.
+ * @param[in] start_handle Start of affected attribute handle range.
+ * @param[in] end_handle   End of affected attribute handle range.
+ *
+ * @retval ::NRF_SUCCESS Successfully queued the Service Changed indication for transmission.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Service Changed not enabled at initialization. See @ref sd_ble_enable and @ref ble_gatts_enable_params_t.
+ * @retval ::NRF_ERROR_INVALID_STATE One or more of the following is true:
+ *                                   - Invalid Connection State
+ *                                   - Notifications and/or indications not enabled in the CCCD
+ *                                   - An ATT_MTU exchange is ongoing
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied, handles must be in the range populated by the application.
+ * @retval ::NRF_ERROR_BUSY Procedure already in progress.
+ * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value.
+ */
+SVCALL(SD_BLE_GATTS_SERVICE_CHANGED, uint32_t, sd_ble_gatts_service_changed(uint16_t conn_handle, uint16_t start_handle, uint16_t end_handle));
+
+/**@brief Respond to a Read/Write authorization request.
+ *
+ * @note This call should only be used as a response to a @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST event issued to the application.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_AUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_AUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_READ_REQ_AUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_WRITE_REQ_AUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_PEER_CANCEL_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle                 Connection handle.
+ * @param[in] p_rw_authorize_reply_params Pointer to a structure with the attribute provided by the application.
+ *
+ * @note @ref ble_gatts_authorize_params_t::p_data is ignored when this function is used to respond
+ *       to a @ref BLE_GATTS_AUTHORIZE_TYPE_READ event if @ref ble_gatts_authorize_params_t::update
+ *       is set to 0.
+ *
+ * @retval ::NRF_SUCCESS               Successfully queued a response to the peer, and in the case of a write operation, Attribute Table updated.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_ADDR    Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE   Invalid Connection State or no authorization request pending.
+ * @retval ::NRF_ERROR_INVALID_PARAM   Authorization op invalid,
+ *                                         handle supplied does not match requested handle,
+ *                                         or invalid data to be written provided by the application.
+ * @retval ::NRF_ERROR_BUSY The stack is busy. Retry at later time.
+ */
+SVCALL(SD_BLE_GATTS_RW_AUTHORIZE_REPLY, uint32_t, sd_ble_gatts_rw_authorize_reply(uint16_t conn_handle, ble_gatts_rw_authorize_reply_params_t const *p_rw_authorize_reply_params));
+
+
+/**@brief Update persistent system attribute information.
+ *
+ * @details Supply information about persistent system attributes to the stack,
+ *          previously obtained using @ref sd_ble_gatts_sys_attr_get.
+ *          This call is only allowed for active connections, and is usually
+ *          made immediately after a connection is established with an known bonded device,
+ *          often as a response to a @ref BLE_GATTS_EVT_SYS_ATTR_MISSING.
+ *
+ *          p_sysattrs may point directly to the application's stored copy of the system attributes
+ *          obtained using @ref sd_ble_gatts_sys_attr_get.
+ *          If the pointer is NULL, the system attribute info is initialized, assuming that
+ *          the application does not have any previously saved system attribute data for this device.
+ *
+ * @note The state of persistent system attributes is reset upon connection establishment and then remembered for its duration.
+ *
+ * @note If this call returns with an error code different from @ref NRF_SUCCESS, the storage of persistent system attributes may have been completed only partially.
+ *       This means that the state of the attribute table is undefined, and the application should either provide a new set of attributes using this same call or
+ *       reset the SoftDevice to return to a known state.
+ *
+ * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS is used with this function, only the system attributes included in system services will be modified.
+ * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS is used with this function, only the system attributes included in user services will be modified.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_HVX_SYS_ATTRS_MISSING_MSC}
+ * @mmsc{@ref BLE_GATTS_SYS_ATTRS_UNK_PEER_MSC}
+ * @mmsc{@ref BLE_GATTS_SYS_ATTRS_BONDED_PEER_MSC}
+ * @endmscs
+ *
+ * @param[in]  conn_handle        Connection handle.
+ * @param[in]  p_sys_attr_data    Pointer to a saved copy of system attributes supplied to the stack, or NULL.
+ * @param[in]  len                Size of data pointed by p_sys_attr_data, in octets.
+ * @param[in]  flags              Optional additional flags, see @ref BLE_GATTS_SYS_ATTR_FLAGS
+ *
+ * @retval ::NRF_SUCCESS Successfully set the system attribute information.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid flags supplied.
+ * @retval ::NRF_ERROR_INVALID_DATA Invalid data supplied, the data should be exactly the same as retrieved with @ref sd_ble_gatts_sys_attr_get.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ * @retval ::NRF_ERROR_BUSY The stack is busy. Retry at later time.
+ */
+SVCALL(SD_BLE_GATTS_SYS_ATTR_SET, uint32_t, sd_ble_gatts_sys_attr_set(uint16_t conn_handle, uint8_t const *p_sys_attr_data, uint16_t len, uint32_t flags));
+
+
+/**@brief Retrieve persistent system attribute information from the stack.
+ *
+ * @details This call is used to retrieve information about values to be stored perisistently by the application
+ *          during the lifetime of a connection or after it has been terminated. When a new connection is established with the same bonded device,
+ *          the system attribute information retrieved with this function should be restored using using @ref sd_ble_gatts_sys_attr_set.
+ *          If retrieved after disconnection, the data should be read before a new connection established. The connection handle for
+ *          the previous, now disconnected, connection will remain valid until a new one is created to allow this API call to refer to it.
+ *          Connection handles belonging to active connections can be used as well, but care should be taken since the system attributes
+ *          may be written to at any time by the peer during a connection's lifetime.
+ *
+ * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS is used with this function, only the system attributes included in system services will be returned.
+ * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS is used with this function, only the system attributes included in user services will be returned.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_SYS_ATTRS_BONDED_PEER_MSC}
+ * @endmscs
+ *
+ * @param[in]     conn_handle       Connection handle of the recently terminated connection.
+ * @param[out]    p_sys_attr_data   Pointer to a buffer where updated information about system attributes will be filled in. The format of the data is described
+ *                                  in @ref BLE_GATTS_SYS_ATTRS_FORMAT. NULL can be provided to obtain the length of the data.
+ * @param[in,out] p_len             Size of application buffer if p_sys_attr_data is not NULL. Unconditially updated to actual length of system attribute data.
+ * @param[in]     flags             Optional additional flags, see @ref BLE_GATTS_SYS_ATTR_FLAGS
+ *
+ * @retval ::NRF_SUCCESS Successfully retrieved the system attribute information.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid flags supplied.
+ * @retval ::NRF_ERROR_DATA_SIZE The system attribute information did not fit into the provided buffer.
+ * @retval ::NRF_ERROR_NOT_FOUND No system attributes found.
+ */
+SVCALL(SD_BLE_GATTS_SYS_ATTR_GET, uint32_t, sd_ble_gatts_sys_attr_get(uint16_t conn_handle, uint8_t *p_sys_attr_data, uint16_t *p_len, uint32_t flags));
+
+
+/**@brief Retrieve the first valid user attribute handle.
+ *
+ * @param[out] p_handle   Pointer to an integer where the handle will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully retrieved the handle.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ */
+SVCALL(SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, uint32_t, sd_ble_gatts_initial_user_handle_get(uint16_t *p_handle));
+
+/**@brief Retrieve the attribute UUID and/or metadata.
+ *
+ * @param[in]  handle Attribute handle
+ * @param[out] p_uuid UUID of the attribute. Use NULL to omit this field.
+ * @param[out] p_md Metadata of the attribute. Use NULL to omit this field.
+ *
+ * @retval ::NRF_SUCCESS Successfully retrieved the attribute metadata,
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameters supplied. Returned when both @c p_uuid and @c p_md are NULL.
+ * @retval ::NRF_ERROR_NOT_FOUND Attribute was not found.
+ */
+SVCALL(SD_BLE_GATTS_ATTR_GET, uint32_t, sd_ble_gatts_attr_get(uint16_t handle, ble_uuid_t * p_uuid, ble_gatts_attr_md_t * p_md));
+
+/**@brief Reply to an ATT_MTU exchange request by sending an Exchange MTU Response to the client.
+ *
+ * @details This function is only used to reply to a @ref BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST event.
+ *
+ * @details The SoftDevice sets ATT_MTU to the minimum of:
+ *          - The Client RX MTU value from @ref BLE_GATTS_EVT_EXCHANGE_MTU_REQUEST, and
+ *          - The Server RX MTU value.
+ *
+ *          However, the SoftDevice never sets ATT_MTU lower than @ref BLE_GATT_MTU_SIZE_DEFAULT.
+ *
+ * @events
+ * @event{@ref BLE_EVT_DATA_LENGTH_CHANGED, Generated if a data length update procedure is performed after the ATT_MTU exchange.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_MTU_EXCHANGE}
+ * @endmscs
+ *
+ * @param[in] conn_handle    The connection handle identifying the connection to perform this procedure on.
+ * @param[in] server_rx_mtu  Server RX MTU size.
+ *                           - The minimum value is @ref BLE_GATT_MTU_SIZE_DEFAULT.
+ *                           - The maximum value is @ref ble_gatt_enable_params_t::att_mtu.
+ *                           - The value must be equal to Client RX MTU size given in @ref sd_ble_gattc_exchange_mtu_request
+ *                             if an ATT_MTU exchange has already been performed in the other direction.
+ *
+ * @retval ::NRF_SUCCESS Successfully sent response to the client.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or no ATT_MTU exchange request pending.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid Server RX MTU size supplied.
+ * @retval ::NRF_ERROR_BUSY The stack is busy. Retry at later time.
+ */
+SVCALL(SD_BLE_GATTS_EXCHANGE_MTU_REPLY, uint32_t, sd_ble_gatts_exchange_mtu_reply(uint16_t conn_handle, uint16_t server_rx_mtu));
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // BLE_GATTS_H__
+
+/**
+  @}
+*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_hci.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,133 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+  @addtogroup BLE_COMMON 
+  @{
+*/
+
+
+#ifndef BLE_HCI_H__
+#define BLE_HCI_H__ 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup BLE_HCI_STATUS_CODES Bluetooth status codes
+ * @{ */
+
+#define BLE_HCI_STATUS_CODE_SUCCESS                        0x00   /**< Success. */
+#define BLE_HCI_STATUS_CODE_UNKNOWN_BTLE_COMMAND           0x01   /**< Unknown BLE Command. */
+#define BLE_HCI_STATUS_CODE_UNKNOWN_CONNECTION_IDENTIFIER  0x02   /**< Unknown Connection Identifier. */
+/*0x03 Hardware Failure
+0x04 Page Timeout
+*/
+#define BLE_HCI_AUTHENTICATION_FAILURE                     0x05   /**< Authentication Failure. */
+#define BLE_HCI_STATUS_CODE_PIN_OR_KEY_MISSING             0x06   /**< Pin or Key missing. */
+#define BLE_HCI_MEMORY_CAPACITY_EXCEEDED                   0x07   /**< Memory Capacity Exceeded. */
+#define BLE_HCI_CONNECTION_TIMEOUT                         0x08   /**< Connection Timeout. */
+/*0x09 Connection Limit Exceeded
+0x0A Synchronous Connection Limit To A Device Exceeded
+0x0B ACL Connection Already Exists*/
+#define BLE_HCI_STATUS_CODE_COMMAND_DISALLOWED             0x0C   /**< Command Disallowed. */
+/*0x0D Connection Rejected due to Limited Resources
+0x0E Connection Rejected Due To Security Reasons
+0x0F Connection Rejected due to Unacceptable BD_ADDR
+0x10 Connection Accept Timeout Exceeded
+0x11 Unsupported Feature or Parameter Value*/
+#define BLE_HCI_STATUS_CODE_INVALID_BTLE_COMMAND_PARAMETERS 0x12  /**< Invalid BLE Command Parameters. */
+#define BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION           0x13  /**< Remote User Terminated Connection. */
+#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_LOW_RESOURCES 0x14  /**< Remote Device Terminated Connection due to low resources.*/
+#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_POWER_OFF     0x15  /**< Remote Device Terminated Connection due to power off. */
+#define BLE_HCI_LOCAL_HOST_TERMINATED_CONNECTION            0x16  /**< Local Host Terminated Connection. */
+/*
+0x17 Repeated Attempts
+0x18 Pairing Not Allowed
+0x19 Unknown LMP PDU
+*/
+#define BLE_HCI_UNSUPPORTED_REMOTE_FEATURE 0x1A                   /**< Unsupported Remote Feature. */
+/*
+0x1B SCO Offset Rejected
+0x1C SCO Interval Rejected
+0x1D SCO Air Mode Rejected*/
+#define BLE_HCI_STATUS_CODE_INVALID_LMP_PARAMETERS     0x1E       /**< Invalid LMP Parameters. */
+#define BLE_HCI_STATUS_CODE_UNSPECIFIED_ERROR          0x1F       /**< Unspecified Error. */
+/*0x20 Unsupported LMP Parameter Value
+0x21 Role Change Not Allowed
+*/
+#define BLE_HCI_STATUS_CODE_LMP_RESPONSE_TIMEOUT       0x22       /**< LMP Response Timeout. */
+#define BLE_HCI_STATUS_CODE_LMP_ERROR_TRANSACTION_COLLISION 0x23  /**< LMP Error Transaction Collision/LL Procedure Collision. */
+#define BLE_HCI_STATUS_CODE_LMP_PDU_NOT_ALLOWED        0x24       /**< LMP PDU Not Allowed. */
+/*0x25 Encryption Mode Not Acceptable
+0x26 Link Key Can Not be Changed
+0x27 Requested QoS Not Supported
+*/
+#define BLE_HCI_INSTANT_PASSED                         0x28       /**< Instant Passed. */
+#define BLE_HCI_PAIRING_WITH_UNIT_KEY_UNSUPPORTED      0x29       /**< Pairing with Unit Key Unsupported. */
+#define BLE_HCI_DIFFERENT_TRANSACTION_COLLISION        0x2A       /**< Different Transaction Collision. */
+/*
+0x2B Reserved
+0x2C QoS Unacceptable Parameter
+0x2D QoS Rejected
+0x2E Channel Classification Not Supported
+0x2F Insufficient Security
+0x30 Parameter Out Of Mandatory Range
+0x31 Reserved
+0x32 Role Switch Pending
+0x33 Reserved
+0x34 Reserved Slot Violation
+0x35 Role Switch Failed
+0x36 Extended Inquiry Response Too Large
+0x37 Secure Simple Pairing Not Supported By Host.
+0x38 Host Busy - Pairing
+0x39 Connection Rejected due to No Suitable Channel Found*/
+#define BLE_HCI_CONTROLLER_BUSY                        0x3A       /**< Controller Busy. */
+#define BLE_HCI_CONN_INTERVAL_UNACCEPTABLE             0x3B       /**< Connection Interval Unacceptable. */
+#define BLE_HCI_DIRECTED_ADVERTISER_TIMEOUT            0x3C       /**< Directed Adverisement Timeout. */
+#define BLE_HCI_CONN_TERMINATED_DUE_TO_MIC_FAILURE     0x3D       /**< Connection Terminated due to MIC Failure. */
+#define BLE_HCI_CONN_FAILED_TO_BE_ESTABLISHED          0x3E       /**< Connection Failed to be Established. */
+
+/** @} */
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif // BLE_HCI_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_l2cap.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,204 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+  @addtogroup BLE_L2CAP Logical Link Control and Adaptation Protocol (L2CAP)
+  @{
+  @brief Definitions and prototypes for the L2CAP interface.
+ */
+
+#ifndef BLE_L2CAP_H__
+#define BLE_L2CAP_H__
+
+#include "ble_types.h"
+#include "ble_ranges.h"
+#include "ble_err.h"
+#include "nrf_svc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@addtogroup BLE_L2CAP_ENUMERATIONS Enumerations
+ * @{ */
+
+/**@brief L2CAP API SVC numbers. */
+enum BLE_L2CAP_SVCS
+{
+  SD_BLE_L2CAP_CID_REGISTER = BLE_L2CAP_SVC_BASE,  /**< Register a CID. */
+  SD_BLE_L2CAP_CID_UNREGISTER,                     /**< Unregister a CID. */
+  SD_BLE_L2CAP_TX                                  /**< Transmit a packet. */
+};
+
+/**@brief L2CAP Event IDs. */
+enum BLE_L2CAP_EVTS
+{
+  BLE_L2CAP_EVT_RX  = BLE_L2CAP_EVT_BASE          /**< L2CAP packet received. */
+};
+
+/** @} */
+
+/**@addtogroup BLE_L2CAP_DEFINES Defines
+ * @{ */
+
+/**@defgroup BLE_ERRORS_L2CAP SVC return values specific to L2CAP
+ * @{ */
+#define BLE_ERROR_L2CAP_CID_IN_USE            (NRF_L2CAP_ERR_BASE + 0x000)  /**< CID already in use. */
+/** @} */
+
+/**@brief Default L2CAP MTU. */
+#define BLE_L2CAP_MTU_DEF           (23)
+
+/**@brief Invalid Channel Identifier. */
+#define BLE_L2CAP_CID_INVALID       (0x0000)
+
+/**@brief Dynamic Channel Identifier base. */
+#define BLE_L2CAP_CID_DYN_BASE      (0x0040)
+
+/**@brief Maximum amount of dynamic CIDs. */
+#define BLE_L2CAP_CID_DYN_MAX       (8)
+
+/** @} */
+
+/**@addtogroup BLE_L2CAP_STRUCTURES Structures
+ * @{ */
+
+/**@brief Packet header format for L2CAP transmission. */
+typedef struct
+{
+  uint16_t   len;                                 /**< Length of valid info in data member. */
+  uint16_t   cid;                                 /**< Channel ID on which packet is transmitted. */
+} ble_l2cap_header_t;
+
+
+/**@brief L2CAP Received packet event report. */
+typedef struct
+{
+  ble_l2cap_header_t header;                      /**< L2CAP packet header. */
+  uint8_t    data[1];                             /**< Packet data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                                       See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_l2cap_evt_rx_t;
+
+
+/**@brief L2CAP event callback event structure. */
+typedef struct
+{
+  uint16_t conn_handle;                           /**< Connection Handle on which event occured. */
+  union
+  {
+    ble_l2cap_evt_rx_t rx;                        /**< RX Event parameters. */
+  } params;                                       /**< Event Parameters. */
+} ble_l2cap_evt_t;
+
+/** @} */
+
+/**@addtogroup BLE_L2CAP_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Register a CID with L2CAP.
+ *
+ * @details This registers a higher protocol layer with the L2CAP multiplexer, and is requried prior to all operations on the CID.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_L2CAP_API_MSC}
+ * @endmscs
+ *
+ * @param[in] cid L2CAP CID.
+ *
+ * @retval ::NRF_SUCCESS Successfully registered a CID with the L2CAP layer.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, CID must be above @ref BLE_L2CAP_CID_DYN_BASE.
+ * @retval ::BLE_ERROR_L2CAP_CID_IN_USE L2CAP CID already in use.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ */
+SVCALL(SD_BLE_L2CAP_CID_REGISTER, uint32_t, sd_ble_l2cap_cid_register(uint16_t cid));
+
+/**@brief Unregister a CID with L2CAP.
+ *
+ * @details This unregisters a previously registerd higher protocol layer with the L2CAP multiplexer.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_L2CAP_API_MSC}
+ * @endmscs
+ *
+ * @param[in] cid L2CAP CID.
+ *
+ * @retval ::NRF_SUCCESS Successfully unregistered the CID.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_NOT_FOUND CID not previously registered.
+ */
+SVCALL(SD_BLE_L2CAP_CID_UNREGISTER, uint32_t, sd_ble_l2cap_cid_unregister(uint16_t cid));
+
+/**@brief Transmit an L2CAP packet.
+ *
+ * @note    It is important to note that a call to this function will <b>consume an application packet</b>, and will therefore
+ *          generate a @ref BLE_EVT_TX_COMPLETE event when the packet has been transmitted.
+ *          Please see the documentation of @ref sd_ble_tx_packet_count_get for more details.
+ *
+ * @events
+ * @event{@ref BLE_EVT_TX_COMPLETE}
+ * @event{@ref BLE_L2CAP_EVT_RX}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_L2CAP_API_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection Handle.
+ * @param[in] p_header    Pointer to a packet header containing length and CID.
+ * @param[in] p_data      Pointer to the data to be transmitted.
+ *
+ * @retval ::NRF_SUCCESS Successfully queued an L2CAP packet for transmission.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, CIDs must be registered beforehand with @ref sd_ble_l2cap_cid_register.
+ * @retval ::NRF_ERROR_NOT_FOUND CID not found.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ * @retval ::BLE_ERROR_NO_TX_PACKETS Not enough application packets available.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, see @ref BLE_L2CAP_MTU_DEF.
+ */
+SVCALL(SD_BLE_L2CAP_TX, uint32_t, sd_ble_l2cap_tx(uint16_t conn_handle, ble_l2cap_header_t const *p_header, uint8_t const *p_data));
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // BLE_L2CAP_H__
+
+/**
+  @}
+*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_ranges.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,140 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+  @addtogroup BLE_COMMON
+  @{
+  @defgroup ble_ranges Module specific SVC, event and option number subranges
+  @{
+
+  @brief Definition of SVC, event and option number subranges for each API module.
+
+  @note
+  SVCs, event and option numbers are split into subranges for each API module.
+  Each module receives its entire allocated range of SVC calls, whether implemented or not,
+  but return BLE_ERROR_NOT_SUPPORTED for unimplemented or undefined calls in its range.
+
+  Note that the symbols BLE_<module>_SVC_LAST is the end of the allocated SVC range,
+  rather than the last SVC function call actually defined and implemented.
+
+  Specific SVC, event and option values are defined in each module's ble_<module>.h file,
+  which defines names of each individual SVC code based on the range start value.
+*/
+
+#ifndef BLE_RANGES_H__
+#define BLE_RANGES_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BLE_SVC_BASE           0x60       /**< Common BLE SVC base. */
+#define BLE_SVC_LAST           0x6B       /**< Common BLE SVC last. */
+
+
+#define BLE_GAP_SVC_BASE       0x6C       /**< GAP BLE SVC base. */
+#define BLE_GAP_SVC_LAST       0x93       /**< GAP BLE SVC last. */
+
+
+#define BLE_GATTC_SVC_BASE     0x94       /**< GATTC BLE SVC base. */
+#define BLE_GATTC_SVC_LAST     0x9F       /**< GATTC BLE SVC last. */
+
+
+#define BLE_GATTS_SVC_BASE     0xA0       /**< GATTS BLE SVC base. */
+#define BLE_GATTS_SVC_LAST     0xAF       /**< GATTS BLE SVC last. */
+
+
+#define BLE_L2CAP_SVC_BASE     0xB0       /**< L2CAP BLE SVC base. */
+#define BLE_L2CAP_SVC_LAST     0xBF       /**< L2CAP BLE SVC last. */
+
+
+#define BLE_EVT_INVALID        0x00       /**< Invalid BLE Event. */
+
+
+#define BLE_EVT_BASE           0x01       /**< Common BLE Event base. */
+#define BLE_EVT_LAST           0x0F       /**< Common BLE Event last. */
+
+
+#define BLE_GAP_EVT_BASE       0x10       /**< GAP BLE Event base. */
+#define BLE_GAP_EVT_LAST       0x2F       /**< GAP BLE Event last. */
+
+
+#define BLE_GATTC_EVT_BASE     0x30       /**< GATTC BLE Event base. */
+#define BLE_GATTC_EVT_LAST     0x4F       /**< GATTC BLE Event last. */
+
+
+#define BLE_GATTS_EVT_BASE     0x50       /**< GATTS BLE Event base. */
+#define BLE_GATTS_EVT_LAST     0x6F       /**< GATTS BLE Event last. */
+
+
+#define BLE_L2CAP_EVT_BASE     0x70       /**< L2CAP BLE Event base. */
+#define BLE_L2CAP_EVT_LAST     0x8F       /**< L2CAP BLE Event last. */
+
+
+#define BLE_OPT_INVALID        0x00       /**< Invalid BLE Option. */
+
+
+#define BLE_OPT_BASE           0x01       /**< Common BLE Option base. */
+#define BLE_OPT_LAST           0x1F       /**< Common BLE Option last. */
+
+
+#define BLE_GAP_OPT_BASE       0x20       /**< GAP BLE Option base. */
+#define BLE_GAP_OPT_LAST       0x3F       /**< GAP BLE Option last. */
+
+
+#define BLE_GATTC_OPT_BASE     0x40       /**< GATTC BLE Option base. */
+#define BLE_GATTC_OPT_LAST     0x5F       /**< GATTC BLE Option last. */
+
+
+#define BLE_GATTS_OPT_BASE     0x60       /**< GATTS BLE Option base. */
+#define BLE_GATTS_OPT_LAST     0x7F       /**< GATTS BLE Option last. */
+
+
+#define BLE_L2CAP_OPT_BASE     0x80       /**< L2CAP BLE Option base. */
+#define BLE_L2CAP_OPT_LAST     0x9F       /**< L2CAP BLE Option last. */
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BLE_RANGES_H__ */
+
+/**
+  @}
+  @}
+*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_types.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,207 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+  @addtogroup BLE_COMMON
+  @{
+  @defgroup ble_types Common types and macro definitions
+  @{
+
+  @brief Common types and macro definitions for the BLE SoftDevice.
+ */
+
+#ifndef BLE_TYPES_H__
+#define BLE_TYPES_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup BLE_TYPES_DEFINES Defines
+ * @{ */
+
+/** @defgroup BLE_CONN_HANDLES BLE Connection Handles
+ * @{ */
+#define BLE_CONN_HANDLE_INVALID 0xFFFF  /**< Invalid Connection Handle. */
+#define BLE_CONN_HANDLE_ALL     0xFFFE  /**< Applies to all Connection Handles. */
+/** @} */
+
+
+/** @defgroup BLE_UUID_VALUES Assigned Values for BLE UUIDs
+ * @{ */
+/* Generic UUIDs, applicable to all services */
+#define BLE_UUID_UNKNOWN                              0x0000 /**< Reserved UUID. */
+#define BLE_UUID_SERVICE_PRIMARY                      0x2800 /**< Primary Service. */
+#define BLE_UUID_SERVICE_SECONDARY                    0x2801 /**< Secondary Service. */
+#define BLE_UUID_SERVICE_INCLUDE                      0x2802 /**< Include. */
+#define BLE_UUID_CHARACTERISTIC                       0x2803 /**< Characteristic. */
+#define BLE_UUID_DESCRIPTOR_CHAR_EXT_PROP             0x2900 /**< Characteristic Extended Properties Descriptor. */
+#define BLE_UUID_DESCRIPTOR_CHAR_USER_DESC            0x2901 /**< Characteristic User Description Descriptor. */
+#define BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG        0x2902 /**< Client Characteristic Configuration Descriptor. */
+#define BLE_UUID_DESCRIPTOR_SERVER_CHAR_CONFIG        0x2903 /**< Server Characteristic Configuration Descriptor. */
+#define BLE_UUID_DESCRIPTOR_CHAR_PRESENTATION_FORMAT  0x2904 /**< Characteristic Presentation Format Descriptor. */
+#define BLE_UUID_DESCRIPTOR_CHAR_AGGREGATE_FORMAT     0x2905 /**< Characteristic Aggregate Format Descriptor. */
+/* GATT specific UUIDs */
+#define BLE_UUID_GATT                                 0x1801 /**< Generic Attribute Profile. */
+#define BLE_UUID_GATT_CHARACTERISTIC_SERVICE_CHANGED  0x2A05 /**< Service Changed Characteristic. */
+/* GAP specific UUIDs */
+#define BLE_UUID_GAP                                  0x1800 /**< Generic Access Profile. */
+#define BLE_UUID_GAP_CHARACTERISTIC_DEVICE_NAME       0x2A00 /**< Device Name Characteristic. */
+#define BLE_UUID_GAP_CHARACTERISTIC_APPEARANCE        0x2A01 /**< Appearance Characteristic. */
+#define BLE_UUID_GAP_CHARACTERISTIC_RECONN_ADDR       0x2A03 /**< Reconnection Address Characteristic. */
+#define BLE_UUID_GAP_CHARACTERISTIC_PPCP              0x2A04 /**< Peripheral Preferred Connection Parameters Characteristic. */
+#define BLE_UUID_GAP_CHARACTERISTIC_CAR               0x2AA6 /**< Central Address Resolution Characteristic. */
+/** @} */
+
+
+/** @defgroup BLE_UUID_TYPES Types of UUID
+ * @{ */
+#define BLE_UUID_TYPE_UNKNOWN       0x00 /**< Invalid UUID type. */
+#define BLE_UUID_TYPE_BLE           0x01 /**< Bluetooth SIG UUID (16-bit). */
+#define BLE_UUID_TYPE_VENDOR_BEGIN  0x02 /**< Vendor UUID types start at this index (128-bit). */
+/** @} */
+
+
+/** @defgroup BLE_APPEARANCES Bluetooth Appearance values
+ *  @note Retrieved from http://developer.bluetooth.org/gatt/characteristics/Pages/CharacteristicViewer.aspx?u=org.bluetooth.characteristic.gap.appearance.xml
+ * @{ */
+#define BLE_APPEARANCE_UNKNOWN                                0 /**< Unknown. */
+#define BLE_APPEARANCE_GENERIC_PHONE                         64 /**< Generic Phone. */
+#define BLE_APPEARANCE_GENERIC_COMPUTER                     128 /**< Generic Computer. */
+#define BLE_APPEARANCE_GENERIC_WATCH                        192 /**< Generic Watch. */
+#define BLE_APPEARANCE_WATCH_SPORTS_WATCH                   193 /**< Watch: Sports Watch. */
+#define BLE_APPEARANCE_GENERIC_CLOCK                        256 /**< Generic Clock. */
+#define BLE_APPEARANCE_GENERIC_DISPLAY                      320 /**< Generic Display. */
+#define BLE_APPEARANCE_GENERIC_REMOTE_CONTROL               384 /**< Generic Remote Control. */
+#define BLE_APPEARANCE_GENERIC_EYE_GLASSES                  448 /**< Generic Eye-glasses. */
+#define BLE_APPEARANCE_GENERIC_TAG                          512 /**< Generic Tag. */
+#define BLE_APPEARANCE_GENERIC_KEYRING                      576 /**< Generic Keyring. */
+#define BLE_APPEARANCE_GENERIC_MEDIA_PLAYER                 640 /**< Generic Media Player. */
+#define BLE_APPEARANCE_GENERIC_BARCODE_SCANNER              704 /**< Generic Barcode Scanner. */
+#define BLE_APPEARANCE_GENERIC_THERMOMETER                  768 /**< Generic Thermometer. */
+#define BLE_APPEARANCE_THERMOMETER_EAR                      769 /**< Thermometer: Ear. */
+#define BLE_APPEARANCE_GENERIC_HEART_RATE_SENSOR            832 /**< Generic Heart rate Sensor. */
+#define BLE_APPEARANCE_HEART_RATE_SENSOR_HEART_RATE_BELT    833 /**< Heart Rate Sensor: Heart Rate Belt. */
+#define BLE_APPEARANCE_GENERIC_BLOOD_PRESSURE               896 /**< Generic Blood Pressure. */
+#define BLE_APPEARANCE_BLOOD_PRESSURE_ARM                   897 /**< Blood Pressure: Arm. */
+#define BLE_APPEARANCE_BLOOD_PRESSURE_WRIST                 898 /**< Blood Pressure: Wrist. */
+#define BLE_APPEARANCE_GENERIC_HID                          960 /**< Human Interface Device (HID). */
+#define BLE_APPEARANCE_HID_KEYBOARD                         961 /**< Keyboard (HID Subtype). */
+#define BLE_APPEARANCE_HID_MOUSE                            962 /**< Mouse (HID Subtype). */
+#define BLE_APPEARANCE_HID_JOYSTICK                         963 /**< Joystiq (HID Subtype). */
+#define BLE_APPEARANCE_HID_GAMEPAD                          964 /**< Gamepad (HID Subtype). */
+#define BLE_APPEARANCE_HID_DIGITIZERSUBTYPE                 965 /**< Digitizer Tablet (HID Subtype). */
+#define BLE_APPEARANCE_HID_CARD_READER                      966 /**< Card Reader (HID Subtype). */
+#define BLE_APPEARANCE_HID_DIGITAL_PEN                      967 /**< Digital Pen (HID Subtype). */
+#define BLE_APPEARANCE_HID_BARCODE                          968 /**< Barcode Scanner (HID Subtype). */
+#define BLE_APPEARANCE_GENERIC_GLUCOSE_METER               1024 /**< Generic Glucose Meter. */
+#define BLE_APPEARANCE_GENERIC_RUNNING_WALKING_SENSOR      1088 /**< Generic Running Walking Sensor. */
+#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_IN_SHOE      1089 /**< Running Walking Sensor: In-Shoe. */
+#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_SHOE      1090 /**< Running Walking Sensor: On-Shoe. */
+#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_HIP       1091 /**< Running Walking Sensor: On-Hip. */
+#define BLE_APPEARANCE_GENERIC_CYCLING                     1152 /**< Generic Cycling. */
+#define BLE_APPEARANCE_CYCLING_CYCLING_COMPUTER            1153 /**< Cycling: Cycling Computer. */
+#define BLE_APPEARANCE_CYCLING_SPEED_SENSOR                1154 /**< Cycling: Speed Sensor. */
+#define BLE_APPEARANCE_CYCLING_CADENCE_SENSOR              1155 /**< Cycling: Cadence Sensor. */
+#define BLE_APPEARANCE_CYCLING_POWER_SENSOR                1156 /**< Cycling: Power Sensor. */
+#define BLE_APPEARANCE_CYCLING_SPEED_CADENCE_SENSOR        1157 /**< Cycling: Speed and Cadence Sensor. */
+#define BLE_APPEARANCE_GENERIC_PULSE_OXIMETER              3136 /**< Generic Pulse Oximeter. */
+#define BLE_APPEARANCE_PULSE_OXIMETER_FINGERTIP            3137 /**< Fingertip (Pulse Oximeter subtype). */
+#define BLE_APPEARANCE_PULSE_OXIMETER_WRIST_WORN           3138 /**< Wrist Worn(Pulse Oximeter subtype). */
+#define BLE_APPEARANCE_GENERIC_WEIGHT_SCALE                3200 /**< Generic Weight Scale. */
+#define BLE_APPEARANCE_GENERIC_OUTDOOR_SPORTS_ACT          5184 /**< Generic Outdoor Sports Activity. */
+#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_DISP         5185 /**< Location Display Device (Outdoor Sports Activity subtype). */
+#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_AND_NAV_DISP 5186 /**< Location and Navigation Display Device (Outdoor Sports Activity subtype). */
+#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_POD          5187 /**< Location Pod (Outdoor Sports Activity subtype). */
+#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_AND_NAV_POD  5188 /**< Location and Navigation Pod (Outdoor Sports Activity subtype). */
+/** @} */
+
+/** @brief Set .type and .uuid fields of ble_uuid_struct to specified uuid value. */
+#define BLE_UUID_BLE_ASSIGN(instance, value) do {\
+            instance.type = BLE_UUID_TYPE_BLE; \
+            instance.uuid = value;} while(0)
+
+/** @brief Copy type and uuid members from src to dst ble_uuid_t pointer. Both pointers must be valid/non-null. */
+#define BLE_UUID_COPY_PTR(dst, src) do {\
+            (dst)->type = (src)->type; \
+            (dst)->uuid = (src)->uuid;} while(0)
+
+/** @brief Copy type and uuid members from src to dst ble_uuid_t struct. */
+#define BLE_UUID_COPY_INST(dst, src) do {\
+            (dst).type = (src).type; \
+            (dst).uuid = (src).uuid;} while(0)
+
+/** @brief Compare for equality both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */
+#define BLE_UUID_EQ(p_uuid1, p_uuid2) \
+            (((p_uuid1)->type == (p_uuid2)->type) && ((p_uuid1)->uuid == (p_uuid2)->uuid))
+
+/** @brief Compare for difference both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */
+#define BLE_UUID_NEQ(p_uuid1, p_uuid2) \
+            (((p_uuid1)->type != (p_uuid2)->type) || ((p_uuid1)->uuid != (p_uuid2)->uuid))
+
+/** @} */
+
+/** @addtogroup BLE_TYPES_STRUCTURES Structures
+ * @{ */
+
+/** @brief 128 bit UUID values. */
+typedef struct
+{ 
+  uint8_t uuid128[16]; /**< Little-Endian UUID bytes. */
+} ble_uuid128_t;
+
+/** @brief  Bluetooth Low Energy UUID type, encapsulates both 16-bit and 128-bit UUIDs. */
+typedef struct
+{
+  uint16_t    uuid; /**< 16-bit UUID value or octets 12-13 of 128-bit UUID. */
+  uint8_t     type; /**< UUID type, see @ref BLE_UUID_TYPES. If type is @ref BLE_UUID_TYPE_UNKNOWN, the value of uuid is undefined. */
+} ble_uuid_t;
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BLE_TYPES_H__ */
+
+/**
+  @}
+  @}
+*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf52/nrf_mbr.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/**
+  @defgroup nrf_mbr_api Master Boot Record API
+  @{
+
+  @brief APIs for updating SoftDevice and BootLoader
+
+*/
+
+/* Header guard */
+#ifndef NRF_MBR_H__
+#define NRF_MBR_H__
+
+#include "nrf_svc.h"
+#include <stdint.h>
+
+#ifndef NRF52840_XXAA
+#error "This header file shall only be included for nRF52 projects"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup NRF_MBR_DEFINES Defines
+ * @{ */
+
+/**@brief MBR SVC Base number. */
+#define MBR_SVC_BASE            (0x18)
+
+/**@brief Page size in words. */
+#define MBR_PAGE_SIZE_IN_WORDS  (1024)
+
+/** @brief The size that must be reserved for the MBR when a softdevice is written to flash.
+This is the offset where the first byte of the softdevice hex file is written.*/
+#define MBR_SIZE                (0x1000)
+
+/** @} */
+
+/** @addtogroup NRF_MBR_ENUMS Enumerations
+ * @{ */
+
+/**@brief nRF Master Boot Record API SVC numbers. */
+enum NRF_MBR_SVCS
+{
+  SD_MBR_COMMAND = MBR_SVC_BASE, /**< ::sd_mbr_command */
+};
+
+/**@brief Possible values for ::sd_mbr_command_t.command */
+enum NRF_MBR_COMMANDS
+{
+  SD_MBR_COMMAND_COPY_BL,               /**< Copy a new BootLoader. @see sd_mbr_command_copy_bl_t */
+  SD_MBR_COMMAND_COPY_SD,               /**< Copy a new SoftDevice. @see ::sd_mbr_command_copy_sd_t*/
+  SD_MBR_COMMAND_INIT_SD,               /**< Init forwarding interrupts to SD, and run reset function in SD*/
+  SD_MBR_COMMAND_COMPARE,               /**< This command works like memcmp. @see ::sd_mbr_command_compare_t*/
+  SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET, /**< Start forwarding all exception to this address @see ::sd_mbr_command_vector_table_base_set_t*/
+};
+
+/** @} */
+
+/** @addtogroup NRF_MBR_TYPES Types
+ * @{ */
+
+/**@brief This command copies part of a new SoftDevice
+ * The destination area is erased before copying.
+ * If dst is in the middle of a flash page, that whole flash page will be erased.
+ * If (dst+len) is in the middle of a flash page, that whole flash page will be erased.
+ *
+ * The user of this function is responsible for setting the BPROT registers.
+ *
+ * @retval ::NRF_SUCCESS indicates that the contents of the memory blocks where copied correctly.
+ * @retval ::NRF_ERROR_INTERNAL indicates that the contents of the memory blocks where not verified correctly after copying.
+ */
+typedef struct
+{
+  uint32_t *src;  /**< Pointer to the source of data to be copied.*/
+  uint32_t *dst;  /**< Pointer to the destination where the content is to be copied.*/
+  uint32_t len;   /**< Number of 32 bit words to copy. Must be a multiple of @ref MBR_PAGE_SIZE_IN_WORDS words.*/
+} sd_mbr_command_copy_sd_t;
+
+
+/**@brief This command works like memcmp, but takes the length in words.
+ *
+ * @retval ::NRF_SUCCESS indicates that the contents of both memory blocks are equal.
+ * @retval ::NRF_ERROR_NULL indicates that the contents of the memory blocks are not equal.
+ */
+typedef struct
+{
+  uint32_t *ptr1; /**< Pointer to block of memory. */
+  uint32_t *ptr2; /**< Pointer to block of memory. */
+  uint32_t len;   /**< Number of 32 bit words to compare.*/
+} sd_mbr_command_compare_t;
+
+
+/**@brief This command copies a new BootLoader.
+ *  With this command, destination of BootLoader is always the address written in NRF_UICR->BOOTADDR.
+ *
+ *  Destination is erased by this function.
+ *  If (destination+bl_len) is in the middle of a flash page, that whole flash page will be erased.
+ *
+ *  This function will use PROTENSET to protect the flash that is not intended to be written.
+ *
+ *  On Success, this function will not return. It will start the new BootLoader from reset-vector as normal.
+ *
+ * @retval ::NRF_ERROR_INTERNAL indicates an internal error that should not happen.
+ * @retval ::NRF_ERROR_FORBIDDEN if NRF_UICR->BOOTADDR is not set.
+ * @retval ::NRF_ERROR_INVALID_LENGTH if parameters attempts to read or write outside flash area.
+ * @retval ::NRF_ERROR_NO_MEM if no parameter page is provided (see sds for more info)
+ */
+typedef struct
+{
+  uint32_t *bl_src;  /**< Pointer to the source of the Bootloader to be be copied.*/
+  uint32_t bl_len;   /**< Number of 32 bit words to copy for BootLoader. */
+} sd_mbr_command_copy_bl_t;
+
+/**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the MBR
+ *
+ * Once this function has been called, this address is where the MBR will start to forward interrupts to after a reset.
+ *
+ * To restore default forwarding this function should be called with @param address set to 0.
+ * The MBR will then start forwarding to interrupts to the address in NFR_UICR->BOOTADDR or to the SoftDevice if the BOOTADDR is not set.
+ *
+ * On Success, this function will not return. It will reset the device.
+ *
+ * @retval ::NRF_ERROR_INTERNAL indicates an internal error that should not happen.
+ * @retval ::NRF_ERROR_INVALID_ADDR if parameter address is outside of the flash size.
+ * @retval ::NRF_ERROR_NO_MEM if no parameter page is provided (see sds for more info)
+ */
+typedef struct
+{
+  uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/
+} sd_mbr_command_vector_table_base_set_t;
+
+
+typedef struct
+{
+  uint32_t command;  /**< type of command to be issued see @ref NRF_MBR_COMMANDS. */
+  union
+  {
+    sd_mbr_command_copy_sd_t copy_sd;  /**< Parameters for copy SoftDevice.*/
+    sd_mbr_command_compare_t compare;  /**< Parameters for verify.*/
+    sd_mbr_command_copy_bl_t copy_bl;  /**< Parameters for copy BootLoader. Requires parameter page. */
+    sd_mbr_command_vector_table_base_set_t base_set; /**< Parameters for vector table base set. Requires parameter page.*/
+  } params;
+} sd_mbr_command_t;
+
+/** @} */
+
+/** @addtogroup NRF_MBR_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Issue Master Boot Record commands
+ *
+ * Commands used when updating a SoftDevice and bootloader.
+ *
+ * The SD_MBR_COMMAND_COPY_BL and SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET requires parameters to be
+ * retained by the MBR when resetting the IC. This is done in a separate flash page
+ * provided by the application. The uicr register UICR.NRFFW[1] must be set
+ * to an address corresponding to a page in the application flash space. This page will be cleared
+ * by the MBR and used to store the command before reset. When the UICR.NRFFW[1] field is set
+ * the page it refers to must not be used by the application. If the UICR.NRFFW[1] is set to
+ * 0xFFFFFFFF (the default) MBR commands which use flash will be unavailable and return
+ * NRF_ERROR_NO_MEM.
+ *
+ * @param[in]  param Pointer to a struct describing the command.
+ *
+ * @note for retvals see ::sd_mbr_command_copy_sd_t ::sd_mbr_command_copy_bl_t ::sd_mbr_command_compare_t ::sd_mbr_command_vector_table_base_set_t
+ *
+ * @retval NRF_ERROR_NO_MEM if UICR.NRFFW[1] is not set (i.e. is 0xFFFFFFFF).
+ * @retval NRF_ERROR_INVALID_PARAM if an invalid command is given.
+*/
+SVCALL(SD_MBR_COMMAND, uint32_t, sd_mbr_command(sd_mbr_command_t* param));
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_MBR_H__
+
+/**
+  @}
+*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_error.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,89 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */ 
+ /**
+  @defgroup nrf_error SoftDevice Global Error Codes
+  @{
+   
+  @brief Global Error definitions
+*/
+
+/* Header guard */
+#ifndef NRF_ERROR_H__
+#define NRF_ERROR_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup NRF_ERRORS_BASE Error Codes Base number definitions
+ * @{ */
+#define NRF_ERROR_BASE_NUM      (0x0)       ///< Global error base
+#define NRF_ERROR_SDM_BASE_NUM  (0x1000)    ///< SDM error base
+#define NRF_ERROR_SOC_BASE_NUM  (0x2000)    ///< SoC error base
+#define NRF_ERROR_STK_BASE_NUM  (0x3000)    ///< STK error base
+/** @} */
+
+#define NRF_SUCCESS                           (NRF_ERROR_BASE_NUM + 0)  ///< Successful command
+#define NRF_ERROR_SVC_HANDLER_MISSING         (NRF_ERROR_BASE_NUM + 1)  ///< SVC handler is missing
+#define NRF_ERROR_SOFTDEVICE_NOT_ENABLED      (NRF_ERROR_BASE_NUM + 2)  ///< SoftDevice has not been enabled
+#define NRF_ERROR_INTERNAL                    (NRF_ERROR_BASE_NUM + 3)  ///< Internal Error
+#define NRF_ERROR_NO_MEM                      (NRF_ERROR_BASE_NUM + 4)  ///< No Memory for operation
+#define NRF_ERROR_NOT_FOUND                   (NRF_ERROR_BASE_NUM + 5)  ///< Not found
+#define NRF_ERROR_NOT_SUPPORTED               (NRF_ERROR_BASE_NUM + 6)  ///< Not supported
+#define NRF_ERROR_INVALID_PARAM               (NRF_ERROR_BASE_NUM + 7)  ///< Invalid Parameter
+#define NRF_ERROR_INVALID_STATE               (NRF_ERROR_BASE_NUM + 8)  ///< Invalid state, operation disallowed in this state
+#define NRF_ERROR_INVALID_LENGTH              (NRF_ERROR_BASE_NUM + 9)  ///< Invalid Length
+#define NRF_ERROR_INVALID_FLAGS               (NRF_ERROR_BASE_NUM + 10) ///< Invalid Flags
+#define NRF_ERROR_INVALID_DATA                (NRF_ERROR_BASE_NUM + 11) ///< Invalid Data
+#define NRF_ERROR_DATA_SIZE                   (NRF_ERROR_BASE_NUM + 12) ///< Invalid Data size
+#define NRF_ERROR_TIMEOUT                     (NRF_ERROR_BASE_NUM + 13) ///< Operation timed out
+#define NRF_ERROR_NULL                        (NRF_ERROR_BASE_NUM + 14) ///< Null Pointer
+#define NRF_ERROR_FORBIDDEN                   (NRF_ERROR_BASE_NUM + 15) ///< Forbidden Operation
+#define NRF_ERROR_INVALID_ADDR                (NRF_ERROR_BASE_NUM + 16) ///< Bad Memory Address
+#define NRF_ERROR_BUSY                        (NRF_ERROR_BASE_NUM + 17) ///< Busy
+#define NRF_ERROR_CONN_COUNT                  (NRF_ERROR_BASE_NUM + 18) ///< Maximum connection count exceeded.
+#define NRF_ERROR_RESOURCES                   (NRF_ERROR_BASE_NUM + 19) ///< Not enough resources for operation
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_ERROR_H__
+
+/**
+  @}
+*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_error_sdm.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,69 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ /**
+  @addtogroup nrf_sdm_api
+  @{
+  @defgroup nrf_sdm_error SoftDevice Manager Error Codes
+  @{
+
+  @brief Error definitions for the SDM API
+*/
+
+/* Header guard */
+#ifndef NRF_ERROR_SDM_H__
+#define NRF_ERROR_SDM_H__
+
+#include "nrf_error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN              (NRF_ERROR_SDM_BASE_NUM + 0)  ///< Unknown lfclk source.
+#define NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION (NRF_ERROR_SDM_BASE_NUM + 1)  ///< Incorrect interrupt configuration (can be caused by using illegal priority levels, or having enabled SoftDevice interrupts).
+#define NRF_ERROR_SDM_INCORRECT_CLENR0                  (NRF_ERROR_SDM_BASE_NUM + 2)  ///< Incorrect CLENR0 (can be caused by erronous SoftDevice flashing).
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_ERROR_SDM_H__
+
+/**
+  @}
+  @}
+*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_error_soc.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,84 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+/**
+  @addtogroup nrf_soc_api
+  @{
+  @defgroup nrf_soc_error SoC Library Error Codes
+  @{
+     
+  @brief Error definitions for the SoC library
+
+*/
+
+/* Header guard */
+#ifndef NRF_ERROR_SOC_H__
+#define NRF_ERROR_SOC_H__
+
+#include "nrf_error.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Mutex Errors */
+#define NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN                 (NRF_ERROR_SOC_BASE_NUM + 0)  ///< Mutex already taken
+
+/* NVIC errors */
+#define NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE        (NRF_ERROR_SOC_BASE_NUM + 1)  ///< NVIC interrupt not available
+#define NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED (NRF_ERROR_SOC_BASE_NUM + 2)  ///< NVIC interrupt priority not allowed
+#define NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN              (NRF_ERROR_SOC_BASE_NUM + 3)  ///< NVIC should not return
+
+/* Power errors */
+#define NRF_ERROR_SOC_POWER_MODE_UNKNOWN                  (NRF_ERROR_SOC_BASE_NUM + 4)  ///< Power mode unknown
+#define NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN         (NRF_ERROR_SOC_BASE_NUM + 5)  ///< Power POF threshold unknown
+#define NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN         (NRF_ERROR_SOC_BASE_NUM + 6)  ///< Power off should not return
+
+/* Rand errors */
+#define NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES              (NRF_ERROR_SOC_BASE_NUM + 7)  ///< RAND not enough values
+
+/* PPI errors */
+#define NRF_ERROR_SOC_PPI_INVALID_CHANNEL                 (NRF_ERROR_SOC_BASE_NUM + 8)  ///< Invalid PPI Channel
+#define NRF_ERROR_SOC_PPI_INVALID_GROUP                   (NRF_ERROR_SOC_BASE_NUM + 9)  ///< Invalid PPI Group
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_ERROR_SOC_H__
+/**
+  @}
+  @}
+*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_nvic.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,521 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+/**
+ * @defgroup nrf_nvic_api SoftDevice NVIC API
+ * @{
+ *
+ * @note In order to use this module, the following code has to be added to a .c file:
+ *     \code
+ *     nrf_nvic_state_t nrf_nvic_state = {0};
+ *     \endcode
+ *
+ * @note Definitions and declarations starting with __ (double underscore) in this header file are
+ * not intended for direct use by the application.
+ *
+ * @brief APIs for the accessing NVIC when using a SoftDevice.
+ *
+ */
+
+#ifndef NRF_NVIC_H__
+#define NRF_NVIC_H__
+
+#include <stdint.h>
+#include "nrf.h"
+
+#include "nrf_error_soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@addtogroup NRF_NVIC_DEFINES Defines
+ * @{ */
+
+/**@defgroup NRF_NVIC_ISER_DEFINES SoftDevice NVIC internal definitions
+ * @{ */
+
+#define __NRF_NVIC_NVMC_IRQn (30) /**< The peripheral ID of the NVMC. IRQ numbers are used to identify peripherals, but the NVMC doesn't have an IRQ number in the MDK. */
+
+#ifdef NRF51
+  #define __NRF_NVIC_ISER_COUNT (1) /**< The number of ISER/ICER registers in the NVIC that are used. */
+
+  /**@brief Interrupts used by the SoftDevice. */
+  #define __NRF_NVIC_SD_IRQS_0 ((uint32_t)( \
+        (1U << POWER_CLOCK_IRQn) \
+      | (1U << RADIO_IRQn) \
+      | (1U << RTC0_IRQn) \
+      | (1U << TIMER0_IRQn) \
+      | (1U << RNG_IRQn) \
+      | (1U << ECB_IRQn) \
+      | (1U << CCM_AAR_IRQn) \
+      | (1U << TEMP_IRQn) \
+      | (1U << __NRF_NVIC_NVMC_IRQn) \
+      | (1U << (uint32_t)SWI4_IRQn) \
+      | (1U << (uint32_t)SWI5_IRQn) \
+    ))
+
+  /**@brief Interrupts available for to application. */
+  #define __NRF_NVIC_APP_IRQS_0 (~__NRF_NVIC_SD_IRQS_0)
+#endif
+
+#ifdef NRF52_SERIES
+  #define __NRF_NVIC_ISER_COUNT (2) /**< The number of ISER/ICER registers in the NVIC that are used. */
+
+  /**@brief Interrupts used by the SoftDevice. */
+  #define __NRF_NVIC_SD_IRQS_0 ((uint32_t)( \
+        (1U << POWER_CLOCK_IRQn) \
+      | (1U << RADIO_IRQn) \
+      | (1U << RTC0_IRQn) \
+      | (1U << TIMER0_IRQn) \
+      | (1U << RNG_IRQn) \
+      | (1U << ECB_IRQn) \
+      | (1U << CCM_AAR_IRQn) \
+      | (1U << TEMP_IRQn) \
+      | (1U << __NRF_NVIC_NVMC_IRQn) \
+      | (1U << (uint32_t)SWI4_EGU4_IRQn) \
+      | (1U << (uint32_t)SWI5_EGU5_IRQn) \
+    ))
+  #define __NRF_NVIC_SD_IRQS_1 ((uint32_t)0)
+
+  /**@brief Interrupts available for to application. */
+  #define __NRF_NVIC_APP_IRQS_0 (~__NRF_NVIC_SD_IRQS_0)
+  #define __NRF_NVIC_APP_IRQS_1 (~__NRF_NVIC_SD_IRQS_1)
+#endif
+/**@} */
+
+/**@} */
+
+/**@addtogroup NRF_NVIC_VARIABLES Variables
+ * @{ */
+
+/**@brief Type representing the state struct for the SoftDevice NVIC module. */
+typedef struct
+{
+  uint32_t volatile __irq_masks[__NRF_NVIC_ISER_COUNT]; /**< IRQs enabled by the application in the NVIC. */
+  uint32_t volatile __cr_flag;                          /**< Non-zero if already in a critical region */
+} nrf_nvic_state_t;
+
+/**@brief Variable keeping the state for the SoftDevice NVIC module. This must be declared in an
+ * application source file. */
+extern nrf_nvic_state_t nrf_nvic_state;
+
+/**@} */
+
+/**@addtogroup NRF_NVIC_INTERNAL_FUNCTIONS SoftDevice NVIC internal functions
+ * @{ */
+
+/**@brief Disables IRQ interrupts globally, including the SoftDevice's interrupts.
+ *
+ * @retval  The value of PRIMASK prior to disabling the interrupts.
+ */
+__STATIC_INLINE int __sd_nvic_irq_disable(void);
+
+/**@brief Enables IRQ interrupts globally, including the SoftDevice's interrupts.
+ */
+__STATIC_INLINE void __sd_nvic_irq_enable(void);
+
+/**@brief Checks if IRQn is available to application
+ * @param[in]  IRQn  irq to check
+ *
+ * @retval  1 (true) if the irq to check is available to the application
+ */
+__STATIC_INLINE uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn);
+
+/**@brief Checks if priority is available to application
+ * @param[in]  priority  priority to check
+ *
+ * @retval  1 (true) if the priority to check is available to the application
+ */
+__STATIC_INLINE uint32_t __sd_nvic_is_app_accessible_priority(uint32_t priority);
+
+/**@} */
+
+/**@addtogroup NRF_NVIC_FUNCTIONS SoftDevice NVIC public functions
+ * @{ */
+
+/**@brief Enable External Interrupt.
+ * @note Corresponds to NVIC_EnableIRQ in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ *
+ * @param[in] IRQn See the NVIC_EnableIRQ documentation in CMSIS.
+ *
+ * @retval ::NRF_SUCCESS The interrupt was enabled.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt has a priority not available for the application.
+ */
+__STATIC_INLINE uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn);
+
+/**@brief  Disable External Interrupt.
+ * @note Corresponds to NVIC_DisableIRQ in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ *
+ * @param[in] IRQn See the NVIC_DisableIRQ documentation in CMSIS.
+ *
+ * @retval ::NRF_SUCCESS The interrupt was disabled.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application.
+ */
+__STATIC_INLINE uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn);
+
+/**@brief  Get Pending Interrupt.
+ * @note Corresponds to NVIC_GetPendingIRQ in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ *
+ * @param[in]   IRQn          See the NVIC_GetPendingIRQ documentation in CMSIS.
+ * @param[out]  p_pending_irq Return value from NVIC_GetPendingIRQ.
+ *
+ * @retval ::NRF_SUCCESS The interrupt is available for the application.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
+ */
+__STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq);
+
+/**@brief  Set Pending Interrupt.
+ * @note Corresponds to NVIC_SetPendingIRQ in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ *
+ * @param[in] IRQn See the NVIC_SetPendingIRQ documentation in CMSIS.
+ *
+ * @retval ::NRF_SUCCESS The interrupt is set pending.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
+ */
+__STATIC_INLINE uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn);
+
+/**@brief  Clear Pending Interrupt.
+ * @note Corresponds to NVIC_ClearPendingIRQ in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ *
+ * @param[in] IRQn See the NVIC_ClearPendingIRQ documentation in CMSIS.
+ *
+ * @retval ::NRF_SUCCESS The interrupt pending flag is cleared.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
+ */
+__STATIC_INLINE uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn);
+
+/**@brief Set Interrupt Priority.
+ * @note Corresponds to NVIC_SetPriority in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ * @pre Priority is valid and not reserved by the stack.
+ *
+ * @param[in] IRQn      See the NVIC_SetPriority documentation in CMSIS.
+ * @param[in] priority  A valid IRQ priority for use by the application.
+ *
+ * @retval ::NRF_SUCCESS The interrupt and priority level is available for the application.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt priority is not available for the application.
+ */
+__STATIC_INLINE uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority);
+
+/**@brief Get Interrupt Priority.
+ * @note Corresponds to NVIC_GetPriority in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ *
+ * @param[in]  IRQn         See the NVIC_GetPriority documentation in CMSIS.
+ * @param[out] p_priority   Return value from NVIC_GetPriority.
+ *
+ * @retval ::NRF_SUCCESS The interrupt priority is returned in p_priority.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE - IRQn is not available for the application.
+ */
+__STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority);
+
+/**@brief System Reset.
+ * @note Corresponds to NVIC_SystemReset in CMSIS.
+ *
+ * @retval ::NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN
+ */
+__STATIC_INLINE uint32_t sd_nvic_SystemReset(void);
+
+/**@brief Enter critical region.
+ *
+ * @post Application interrupts will be disabled.
+ * @note sd_nvic_critical_region_enter() and ::sd_nvic_critical_region_exit() must be called in matching pairs inside each
+ * execution context
+ * @sa sd_nvic_critical_region_exit
+ *
+ * @param[out] p_is_nested_critical_region If 1, the application is now in a nested critical region.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+__STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region);
+
+/**@brief Exit critical region.
+ *
+ * @pre Application has entered a critical region using ::sd_nvic_critical_region_enter.
+ * @post If not in a nested critical region, the application interrupts will restored to the state before ::sd_nvic_critical_region_enter was called.
+ *
+ * @param[in] is_nested_critical_region If this is set to 1, the critical region won't be exited. @sa sd_nvic_critical_region_enter.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+__STATIC_INLINE uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region);
+
+/**@} */
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE int __sd_nvic_irq_disable(void)
+{
+  int pm = __get_PRIMASK();
+  __disable_irq();
+  return pm;
+}
+
+__STATIC_INLINE void __sd_nvic_irq_enable(void)
+{
+  __enable_irq();
+}
+
+__STATIC_INLINE uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn)
+{
+  if (IRQn < 32)
+  {
+    return ((1UL<<IRQn) & __NRF_NVIC_APP_IRQS_0) != 0;
+  }
+#ifdef NRF52_SERIES
+  else if (IRQn < 64)
+  {
+    return ((1UL<<(IRQn-32)) & __NRF_NVIC_APP_IRQS_1) != 0;
+  }
+#endif
+  else
+  {
+    return 1;
+  }
+}
+
+__STATIC_INLINE uint32_t __sd_nvic_is_app_accessible_priority(uint32_t priority)
+{
+  if(priority >= (1 << __NVIC_PRIO_BITS))
+  {
+    return 0;
+  }
+#ifdef NRF51
+  if(   priority == 0
+     || priority == 2
+     )
+  {
+    return 0;
+  }
+#endif
+#ifdef NRF52_SERIES
+  if(   priority == 0
+     || priority == 1
+     || priority == 4
+     || priority == 5
+     )
+  {
+    return 0;
+  }
+#endif
+  return 1;
+}
+
+
+__STATIC_INLINE uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn)
+{
+  if (!__sd_nvic_app_accessible_irq(IRQn))
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+  if (!__sd_nvic_is_app_accessible_priority(NVIC_GetPriority(IRQn)))
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED;
+  }
+
+  if (nrf_nvic_state.__cr_flag)
+  {
+    nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] |= (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F));
+  }
+  else
+  {
+    NVIC_EnableIRQ(IRQn);
+  }
+  return NRF_SUCCESS;
+}
+
+__STATIC_INLINE uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn)
+{
+  if (!__sd_nvic_app_accessible_irq(IRQn))
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+
+  if (nrf_nvic_state.__cr_flag)
+  {
+    nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] &= ~(1UL << ((uint32_t)(IRQn) & 0x1F));
+  }
+  else
+  {
+    NVIC_DisableIRQ(IRQn);
+  }
+
+  return NRF_SUCCESS;
+}
+
+__STATIC_INLINE uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq)
+{
+  if (__sd_nvic_app_accessible_irq(IRQn))
+  {
+    *p_pending_irq = NVIC_GetPendingIRQ(IRQn);
+    return NRF_SUCCESS;
+  }
+  else
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+}
+
+__STATIC_INLINE uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if (__sd_nvic_app_accessible_irq(IRQn))
+  {
+    NVIC_SetPendingIRQ(IRQn);
+    return NRF_SUCCESS;
+  }
+  else
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+}
+
+__STATIC_INLINE uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if (__sd_nvic_app_accessible_irq(IRQn))
+  {
+    NVIC_ClearPendingIRQ(IRQn);
+    return NRF_SUCCESS;
+  }
+  else
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+}
+
+__STATIC_INLINE uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if (!__sd_nvic_app_accessible_irq(IRQn))
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+
+  if (!__sd_nvic_is_app_accessible_priority(priority))
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED;
+  }
+
+  NVIC_SetPriority(IRQn, (uint32_t)priority);
+  return NRF_SUCCESS;
+}
+
+__STATIC_INLINE uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority)
+{
+  if (__sd_nvic_app_accessible_irq(IRQn))
+  {
+    *p_priority = (NVIC_GetPriority(IRQn) & 0xFF);
+    return NRF_SUCCESS;
+  }
+  else
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+}
+
+__STATIC_INLINE uint32_t sd_nvic_SystemReset(void)
+{
+  NVIC_SystemReset();
+  return NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN;
+}
+
+__STATIC_INLINE uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region)
+{
+  int was_masked = __sd_nvic_irq_disable();
+  if (!nrf_nvic_state.__cr_flag)
+  {
+    nrf_nvic_state.__cr_flag = 1;
+    nrf_nvic_state.__irq_masks[0] = ( NVIC->ICER[0] & __NRF_NVIC_APP_IRQS_0 );
+    NVIC->ICER[0] = __NRF_NVIC_APP_IRQS_0;
+    #ifdef NRF52_SERIES
+    nrf_nvic_state.__irq_masks[1] = ( NVIC->ICER[1] & __NRF_NVIC_APP_IRQS_1 );
+    NVIC->ICER[1] = __NRF_NVIC_APP_IRQS_1;
+    #endif
+    *p_is_nested_critical_region = 0;
+  }
+  else
+  {
+    *p_is_nested_critical_region = 1;
+  }
+  if (!was_masked)
+  {
+    __sd_nvic_irq_enable();
+  }
+  return NRF_SUCCESS;
+}
+
+__STATIC_INLINE uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region)
+{
+  if (nrf_nvic_state.__cr_flag && (is_nested_critical_region == 0))
+  {
+    int was_masked = __sd_nvic_irq_disable();
+    NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0];
+    #ifdef NRF52_SERIES
+    NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1];
+    #endif
+    nrf_nvic_state.__cr_flag = 0;
+    if (!was_masked)
+    {
+      __sd_nvic_irq_enable();
+    }
+  }
+
+  return NRF_SUCCESS;
+}
+
+#endif /* SUPPRESS_INLINE_IMPLEMENTATION */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_NVIC_H__
+
+/**@} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_sd_def.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,58 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_SD_DEF_H__
+#define NRF_SD_DEF_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SD_PPI_CHANNELS_USED            0xFFFE0000uL /**< PPI channels utilized by SotfDevice (not available to the application). */
+#define SD_PPI_GROUPS_USED              0x0000000CuL /**< PPI groups utilized by SoftDevice (not available to the application). */
+#define SD_TIMERS_USED                  0x00000001uL /**< Timers used by SoftDevice. */
+#define SD_SWI_USED                     0x0000003CuL /**< Software interrupts used by SoftDevice */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF_SD_DEF_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_sdm.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,335 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+/**
+  @defgroup nrf_sdm_api SoftDevice Manager API
+  @{
+
+  @brief APIs for SoftDevice management.
+
+*/
+
+#ifndef NRF_SDM_H__
+#define NRF_SDM_H__
+
+#include "nrf_svc.h"
+#include "nrf.h"
+#include "nrf_soc.h"
+#include "nrf_error_sdm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup NRF_SDM_DEFINES Defines
+ * @{ */
+#ifdef NRFSOC_DOXYGEN
+/// Declared in nrf_mbr.h
+#define MBR_SIZE 0
+#warning test
+#endif
+
+/** @brief The major version for the SoftDevice binary distributed with this header file. */
+#define SD_MAJOR_VERSION  (5)
+
+/** @brief The minor version for the SoftDevice binary distributed with this header file. */
+#define SD_MINOR_VERSION  (0)
+
+/** @brief The bugfix version for the SoftDevice binary distributed with this header file. */
+#define SD_BUGFIX_VERSION (0)
+
+/** @brief The full version number for the SoftDevice binary this header file was distributed
+ *         with, as a decimal number in the form Mmmmbbb, where:
+ *           - M is major version (one or more digits)
+ *           - mmm is minor version (three digits)
+ *           - bbb is bugfix version (three digits). */
+#define SD_VERSION (SD_MAJOR_VERSION * 1000000 + SD_MINOR_VERSION * 1000 + SD_BUGFIX_VERSION)
+
+/** @brief SoftDevice Manager SVC Base number. */
+#define SDM_SVC_BASE 0x10
+
+/** @brief Invalid info field. Returned when an info field does not exist. */
+#define SDM_INFO_FIELD_INVALID (0)
+
+/** @brief Defines the SoftDevice Information Structure location (address) as an offset from
+the start of the softdevice (without MBR)*/
+#define SOFTDEVICE_INFO_STRUCT_OFFSET (0x2000)
+
+/** @brief Defines the absolute SoftDevice Information Structure location (address) when the
+ *         SoftDevice is installed just above the MBR (the usual case). */
+#define SOFTDEVICE_INFO_STRUCT_ADDRESS (SOFTDEVICE_INFO_STRUCT_OFFSET + MBR_SIZE)
+
+/** @brief Defines the offset for the SoftDevice Information Structure size value relative to the
+ *         SoftDevice base address. The size value is of type uint8_t. */
+#define SD_INFO_STRUCT_SIZE_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET)
+
+/** @brief Defines the offset for the SoftDevice size value relative to the SoftDevice base address.
+ *         The size value is of type uint32_t. */
+#define SD_SIZE_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x08)
+
+/** @brief Defines the offset for FWID value relative to the SoftDevice base address. The FWID value
+ *         is of type uint16_t.  */
+#define SD_FWID_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x0C)
+
+/** @brief Defines the offset for the SoftDevice ID relative to the SoftDevice base address. The ID
+ *         is of type uint32_t. */
+#define SD_ID_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x10)
+
+/** @brief Defines the offset for the SoftDevice version relative to the SoftDevice base address in
+ *         the same format as @ref SD_VERSION, stored as an uint32_t. */
+#define SD_VERSION_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x14)
+
+/** @brief Defines a macro for retreiving the actual SoftDevice Information Structure size value
+ *         from a given base address. Use @ref MBR_SIZE as the argument when the SoftDevice is
+ *         installed just above the MBR (the usual case). */
+#define SD_INFO_STRUCT_SIZE_GET(baseaddr) (*((uint8_t *) ((baseaddr) + SD_INFO_STRUCT_SIZE_OFFSET)))
+
+/** @brief Defines a macro for retreiving the actual SoftDevice size value from a given base
+ *         address. Use @ref MBR_SIZE as the argument when the SoftDevice is installed just above
+ *         the MBR (the usual case). */
+#define SD_SIZE_GET(baseaddr) (*((uint32_t *) ((baseaddr) + SD_SIZE_OFFSET)))
+
+/** @brief Defines a macro for retreiving the actual FWID value from a given base address. Use @ref
+ *         MBR_SIZE as the argument when the SoftDevice is installed just above the MBR (the usual
+ *         case). */
+#define SD_FWID_GET(baseaddr) (*((uint16_t *) ((baseaddr) + SD_FWID_OFFSET)))
+
+/** @brief Defines a macro for retreiving the actual SoftDevice ID from a given base address. Use
+ *         @ref MBR_SIZE as the argument when the SoftDevice is installed just above the MBR (the
+ *         usual case). */
+#define SD_ID_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_ID_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \
+        ? (*((uint32_t *) ((baseaddr) + SD_ID_OFFSET))) : SDM_INFO_FIELD_INVALID)
+
+/** @brief Defines a macro for retreiving the actual FWID value from a given base address. Use @ref
+ *         MBR_SIZE as the argument when the SoftDevice is installed just above the MBR (the usual
+ *         case). */
+#define SD_VERSION_GET(baseaddr) ((SD_INFO_STRUCT_SIZE_GET(baseaddr) > (SD_VERSION_OFFSET - SOFTDEVICE_INFO_STRUCT_OFFSET)) \
+        ? (*((uint32_t *) ((baseaddr) + SD_VERSION_OFFSET))) : SDM_INFO_FIELD_INVALID)
+
+/**@defgroup NRF_FAULT_ID_RANGES Fault ID ranges
+ * @{ */
+#define NRF_FAULT_ID_SD_RANGE_START     0x00000000            /**< SoftDevice ID range start. */
+#define NRF_FAULT_ID_APP_RANGE_START    0x00001000            /**< Application ID range start. */
+/**@} */
+
+/**@defgroup NRF_FAULT_IDS Fault ID types
+ * @{ */
+#define NRF_FAULT_ID_SD_ASSERT    (NRF_FAULT_ID_SD_RANGE_START  + 1)          /**< SoftDevice assertion. The info parameter is reserved for future used. */
+#define NRF_FAULT_ID_APP_MEMACC   (NRF_FAULT_ID_APP_RANGE_START + 1)          /**< Application invalid memory access (nRF52 only). The info parameter will contain 0x00000000, in case of SoftDevice RAM
+                                                                              access violation. In case of SoftDevice peripheral register violation the info parameter will contain the sub-region number of PREGION[0], on whose address range the unallowed
+                                                                              write access caused the memory access fault. */
+/**@} */
+
+/** @} */
+
+/** @addtogroup NRF_SDM_ENUMS Enumerations
+ * @{ */
+
+/**@brief nRF SoftDevice Manager API SVC numbers. */
+enum NRF_SD_SVCS
+{
+  SD_SOFTDEVICE_ENABLE = SDM_SVC_BASE, /**< ::sd_softdevice_enable */
+  SD_SOFTDEVICE_DISABLE,               /**< ::sd_softdevice_disable */
+  SD_SOFTDEVICE_IS_ENABLED,            /**< ::sd_softdevice_is_enabled */
+  SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, /**< ::sd_softdevice_vector_table_base_set */
+  SVC_SDM_LAST                         /**< Placeholder for last SDM SVC */
+};
+
+/** @} */
+
+/** @addtogroup NRF_SDM_DEFINES Defines
+ * @{ */
+
+/**@defgroup NRF_CLOCK_LF_XTAL_ACCURACY Clock accuracy
+ * @{ */
+
+#define NRF_CLOCK_LF_XTAL_ACCURACY_250_PPM (0) /**< Default: 250 ppm */
+#define NRF_CLOCK_LF_XTAL_ACCURACY_500_PPM (1) /**< 500 ppm */
+#define NRF_CLOCK_LF_XTAL_ACCURACY_150_PPM (2) /**< 150 ppm */
+#define NRF_CLOCK_LF_XTAL_ACCURACY_100_PPM (3) /**< 100 ppm */
+#define NRF_CLOCK_LF_XTAL_ACCURACY_75_PPM  (4) /**< 75 ppm */
+#define NRF_CLOCK_LF_XTAL_ACCURACY_50_PPM  (5) /**< 50 ppm */
+#define NRF_CLOCK_LF_XTAL_ACCURACY_30_PPM  (6) /**< 30 ppm */
+#define NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM  (7) /**< 20 ppm */
+
+/** @} */
+
+/**@defgroup NRF_CLOCK_LF_SRC Possible lfclk oscillator sources
+ * @{ */
+
+#define NRF_CLOCK_LF_SRC_RC      (0)                        /**< LFCLK RC oscillator. */
+#define NRF_CLOCK_LF_SRC_XTAL    (1)                        /**< LFCLK crystal oscillator. */
+#define NRF_CLOCK_LF_SRC_SYNTH   (2)                        /**< LFCLK Synthesized from HFCLK. */
+
+/** @} */
+
+/** @} */
+
+/** @addtogroup NRF_SDM_TYPES Types
+ * @{ */
+
+/**@brief Type representing lfclk oscillator source. */
+typedef struct
+{
+  uint8_t source;        /**< LF oscillator clock source, see @ref NRF_CLOCK_LF_SRC. */
+  uint8_t rc_ctiv;      /**< Only for NRF_CLOCK_LF_SRC_RC: Calibration timer interval in 1/4 second
+                              units (nRF51: 1-64, nRF52: 1-32).
+                              @note To avoid excessive clock drift, 0.5 degrees Celsius is the
+                                    maximum temperature change allowed in one calibration timer
+                                    interval. The interval should be selected to ensure this.
+
+                              @note Must be 0 if source is not NRF_CLOCK_LF_SRC_RC.  */
+  uint8_t rc_temp_ctiv; /**<  Only for NRF_CLOCK_LF_SRC_RC: How often (in number of calibration
+                              intervals) the RC oscillator shall be calibrated if the temperature
+                              hasn't changed.
+                                  0: Always calibrate even if the temperature hasn't changed.
+                                  1: Only calibrate if the temperature has changed (nRF51 only).
+                                  2-33: Check the temperature and only calibrate if it has changed,
+                                        however calibration will take place every rc_temp_ctiv
+                                        intervals in any case.
+
+                              @note Must be 0 if source is not NRF_CLOCK_LF_SRC_RC.
+
+                              @note For nRF52, the application must ensure calibration at least once
+                                    every 8 seconds to ensure +/-250ppm clock stability. The
+                                    recommended configuration for NRF_CLOCK_LF_SRC_RC on nRF52 is
+                                    rc_ctiv=16 and rc_temp_ctiv=2. This will ensure calibration at
+                                    least once every 8 seconds and for temperature changes of 0.5
+                                    degrees Celsius every 4 seconds. See the Product Specification
+                                    for the nRF52 device being used for more information.*/
+  uint8_t xtal_accuracy; /**< External crystal clock accuracy used in the LL to compute timing windows.
+
+                              @note For the NRF_CLOCK_LF_SRC_RC clock source this parameter is ignored. */
+} nrf_clock_lf_cfg_t;
+
+/**@brief Fault Handler type.
+ *
+ * When certain unrecoverable errors occur within the application or SoftDevice the fault handler will be called back.
+ * The protocol stack will be in an undefined state when this happens and the only way to recover will be to
+ * perform a reset, using e.g. CMSIS NVIC_SystemReset().
+ * If the application returns from the fault handler the SoftDevice will call NVIC_SystemReset().
+ *
+ * @note This callback is executed in HardFault context, thus SVC functions cannot be called from the fault callback.
+ *
+ * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS.
+ * @param[in] pc The program counter of the instruction that triggered the fault.
+ * @param[in] info Optional additional information regarding the fault. Refer to each Fault identifier for details.
+ *
+ * @note When id is set to NRF_FAULT_ID_APP_MEMACC, pc will contain the address of the instruction being executed at the time when
+ * the fault is detected by the CPU. The CPU program counter may have advanced up to 2 instructions (no branching) after the one that triggered the fault.
+ */
+typedef void (*nrf_fault_handler_t)(uint32_t id, uint32_t pc, uint32_t info);
+
+/** @} */
+
+/** @addtogroup NRF_SDM_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Enables the SoftDevice and by extension the protocol stack.
+ *
+ * @note Some care must be taken if a low frequency clock source is already running when calling this function:
+ *       If the LF clock has a different source then the one currently running, it will be stopped. Then, the new
+ *       clock source will be started.
+ *
+ * @note This function has no effect when returning with an error.
+ *
+ * @post If return code is ::NRF_SUCCESS
+ *       - SoC library and protocol stack APIs are made available.
+ *       - A portion of RAM will be unavailable (see relevant SDS documentation).
+ *       - Some peripherals will be unavailable or available only through the SoC API (see relevant SDS documentation).
+ *       - Interrupts will not arrive from protected peripherals or interrupts.
+ *       - nrf_nvic_ functions must be used instead of CMSIS NVIC_ functions for reliable usage of the SoftDevice.
+ *       - Interrupt latency may be affected by the SoftDevice  (see relevant SDS documentation).
+ *       - Chosen low frequency clock source will be running.
+ *
+ * @param p_clock_lf_cfg Low frequency clock source and accuracy.
+                         If NULL the clock will be configured as an rc source with rc_ctiv = 16 and .rc_temp_ctiv = 2
+                         In the case of XTAL source, the PPM accuracy of the chosen clock source must be greater than or equal to the actual characteristics of your XTAL clock.
+ * @param fault_handler Callback to be invoked in case of fault, cannot be NULL.
+ *
+ * @retval ::NRF_SUCCESS
+ * @retval ::NRF_ERROR_INVALID_ADDR  Invalid or NULL pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE SoftDevice is already enabled, and the clock source and fault handler cannot be updated.
+ * @retval ::NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION SoftDevice interrupt is already enabled, or an enabled interrupt has an illegal priority level.
+ * @retval ::NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN Unknown low frequency clock source selected.
+ */
+SVCALL(SD_SOFTDEVICE_ENABLE, uint32_t, sd_softdevice_enable(nrf_clock_lf_cfg_t const * p_clock_lf_cfg, nrf_fault_handler_t fault_handler));
+
+
+/**@brief Disables the SoftDevice and by extension the protocol stack.
+ *
+ * Idempotent function to disable the SoftDevice.
+ *
+ * @post SoC library and protocol stack APIs are made unavailable.
+ * @post All interrupts that was protected by the SoftDevice will be disabled and initialized to priority 0 (highest).
+ * @post All peripherals used by the SoftDevice will be reset to default values.
+ * @post All of RAM become available.
+ * @post All interrupts are forwarded to the application.
+ * @post LFCLK source chosen in ::sd_softdevice_enable will be left running.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_SOFTDEVICE_DISABLE, uint32_t, sd_softdevice_disable(void));
+
+/**@brief Check if the SoftDevice is enabled.
+ *
+ * @param[out]  p_softdevice_enabled If the SoftDevice is enabled: 1 else 0.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_SOFTDEVICE_IS_ENABLED, uint32_t, sd_softdevice_is_enabled(uint8_t * p_softdevice_enabled));
+
+/**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the SoftDevice
+ *
+ * This function is only intended to be called when a bootloader is enabled.
+ *
+ * @param[in] address The base address of the interrupt vector table for forwarded interrupts.
+
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, uint32_t, sd_softdevice_vector_table_base_set(uint32_t address));
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_SDM_H__
+
+/**
+  @}
+*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_soc.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,908 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */ 
+/**
+ * @defgroup nrf_soc_api SoC Library API
+ * @{
+ * 
+ * @brief APIs for the SoC library.
+ * 
+ */
+
+#ifndef NRF_SOC_H__
+#define NRF_SOC_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf_svc.h"
+#include "nrf.h"
+
+#include "nrf_error_soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@addtogroup NRF_SOC_DEFINES Defines
+ * @{ */
+
+/**@brief The number of the lowest SVC number reserved for the SoC library. */
+#define SOC_SVC_BASE               (0x20)                   /**< Base value for SVCs that are available when the SoftDevice is disabled. */
+#define SOC_SVC_BASE_NOT_AVAILABLE (0x2B)                   /**< Base value for SVCs that are not available when the SoftDevice is disabled. */
+
+/**@brief Guranteed time for application to process radio inactive notification. */
+#define NRF_RADIO_NOTIFICATION_INACTIVE_GUARANTEED_TIME_US  (62)
+
+/**@brief The minimum allowed timeslot extension time. */
+#define NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US (200)
+
+#define SOC_ECB_KEY_LENGTH                (16)                       /**< ECB key length. */
+#define SOC_ECB_CLEARTEXT_LENGTH          (16)                       /**< ECB cleartext length. */
+#define SOC_ECB_CIPHERTEXT_LENGTH         (SOC_ECB_CLEARTEXT_LENGTH) /**< ECB ciphertext length. */
+
+#ifdef NRF51
+#define SD_EVT_IRQn                       (SWI2_IRQn)        /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */
+#define SD_EVT_IRQHandler                 (SWI2_IRQHandler)  /**< SoftDevice Event IRQ handler. Used for both protocol events and SoC events. */
+#define RADIO_NOTIFICATION_IRQn           (SWI1_IRQn)        /**< The radio notification IRQ number. */
+#define RADIO_NOTIFICATION_IRQHandler     (SWI1_IRQHandler)  /**< The radio notification IRQ handler. */
+#endif
+#ifdef NRF52_SERIES
+#define SD_EVT_IRQn                       (SWI2_EGU2_IRQn)        /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */
+#define SD_EVT_IRQHandler                 (SWI2_EGU2_IRQHandler)  /**< SoftDevice Event IRQ handler. Used for both protocol events and SoC events. */
+#define RADIO_NOTIFICATION_IRQn           (SWI1_EGU1_IRQn)        /**< The radio notification IRQ number. */
+#define RADIO_NOTIFICATION_IRQHandler     (SWI1_EGU1_IRQHandler)  /**< The radio notification IRQ handler. */
+#endif
+
+#define NRF_RADIO_LENGTH_MIN_US           (100)               /**< The shortest allowed radio timeslot, in microseconds. */
+#define NRF_RADIO_LENGTH_MAX_US           (100000)            /**< The longest allowed radio timeslot, in microseconds. */
+
+#define NRF_RADIO_DISTANCE_MAX_US         (128000000UL - 1UL) /**< The longest timeslot distance, in microseconds, allowed for the distance parameter (see @ref nrf_radio_request_normal_t) in the request. */
+
+#define NRF_RADIO_EARLIEST_TIMEOUT_MAX_US (128000000UL - 1UL) /**< The longest timeout, in microseconds, allowed when requesting the earliest possible timeslot. */
+
+#define NRF_RADIO_START_JITTER_US         (2)                 /**< The maximum jitter in @ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START relative to the requested start time. */
+
+/**@} */
+
+/**@addtogroup NRF_SOC_ENUMS Enumerations
+ * @{ */
+
+/**@brief The SVC numbers used by the SVC functions in the SoC library. */
+enum NRF_SOC_SVCS
+{
+  SD_PPI_CHANNEL_ENABLE_GET = SOC_SVC_BASE,
+  SD_PPI_CHANNEL_ENABLE_SET,
+  SD_PPI_CHANNEL_ENABLE_CLR,
+  SD_PPI_CHANNEL_ASSIGN,
+  SD_PPI_GROUP_TASK_ENABLE,
+  SD_PPI_GROUP_TASK_DISABLE,
+  SD_PPI_GROUP_ASSIGN,
+  SD_PPI_GROUP_GET,
+  SD_FLASH_PAGE_ERASE,
+  SD_FLASH_WRITE,
+  SD_FLASH_PROTECT,
+  SD_MUTEX_NEW = SOC_SVC_BASE_NOT_AVAILABLE,
+  SD_MUTEX_ACQUIRE,
+  SD_MUTEX_RELEASE,
+  SD_RAND_APPLICATION_POOL_CAPACITY_GET,
+  SD_RAND_APPLICATION_BYTES_AVAILABLE_GET,
+  SD_RAND_APPLICATION_VECTOR_GET,
+  SD_POWER_MODE_SET,
+  SD_POWER_SYSTEM_OFF,
+  SD_POWER_RESET_REASON_GET,
+  SD_POWER_RESET_REASON_CLR,
+  SD_POWER_POF_ENABLE,
+  SD_POWER_POF_THRESHOLD_SET,
+  SD_POWER_RAMON_SET,
+  SD_POWER_RAMON_CLR,
+  SD_POWER_RAMON_GET,
+  SD_POWER_GPREGRET_SET,
+  SD_POWER_GPREGRET_CLR,
+  SD_POWER_GPREGRET_GET,
+  SD_POWER_DCDC_MODE_SET,
+  SD_APP_EVT_WAIT,
+  SD_CLOCK_HFCLK_REQUEST,
+  SD_CLOCK_HFCLK_RELEASE,
+  SD_CLOCK_HFCLK_IS_RUNNING,
+  SD_RADIO_NOTIFICATION_CFG_SET,
+  SD_ECB_BLOCK_ENCRYPT,
+  SD_ECB_BLOCKS_ENCRYPT,
+  SD_RADIO_SESSION_OPEN,
+  SD_RADIO_SESSION_CLOSE,
+  SD_RADIO_REQUEST,
+  SD_EVT_GET,
+  SD_TEMP_GET,
+  SVC_SOC_LAST
+};
+
+/**@brief Possible values of a ::nrf_mutex_t. */
+enum NRF_MUTEX_VALUES
+{
+  NRF_MUTEX_FREE,
+  NRF_MUTEX_TAKEN
+};
+
+/**@brief Power modes. */
+enum NRF_POWER_MODES
+{
+  NRF_POWER_MODE_CONSTLAT,  /**< Constant latency mode. See power management in the reference manual. */
+  NRF_POWER_MODE_LOWPWR     /**< Low power mode. See power management in the reference manual. */
+};
+
+
+/**@brief Power failure thresholds */
+enum NRF_POWER_THRESHOLDS
+{
+  NRF_POWER_THRESHOLD_V21,  /**< 2.1 Volts power failure threshold. */
+  NRF_POWER_THRESHOLD_V23,  /**< 2.3 Volts power failure threshold. */
+  NRF_POWER_THRESHOLD_V25,  /**< 2.5 Volts power failure threshold. */ 
+  NRF_POWER_THRESHOLD_V27   /**< 2.7 Volts power failure threshold. */
+};
+
+
+/**@brief DC/DC converter modes. */
+enum NRF_POWER_DCDC_MODES
+{
+  NRF_POWER_DCDC_DISABLE,          /**< The DCDC is disabled. */
+  NRF_POWER_DCDC_ENABLE            /**< The DCDC is enabled.  */
+};
+
+/**@brief Radio notification distances. */
+enum NRF_RADIO_NOTIFICATION_DISTANCES
+{
+  NRF_RADIO_NOTIFICATION_DISTANCE_NONE = 0, /**< The event does not have a notification. */
+  NRF_RADIO_NOTIFICATION_DISTANCE_800US,    /**< The distance from the active notification to start of radio activity. */
+  NRF_RADIO_NOTIFICATION_DISTANCE_1740US,   /**< The distance from the active notification to start of radio activity. */
+  NRF_RADIO_NOTIFICATION_DISTANCE_2680US,   /**< The distance from the active notification to start of radio activity. */
+  NRF_RADIO_NOTIFICATION_DISTANCE_3620US,   /**< The distance from the active notification to start of radio activity. */
+  NRF_RADIO_NOTIFICATION_DISTANCE_4560US,   /**< The distance from the active notification to start of radio activity. */
+  NRF_RADIO_NOTIFICATION_DISTANCE_5500US    /**< The distance from the active notification to start of radio activity. */
+};
+
+
+/**@brief Radio notification types. */
+enum NRF_RADIO_NOTIFICATION_TYPES
+{
+  NRF_RADIO_NOTIFICATION_TYPE_NONE = 0,        /**< The event does not have a radio notification signal. */
+  NRF_RADIO_NOTIFICATION_TYPE_INT_ON_ACTIVE,   /**< Using interrupt for notification when the radio will be enabled. */
+  NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE, /**< Using interrupt for notification when the radio has been disabled. */
+  NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH,     /**< Using interrupt for notification both when the radio will be enabled and disabled. */
+};
+
+/**@brief The Radio signal callback types. */
+enum NRF_RADIO_CALLBACK_SIGNAL_TYPE
+{
+  NRF_RADIO_CALLBACK_SIGNAL_TYPE_START,             /**< This signal indicates the start of the radio timeslot. */
+  NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0,            /**< This signal indicates the NRF_TIMER0 interrupt. */
+  NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO,             /**< This signal indicates the NRF_RADIO interrupt. */
+  NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_FAILED,     /**< This signal indicates extend action failed. */
+  NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_SUCCEEDED   /**< This signal indicates extend action succeeded. */
+};
+
+/**@brief The actions requested by the signal callback.
+ *
+ *  This code gives the SOC instructions about what action to take when the signal callback has
+ *  returned.
+ */
+enum NRF_RADIO_SIGNAL_CALLBACK_ACTION
+{
+  NRF_RADIO_SIGNAL_CALLBACK_ACTION_NONE,            /**< Return without action. */
+  NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND,          /**< Request an extension of the current timeslot (maximum execution time for this action is when the extension succeeded). */
+  NRF_RADIO_SIGNAL_CALLBACK_ACTION_END,             /**< End the current radio timeslot. */
+  NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END  /**< Request a new radio timeslot and end the current timeslot. */
+};
+
+/**@brief Radio timeslot high frequency clock source configuration. */
+enum NRF_RADIO_HFCLK_CFG
+{
+  NRF_RADIO_HFCLK_CFG_XTAL_GUARANTEED, /**< The SoftDevice will guarantee that the high frequency clock source is the
+                                           external crystal for the whole duration of the timeslot. This should be the
+                                           preferred option for events that use the radio or require high timing accuracy. */
+  NRF_RADIO_HFCLK_CFG_NO_GUARANTEE    /**< This configuration allows for earlier and tighter scheduling of timeslots.
+                                           The RC oscillator may be the clock source in part or for the whole duration of the timeslot.
+                                           The RC oscillator's accuracy must therefore be taken into consideration.
+                                           @note If the application will use the radio peripheral in timeslots with this configuration,
+                                           it must make sure that the crystal is running and stable before starting the radio. */
+};
+
+/**@brief Radio timeslot priorities. */
+enum NRF_RADIO_PRIORITY
+{
+  NRF_RADIO_PRIORITY_HIGH,                          /**< High (equal priority as the normal connection priority of the SoftDevice stack(s)). */
+  NRF_RADIO_PRIORITY_NORMAL,                        /**< Normal (equal priority as the priority of secondary activites of the SoftDevice stack(s)). */
+};
+
+/**@brief Radio timeslot request type. */
+enum NRF_RADIO_REQUEST_TYPE
+{
+  NRF_RADIO_REQ_TYPE_EARLIEST,                      /**< Request radio timeslot as early as possible. This should always be used for the first request in a session. */
+  NRF_RADIO_REQ_TYPE_NORMAL                         /**< Normal radio timeslot request. */
+};
+
+/**@brief SoC Events. */
+enum NRF_SOC_EVTS
+{
+  NRF_EVT_HFCLKSTARTED,                         /**< Event indicating that the HFCLK has started. */
+  NRF_EVT_POWER_FAILURE_WARNING,                /**< Event indicating that a power failure warning has occurred. */
+  NRF_EVT_FLASH_OPERATION_SUCCESS,              /**< Event indicating that the ongoing flash operation has completed successfully. */
+  NRF_EVT_FLASH_OPERATION_ERROR,                /**< Event indicating that the ongoing flash operation has timed out with an error. */
+  NRF_EVT_RADIO_BLOCKED,                        /**< Event indicating that a radio timeslot was blocked. */
+  NRF_EVT_RADIO_CANCELED,                       /**< Event indicating that a radio timeslot was canceled by SoftDevice. */
+  NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN, /**< Event indicating that a radio timeslot signal callback handler return was invalid. */
+  NRF_EVT_RADIO_SESSION_IDLE,                   /**< Event indicating that a radio timeslot session is idle. */
+  NRF_EVT_RADIO_SESSION_CLOSED,                 /**< Event indicating that a radio timeslot session is closed. */
+  NRF_EVT_NUMBER_OF_EVTS
+};
+
+/**@} */
+
+
+/**@addtogroup NRF_SOC_STRUCTURES Structures
+ * @{ */
+
+/**@brief Represents a mutex for use with the nrf_mutex functions.
+ * @note Accessing the value directly is not safe, use the mutex functions!
+ */
+typedef volatile uint8_t nrf_mutex_t;
+
+/**@brief Parameters for a request for a timeslot as early as possible. */
+typedef struct
+{
+  uint8_t       hfclk;                              /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */
+  uint8_t       priority;                           /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */
+  uint32_t      length_us;                          /**< The radio timeslot length (in the range 100 to 100,000] microseconds). */
+  uint32_t      timeout_us;                         /**< Longest acceptable delay until the start of the requested timeslot (up to @ref NRF_RADIO_EARLIEST_TIMEOUT_MAX_US microseconds). */
+} nrf_radio_request_earliest_t;
+
+/**@brief Parameters for a normal radio timeslot request. */
+typedef struct
+{
+  uint8_t       hfclk;                              /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */
+  uint8_t       priority;                           /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */
+  uint32_t      distance_us;                        /**< Distance from the start of the previous radio timeslot (up to @ref NRF_RADIO_DISTANCE_MAX_US microseconds). */
+  uint32_t      length_us;                          /**< The radio timeslot length (in the range [100..100,000] microseconds). */
+} nrf_radio_request_normal_t;
+
+/**@brief Radio timeslot request parameters. */
+typedef struct
+{
+  uint8_t                         request_type;     /**< Type of request, see @ref NRF_RADIO_REQUEST_TYPE. */
+  union
+  {
+    nrf_radio_request_earliest_t  earliest;         /**< Parameters for requesting a radio timeslot as early as possible. */
+    nrf_radio_request_normal_t    normal;           /**< Parameters for requesting a normal radio timeslot. */
+  } params;                                         /**< Parameter union. */
+} nrf_radio_request_t;
+
+/**@brief Return parameters of the radio timeslot signal callback. */
+typedef struct
+{
+  uint8_t               callback_action;            /**< The action requested by the application when returning from the signal callback, see @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION. */
+  union
+  {
+    struct
+    {
+      nrf_radio_request_t * p_next;                 /**< The request parameters for the next radio timeslot. */
+    } request;                                      /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END. */
+    struct
+    {
+      uint32_t              length_us;              /**< Requested extension of the radio timeslot duration (microseconds) (for minimum time see @ref NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US). */
+    } extend;                                       /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND. */
+  } params;                                         /**< Parameter union. */
+} nrf_radio_signal_callback_return_param_t;
+
+/**@brief The radio timeslot signal callback type.
+ *
+ * @note In case of invalid return parameters, the radio timeslot will automatically end
+ *       immediately after returning from the signal callback and the
+ *       @ref NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN event will be sent.
+ * @note The returned struct pointer must remain valid after the signal callback
+ *       function returns. For instance, this means that it must not point to a stack variable.
+ *
+ * @param[in] signal_type Type of signal, see @ref NRF_RADIO_CALLBACK_SIGNAL_TYPE.
+ *
+ * @return Pointer to structure containing action requested by the application.
+ */
+typedef nrf_radio_signal_callback_return_param_t * (*nrf_radio_signal_callback_t) (uint8_t signal_type);
+
+/**@brief AES ECB parameter typedefs */
+typedef uint8_t soc_ecb_key_t[SOC_ECB_KEY_LENGTH];                /**< Encryption key type. */
+typedef uint8_t soc_ecb_cleartext_t[SOC_ECB_CLEARTEXT_LENGTH];    /**< Cleartext data type. */
+typedef uint8_t soc_ecb_ciphertext_t[SOC_ECB_CIPHERTEXT_LENGTH];  /**< Ciphertext data type. */
+
+/**@brief AES ECB data structure */
+typedef struct
+{
+  soc_ecb_key_t        key;            /**< Encryption key. */
+  soc_ecb_cleartext_t  cleartext;      /**< Cleartext data. */
+  soc_ecb_ciphertext_t ciphertext;     /**< Ciphertext data. */
+} nrf_ecb_hal_data_t;
+
+/**@brief AES ECB block. Used to provide multiple blocks in a single call
+          to @ref sd_ecb_blocks_encrypt.*/
+typedef struct
+{
+  soc_ecb_key_t*        p_key;           /**< Pointer to the Encryption key. */
+  soc_ecb_cleartext_t*  p_cleartext;     /**< Pointer to the Cleartext data. */
+  soc_ecb_ciphertext_t* p_ciphertext;    /**< Pointer to the Ciphertext data. */
+} nrf_ecb_hal_data_block_t;
+
+/**@} */
+
+/**@addtogroup NRF_SOC_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Initialize a mutex.
+ *
+ * @param[in] p_mutex Pointer to the mutex to initialize.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_MUTEX_NEW, uint32_t, sd_mutex_new(nrf_mutex_t * p_mutex));
+
+/**@brief Attempt to acquire a mutex.
+ *
+ * @param[in] p_mutex Pointer to the mutex to acquire.
+ *
+ * @retval ::NRF_SUCCESS The mutex was successfully acquired.
+ * @retval ::NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN The mutex could not be acquired.
+ */
+SVCALL(SD_MUTEX_ACQUIRE, uint32_t, sd_mutex_acquire(nrf_mutex_t * p_mutex));
+
+/**@brief Release a mutex.
+ *
+ * @param[in] p_mutex Pointer to the mutex to release.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_MUTEX_RELEASE, uint32_t, sd_mutex_release(nrf_mutex_t * p_mutex));
+
+/**@brief Query the capacity of the application random pool.
+ *
+ * @param[out] p_pool_capacity The capacity of the pool.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_RAND_APPLICATION_POOL_CAPACITY_GET, uint32_t, sd_rand_application_pool_capacity_get(uint8_t * p_pool_capacity));
+
+/**@brief Get number of random bytes available to the application.
+ *
+ * @param[out] p_bytes_available The number of bytes currently available in the pool.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_RAND_APPLICATION_BYTES_AVAILABLE_GET, uint32_t, sd_rand_application_bytes_available_get(uint8_t * p_bytes_available));
+
+/**@brief Get random bytes from the application pool.
+ *
+ * @param[out]  p_buff  Pointer to unit8_t buffer for storing the bytes.
+ * @param[in]   length  Number of bytes to take from pool and place in p_buff.
+ *
+ * @retval ::NRF_SUCCESS The requested bytes were written to p_buff.
+ * @retval ::NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES No bytes were written to the buffer, because there were not enough bytes available.
+*/
+SVCALL(SD_RAND_APPLICATION_VECTOR_GET, uint32_t, sd_rand_application_vector_get(uint8_t * p_buff, uint8_t length));
+
+/**@brief Gets the reset reason register. 
+ *
+ * @param[out]  p_reset_reason  Contents of the NRF_POWER->RESETREAS register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_RESET_REASON_GET, uint32_t, sd_power_reset_reason_get(uint32_t * p_reset_reason));
+
+/**@brief Clears the bits of the reset reason register. 
+ *
+ * @param[in] reset_reason_clr_msk Contains the bits to clear from the reset reason register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_RESET_REASON_CLR, uint32_t, sd_power_reset_reason_clr(uint32_t reset_reason_clr_msk));
+
+/**@brief Sets the power mode when in CPU sleep.
+ *
+ * @param[in] power_mode The power mode to use when in CPU sleep, see @ref NRF_POWER_MODES. @sa sd_app_evt_wait
+ *
+ * @retval ::NRF_SUCCESS The power mode was set.
+ * @retval ::NRF_ERROR_SOC_POWER_MODE_UNKNOWN The power mode was unknown.
+ */
+SVCALL(SD_POWER_MODE_SET, uint32_t, sd_power_mode_set(uint8_t power_mode));
+
+/**@brief Puts the chip in System OFF mode. 
+ *
+ * @retval ::NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN
+ */
+SVCALL(SD_POWER_SYSTEM_OFF, uint32_t, sd_power_system_off(void));
+
+/**@brief Enables or disables the power-fail comparator.
+ *
+ * Enabling this will give a softdevice event (NRF_EVT_POWER_FAILURE_WARNING) when the power failure warning occurs.
+ * The event can be retrieved with sd_evt_get();
+ *
+ * @param[in] pof_enable    True if the power-fail comparator should be enabled, false if it should be disabled.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_POF_ENABLE, uint32_t, sd_power_pof_enable(uint8_t pof_enable));
+
+/**@brief Sets the power-fail threshold value.
+ *
+ * @param[in] threshold The power-fail threshold value to use, see @ref NRF_POWER_THRESHOLDS.
+ *
+ * @retval ::NRF_SUCCESS The power failure threshold was set.
+ * @retval ::NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN The power failure threshold is unknown.
+ */
+SVCALL(SD_POWER_POF_THRESHOLD_SET, uint32_t, sd_power_pof_threshold_set(uint8_t threshold));
+
+/**@brief Sets bits in the NRF_POWER->RAMON register.
+ *
+ * @param[in] ramon Contains the bits needed to be set in the NRF_POWER->RAMON register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_RAMON_SET, uint32_t, sd_power_ramon_set(uint32_t ramon));
+
+/**@brief Clears bits in the NRF_POWER->RAMON register.
+ *
+ * @param ramon Contains the bits needed to be cleared in the NRF_POWER->RAMON register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_RAMON_CLR, uint32_t, sd_power_ramon_clr(uint32_t ramon));
+
+/**@brief Get contents of NRF_POWER->RAMON register, indicates power status of ram blocks.
+ *
+ * @param[out] p_ramon Content of NRF_POWER->RAMON register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_RAMON_GET, uint32_t, sd_power_ramon_get(uint32_t * p_ramon));
+
+/**@brief Set bits in the general purpose retention registers (NRF_POWER->GPREGRET*).
+ *
+ * @param[in] gpregret_id 0 for GPREGRET, 1 for GPREGRET2.
+ * @param[in] gpregret_msk Bits to be set in the GPREGRET register.
+ *
+ * @note nRF51 does only have one general purpose retained register, so gpregret_id must be 0 on nRF51.
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_GPREGRET_SET, uint32_t, sd_power_gpregret_set(uint32_t gpregret_id, uint32_t gpregret_msk));
+
+/**@brief Clear bits in the general purpose retention registers (NRF_POWER->GPREGRET*).
+ *
+ * @param[in] gpregret_id 0 for GPREGRET, 1 for GPREGRET2.
+ * @param[in] gpregret_msk Bits to be clear in the GPREGRET register.
+ *
+ * @note nRF51 does only have one general purpose retained register, so gpregret_id must be 0 on nRF51.
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_GPREGRET_CLR, uint32_t, sd_power_gpregret_clr(uint32_t gpregret_id, uint32_t gpregret_msk));
+
+/**@brief Get contents of the general purpose retention registers (NRF_POWER->GPREGRET*).
+ *
+ * @param[in] gpregret_id 0 for GPREGRET, 1 for GPREGRET2.
+ * @param[out] p_gpregret Contents of the GPREGRET register.
+ *
+ * @note nRF51 does only have one general purpose retained register, so gpregret_id must be 0 on nRF51.
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_GPREGRET_GET, uint32_t, sd_power_gpregret_get(uint32_t gpregret_id, uint32_t *p_gpregret));
+
+/**@brief Sets the DCDC mode.
+ *
+ * Enable or disable the DCDC peripheral.
+ *
+ * @param[in] dcdc_mode The mode of the DCDC, see @ref NRF_POWER_DCDC_MODES.
+ *
+ * @retval ::NRF_SUCCESS
+ * @retval ::NRF_ERROR_INVALID_PARAM The DCDC mode is invalid.
+ */
+SVCALL(SD_POWER_DCDC_MODE_SET, uint32_t, sd_power_dcdc_mode_set(uint8_t dcdc_mode));
+
+/**@brief Request the high frequency crystal oscillator.
+ *
+ * Will start the high frequency crystal oscillator, the startup time of the crystal varies
+ * and the ::sd_clock_hfclk_is_running function can be polled to check if it has started.
+ *
+ * @see sd_clock_hfclk_is_running
+ * @see sd_clock_hfclk_release
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_CLOCK_HFCLK_REQUEST, uint32_t, sd_clock_hfclk_request(void));
+
+/**@brief Releases the high frequency crystal oscillator.
+ *
+ * Will stop the high frequency crystal oscillator, this happens immediately.
+ *
+ * @see sd_clock_hfclk_is_running
+ * @see sd_clock_hfclk_request
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_CLOCK_HFCLK_RELEASE, uint32_t, sd_clock_hfclk_release(void));
+
+/**@brief Checks if the high frequency crystal oscillator is running.
+ *
+ * @see sd_clock_hfclk_request
+ * @see sd_clock_hfclk_release
+ *
+ * @param[out] p_is_running 1 if the external crystal oscillator is running, 0 if not.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_CLOCK_HFCLK_IS_RUNNING, uint32_t, sd_clock_hfclk_is_running(uint32_t * p_is_running));
+
+/**@brief Waits for an application event.
+ * 
+ * An application event is either an application interrupt or a pended interrupt when the
+ * interrupt is disabled. When the interrupt is enabled it will be taken immediately since
+ * this function will wait in thread mode, then the execution will return in the application's
+ * main thread. When an interrupt is disabled and gets pended it will return to the application's 
+ * thread main. The application must ensure that the pended flag is cleared using 
+ * ::sd_nvic_ClearPendingIRQ in order to sleep using this function. This is only necessary for
+ * disabled interrupts, as the interrupt handler will clear the pending flag automatically for
+ * enabled interrupts.
+ *
+ * In order to wake up from disabled interrupts, the SEVONPEND flag has to be set in the Cortex-M0
+ * System Control Register (SCR). @sa CMSIS_SCB
+ *
+ * @note If an application interrupt has happened since the last time sd_app_evt_wait was
+ *       called this function will return immediately and not go to sleep. This is to avoid race
+ *       conditions that can occur when a flag is updated in the interrupt handler and processed
+ *       in the main loop.
+ *
+ * @post An application interrupt has happened or a interrupt pending flag is set.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_APP_EVT_WAIT, uint32_t, sd_app_evt_wait(void));
+
+/**@brief Get PPI channel enable register contents.
+ *
+ * @param[out] p_channel_enable The contents of the PPI CHEN register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_CHANNEL_ENABLE_GET, uint32_t, sd_ppi_channel_enable_get(uint32_t * p_channel_enable));
+
+/**@brief Set PPI channel enable register.
+ *
+ * @param[in] channel_enable_set_msk Mask containing the bits to set in the PPI CHEN register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_CHANNEL_ENABLE_SET, uint32_t, sd_ppi_channel_enable_set(uint32_t channel_enable_set_msk));
+
+/**@brief Clear PPI channel enable register.
+ *
+ * @param[in] channel_enable_clr_msk Mask containing the bits to clear in the PPI CHEN register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_CHANNEL_ENABLE_CLR, uint32_t, sd_ppi_channel_enable_clr(uint32_t channel_enable_clr_msk));
+
+/**@brief Assign endpoints to a PPI channel.
+ *
+ * @param[in] channel_num Number of the PPI channel to assign.
+ * @param[in] evt_endpoint Event endpoint of the PPI channel.
+ * @param[in] task_endpoint Task endpoint of the PPI channel.
+ *
+ * @retval ::NRF_ERROR_SOC_PPI_INVALID_CHANNEL The channel number is invalid.
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_CHANNEL_ASSIGN, uint32_t, sd_ppi_channel_assign(uint8_t channel_num, const volatile void * evt_endpoint, const volatile void * task_endpoint));
+
+/**@brief Task to enable a channel group.
+ *
+ * @param[in] group_num Number of the channel group.
+ *
+ * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_GROUP_TASK_ENABLE, uint32_t, sd_ppi_group_task_enable(uint8_t group_num));
+
+/**@brief Task to disable a channel group.
+ *
+ * @param[in] group_num Number of the PPI group.
+ *
+ * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid.
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_GROUP_TASK_DISABLE, uint32_t, sd_ppi_group_task_disable(uint8_t group_num));
+
+/**@brief Assign PPI channels to a channel group.
+ *
+ * @param[in] group_num Number of the channel group.
+ * @param[in] channel_msk Mask of the channels to assign to the group.
+ *
+ * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid.
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_GROUP_ASSIGN, uint32_t, sd_ppi_group_assign(uint8_t group_num, uint32_t channel_msk));
+
+/**@brief Gets the PPI channels of a channel group.
+ *
+ * @param[in]   group_num Number of the channel group.
+ * @param[out]  p_channel_msk Mask of the channels assigned to the group.
+ *
+ * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid.
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_GROUP_GET, uint32_t, sd_ppi_group_get(uint8_t group_num, uint32_t * p_channel_msk));
+
+/**@brief Configures the Radio Notification signal.
+ *
+ * @note
+ *      - The notification signal latency depends on the interrupt priority settings of SWI used
+ *        for notification signal.
+ *      - To ensure that the radio notification signal behaves in a consistent way, always 
+ *        configure radio notifications when there is no protocol stack or other SoftDevice 
+ *        activity in progress. It is recommended that the radio notification signal is 
+ *        configured directly after the SoftDevice has been enabled.
+ *      - In the period between the ACTIVE signal and the start of the Radio Event, the SoftDevice
+ *        will interrupt the application to do Radio Event preparation.
+ *      - Using the Radio Notification feature may limit the bandwidth, as the SoftDevice may have
+ *        to shorten the connection events to have time for the Radio Notification signals.
+ *
+ * @param[in]  type      Type of notification signal, see @ref NRF_RADIO_NOTIFICATION_TYPES.
+ *                       @ref NRF_RADIO_NOTIFICATION_TYPE_NONE shall be used to turn off radio
+ *                       notification. Using @ref NRF_RADIO_NOTIFICATION_DISTANCE_NONE is
+ *                       recommended (but not required) to be used with
+ *                       @ref NRF_RADIO_NOTIFICATION_TYPE_NONE.
+ *
+ * @param[in]  distance  Distance between the notification signal and start of radio activity, see @ref NRF_RADIO_NOTIFICATION_DISTANCES.
+ *                       This parameter is ignored when @ref NRF_RADIO_NOTIFICATION_TYPE_NONE or 
+ *                       @ref NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE is used. 
+ *
+ * @retval ::NRF_ERROR_INVALID_PARAM The group number is invalid.
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_RADIO_NOTIFICATION_CFG_SET, uint32_t, sd_radio_notification_cfg_set(uint8_t type, uint8_t distance));
+
+/**@brief Encrypts a block according to the specified parameters.
+ *
+ * 128-bit AES encryption.
+ *
+ * @note:
+ *    - The application may set the SEVONPEND bit in the SCR to 1 to make the SoftDevice sleep while
+ *      the ECB is running. The SEVONPEND bit should only be cleared (set to 0) from application
+ *      main or low interrupt level.
+ *
+ * @param[in, out] p_ecb_data Pointer to the ECB parameters' struct (two input
+ *                            parameters and one output parameter).
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_ECB_BLOCK_ENCRYPT, uint32_t, sd_ecb_block_encrypt(nrf_ecb_hal_data_t * p_ecb_data));
+
+/**@brief Encrypts multiple data blocks provided as an array of data block structures.
+ *
+ * @details: Performs 128-bit AES encryption on multiple data blocks
+ *
+ * @note:
+ *    - The application may set the SEVONPEND bit in the SCR to 1 to make the SoftDevice sleep while
+ *      the ECB is running. The SEVONPEND bit should only be cleared (set to 0) from application
+ *      main or low interrupt level.
+ *
+ * @param[in]     block_count     Count of blocks in the p_data_blocks array.
+ * @param[in,out] p_data_blocks   Pointer to the first entry in a contiguous array of
+ *                                @ref nrf_ecb_hal_data_block_t structures.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_ECB_BLOCKS_ENCRYPT, uint32_t, sd_ecb_blocks_encrypt(uint8_t block_count, nrf_ecb_hal_data_block_t * p_data_blocks));
+
+/**@brief Gets any pending events generated by the SoC API.
+ *
+ * The application should keep calling this function to get events, until ::NRF_ERROR_NOT_FOUND is returned.
+ *
+ * @param[out] p_evt_id Set to one of the values in @ref NRF_SOC_EVTS, if any events are pending.
+ *
+ * @retval ::NRF_SUCCESS An event was pending. The event id is written in the p_evt_id parameter.
+ * @retval ::NRF_ERROR_NOT_FOUND No pending events. 
+ */
+SVCALL(SD_EVT_GET, uint32_t, sd_evt_get(uint32_t * p_evt_id));
+
+/**@brief Get the temperature measured on the chip
+ * 
+ * This function will block until the temperature measurement is done.
+ * It takes around 50us from call to return.
+ *
+ * @param[out] p_temp Result of temperature measurement. Die temperature in 0.25 degrees celsius.
+ *
+ * @retval ::NRF_SUCCESS A temperature measurement was done, and the temperature was written to temp
+ */
+SVCALL(SD_TEMP_GET, uint32_t, sd_temp_get(int32_t * p_temp));
+
+/**@brief Flash Write
+*
+* Commands to write a buffer to flash
+*
+* If the SoftDevice is enabled:
+*  This call initiates the flash access command, and its completion will be communicated to the
+*  application with exactly one of the following events:
+*      - @ref NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed.
+*      - @ref NRF_EVT_FLASH_OPERATION_ERROR   - The command could not be started.
+*
+* If the SoftDevice is not enabled no event will be generated, and this call will return @ref NRF_SUCCESS when the 
+ * write has been completed
+*
+* @note
+*      - This call takes control over the radio and the CPU during flash erase and write to make sure that
+*        they will not interfere with the flash access. This means that all interrupts will be blocked
+*        for a predictable time (depending on the NVMC specification in nRF51 Series Reference Manual
+*        and the command parameters).
+*      - The data in the p_src buffer should not be modified before the @ref NRF_EVT_FLASH_OPERATION_SUCCESS
+*        or the @ref NRF_EVT_FLASH_OPERATION_ERROR have been received if the SoftDevice is enabled.
+*
+*
+* @param[in]  p_dst Pointer to start of flash location to be written.
+* @param[in]  p_src Pointer to buffer with data to be written.
+* @param[in]  size  Number of 32-bit words to write. Maximum size is 256 32-bit words for nRF51 and 1024 for nRF52.
+*
+* @retval ::NRF_ERROR_INVALID_ADDR   Tried to write to a non existing flash address, or p_dst or p_src was unaligned.
+* @retval ::NRF_ERROR_BUSY           The previous command has not yet completed.
+* @retval ::NRF_ERROR_INVALID_LENGTH Size was 0, or higher than the maximum allowed size.
+* @retval ::NRF_ERROR_FORBIDDEN      Tried to write to or read from protected location.
+* @retval ::NRF_SUCCESS              The command was accepted.
+*/
+SVCALL(SD_FLASH_WRITE, uint32_t, sd_flash_write(uint32_t * const p_dst, uint32_t const * const p_src, uint32_t size));
+
+
+/**@brief Flash Erase page
+*
+* Commands to erase a flash page
+* If the SoftDevice is enabled:
+*  This call initiates the flash access command, and its completion will be communicated to the
+*  application with exactly one of the following events:
+*      - @ref NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed.
+*      - @ref NRF_EVT_FLASH_OPERATION_ERROR   - The command could not be started.
+*
+* If the SoftDevice is not enabled no event will be generated, and this call will return @ref NRF_SUCCESS when the 
+* erase has been completed
+*
+* @note
+*      - This call takes control over the radio and the CPU during flash erase and write to make sure that
+*        they will not interfere with the flash access. This means that all interrupts will be blocked
+*        for a predictable time (depending on the NVMC specification in nRF51 Series Reference Manual
+*        and the command parameters).
+*
+*
+* @param[in]  page_number Pagenumber of the page to erase
+* @retval ::NRF_ERROR_INTERNAL      If a new session could not be opened due to an internal error.
+* @retval ::NRF_ERROR_INVALID_ADDR  Tried to erase to a non existing flash page.
+* @retval ::NRF_ERROR_BUSY          The previous command has not yet completed.
+* @retval ::NRF_ERROR_FORBIDDEN     Tried to erase a protected page.
+* @retval ::NRF_SUCCESS             The command was accepted.
+*/
+SVCALL(SD_FLASH_PAGE_ERASE, uint32_t, sd_flash_page_erase(uint32_t page_number));
+
+
+/**@brief Flash Protection set
+ *
+ * Commands to set the flash protection configuration registers.
+   On nRF51 this sets the PROTENSETx registers of the MPU peripheral.
+   On nRF52 this sets the CONFIGx registers of the BPROT peripheral.
+ *
+ * @note To read the values read them directly. They are only write-protected.
+ *
+ * @param[in]  block_cfg0 Value to be written to the configuration register.
+ * @param[in]  block_cfg1 Value to be written to the configuration register.
+ * @param[in]  block_cfg2 Value to be written to the configuration register (ignored on nRF51).
+ * @param[in]  block_cfg3 Value to be written to the configuration register (ignored on nRF51).
+ *
+ * @retval ::NRF_ERROR_FORBIDDEN Tried to protect the SoftDevice.
+ * @retval ::NRF_SUCCESS Values successfully written to configuration registers.
+ */
+SVCALL(SD_FLASH_PROTECT, uint32_t, sd_flash_protect(uint32_t block_cfg0, uint32_t block_cfg1, uint32_t block_cfg2, uint32_t block_cfg3));
+
+/**@brief Opens a session for radio timeslot requests.
+ *
+ * @note Only one session can be open at a time.
+ * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START) will be called when the radio timeslot
+ *       starts. From this point the NRF_RADIO and NRF_TIMER0 peripherals can be freely accessed
+ *       by the application.
+ * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0) is called whenever the NRF_TIMER0
+ *       interrupt occurs.
+ * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO) is called whenever the NRF_RADIO
+ *       interrupt occurs.
+ * @note p_radio_signal_callback() will be called at ARM interrupt priority level 0. This
+ *       implies that none of the sd_* API calls can be used from p_radio_signal_callback().
+ *
+ * @param[in] p_radio_signal_callback The signal callback.
+ *
+ * @retval ::NRF_ERROR_INVALID_ADDR p_radio_signal_callback is an invalid function pointer.
+ * @retval ::NRF_ERROR_BUSY If session cannot be opened.
+ * @retval ::NRF_ERROR_INTERNAL If a new session could not be opened due to an internal error.
+ * @retval ::NRF_SUCCESS Otherwise.
+ */
+ SVCALL(SD_RADIO_SESSION_OPEN, uint32_t, sd_radio_session_open(nrf_radio_signal_callback_t p_radio_signal_callback));
+
+/**@brief Closes a session for radio timeslot requests.
+ *
+ * @note Any current radio timeslot will be finished before the session is closed.
+ * @note If a radio timeslot is scheduled when the session is closed, it will be canceled.
+ * @note The application cannot consider the session closed until the @ref NRF_EVT_RADIO_SESSION_CLOSED
+ *       event is received.
+ *
+ * @retval ::NRF_ERROR_FORBIDDEN If session not opened.
+ * @retval ::NRF_ERROR_BUSY If session is currently being closed.
+ * @retval ::NRF_SUCCESS Otherwise.
+ */
+ SVCALL(SD_RADIO_SESSION_CLOSE, uint32_t, sd_radio_session_close(void));
+
+/**@brief Requests a radio timeslot.
+ *
+ * @note The request type is determined by p_request->request_type, and can be one of @ref NRF_RADIO_REQ_TYPE_EARLIEST
+ *       and @ref NRF_RADIO_REQ_TYPE_NORMAL. The first request in a session must always be of type @ref NRF_RADIO_REQ_TYPE_EARLIEST.
+ * @note For a normal request (@ref NRF_RADIO_REQ_TYPE_NORMAL), the start time of a radio timeslot is specified by
+ *       p_request->distance_us and is given relative to the start of the previous timeslot. 
+ * @note A too small p_request->distance_us will lead to a @ref NRF_EVT_RADIO_BLOCKED event.
+ * @note Timeslots scheduled too close will lead to a @ref NRF_EVT_RADIO_BLOCKED event.
+ * @note See the SoftDevice Specification for more on radio timeslot scheduling, distances and lengths.
+ * @note If an opportunity for the first radio timeslot is not found before 100ms after the call to this
+ *       function, it is not scheduled, and instead a @ref NRF_EVT_RADIO_BLOCKED event is sent.
+ *       The application may then try to schedule the first radio timeslot again.
+ * @note Successful requests will result in nrf_radio_signal_callback_t(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START).
+ *       Unsuccessful requests will result in a @ref NRF_EVT_RADIO_BLOCKED event, see @ref NRF_SOC_EVTS.
+ * @note The jitter in the start time of the radio timeslots is +/- @ref NRF_RADIO_START_JITTER_US us.
+ * @note The nrf_radio_signal_callback_t(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START) call has a latency relative to the
+ *       specified radio timeslot start, but this does not affect the actual start time of the timeslot.
+ * @note NRF_TIMER0 is reset at the start of the radio timeslot, and is clocked at 1MHz from the high frequency
+ *       (16 MHz) clock source. If p_request->hfclk_force_xtal is true, the high frequency clock is 
+ *       guaranteed to be clocked from the external crystal.
+ * @note The SoftDevice will neither access the NRF_RADIO peripheral nor the NRF_TIMER0 peripheral
+ *       during the radio timeslot.
+ *
+ * @param[in] p_request Pointer to the request parameters.
+ *
+ * @retval ::NRF_ERROR_FORBIDDEN If session not opened or the session is not IDLE.
+ * @retval ::NRF_ERROR_INVALID_ADDR If the p_request pointer is invalid.
+ * @retval ::NRF_ERROR_INVALID_PARAM If the parameters of p_request are not valid.
+ * @retval ::NRF_SUCCESS Otherwise.
+ */
+ SVCALL(SD_RADIO_REQUEST, uint32_t, sd_radio_request(nrf_radio_request_t * p_request ));
+
+/**@} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_SOC_H__
+
+/**@} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_svc.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,90 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_SVC__
+#define NRF_SVC__
+
+#include "stdint.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef SVCALL_AS_NORMAL_FUNCTION
+#define SVCALL(number, return_type, signature) return_type signature
+#else
+
+#ifndef SVCALL
+#if defined (__CC_ARM)
+#define SVCALL(number, return_type, signature) return_type __svc(number) signature
+#elif defined (__GNUC__)
+#ifdef __cplusplus
+#define GCC_CAST_CPP (uint16_t)
+#else
+#define GCC_CAST_CPP
+#endif
+#define SVCALL(number, return_type, signature)          \
+  _Pragma("GCC diagnostic push")                        \
+  _Pragma("GCC diagnostic ignored \"-Wreturn-type\"")   \
+  __attribute__((naked))                                \
+  __attribute__((unused))                               \
+  static return_type signature                          \
+  {                                                     \
+    __asm(                                              \
+        "svc %0\n"                                      \
+        "bx r14" : : "I" (GCC_CAST_CPP number) : "r0"   \
+    );                                                  \
+  }                                                     \
+  _Pragma("GCC diagnostic pop")
+
+#elif defined (__ICCARM__)
+#define PRAGMA(x) _Pragma(#x)
+#define SVCALL(number, return_type, signature)          \
+PRAGMA(swi_number = (number))                           \
+ __swi return_type signature;
+#else
+#define SVCALL(number, return_type, signature) return_type signature
+#endif
+#endif  // SVCALL
+
+#endif  // SVCALL_AS_NORMAL_FUNCTION
+
+#ifdef __cplusplus
+}
+#endif
+#endif  // NRF_SVC__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/hex/s140_nrf52840_5.0.0-1.alpha_softdevice.hex	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,8202 @@
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+:1000000000040020E508000079050000C508000094
+:10001000830500008D05000097050000000000002A
+:1000200000000000000000000000000009090000BE
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--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/analogin_api.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,123 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "mbed_assert.h"
+#include "analogin_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "app_util_platform.h"
+#include "nrf_drv_saadc.h"
+
+#ifdef DEVICE_ANALOGIN
+
+#define ADC_12BIT_RANGE 0xFFF
+#define ADC_RANGE       ADC_12BIT_RANGE
+
+__STATIC_INLINE nrf_saadc_input_t nrf_drv_saadc_gpio_to_ain(uint32_t pin);
+
+
+static void analog_in_event_handler(nrf_drv_saadc_evt_t const *p_event)// type of nrf_drv_saadc_event_handler_t 
+{
+    (void) p_event;
+}
+
+static const nrf_drv_saadc_config_t saadc_config = 
+{
+    .resolution         = NRF_SAADC_RESOLUTION_12BIT,
+    .oversample         = NRF_SAADC_OVERSAMPLE_DISABLED,
+    .interrupt_priority = SAADC_CONFIG_IRQ_PRIORITY
+};
+
+void SAADC_IRQHandler(void);
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    ret_code_t ret_code;
+    
+    NVIC_SetVector(SAADC_IRQn, (uint32_t)SAADC_IRQHandler);
+    
+    ret_code = nrf_drv_saadc_init(&saadc_config, analog_in_event_handler);
+    MBED_ASSERT(((ret_code == NRF_SUCCESS) || (ret_code == NRF_ERROR_INVALID_STATE))); //NRF_ERROR_INVALID_STATE expected for multiple channels used.
+    
+    uint8_t saadcIn = nrf_drv_saadc_gpio_to_ain(pin);
+    MBED_ASSERT(saadcIn != NRF_SAADC_INPUT_DISABLED);
+    
+    obj->adc     = ADC0_0; // only one instance of ADC in nRF52 SoC
+    obj->adc_pin = saadcIn  - 1;
+    
+    nrf_saadc_channel_config_t channel_config =
+            NRF_DRV_SAADC_DEFAULT_CHANNEL_CONFIG_SE(saadcIn); //Single ended, negative input to ADC shorted to GND.
+    
+    ret_code = nrf_drv_saadc_channel_init(obj->adc_pin, &channel_config);
+    MBED_ASSERT(ret_code == NRF_SUCCESS);
+}
+
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+    int16_t    adc_value;
+    ret_code_t ret_code;
+    
+    ret_code = nrf_drv_saadc_sample_convert(obj->adc_pin, &adc_value);
+    MBED_ASSERT(ret_code == NRF_SUCCESS);
+    
+    if (adc_value < 0)
+    {
+        // Even in the single ended mode measured value can be {-0}. Saturation for avoid casting to a big integer.
+        return 0;
+    }
+    else
+    {
+        return (uint16_t) adc_value;
+    }
+}
+
+float analogin_read(analogin_t *obj)
+{
+    uint16_t value = analogin_read_u16(obj);
+    return (float)value * (1.0f / (float)ADC_RANGE);
+}
+
+
+/**
+ * @brief Function for converting a GPIO pin number to an analog input pin number used in the channel
+ *        configuration.
+ *
+ * @param[in]  pin GPIO pin.
+ *
+ * @return     Value representing an analog input pin. The function returns @ref NRF_SAADC_INPUT_DISABLED
+ *             if the specified pin is not an analog input.
+ */
+__STATIC_INLINE nrf_saadc_input_t nrf_drv_saadc_gpio_to_ain(uint32_t pin)
+{
+    // AIN0 - AIN3
+    if (pin >= 2 && pin <= 5)
+    {
+        //0 means "not connected", hence this "+ 1"
+        return (nrf_saadc_input_t)(pin - 2 + 1);
+    }
+    // AIN4 - AIN7
+    else if (pin >= 28 && pin <= 31)
+    {
+        return (nrf_saadc_input_t)(pin - 24 + 1);
+    }
+    else
+    {
+        return NRF_SAADC_INPUT_DISABLED;
+    }
+}
+
+#endif // DEVICE_ANALOGIN

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/common_rtc.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef COMMON_RTC_H
+#define COMMON_RTC_H
+
+#include "nrf_rtc.h"
+
+#define RTC_COUNTER_BITS        24u
+
+// Instance 0 is reserved for SoftDevice.
+// Instance 1 is used as a common one for us_ticker, lp_ticker and (in case
+// of NRF51) as an alternative tick source for RTOS.
+// ["us_ticker.c" uses hard coded addresses of the 'NRF_RTC1->EVENT_COMPARE[1]'
+//  register in inline assembly implementations of COMMON_RTC_IRQ_HANDLER,
+//  please remember to update those in case of doing changes here]
+#define COMMON_RTC_INSTANCE     NRF_RTC1
+#define COMMON_RTC_IRQ_HANDLER  RTC1_IRQHandler
+#define US_TICKER_CC_CHANNEL    0
+#define OS_TICK_CC_CHANNEL      1
+#define LP_TICKER_CC_CHANNEL    2
+
+#define COMMON_RTC_EVENT_COMPARE(channel) \
+    CONCAT_2(NRF_RTC_EVENT_COMPARE_, channel)
+#define COMMON_RTC_INT_COMPARE_MASK(channel) \
+    CONCAT_3(NRF_RTC_INT_COMPARE, channel, _MASK)
+
+#define US_TICKER_EVENT     COMMON_RTC_EVENT_COMPARE(US_TICKER_CC_CHANNEL)
+#define US_TICKER_INT_MASK  COMMON_RTC_INT_COMPARE_MASK(US_TICKER_CC_CHANNEL)
+#define OS_TICK_EVENT       COMMON_RTC_EVENT_COMPARE(OS_TICK_CC_CHANNEL)
+#define OS_TICK_INT_MASK    COMMON_RTC_INT_COMPARE_MASK(OS_TICK_CC_CHANNEL)
+#define LP_TICKER_EVENT     COMMON_RTC_EVENT_COMPARE(LP_TICKER_CC_CHANNEL)
+#define LP_TICKER_INT_MASK  COMMON_RTC_INT_COMPARE_MASK(LP_TICKER_CC_CHANNEL)
+
+extern bool              m_common_rtc_enabled;
+extern uint32_t volatile m_common_rtc_overflows;
+
+void     common_rtc_init(void);
+uint32_t common_rtc_32bit_ticks_get(void);
+uint64_t common_rtc_64bit_us_get(void);
+void     common_rtc_set_interrupt(uint32_t us_timestamp, uint32_t cc_channel,
+                                  uint32_t int_mask);
+
+#endif // COMMON_RTC_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/gpio_api.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,283 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "gpio_api.h"
+#include "gpio_irq_api.h"
+#include "pinmap.h"
+#include "nrf_drv_gpiote.h"
+
+#if defined(TARGET_MCU_NRF51822)
+    #define GPIO_PIN_COUNT 31
+#elif defined(TARGET_MCU_NRF52832)
+    #define GPIO_PIN_COUNT 32
+#elif defined(TARGET_MCU_NRF52840)
+    #define GPIO_PIN_COUNT 48
+#else
+    #error not recognized gpio count for mcu
+#endif
+
+typedef struct
+{
+    bool         used_as_gpio : 1;
+    PinDirection direction    : 1;
+    bool         init_high    : 1;
+    PinMode      pull         : 2;
+    bool         used_as_irq  : 1;
+    bool         irq_fall     : 1;
+    bool         irq_rise     : 1;
+} gpio_cfg_t;
+
+#if GPIO_PIN_COUNT > 32
+    typedef uint64_t gpio_mask_t;
+#else
+    typedef uint32_t gpio_mask_t;
+#endif
+
+static gpio_mask_t m_gpio_initialized;
+static gpio_cfg_t  m_gpio_cfg[GPIO_PIN_COUNT];
+
+
+/***********
+  GPIO IRQ
+***********/
+
+static gpio_irq_handler m_irq_handler;
+static uint32_t         m_channel_ids[GPIO_PIN_COUNT] = {0};
+static gpio_mask_t      m_gpio_irq_enabled;
+
+
+static void gpiote_irq_handler(nrf_drv_gpiote_pin_t pin, nrf_gpiote_polarity_t action)
+{
+    nrf_gpio_pin_sense_t sense =  nrf_gpio_pin_sense_get(pin);
+    gpio_irq_event event = (sense == NRF_GPIO_PIN_SENSE_LOW) ? IRQ_RISE : IRQ_FALL;
+
+    if (m_gpio_irq_enabled & ((gpio_mask_t)1 << pin))
+    {
+        if (((event == IRQ_RISE) && m_gpio_cfg[pin].irq_rise)
+            || ((event == IRQ_FALL) && m_gpio_cfg[pin].irq_fall))
+        {
+            m_irq_handler(m_channel_ids[pin], event);
+        }
+    }
+}
+
+void GPIOTE_IRQHandler(void);// exported from nrf_drv_gpiote.c
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+    obj->pin = pin;
+    if (pin == (PinName)NC)
+    {
+        return;
+    }
+    MBED_ASSERT((uint32_t)pin < GPIO_PIN_COUNT);
+    
+    NVIC_SetVector(GPIOTE_IRQn, (uint32_t) GPIOTE_IRQHandler);
+    
+    (void) nrf_drv_gpiote_init();
+
+    m_gpio_cfg[obj->pin].used_as_gpio = true;
+}
+
+
+int gpio_read(gpio_t *obj)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    if (m_gpio_cfg[obj->pin].direction == PIN_OUTPUT)
+    {
+        return (nrf_gpio_pin_out_read(obj->pin) ? 1 : 0);
+    }
+    else
+    {
+        return nrf_gpio_pin_read(obj->pin);
+    }
+}
+
+static void gpiote_pin_uninit(uint8_t pin)
+{
+    if (m_gpio_initialized & ((gpio_mask_t)1 << pin))
+    {
+        if ((m_gpio_cfg[pin].direction == PIN_OUTPUT) && (!m_gpio_cfg[pin].used_as_irq))
+        {
+            nrf_drv_gpiote_out_uninit(pin);
+        }
+        else
+        {
+            nrf_drv_gpiote_in_uninit(pin);
+        }
+    }
+}
+
+static void gpio_apply_config(uint8_t pin)
+{
+    if (m_gpio_cfg[pin].used_as_gpio || m_gpio_cfg[pin].used_as_irq)
+    {
+        if ((m_gpio_cfg[pin].direction == PIN_INPUT)
+            || (m_gpio_cfg[pin].used_as_irq))
+        {
+            //Configure as input.
+            nrf_drv_gpiote_in_config_t cfg;
+
+            cfg.hi_accuracy = false;
+            cfg.is_watcher = false;
+            cfg.sense = NRF_GPIOTE_POLARITY_TOGGLE;
+            if (m_gpio_cfg[pin].used_as_irq)
+            {
+                cfg.pull = NRF_GPIO_PIN_PULLUP;
+                nrf_drv_gpiote_in_init(pin, &cfg, gpiote_irq_handler);
+                if ((m_gpio_irq_enabled & ((gpio_mask_t)1 << pin))
+                    && (m_gpio_cfg[pin].irq_rise || m_gpio_cfg[pin].irq_fall))
+                {
+                    nrf_drv_gpiote_in_event_enable(pin, true);
+                }
+            }
+            else
+            {
+                switch (m_gpio_cfg[pin].pull)
+                {
+                    case PullUp:
+                        cfg.pull = NRF_GPIO_PIN_PULLUP;
+                    break;
+                    case PullDown:
+                        cfg.pull = NRF_GPIO_PIN_PULLDOWN;
+                    break;
+                    default:
+                        cfg.pull = NRF_GPIO_PIN_NOPULL;
+                    break;
+                }
+                nrf_drv_gpiote_in_init(pin, &cfg, NULL);
+            }
+        }
+        else
+        {
+            // Configure as output.
+            nrf_drv_gpiote_out_config_t cfg = GPIOTE_CONFIG_OUT_SIMPLE(m_gpio_cfg[pin].init_high);
+            nrf_drv_gpiote_out_init(pin, &cfg);
+        }
+        m_gpio_initialized |= ((gpio_mask_t)1 << pin);
+    }
+    else
+    {
+        m_gpio_initialized &= ~((gpio_mask_t)1 << pin);
+    }
+}
+
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    
+    gpiote_pin_uninit(obj->pin); // try to uninitialize gpio before a change.
+    
+    m_gpio_cfg[obj->pin].pull = mode;
+    gpio_apply_config(obj->pin);
+}
+
+
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    
+    gpiote_pin_uninit(obj->pin); // try to uninitialize gpio before a change.
+    
+    m_gpio_cfg[obj->pin].direction = direction;
+    gpio_apply_config(obj->pin);
+}
+
+
+/***********
+  GPIO IRQ
+***********/
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+    if (pin == NC)
+    {
+        return -1;
+    }
+    MBED_ASSERT((uint32_t)pin < GPIO_PIN_COUNT);
+    (void) nrf_drv_gpiote_init();
+
+    gpiote_pin_uninit(pin); // try to uninitialize gpio before a change.
+    
+    m_gpio_cfg[pin].used_as_irq = true;
+    m_channel_ids[pin] = id;
+    obj->ch            = pin;
+    m_irq_handler      = handler;
+    m_channel_ids[pin] = id;
+
+    gpio_apply_config(pin);
+    return 1;
+}
+
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+    nrf_drv_gpiote_in_uninit(obj->ch);
+    m_gpio_cfg[obj->ch].used_as_irq = false;
+    m_channel_ids[obj->ch] = 0;
+
+    gpio_apply_config(obj->ch);
+}
+
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+    gpio_cfg_t* cfg = &m_gpio_cfg[obj->ch];
+    bool irq_enabled_before =
+        (m_gpio_irq_enabled & ((gpio_mask_t)1 << obj->ch)) &&
+        (cfg->irq_rise || cfg->irq_fall);
+
+    if (event == IRQ_RISE)
+    {
+        cfg->irq_rise = enable ? true : false;
+    }
+    else if (event == IRQ_FALL)
+    {
+        cfg->irq_fall = enable ? true : false;
+    }
+
+    bool irq_enabled_after = cfg->irq_rise || cfg->irq_fall;
+
+    if (irq_enabled_before != irq_enabled_after)
+    {
+        if (irq_enabled_after)
+        {
+            gpio_irq_enable(obj);
+        }
+        else
+        {
+            gpio_irq_disable(obj);
+        }
+    }
+}
+
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+    m_gpio_irq_enabled |= ((gpio_mask_t)1 << obj->ch);
+    if (m_gpio_cfg[obj->ch].irq_rise || m_gpio_cfg[obj->ch].irq_fall)
+    {
+        nrf_drv_gpiote_in_event_enable(obj->ch, true);
+    }
+}
+
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+    m_gpio_irq_enabled &= ~((gpio_mask_t)1 << obj->ch);
+    nrf_drv_gpiote_in_event_disable(obj->ch);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/gpio_object.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+
+#include "nrf_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct
+{
+    PinName  pin;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    if (value)
+    {
+        nrf_gpio_pin_set(obj->pin);
+    }
+    else
+    {
+        nrf_gpio_pin_clear(obj->pin);
+    }
+}
+
+static inline int gpio_is_connected(const gpio_t *obj)
+{
+    return obj->pin != (PinName)NC;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/i2c_api.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,784 @@
+/* 
+ * Copyright (c) 2017 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "i2c_api.h"
+
+#if DEVICE_I2C
+
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "nrf_twi.h"
+#include "nrf_drv_common.h"
+#include "sdk_config.h"
+#include "app_util_platform.h"
+#include "nrf_gpio.h"
+#include "nrf_delay.h"
+
+// An arbitrary value used as the counter in loops waiting for given event
+// (e.g. STOPPED), needed to avoid infinite loops (and not involve any timers
+// or tickers).
+#define TIMEOUT_VALUE  1000
+
+#if DEVICE_I2C_ASYNCH
+    #define TWI_IDX(obj)    ((obj)->i2c.twi_idx)
+#else
+    #define TWI_IDX(obj)    ((obj)->twi_idx)
+#endif
+#define TWI_INFO(obj)   (&m_twi_info[TWI_IDX(obj)])
+
+#define TWI0_INSTANCE_INDEX 0
+#define TWI1_INSTANCE_INDEX TWI0_INSTANCE_INDEX+TWI0_ENABLED
+
+typedef struct {
+    bool                initialized;
+    uint32_t            pselsda;
+    uint32_t            pselscl;
+    nrf_twi_frequency_t frequency;
+    bool                start_twi;
+
+#if DEVICE_I2C_ASYNCH
+    volatile bool   active;
+    uint8_t const  *tx;
+    size_t          tx_length;
+    uint8_t        *rx;
+    size_t          rx_length;
+    bool            stop;
+
+    volatile uint32_t   events;
+    void              (*handler)(void);
+    uint32_t            evt_mask;
+#endif // DEVICE_I2C_ASYNCH
+} twi_info_t;
+static twi_info_t m_twi_info[TWI_COUNT];
+
+static NRF_TWI_Type * const m_twi_instances[TWI_COUNT] = {
+#if TWI0_ENABLED
+    NRF_TWI0,
+#endif
+#if TWI1_ENABLED
+    NRF_TWI1,
+#endif
+};
+
+void SPI0_TWI0_IRQHandler(void);
+void SPI1_TWI1_IRQHandler(void);
+
+static const peripheral_handler_desc_t twi_handlers[TWI_COUNT] =
+{
+#if TWI0_ENABLED
+    {
+        SPI0_TWI0_IRQn,
+        (uint32_t) SPI0_TWI0_IRQHandler
+    },
+#endif
+#if TWI1_ENABLED
+    {
+        SPI1_TWI1_IRQn,
+        (uint32_t) SPI1_TWI1_IRQHandler
+    }
+#endif
+};
+#ifdef NRF51
+    #define TWI_IRQ_PRIORITY  APP_IRQ_PRIORITY_LOW
+#elif defined(NRF52) || defined(NRF52840_XXAA)
+    #define TWI_IRQ_PRIORITY  APP_IRQ_PRIORITY_LOWEST
+#endif
+
+
+#if DEVICE_I2C_ASYNCH
+static void start_asynch_rx(twi_info_t *twi_info, NRF_TWI_Type *twi)
+{
+    if (twi_info->rx_length == 1 && twi_info->stop)
+    {
+        nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_STOP_MASK);
+    }
+    else
+    {
+        nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_SUSPEND_MASK);
+    }
+    nrf_twi_task_trigger(twi, NRF_TWI_TASK_STARTRX);
+}
+
+static void twi_irq_handler(uint8_t instance_idx)
+{
+    twi_info_t *twi_info = &m_twi_info[instance_idx];
+
+    NRF_TWI_Type *twi = m_twi_instances[instance_idx];
+    if (nrf_twi_event_check(twi, NRF_TWI_EVENT_ERROR))
+    {
+        nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR);
+
+        // In case of an error, force STOP.
+        // The current transfer may be suspended (if it is RX), so it must be
+        // resumed before the STOP task is triggered.
+        nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME);
+        nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP);
+
+        uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(twi);
+        twi_info->events |= I2C_EVENT_ERROR;
+        if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK)
+        {
+            twi_info->events |= I2C_EVENT_ERROR_NO_SLAVE;
+        }
+        if (errorsrc & NRF_TWI_ERROR_DATA_NACK)
+        {
+            twi_info->events |= I2C_EVENT_TRANSFER_EARLY_NACK;
+        }
+    }
+
+    bool finished = false;
+
+    if (nrf_twi_event_check(twi, NRF_TWI_EVENT_TXDSENT))
+    {
+        nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT);
+
+        MBED_ASSERT(twi_info->tx_length > 0);
+        --(twi_info->tx_length);
+        // Send next byte if there is still something to be sent.
+        if (twi_info->tx_length > 0)
+        {
+            nrf_twi_txd_set(twi, *(twi_info->tx));
+            ++(twi_info->tx);
+            // It TX is done, start RX if requested.
+        }
+        else if (twi_info->rx_length > 0)
+        {
+            start_asynch_rx(twi_info, twi);
+            // If there is nothing more to do, finalize the transfer.
+        }
+        else
+        {
+            if (twi_info->stop)
+            {
+                nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP);
+            }
+            else
+            {
+                nrf_twi_task_trigger(twi, NRF_TWI_TASK_SUSPEND);
+                finished = true;
+            }
+            twi_info->events |= I2C_EVENT_TRANSFER_COMPLETE;
+        }
+    }
+
+    if (nrf_twi_event_check(twi, NRF_TWI_EVENT_RXDREADY))
+    {
+        nrf_twi_event_clear(twi, NRF_TWI_EVENT_RXDREADY);
+
+        MBED_ASSERT(twi_info->rx_length > 0);
+        *(twi_info->rx) = nrf_twi_rxd_get(twi);
+        ++(twi_info->rx);
+        --(twi_info->rx_length);
+
+        if (twi_info->rx_length > 0)
+        {
+            // If more bytes should be received, resume the transfer
+            // (in case the stop condition should be generated after the next
+            // byte, change the shortcuts configuration first).
+            if (twi_info->rx_length == 1 && twi_info->stop)
+            {
+                nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_STOP_MASK);
+            }
+            nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME);
+        }
+        else
+        {
+            // If all requested bytes were received, finalize the transfer.
+            finished = true;
+            twi_info->events |= I2C_EVENT_TRANSFER_COMPLETE;
+        }
+    }
+
+    if (finished ||
+        nrf_twi_event_check(twi, NRF_TWI_EVENT_STOPPED) ||
+        (nrf_twi_int_enable_check(twi, NRF_TWI_INT_SUSPENDED_MASK) &&
+         nrf_twi_event_check(twi, NRF_TWI_EVENT_SUSPENDED)))
+    {
+        // There is no need to clear the STOPPED and SUSPENDED events here,
+        // they will no longer generate the interrupt - see below.
+
+        nrf_twi_shorts_set(twi, 0);
+        // Disable all interrupt sources.
+        nrf_twi_int_disable(twi, UINT32_MAX);
+        twi_info->active = false;
+
+        if (twi_info->handler)
+        {
+            twi_info->handler();
+        }
+    }
+}
+
+#if TWI0_ENABLED
+static void irq_handler_twi0(void)
+{
+    twi_irq_handler(TWI0_INSTANCE_INDEX);
+}
+#endif
+#if TWI1_ENABLED
+static void irq_handler_twi1(void)
+{
+    twi_irq_handler(TWI1_INSTANCE_INDEX);
+}
+#endif
+static nrf_drv_irq_handler_t const m_twi_irq_handlers[TWI_COUNT] =
+{
+#if TWI0_ENABLED
+    irq_handler_twi0,
+#endif
+#if TWI1_ENABLED
+    irq_handler_twi1,
+#endif
+};
+#endif // DEVICE_I2C_ASYNCH
+
+
+static void configure_twi_pin(uint32_t pin, nrf_gpio_pin_dir_t dir)
+{
+    nrf_gpio_cfg(pin,
+        dir,
+        NRF_GPIO_PIN_INPUT_CONNECT,
+        NRF_GPIO_PIN_PULLUP,
+        NRF_GPIO_PIN_S0D1,
+        NRF_GPIO_PIN_NOSENSE);
+}
+
+static void twi_clear_bus(twi_info_t *twi_info)
+{
+    // Try to set SDA high, and check if no slave tries to drive it low.
+    nrf_gpio_pin_set(twi_info->pselsda);
+    configure_twi_pin(twi_info->pselsda, NRF_GPIO_PIN_DIR_OUTPUT);
+    // In case SDA is low, make up to 9 cycles on SCL line to help the slave
+    // that pulls SDA low release it.
+    if (!nrf_gpio_pin_read(twi_info->pselsda))
+    {
+        nrf_gpio_pin_set(twi_info->pselscl);
+        configure_twi_pin(twi_info->pselscl, NRF_GPIO_PIN_DIR_OUTPUT);
+        nrf_delay_us(4);
+
+        for (int i = 0; i < 9; i++)
+        {
+            if (nrf_gpio_pin_read(twi_info->pselsda))
+            {
+                break;
+            }
+            nrf_gpio_pin_clear(twi_info->pselscl);
+            nrf_delay_us(4);
+            nrf_gpio_pin_set(twi_info->pselscl);
+            nrf_delay_us(4);
+        }
+
+        // Finally, generate STOP condition to put the bus into initial state.
+        nrf_gpio_pin_clear(twi_info->pselsda);
+        nrf_delay_us(4);
+        nrf_gpio_pin_set(twi_info->pselsda);
+    }
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+    int i;
+
+    for (i = 0; i < TWI_COUNT; ++i)
+    {
+        if (m_twi_info[i].initialized &&
+            m_twi_info[i].pselsda == (uint32_t)sda &&
+            m_twi_info[i].pselscl == (uint32_t)scl)
+        {
+            TWI_IDX(obj) = i;
+            TWI_INFO(obj)->frequency = NRF_TWI_FREQ_100K;
+            i2c_reset(obj);
+            return;
+        }
+    }
+
+    for (i = 0; i < TWI_COUNT; ++i)
+    {
+        if (!m_twi_info[i].initialized)
+        {
+            TWI_IDX(obj) = i;
+
+            twi_info_t *twi_info = TWI_INFO(obj);
+            twi_info->initialized = true;
+            twi_info->pselsda     = (uint32_t)sda;
+            twi_info->pselscl     = (uint32_t)scl;
+            twi_info->frequency   = NRF_TWI_FREQ_100K;
+            twi_info->start_twi   = false;
+#if DEVICE_I2C_ASYNCH
+            twi_info->active      = false;
+#endif
+
+            twi_clear_bus(twi_info);
+
+            configure_twi_pin(twi_info->pselsda, NRF_GPIO_PIN_DIR_INPUT);
+            configure_twi_pin(twi_info->pselscl, NRF_GPIO_PIN_DIR_INPUT);
+
+            i2c_reset(obj);
+
+#if DEVICE_I2C_ASYNCH
+            nrf_drv_common_per_res_acquire(m_twi_instances[i],
+                m_twi_irq_handlers[i]);
+            NVIC_SetVector(twi_handlers[i].IRQn, twi_handlers[i].vector);
+            nrf_drv_common_irq_enable(twi_handlers[i].IRQn, TWI_IRQ_PRIORITY);
+#endif
+
+            return;
+        }
+    }
+
+    error("No available I2C peripheral\r\n");
+}
+
+void i2c_reset(i2c_t *obj)
+{
+    twi_info_t *twi_info = TWI_INFO(obj);
+    NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)];
+
+    nrf_twi_disable(twi);
+    nrf_twi_pins_set(twi, twi_info->pselscl, twi_info->pselsda);
+    nrf_twi_frequency_set(twi, twi_info->frequency);
+    nrf_twi_enable(twi);
+}
+
+int i2c_start(i2c_t *obj)
+{
+    twi_info_t *twi_info = TWI_INFO(obj);
+#if DEVICE_I2C_ASYNCH
+    if (twi_info->active)
+    {
+        return I2C_ERROR_BUS_BUSY;
+    }
+#endif
+    twi_info->start_twi = true;
+
+    return 0;
+}
+
+int i2c_stop(i2c_t *obj)
+{
+    NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)];
+
+    // The current transfer may be suspended (if it is RX), so it must be
+    // resumed before the STOP task is triggered.
+    nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME);
+    nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP);
+    uint32_t remaining_time = TIMEOUT_VALUE;
+
+    do
+    {
+        if (nrf_twi_event_check(twi, NRF_TWI_EVENT_STOPPED))
+        {
+            return 0;
+        }
+    }
+    while (--remaining_time);
+
+    return 1;
+}
+
+void i2c_frequency(i2c_t *obj, int hz)
+{
+    twi_info_t *twi_info = TWI_INFO(obj);
+    NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)];
+
+    if (hz < 250000)
+    {
+        twi_info->frequency = NRF_TWI_FREQ_100K;
+    }
+    else if (hz < 400000)
+    {
+        twi_info->frequency = NRF_TWI_FREQ_250K;
+    }
+    else
+    {
+        twi_info->frequency = NRF_TWI_FREQ_400K;
+    }
+    nrf_twi_frequency_set(twi, twi_info->frequency);
+}
+
+static uint8_t twi_address(int i2c_address)
+{
+    // The TWI peripheral requires 7-bit slave address (without R/W bit).
+    return (i2c_address >> 1);
+}
+
+static void start_twi_read(NRF_TWI_Type *twi, int address)
+{
+    nrf_twi_event_clear(twi, NRF_TWI_EVENT_STOPPED);
+    nrf_twi_event_clear(twi, NRF_TWI_EVENT_RXDREADY);
+    nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR);
+    (void)nrf_twi_errorsrc_get_and_clear(twi);
+
+    nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_SUSPEND_MASK);
+
+    nrf_twi_address_set(twi, twi_address(address));
+    nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME);
+    nrf_twi_task_trigger(twi, NRF_TWI_TASK_STARTRX);
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+    // Zero-length RX transfers are not supported. Such transfers cannot
+    // be easily achieved with TWI peripheral (some dirty tricks would be
+    // required for this), and they are actually useless (TX can be used
+    // to check if the address is acknowledged by a slave).
+    MBED_ASSERT(length > 0);
+
+    twi_info_t *twi_info = TWI_INFO(obj);
+#if DEVICE_I2C_ASYNCH
+    if (twi_info->active)
+    {
+        return I2C_ERROR_BUS_BUSY;
+    }
+#endif
+    twi_info->start_twi = false;
+
+    NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)];
+    start_twi_read(twi, address);
+
+    int result = length;
+
+    while (length > 0)
+    {
+        int byte_read_result = i2c_byte_read(obj, (stop && length == 1));
+        if (byte_read_result < 0)
+        {
+            // When an error occurs, return the number of bytes that have been
+            // received successfully.
+            result -= length;
+            // Force STOP condition.
+            stop = 1;
+            break;
+        }
+        *data++ = (uint8_t)byte_read_result;
+        --length;
+    }
+
+    if (stop)
+    {
+        (void)i2c_stop(obj);
+    }
+
+    return result;
+}
+
+static uint8_t twi_byte_write(NRF_TWI_Type *twi, uint8_t data)
+{
+    nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT);
+    nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR);
+
+    nrf_twi_txd_set(twi, data);
+    uint32_t remaining_time = TIMEOUT_VALUE;
+
+    do
+    {
+        if (nrf_twi_event_check(twi, NRF_TWI_EVENT_TXDSENT))
+        {
+            nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT);
+            return 1; // ACK received
+        }
+        if (nrf_twi_event_check(twi, NRF_TWI_EVENT_ERROR))
+        {
+            nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR);
+            return 0; // some error occurred
+        }
+    }
+    while (--remaining_time);
+
+    return 2; // timeout;
+}
+
+static void start_twi_write(NRF_TWI_Type *twi, int address)
+{
+    nrf_twi_event_clear(twi, NRF_TWI_EVENT_STOPPED);
+    nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT);
+    nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR);
+    (void)nrf_twi_errorsrc_get_and_clear(twi);
+
+    nrf_twi_shorts_set(twi, 0);
+
+    nrf_twi_address_set(twi, twi_address(address));
+    nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME);
+    nrf_twi_task_trigger(twi, NRF_TWI_TASK_STARTTX);
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+    twi_info_t *twi_info = TWI_INFO(obj);
+#if DEVICE_I2C_ASYNCH
+    if (twi_info->active)
+    {
+        return I2C_ERROR_BUS_BUSY;
+    }
+#endif
+    twi_info->start_twi = false;
+
+    NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)];
+    start_twi_write(twi, address);
+
+    // Special case - transaction with no data.
+    // It can be used to check if a slave acknowledges the address.
+    if (length == 0)
+    {
+        nrf_twi_event_t event;
+        if (stop)
+        {
+            event = NRF_TWI_EVENT_STOPPED;
+            nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP);
+        }
+        else
+        {
+            event = NRF_TWI_EVENT_SUSPENDED;
+            nrf_twi_event_clear(twi, event);
+            nrf_twi_task_trigger(twi, NRF_TWI_TASK_SUSPEND);
+        }
+        uint32_t remaining_time = TIMEOUT_VALUE;
+
+        do
+        {
+            if (nrf_twi_event_check(twi, event))
+            {
+                break;
+            }
+        }
+        while (--remaining_time);
+
+        uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(twi);
+        if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK)
+        {
+            if (!stop)
+            {
+                i2c_stop(obj);
+            }
+            return I2C_ERROR_NO_SLAVE;
+        }
+
+        return (remaining_time ? 0 : I2C_ERROR_BUS_BUSY);
+    }
+
+    int result = length;
+
+    do
+    {
+        uint8_t byte_write_result = twi_byte_write(twi, (uint8_t)*data++);
+        if (byte_write_result != 1)
+        {
+            if (byte_write_result == 0)
+            {
+                // Check what kind of error has been signaled by TWI.
+                uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(twi);
+                if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK)
+                {
+                    result = I2C_ERROR_NO_SLAVE;
+                }
+                else
+                {
+                    // Some other error - return the number of bytes that
+                    // have been sent successfully.
+                    result -= length;
+                }
+            }
+            else
+            {
+                result = I2C_ERROR_BUS_BUSY;
+            }
+            // Force STOP condition.
+            stop = 1;
+            break;
+        }
+        --length;
+    }
+    while (length > 0);
+
+    if (stop)
+    {
+        (void)i2c_stop(obj);
+    }
+
+    return result;
+}
+
+int i2c_byte_read(i2c_t *obj, int last)
+{
+    NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)];
+
+    if (last)
+    {
+        nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_STOP_MASK);
+    }
+    nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME);
+
+    uint32_t remaining_time = TIMEOUT_VALUE;
+
+    do
+    {
+        if (nrf_twi_event_check(twi, NRF_TWI_EVENT_RXDREADY))
+        {
+            nrf_twi_event_clear(twi, NRF_TWI_EVENT_RXDREADY);
+            return nrf_twi_rxd_get(twi);
+        }
+        if (nrf_twi_event_check(twi, NRF_TWI_EVENT_ERROR))
+        {
+            nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR);
+            return I2C_ERROR_NO_SLAVE;
+        }
+    }
+    while (--remaining_time);
+
+    return I2C_ERROR_BUS_BUSY;
+}
+
+int i2c_byte_write(i2c_t *obj, int data)
+{
+    NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)];
+    twi_info_t *twi_info = TWI_INFO(obj);
+    if (twi_info->start_twi)
+    {
+        twi_info->start_twi = false;
+
+        if (data & 1)
+        {
+            start_twi_read(twi, data);
+        }
+        else
+        {
+            start_twi_write(twi, data);
+        }
+        return 1;
+    }
+    else
+    {
+        nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME);
+        // 0 - TWI signaled error (NAK is the only possibility here)
+        // 1 - ACK received
+        // 2 - timeout (clock stretched for too long?)
+        return twi_byte_write(twi, (uint8_t)data);
+    }
+}
+
+
+#if DEVICE_I2C_ASYNCH
+void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length,
+                         void *rx, size_t rx_length, uint32_t address,
+                         uint32_t stop, uint32_t handler,
+                         uint32_t event, DMAUsage hint)
+{
+    (void)hint;
+
+    twi_info_t *twi_info = TWI_INFO(obj);
+    if (twi_info->active)
+    {
+        return;
+    }
+    twi_info->active    = true;
+    twi_info->events    = 0;
+    twi_info->handler   = (void (*)(void))handler;
+    twi_info->evt_mask  = event;
+    twi_info->tx_length = tx_length;
+    twi_info->tx        = tx;
+    twi_info->rx_length = rx_length;
+    twi_info->rx        = rx;
+    twi_info->stop      = stop;
+
+    NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)];
+
+    nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT);
+    nrf_twi_event_clear(twi, NRF_TWI_EVENT_RXDREADY);
+    nrf_twi_event_clear(twi, NRF_TWI_EVENT_STOPPED);
+    nrf_twi_event_clear(twi, NRF_TWI_EVENT_SUSPENDED);
+    nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR);
+    (void)nrf_twi_errorsrc_get_and_clear(twi);
+
+    nrf_twi_address_set(twi, twi_address(address));
+    nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME);
+    // TX only, or TX + RX (after a repeated start).
+    if (tx_length > 0)
+    {
+        nrf_twi_task_trigger(twi, NRF_TWI_TASK_STARTTX);
+        nrf_twi_txd_set(twi, *(twi_info->tx));
+        ++(twi_info->tx);
+        // RX only.
+    }
+    else if (rx_length > 0)
+    {
+        start_asynch_rx(twi_info, twi);
+        // Both 'tx_length' and 'rx_length' are 0 - this case may be used
+        // to test if the slave is presentand ready for transfer (by just
+        // sending the address and checking if it is acknowledged).
+    }
+    else
+    {
+        nrf_twi_task_trigger(twi, NRF_TWI_TASK_STARTTX);
+        if (stop)
+        {
+            nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP);
+        }
+        else
+        {
+            nrf_twi_task_trigger(twi, NRF_TWI_TASK_SUSPEND);
+            nrf_twi_int_enable(twi, NRF_TWI_INT_SUSPENDED_MASK);
+        }
+        twi_info->events |= I2C_EVENT_TRANSFER_COMPLETE;
+    }
+
+    nrf_twi_int_enable(twi, NRF_TWI_INT_TXDSENT_MASK |
+                            NRF_TWI_INT_RXDREADY_MASK |
+                            NRF_TWI_INT_STOPPED_MASK |
+                            NRF_TWI_INT_ERROR_MASK);
+}
+
+uint32_t i2c_irq_handler_asynch(i2c_t *obj)
+{
+    twi_info_t *twi_info = TWI_INFO(obj);
+    return (twi_info->events & twi_info->evt_mask);
+}
+
+uint8_t i2c_active(i2c_t *obj)
+{
+    twi_info_t *twi_info = TWI_INFO(obj);
+    return twi_info->active;
+}
+
+void i2c_abort_asynch(i2c_t *obj)
+{
+    i2c_reset(obj);
+}
+#endif // DEVICE_I2C_ASYNCH
+
+#endif // DEVICE_I2C

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/irq_handlers_hw.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,55 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @file irq_handlers_hw.h
+ * @brief Heleper file for wiring irq handlers to theirs vectors.
+ */
+ 
+#ifndef IRQ_HANDLERS_HW_H__
+#define IRQ_HANDLERS_HW_H__
+
+
+typedef struct
+{
+    IRQn_Type      IRQn;
+    uint32_t       vector;
+} peripheral_handler_desc_t;
+
+#endif // IRQ_HANDLERS_HW_H__
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/lp_ticker.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "lp_ticker_api.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "common_rtc.h"
+
+void lp_ticker_init(void)
+{
+    common_rtc_init();
+}
+
+uint32_t lp_ticker_read()
+{
+    return (uint32_t)common_rtc_64bit_us_get();
+}
+
+void lp_ticker_set_interrupt(timestamp_t timestamp)
+{
+    common_rtc_set_interrupt(timestamp,
+        LP_TICKER_CC_CHANNEL, LP_TICKER_INT_MASK);
+}
+
+void lp_ticker_disable_interrupt(void)
+{
+    nrf_rtc_event_disable(COMMON_RTC_INSTANCE, LP_TICKER_INT_MASK);
+}
+
+void lp_ticker_clear_interrupt(void)
+{
+    nrf_rtc_event_clear(COMMON_RTC_INSTANCE, LP_TICKER_EVENT);
+}
+
+#endif // DEVICE_LOWPOWERTIMER

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/nordic_critical.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>                  // uint32_t, UINT32_MAX
+#include <assert.h>                  // uint32_t, UINT32_MAX
+#include "cmsis.h"
+#include "nrf_soc.h"
+#include "nrf_sdm.h"
+#include "nrf_nvic.h"
+
+static uint8_t  _sd_state = 0;
+static volatile uint32_t _entry_count = 0;
+
+void core_util_critical_section_enter()
+{
+    // if a critical section has already been entered, just update the counter
+    if (_entry_count)
+    {
+        ++_entry_count;
+        return;
+    }
+
+    // in this path, a critical section has never been entered
+    // routine of SD V11 work even if the softdevice is not active
+    sd_nvic_critical_region_enter(&_sd_state);
+
+    assert(_entry_count == 0); // entry count should always be equal to 0 at this point
+    ++_entry_count;
+}
+
+void core_util_critical_section_exit()
+{
+    assert(_entry_count > 0);
+    --_entry_count;
+
+    // If their is other segments which have entered the critical section, just leave
+    if (_entry_count)
+    {
+        return;
+    }
+
+    // This is the last segment of the critical section, state should be restored as before entering
+    // the critical section
+    sd_nvic_critical_region_exit(_sd_state);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/nrf5x_lf_clk_helper.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,66 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef __NRF5X_LF_CLK_HELPER_H_
+    
+#ifndef MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC
+    #define MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC (NRF_LF_SRC_XTAL)
+    #warning No configuration for LF clock source. Xtal source will be used as a default configuration.
+#endif
+
+
+
+#define NRF_LF_SRC_XTAL  2 
+#define NRF_LF_SRC_SYNTH 3 
+#define NRF_LF_SRC_RC    4
+
+#if MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_SYNTH
+    #define CLOCK_LFCLKSRC_SRC_TO_USE (CLOCK_LFCLKSRC_SRC_Synth)
+#elif MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_XTAL
+    #define CLOCK_LFCLKSRC_SRC_TO_USE (CLOCK_LFCLKSRC_SRC_Xtal)
+#elif MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_RC
+    #define CLOCK_LFCLKSRC_SRC_TO_USE (CLOCK_LFCLKSRC_SRC_RC)
+#else
+    #error Bad LFCLK configuration. Declare proper source through mbed configuration.
+#endif
+
+#undef NRF_LF_SRC_XTAL
+#undef NRF_LF_SRC_SYNTH
+#undef NRF_LF_SRC_RC
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/objects.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,98 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct serial_s
+{
+    uint32_t placeholder; // struct is unused by nRF5x API implementation
+};                        // but it must be not empty (required by strict compiler - IAR)
+
+struct spi_s
+{
+    uint8_t spi_idx;
+};
+
+struct port_s
+{
+    PortName port;
+    uint32_t mask;
+};
+
+struct pwmout_s
+{
+    PWMName pwm_name;
+    PinName pin;
+    uint8_t pwm_channel;
+    void *  pwm_struct;
+};
+
+struct i2c_s
+{
+    uint8_t twi_idx;
+};
+
+struct analogin_s
+{
+    ADCName adc;
+    uint8_t adc_pin;
+};
+
+struct gpio_irq_s
+{
+    uint32_t ch;
+};
+
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/pinmap.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,37 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "pinmap.h"
+
+void pin_function(PinName pin, int function)
+{
+    /* Avoid compiler warnings */
+    (void) pin;
+    (void) function;
+}
+
+void pin_mode(PinName pin, PinMode mode)
+{
+    MBED_ASSERT(pin != (PinName)NC);
+
+    uint32_t pin_number = (uint32_t)pin;
+    
+    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+
+    reg->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_PULL_Msk;
+    reg->PIN_CNF[pin_number] |= (mode << GPIO_PIN_CNF_PULL_Pos);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/port_api.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,133 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "port_api.h"
+#include "pinmap.h"
+
+static NRF_GPIO_Type * const m_ports[] = GPIO_REG_LIST;
+
+#if defined(TARGET_MCU_NRF51822)
+    static const uint32_t m_gpio_pin_count[] = {31};
+#elif defined(TARGET_MCU_NRF52832)
+    static const uint32_t m_gpio_pin_count[] = {32};
+#elif defined(TARGET_MCU_NRF52840)
+    static const uint32_t m_gpio_pin_count[] = {32, 16};
+#else
+    #error not recognized gpio count for mcu
+#endif
+
+#define GPIO_PORT_COUNT (sizeof(m_gpio_pin_count)/sizeof(uint32_t))
+
+
+PinName port_pin(PortName port, int pin_n)
+{
+    return (PinName)NRF_GPIO_PIN_MAP(port, pin_n);
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
+    MBED_ASSERT((uint32_t)port < GPIO_PORT_COUNT);
+    
+    obj->port = port;
+    obj->mask = mask;
+
+    port_dir(obj, dir);
+}
+
+void port_mode(port_t *obj, PinMode mode)
+{
+    uint32_t i;
+    // The mode is set per pin: reuse pinmap logic
+    for (i = 0; i < m_gpio_pin_count[obj->port]; i++)
+    {
+        if (obj->mask & (1 << i))
+        {
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_dir(port_t *obj, PinDirection dir)
+{
+    uint32_t i;
+    
+    volatile uint32_t *reg_cnf = (volatile uint32_t*) m_ports[obj->port]->PIN_CNF;
+
+    switch (dir)
+    {
+        case PIN_INPUT:
+
+            for (i = 0; i < m_gpio_pin_count[obj->port]; i++)
+            {
+                if (obj->mask & (1 << i))
+                {
+                    reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
+                                 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
+                                 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
+                                 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
+                }
+            }
+            break;
+
+        case PIN_OUTPUT:
+
+            for (i = 0; i < m_gpio_pin_count[obj->port]; i++)
+            {
+                if (obj->mask & (1 << i))
+                {
+                    reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
+                                 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
+                                 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
+                                 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
+                                 | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+                }
+            }
+            break;
+    }
+}
+
+void port_write(port_t *obj, int value)
+{
+    m_ports[obj->port]->OUTSET = value & obj->mask;
+    m_ports[obj->port]->OUTCLR = (~value) & obj->mask;
+}
+
+int port_read(port_t *obj)
+{
+    return ((m_ports[obj->port]->IN) & obj->mask);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/porting_tools/copyright_header.txt	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,37 @@
+/* 
+ * Copyright (c) <YEAR> Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/porting_tools/replace_headers.py	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,48 @@
+import os
+import re
+
+
+
+
+def replace_header(in_path):
+    with open("copyright_header.txt", "r") as fd:
+        header = fd.read()
+
+        for root, dirs, files in os.walk(in_path):
+            for fn in [os.path.join(root, x) for x in files]:
+                with open(fn, "r+") as fd:
+                    #print fn
+                    s = fd.read()
+                    start = s.find("/*")
+                    end = s.find("*/")
+                    copyright_str = s[start:end+2]
+                    if ("copyright (c)" in copyright_str.lower()) and ("nordic semiconductor" in copyright_str.lower()):
+
+                    
+                        pat_reg  = r"copyright \(c\)[\s]{1,5}([0-9]{4})"
+                        find_obj = re.search(pat_reg, copyright_str.lower())
+                        
+                        if find_obj == None:
+                            header_year = re.sub(r'(<YEAR>)',"2000",header)
+                            print "default date>>" + fn
+                        else:
+                            header_year = re.sub(r'(<YEAR>)',find_obj.group(1),header)
+                        
+                        s = s.replace(copyright_str, header_year)
+                        
+                        #print(header_year)
+
+                        fd.seek(0)
+                        fd.write(s)
+                        fd.truncate()
+                        
+                        ##print "+"*35
+                        print fn
+
+
+pathes = ["..\\sdk",
+          "..\\TARGET_MCU_NRF52832\\sdk",
+          "..\\TARGET_MCU_NRF52840\\sdk"]
+    
+for path in pathes:
+    replace_header(path)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/porting_tools/sdk_update.py	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,277 @@
+#!python3
+import os, shutil, json, pprint, sys, string, json, argparse
+from collections import OrderedDict
+from shutil import copyfile, copytree
+
+def rename_sdk_old_dirs(path, dry_run = False):
+    # I make assumption that all old sdk dirs have "sdk" names.
+    sdk_dir_name = "sdk"
+    path = "."
+    
+    for root, dirs, files in os.walk(path):
+        for name in dirs:
+            if name == "sdk":
+                full_path = root + "\\" + name
+                new_full_path = root + "\\_old_" + name
+                print("rename " + full_path + " ---> " + new_full_path)
+                if not dry_run:
+                    os.rename(full_path, new_full_path)
+                    os.mkdir(full_path)
+    
+def rename_dirs(sdk_dirs_in_mbed, new_name, dry_run=False):
+    
+    for dir_path in sdk_dirs_in_mbed:
+        xdir_path = os.path.join('.',dir_path)
+        new_dir_path = os.path.join(os.path.dirname(xdir_path), new_name)
+        print("rename " + xdir_path + " ---> " + new_dir_path)
+        if not dry_run:
+            os.rename(xdir_path, new_dir_path)
+ 
+def get_file_pathes_couples(path_sdk_componets, skip_dirs = [], skip_files = [], verbose = False):
+    mbed_list = []
+    cutted_roots = []
+    cutted_files = []
+    
+    path_sdk_componets = path_sdk_componets + '\\'
+    
+    for root, dirs, files in os.walk(path_sdk_componets):
+        procced = True
+        cutted_root = root[len(path_sdk_componets):]
+        
+        for skip_d in skip_dirs:
+            if 0 == string.find(cutted_root, skip_d):
+                cutted_roots.append(cutted_root)
+                procced = False
+         
+        if procced:
+            for file_name in files:
+            
+                procced = True
+                for skip_f in skip_files:
+                    if (-1) != string.find(file_name, skip_f):
+                        cutted_files.append(file_name)
+                        procced = False
+                        
+                if procced:
+                    if file_name.endswith((".c", ".h")):
+                        #cutted_path = cutted_root + "\\" + file_name
+                        cutted_path = os.path.join(cutted_root, file_name)
+                        #full_path = root + "\\" + file_name
+                        full_path = os.path.join(root, file_name)
+                        item = {"full_path": full_path, "id": cutted_path, "cutted_root": cutted_root}
+                        #mbed_list.append([full_path, cutted_path])
+                        mbed_list.append(item)
+
+    if verbose:                    
+        print("\r\nskipped directories:  {0:#d}".format(len(cutted_roots)))
+    
+        for xitem in cutted_roots:
+            print(xitem)
+
+        print("\r\nskipped files:  {0:#d}".format(len(cutted_files)))
+
+        for kitem in cutted_files:
+            print(kitem)
+    
+    return mbed_list
+    
+def apply_replacement_id(mbed_list, replacemet_couples):
+    for item in mbed_list:
+        splited = os.path.split(item["id"])
+        result = string.find(splited[1], replacemet_couples["old"])
+        if result != -1:
+            new_tail = replacemet_couples["new"] + splited[1][len(replacemet_couples["old"]):]
+            item["id"] = os.path.join(splited[0],new_tail)
+            #print('bingo!')
+            #print(item)
+        
+    return mbed_list
+            
+
+def get_copying_automatic_list(list_mbed, list_sdk, mbed_port_path = '', verbose = False):
+    copy_list = [] #list of copy items
+    orphan_list = []
+
+    licz = 0
+    for pathes_mbed in list_mbed:
+        empty = True
+        for pathes_sdk in list_sdk:
+            if pathes_mbed["id"] == pathes_sdk["id"]:
+                dest_path = pathes_mbed["full_path"]
+
+                dest_path = dest_path[ (len(mbed_port_path)):]
+            
+                item = {"id" : pathes_mbed["id"], "src_path": pathes_sdk["full_path"], "dest_path": dest_path, "old_path": pathes_mbed["full_path"]}
+                copy_list.append(item)
+                
+                empty = False;
+                
+                
+        if empty:
+            orphan_list.append(pathes_mbed["full_path"])
+    
+    print("\r\nfitted files: {0:#d}".format(len(copy_list)))
+    
+    if verbose:
+        for item in copy_list:
+            str_verbose = "{0} --> {1}"
+            print(str_verbose.format(item["id"], item["dest_path"]))
+    
+    
+    print("\r\norphaned files:  {0:#d}".format(len(orphan_list)))
+
+    if verbose:
+        for xitem in orphan_list:
+            print(xitem)
+            
+    return copy_list
+    
+def is_in_copying_list(copy_list, file_id):
+    for pathes_copy in copy_list:
+        if pathes_copy["id"] == file_id:
+
+            return False
+            
+    return True
+
+    
+def upgrade_copying_list(copy_list, pathes_sdk, dest_mbed_dir_path, print_list):
+    splited = os.path.split(pathes_sdk["id"])
+    dest_path = os.path.join(dest_mbed_dir_path, splited[1])
+    item = {"id" : pathes_sdk["id"], "src_path": pathes_sdk["full_path"], "dest_path": dest_path} #, "old_path": pathes_mbed["full_path"]}
+    copy_list.append(item)    
+    print_list.append(item)
+    
+    
+    
+    
+def upgrade_copying_list_by_dirs(copy_list, list_sdk, force_copy_dirs_list, port_relative_dir = '',verbose = False):
+    print_list = []
+    
+    for pathes_sdk in list_sdk:
+        if is_in_copying_list(copy_list, pathes_sdk["id"]):
+            
+            make_hard_copy = False
+            
+            for hard_copy_dir in force_copy_dirs_list:
+            
+                if 0 == string.find(pathes_sdk["cutted_root"], hard_copy_dir["sdk_dir"]):
+            
+                    make_hard_copy = True
+
+                    post_path = os.path.relpath(pathes_sdk["cutted_root"], hard_copy_dir["sdk_dir"])
+                    
+                    if post_path == '.':
+                        corect_hard_copy_dir = hard_copy_dir["mbed_dir"]
+                    if post_path != '.': # destynation is a nested directory
+                        corect_hard_copy_dir = os.path.join(hard_copy_dir["mbed_dir"], post_path)
+                    
+                    corect_hard_copy_dir = os.path.join(port_relative_dir, corect_hard_copy_dir)
+                    
+                    upgrade_copying_list(copy_list, pathes_sdk, corect_hard_copy_dir, print_list)
+                    break
+                    
+                
+    print("\r\nforced copy of files by directories: {0:#d}".format(len(print_list)))
+    
+    if verbose:
+        for item in print_list:
+            str_verbose = "{0} --> {1}"
+            print(str_verbose.format(item["id"], item["dest_path"]))
+                        
+def upgrade_copying_list_by_files(copy_list, list_sdk, force_copy_files_list, port_relative_dir ='',verbose = False):
+    print_list = []
+    
+    for pathes_sdk in list_sdk:
+        if is_in_copying_list(copy_list, pathes_sdk["id"]):
+            
+            make_hard_copy = False
+            
+            for hard_copy_file in force_copy_files_list:
+                if pathes_sdk["id"] == hard_copy_file["sdk_file"]:
+                    make_hard_copy = True
+                    
+                    corect_hard_copy_dir = os.path.join(port_relative_dir, hard_copy_file["mbed_dir"])
+                    
+                    upgrade_copying_list(copy_list, pathes_sdk, corect_hard_copy_dir, print_list)
+                    break
+                
+    print("\r\nforced copy of files by files: {0:#d}".format(len(print_list)))
+    
+    if verbose:
+        for item in print_list:
+            str_verbose = "{0} --> {1}"
+            print(str_verbose.format(item["id"], item["dest_path"]))
+            
+def copy_one_file(src, dest, verbose=False,dry_run=False):
+    dirs_to_created = os.path.dirname(dest)
+    
+    if not os.path.exists(dirs_to_created):
+        if not dry_run:
+            os.makedirs(dirs_to_created)
+            
+        if verbose:
+            print('makerdirs: {0}'.format(dirs_to_created))
+        
+    if not dry_run:
+        shutil.copyfile(src, dest)
+        
+    if verbose:        
+        print('copy: {0} --> {1}'.format(src, dest))
+
+
+
+if __name__ == '__main__':
+    argument_parser = argparse.ArgumentParser()
+    argument_parser.add_argument('-r', '--run', help='run', action='store_true')
+    argument_parser.add_argument('-v', '--verbose', help='Verbose mode', action='store_true')
+    #argument_parser.add_argument('-r', '--rename_only', help='rename only', action='store_true')
+    
+    parser_args = vars(argument_parser.parse_args())    
+    
+    verbose = False
+    
+    if parser_args['verbose'] or not parser_args['run']:
+        verbose = True
+                        
+    with open('update_desc.json') as data_file:    
+        update_desc = json.load(data_file)
+
+    
+    #if not parser_args ['rename_only']:
+    ignore_file_list = update_desc['ignore_file_list']
+    ignore_dirs_list = update_desc['ignore_dirs_list']
+    id_replacements  = update_desc['id_replacements']
+    force_copy_files_list = update_desc['force_copy_files_list']
+    force_copy_dirs_list = update_desc['force_copy_dirs_list']
+    sdk_dirs_in_mbed  = update_desc['sdk_dirs_in_mbed']
+    sdk_component_path = update_desc['sdk_component_path']
+    port_relative_dir = update_desc['port_relative_dir_in_mbed']
+     
+    list_sdk = get_file_pathes_couples(sdk_component_path,
+                                       ignore_dirs_list,
+                                       ignore_file_list,
+                                       verbose)
+    list_mbed = []
+    for directory in sdk_dirs_in_mbed:
+        list_mbed.extend(get_file_pathes_couples(directory))
+
+    list_mbed = apply_replacement_id(list_mbed, id_replacements)
+
+    mbed_port_path = ''
+
+    copy_list = get_copying_automatic_list(list_mbed, list_sdk, mbed_port_path, verbose)
+            
+    upgrade_copying_list_by_dirs(copy_list, list_sdk, force_copy_dirs_list, port_relative_dir, verbose)
+    upgrade_copying_list_by_files(copy_list, list_sdk, force_copy_files_list, port_relative_dir, verbose)
+    
+    rename_dirs(sdk_dirs_in_mbed, '_old_sdk', not parser_args['run'])
+    
+    for copy_item in copy_list:
+        src = os.path.join('.',copy_item["src_path"])
+        dest = os.path.join('.',copy_item["dest_path"])
+            
+        copy_one_file(src, dest, verbose, not parser_args['run'])
+            
+    with open('sdk_update_result.json', 'w') as fp:
+        json.dump(copy_list, fp)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/porting_tools/update_desc.json	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,122 @@
+{
+    "id_replacements" : {"old": "nrf_ble", "new": "ble"},
+    "ignore_dirs_list" : [ "ant",
+                      "nfc",
+                      "proprietary_rf",
+                      "serialization",
+                      "toolchain",
+                      "ble\\ble_services\\ble_ancs_c",
+                      "ble\\ble_services\\ble_ans_c",
+                      "ble\\ble_services\\ble_bas",
+                      "ble\\ble_services\\ble_bas_c",
+                      "ble\\ble_services\\ble_bps",
+                      "ble\\ble_services\\ble_cscs",
+                      "ble\\ble_services\\ble_cts_c",
+                      "ble\\ble_services\\ble_dis",
+                      "ble\\ble_services\\ble_escs",
+                      "ble\\ble_services\\ble_gls",
+                      "ble\\ble_services\\ble_hids",
+                      "ble\\ble_services\\ble_hrs",
+                      "ble\\ble_services\\ble_hrs_c",
+                      "ble\\ble_services\\ble_hts",
+                      "ble\\ble_services\\ble_ias",
+                      "ble\\ble_services\\ble_ias_c",
+                      "ble\\ble_services\\ble_lbs",
+                      "ble\\ble_services\\ble_lbs_c",
+                      "ble\\ble_services\\ble_lls",
+                      "ble\\ble_services\\ble_nus",
+                      "ble\\ble_services\\ble_nus_c",
+                      "ble\\ble_services\\ble_rscs",
+                      "ble\\ble_services\\ble_rscs_c",
+                      "ble\\ble_services\\ble_tps",
+                      "ble\\ble_services\\experimental_ble_lns",
+                      "ble\\ble_services\\experimental_nrf_ble_bms",
+                      "ble\\ble_services\\experimental_nrf_ble_cgms",
+                      "drivers_ext",
+                      "softdevice\\s212",
+                      "softdevice\\s332",
+                      "ble\\nrf_ble_qwr",
+                      "libraries\\button",
+                      "libraries\\crc32",
+                      "libraries\\crypto",
+                      "libraries\\csense",
+                      "libraries\\ecc",
+                      "libraries\\fifo",
+                      "libraries\\gpiote",
+                      "libraries\\hardfault",
+                      "libraries\\ic_info",
+                      "libraries\\led_softblink",
+                      "libraries\\low_power_pwm",
+                      "libraries\\mailbox",
+                      "libraries\\mem_manager",
+                      "libraries\\sensorsim",
+                      "libraries\\sha256",
+                      "libraries\\simple_timer",
+                      "libraries\\slip",
+                      "libraries\\timer",
+                      "libraries\\twi",
+                      "libraries\\uart",
+                      "drivers_nrf\\twi_master\\deprecated"
+                    ],
+                    
+    "ignore_file_list": [
+                            "dox_config.h",
+                            "ble_error_log.c",
+                            "ble_conn_params.c",
+                            "app_error_weak_cmock.c",
+                            "hci_slip.c",
+                            "hci_slip.h",
+                            "hci_transport.c",
+                            "hci_transport.h",
+                            "spi_5W_master.c",
+                            "spi_5W_master.h",
+                            "app_scheduler_serconn.c"
+                        ],
+                    
+    "force_copy_files_list" : [{"sdk_file": "sdk_validation.h", "mbed_dir": "sdk"},
+                         {"sdk_file": "drivers_nrf\\hal\\nrf_comp.h", "mbed_dir": "sdk\\drivers_nrf\\hal"},
+                         {"sdk_file": "drivers_nrf\\hal\\nrf_egu.h", "mbed_dir": "sdk\\drivers_nrf\\hal"},
+                         {"sdk_file": "drivers_nrf\\hal\\nrf_i2s.h", "mbed_dir": "sdk\\drivers_nrf\\hal"},
+                         {"sdk_file": "drivers_nrf\\hal\\nrf_lpcomp.h", "mbed_dir": "sdk\\drivers_nrf\\hal"},
+                         {"sdk_file": "drivers_nrf\\hal\\nrf_peripherals.h", "mbed_dir": "sdk\\drivers_nrf\\hal"},
+                         {"sdk_file": "drivers_nrf\\hal\\nrf_qdec.h", "mbed_dir": "sdk\\drivers_nrf\\hal"},
+                         {"sdk_file": "drivers_nrf\\hal\\nrf_rng.h", "mbed_dir": "sdk\\drivers_nrf\\hal"},
+                         {"sdk_file": "drivers_nrf\\hal\\nrf_twim.h", "mbed_dir": "sdk\\drivers_nrf\\hal"},
+                         {"sdk_file": "drivers_nrf\\hal\\nrf_twis.h", "mbed_dir": "sdk\\drivers_nrf\\hal"},
+                         {"sdk_file": "drivers_nrf\\hal\\nrf_uarte.h", "mbed_dir": "sdk\\drivers_nrf\\hal"}
+                        ],
+                        
+    "force_copy_dirs_list" : [{"sdk_dir": "device",                    "mbed_dir": "sdk\\device"},
+                        {"sdk_dir": "ble\\ble_dtm",              "mbed_dir": "sdk\\ble\\ble_dtm"},
+                        {"sdk_dir": "drivers_nrf\\comp",         "mbed_dir": "sdk\\drivers_nrf\\comp"},
+                        {"sdk_dir": "drivers_nrf\\i2s",          "mbed_dir": "sdk\\drivers_nrf\\i2s"},
+                        {"sdk_dir": "drivers_nrf\\lpcomp",       "mbed_dir": "sdk\\drivers_nrf\\lpcomp"},
+                        {"sdk_dir": "drivers_nrf\\nrf_soc_nosd", "mbed_dir": "sdk\\drivers_nrf\\nrf_soc_nosd"},
+                        {"sdk_dir": "drivers_nrf\\pdm",          "mbed_dir": "sdk\\drivers_nrf\\pdm"},
+                        {"sdk_dir": "drivers_nrf\\qdec",         "mbed_dir": "sdk\\drivers_nrf\\qdec"},
+                        {"sdk_dir": "drivers_nrf\\radio_config", "mbed_dir": "sdk\\drivers_nrf\\radio_config"},
+                        {"sdk_dir": "drivers_nrf\\rng",          "mbed_dir": "sdk\\drivers_nrf\\rng"},
+                        {"sdk_dir": "drivers_nrf\\rtc",          "mbed_dir": "sdk\\drivers_nrf\\rtc"},
+                        {"sdk_dir": "drivers_nrf\\sdio",         "mbed_dir": "sdk\\drivers_nrf\\sdio"},
+                        {"sdk_dir": "drivers_nrf\\swi",          "mbed_dir": "sdk\\drivers_nrf\\swi"},
+                        {"sdk_dir": "drivers_nrf\\twis_slave",   "mbed_dir": "sdk\\drivers_nrf\\twis_slave"},
+                        {"sdk_dir": "drivers_nrf\\uart",         "mbed_dir": "sdk\\drivers_nrf\\uart"},
+                        {"sdk_dir": "drivers_nrf\\wdt",          "mbed_dir": "sdk\\drivers_nrf\\wdt"},
+                        {"sdk_dir": "libraries\\log",            "mbed_dir": "sdk\\libraries\\log"},
+                        {"sdk_dir": "libraries\\bootloader",     "mbed_dir": "sdk\\libraries\\bootloader"},
+                        {"sdk_dir": "libraries\\svc",            "mbed_dir": "sdk\\libraries\\svc"},
+                        {"sdk_dir": "ble\\ble_services\\ble_dfu", "mbed_dir": "ble\\ble_services\\ble_dfu"},
+                        {"sdk_dir": "libraries\\bootloader", "mbed_dir": "libraries\\bootloader"},
+                        {"sdk_dir": "softdevice\\s140", "mbed_dir": "TARGET_MCU_NRF52840\\sdk\\softdevice\\s140"},
+                        {"sdk_dir": "softdevice\\s140\\nrf52", "mbed_dir": "TARGET_MCU_NRF52840\\sdk\\softdevice\\s140\\nrf52"}
+                       ],
+                       
+    "sdk_dirs_in_mbed" : [
+                          "..\\sdk",
+                          "..\\TARGET_MCU_NRF52832\\sdk"
+                         ],
+                         
+    "port_relative_dir_in_mbed" : "..",
+                         
+    "sdk_component_path": "C:\\nRF5_SDK_13.0.0-1.alpha_055eef3\\components"
+}
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/pwmout_api.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,399 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "pwmout_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+
+#if DEVICE_PWMOUT
+
+#include "app_util_platform.h"
+#include "nrf_drv_pwm.h"
+
+#define MAX_PWM_COUNTERTOP  (0x7FFF)                 // 0x7FFF is the max of COUNTERTOP value for the PWM peripherial of the nRF52.
+#define MAX_PWM_PERIOD_US   (MAX_PWM_COUNTERTOP * 8) // PWM hw is driven by 16 MHz clock, hence the tick is 1_us/16,
+                                                     // and 128 is the max prescaler value.
+#define MAX_PWM_PERIOD_MS   ((MAX_PWM_PERIOD_US / 1000) + 1)    // approximations advance
+#define MAX_PWM_PERIOD_S    ((MAX_PWM_PERIOD_US / 1000000) + 1) // approximations advance
+
+
+#define PWM_INSTANCE_COUNT  (PWM_COUNT) // import from the nrf_drv_config.h file
+
+///> instances of nRF52 PWM driver
+static const nrf_drv_pwm_t m_pwm_driver[PWM_INSTANCE_COUNT] =
+{
+#if PWM0_ENABLED
+    NRF_DRV_PWM_INSTANCE(0),
+#endif
+#if PWM1_ENABLED
+    NRF_DRV_PWM_INSTANCE(1),
+#endif
+#if PWM2_ENABLED
+    NRF_DRV_PWM_INSTANCE(2)
+#endif
+};
+
+typedef struct
+{
+    uint32_t period_us;
+    uint32_t duty_us;
+    float    duty;
+} pwm_signal_t; /// PWM signal description type
+
+typedef struct
+{
+    nrf_drv_pwm_t * p_pwm_driver;
+    pwm_signal_t signal;
+    volatile nrf_pwm_values_common_t seq_values[1];
+} pwm_t; /// internal PWM instance support type
+
+static pwm_t m_pwm[PWM_INSTANCE_COUNT] =
+{
+#if PWM0_ENABLED
+    {.p_pwm_driver = NULL},
+#endif
+#if PWM1_ENABLED
+    {.p_pwm_driver = NULL},
+#endif
+#if PWM2_ENABLED
+    {.p_pwm_driver = NULL}
+#endif
+};  /// Array of internal PWM instances.
+
+typedef struct
+{
+    uint16_t       period_hwu; // unit related to pwm_clk
+    uint16_t       duty_hwu;   // unit related to pwm_clk
+    nrf_pwm_clk_t  pwm_clk;
+} pulsewidth_set_t; /// helper type for timing calculations
+    
+    
+static void internal_pwmout_exe(pwmout_t *obj, bool new_period, bool initialization);
+    
+// extern PWM nIRQ handler implementations
+void PWM0_IRQHandler(void);
+void PWM1_IRQHandler(void);
+void PWM2_IRQHandler(void);
+
+static const peripheral_handler_desc_t pwm_handlers[PWM_INSTANCE_COUNT] =
+{
+    {
+        PWM0_IRQn,
+        (uint32_t)PWM0_IRQHandler
+    },
+    {
+        PWM1_IRQn,
+        (uint32_t)PWM1_IRQHandler
+    },
+    {
+        PWM2_IRQn,
+        (uint32_t)PWM2_IRQHandler
+    }
+};
+ 
+void pwmout_init(pwmout_t *obj, PinName pin)
+{
+    uint32_t i;
+    
+    for (i = 0; PWM_INSTANCE_COUNT; i++)
+    {
+        if (m_pwm[i].p_pwm_driver == NULL) // a driver instance not assigned to the obj?
+        {
+            NVIC_SetVector(pwm_handlers[i].IRQn, pwm_handlers[i].vector);
+            
+            obj->pin         = pin;
+            
+            obj->pwm_channel = i;
+            
+            m_pwm[i].p_pwm_driver = (nrf_drv_pwm_t *) &m_pwm_driver[i];
+            m_pwm[i].signal.period_us = 200000; // 0.02 s
+            m_pwm[i].signal.duty_us   = 100000;
+            m_pwm[i].signal.duty      = 0.5f;
+            
+            obj->pwm_struct  = &m_pwm[i];
+
+            internal_pwmout_exe(obj, true, true);
+
+            break;
+        }
+    }
+    
+    MBED_ASSERT(i != PWM_INSTANCE_COUNT); // assert if free instance was not found.
+}
+
+void pwmout_free(pwmout_t *obj)
+{
+    nrf_drv_pwm_uninit( (nrf_drv_pwm_t*) obj->pwm_struct );
+
+    m_pwm[obj->pwm_channel].p_pwm_driver = NULL;
+}
+
+void pwmout_write(pwmout_t *obj, float percent)
+{
+    
+    if (percent < 0)
+    {
+        percent = 0;
+    }
+    else if (percent > 1)
+    {
+        percent = 1;
+    }
+    
+    pwm_signal_t * p_pwm_signal = &(((pwm_t*)obj->pwm_struct)->signal);
+    
+    p_pwm_signal->duty = percent;
+    
+    int us  = (((int)p_pwm_signal->period_us) * percent);
+    
+    pwmout_pulsewidth_us(obj, us);
+}
+
+float pwmout_read(pwmout_t *obj)
+{
+    pwm_signal_t * p_pwm_signal = &(((pwm_t*)obj->pwm_struct)->signal);
+    
+    return (float)p_pwm_signal->duty_us / (float)p_pwm_signal->period_us;
+}
+
+void pwmout_period(pwmout_t *obj, float seconds)
+{
+    // raught saturation < 0, quasi-max>
+    if (seconds > MAX_PWM_PERIOD_S)
+    {
+        seconds = MAX_PWM_PERIOD_S;
+    }
+    else if (seconds < 0)
+    {
+        seconds = 0; // f. pwmout_period_us will set period to min. value
+    }
+    
+    int us = seconds * 1000000;
+    
+    pwmout_period_us(obj, us);
+}
+
+void pwmout_period_ms(pwmout_t *obj, int ms)
+{
+    // reught saturation < 0, quasi-max>
+    if (ms > MAX_PWM_PERIOD_MS)
+    {
+        ms = MAX_PWM_PERIOD_MS;
+    }
+    else if (ms < 0)
+    {
+        ms = 0; // f. pwmout_period_us will set period to min. value
+    }
+    
+    int us = ms * 1000;
+    
+    pwmout_period_us(obj, us);
+}
+
+
+void pwmout_period_us(pwmout_t *obj, int us)
+{
+    pwm_signal_t * p_pwm_signal = &(((pwm_t*)obj->pwm_struct)->signal);
+    
+    // saturation <1, real-max>
+    if (us > MAX_PWM_PERIOD_US)
+    {
+        us = MAX_PWM_PERIOD_US;
+    }
+    else if (us < 1)
+    {
+        us = 1;
+    }
+    
+    p_pwm_signal->duty_us = (int)((float)us * p_pwm_signal->duty);
+    
+    p_pwm_signal->period_us  = us;
+    
+    internal_pwmout_exe(obj, true, false);
+}
+
+void pwmout_pulsewidth(pwmout_t *obj, float seconds)
+{
+    // raught saturation < 0, quasi-max>
+    if (seconds > MAX_PWM_PERIOD_S)
+    {
+        seconds = MAX_PWM_PERIOD_S;
+    }
+    else if (seconds < 0)
+    {
+        seconds = 0;
+    }
+    
+    int us = seconds * 1000000;
+    
+    pwmout_pulsewidth_us(obj,us);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
+{
+    // raught saturation < 0, quasi-max>
+    if (ms > MAX_PWM_PERIOD_MS)
+    {
+        ms = MAX_PWM_PERIOD_MS;
+    }
+    else if (ms < 0)
+    {
+        ms = 0;
+    }
+    
+    int us = ms * 1000;
+    
+    pwmout_pulsewidth_us(obj, us);
+}
+
+void pwmout_pulsewidth_us(pwmout_t *obj, int us)
+{
+    // saturation <0, real-max>
+    if (us > MAX_PWM_PERIOD_US)
+    {
+        us = MAX_PWM_PERIOD_US;
+    }
+    else if (us < 0)
+    {
+        us = 0;
+    }
+    
+    pwm_signal_t * p_pwm_signal = &(((pwm_t*)obj->pwm_struct)->signal);
+    
+    p_pwm_signal->duty_us  = us;
+    p_pwm_signal->duty     = us / p_pwm_signal->period_us;
+    
+    internal_pwmout_exe(obj, false, false);
+}
+
+
+
+
+
+
+static ret_code_t pulsewidth_us_set_get(int period_hwu, int duty_hwu, pulsewidth_set_t * p_settings)
+{
+    uint16_t      div;
+    nrf_pwm_clk_t pwm_clk = NRF_PWM_CLK_16MHz;
+    
+    for(div = 1; div <= 128 ; div <<= 1) // 128 is the maximum of clock prescaler for PWM peripherial
+    {
+        if (MAX_PWM_COUNTERTOP >= period_hwu)
+        {
+            p_settings->period_hwu  = period_hwu; // unit [us/16 * div]
+            p_settings->duty_hwu = duty_hwu;       // unit [us/16 * div]
+            p_settings->pwm_clk   = pwm_clk;
+    
+            return NRF_SUCCESS;
+        }
+        
+        period_hwu >>= 1;
+        duty_hwu >>= 1;
+        pwm_clk++;
+    }
+    
+    return NRF_ERROR_INVALID_PARAM;
+}
+
+
+static void internal_pwmout_exe(pwmout_t *obj, bool new_period, bool initialization)
+{
+    pulsewidth_set_t          pulsewidth_set;
+    pwm_signal_t            * p_pwm_signal;
+    nrf_drv_pwm_t           * p_pwm_driver;
+    ret_code_t                ret_code;
+    
+    p_pwm_signal = &(((pwm_t*)obj->pwm_struct)->signal);
+    
+    if (NRF_SUCCESS == pulsewidth_us_set_get(p_pwm_signal->period_us * 16, // base clk for PWM is 16 MHz
+                                             p_pwm_signal->duty_us * 16,   // base clk for PWM is 16 MHz
+                                             &pulsewidth_set))
+    {
+        p_pwm_driver = (((pwm_t*)obj->pwm_struct)->p_pwm_driver);
+        
+        const nrf_pwm_sequence_t seq =
+        {
+            .values.p_common = (nrf_pwm_values_common_t*) (((pwm_t*)obj->pwm_struct)->seq_values),
+            .length          = 1,
+            .repeats         = 0,
+            .end_delay       = 0
+        };
+        
+        (((pwm_t*)obj->pwm_struct)->seq_values)[0] = pulsewidth_set.duty_hwu | 0x8000;
+        
+        if (new_period)
+        {
+            nrf_drv_pwm_config_t config0 =
+            {
+                .output_pins =
+                {
+                    obj->pin | NRF_DRV_PWM_PIN_INVERTED, // channel 0
+                    NRF_DRV_PWM_PIN_NOT_USED,            // channel 1
+                    NRF_DRV_PWM_PIN_NOT_USED,            // channel 2
+                    NRF_DRV_PWM_PIN_NOT_USED,            // channel 3
+                },
+                .irq_priority = PWM_DEFAULT_CONFIG_IRQ_PRIORITY,
+                .base_clock   = pulsewidth_set.pwm_clk,
+                .count_mode   = NRF_PWM_MODE_UP,
+                .top_value    = pulsewidth_set.period_hwu,
+                .load_mode    = NRF_PWM_LOAD_COMMON,
+                .step_mode    = NRF_PWM_STEP_AUTO
+            };
+            
+            if (!initialization)
+            {
+                nrf_drv_pwm_uninit(p_pwm_driver);
+            }
+        
+            ret_code = nrf_drv_pwm_init( p_pwm_driver, &config0, NULL);
+        
+            MBED_ASSERT(ret_code == NRF_SUCCESS); // assert if free instance was not found.
+        }
+
+        nrf_drv_pwm_simple_playback(p_pwm_driver, &seq, 0, NRF_DRV_PWM_FLAG_LOOP);
+    }
+    else
+    {
+        MBED_ASSERT(0); // force assertion
+    }
+    
+}
+
+#endif // DEVICE_PWMOUT

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/reloc_vector_table.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,78 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+#include "nrf.h"
+#include "cmsis_nvic.h"
+#include "stdint.h"
+#include "nrf_sdm.h"
+#include "section_vars.h"
+
+#if defined(__CC_ARM)
+    __attribute__ ((section("noinit"),zero_init))
+    uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS];
+#elif defined(__GNUC__)
+    __attribute__ ((section(".noinit")))
+    uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS];
+#elif defined(__ICCARM__)
+    uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS] @ ".noinit";
+#endif
+
+
+typedef void (*generic_irq_handler_t)(void);
+
+
+extern uint32_t __Vectors[];
+#define VECTORS_FLASH_START __Vectors
+
+/**
+ * @brief Function for relocation of the vector to RAM on nRF5x devices.
+ * This function is intended to be called during startup.
+ */
+void nrf_reloc_vector_table(void)
+{
+    // Copy and switch to dynamic vectors
+    uint32_t *old_vectors = (uint32_t*)VECTORS_FLASH_START;
+    uint32_t i;
+    
+    for (i = 0; i< NVIC_NUM_VECTORS; i++)
+    {
+        nrf_dispatch_vector[i] = old_vectors[i];
+    }
+
+    sd_softdevice_vector_table_base_set((uint32_t) nrf_dispatch_vector);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/rtc_api.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,94 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "rtc_api.h"
+
+#if DEVICE_RTC
+
+#include "common_rtc.h"
+#include "nrf_drv_clock.h"
+#include "app_util_platform.h"
+
+static time_t m_time_base;
+
+void rtc_init(void)
+{
+    common_rtc_init();
+}
+
+void rtc_free(void)
+{
+    // A common counter is used for RTC, lp_ticker and us_ticker, so it can't be
+    // disabled here, but this does not cause any extra cost. Besides, currently
+    // this function is not used by RTC API in mbed-drivers.
+}
+
+int rtc_isenabled(void)
+{
+    return m_common_rtc_enabled;
+}
+
+static uint32_t rtc_seconds_get(void)
+{
+    // Convert current counter value to seconds.
+    uint32_t seconds = nrf_rtc_counter_get(COMMON_RTC_INSTANCE) / RTC_INPUT_FREQ;
+    // Add proper amount of seconds for each registered overflow of the counter.
+    uint32_t seconds_per_overflow = (1uL << RTC_COUNTER_BITS) / RTC_INPUT_FREQ;
+    return (seconds + (m_common_rtc_overflows * seconds_per_overflow));
+}
+
+time_t rtc_read(void)
+{
+    return m_time_base + rtc_seconds_get();
+}
+
+void rtc_write(time_t t)
+{
+    uint32_t seconds;
+
+    do
+    {
+        seconds = rtc_seconds_get();
+        m_time_base = t - seconds;
+    // If the number of seconds indicated by the counter changed during the
+    // update of the time base, just repeat the update, now using the new
+    // number of seconds.
+    } while (seconds != rtc_seconds_get());
+}
+
+#endif // DEVICE_RTC

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_advertising/ble_advertising.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,717 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include  "sdk_common.h"
+#if NRF_MODULE_ENABLED(BLE_ADVERTISING)
+#include "ble_advdata.h"
+#include "ble_advertising.h"
+#include "nrf_soc.h"
+#include "nrf_log.h"
+#include "fstorage.h"
+#include "sdk_errors.h"
+
+
+// Total number of possible advertising modes.
+#define BLE_ADV_MODES                  (5)
+
+
+static bool                            m_initialized;
+static bool                            m_advertising_start_pending;                 /**< Flag to keep track of ongoing operations in flash. */
+
+static ble_adv_evt_t                   m_adv_evt;                                   /**< Advertising event propogated to the main application. The event is either a transaction to a new advertising mode, or a request for whitelist or peer address. */
+
+static ble_adv_mode_t                  m_adv_mode_current;                          /**< Variable to keep track of the current advertising mode. */
+static ble_adv_modes_config_t          m_adv_modes_config;                          /**< Struct to keep track of disabled and enabled advertising modes, as well as time-outs and intervals.*/
+
+static ble_gap_addr_t                  m_peer_address;                              /**< Address of the most recently connected peer, used for direct advertising. */
+static bool                            m_peer_addr_reply_expected;                  /**< Flag to verify that peer address is only set when requested. */
+
+static ble_advdata_t                   m_advdata;                                   /**< Used by the initialization function to set name, appearance, and UUIDs and advertising flags visible to peer devices. */
+static ble_advdata_manuf_data_t        m_manuf_specific_data;                       /**< Manufacturer specific data structure*/
+static uint8_t                         m_manuf_data_array[BLE_GAP_ADV_MAX_SIZE];    /**< Array to store the Manufacturer specific data*/
+static ble_advdata_service_data_t      m_service_data;                              /**< Service data structure. */
+static uint8_t                         m_service_data_array[BLE_GAP_ADV_MAX_SIZE];  /**< Array to store the service data. */
+static ble_advdata_conn_int_t          m_slave_conn_int;                            /**< Connection interval range structure.*/
+static uint16_t                        m_current_slave_link_conn_handle;            /**< Connection handle for the active link. */
+
+static ble_advertising_evt_handler_t   m_evt_handler;                               /**< Handler for the advertising events. Can be initialized as NULL if no handling is implemented on in the main application. */
+static ble_advertising_error_handler_t m_error_handler;                             /**< Handler for the advertising error events. */
+
+static bool                            m_whitelist_temporarily_disabled;            /**< Flag to keep track of temporary disabling of the whitelist. */
+static bool                            m_whitelist_reply_expected;
+
+#if (NRF_SD_BLE_API_VERSION <= 2)
+
+    // For SoftDevices v 2.x, this module caches a whitelist which is retrieved from the
+    // application using an event, and which is passed as a parameter when calling
+    // sd_ble_gap_adv_start().
+
+    static ble_gap_addr_t      * m_p_whitelist_addrs[BLE_GAP_WHITELIST_ADDR_MAX_COUNT];
+    static ble_gap_irk_t       * m_p_whitelist_irks[BLE_GAP_WHITELIST_IRK_MAX_COUNT];
+    static ble_gap_addr_t      m_whitelist_addrs[BLE_GAP_WHITELIST_ADDR_MAX_COUNT];
+    static ble_gap_irk_t       m_whitelist_irks[BLE_GAP_WHITELIST_IRK_MAX_COUNT];
+
+    static ble_gap_whitelist_t   m_whitelist =
+    {
+        .pp_addrs = m_p_whitelist_addrs,
+        .pp_irks  = m_p_whitelist_irks
+    };
+
+#else
+
+    // For SoftDevices v 3.x, this module does not need to cache a whitelist, but it needs to
+    // be aware of whether or not a whitelist has been set (e.g. using the Peer Manager)
+    // in order to start advertising with the proper advertising params (filter policy).
+
+    static bool m_whitelist_in_use;
+
+#endif
+
+
+#if (NRF_SD_BLE_API_VERSION <= 2)
+
+    static bool whitelist_has_entries()
+    {
+        return ((m_whitelist.addr_count != 0) || (m_whitelist.irk_count != 0));
+    }
+
+#else
+
+    static bool whitelist_has_entries()
+    {
+        return m_whitelist_in_use;
+    }
+
+#endif
+
+
+
+/**@brief Function for checking if an address is valid.
+ */
+static bool addr_is_valid(uint8_t const * const addr)
+{
+    for (uint32_t i = 0; i < BLE_GAP_ADDR_LEN; i++)
+    {
+        if (addr[i] != 0)
+        {
+            return true;
+        }
+    }
+    return false;
+}
+
+
+static ble_adv_mode_t adv_mode_next_get(ble_adv_mode_t adv_mode)
+{
+    return (ble_adv_mode_t)((adv_mode + 1) % BLE_ADV_MODES);
+}
+
+
+/**@brief Function for handling the Connected event.
+ *
+ * @param[in] p_ble_evt Event received from the BLE stack.
+ */
+static void on_connected(ble_evt_t const * p_ble_evt)
+{
+    if (p_ble_evt->evt.gap_evt.params.connected.role == BLE_GAP_ROLE_PERIPH)
+    {
+        m_current_slave_link_conn_handle = p_ble_evt->evt.gap_evt.conn_handle;
+    }
+}
+
+
+/**@brief Function for handling the Disconnected event.
+ *
+ * @param[in] p_ble_evt Event received from the BLE stack.
+ */
+static void on_disconnected(ble_evt_t const * p_ble_evt)
+{
+    uint32_t ret;
+
+    m_whitelist_temporarily_disabled = false;
+
+    if (p_ble_evt->evt.gap_evt.conn_handle == m_current_slave_link_conn_handle)
+    {
+       ret = ble_advertising_start(BLE_ADV_MODE_DIRECTED);
+       if ((ret != NRF_SUCCESS) && (m_error_handler != NULL))
+       {
+           m_error_handler(ret);
+       }
+    }
+}
+
+
+/**@brief Function for handling the Timeout event.
+ *
+ * @param[in] p_ble_evt Event received from the BLE stack.
+ */
+static void on_timeout(ble_evt_t const * p_ble_evt)
+{
+    ret_code_t ret;
+
+    if (p_ble_evt->evt.gap_evt.params.timeout.src != BLE_GAP_TIMEOUT_SRC_ADVERTISING)
+    {
+        // Nothing to do.
+        return;
+    }
+
+    // Start advertising in the next mode.
+    ret = ble_advertising_start(adv_mode_next_get(m_adv_mode_current));
+
+    if ((ret != NRF_SUCCESS) && (m_error_handler != NULL))
+    {
+        m_error_handler(ret);
+    }
+}
+
+
+/** @brief Function to determine if a flash write operation in in progress.
+ *
+ * @return true if a flash operation is in progress, false if not.
+ */
+static bool flash_access_in_progress()
+{
+    uint32_t count;
+
+    (void)fs_queued_op_count_get(&count);
+
+    return (count != 0);
+}
+
+
+/**@brief Get the next available advertising mode.
+ *
+ * @param[in] adv_mode Requested advertising mode.
+ *
+ * @returns adv_mode if possible, or the best available mode if not.
+ */
+static ble_adv_mode_t adv_mode_next_avail_get(ble_adv_mode_t adv_mode)
+{
+    bool peer_addr_is_valid = addr_is_valid(m_peer_address.addr);
+
+    // If a mode is disabled, continue to the next mode.
+
+    switch (adv_mode)
+    {
+        case BLE_ADV_MODE_DIRECTED:
+            if ((m_adv_modes_config.ble_adv_directed_enabled) && peer_addr_is_valid)
+            {
+                return BLE_ADV_MODE_DIRECTED;
+            }
+            // Fallthrough.
+
+        case BLE_ADV_MODE_DIRECTED_SLOW:
+            if ((m_adv_modes_config.ble_adv_directed_slow_enabled) && peer_addr_is_valid)
+            {
+                return BLE_ADV_MODE_DIRECTED_SLOW;
+            }
+            // Fallthrough.
+
+        case BLE_ADV_MODE_FAST:
+            if (m_adv_modes_config.ble_adv_fast_enabled)
+            {
+                return BLE_ADV_MODE_FAST;
+            }
+            // Fallthrough.
+
+        case BLE_ADV_MODE_SLOW:
+            if (m_adv_modes_config.ble_adv_slow_enabled)
+            {
+                return BLE_ADV_MODE_SLOW;
+            }
+            // Fallthrough.
+
+        default:
+            return BLE_ADV_MODE_IDLE;
+    }
+}
+
+
+/**@brief Function for starting directed advertising.
+ *
+ * @param[out] p_adv_params Advertising parameters.
+ *
+ * @return NRF_SUCCESS
+ */
+static ret_code_t set_adv_mode_directed(ble_gap_adv_params_t * p_adv_params)
+{
+    m_adv_evt  = BLE_ADV_EVT_DIRECTED;
+
+    p_adv_params->p_peer_addr = &m_peer_address;
+    p_adv_params->type        = BLE_GAP_ADV_TYPE_ADV_DIRECT_IND;
+    p_adv_params->timeout     = 0;
+    p_adv_params->interval    = 0;
+
+    return NRF_SUCCESS;
+}
+
+
+/**@brief Function for starting directed slow advertising.
+ *
+ * @param[out] p_adv_params Advertising parameters.
+ *
+ * @return NRF_SUCCESS
+ */
+static ret_code_t set_adv_mode_directed_slow(ble_gap_adv_params_t * p_adv_params)
+{
+    m_adv_evt = BLE_ADV_EVT_DIRECTED_SLOW;
+
+    p_adv_params->p_peer_addr = &m_peer_address;
+    p_adv_params->type        = BLE_GAP_ADV_TYPE_ADV_DIRECT_IND;
+    p_adv_params->timeout     = m_adv_modes_config.ble_adv_directed_slow_timeout;
+    p_adv_params->interval    = m_adv_modes_config.ble_adv_directed_slow_interval;
+
+    return NRF_SUCCESS;
+}
+
+
+/**@brief Function for starting fast advertising.
+ *
+ * @param[out] p_adv_params Advertising parameters.
+ *
+ * @return NRF_SUCCESS or an error from @ref ble_advdata_set().
+ */
+static ret_code_t set_adv_mode_fast(ble_gap_adv_params_t * p_adv_params)
+{
+    ret_code_t ret;
+
+    p_adv_params->interval = m_adv_modes_config.ble_adv_fast_interval;
+    p_adv_params->timeout  = m_adv_modes_config.ble_adv_fast_timeout;
+
+    if ((m_adv_modes_config.ble_adv_whitelist_enabled) &&
+        (!m_whitelist_temporarily_disabled) &&
+        (whitelist_has_entries()))
+    {
+        #if (NRF_SD_BLE_API_VERSION <= 2)
+            p_adv_params->p_whitelist = &m_whitelist;
+        #endif
+
+        p_adv_params->fp = BLE_GAP_ADV_FP_FILTER_CONNREQ;
+        m_advdata.flags  = BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED;
+
+        ret = ble_advdata_set(&m_advdata, NULL);
+        if (ret != NRF_SUCCESS)
+        {
+            return ret;
+        }
+
+        m_adv_evt = BLE_ADV_EVT_FAST_WHITELIST;
+    }
+    else
+    {
+        m_adv_evt = BLE_ADV_EVT_FAST;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+/**@brief Function for starting slow advertising.
+ *
+ * @param[out] p_adv_params Advertising parameters.
+ *
+ * @return NRF_SUCCESS or an error from @ref ble_advdata_set().
+ */
+static ret_code_t set_adv_mode_slow(ble_gap_adv_params_t * p_adv_params)
+{
+    ret_code_t ret;
+
+    p_adv_params->interval = m_adv_modes_config.ble_adv_slow_interval;
+    p_adv_params->timeout  = m_adv_modes_config.ble_adv_slow_timeout;
+
+    if ((m_adv_modes_config.ble_adv_whitelist_enabled) &&
+        (!m_whitelist_temporarily_disabled) &&
+        (whitelist_has_entries()))
+    {
+        #if (NRF_SD_BLE_API_VERSION <= 2)
+        {
+            p_adv_params->p_whitelist = &m_whitelist;
+        }
+        #endif
+
+        p_adv_params->fp = BLE_GAP_ADV_FP_FILTER_CONNREQ;
+        m_advdata.flags  = BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED;
+
+        ret = ble_advdata_set(&m_advdata, NULL);
+        if (ret != NRF_SUCCESS)
+        {
+            return ret;
+        }
+
+        m_adv_evt = BLE_ADV_EVT_SLOW_WHITELIST;
+    }
+    else
+    {
+        m_adv_evt = BLE_ADV_EVT_SLOW;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_advertising_init(ble_advdata_t                   const * p_advdata,
+                              ble_advdata_t                   const * p_srdata,
+                              ble_adv_modes_config_t          const * p_config,
+                              ble_advertising_evt_handler_t   const   evt_handler,
+                              ble_advertising_error_handler_t const   error_handler)
+{
+    uint32_t ret;
+
+    if ((p_advdata == NULL) || (p_config == NULL))
+    {
+        return NRF_ERROR_NULL;
+    }
+
+    m_initialized                    = true;
+    m_adv_mode_current               = BLE_ADV_MODE_IDLE;
+    m_adv_modes_config               = *p_config;
+    m_evt_handler                    = evt_handler;
+    m_error_handler                  = error_handler;
+    m_current_slave_link_conn_handle = BLE_CONN_HANDLE_INVALID;
+
+    memset(&m_peer_address, 0, sizeof(m_peer_address));
+    memset(&m_advdata,      0, sizeof(m_advdata));
+
+    // Copy advertising data.
+    m_advdata.name_type            = p_advdata->name_type;
+    m_advdata.include_appearance   = p_advdata->include_appearance;
+    m_advdata.flags                = p_advdata->flags;
+    m_advdata.short_name_len       = p_advdata->short_name_len;
+
+    m_advdata.uuids_complete       = p_advdata->uuids_complete;
+    m_advdata.uuids_more_available = p_advdata->uuids_more_available;
+    m_advdata.uuids_solicited      = p_advdata->uuids_solicited;
+
+    if (p_advdata->p_manuf_specific_data != NULL)
+    {
+        m_advdata.p_manuf_specific_data   = &m_manuf_specific_data;
+        m_manuf_specific_data.data.p_data = m_manuf_data_array;
+        m_advdata.p_manuf_specific_data->company_identifier =
+        p_advdata->p_manuf_specific_data->company_identifier;
+        m_advdata.p_manuf_specific_data->data.size = p_advdata->p_manuf_specific_data->data.size;
+
+        for (uint32_t i = 0; i < m_advdata.p_manuf_specific_data->data.size; i++)
+        {
+            m_manuf_data_array[i] = p_advdata->p_manuf_specific_data->data.p_data[i];
+        }
+    }
+
+    if (p_advdata->p_service_data_array != NULL)
+    {
+        m_service_data.data.p_data                   = m_service_data_array;
+        m_advdata.p_service_data_array               = &m_service_data;
+        m_advdata.p_service_data_array->data.p_data  = m_service_data_array;
+        m_advdata.p_service_data_array->data.size    = p_advdata->p_service_data_array->data.size;
+        m_advdata.p_service_data_array->service_uuid = p_advdata->p_service_data_array->service_uuid;
+
+        for (uint32_t i = 0; i < m_advdata.p_service_data_array->data.size; i++)
+        {
+            m_service_data_array[i] = p_advdata->p_service_data_array->data.p_data[i];
+        }
+
+        m_advdata.service_data_count = p_advdata->service_data_count;
+    }
+
+    if (p_advdata->p_slave_conn_int != NULL)
+    {
+        m_advdata.p_slave_conn_int                    = &m_slave_conn_int;
+        m_advdata.p_slave_conn_int->max_conn_interval = p_advdata->p_slave_conn_int->max_conn_interval;
+        m_advdata.p_slave_conn_int->min_conn_interval = p_advdata->p_slave_conn_int->min_conn_interval;
+    }
+
+    if (p_advdata->p_tx_power_level != NULL)
+    {
+        m_advdata.p_tx_power_level = p_advdata->p_tx_power_level;
+    }
+
+#if (NRF_SD_BLE_API_VERSION <= 2)
+        for (int i = 0; i <BLE_GAP_WHITELIST_ADDR_MAX_COUNT ; i++)
+        {
+            m_whitelist.pp_addrs[i] = &m_whitelist_addrs[i];
+        }
+
+        for (int i = 0; i <BLE_GAP_WHITELIST_IRK_MAX_COUNT ; i++)
+        {
+            m_whitelist.pp_irks[i] = &m_whitelist_irks[i];
+        }
+#endif
+
+    ret = ble_advdata_set(&m_advdata, p_srdata);
+    return ret;
+}
+
+
+uint32_t ble_advertising_start(ble_adv_mode_t advertising_mode)
+{
+    uint32_t             ret;
+    ble_gap_adv_params_t adv_params;
+
+    if (m_initialized == false)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    m_adv_mode_current = advertising_mode;
+
+    // Delay starting advertising until the flash operations are complete.
+    if (flash_access_in_progress())
+    {
+        m_advertising_start_pending = true;
+        return NRF_SUCCESS;
+    }
+
+   memset(&m_peer_address, 0, sizeof(m_peer_address));
+
+    if (  ((m_adv_modes_config.ble_adv_directed_enabled)      && (m_adv_mode_current == BLE_ADV_MODE_DIRECTED))
+        ||((m_adv_modes_config.ble_adv_directed_slow_enabled) && (m_adv_mode_current == BLE_ADV_MODE_DIRECTED))
+        ||((m_adv_modes_config.ble_adv_directed_slow_enabled) && (m_adv_mode_current == BLE_ADV_MODE_DIRECTED_SLOW))
+       )
+    {
+        if (m_evt_handler != NULL)
+        {
+            m_peer_addr_reply_expected = true;
+            m_evt_handler(BLE_ADV_EVT_PEER_ADDR_REQUEST);
+        }
+        else
+        {
+            m_peer_addr_reply_expected = false;
+        }
+    }
+
+    m_adv_mode_current = adv_mode_next_avail_get(advertising_mode);
+
+    // Fetch the whitelist.
+    if ((m_evt_handler != NULL) &&
+        (m_adv_mode_current == BLE_ADV_MODE_FAST || m_adv_mode_current == BLE_ADV_MODE_SLOW) &&
+        (m_adv_modes_config.ble_adv_whitelist_enabled) &&
+        (!m_whitelist_temporarily_disabled))
+    {
+        #if (NRF_SD_BLE_API_VERSION >= 3)
+            m_whitelist_in_use = false;
+        #endif
+        m_whitelist_reply_expected = true;
+        m_evt_handler(BLE_ADV_EVT_WHITELIST_REQUEST);
+    }
+    else
+    {
+        m_whitelist_reply_expected = false;
+    }
+
+    // Initialize advertising parameters with default values.
+    memset(&adv_params, 0, sizeof(adv_params));
+
+    adv_params.type = BLE_GAP_ADV_TYPE_ADV_IND;
+    adv_params.fp   = BLE_GAP_ADV_FP_ANY;
+
+    // Set advertising parameters and events according to selected advertising mode.
+    switch (m_adv_mode_current)
+    {
+        case BLE_ADV_MODE_DIRECTED:
+            ret = set_adv_mode_directed(&adv_params);
+            break;
+
+        case BLE_ADV_MODE_DIRECTED_SLOW:
+            ret = set_adv_mode_directed_slow(&adv_params);
+            break;
+
+        case BLE_ADV_MODE_FAST:
+            ret = set_adv_mode_fast(&adv_params);
+            break;
+
+        case BLE_ADV_MODE_SLOW:
+            ret = set_adv_mode_slow(&adv_params);
+            break;
+
+        case BLE_ADV_MODE_IDLE:
+            m_adv_evt = BLE_ADV_EVT_IDLE;
+            break;
+
+        default:
+            break;
+    }
+
+    if (m_adv_mode_current != BLE_ADV_MODE_IDLE)
+    {
+        ret = sd_ble_gap_adv_start(&adv_params);
+        if (ret != NRF_SUCCESS)
+        {
+            return ret;
+        }
+    }
+
+    if (m_evt_handler != NULL)
+    {
+        m_evt_handler(m_adv_evt);
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+void ble_advertising_on_ble_evt(ble_evt_t const * p_ble_evt)
+{
+    switch (p_ble_evt->header.evt_id)
+    {
+        case BLE_GAP_EVT_CONNECTED:
+            on_connected(p_ble_evt);
+            break;
+
+        // Upon disconnection, whitelist will be activated and direct advertising is started.
+        case BLE_GAP_EVT_DISCONNECTED:
+            on_disconnected(p_ble_evt);
+            break;
+
+        // Upon time-out, the next advertising mode is started.
+        case BLE_GAP_EVT_TIMEOUT:
+            on_timeout(p_ble_evt);
+            break;
+
+        default:
+            break;
+    }
+}
+
+
+void ble_advertising_on_sys_evt(uint32_t sys_evt)
+{
+    uint32_t ret;
+
+    switch (sys_evt)
+    {
+        //When a flash operation finishes, re-attempt to start advertising operations.
+        case NRF_EVT_FLASH_OPERATION_SUCCESS:
+        case NRF_EVT_FLASH_OPERATION_ERROR:
+            if (m_advertising_start_pending)
+            {
+                m_advertising_start_pending = false;
+                ret = ble_advertising_start(m_adv_mode_current);
+                if ((ret != NRF_SUCCESS) && (m_error_handler != NULL))
+                {
+                    m_error_handler(ret);
+                }
+            }
+            break;
+
+        default:
+            // No implementation needed.
+            break;
+    }
+}
+
+
+uint32_t ble_advertising_peer_addr_reply(ble_gap_addr_t * p_peer_address)
+{
+    if (!m_peer_addr_reply_expected)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    m_peer_addr_reply_expected = false;
+
+    memcpy(&m_peer_address, p_peer_address, sizeof(m_peer_address));
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_advertising_whitelist_reply(ble_gap_addr_t const * p_gap_addrs,
+                                         uint32_t               addr_cnt,
+                                         ble_gap_irk_t  const * p_gap_irks,
+                                         uint32_t               irk_cnt)
+{
+    if (!m_whitelist_reply_expected)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    m_whitelist_reply_expected = false;
+
+    #if (NRF_SD_BLE_API_VERSION <= 2)
+
+        m_whitelist.addr_count = addr_cnt;
+        m_whitelist.irk_count  = irk_cnt;
+
+        for (uint32_t i = 0; i < addr_cnt; i++)
+        {
+            *m_whitelist.pp_addrs[i] = p_gap_addrs[i];
+        }
+
+        for (uint32_t i = 0; i < irk_cnt; i++)
+        {
+            *m_whitelist.pp_irks[i] = p_gap_irks[i];
+        }
+
+    #else
+
+        m_whitelist_in_use = ((addr_cnt > 0) || (irk_cnt > 0));
+
+    #endif
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_advertising_restart_without_whitelist(void)
+{
+    uint32_t ret;
+
+    (void) sd_ble_gap_adv_stop();
+
+    m_whitelist_temporarily_disabled = true;
+
+    #if (NRF_SD_BLE_API_VERSION >= 3)
+        m_whitelist_in_use = false;
+    #endif
+
+    m_advdata.flags = BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE;
+
+    ret = ble_advdata_set(&m_advdata, NULL);
+    if (ret != NRF_SUCCESS)
+    {
+        return ret;
+    }
+
+    ret = ble_advertising_start(m_adv_mode_current);
+    if ((ret != NRF_SUCCESS) && (m_error_handler != NULL))
+    {
+        m_error_handler(ret);
+    }
+
+    return NRF_SUCCESS;
+}
+
+#endif // NRF_MODULE_ENABLED(BLE_ADVERTISING)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_advertising/ble_advertising.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,261 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**@file
+ *
+ * @defgroup ble_advertising Advertising Module
+ * @{
+ * @ingroup  ble_sdk_lib
+ * @brief    Module for handling connectable BLE advertising.
+ *
+ * @details  The Advertising Module handles connectable advertising for your application. It can
+ *           be configured with advertising modes to suit most typical use cases.
+ *           Your main application can react to changes in advertising modes
+ *           if an event handler is provided.
+ *
+ * @note     The Advertising Module supports only applications with a single peripheral link.
+ *
+ * The application must propagate BLE stack events to this module by calling
+ * @ref ble_advertising_on_ble_evt() and system events by calling
+ * @ref ble_advertising_on_sys_evt().
+ *
+ */
+
+#ifndef BLE_ADVERTISING_H__
+#define BLE_ADVERTISING_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+#include "headers/ble.h"
+#include "ble_gattc.h"
+#include "ble_advdata.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**@brief Advertising modes.
+*/
+typedef enum
+{
+    BLE_ADV_MODE_IDLE,          /**< Idle; no connectable advertising is ongoing. */
+    BLE_ADV_MODE_DIRECTED,      /**< Directed advertising attempts to connect to the most recently disconnected peer. */
+    BLE_ADV_MODE_DIRECTED_SLOW, /**< Directed advertising (low duty cycle) attempts to connect to the most recently disconnected peer. */
+    BLE_ADV_MODE_FAST,          /**< Fast advertising will connect to any peer device, or filter with a whitelist if one exists. */
+    BLE_ADV_MODE_SLOW,          /**< Slow advertising is similar to fast advertising. By default, it uses a longer advertising interval and time-out than fast advertising. However, these options are defined by the user. */
+} ble_adv_mode_t;
+
+/**@brief Advertising events.
+ *
+ * @details These events are propagated to the main application if a handler was provided during
+ *          initialization of the Advertising Module. Events for modes that are not used can be
+ *          ignored. Similarly, BLE_ADV_EVT_WHITELIST_REQUEST and BLE_ADV_EVT_PEER_ADDR_REQUEST
+ *          can be ignored if whitelist and direct advertising is not used.
+ */
+typedef enum
+{
+    BLE_ADV_EVT_IDLE,                /**< Idle; no connectable advertising is ongoing.*/
+    BLE_ADV_EVT_DIRECTED,            /**< Direct advertising mode has started. */
+    BLE_ADV_EVT_DIRECTED_SLOW,       /**< Directed advertising (low duty cycle) has started. */
+    BLE_ADV_EVT_FAST,                /**< Fast advertising mode has started. */
+    BLE_ADV_EVT_SLOW,                /**< Slow advertising mode has started. */
+    BLE_ADV_EVT_FAST_WHITELIST,      /**< Fast advertising mode using the whitelist has started. */
+    BLE_ADV_EVT_SLOW_WHITELIST,      /**< Slow advertising mode using the whitelist has started. */
+    BLE_ADV_EVT_WHITELIST_REQUEST,   /**< Request a whitelist from the main application. For whitelist advertising to work, the whitelist must be set when this event occurs. */
+    BLE_ADV_EVT_PEER_ADDR_REQUEST    /**< Request a peer address from the main application. For directed advertising to work, the peer address must be set when this event occurs. */
+} ble_adv_evt_t;
+
+
+/**@brief Options for the different advertisement modes.
+ *
+ * @details This structure is used to enable or disable advertising modes and to configure time-out
+ *          periods and advertising intervals.
+ */
+typedef struct
+{
+    bool     ble_adv_whitelist_enabled;       /**< Enable or disable use of the whitelist. */
+    bool     ble_adv_directed_enabled;        /**< Enable or disable direct advertising mode. */
+    bool     ble_adv_directed_slow_enabled;   /**< Enable or disable direct advertising mode. */
+    bool     ble_adv_fast_enabled;            /**< Enable or disable fast advertising mode. */
+    bool     ble_adv_slow_enabled;            /**< Enable or disable slow advertising mode. */
+    uint32_t ble_adv_directed_slow_interval;  /**< Advertising interval for directed advertising. */
+    uint32_t ble_adv_directed_slow_timeout;   /**< Time-out (number of tries) for direct advertising. */
+    uint32_t ble_adv_fast_interval;           /**< Advertising interval for fast advertising. */
+    uint32_t ble_adv_fast_timeout;            /**< Time-out (in seconds) for fast advertising. */
+    uint32_t ble_adv_slow_interval;           /**< Advertising interval for slow advertising. */
+    uint32_t ble_adv_slow_timeout;            /**< Time-out (in seconds) for slow advertising. */
+} ble_adv_modes_config_t;
+
+
+typedef struct
+{
+    uint32_t interval;
+    uint32_t timeout;
+    bool     enabled;
+} ble_adv_mode_config_t;
+
+
+/**@brief BLE advertising event handler type. */
+typedef void (*ble_advertising_evt_handler_t) (ble_adv_evt_t const adv_evt);
+
+/**@brief BLE advertising error handler type. */
+typedef void (*ble_advertising_error_handler_t) (uint32_t nrf_error);
+
+/**@brief Initialization parameters for the Advertising Module.
+ * @details This structure is used to pass advertising options, advertising data, and an event handler to the Advertising Module during initialization. */
+typedef struct
+{
+    ble_adv_modes_config_t        options;     /**< Parameters for advertising modes.*/
+    ble_advdata_t                 advdata;     /**< Advertising data. */
+    ble_advertising_evt_handler_t evt_handler; /**< Event handler. */
+} ble_adv_init_t;
+
+
+/**@brief Function for handling BLE events.
+ *
+ * @details This function must be called from the BLE stack event dispatcher for
+ *          the module to handle BLE events that are relevant for the Advertising Module.
+ *
+ * @param[in] p_ble_evt BLE stack event.
+ */
+void ble_advertising_on_ble_evt(const ble_evt_t * const p_ble_evt);
+
+
+/**@brief Function for handling system events.
+ *
+ * @details This function must be called to handle system events that are relevant
+ *          for the Advertising Module. Specifically, the advertising module can not use the
+ *          softdevice as long as there are pending writes to the flash memory. This
+ *          event handler is designed to delay advertising until there is no flash operation.
+ *
+ * @param[in] sys_evt  System event.
+ */
+void ble_advertising_on_sys_evt(uint32_t sys_evt);
+
+
+/**@brief Function for initializing the Advertising Module.
+ *
+ * @details Encodes the required advertising data and passes it to the stack.
+ *          Also builds a structure to be passed to the stack when starting advertising.
+ *          The supplied advertising data is copied to a local structure and is manipulated
+ *          depending on what advertising modes are started in @ref ble_advertising_start.
+ *
+ * @param[in] p_advdata     Advertising data: name, appearance, discovery flags, and more.
+ * @param[in] p_srdata      Scan response data: Supplement to advertising data.
+ * @param[in] p_config      Select which advertising modes and intervals will be utilized.
+ * @param[in] evt_handler   Event handler that will be called upon advertising events.
+ * @param[in] error_handler Error handler that will propogate internal errors to the main applications.
+ *
+ * @retval NRF_SUCCESS If initialization was successful. Otherwise, an error code is returned.
+ */
+uint32_t ble_advertising_init(ble_advdata_t                   const * p_advdata,
+                              ble_advdata_t                   const * p_srdata,
+                              ble_adv_modes_config_t          const * p_config,
+                              ble_advertising_evt_handler_t   const   evt_handler,
+                              ble_advertising_error_handler_t const   error_handler);
+
+
+/**@brief Function for starting advertising.
+ *
+ * @details You can start advertising in any of the advertising modes that you enabled
+ *          during initialization.
+ *
+ * @param[in] advertising_mode  Advertising mode.
+ *
+ * @retval @ref NRF_SUCCESS On success, else an error code indicating reason for failure.
+ * @retval @ref NRF_ERROR_INVALID_STATE If the module is not initialized.
+ */
+uint32_t ble_advertising_start(ble_adv_mode_t advertising_mode);
+
+
+/**@brief Function for setting the peer address.
+ *
+ * @details The peer address must be set by the application upon receiving a
+ *          @ref BLE_ADV_EVT_PEER_ADDR_REQUEST event. Without the peer address, the directed
+ *          advertising mode will not be run.
+ *
+ * @param[in] p_peer_addr  Pointer to a peer address.
+ *
+ * @retval @ref NRF_SUCCESS Successfully stored the peer address pointer in the advertising module.
+ * @retval @ref NRF_ERROR_INVALID_STATE If a reply was not expected.
+ */
+uint32_t ble_advertising_peer_addr_reply(ble_gap_addr_t * p_peer_addr);
+
+
+/**@brief Function for setting a whitelist.
+ *
+ * @details The whitelist must be set by the application upon receiving a
+ *          @ref BLE_ADV_EVT_WHITELIST_REQUEST event. Without the whitelist, the whitelist
+ *          advertising for fast and slow modes will not be run.
+ *
+ * @param[in] p_gap_addrs   The list of GAP addresses to whitelist.
+ * @param[in] addr_cnt      The number of GAP addresses to whitelist.
+ * @param[in] p_gap_irks    The list of peer IRK to whitelist.
+ * @param[in] irk_cnt       The number of peer IRK to whitelist.
+ *
+ * @retval @ref NRF_SUCCESS                 If the operation was successful.
+ * @retval @ref NRF_ERROR_INVALID_STATE     If a call to this function was made without a
+ *                                          BLE_ADV_EVT_WHITELIST_REQUEST event being received.
+ */
+uint32_t ble_advertising_whitelist_reply(ble_gap_addr_t const * p_gap_addrs,
+                                         uint32_t               addr_cnt,
+                                         ble_gap_irk_t  const * p_gap_irks,
+                                         uint32_t               irk_cnt);
+
+
+/**@brief Function for disabling whitelist advertising.
+ *
+ * @details This function temporarily disables whitelist advertising.
+ *          Calling this function resets the current time-out countdown.
+ *
+ * @retval @ref NRF_SUCCESS On success, else an error message propogated from the Softdevice.
+ */
+uint32_t ble_advertising_restart_without_whitelist(void);
+
+/** @} */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // BLE_ADVERTISING_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_db_discovery/ble_db_discovery.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,989 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(BLE_DB_DISCOVERY)
+#include "ble_db_discovery.h"
+#include <stdlib.h>
+#include "headers\ble.h"
+#include "ble_srv_common.h"
+#define NRF_LOG_MODULE_NAME "BLE_DB_DISC"
+#include "nrf_log.h"
+
+#define SRV_DISC_START_HANDLE  0x0001                    /**< The start handle value used during service discovery. */
+#define DB_DISCOVERY_MAX_USERS BLE_DB_DISCOVERY_MAX_SRV  /**< The maximum number of users/registrations allowed by this module. */
+#define MODULE_INITIALIZED (m_initialized == true)       /**< Macro designating whether the module has been initialized properly. */
+
+
+/**@brief Array of structures containing information about the registered application modules. */
+static ble_uuid_t m_registered_handlers[DB_DISCOVERY_MAX_USERS];
+
+
+/**@brief   Array of structures containing pending events to be sent to the application modules.
+ *
+ * @details Whenever a discovery related event is to be raised to a user module, it will be stored
+ *          in this array first. When all services needed to be discovered have been
+ *          discovered, all pending events will be sent to the corresponding user modules.
+ **/
+static struct
+{
+    ble_db_discovery_evt_t         evt;          /**< The pending event. */
+    ble_db_discovery_evt_handler_t evt_handler;  /**< The event handler which should be called to raise this event. */
+} m_pending_user_evts[DB_DISCOVERY_MAX_USERS];
+
+static ble_db_discovery_evt_handler_t m_evt_handler;
+static uint32_t m_pending_usr_evt_index;    /**< The index to the pending user event array, pointing to the last added pending user event. */
+static uint32_t m_num_of_handlers_reg;      /**< The number of handlers registered with the DB Discovery module. */
+static bool     m_initialized = false;      /**< This variable Indicates if the module is initialized or not. */
+
+/**@brief     Function for fetching the event handler provided by a registered application module.
+ *
+ * @param[in] srv_uuid UUID of the service.
+ *
+ * @retval    evt_handler Event handler of the module, registered for the given service UUID.
+ * @retval    NULL If no event handler is found.
+ */
+static ble_db_discovery_evt_handler_t registered_handler_get(const ble_uuid_t * const p_srv_uuid)
+{
+    uint32_t i;
+
+    for (i = 0; i < m_num_of_handlers_reg; i++)
+    {
+        if (BLE_UUID_EQ(&(m_registered_handlers[i]), p_srv_uuid))
+        {
+            return (m_evt_handler);
+        }
+    }
+
+    return NULL;
+}
+
+
+/**@brief     Function for storing the event handler provided by a registered application module.
+ *
+ * @param[in] p_srv_uuid    The UUID of the service.
+ * @param[in] p_evt_handler The event handler provided by the application.
+ *
+ * @retval    NRF_SUCCESS If the handler was stored or already present in the list.
+ * @retval    NRF_ERROR_NO_MEM If there is no space left to store the handler.
+ */
+static uint32_t registered_handler_set(const ble_uuid_t * const       p_srv_uuid,
+                                       ble_db_discovery_evt_handler_t p_evt_handler)
+{
+    if (registered_handler_get(p_srv_uuid) != NULL)
+    {
+        return NRF_SUCCESS;
+    }
+    if (m_num_of_handlers_reg < DB_DISCOVERY_MAX_USERS)
+    {
+        m_registered_handlers[m_num_of_handlers_reg] = *p_srv_uuid;
+
+        m_num_of_handlers_reg++;
+
+        return NRF_SUCCESS;
+    }
+    else
+    {
+        return NRF_ERROR_NO_MEM;
+    }
+}
+
+
+/**@brief Function for sending all pending discovery events to the corresponding user modules.
+ */
+static void pending_user_evts_send(void)
+{
+    uint32_t i = 0;
+
+    for (i = 0; i < m_num_of_handlers_reg; i++)
+    {
+        // Pass the event to the corresponding event handler.
+        m_pending_user_evts[i].evt_handler(&(m_pending_user_evts[i].evt));
+    }
+    m_pending_usr_evt_index = 0;
+}
+
+
+/**@brief     Function for indicating error to the application.
+ *
+ * @details   This function will fetch the event handler based on the UUID of the service being
+ *            discovered. (The event handler is registered by the application beforehand).
+ *            The error code is added to the pending events together with the event handler.
+ *            If no event handler was found, then this function will do nothing.
+ *
+ * @param[in] p_db_discovery Pointer to the DB discovery structure.
+ * @param[in] err_code       Error code that should be provided to the application.
+ * @param[in] conn_handle    Connection Handle.
+ *
+ */
+static void discovery_error_evt_trigger(ble_db_discovery_t * const p_db_discovery,
+                                        uint32_t                   err_code,
+                                        uint16_t const             conn_handle)
+{
+    ble_db_discovery_evt_handler_t p_evt_handler;
+    ble_gatt_db_srv_t            * p_srv_being_discovered;
+
+    p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+    p_evt_handler = registered_handler_get(&(p_srv_being_discovered->srv_uuid));
+
+    if (p_evt_handler != NULL)
+    {
+        ble_db_discovery_evt_t evt;
+
+        evt.conn_handle     = conn_handle;
+        evt.evt_type        = BLE_DB_DISCOVERY_ERROR;
+        evt.params.err_code = err_code;
+
+        p_evt_handler(&evt);
+    }
+}
+
+
+/**@brief     Function for triggering a Discovery Complete or Service Not Found event to the
+ *            application.
+ *
+ * @details   This function will fetch the event handler based on the UUID of the service being
+ *            discovered. (The event handler is registered by the application beforehand).
+ *            It then triggers an event indicating the completion of the service discovery.
+ *            If no event handler was found, then this function will do nothing.
+ *
+ * @param[in] p_db_discovery Pointer to the DB discovery structure.
+ * @param[in] is_srv_found   Variable to indicate if the service was found at the peer.
+ * @param[in] conn_handle    Connection Handle.
+ */
+static void discovery_complete_evt_trigger(ble_db_discovery_t * const p_db_discovery,
+                                           bool                       is_srv_found,
+                                           uint16_t const             conn_handle)
+{
+    ble_db_discovery_evt_handler_t p_evt_handler;
+    ble_gatt_db_srv_t            * p_srv_being_discovered;
+
+    p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+    p_evt_handler = registered_handler_get(&(p_srv_being_discovered->srv_uuid));
+
+    if (p_evt_handler != NULL)
+    {
+        if (m_pending_usr_evt_index < DB_DISCOVERY_MAX_USERS)
+        {
+            // Insert an event into the pending event list.
+            m_pending_user_evts[m_pending_usr_evt_index].evt.conn_handle = conn_handle;
+
+            m_pending_user_evts[m_pending_usr_evt_index].evt.params.discovered_db =
+                *p_srv_being_discovered;
+            if (is_srv_found)
+            {
+                m_pending_user_evts[m_pending_usr_evt_index].evt.evt_type =
+                    BLE_DB_DISCOVERY_COMPLETE;
+            }
+            else
+            {
+                m_pending_user_evts[m_pending_usr_evt_index].evt.evt_type =
+                    BLE_DB_DISCOVERY_SRV_NOT_FOUND;
+            }
+            m_pending_user_evts[m_pending_usr_evt_index].evt_handler = p_evt_handler;
+
+            m_pending_usr_evt_index++;
+
+            if (m_pending_usr_evt_index == m_num_of_handlers_reg)
+            {
+                // All registered modules have pending events. Send all pending events to the user
+                // modules.
+                pending_user_evts_send();
+            }
+            else
+            {
+                // Too many events pending. Do nothing. (Ideally this should not happen.)
+            }
+        }
+    }
+}
+
+
+/**@brief     Function for handling service discovery completion.
+ *
+ * @details   This function will be used to determine if there are more services to be discovered,
+ *            and if so, initiate the discovery of the next service.
+ *
+ * @param[in] p_db_discovery Pointer to the DB Discovery Structure.
+ * @param[in] conn_handle    Connection Handle.
+ */
+static void on_srv_disc_completion(ble_db_discovery_t * p_db_discovery,
+                                   uint16_t const       conn_handle)
+{
+    p_db_discovery->discoveries_count++;
+
+    // Check if more services need to be discovered.
+    if (p_db_discovery->discoveries_count < m_num_of_handlers_reg)
+    {
+        // Reset the current characteristic index since a new service discovery is about to start.
+        p_db_discovery->curr_char_ind = 0;
+
+        // Initiate discovery of the next service.
+        p_db_discovery->curr_srv_ind++;
+
+        ble_gatt_db_srv_t * p_srv_being_discovered;
+
+        p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+        p_srv_being_discovered->srv_uuid = m_registered_handlers[p_db_discovery->curr_srv_ind];
+
+        // Reset the characteristic count in the current service to zero since a new service
+        // discovery is about to start.
+        p_srv_being_discovered->char_count = 0;
+
+        NRF_LOG_INFO("Starting discovery of service with UUID 0x%x for Connection handle %d\r\n",
+               p_srv_being_discovered->srv_uuid.uuid, conn_handle);
+
+        uint32_t err_code;
+
+        err_code = sd_ble_gattc_primary_services_discover
+                   (
+                   conn_handle,
+                   SRV_DISC_START_HANDLE,
+                   &(p_srv_being_discovered->srv_uuid)
+                   );
+        if (err_code != NRF_SUCCESS)
+        {
+            p_db_discovery->discovery_in_progress = false;
+
+            // Error with discovering the service.
+            // Indicate the error to the registered user application.
+            discovery_error_evt_trigger(p_db_discovery, err_code, conn_handle);
+
+            m_pending_user_evts[0].evt.evt_type    = BLE_DB_DISCOVERY_AVAILABLE;
+            m_pending_user_evts[0].evt.conn_handle = conn_handle;
+//            m_evt_handler(&m_pending_user_evts[0].evt);
+
+            return;
+        }
+    }
+    else
+    {
+        // No more service discovery is needed.
+        p_db_discovery->discovery_in_progress  = false;
+        m_pending_user_evts[0].evt.evt_type    = BLE_DB_DISCOVERY_AVAILABLE;
+        m_pending_user_evts[0].evt.conn_handle = conn_handle;
+        //m_evt_handler(&m_pending_user_evts[0].evt);
+    }
+}
+
+
+/**@brief     Function for finding out if a characteristic discovery should be performed after the
+ *            last discovered characteristic.
+ *
+ * @details   This function is used during the time of database discovery to find out if there is
+ *            a need to do more characteristic discoveries. The value handles of the
+ *            last discovered characteristic is compared with the end handle of the service.
+ *            If the service handle is greater than one of the former characteristic handles,
+ *            it means that a characteristic discovery is required.
+ *
+ * @param[in] p_db_discovery The pointer to the DB Discovery structure.
+ * @param[in] p_after_char   The pointer to the last discovered characteristic.
+ *
+ * @retval    True if a characteristic discovery is required.
+ * @retval    False if a characteristic discovery is NOT required.
+ */
+static bool is_char_discovery_reqd(ble_db_discovery_t * const p_db_discovery,
+                                   ble_gattc_char_t         * p_after_char)
+{
+    if (
+        p_after_char->handle_value <
+        p_db_discovery->services[p_db_discovery->curr_srv_ind].handle_range.end_handle
+       )
+    {
+        // Handle value of the characteristic being discovered is less than the end handle of
+        // the service being discovered. There is a possibility of more characteristics being
+        // present. Hence a characteristic discovery is required.
+        return true;
+    }
+
+    return false;
+}
+
+
+/**@brief      Function to find out if a descriptor discovery is required.
+ *
+ * @details    This function finds out if there is a possibility of existence of descriptors between
+ *             current characteristic and the next characteristic. If so, this function will compute
+ *             the handle range on which the descriptors may be present and will return it.
+ *             If the current characteristic is the last known characteristic, then this function
+ *             will use the service end handle to find out if the current characteristic can have
+ *             descriptors.
+ *
+ * @param[in]  p_db_discovery Pointer to the DB Discovery structure.
+ * @param[in]  p_curr_char    Pointer to the current characteristic.
+ * @param[in]  p_next_char    Pointer to the next characteristic. This should be NULL if the
+ *                            caller knows that there is no characteristic after the current
+ *                            characteristic at the peer.
+ * @param[out] p_handle_range Pointer to the handle range in which descriptors may exist at the
+ *                            the peer.
+ *
+ * @retval     True If a descriptor discovery is required.
+ * @retval     False If a descriptor discovery is NOT required.
+ */
+static bool is_desc_discovery_reqd(ble_db_discovery_t       * p_db_discovery,
+                                   ble_gatt_db_char_t       * p_curr_char,
+                                   ble_gatt_db_char_t       * p_next_char,
+                                   ble_gattc_handle_range_t * p_handle_range)
+{
+    if (p_next_char == NULL)
+    {
+        // Current characteristic is the last characteristic in the service. Check if the value
+        // handle of the current characteristic is equal to the service end handle.
+        if (
+            p_curr_char->characteristic.handle_value ==
+            p_db_discovery->services[p_db_discovery->curr_srv_ind].handle_range.end_handle
+           )
+        {
+            // No descriptors can be present for the current characteristic. p_curr_char is the last
+            // characteristic with no descriptors.
+            return false;
+        }
+
+        p_handle_range->start_handle = p_curr_char->characteristic.handle_value + 1;
+
+        // Since the current characteristic is the last characteristic in the service, the end
+        // handle should be the end handle of the service.
+        p_handle_range->end_handle =
+            p_db_discovery->services[p_db_discovery->curr_srv_ind].handle_range.end_handle;
+
+        return true;
+    }
+
+    // p_next_char != NULL. Check for existence of descriptors between the current and the next
+    // characteristic.
+    if ((p_curr_char->characteristic.handle_value + 1) == p_next_char->characteristic.handle_decl)
+    {
+        // No descriptors can exist between the two characteristic.
+        return false;
+    }
+
+    p_handle_range->start_handle = p_curr_char->characteristic.handle_value + 1;
+    p_handle_range->end_handle   = p_next_char->characteristic.handle_decl - 1;
+
+    return true;
+}
+
+
+/**@brief     Function for performing characteristic discovery.
+ *
+ * @param[in] p_db_discovery Pointer to the DB Discovery structure.
+ * @param[in] conn_handle    Connection Handle.
+ *
+ * @return    NRF_SUCCESS if the SoftDevice was successfully requested to perform the characteristic
+ *            discovery. Otherwise an error code. This function returns the error code returned
+ *            by the SoftDevice API @ref sd_ble_gattc_characteristics_discover.
+ */
+static uint32_t characteristics_discover(ble_db_discovery_t * const p_db_discovery,
+                                         uint16_t const             conn_handle)
+{
+    ble_gatt_db_srv_t      * p_srv_being_discovered;
+    ble_gattc_handle_range_t handle_range;
+
+    p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+    if (p_db_discovery->curr_char_ind != 0)
+    {
+        // This is not the first characteristic being discovered. Hence the 'start handle' to be
+        // used must be computed using the handle_value of the previous characteristic.
+        ble_gattc_char_t * p_prev_char;
+        uint8_t            prev_char_ind = p_db_discovery->curr_char_ind - 1;
+
+        p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+        p_prev_char = &(p_srv_being_discovered->charateristics[prev_char_ind].characteristic);
+
+        handle_range.start_handle = p_prev_char->handle_value + 1;
+    }
+    else
+    {
+        // This is the first characteristic of this service being discovered.
+        handle_range.start_handle = p_srv_being_discovered->handle_range.start_handle;
+    }
+
+    handle_range.end_handle = p_srv_being_discovered->handle_range.end_handle;
+
+    return sd_ble_gattc_characteristics_discover(conn_handle, &handle_range);
+}
+
+
+/**@brief      Function for performing descriptor discovery, if required.
+ *
+ * @details    This function will check if descriptor discovery is required and then perform it if
+ *             needed. If no more descriptor discovery is required for the service, then the output
+ *             parameter p_raise_discov_complete is set to true, indicating to the caller that a
+ *             discovery complete event can be triggered to the application.
+ *
+ * @param[in]  p_db_discovery           Pointer to the DB Discovery structure.
+ * @param[out] p_raise_discov_complete  The value pointed to by this pointer will be set to true if
+ *                                      the Discovery Complete event can be triggered to the
+ *                                      application.
+ * @param[in] conn_handle               Connection Handle.
+ *
+ * @return     NRF_SUCCESS if the SoftDevice was successfully requested to perform the descriptor
+ *             discovery, or if no more descriptor discovery is required. Otherwise an error code.
+ *             This function returns the error code returned by the SoftDevice API @ref
+ *             sd_ble_gattc_descriptors_discover.
+ */
+static uint32_t descriptors_discover(ble_db_discovery_t * const p_db_discovery,
+                                     bool *                     p_raise_discov_complete,
+                                     uint16_t const             conn_handle)
+{
+    ble_gattc_handle_range_t   handle_range;
+    ble_gatt_db_char_t       * p_curr_char_being_discovered;
+    ble_gatt_db_srv_t        * p_srv_being_discovered;
+    bool                       is_discovery_reqd = false;
+
+    p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+    p_curr_char_being_discovered =
+        &(p_srv_being_discovered->charateristics[p_db_discovery->curr_char_ind]);
+
+    if ((p_db_discovery->curr_char_ind + 1) == p_srv_being_discovered->char_count)
+    {
+        // This is the last characteristic of this service.
+        is_discovery_reqd = is_desc_discovery_reqd(p_db_discovery,
+                                                   p_curr_char_being_discovered,
+                                                   NULL,
+                                                   &handle_range);
+    }
+    else
+    {
+        uint8_t                   i;
+        ble_gatt_db_char_t * p_next_char;
+
+        for (i = p_db_discovery->curr_char_ind;
+             i < p_srv_being_discovered->char_count;
+             i++)
+        {
+
+            if (i == (p_srv_being_discovered->char_count - 1))
+            {
+                // The current characteristic is the last characteristic in the service.
+                p_next_char = NULL;
+            }
+            else
+            {
+                p_next_char = &(p_srv_being_discovered->charateristics[i + 1]);
+            }
+
+            // Check if it is possible for the current characteristic to have a descriptor.
+            if (is_desc_discovery_reqd(p_db_discovery,
+                                       p_curr_char_being_discovered,
+                                       p_next_char,
+                                       &handle_range))
+            {
+                is_discovery_reqd = true;
+                break;
+            }
+            else
+            {
+                // No descriptors can exist.
+                p_curr_char_being_discovered = p_next_char;
+                p_db_discovery->curr_char_ind++;
+            }
+        }
+    }
+
+    if (!is_discovery_reqd)
+    {
+        // No more descriptor discovery required. Discovery is complete.
+        // This informs the caller that a discovery complete event can be triggered.
+        *p_raise_discov_complete = true;
+
+        return NRF_SUCCESS;
+    }
+
+    *p_raise_discov_complete = false;
+
+    return sd_ble_gattc_descriptors_discover(conn_handle, &handle_range);
+}
+
+
+/**@brief     Function for handling primary service discovery response.
+ *
+ * @details   This function will handle the primary service discovery response and start the
+ *            discovery of characteristics within that service.
+ *
+ * @param[in] p_db_discovery    Pointer to the DB Discovery structure.
+ * @param[in] p_ble_gattc_evt   Pointer to the GATT Client event.
+ */
+static void on_primary_srv_discovery_rsp(ble_db_discovery_t * const    p_db_discovery,
+                                         const ble_gattc_evt_t * const p_ble_gattc_evt)
+{
+    ble_gatt_db_srv_t                        * p_srv_being_discovered;
+    p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+    if (p_ble_gattc_evt->conn_handle != p_db_discovery->conn_handle)
+    {
+        return;
+    }
+    if (p_ble_gattc_evt->gatt_status == BLE_GATT_STATUS_SUCCESS)
+    {
+        uint32_t err_code;
+        const ble_gattc_evt_prim_srvc_disc_rsp_t * p_prim_srvc_disc_rsp_evt;
+
+        NRF_LOG_INFO("Found service UUID 0x%x\r\n", p_srv_being_discovered->srv_uuid.uuid);
+
+        p_prim_srvc_disc_rsp_evt = &(p_ble_gattc_evt->params.prim_srvc_disc_rsp);
+
+        p_srv_being_discovered->srv_uuid     = p_prim_srvc_disc_rsp_evt->services[0].uuid;
+        p_srv_being_discovered->handle_range = p_prim_srvc_disc_rsp_evt->services[0].handle_range;
+
+        err_code = characteristics_discover(p_db_discovery,
+                                            p_ble_gattc_evt->conn_handle);
+
+        if (err_code != NRF_SUCCESS)
+        {
+            p_db_discovery->discovery_in_progress = false;
+
+            // Error with discovering the service.
+            // Indicate the error to the registered user application.
+            discovery_error_evt_trigger(p_db_discovery,
+                                        err_code,
+                                        p_ble_gattc_evt->conn_handle);
+
+            m_pending_user_evts[0].evt.evt_type    = BLE_DB_DISCOVERY_AVAILABLE;
+            m_pending_user_evts[0].evt.conn_handle = p_ble_gattc_evt->conn_handle;
+            //m_evt_handler(&m_pending_user_evts[0].evt);
+        }
+    }
+    else
+    {
+        NRF_LOG_INFO("Service UUID 0x%x Not found\r\n", p_srv_being_discovered->srv_uuid.uuid);
+        // Trigger Service Not Found event to the application.
+        discovery_complete_evt_trigger(p_db_discovery,
+                                       false,
+                                       p_ble_gattc_evt->conn_handle);
+
+        on_srv_disc_completion(p_db_discovery,
+                               p_ble_gattc_evt->conn_handle);
+    }
+}
+
+
+/**@brief     Function for handling characteristic discovery response.
+ *
+ * @param[in] p_db_discovery    Pointer to the DB Discovery structure.
+ * @param[in] p_ble_gattc_evt   Pointer to the GATT Client event.
+ */
+static void on_characteristic_discovery_rsp(ble_db_discovery_t * const    p_db_discovery,
+                             const ble_gattc_evt_t * const                p_ble_gattc_evt)
+{
+    uint32_t                 err_code;
+    ble_gatt_db_srv_t      * p_srv_being_discovered;
+    bool                     perform_desc_discov = false;
+
+    if (p_ble_gattc_evt->conn_handle != p_db_discovery->conn_handle)
+    {
+        return;
+    }
+    p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+    if (p_ble_gattc_evt->gatt_status == BLE_GATT_STATUS_SUCCESS)
+    {
+        const ble_gattc_evt_char_disc_rsp_t * p_char_disc_rsp_evt;
+
+        p_char_disc_rsp_evt = &(p_ble_gattc_evt->params.char_disc_rsp);
+
+        // Find out the number of characteristics that were previously discovered (in earlier
+        // characteristic discovery responses, if any).
+        uint8_t num_chars_prev_disc = p_srv_being_discovered->char_count;
+
+        // Find out the number of characteristics that are currently discovered (in the
+        // characteristic discovery response being handled).
+        uint8_t num_chars_curr_disc = p_char_disc_rsp_evt->count;
+
+        // Check if the total number of discovered characteristics are supported by this module.
+        if ((num_chars_prev_disc + num_chars_curr_disc) <= BLE_GATT_DB_MAX_CHARS)
+        {
+            // Update the characteristics count.
+            p_srv_being_discovered->char_count += num_chars_curr_disc;
+        }
+        else
+        {
+            // The number of characteristics discovered at the peer is more than the supported
+            // maximum. This module will store only the characteristics found up to this point.
+            p_srv_being_discovered->char_count = BLE_GATT_DB_MAX_CHARS;
+        }
+
+        uint32_t i;
+        uint32_t j;
+
+        for (i = num_chars_prev_disc, j = 0; i < p_srv_being_discovered->char_count; i++, j++)
+        {
+            p_srv_being_discovered->charateristics[i].characteristic =
+                p_char_disc_rsp_evt->chars[j];
+
+            p_srv_being_discovered->charateristics[i].cccd_handle       = BLE_GATT_HANDLE_INVALID;
+            p_srv_being_discovered->charateristics[i].ext_prop_handle   = BLE_GATT_HANDLE_INVALID;
+            p_srv_being_discovered->charateristics[i].user_desc_handle  = BLE_GATT_HANDLE_INVALID;
+            p_srv_being_discovered->charateristics[i].report_ref_handle = BLE_GATT_HANDLE_INVALID;
+        }
+
+        ble_gattc_char_t * p_last_known_char;
+
+        p_last_known_char = &(p_srv_being_discovered->charateristics[i - 1].characteristic);
+
+        // If no more characteristic discovery is required, or if the maximum number of supported
+        // characteristic per service has been reached, descriptor discovery will be performed.
+        if (
+            !is_char_discovery_reqd(p_db_discovery, p_last_known_char) ||
+            (p_srv_being_discovered->char_count == BLE_GATT_DB_MAX_CHARS)
+           )
+        {
+            perform_desc_discov = true;
+        }
+        else
+        {
+            // Update the current characteristic index.
+            p_db_discovery->curr_char_ind = p_srv_being_discovered->char_count;
+
+            // Perform another round of characteristic discovery.
+            err_code = characteristics_discover(p_db_discovery,
+                                                p_ble_gattc_evt->conn_handle);
+
+            if (err_code != NRF_SUCCESS)
+            {
+                p_db_discovery->discovery_in_progress = false;
+
+                discovery_error_evt_trigger(p_db_discovery,
+                                            err_code,
+                                            p_ble_gattc_evt->conn_handle);
+
+                m_pending_user_evts[0].evt.evt_type    = BLE_DB_DISCOVERY_AVAILABLE;
+                m_pending_user_evts[0].evt.conn_handle = p_ble_gattc_evt->conn_handle;
+                //m_evt_handler(&m_pending_user_evts[0].evt);
+
+                return;
+            }
+        }
+    }
+    else
+    {
+        // The previous characteristic discovery resulted in no characteristics.
+        // descriptor discovery should be performed.
+        perform_desc_discov = true;
+    }
+
+    if (perform_desc_discov)
+    {
+        bool raise_discov_complete;
+
+        p_db_discovery->curr_char_ind = 0;
+
+        err_code = descriptors_discover(p_db_discovery,
+                                        &raise_discov_complete,
+                                        p_ble_gattc_evt->conn_handle);
+
+        if (err_code != NRF_SUCCESS)
+        {
+            p_db_discovery->discovery_in_progress = false;
+
+            discovery_error_evt_trigger(p_db_discovery,
+                                        err_code,
+                                        p_ble_gattc_evt->conn_handle);
+
+            m_pending_user_evts[0].evt.evt_type    = BLE_DB_DISCOVERY_AVAILABLE;
+            m_pending_user_evts[0].evt.conn_handle = p_ble_gattc_evt->conn_handle;
+            //m_evt_handler(&m_pending_user_evts[0].evt);
+
+            return;
+        }
+        if (raise_discov_complete)
+        {
+            // No more characteristics and descriptors need to be discovered. Discovery is complete.
+            // Send a discovery complete event to the user application.
+            NRF_LOG_INFO("Discovery of service with UUID 0x%x completed with success for Connection"
+                   " handle %d\r\n", p_srv_being_discovered->srv_uuid.uuid,
+                   p_ble_gattc_evt->conn_handle);
+
+            discovery_complete_evt_trigger(p_db_discovery,
+                                           true,
+                                           p_ble_gattc_evt->conn_handle);
+
+            on_srv_disc_completion(p_db_discovery,
+                                   p_ble_gattc_evt->conn_handle);
+        }
+    }
+}
+
+
+/**@brief     Function for handling descriptor discovery response.
+ *
+ * @param[in] p_db_discovery    Pointer to the DB Discovery structure.
+ * @param[in] p_ble_gattc_evt   Pointer to the GATT Client event.
+ */
+static void on_descriptor_discovery_rsp(ble_db_discovery_t * const    p_db_discovery,
+                                        const ble_gattc_evt_t * const p_ble_gattc_evt)
+{
+    const ble_gattc_evt_desc_disc_rsp_t * p_desc_disc_rsp_evt;
+    ble_gatt_db_srv_t                   * p_srv_being_discovered;
+
+    if (p_ble_gattc_evt->conn_handle != p_db_discovery->conn_handle)
+    {
+        return;
+    }
+
+    p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+    p_desc_disc_rsp_evt = &(p_ble_gattc_evt->params.desc_disc_rsp);
+
+    ble_gatt_db_char_t * p_char_being_discovered =
+        &(p_srv_being_discovered->charateristics[p_db_discovery->curr_char_ind]);
+
+    if (p_ble_gattc_evt->gatt_status == BLE_GATT_STATUS_SUCCESS)
+    {
+        // The descriptor was found at the peer.
+        // Iterate through and collect CCCD, Extended Properties,
+        // User Description & Report Reference descriptor handles.
+        for (uint32_t i = 0; i < p_desc_disc_rsp_evt->count; i++)
+        {
+            switch (p_desc_disc_rsp_evt->descs[i].uuid.uuid)
+            {
+                case BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG:
+                    p_char_being_discovered->cccd_handle =
+                        p_desc_disc_rsp_evt->descs[i].handle;
+                    break;
+
+                case BLE_UUID_DESCRIPTOR_CHAR_EXT_PROP:
+                    p_char_being_discovered->ext_prop_handle =
+                        p_desc_disc_rsp_evt->descs[i].handle;
+                    break;
+
+                case BLE_UUID_DESCRIPTOR_CHAR_USER_DESC:
+                    p_char_being_discovered->user_desc_handle =
+                        p_desc_disc_rsp_evt->descs[i].handle;
+                    break;
+
+                case BLE_UUID_REPORT_REF_DESCR:
+                    p_char_being_discovered->report_ref_handle =
+                        p_desc_disc_rsp_evt->descs[i].handle;
+                    break;
+            }
+
+            /* Break if we've found all the descriptors we are looking for. */
+            if (p_char_being_discovered->cccd_handle       != BLE_GATT_HANDLE_INVALID &&
+                p_char_being_discovered->ext_prop_handle   != BLE_GATT_HANDLE_INVALID &&
+                p_char_being_discovered->user_desc_handle  != BLE_GATT_HANDLE_INVALID &&
+                p_char_being_discovered->report_ref_handle != BLE_GATT_HANDLE_INVALID)
+            {
+                break;
+            }
+        }
+    }
+
+    bool raise_discov_complete = false;
+
+    if ((p_db_discovery->curr_char_ind + 1) == p_srv_being_discovered->char_count)
+    {
+        // No more characteristics and descriptors need to be discovered. Discovery is complete.
+        // Send a discovery complete event to the user application.
+
+        raise_discov_complete = true;
+    }
+    else
+    {
+        // Begin discovery of descriptors for the next characteristic.
+        uint32_t err_code;
+
+        p_db_discovery->curr_char_ind++;
+
+        err_code = descriptors_discover(p_db_discovery,
+                                        &raise_discov_complete,
+                                        p_ble_gattc_evt->conn_handle);
+
+        if (err_code != NRF_SUCCESS)
+        {
+            p_db_discovery->discovery_in_progress = false;
+
+            // Error with discovering the service.
+            // Indicate the error to the registered user application.
+            discovery_error_evt_trigger(p_db_discovery,
+                                        err_code,
+                                        p_ble_gattc_evt->conn_handle);
+
+            m_pending_user_evts[0].evt.evt_type    = BLE_DB_DISCOVERY_AVAILABLE;
+            m_pending_user_evts[0].evt.conn_handle = p_ble_gattc_evt->conn_handle;
+
+            return;
+        }
+    }
+
+    if (raise_discov_complete)
+    {
+        NRF_LOG_INFO("Discovery of service with UUID 0x%x completed with success for Connection"
+               " handle %d\r\n", p_srv_being_discovered->srv_uuid.uuid,
+               p_ble_gattc_evt->conn_handle);
+
+        discovery_complete_evt_trigger(p_db_discovery,
+                                       true,
+                                       p_ble_gattc_evt->conn_handle);
+
+        on_srv_disc_completion(p_db_discovery,
+                               p_ble_gattc_evt->conn_handle);
+    }
+}
+
+
+uint32_t ble_db_discovery_init(const ble_db_discovery_evt_handler_t evt_handler)
+{
+    uint32_t err_code = NRF_SUCCESS;
+    VERIFY_PARAM_NOT_NULL(evt_handler);
+
+    m_num_of_handlers_reg      = 0;
+    m_initialized              = true;
+    m_pending_usr_evt_index    = 0;
+    m_evt_handler              = evt_handler;
+
+    return err_code;
+
+}
+
+
+uint32_t ble_db_discovery_close()
+{
+    m_num_of_handlers_reg      = 0;
+    m_initialized              = false;
+    m_pending_usr_evt_index    = 0;
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_db_discovery_evt_register(const ble_uuid_t * const p_uuid)
+{
+    VERIFY_PARAM_NOT_NULL(p_uuid);
+    VERIFY_MODULE_INITIALIZED();
+
+    return registered_handler_set(p_uuid, m_evt_handler);
+}
+
+
+uint32_t ble_db_discovery_start(ble_db_discovery_t * const p_db_discovery,
+                                uint16_t                   conn_handle)
+{
+    VERIFY_PARAM_NOT_NULL(p_db_discovery);
+    VERIFY_MODULE_INITIALIZED();
+
+    if (m_num_of_handlers_reg == 0)
+    {
+        // No user modules were registered. There are no services to discover.
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    if (p_db_discovery->discovery_in_progress)
+    {
+        return NRF_ERROR_BUSY;
+    }
+
+    p_db_discovery->conn_handle = conn_handle;
+    ble_gatt_db_srv_t * p_srv_being_discovered;
+
+    m_pending_usr_evt_index   = 0;
+
+    p_db_discovery->discoveries_count = 0;
+    p_db_discovery->curr_srv_ind      = 0;
+    p_db_discovery->curr_char_ind     = 0;
+
+    p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+    p_srv_being_discovered->srv_uuid = m_registered_handlers[p_db_discovery->curr_srv_ind];
+
+    NRF_LOG_INFO("Starting discovery of service with UUID 0x%x for Connection handle %d\r\n",
+           p_srv_being_discovered->srv_uuid.uuid, conn_handle);
+
+    uint32_t err_code;
+
+    err_code = sd_ble_gattc_primary_services_discover(conn_handle,
+                                                      SRV_DISC_START_HANDLE,
+                                                      &(p_srv_being_discovered->srv_uuid));
+    VERIFY_SUCCESS(err_code);
+    p_db_discovery->discovery_in_progress = true;
+
+    return NRF_SUCCESS;
+}
+
+
+/**@brief     Function for handling disconnected event.
+ *
+ * @param[in] p_db_discovery    Pointer to the DB Discovery structure.
+ * @param[in] p_ble_gattc_evt   Pointer to the GAP event.
+ */
+static void on_disconnected(ble_db_discovery_t * const  p_db_discovery,
+                            const ble_gap_evt_t * const p_evt)
+{
+    if (p_evt->conn_handle == p_db_discovery->conn_handle)
+    {
+        p_db_discovery->discovery_in_progress = false;
+    }
+}
+
+
+void ble_db_discovery_on_ble_evt(ble_db_discovery_t * const p_db_discovery,
+                                 const ble_evt_t * const    p_ble_evt)
+{
+    VERIFY_PARAM_NOT_NULL_VOID(p_db_discovery);
+    VERIFY_PARAM_NOT_NULL_VOID(p_ble_evt);
+    VERIFY_MODULE_INITIALIZED_VOID();
+
+    switch (p_ble_evt->header.evt_id)
+    {
+        case BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP:
+            on_primary_srv_discovery_rsp(p_db_discovery, &(p_ble_evt->evt.gattc_evt));
+            break;
+
+        case BLE_GATTC_EVT_CHAR_DISC_RSP:
+            on_characteristic_discovery_rsp(p_db_discovery, &(p_ble_evt->evt.gattc_evt));
+            break;
+
+        case BLE_GATTC_EVT_DESC_DISC_RSP:
+            on_descriptor_discovery_rsp(p_db_discovery, &(p_ble_evt->evt.gattc_evt));
+            break;
+
+        case BLE_GAP_EVT_DISCONNECTED:
+            on_disconnected(p_db_discovery, &(p_ble_evt->evt.gap_evt));
+            break;
+
+        default:
+            break;
+    }
+}
+#endif // NRF_MODULE_ENABLED(BLE_DB_DISCOVERY)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_db_discovery/ble_db_discovery.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,216 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**@file
+ *
+ * @defgroup ble_db_discovery Database Discovery
+ * @{
+ * @ingroup  ble_sdk_lib
+ * @brief    Database discovery module.
+ *
+ * @details  This module contains the APIs and types exposed by the DB Discovery module. These APIs
+ *           and types can be used by the application to perform discovery of a service and its
+ *           characteristics at the peer server. This module can also be used to discover the
+ *           desired services in multiple remote devices.
+ *
+ * @warning  The maximum number of characteristics per service that can be discovered by this module
+ *           is determined by the number of characteristics in the service structure defined in
+ *           db_disc_config.h. If the peer has more than the supported number of characteristics, then
+ *           the first found will be discovered and any further characteristics will be ignored. Only the
+ *           following descriptors will be searched for at the peer: Client Characteristic Configuration,
+ *           Characteristic Extended Properties, Characteristic User Description, and Report Reference.
+ *
+ * @note     Presently only one instance of a Primary Service can be discovered by this module. If
+ *           there are multiple instances of the service at the peer, only the first instance
+ *           of it at the peer is fetched and returned to the application.
+ *
+ * @note     The application must propagate BLE stack events to this module by calling
+ *           ble_db_discovery_on_ble_evt().
+ *
+ */
+
+#ifndef BLE_DB_DISCOVERY_H__
+#define BLE_DB_DISCOVERY_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+#include "headers\ble.h"
+#include "ble_gattc.h"
+#include "ble_srv_common.h"
+#include "ble_gatt_db.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define BLE_DB_DISCOVERY_MAX_SRV          6  /**< Maximum number of services supported by this module. This also indicates the maximum number of users allowed to be registered to this module. (one user per service). */
+
+
+/**@brief   Type of the DB Discovery event.
+ */
+typedef enum
+{
+    BLE_DB_DISCOVERY_COMPLETE,      /**< Event indicating that the GATT Database discovery is complete. */
+    BLE_DB_DISCOVERY_ERROR,         /**< Event indicating that an internal error has occurred in the DB Discovery module. This could typically be because of the SoftDevice API returning an error code during the DB discover.*/
+    BLE_DB_DISCOVERY_SRV_NOT_FOUND, /**< Event indicating that the service was not found at the peer.*/
+    BLE_DB_DISCOVERY_AVAILABLE      /**< Event indicating that the DB discovery module is available.*/
+} ble_db_discovery_evt_type_t;
+
+
+
+/**@brief   Structure for holding the information related to the GATT database at the server.
+ *
+ * @details This module identifies a remote database. Use one instance of this structure per
+ *          connection.
+ *
+ * @warning This structure must be zero-initialized.
+ */
+typedef struct
+{
+    ble_gatt_db_srv_t   services[BLE_DB_DISCOVERY_MAX_SRV];  /**< Information related to the current service being discovered. This is intended for internal use during service discovery.*/
+    uint8_t             srv_count;                           /**< Number of services at the peers GATT database.*/
+    uint8_t             curr_char_ind;                       /**< Index of the current characteristic being discovered. This is intended for internal use during service discovery.*/
+    uint8_t             curr_srv_ind;                        /**< Index of the current service being discovered. This is intended for internal use during service discovery.*/
+    bool                discovery_in_progress;               /**< Variable to indicate if there is a service discovery in progress. */
+    uint8_t             discoveries_count;                   /**< Number of service discoveries made, both successful and unsuccessful. */
+    uint16_t            conn_handle;                         /**< Connection handle on which the discovery is started*/
+} ble_db_discovery_t;
+
+
+/**@brief   Structure containing the event from the DB discovery module to the application.
+ */
+typedef struct
+{
+    ble_db_discovery_evt_type_t evt_type;     /**< Type of event. */
+    uint16_t                    conn_handle;  /**< Handle of the connection for which this event has occurred. */
+    union
+    {
+        ble_gatt_db_srv_t discovered_db;  /**< Structure containing the information about the GATT Database at the server. This will be filled when the event type is @ref BLE_DB_DISCOVERY_COMPLETE.*/
+        uint32_t               err_code;       /**< nRF Error code indicating the type of error which occurred in the DB Discovery module. This will be filled when the event type is @ref BLE_DB_DISCOVERY_ERROR. */
+    } params;
+} ble_db_discovery_evt_t;
+
+
+/**@brief   DB Discovery event handler type. */
+typedef void (* ble_db_discovery_evt_handler_t)(ble_db_discovery_evt_t * p_evt);
+
+
+/**@brief     Function for initializing the DB Discovery module.
+ *
+ * @param[in] evt_handler        Event handler to be called by the DB discovery module when any event
+ *                               related to discovery of the registered service occurs.
+ *
+ * @retval  NRF_SUCCESS    On successful initialization.
+ * @retval  NRF_ERROR_NULL If the handler was NULL.
+ */
+uint32_t ble_db_discovery_init(ble_db_discovery_evt_handler_t evt_handler);
+
+
+/**@brief Function for closing the DB Discovery module.
+ *
+ * @details This function will clear up any internal variables and states maintained by the
+ *          module. To re-use the module after calling this function, the function @ref
+ *          ble_db_discovery_init must be called again.
+ *
+ * @retval  NRF_SUCCESS    Operation success.
+ */
+uint32_t ble_db_discovery_close(void);
+
+
+/**@brief Function for registering with the DB Discovery module.
+ *
+ * @details   The application can use this function to inform which service it is interested in
+ *            discovering at the server.
+ *
+ * @param[in] p_uuid             Pointer to the UUID of the service to be discovered at the server.
+ *
+ * @note      The total number of services that can be discovered by this module is @ref
+ *            BLE_DB_DISCOVERY_MAX_SRV. This effectively means that the maximum number of
+ *            registrations possible is equal to the @ref BLE_DB_DISCOVERY_MAX_SRV.
+ *
+ * @retval    NRF_SUCCESS               Operation success.
+ * @retval    NRF_ERROR_NULL            When a NULL pointer is passed as input.
+ * @retval    NRF_ERROR_INVALID_STATE   If this function is called without calling the
+ *                                      @ref ble_db_discovery_init.
+ * @retval    NRF_ERROR_NO_MEM          The maximum number of registrations allowed by this module
+ *                                      has been reached.
+ */
+uint32_t ble_db_discovery_evt_register(const ble_uuid_t * const             p_uuid);
+
+
+/**@brief Function for starting the discovery of the GATT database at the server.
+ *
+ * @warning p_db_discovery structure must be zero-initialized.
+ *
+ * @param[out] p_db_discovery    Pointer to the DB Discovery structure.
+ * @param[in]  conn_handle       The handle of the connection for which the discovery should be
+ *                               started.
+ *
+ * @retval    NRF_SUCCESS               Operation success.
+ * @retval    NRF_ERROR_NULL            When a NULL pointer is passed as input.
+ * @retval    NRF_ERROR_INVALID_STATE   If this function is called without calling the
+ *                                      @ref ble_db_discovery_init, or without calling
+ *                                      @ref ble_db_discovery_evt_register.
+ * @retval    NRF_ERROR_BUSY            If a discovery is already in progress for the current
+ *                                      connection.
+ *
+ * @return                              This API propagates the error code returned by the
+ *                                      SoftDevice API @ref sd_ble_gattc_primary_services_discover.
+ */
+uint32_t ble_db_discovery_start(ble_db_discovery_t * const p_db_discovery,
+                                uint16_t                   conn_handle);
+
+
+/**@brief Function for handling the Application's BLE Stack events.
+ *
+ * @param[in,out] p_db_discovery Pointer to the DB Discovery structure.
+ * @param[in]     p_ble_evt      Pointer to the BLE event received.
+ */
+void ble_db_discovery_on_ble_evt(ble_db_discovery_t * const p_db_discovery,
+                                 const ble_evt_t * const    p_ble_evt);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // BLE_DB_DISCOVERY_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_debug_assert_handler/ble_debug_assert_handler.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,81 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "ble_debug_assert_handler.h"
+#include <string.h>
+#include "nrf.h"
+#include "ble_error_log.h"
+#include "nordic_common.h"
+
+#define MAX_LENGTH_FILENAME 128  /**< Max length of filename to copy for the debug error handlier. */
+
+
+// WARNING - DO NOT USE THIS FUNCTION IN END PRODUCT. - WARNING
+// WARNING -         FOR DEBUG PURPOSES ONLY.         - WARNING
+void ble_debug_assert_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name)
+{
+    // Copying parameters to static variables because parameters may not be accessible in debugger.
+    static volatile uint8_t  s_file_name[MAX_LENGTH_FILENAME];
+    static volatile uint16_t s_line_num;
+    static volatile uint32_t s_error_code;
+
+    strncpy((char *)s_file_name, (const char *)p_file_name, MAX_LENGTH_FILENAME - 1);
+    s_file_name[MAX_LENGTH_FILENAME - 1] = '\0';
+    s_line_num                           = line_num;
+    s_error_code                         = error_code;
+    UNUSED_VARIABLE(s_file_name);
+    UNUSED_VARIABLE(s_line_num);
+    UNUSED_VARIABLE(s_error_code);
+
+    // WARNING: The PRIMASK register is set to disable ALL interrups during writing the error log.
+    //
+    // Do not use __disable_irq() in normal operation.
+    __disable_irq();
+
+    // This function will write error code, filename, and line number to the flash.
+    // In addition, the Cortex-M0 stack memory will also be written to the flash.
+    //(void) ble_error_log_write(error_code, p_file_name, line_num);
+
+    // For debug purposes, this function never returns.
+    // Attach a debugger for tracing the error cause.
+    for (;;)
+    {
+        // Do nothing.
+    }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_debug_assert_handler/ble_debug_assert_handler.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,86 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup ble_debug_assert_handler Assert handler for debug purposes
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Module for handling of assert during application development when debugging.
+ *
+ * @details This module may be used during development of an application to facilitate debugging.
+ *          It contains a function to write file name, line number and the Stack Memory to flash.
+ *          This module is ONLY for debugging purposes and must never be used in final product.
+ *
+ */
+
+#ifndef BLE_DEBUG_ASSERT_HANDLER_H__
+#define BLE_DEBUG_ASSERT_HANDLER_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Function for handling the Debug assert, which can be called from an error handler.
+ *        To be used only for debugging purposes.
+ *
+ *@details This code will copy the filename and line number into local variables for them to always
+ *         be accessible in Keil debugger. The function will also write the ARM Cortex-M0 stack
+ *         memory into flash where it can be retrieved and manually un-winded in order to
+ *         back-trace the location where the error ocured.<br>
+ * @warning <b>ALL INTERRUPTS WILL BE DISABLED.</b>
+ *
+ * @note    This function will never return but loop forever for debug purposes.
+ *
+ * @param[in] error_code  Error code supplied to the handler.
+ * @param[in] line_num    Line number where the original handler is called.
+ * @param[in] p_file_name Pointer to the file name.
+ */
+void ble_debug_assert_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BLE_DEBUG_ASSERT_HANDLER_H__ */
+
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_dtm/ble_dtm.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,661 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(BLE_DTM)
+#include "ble_dtm.h"
+#include "ble_dtm_hw.h"
+#include <stdbool.h>
+#include <string.h>
+#include "nrf.h"
+
+#define DTM_HEADER_OFFSET        0                                         /**< Index where the header of the pdu is located. */
+#define DTM_HEADER_SIZE          2                                         /**< Size of PDU header. */
+#define DTM_PAYLOAD_MAX_SIZE     255                                       /**< Maximum payload size allowed during dtm execution. */
+#define DTM_LENGTH_OFFSET        (DTM_HEADER_OFFSET + 1)                   /**< Index where the length of the payload is encoded. */
+#define DTM_PDU_MAX_MEMORY_SIZE  (DTM_HEADER_SIZE + DTM_PAYLOAD_MAX_SIZE)  /**< Maximum PDU size allowed during dtm execution. */
+#define DTM_ON_AIR_OVERHEAD_SIZE 10                                        /**< Size of the packet on air without the payload (preamble + sync word + type + RFU + length + CRC). */
+
+#define RX_MODE          true   /**< Constant defining RX mode for radio during dtm test. */
+#define TX_MODE          false  /**< Constant defining TX mode for radio during dtm test. */
+
+#define PHYS_CH_MAX      39     /**< Maximum number of valid channels in BLE. */
+
+// Values that for now are "constants" - they could be configured by a function setting them,
+// but most of these are set by the BLE DTM standard, so changing them is not relevant.
+#define RFPHY_TEST_0X0F_REF_PATTERN  0x0f  /**<  RF-PHY test packet patterns, for the repeated octet packets. */
+#define RFPHY_TEST_0X55_REF_PATTERN  0x55  /**<  RF-PHY test packet patterns, for the repeated octet packets. */
+
+#define PRBS9_CONTENT  {0xFF, 0xC1, 0xFB, 0xE8, 0x4C, 0x90, 0x72, 0x8B,   \
+                        0xE7, 0xB3, 0x51, 0x89, 0x63, 0xAB, 0x23, 0x23,   \
+                        0x02, 0x84, 0x18, 0x72, 0xAA, 0x61, 0x2F, 0x3B,   \
+                        0x51, 0xA8, 0xE5, 0x37, 0x49, 0xFB, 0xC9, 0xCA,   \
+                        0x0C, 0x18, 0x53, 0x2C, 0xFD, 0x45, 0xE3, 0x9A,   \
+                        0xE6, 0xF1, 0x5D, 0xB0, 0xB6, 0x1B, 0xB4, 0xBE,   \
+                        0x2A, 0x50, 0xEA, 0xE9, 0x0E, 0x9C, 0x4B, 0x5E,   \
+                        0x57, 0x24, 0xCC, 0xA1, 0xB7, 0x59, 0xB8, 0x87,   \
+                        0xFF, 0xE0, 0x7D, 0x74, 0x26, 0x48, 0xB9, 0xC5,   \
+                        0xF3, 0xD9, 0xA8, 0xC4, 0xB1, 0xD5, 0x91, 0x11,   \
+                        0x01, 0x42, 0x0C, 0x39, 0xD5, 0xB0, 0x97, 0x9D,   \
+                        0x28, 0xD4, 0xF2, 0x9B, 0xA4, 0xFD, 0x64, 0x65,   \
+                        0x06, 0x8C, 0x29, 0x96, 0xFE, 0xA2, 0x71, 0x4D,   \
+                        0xF3, 0xF8, 0x2E, 0x58, 0xDB, 0x0D, 0x5A, 0x5F,   \
+                        0x15, 0x28, 0xF5, 0x74, 0x07, 0xCE, 0x25, 0xAF,   \
+                        0x2B, 0x12, 0xE6, 0xD0, 0xDB, 0x2C, 0xDC, 0xC3,   \
+                        0x7F, 0xF0, 0x3E, 0x3A, 0x13, 0xA4, 0xDC, 0xE2,   \
+                        0xF9, 0x6C, 0x54, 0xE2, 0xD8, 0xEA, 0xC8, 0x88,   \
+                        0x00, 0x21, 0x86, 0x9C, 0x6A, 0xD8, 0xCB, 0x4E,   \
+                        0x14, 0x6A, 0xF9, 0x4D, 0xD2, 0x7E, 0xB2, 0x32,   \
+                        0x03, 0xC6, 0x14, 0x4B, 0x7F, 0xD1, 0xB8, 0xA6,   \
+                        0x79, 0x7C, 0x17, 0xAC, 0xED, 0x06, 0xAD, 0xAF,   \
+                        0x0A, 0x94, 0x7A, 0xBA, 0x03, 0xE7, 0x92, 0xD7,   \
+                        0x15, 0x09, 0x73, 0xE8, 0x6D, 0x16, 0xEE, 0xE1,   \
+                        0x3F, 0x78, 0x1F, 0x9D, 0x09, 0x52, 0x6E, 0xF1,   \
+                        0x7C, 0x36, 0x2A, 0x71, 0x6C, 0x75, 0x64, 0x44,   \
+                        0x80, 0x10, 0x43, 0x4E, 0x35, 0xEC, 0x65, 0x27,   \
+                        0x0A, 0xB5, 0xFC, 0x26, 0x69, 0x3F, 0x59, 0x99,   \
+                        0x01, 0x63, 0x8A, 0xA5, 0xBF, 0x68, 0x5C, 0xD3,   \
+                        0x3C, 0xBE, 0x0B, 0xD6, 0x76, 0x83, 0xD6, 0x57,   \
+                        0x05, 0x4A, 0x3D, 0xDD, 0x81, 0x73, 0xC9, 0xEB,   \
+                        0x8A, 0x84, 0x39, 0xF4, 0x36, 0x0B, 0xF7}           /**< The PRBS9 sequence used as packet payload.
+                                                                                 The bytes in the sequence is in the right order, but the bits of each byte in the array is reverse.
+                                                                                 of that found by running the PRBS9 algorithm. This is because of the endianess of the nRF5 radio. */
+
+/**@brief Structure holding the PDU used for transmitting/receiving a PDU.
+ */
+typedef struct
+{
+    uint8_t content[DTM_HEADER_SIZE + DTM_PAYLOAD_MAX_SIZE];                 /**< PDU packet content. */
+} pdu_type_t;
+
+/**@brief States used for the DTM test implementation.
+ */
+typedef enum
+{
+    STATE_UNINITIALIZED,                                                     /**< The DTM is uninitialized. */
+    STATE_IDLE,                                                              /**< State when system has just initialized, or current test has completed. */
+    STATE_TRANSMITTER_TEST,                                                  /**< State used when a DTM Transmission test is running. */
+    STATE_CARRIER_TEST,                                                      /**< State used when a DTM Carrier test is running (Vendor specific test). */
+    STATE_RECEIVER_TEST                                                      /**< State used when a DTM Receive test is running. */
+} state_t;
+
+// Internal variables set as side effects of commands or events.
+static state_t           m_state = STATE_UNINITIALIZED;                      /**< Current machine state. */
+static uint16_t          m_rx_pkt_count;                                     /**< Number of valid packets received. */
+static pdu_type_t        m_pdu;                                              /**< PDU to be sent. */
+static uint16_t          m_event;                                            /**< current command status - initially "ok", may be set if error detected, or to packet count. */
+static bool              m_new_event;                                        /**< Command has been processed - number of not yet reported event bytes. */
+static uint32_t          m_packet_length;                                    /**< Payload length of transmitted PDU, bits 2:7 of 16-bit dtm command. */
+static dtm_pkt_type_t    m_packet_type;                                      /**< Bits 0..1 of 16-bit transmit command, or 0xFFFFFFFF. */
+static dtm_freq_t        m_phys_ch;                                          /**< 0..39 physical channel number (base 2402 MHz, Interval 2 MHz), bits 8:13 of 16-bit dtm command. */
+static uint32_t          m_current_time = 0;                                 /**< Counter for interrupts from timer to ensure that the 2 bytes forming a DTM command are received within the time window. */
+
+// Nordic specific configuration values (not defined by BLE standard).
+// Definition of initial values found in ble_dtm.h
+static int32_t           m_tx_power          = DEFAULT_TX_POWER;             /**< TX power for transmission test, default to maximum value (+4 dBm). */
+static NRF_TIMER_Type *  mp_timer            = DEFAULT_TIMER;                /**< Timer to be used. */
+static IRQn_Type         m_timer_irq         = DEFAULT_TIMER_IRQn;           /**< which interrupt line to clear on every timeout */
+
+static uint8_t const     m_prbs_content[]    = PRBS9_CONTENT;                /**< Pseudo-random bit sequence defined by the BLE standard. */
+static uint8_t           m_packetHeaderLFlen = 8;                            /**< Length of length field in packet Header (in bits). */
+static uint8_t           m_packetHeaderS0len = 1;                            /**< Length of S0 field in packet Header (in bytes). */
+static uint8_t           m_packetHeaderS1len = 0;                            /**< Length of S1 field in packet Header (in bits). */
+static uint8_t           m_crcConfSkipAddr   = 1;                            /**< Leave packet address field out of CRC calculation. */
+static uint8_t           m_static_length     = 0;                            /**< Number of bytes sent in addition to the var.length payload. */
+static uint32_t          m_balen             = 3;                            /**< Base address length in bytes. */
+static uint32_t          m_endian            = RADIO_PCNF1_ENDIAN_Little;    /**< On air endianess of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
+static uint32_t          m_whitening         = RADIO_PCNF1_WHITEEN_Disabled; /**< Whitening disabled. */
+static uint8_t           m_crcLength         = RADIO_CRCCNF_LEN_Three;       /**< CRC Length (in bytes). */
+static uint32_t          m_address           = 0x71764129;                   /**< Address. */
+static uint32_t          m_crc_poly          = 0x0000065B;                   /**< CRC polynomial. */
+static uint32_t          m_crc_init          = 0x00555555;                   /**< Initial value for CRC calculation. */
+static uint8_t           m_radio_mode        = RADIO_MODE_MODE_Ble_1Mbit;    /**< nRF51 specific radio mode value. */
+static uint32_t          m_txIntervaluS      = 2500;                          /**< Time between start of Tx packets (in uS). */
+
+
+/**@brief Function for verifying that a received PDU has the expected structure and content.
+ */
+static bool check_pdu(void)
+{
+    uint8_t        k;                // Byte pointer for running through PDU payload
+    uint8_t        pattern;          // Repeating octet value in payload
+    dtm_pkt_type_t pdu_packet_type;  // Note: PDU packet type is a 4-bit field in HCI, but 2 bits in BLE DTM
+    uint32_t       length = 0;
+
+    pdu_packet_type = (dtm_pkt_type_t)(m_pdu.content[DTM_HEADER_OFFSET] & 0x0F);
+    length          = m_pdu.content[DTM_LENGTH_OFFSET];
+
+    if ((pdu_packet_type > (dtm_pkt_type_t)PACKET_TYPE_MAX) || (length > DTM_PAYLOAD_MAX_SIZE))
+    {
+        return false;
+    }
+
+    if (pdu_packet_type == DTM_PKT_PRBS9)
+    {
+        // Payload does not consist of one repeated octet; must compare ir with entire block into
+        return (memcmp(m_pdu.content + DTM_HEADER_SIZE, m_prbs_content, length) == 0);
+    }
+
+    if (pdu_packet_type == DTM_PKT_0X0F)
+    {
+        pattern = RFPHY_TEST_0X0F_REF_PATTERN;
+    }
+    else
+    {
+        pattern = RFPHY_TEST_0X55_REF_PATTERN;
+    }
+
+    for (k = 0; k < length; k++)
+    {
+        // Check repeated pattern filling the PDU payload
+        if (m_pdu.content[k + 2] != pattern)
+        {
+            return false;
+        }
+    }
+    return true;
+}
+
+
+/**@brief Function for turning off the radio after a test.
+ *        Also called after test done, to be ready for next test.
+ */
+static void radio_reset(void)
+{
+    NRF_PPI->CHENCLR = PPI_CHENCLR_CH0_Msk | PPI_CHENCLR_CH1_Msk;
+
+    NRF_RADIO->SHORTS          = 0;
+    NRF_RADIO->EVENTS_DISABLED = 0;
+    NRF_RADIO->TASKS_DISABLE   = 1;
+
+    while (NRF_RADIO->EVENTS_DISABLED == 0)
+    {
+        // Do nothing
+    }
+
+    NRF_RADIO->EVENTS_DISABLED = 0;
+    NRF_RADIO->TASKS_RXEN      = 0;
+    NRF_RADIO->TASKS_TXEN      = 0;
+
+    m_rx_pkt_count = 0;
+}
+
+
+/**@brief Function for initializing the radio for DTM.
+ */
+static uint32_t radio_init(void)
+{
+    if(dtm_radio_validate(m_tx_power, m_radio_mode) != DTM_SUCCESS)
+    {
+        return DTM_ERROR_ILLEGAL_CONFIGURATION;
+    }
+
+    // Turn off radio before configuring it
+    radio_reset();
+
+    NRF_RADIO->TXPOWER = m_tx_power;
+    NRF_RADIO->MODE    = m_radio_mode << RADIO_MODE_MODE_Pos;
+
+    // Set the access address, address0/prefix0 used for both Rx and Tx address
+    NRF_RADIO->PREFIX0    &= ~RADIO_PREFIX0_AP0_Msk;
+    NRF_RADIO->PREFIX0    |= (m_address >> 24) & RADIO_PREFIX0_AP0_Msk;
+    NRF_RADIO->BASE0       = m_address << 8;
+    NRF_RADIO->RXADDRESSES = RADIO_RXADDRESSES_ADDR0_Enabled << RADIO_RXADDRESSES_ADDR0_Pos;
+    NRF_RADIO->TXADDRESS   = (0x00 << RADIO_TXADDRESS_TXADDRESS_Pos) & RADIO_TXADDRESS_TXADDRESS_Msk;
+
+    // Configure CRC calculation
+    NRF_RADIO->CRCCNF = (m_crcConfSkipAddr << RADIO_CRCCNF_SKIP_ADDR_Pos) |
+                        (m_crcLength << RADIO_CRCCNF_LEN_Pos);
+
+    NRF_RADIO->PCNF0 = (m_packetHeaderS1len << RADIO_PCNF0_S1LEN_Pos) |
+                       (m_packetHeaderS0len << RADIO_PCNF0_S0LEN_Pos) |
+                       (m_packetHeaderLFlen << RADIO_PCNF0_LFLEN_Pos);
+
+    NRF_RADIO->PCNF1 = (m_whitening          << RADIO_PCNF1_WHITEEN_Pos) |
+                       (m_endian             << RADIO_PCNF1_ENDIAN_Pos)  |
+                       (m_balen              << RADIO_PCNF1_BALEN_Pos)   |
+                       (m_static_length      << RADIO_PCNF1_STATLEN_Pos) |
+                       (DTM_PAYLOAD_MAX_SIZE << RADIO_PCNF1_MAXLEN_Pos);
+
+    return DTM_SUCCESS;
+}
+
+
+/**@brief Function for preparing the radio. At start of each test: Turn off RF, clear interrupt flags of RF, initialize the radio
+ *        at given RF channel.
+ *
+ *@param[in] rx     boolean indicating if radio should be prepared in rx mode (true) or tx mode.
+ */
+static void radio_prepare(bool rx)
+{
+    dtm_turn_off_test();
+    NRF_RADIO->CRCPOLY      = m_crc_poly;
+    NRF_RADIO->CRCINIT      = m_crc_init;
+    NRF_RADIO->FREQUENCY    = (m_phys_ch << 1) + 2;                  // Actual frequency (MHz): 2400 + register value
+    NRF_RADIO->PACKETPTR    = (uint32_t)&m_pdu;                      // Setting packet pointer will start the radio
+    NRF_RADIO->EVENTS_READY = 0;
+    NRF_RADIO->SHORTS       = (1 << RADIO_SHORTS_READY_START_Pos) |  // Shortcut between READY event and START task
+                              (1 << RADIO_SHORTS_END_DISABLE_Pos);   // Shortcut between END event and DISABLE task
+
+    if (rx)
+    {
+        NRF_RADIO->EVENTS_END = 0;
+        NRF_RADIO->TASKS_RXEN = 1;  // shorts will start radio in RX mode when it is ready
+    }
+    else // tx
+    {
+        NRF_RADIO->TXPOWER = m_tx_power;
+    }
+}
+
+
+/**@brief Function for terminating the ongoing test (if any) and closing down the radio.
+ */
+static void dtm_test_done(void)
+{
+    dtm_turn_off_test();
+    NRF_PPI->CHENCLR = 0x01;
+    NRF_PPI->CH[0].EEP = 0;     // Break connection from timer to radio to stop transmit loop
+    NRF_PPI->CH[0].TEP = 0;
+
+    radio_reset();
+    m_state = STATE_IDLE;
+}
+
+
+/**@brief Function for configuring the timer for 625us cycle time.
+ */
+static uint32_t timer_init(void)
+{
+    // Use 16MHz from external crystal
+    // This could be customized for RC/Xtal, or even to use a 32 kHz crystal
+    NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
+    NRF_CLOCK->TASKS_HFCLKSTART    = 1;
+
+    while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0)
+    {
+        // Do nothing while waiting for the clock to start
+    }
+
+    mp_timer->TASKS_STOP        = 1;                      // Stop timer, if it was running
+    mp_timer->TASKS_CLEAR       = 1;
+    mp_timer->MODE              = TIMER_MODE_MODE_Timer;  // Timer mode (not counter)
+    mp_timer->EVENTS_COMPARE[0] = 0;                      // clean up possible old events
+    mp_timer->EVENTS_COMPARE[1] = 0;
+    mp_timer->EVENTS_COMPARE[2] = 0;
+    mp_timer->EVENTS_COMPARE[3] = 0;
+
+    // Timer is polled, but enable the compare0 interrupt in order to wakeup from CPU sleep
+    mp_timer->INTENSET    = TIMER_INTENSET_COMPARE0_Msk;
+    mp_timer->SHORTS      = 1 << TIMER_SHORTS_COMPARE0_CLEAR_Pos;  // Clear the count every time timer reaches the CCREG0 count
+    mp_timer->PRESCALER   = 4;                                     // Input clock is 16MHz, timer clock = 2 ^ prescale -> interval 1us
+    mp_timer->CC[0]       = m_txIntervaluS;                        // 625uS with 1MHz clock to the timer
+    mp_timer->CC[1]       = UART_POLL_CYCLE;                       // Depends on the baud rate of the UART. Default baud rate of 19200 will result in a 260uS time with 1MHz clock to the timer
+    mp_timer->TASKS_START = 1;                                     // Start the timer - it will be running continuously
+    m_current_time        = 0;
+    return DTM_SUCCESS;
+}
+
+
+/**@brief Function for handling vendor specific commands.
+ *        Used when packet type is set to Vendor specific.
+ *        The length field is used for encoding vendor specific command.
+ *        The frequency field is used for encoding vendor specific options to the command.
+ *
+ * @param[in]   vendor_cmd      Vendor specific command to be executed.
+ * @param[in]   vendor_option   Vendor specific option to the vendor command.
+ *
+ * @return      DTM_SUCCESS or one of the DTM_ERROR_ values
+ */
+static uint32_t dtm_vendor_specific_pkt(uint32_t vendor_cmd, dtm_freq_t vendor_option)
+{
+    switch (vendor_cmd)
+    {
+        // nRFgo Studio uses CARRIER_TEST_STUDIO to indicate a continuous carrier without
+        // a modulated signal.
+        case CARRIER_TEST:
+        case CARRIER_TEST_STUDIO:
+            // Not a packet type, but used to indicate that a continuous carrier signal
+            // should be transmitted by the radio.
+            radio_prepare(TX_MODE);
+
+            dtm_constant_carrier();
+
+            // Shortcut between READY event and START task
+            NRF_RADIO->SHORTS = 1 << RADIO_SHORTS_READY_START_Pos;
+
+            // Shortcut will start radio in Tx mode when it is ready
+            NRF_RADIO->TASKS_TXEN = 1;
+            m_state               = STATE_CARRIER_TEST;
+            break;
+
+        case SET_TX_POWER:
+            if (!dtm_set_txpower(vendor_option))
+            {
+                return DTM_ERROR_ILLEGAL_CONFIGURATION;
+            }
+            break;
+
+        case SELECT_TIMER:
+            if (!dtm_set_timer(vendor_option))
+            {
+                return DTM_ERROR_ILLEGAL_CONFIGURATION;
+            }
+            break;
+    }
+    // Event code is unchanged, successful
+    return DTM_SUCCESS;
+}
+
+
+uint32_t dtm_init(void)
+{
+    if ((timer_init() != DTM_SUCCESS) || (radio_init() != DTM_SUCCESS))
+    {
+        return DTM_ERROR_ILLEGAL_CONFIGURATION;
+    }
+    m_new_event     = false;
+    m_state         = STATE_IDLE;
+    m_packet_length = 0;
+
+    // Enable wake-up on event
+    SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
+
+    return DTM_SUCCESS;
+}
+
+
+uint32_t dtm_wait(void)
+{
+    // Enable wake-up on event
+    SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
+
+    for (;;)
+    {
+        // Event may be the reception of a packet -
+        // handle radio first, to give it highest priority:
+        if (NRF_RADIO->EVENTS_END != 0)
+        {
+            NRF_RADIO->EVENTS_END = 0;
+            NVIC_ClearPendingIRQ(RADIO_IRQn);
+
+            if (m_state == STATE_RECEIVER_TEST)
+            {
+                NRF_RADIO->TASKS_RXEN = 1;
+                if ((NRF_RADIO->CRCSTATUS == 1) && check_pdu())
+                {
+                    // Count the number of successfully received packets
+                    m_rx_pkt_count++;
+                }
+                // Note that failing packets are simply ignored (CRC or contents error).
+
+                // Zero fill all pdu fields to avoid stray data
+                memset(&m_pdu, 0, DTM_PDU_MAX_MEMORY_SIZE);
+            }
+            // If no RECEIVER_TEST is running, ignore incoming packets (but do clear IRQ!)
+        }
+
+        // Check for timeouts:
+        if (mp_timer->EVENTS_COMPARE[0] != 0)
+        {
+            mp_timer->EVENTS_COMPARE[0] = 0;
+        }
+        else if (mp_timer->EVENTS_COMPARE[1] != 0)
+        {
+            // Reset timeout event flag for next iteration.
+            mp_timer->EVENTS_COMPARE[1] = 0;
+            NVIC_ClearPendingIRQ(m_timer_irq);
+            return ++m_current_time;
+        }
+
+        // Other events: No processing
+    }
+}
+
+
+uint32_t dtm_cmd(dtm_cmd_t cmd, dtm_freq_t freq, uint32_t length, dtm_pkt_type_t payload)
+{
+    // Save specified packet in static variable for tx/rx functions to use.
+    // Note that BLE conformance testers always use full length packets.
+    m_packet_length = (m_packet_length & 0xC0) | ((uint8_t)length & 0x3F);
+    m_packet_type   = payload;
+    m_phys_ch       = freq;
+
+    // Clean out any non-retrieved event that might linger from an earlier test
+    m_new_event     = true;
+
+    // Set default event; any error will set it to LE_TEST_STATUS_EVENT_ERROR
+    m_event         = LE_TEST_STATUS_EVENT_SUCCESS;
+
+    if (m_state == STATE_UNINITIALIZED)
+    {
+        // Application has not explicitly initialized DTM,
+        return DTM_ERROR_UNINITIALIZED;
+    }
+
+    if (cmd == LE_RESET)
+    {
+        // Note that timer will continue running after a reset
+        dtm_test_done();
+        if (freq == 0x01)
+        {
+            m_packet_length = length << 6;
+        }
+        else
+        {
+            m_packet_length = 0;
+        }
+        return DTM_SUCCESS;
+    }
+
+    if (cmd == LE_TEST_END)
+    {
+        if (m_state == STATE_IDLE)
+        {
+            // Sequencing error - only rx or tx test may be ended!
+            m_event = LE_TEST_STATUS_EVENT_ERROR;
+            return DTM_ERROR_INVALID_STATE;
+        }
+        m_event = LE_PACKET_REPORTING_EVENT | m_rx_pkt_count;
+        dtm_test_done();
+        return DTM_SUCCESS;
+    }
+
+    if (m_state != STATE_IDLE)
+    {
+        // Sequencing error - only TEST_END/RESET are legal while test is running
+        // Note: State is unchanged; ongoing test not affected
+        m_event = LE_TEST_STATUS_EVENT_ERROR;
+        return DTM_ERROR_INVALID_STATE;
+    }
+
+    // Check for illegal values of m_phys_ch. Skip the check if the packet is vendor spesific.
+    if (payload != DTM_PKT_VENDORSPECIFIC && m_phys_ch > PHYS_CH_MAX)
+    {
+        // Parameter error
+        // Note: State is unchanged; ongoing test not affected
+        m_event = LE_TEST_STATUS_EVENT_ERROR;
+        return DTM_ERROR_ILLEGAL_CHANNEL;
+    }
+
+    m_rx_pkt_count = 0;
+
+    if (cmd == LE_RECEIVER_TEST)
+    {
+        // Zero fill all pdu fields to avoid stray data from earlier test run
+        memset(&m_pdu, 0, DTM_PDU_MAX_MEMORY_SIZE);
+        radio_prepare(RX_MODE);                      // Reinitialize "everything"; RF interrupts OFF
+        m_state = STATE_RECEIVER_TEST;
+        return DTM_SUCCESS;
+    }
+
+    if (cmd == LE_TRANSMITTER_TEST)
+    {
+        // Check for illegal values of m_packet_length. Skip the check if the packet is vendor spesific.
+        if (payload != DTM_PKT_VENDORSPECIFIC && m_packet_length > DTM_PAYLOAD_MAX_SIZE)
+        {
+            // Parameter error
+            m_event = LE_TEST_STATUS_EVENT_ERROR;
+            return DTM_ERROR_ILLEGAL_LENGTH;
+        }
+
+        // Note that PDU uses 4 bits even though BLE DTM uses only 2 (the HCI SDU uses all 4)
+        m_pdu.content[DTM_HEADER_OFFSET] = ((uint8_t)m_packet_type & 0x0F);
+        m_pdu.content[DTM_LENGTH_OFFSET] = m_packet_length;
+
+        switch (m_packet_type)
+        {
+            case DTM_PKT_PRBS9:
+                // Non-repeated, must copy entire pattern to PDU
+                memcpy(m_pdu.content + DTM_HEADER_SIZE, m_prbs_content, m_packet_length);
+                break;
+
+            case DTM_PKT_0X0F:
+                // Bit pattern 00001111 repeated
+                memset(m_pdu.content + DTM_HEADER_SIZE, RFPHY_TEST_0X0F_REF_PATTERN, m_packet_length);
+                break;
+
+            case DTM_PKT_0X55:
+                // Bit pattern 01010101 repeated
+                memset(m_pdu.content + DTM_HEADER_SIZE, RFPHY_TEST_0X55_REF_PATTERN, m_packet_length);
+                break;
+
+            case DTM_PKT_VENDORSPECIFIC:
+                // The length field is for indicating the vendor specific command to execute.
+                // The frequency field is used for vendor specific options to the command.
+                return dtm_vendor_specific_pkt(length, freq);
+
+            default:
+                // Parameter error
+                m_event = LE_TEST_STATUS_EVENT_ERROR;
+                return DTM_ERROR_ILLEGAL_CONFIGURATION;
+        }
+
+        // Initialize CRC value, set channel:
+        radio_prepare(TX_MODE);
+        // Set the timer to the correct period. The delay between each packet is described in the
+        // Bluetooth Core Spsification version 4.2 Vol. 6 Part F Section 4.1.6.
+        if ((m_packet_length + DTM_ON_AIR_OVERHEAD_SIZE ) * 8  <= 376)
+        {
+            mp_timer->CC[0]       = 625;                        // 625uS with 1MHz clock to the timer
+        }
+        else if ((m_packet_length + DTM_ON_AIR_OVERHEAD_SIZE ) * 8  <= 1000)
+        {
+            mp_timer->CC[0]       = 1250;                        // 625uS with 1MHz clock to the timer
+        }
+        else if ((m_packet_length + DTM_ON_AIR_OVERHEAD_SIZE ) * 8  <= 1624)
+        {
+            mp_timer->CC[0]       = 1875;                        // 625uS with 1MHz clock to the timer
+        }
+        else
+        {
+            mp_timer->CC[0]       = 2500;                        // 625uS with 1MHz clock to the timer
+        }
+
+        // Configure PPI so that timer will activate radio every 625 us
+        NRF_PPI->CH[0].EEP = (uint32_t)&mp_timer->EVENTS_COMPARE[0];
+        NRF_PPI->CH[0].TEP = (uint32_t)&NRF_RADIO->TASKS_TXEN;
+        NRF_PPI->CHENSET   = 0x01;
+        m_state            = STATE_TRANSMITTER_TEST;
+    }
+    return DTM_SUCCESS;
+}
+
+
+bool dtm_event_get(dtm_event_t *p_dtm_event)
+{
+    bool was_new = m_new_event;
+    // mark the current event as retrieved
+    m_new_event  = false;
+    *p_dtm_event = m_event;
+    // return value indicates whether this value was already retrieved.
+    return was_new;
+}
+
+
+// =================================================================================================
+// Configuration functions (only for parameters not definitely determined by the BLE DTM standard).
+// These functions return true if successful, false if value could not be set
+
+
+/**@brief Function for configuring the output power for transmitter test.
+          This function may be called directly, or through dtm_cmd() specifying
+          DTM_PKT_VENDORSPECIFIC as payload, SET_TX_POWER as length, and the dBm value as frequency.
+ */
+bool dtm_set_txpower(uint32_t new_tx_power)
+{
+    // radio->TXPOWER register is 32 bits, low octet a signed value, upper 24 bits zeroed
+    int8_t new_power8 = (int8_t)(new_tx_power & 0xFF);
+
+    // The two most significant bits are not sent in the 6 bit field of the DTM command.
+    // These two bits are 1's if and only if the tx_power is a negative number.
+    // All valid negative values have the fourth most significant bit as 1.
+    // All valid positive values have the fourth most significant bit as 0.
+    // By checking this bit, the two most significant bits can be determined.
+    new_power8 = (new_power8 & 0x30) != 0 ? (new_power8 | 0xC0) : new_power8;
+
+    if (m_state > STATE_IDLE)
+    {
+        // radio must be idle to change the tx power
+        return false;
+    }
+
+    m_tx_power = new_power8;
+
+    return true;
+}
+
+
+/**@brief Function for selecting a timer resource.
+ *        This function may be called directly, or through dtm_cmd() specifying
+ *        DTM_PKT_VENDORSPECIFIC as payload, SELECT_TIMER as length, and the timer as freq
+ *
+ * @param[in] new_timer     Timer id for the timer to use: 0, 1, or 2.
+ *
+ * @return true if the timer was successfully changed, false otherwise.
+ */
+bool dtm_set_timer(uint32_t new_timer)
+{
+    if (m_state > STATE_IDLE)
+    {
+        return false;
+    }
+    return dtm_hw_set_timer(&mp_timer, &m_timer_irq, new_timer);
+}
+
+/// @}
+#endif // NRF_MODULE_ENABLED(BLE_DTM)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_dtm/ble_dtm.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,215 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup ble_dtm DTM - Direct Test Mode
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Module for testing RF/PHY using DTM commands.
+ */
+
+#ifndef BLE_DTM_H__
+#define BLE_DTM_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**@brief Configuration parameters. */
+#define DTM_BITRATE                     UART_BAUDRATE_BAUDRATE_Baud19200/**< Serial bitrate on the UART */
+#define DEFAULT_TX_POWER                RADIO_TXPOWER_TXPOWER_0dBm      /**< Default Transmission power using in the DTM module. */
+#define DEFAULT_TIMER                   NRF_TIMER0                      /**< Default timer used for timing. */
+#define DEFAULT_TIMER_IRQn              TIMER0_IRQn                     /**< IRQ used for timer. NOTE: MUST correspond to DEFAULT_TIMER. */
+
+/**@brief BLE DTM command codes. */
+typedef uint32_t dtm_cmd_t;                                             /**< DTM command type. */
+
+#define LE_RESET                        0                               /**< DTM command: Reset device. */
+#define LE_RECEIVER_TEST                1                               /**< DTM command: Start receive test. */
+#define LE_TRANSMITTER_TEST             2                               /**< DTM command: Start transmission test. */
+#define LE_TEST_END                     3                               /**< DTM command: End test and send packet report. */
+
+// Configuration options used as parameter 2
+// when cmd == LE_TRANSMITTER_TEST and payload == DTM_PKT_VENDORSPECIFIC
+// Configuration value, if any, is supplied in parameter 3
+
+#define CARRIER_TEST                    0                               /**< Length=0 indicates a constant, unmodulated carrier until LE_TEST_END or LE_RESET */
+#define CARRIER_TEST_STUDIO             1                               /**< nRFgo Studio uses value 1 in length field, to indicate a constant, unmodulated carrier until LE_TEST_END or LE_RESET */
+#define SET_TX_POWER                    2                               /**< Set transmission power, value -40..+4 dBm in steps of 4 */
+#define SELECT_TIMER                    3                               /**< Select on of the 16 MHz timers 0, 1 or 2 */
+
+#define LE_PACKET_REPORTING_EVENT       0x8000                          /**< DTM Packet reporting event, returned by the device to the tester. */
+#define LE_TEST_STATUS_EVENT_SUCCESS    0x0000                          /**< DTM Status event, indicating success. */
+#define LE_TEST_STATUS_EVENT_ERROR      0x0001                          /**< DTM Status event, indicating an error. */
+
+#define DTM_PKT_PRBS9                   0x00                            /**< Bit pattern PRBS9. */
+#define DTM_PKT_0X0F                    0x01                            /**< Bit pattern 11110000 (LSB is the leftmost bit). */
+#define DTM_PKT_0X55                    0x02                            /**< Bit pattern 10101010 (LSB is the leftmost bit). */
+#define DTM_PKT_VENDORSPECIFIC          0xFFFFFFFF                      /**< Vendor specific. Nordic: Continuous carrier test, or configuration. */
+
+/**@brief Return codes from dtm_cmd(). */
+#define DTM_SUCCESS                     0x00                            /**< Indicate that the DTM function completed with success. */
+#define DTM_ERROR_ILLEGAL_CHANNEL       0x01                            /**< Physical channel number must be in the range 0..39. */
+#define DTM_ERROR_INVALID_STATE         0x02                            /**< Sequencing error: Command is not valid now. */
+#define DTM_ERROR_ILLEGAL_LENGTH        0x03                            /**< Payload size must be in the range 0..37. */
+#define DTM_ERROR_ILLEGAL_CONFIGURATION 0x04                            /**< Parameter out of range (legal range is function dependent). */
+#define DTM_ERROR_UNINITIALIZED         0x05                            /**< DTM module has not been initialized by the application. */
+
+/**@details The UART poll cycle in micro seconds.
+ *          A baud rate of e.g. 19200 bits / second, and 8 data bits, 1 start/stop bit, no flow control,
+ *          give the time to transmit a byte: 10 bits * 1/19200 = approx: 520 us.
+ *          To ensure no loss of bytes, the UART should be polled every 260 us.
+ */
+#if DTM_BITRATE == UART_BAUDRATE_BAUDRATE_Baud9600
+#define UART_POLL_CYCLE ((uint32_t)(10*1e6/9600/2))
+#elif DTM_BITRATE == UART_BAUDRATE_BAUDRATE_Baud14400
+#define UART_POLL_CYCLE ((uint32_t)(10*1e6/14400/2))
+#elif DTM_BITRATE == UART_BAUDRATE_BAUDRATE_Baud19200
+#define UART_POLL_CYCLE ((uint32_t)(10*1e6/19200/2))
+#elif DTM_BITRATE == UART_BAUDRATE_BAUDRATE_Baud28800
+#define UART_POLL_CYCLE ((uint32_t)(10*1e6/28800/2))
+#elif DTM_BITRATE == UART_BAUDRATE_BAUDRATE_Baud38400
+#define UART_POLL_CYCLE ((uint32_t)(10*1e6/38400/2))
+#elif DTM_BITRATE == UART_BAUDRATE_BAUDRATE_Baud57600
+#define UART_POLL_CYCLE ((uint32_t)(10*1e6/57600/2))
+#elif DTM_BITRATE == UART_BAUDRATE_BAUDRATE_Baud76800
+#define UART_POLL_CYCLE ((uint32_t)(10*1e6/768000/2))
+#elif DTM_BITRATE == UART_BAUDRATE_BAUDRATE_Baud115200
+#define UART_POLL_CYCLE ((uint32_t)(10*1e6/115200/2))
+#elif DTM_BITRATE == UART_BAUDRATE_BAUDRATE_Baud230400
+#define UART_POLL_CYCLE ((uint32_t)(10*1e6/230400/2))
+#elif DTM_BITRATE == UART_BAUDRATE_BAUDRATE_Baud250000
+#define UART_POLL_CYCLE ((uint32_t)(10*1e6/250000/2))
+#elif DTM_BITRATE == UART_BAUDRATE_BAUDRATE_Baud460800
+#define UART_POLL_CYCLE ((uint32_t)(10*1e6/460800/2))
+#elif DTM_BITRATE == UART_BAUDRATE_BAUDRATE_Baud921600
+#define UART_POLL_CYCLE ((uint32_t)(10*1e6/921600/2))
+#elif DTM_BITRATE == UART_BAUDRATE_BAUDRATE_Baud1M
+#define UART_POLL_CYCLE ((uint32_t)(10*1e6/1e6/2))
+#else
+// It is possible to find values that work for other baud rates, but the formula above is not
+// guaranteed to work for all values. Suitable values may have to be found by trial and error.
+#error "Unsupported baud rate set."
+#endif
+
+// Note: DTM_PKT_VENDORSPECIFIC, is not a packet type
+#define PACKET_TYPE_MAX                 DTM_PKT_0X55                    /**< Highest value allowed as DTM Packet type. */
+
+/** @brief BLE DTM event type. */
+typedef uint32_t dtm_event_t;                                           /**< Type for handling DTM event. */
+
+/** @brief BLE DTM frequency type. */
+typedef uint32_t dtm_freq_t;                                            /**< Physical channel, valid range: 0..39. */
+
+/**@brief BLE DTM packet types. */
+typedef uint32_t dtm_pkt_type_t;                                        /**< Type for holding the requested DTM payload type.*/
+
+
+/**@brief Function for initializing or re-initializing DTM module
+ *
+ * @return DTM_SUCCESS on successful initialization of the DTM module.
+*/
+uint32_t dtm_init(void);
+
+
+/**@brief Function for giving control to dtmlib for handling timer and radio events.
+ *        Will return to caller at 625us intervals or whenever another event than radio occurs
+ *        (such as UART input). Function will put MCU to sleep between events.
+ *
+ * @return      Time counter, incremented every 625 us.
+ */
+uint32_t dtm_wait(void);
+
+
+/**@brief Function for calling when a complete command has been prepared by the Tester.
+ *
+ * @param[in]   cmd       One of the DTM_CMD values (bits 14:15 in the 16-bit UART format).
+ * @param[in]   freq      Phys. channel no - actual frequency = (2402 + freq * 2) MHz (bits 8:13 in
+ *                        the 16-bit UART format).
+ * @param[in]   length    Payload length, 0..37 (bits 2:7 in the 16-bit UART format).
+ * @param[in]   payload   One of the DTM_PKT values (bits 0:1 in the 16-bit UART format).
+ *
+ * @return      DTM_SUCCESS or one of the DTM_ERROR_ values
+ */
+uint32_t dtm_cmd(dtm_cmd_t cmd, dtm_freq_t freq, uint32_t length, dtm_pkt_type_t payload);
+
+
+/**@brief Function for reading the result of a DTM command
+ *
+ * @param[out]  p_dtm_event   Pointer to buffer for 16 bit event code according to DTM standard.
+ *
+ * @return      true: new event, false: no event since last call, this event has been read earlier
+ */
+bool dtm_event_get(dtm_event_t * p_dtm_event);
+
+
+/**@brief Function for configuring the timer to use.
+ *
+ * @note        Must be called when no DTM test is running.
+ *
+ * @param[in]   new_timer   Index (0..2) of timer to be used by the DTM library
+ *
+ * @return      true: success, new timer was selected, false: parameter error
+ */
+bool dtm_set_timer(uint32_t new_timer);
+
+
+/**@brief Function for configuring the transmit power.
+ *
+ * @note        Must be called when no DTM test is running.
+ *
+ * @param[in]   new_tx_power   New output level, +4..-40, in steps of 4.
+ *
+ * @return      true: tx power setting changed, false: parameter error
+ */
+bool dtm_set_txpower(uint32_t new_tx_power);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // BLE_DTM_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_dtm/ble_dtm_hw.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,102 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup ble_dtm_hw Direct Test Mode HW
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Module contains hardware related function for testing RF/PHY using DTM commands.
+ */
+
+#ifndef BLE_DTM_HW_H__
+#define BLE_DTM_HW_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**@brief Function for selecting a timer resource.
+ *        This function may be called directly, or through dtm_cmd() specifying
+ *        DTM_PKT_VENDORSPECIFIC as payload, SELECT_TIMER as length, and the timer as freq
+ *
+ * @param[out] mp_timer      Pointer to timer instance used in dtm source file.
+ * @param[out] m_timer_irq   Pointer to timer interrupt related to mp_timer.
+ * @param[in]  new_timer     Timer id for the timer to use.
+ *
+ * @retval true  if the timer was successfully changed.
+ * @retval false if the error occurs.
+ */
+
+bool dtm_hw_set_timer(NRF_TIMER_Type ** mp_timer, IRQn_Type * m_timer_irq, uint32_t new_timer);
+
+
+/**@brief Function for turning off radio test.
+ *        This function is platform depending. For now only nRF51 requieres this special function.
+ */
+void dtm_turn_off_test(void);
+
+
+/**@brief Function for setting constant carrier in radio settings.
+ *        This function is used to handle vendor specific command testing continous carrier without
+ *        a modulated signal.
+ */
+void dtm_constant_carrier(void);
+
+
+/**@brief Function for validating tx power and radio move settings.
+ * @param[in] m_tx_power    TX power for transmission test.
+ * @param[in] m_radio_mode  Radio mode value.
+ *
+ * @retval DTM_SUCCESS                     if input parameters values are correct.
+ * @retval DTM_ERROR_ILLEGAL_CONFIGURATION if input parameters values are not correct.
+ */
+uint32_t dtm_radio_validate(int32_t m_tx_power, uint8_t m_radio_mode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // BLE_DTM_HW_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_dtm/ble_dtm_hw_nrf52.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,117 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "ble_dtm_hw.h"
+#include "ble_dtm.h"
+#include <stdbool.h>
+#include <string.h>
+#include "nrf.h"
+
+
+void dtm_turn_off_test()
+{
+}
+
+
+void dtm_constant_carrier()
+{
+NRF_RADIO->MODECNF0 = (RADIO_MODECNF0_RU_Default << RADIO_MODECNF0_RU_Pos) |
+                      (RADIO_MODECNF0_DTX_Center << RADIO_MODECNF0_DTX_Pos);
+}
+
+
+uint32_t dtm_radio_validate(int32_t m_tx_power, uint8_t m_radio_mode)
+{
+    // Initializing code below is quite generic - for BLE, the values are fixed, and expressions
+    // are constant. Non-constant values are essentially set in radio_prepare().
+    if (!(m_tx_power == RADIO_TXPOWER_TXPOWER_0dBm     ||
+          m_tx_power == RADIO_TXPOWER_TXPOWER_Pos4dBm  ||
+          m_tx_power == RADIO_TXPOWER_TXPOWER_Neg30dBm ||
+          m_tx_power == RADIO_TXPOWER_TXPOWER_Neg20dBm ||
+          m_tx_power == RADIO_TXPOWER_TXPOWER_Neg16dBm ||
+          m_tx_power == RADIO_TXPOWER_TXPOWER_Neg12dBm ||
+          m_tx_power == RADIO_TXPOWER_TXPOWER_Neg8dBm  ||
+          m_tx_power == RADIO_TXPOWER_TXPOWER_Neg4dBm  ||
+          m_tx_power == RADIO_TXPOWER_TXPOWER_Pos3dBm  ||
+          m_tx_power == RADIO_TXPOWER_TXPOWER_Neg40dBm
+          ) ||
+        (m_radio_mode > RADIO_MODE_MODE_Ble_1Mbit) // Values 0 - 2: Proprietary mode, 3 (last valid): BLE
+        )
+    {
+        return DTM_ERROR_ILLEGAL_CONFIGURATION;
+    }
+
+    return DTM_SUCCESS;
+}
+
+
+bool dtm_hw_set_timer(NRF_TIMER_Type ** mp_timer, IRQn_Type * m_timer_irq, uint32_t new_timer)
+{
+    if (new_timer == 0)
+    {
+        *mp_timer    = NRF_TIMER0;
+        *m_timer_irq = TIMER0_IRQn;
+    }
+    else if (new_timer == 1)
+    {
+        *mp_timer    = NRF_TIMER1;
+        *m_timer_irq = TIMER1_IRQn;
+    }
+    else if (new_timer == 2)
+    {
+        *mp_timer    = NRF_TIMER2;
+        *m_timer_irq = TIMER2_IRQn;
+    }
+    else if (new_timer == 3)
+    {
+        *mp_timer    = NRF_TIMER3;
+        *m_timer_irq = TIMER3_IRQn;
+    }
+    else if (new_timer == 4)
+    {
+        *mp_timer    = NRF_TIMER4;
+        *m_timer_irq = TIMER4_IRQn;
+    }
+    else
+    {
+        // Parameter error: Only TIMER 0, 1, 2, 3 and 4 provided by nRF52
+        return false;
+    }
+    // New timer has been selected:
+    return true;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_error_log/ble_error_log.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,104 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup ble_error_log_module Error Log Module
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Module for writing error and stack to flash memory.
+ *
+ * @details It contains functions for writing an error code, line number, filename/message and
+ *          the stack to the flash during an error, e.g. in the assert handler.
+ *
+ */
+#ifndef BLE_ERROR_LOG_H__
+#define BLE_ERROR_LOG_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "ble_flash.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ERROR_MESSAGE_LENGTH  128                                /**< Length of error message to stored. */
+#define STACK_DUMP_LENGTH     256                                /**< Length of stack to be stored at max: 64 entries of 4 bytes each. */
+#define FLASH_PAGE_ERROR_LOG  (BLE_FLASH_PAGE_END - 2)           /**< Address in flash where stack trace can be stored. */
+
+/**@brief Error Log Data structure.
+ *
+ * @details The structure contains the error, message/filename, line number as well as the current
+ *          stack, at the time where an error occured.
+ */
+typedef struct
+{
+    uint16_t                  failure;                           /**< Indication that a major failure has occurred during last execution of the application. */
+    uint16_t                  line_number;                       /**< Line number indicating at which line the failure occurred. */
+    uint32_t                  err_code;                          /**< Error code when failure occurred. */
+    uint8_t                   message[ERROR_MESSAGE_LENGTH];     /**< Will just use the first 128 bytes of filename to store for debugging purposes. */
+    uint32_t                  stack_info[STACK_DUMP_LENGTH / 4]; /**< Will contain stack information, can be manually unwinded for debug purposes. */
+} ble_error_log_data_t;
+
+
+/**@brief Function for writing the file name/message, line number, and current program stack
+ *        to flash.
+ *
+ * @note This function will force the writing to flash, and disregard any radio communication.
+ *       USE THIS FUNCTION WITH CARE.
+ *
+ * @param[in]   err_code    Error code to be logged.
+ * @param[in]   p_message   Message to be written to the flash together with stack dump, usually
+ *                          the file name where the error occured.
+ * @param[in]   line_number Line number where the error occured.
+ *
+ * @return      NRF_SUCCESS on successful writing of the error log.
+ *
+ */
+uint32_t ble_error_log_write(uint32_t err_code, const uint8_t * p_message, uint16_t line_number);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BLE_ERROR_LOG_H__ */
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_racp/ble_racp.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,85 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(BLE_RACP)
+#include "ble_racp.h"
+#include <stdlib.h>
+
+
+void ble_racp_decode(uint8_t data_len, uint8_t * p_data, ble_racp_value_t * p_racp_val)
+{
+    p_racp_val->opcode      = 0xFF;
+    p_racp_val->operator    = 0xFF;
+    p_racp_val->operand_len = 0;
+    p_racp_val->p_operand   = NULL;
+
+    if (data_len > 0)
+    {
+        p_racp_val->opcode = p_data[0];
+    }
+    if (data_len > 1)
+    {
+        p_racp_val->operator = p_data[1];      //lint !e415
+    }
+    if (data_len > 2)
+    {
+        p_racp_val->operand_len = data_len - 2;
+        p_racp_val->p_operand   = &p_data[2];  //lint !e416
+    }
+}
+
+
+uint8_t ble_racp_encode(const ble_racp_value_t * p_racp_val, uint8_t * p_data)
+{
+    uint8_t len = 0;
+    int     i;
+
+    if (p_data != NULL)
+    {
+        p_data[len++] = p_racp_val->opcode;
+        p_data[len++] = p_racp_val->operator;
+
+        for (i = 0; i < p_racp_val->operand_len; i++)
+        {
+            p_data[len++] = p_racp_val->p_operand[i];
+        }
+    }
+
+    return len;
+}
+#endif // NRF_MODULE_ENABLED(BLE_RACP)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_racp/ble_racp.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,134 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup ble_racp Record Access Control Point
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Record Access Control Point library.
+ */
+
+#ifndef BLE_RACP_H__
+#define BLE_RACP_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "headers\ble.h"
+#include "ble_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Record Access Control Point opcodes. */
+#define RACP_OPCODE_RESERVED                0       /**< Record Access Control Point opcode - Reserved for future use. */
+#define RACP_OPCODE_REPORT_RECS             1       /**< Record Access Control Point opcode - Report stored records. */
+#define RACP_OPCODE_DELETE_RECS             2       /**< Record Access Control Point opcode - Delete stored records. */
+#define RACP_OPCODE_ABORT_OPERATION         3       /**< Record Access Control Point opcode - Abort operation. */
+#define RACP_OPCODE_REPORT_NUM_RECS         4       /**< Record Access Control Point opcode - Report number of stored records. */
+#define RACP_OPCODE_NUM_RECS_RESPONSE       5       /**< Record Access Control Point opcode - Number of stored records response. */
+#define RACP_OPCODE_RESPONSE_CODE           6       /**< Record Access Control Point opcode - Response code. */
+
+/**@brief Record Access Control Point operators. */
+#define RACP_OPERATOR_NULL                   0       /**< Record Access Control Point operator - Null. */
+#define RACP_OPERATOR_ALL                    1       /**< Record Access Control Point operator - All records. */
+#define RACP_OPERATOR_LESS_OR_EQUAL          2       /**< Record Access Control Point operator - Less than or equal to. */
+#define RACP_OPERATOR_GREATER_OR_EQUAL       3       /**< Record Access Control Point operator - Greater than or equal to. */
+#define RACP_OPERATOR_RANGE                  4       /**< Record Access Control Point operator - Within range of (inclusive). */
+#define RACP_OPERATOR_FIRST                  5       /**< Record Access Control Point operator - First record (i.e. oldest record). */
+#define RACP_OPERATOR_LAST                   6       /**< Record Access Control Point operator - Last record (i.e. most recent record). */
+#define RACP_OPERATOR_RFU_START              7       /**< Record Access Control Point operator - Start of Reserved for Future Use area. */
+
+/**@brief Record Access Control Point Operand Filter Type Value. */
+#define RACP_OPERAND_FILTER_TYPE_TIME_OFFSET 1       /**< Record Access Control Point Operand Filter Type Value - Time Offset- */
+
+/**@brief Record Access Control Point response codes. */
+#define RACP_RESPONSE_RESERVED               0       /**< Record Access Control Point response code - Reserved for future use. */
+#define RACP_RESPONSE_SUCCESS                1       /**< Record Access Control Point response code - Successful operation. */
+#define RACP_RESPONSE_OPCODE_UNSUPPORTED     2       /**< Record Access Control Point response code - Unsupported op code received. */
+#define RACP_RESPONSE_INVALID_OPERATOR       3       /**< Record Access Control Point response code - Operator not valid for service. */
+#define RACP_RESPONSE_OPERATOR_UNSUPPORTED   4       /**< Record Access Control Point response code - Unsupported operator. */
+#define RACP_RESPONSE_INVALID_OPERAND        5       /**< Record Access Control Point response code - Operand not valid for service. */
+#define RACP_RESPONSE_NO_RECORDS_FOUND       6       /**< Record Access Control Point response code - No matching records found. */
+#define RACP_RESPONSE_ABORT_FAILED           7       /**< Record Access Control Point response code - Abort could not be completed. */
+#define RACP_RESPONSE_PROCEDURE_NOT_DONE     8       /**< Record Access Control Point response code - Procedure could not be completed. */
+#define RACP_RESPONSE_OPERAND_UNSUPPORTED    9       /**< Record Access Control Point response code - Unsupported operand. */
+
+/**@brief Record Access Control Point value structure. */
+typedef struct
+{
+    uint8_t   opcode;                               /**< Op Code. */
+    uint8_t   operator;                             /**< Operator. */
+    uint8_t   operand_len;                          /**< Length of the operand. */
+    uint8_t * p_operand;                            /**< Pointer to the operand. */
+} ble_racp_value_t;
+
+/**@brief Function for decoding a Record Access Control Point write.
+ *
+ * @details This call decodes a write to the Record Access Control Point.
+ *
+ * @param[in]   data_len     Length of data in received write.
+ * @param[in]   p_data       Pointer to received data.
+ * @param[out]  p_racp_val   Pointer to decoded Record Access Control Point write.
+ *                           @note This does not do a data copy. It assumes the data pointed to by
+ *                                 p_data is persistant until no longer needed.
+ */
+void ble_racp_decode(uint8_t data_len, uint8_t * p_data, ble_racp_value_t * p_racp_val);
+
+/**@brief Function for encoding a Record Access Control Point response.
+ *
+ * @details This call encodes a response from the Record Access Control Point response.
+ *
+ * @param[in]   p_racp_val   Pointer to Record Access Control Point to encode.
+ * @param[out]  p_data       Pointer to where encoded data is written.
+ *                           NOTE! It is calling routines respsonsibility to make sure.
+ *
+ * @return      Length of encoded data.
+ */
+uint8_t ble_racp_encode(const ble_racp_value_t * p_racp_val, uint8_t * p_data);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // BLE_RACP_H__
+
+/** @} */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_radio_notification/ble_radio_notification.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,87 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "ble_radio_notification.h"
+#include "nrf_nvic.h"
+#include <stdlib.h>
+
+
+static bool                                 m_radio_active = false;  /**< Current radio state. */
+static ble_radio_notification_evt_handler_t m_evt_handler  = NULL;   /**< Application event handler for handling Radio Notification events. */
+
+
+void SWI1_IRQHandler(void)
+{
+    m_radio_active = !m_radio_active;
+    if (m_evt_handler != NULL)
+    {
+        m_evt_handler(m_radio_active);
+    }
+}
+
+
+uint32_t ble_radio_notification_init(uint32_t                             irq_priority,
+                                     uint8_t                              distance,
+                                     ble_radio_notification_evt_handler_t evt_handler)
+{
+    uint32_t err_code;
+
+    m_evt_handler = evt_handler;
+
+    // Initialize Radio Notification software interrupt
+    err_code = sd_nvic_ClearPendingIRQ(SWI1_IRQn);
+    if (err_code != NRF_SUCCESS)
+    {
+        return err_code;
+    }
+
+    err_code = sd_nvic_SetPriority(SWI1_IRQn, irq_priority);
+    if (err_code != NRF_SUCCESS)
+    {
+        return err_code;
+    }
+
+    err_code = sd_nvic_EnableIRQ(SWI1_IRQn);
+    if (err_code != NRF_SUCCESS)
+    {
+        return err_code;
+    }
+
+    // Configure the event
+    return sd_radio_notification_cfg_set(NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH, distance);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_radio_notification/ble_radio_notification.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,81 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup ble_radio_notification Radio Notification Event Handler
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Module for propagating Radio Notification events to the application.
+ */
+
+#ifndef BLE_RADIO_NOTIFICATION_H__
+#define BLE_RADIO_NOTIFICATION_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf_soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Application radio notification event handler type. */
+typedef void (*ble_radio_notification_evt_handler_t) (bool radio_active);
+
+/**@brief Function for initializing the Radio Notification module.
+ *
+ * @param[in]  irq_priority   Interrupt priority for the Radio Notification interrupt handler.
+ * @param[in]  distance       The time from an Active event until the radio is activated.
+ * @param[in]  evt_handler    Handler to be executed when a radio notification event has been
+ *                            received.
+ *
+ * @return     NRF_SUCCESS on successful initialization, otherwise an error code.
+ */
+uint32_t ble_radio_notification_init(uint32_t                             irq_priority,
+                                     uint8_t                              distance,
+                                     ble_radio_notification_evt_handler_t evt_handler);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // BLE_RADIO_NOTIFICATION_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_advdata.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,680 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "ble_advdata.h"
+#include "ble_gap.h"
+#include "ble_srv_common.h"
+#include "sdk_common.h"
+
+// NOTE: For now, Security Manager Out of Band Flags (OOB) are omitted from the advertising data.
+
+// Types of LE Bluetooth Device Address AD type
+#define AD_TYPE_BLE_DEVICE_ADDR_TYPE_PUBLIC 0UL
+#define AD_TYPE_BLE_DEVICE_ADDR_TYPE_RANDOM 1UL
+
+static uint32_t ble_device_addr_encode(uint8_t  * p_encoded_data,
+                                       uint16_t * p_offset,
+                                       uint16_t   max_size)
+{
+    uint32_t err_code;
+    ble_gap_addr_t device_addr;
+
+    // Check for buffer overflow.
+    if (((*p_offset) + AD_TYPE_BLE_DEVICE_ADDR_SIZE) > max_size)
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // Get BLE address.
+    #if (NRF_SD_BLE_API_VERSION >= 3)
+        err_code = sd_ble_gap_addr_get(&device_addr);
+    #else
+        err_code = sd_ble_gap_address_get(&device_addr);
+    #endif
+    VERIFY_SUCCESS(err_code);
+
+    // Encode LE Bluetooth Device Address.
+    p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE +
+                                               AD_TYPE_BLE_DEVICE_ADDR_DATA_SIZE);
+    *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = BLE_GAP_AD_TYPE_LE_BLUETOOTH_DEVICE_ADDRESS;
+    *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+    memcpy(&p_encoded_data[*p_offset], &device_addr.addr[0], BLE_GAP_ADDR_LEN);
+    *p_offset                 += BLE_GAP_ADDR_LEN;
+    if (BLE_GAP_ADDR_TYPE_PUBLIC == device_addr.addr_type)
+    {
+        p_encoded_data[*p_offset] = AD_TYPE_BLE_DEVICE_ADDR_TYPE_PUBLIC;
+    }
+    else
+    {
+        p_encoded_data[*p_offset] = AD_TYPE_BLE_DEVICE_ADDR_TYPE_RANDOM;
+    }
+    *p_offset += AD_TYPE_BLE_DEVICE_ADDR_TYPE_SIZE;
+
+    return NRF_SUCCESS;
+}
+
+static uint32_t name_encode(const ble_advdata_t * p_advdata,
+                            uint8_t             * p_encoded_data,
+                            uint16_t            * p_offset,
+                            uint16_t              max_size)
+{
+    uint32_t err_code;
+    uint16_t rem_adv_data_len;
+    uint16_t actual_length;
+    uint8_t  adv_data_format;
+
+
+    // Validate parameters
+    if ((BLE_ADVDATA_SHORT_NAME == p_advdata->name_type) && (0 == p_advdata->short_name_len))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    // Check for buffer overflow.
+    if ( (((*p_offset) + ADV_AD_DATA_OFFSET) > max_size) ||
+         ( (BLE_ADVDATA_SHORT_NAME == p_advdata->name_type) &&
+           (((*p_offset) + ADV_AD_DATA_OFFSET + p_advdata->short_name_len) > max_size)))
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    rem_adv_data_len = max_size - (*p_offset) - ADV_AD_DATA_OFFSET;
+    actual_length    = rem_adv_data_len;
+
+    // Get GAP device name and length
+    err_code = sd_ble_gap_device_name_get(&p_encoded_data[(*p_offset) + ADV_AD_DATA_OFFSET],
+                                          &actual_length);
+    VERIFY_SUCCESS(err_code);
+
+    // Check if device intend to use short name and it can fit available data size.
+    if ((p_advdata->name_type == BLE_ADVDATA_FULL_NAME) && (actual_length <= rem_adv_data_len))
+    {
+        // Complete device name can fit, setting Complete Name in Adv Data.
+        adv_data_format = BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME;
+    }
+    else
+    {
+        // Else short name needs to be used. Or application has requested use of short name.
+        adv_data_format = BLE_GAP_AD_TYPE_SHORT_LOCAL_NAME;
+
+        // If application has set a preference on the short name size, it needs to be considered,
+        // else fit what can be fit.
+        if ((BLE_ADVDATA_SHORT_NAME == p_advdata->name_type) &&
+                (p_advdata->short_name_len <= rem_adv_data_len))
+        {
+            // Short name fits available size.
+            actual_length = p_advdata->short_name_len;
+        }
+        // Else whatever can fit the data buffer will be packed.
+        else
+        {
+            actual_length = rem_adv_data_len;
+        }
+    }
+
+    // There is only 1 byte intended to encode length which is (actual_length + ADV_AD_TYPE_FIELD_SIZE)
+    if (actual_length > (0x00FF - ADV_AD_TYPE_FIELD_SIZE))
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // Complete name field in encoded data.
+    p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + actual_length);
+    *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = adv_data_format;
+    *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+    *p_offset                 += actual_length;
+
+    return NRF_SUCCESS;
+}
+
+
+static uint32_t appearance_encode(uint8_t  * p_encoded_data,
+                                  uint16_t * p_offset,
+                                  uint16_t   max_size)
+{
+    uint32_t err_code;
+    uint16_t appearance;
+
+    // Check for buffer overflow.
+    if (((*p_offset) + AD_TYPE_APPEARANCE_SIZE) > max_size)
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // Get GAP appearance field.
+    err_code = sd_ble_gap_appearance_get(&appearance);
+    VERIFY_SUCCESS(err_code);
+
+    // Encode Length, AD Type and Appearance.
+    p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_APPEARANCE_DATA_SIZE);
+    *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = BLE_GAP_AD_TYPE_APPEARANCE;
+    *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+    *p_offset                 += uint16_encode(appearance, &p_encoded_data[*p_offset]);
+
+    return NRF_SUCCESS;
+}
+
+static uint32_t flags_encode(int8_t     flags,
+                             uint8_t  * p_encoded_data,
+                             uint16_t * p_offset,
+                             uint16_t   max_size)
+{
+    // Check for buffer overflow.
+    if (((*p_offset) + AD_TYPE_FLAGS_SIZE) > max_size)
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // Encode flags.
+    p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_FLAGS_DATA_SIZE);
+    *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = BLE_GAP_AD_TYPE_FLAGS;
+    *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = flags;
+    *p_offset                 += AD_TYPE_FLAGS_DATA_SIZE;
+
+    return NRF_SUCCESS;
+}
+
+static uint32_t tx_power_level_encode(int8_t     tx_power_level,
+                                      uint8_t  * p_encoded_data,
+                                      uint16_t * p_offset,
+                                      uint16_t   max_size)
+{
+    // Check for buffer overflow.
+    if (((*p_offset) + AD_TYPE_TX_POWER_LEVEL_SIZE) > max_size)
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // Encode TX Power Level.
+    p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE +
+                                                  AD_TYPE_TX_POWER_LEVEL_DATA_SIZE);
+    *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = BLE_GAP_AD_TYPE_TX_POWER_LEVEL;
+    *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = tx_power_level;
+    *p_offset                 += AD_TYPE_TX_POWER_LEVEL_DATA_SIZE;
+
+    return NRF_SUCCESS;
+}
+
+
+static uint32_t uuid_list_sized_encode(const ble_advdata_uuid_list_t * p_uuid_list,
+                                       uint8_t                         adv_type,
+                                       uint8_t                         uuid_size,
+                                       uint8_t                       * p_encoded_data,
+                                       uint16_t                      * p_offset,
+                                       uint16_t                        max_size)
+{
+    int      i;
+    bool     is_heading_written = false;
+    uint16_t start_pos          = *p_offset;
+    uint16_t length;
+
+    for (i = 0; i < p_uuid_list->uuid_cnt; i++)
+    {
+        uint32_t   err_code;
+        uint8_t    encoded_size;
+        ble_uuid_t uuid = p_uuid_list->p_uuids[i];
+
+        // Find encoded uuid size.
+        err_code = sd_ble_uuid_encode(&uuid, &encoded_size, NULL);
+        VERIFY_SUCCESS(err_code);
+
+        // Check size.
+        if (encoded_size == uuid_size)
+        {
+            uint8_t heading_bytes = (is_heading_written) ? 0 : ADV_AD_DATA_OFFSET;
+
+            // Check for buffer overflow
+            if (((*p_offset) + encoded_size + heading_bytes) > max_size)
+            {
+                return NRF_ERROR_DATA_SIZE;
+            }
+
+            if (!is_heading_written)
+            {
+                // Write AD structure heading.
+                *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+                p_encoded_data[*p_offset]  = adv_type;
+                *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+                is_heading_written         = true;
+            }
+
+            // Write UUID.
+            err_code = sd_ble_uuid_encode(&uuid, &encoded_size, &p_encoded_data[*p_offset]);
+            VERIFY_SUCCESS(err_code);
+            *p_offset += encoded_size;
+        }
+    }
+
+    if (is_heading_written)
+    {
+        // Write length.
+        length = (*p_offset) - (start_pos + ADV_LENGTH_FIELD_SIZE);
+        // There is only 1 byte intended to encode length
+        if (length > 0x00FF)
+        {
+            return NRF_ERROR_DATA_SIZE;
+        }
+        p_encoded_data[start_pos] = (uint8_t)length;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+static uint32_t uuid_list_encode(const ble_advdata_uuid_list_t * p_uuid_list,
+                                 uint8_t                         adv_type_16,
+                                 uint8_t                         adv_type_128,
+                                 uint8_t                       * p_encoded_data,
+                                 uint16_t                      * p_offset,
+                                 uint16_t                        max_size)
+{
+    uint32_t err_code;
+
+    // Encode 16 bit UUIDs.
+    err_code = uuid_list_sized_encode(p_uuid_list,
+                                      adv_type_16,
+                                      sizeof(uint16_le_t),
+                                      p_encoded_data,
+                                      p_offset,
+                                      max_size);
+    VERIFY_SUCCESS(err_code);
+
+    // Encode 128 bit UUIDs.
+    err_code = uuid_list_sized_encode(p_uuid_list,
+                                      adv_type_128,
+                                      sizeof(ble_uuid128_t),
+                                      p_encoded_data,
+                                      p_offset,
+                                      max_size);
+    VERIFY_SUCCESS(err_code);
+
+    return NRF_SUCCESS;
+}
+
+
+static uint32_t conn_int_check(const ble_advdata_conn_int_t *p_conn_int)
+{
+    // Check Minimum Connection Interval.
+    if ((p_conn_int->min_conn_interval < 0x0006) ||
+        (
+            (p_conn_int->min_conn_interval > 0x0c80) &&
+            (p_conn_int->min_conn_interval != 0xffff)
+        )
+       )
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    // Check Maximum Connection Interval.
+    if ((p_conn_int->max_conn_interval < 0x0006) ||
+        (
+            (p_conn_int->max_conn_interval > 0x0c80) &&
+            (p_conn_int->max_conn_interval != 0xffff)
+        )
+       )
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    // Make sure Minimum Connection Interval is not bigger than Maximum Connection Interval.
+    if ((p_conn_int->min_conn_interval != 0xffff) &&
+        (p_conn_int->max_conn_interval != 0xffff) &&
+        (p_conn_int->min_conn_interval > p_conn_int->max_conn_interval)
+        )
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+static uint32_t conn_int_encode(const ble_advdata_conn_int_t * p_conn_int,
+                                uint8_t                      * p_encoded_data,
+                                uint16_t                     * p_offset,
+                                uint16_t                       max_size)
+{
+    uint32_t err_code;
+
+    // Check for buffer overflow.
+    if (((*p_offset) + AD_TYPE_CONN_INT_SIZE) > max_size)
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // Check parameters.
+    err_code = conn_int_check(p_conn_int);
+    VERIFY_SUCCESS(err_code);
+
+    // Encode Length and AD Type.
+    p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_CONN_INT_DATA_SIZE);
+    *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = BLE_GAP_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE;
+    *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+
+    // Encode Minimum and Maximum Connection Intervals.
+    *p_offset += uint16_encode(p_conn_int->min_conn_interval, &p_encoded_data[*p_offset]);
+    *p_offset += uint16_encode(p_conn_int->max_conn_interval, &p_encoded_data[*p_offset]);
+
+    return NRF_SUCCESS;
+}
+
+
+static uint32_t manuf_specific_data_encode(const ble_advdata_manuf_data_t * p_manuf_sp_data,
+                                           uint8_t                        * p_encoded_data,
+                                           uint16_t                       * p_offset,
+                                           uint16_t                         max_size)
+{
+    uint32_t data_size = AD_TYPE_MANUF_SPEC_DATA_ID_SIZE + p_manuf_sp_data->data.size;
+
+    // Check for buffer overflow.
+    if (((*p_offset) + ADV_AD_DATA_OFFSET + data_size) > max_size)
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // There is only 1 byte intended to encode length which is (data_size + ADV_AD_TYPE_FIELD_SIZE)
+    if (data_size > (0x00FF - ADV_AD_TYPE_FIELD_SIZE))
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // Encode Length and AD Type.
+    p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + data_size);
+    *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = BLE_GAP_AD_TYPE_MANUFACTURER_SPECIFIC_DATA;
+    *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+
+    // Encode Company Identifier.
+    *p_offset += uint16_encode(p_manuf_sp_data->company_identifier, &p_encoded_data[*p_offset]);
+
+    // Encode additional manufacturer specific data.
+    if (p_manuf_sp_data->data.size > 0)
+    {
+        if (p_manuf_sp_data->data.p_data == NULL)
+        {
+            return NRF_ERROR_INVALID_PARAM;
+        }
+        memcpy(&p_encoded_data[*p_offset], p_manuf_sp_data->data.p_data, p_manuf_sp_data->data.size);
+        *p_offset += p_manuf_sp_data->data.size;
+    }
+
+    return NRF_SUCCESS;
+}
+
+// Implemented only for 16-bit UUIDs
+static uint32_t service_data_encode(const ble_advdata_t * p_advdata,
+                                    uint8_t             * p_encoded_data,
+                                    uint16_t            * p_offset,
+                                    uint16_t              max_size)
+{
+    uint8_t i;
+
+    // Check parameter consistency.
+    if (p_advdata->p_service_data_array == NULL)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    for (i = 0; i < p_advdata->service_data_count; i++)
+    {
+        ble_advdata_service_data_t * p_service_data;
+        uint32_t                     data_size;
+
+        p_service_data = &p_advdata->p_service_data_array[i];
+        // For now implemented only for 16-bit UUIDs
+        data_size      = AD_TYPE_SERV_DATA_16BIT_UUID_SIZE + p_service_data->data.size;
+
+        // There is only 1 byte intended to encode length which is (data_size + ADV_AD_TYPE_FIELD_SIZE)
+        if (data_size > (0x00FF - ADV_AD_TYPE_FIELD_SIZE))
+        {
+            return NRF_ERROR_DATA_SIZE;
+        }
+
+        // Encode Length and AD Type.
+        p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + data_size);
+        *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+        p_encoded_data[*p_offset]  = BLE_GAP_AD_TYPE_SERVICE_DATA;
+        *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+
+        // Encode service 16-bit UUID.
+        *p_offset += uint16_encode(p_service_data->service_uuid, &p_encoded_data[*p_offset]);
+
+        // Encode additional service data.
+        if (p_service_data->data.size > 0)
+        {
+            if (p_service_data->data.p_data == NULL)
+            {
+                return NRF_ERROR_INVALID_PARAM;
+            }
+            memcpy(&p_encoded_data[*p_offset], p_service_data->data.p_data, p_service_data->data.size);
+            *p_offset += p_service_data->data.size;
+        }
+    }
+
+    return NRF_SUCCESS;
+}
+
+uint32_t adv_data_encode(ble_advdata_t const * const p_advdata,
+                         uint8_t             * const p_encoded_data,
+                         uint16_t            * const p_len)
+{
+    uint32_t err_code = NRF_SUCCESS;
+    uint16_t max_size = *p_len;
+    *p_len = 0;
+
+    // Encode LE Bluetooth Device Address
+    if (p_advdata->include_ble_device_addr)
+    {
+        err_code = ble_device_addr_encode(p_encoded_data, p_len, max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode appearance.
+    if (p_advdata->include_appearance)
+    {
+        err_code = appearance_encode(p_encoded_data, p_len, max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    //Encode Flags
+    if (p_advdata->flags != 0 )
+    {
+        err_code = flags_encode(p_advdata->flags, p_encoded_data, p_len, max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode TX power level.
+    if (p_advdata->p_tx_power_level != NULL)
+    {
+        err_code = tx_power_level_encode(*p_advdata->p_tx_power_level,
+                                         p_encoded_data,
+                                         p_len,
+                                         max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode 'more available' uuid list.
+    if (p_advdata->uuids_more_available.uuid_cnt > 0)
+    {
+        err_code = uuid_list_encode(&p_advdata->uuids_more_available,
+                                    BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE,
+                                    BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE,
+                                    p_encoded_data,
+                                    p_len,
+                                    max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode 'complete' uuid list.
+    if (p_advdata->uuids_complete.uuid_cnt > 0)
+    {
+        err_code = uuid_list_encode(&p_advdata->uuids_complete,
+                                    BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE,
+                                    BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE,
+                                    p_encoded_data,
+                                    p_len,
+                                    max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode 'solicited service' uuid list.
+    if (p_advdata->uuids_solicited.uuid_cnt > 0)
+    {
+        err_code = uuid_list_encode(&p_advdata->uuids_solicited,
+                                    BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT,
+                                    BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT,
+                                    p_encoded_data,
+                                    p_len,
+                                    max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode Slave Connection Interval Range.
+    if (p_advdata->p_slave_conn_int != NULL)
+    {
+        err_code = conn_int_encode(p_advdata->p_slave_conn_int, p_encoded_data, p_len, max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode Manufacturer Specific Data.
+    if (p_advdata->p_manuf_specific_data != NULL)
+    {
+        err_code = manuf_specific_data_encode(p_advdata->p_manuf_specific_data,
+                                              p_encoded_data,
+                                              p_len,
+                                              max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode Service Data.
+    if (p_advdata->service_data_count > 0)
+    {
+        err_code = service_data_encode(p_advdata, p_encoded_data, p_len, max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode name. WARNING: it is encoded last on purpose since too long device name is truncated.
+    if (p_advdata->name_type != BLE_ADVDATA_NO_NAME)
+    {
+        err_code = name_encode(p_advdata, p_encoded_data, p_len, max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    return err_code;
+}
+
+
+static uint32_t advdata_check(const ble_advdata_t * p_advdata)
+{
+    // Flags must be included in advertising data, and the BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED flag must be set.
+    if (
+        ((p_advdata->flags & BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) == 0)
+       )
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+static uint32_t srdata_check(const ble_advdata_t * p_srdata)
+{
+    // Flags shall not be included in the scan response data.
+    if (p_srdata->flags)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_advdata_set(const ble_advdata_t * p_advdata, const ble_advdata_t * p_srdata)
+{
+    uint32_t  err_code;
+    uint16_t  len_advdata = BLE_GAP_ADV_MAX_SIZE;
+    uint16_t  len_srdata  = BLE_GAP_ADV_MAX_SIZE;
+    uint8_t   encoded_advdata[BLE_GAP_ADV_MAX_SIZE];
+    uint8_t   encoded_srdata[BLE_GAP_ADV_MAX_SIZE];
+    uint8_t * p_encoded_advdata;
+    uint8_t * p_encoded_srdata;
+
+    // Encode advertising data (if supplied).
+    if (p_advdata != NULL)
+    {
+        err_code = advdata_check(p_advdata);
+        VERIFY_SUCCESS(err_code);
+
+        err_code = adv_data_encode(p_advdata, encoded_advdata, &len_advdata);
+        VERIFY_SUCCESS(err_code);
+        p_encoded_advdata = encoded_advdata;
+    }
+    else
+    {
+        p_encoded_advdata = NULL;
+        len_advdata = 0;
+    }
+
+    // Encode scan response data (if supplied).
+    if (p_srdata != NULL)
+    {
+        err_code = srdata_check(p_srdata);
+        VERIFY_SUCCESS(err_code);
+
+        err_code = adv_data_encode(p_srdata, encoded_srdata, &len_srdata);
+        VERIFY_SUCCESS(err_code);
+        p_encoded_srdata = encoded_srdata;
+    }
+    else
+    {
+        p_encoded_srdata = NULL;
+        len_srdata = 0;
+    }
+
+    // Pass encoded advertising data and/or scan response data to the stack.
+    return sd_ble_gap_adv_data_set(p_encoded_advdata, len_advdata, p_encoded_srdata, len_srdata);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_advdata.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,229 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup ble_sdk_lib_advdata Advertising and Scan Response Data Encoder
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Functions for encoding data in the Advertising and Scan Response Data format,
+ *        and for passing the data to the stack.
+ */
+
+#ifndef BLE_ADVDATA_H__
+#define BLE_ADVDATA_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+#include "headers/ble.h"
+#include "app_util.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define ADV_LENGTH_FIELD_SIZE              1UL                                 /**< Advertising Data and Scan Response format contains 1 octet for the length. */
+#define ADV_AD_TYPE_FIELD_SIZE             1UL                                 /**< Advertising Data and Scan Response format contains 1 octet for the AD type. */
+#define ADV_AD_DATA_OFFSET                 (ADV_LENGTH_FIELD_SIZE + \
+                                            ADV_AD_TYPE_FIELD_SIZE)            /**< Offset for the AD data field of the Advertising Data and Scan Response format. */
+#define AD_TYPE_BLE_DEVICE_ADDR_TYPE_SIZE  1UL                                 /**< Data size (in octets) of the Address type of the LE Bluetooth Device Address AD type. */
+#define AD_TYPE_BLE_DEVICE_ADDR_DATA_SIZE  (BLE_GAP_ADDR_LEN + \
+                                            AD_TYPE_BLE_DEVICE_ADDR_TYPE_SIZE) /**< Data size (in octets) of the LE Bluetooth Device Address AD type. */
+#define AD_TYPE_BLE_DEVICE_ADDR_SIZE       (ADV_AD_DATA_OFFSET + \
+                                            AD_TYPE_BLE_DEVICE_ADDR_DATA_SIZE) /**< Size (in octets) of the LE Bluetooth Device Address AD type. */
+#define AD_TYPE_APPEARANCE_DATA_SIZE       2UL                                 /**< Data size (in octets) of the Appearance AD type. */
+#define AD_TYPE_APPEARANCE_SIZE            (ADV_AD_DATA_OFFSET + \
+                                            AD_TYPE_APPEARANCE_DATA_SIZE)      /**< Size (in octets) of the Appearance AD type. */
+#define AD_TYPE_FLAGS_DATA_SIZE            1UL                                 /**< Data size (in octets) of the Flags AD type. */
+#define AD_TYPE_FLAGS_SIZE                 (ADV_AD_DATA_OFFSET + \
+                                            AD_TYPE_FLAGS_DATA_SIZE)           /**< Size (in octets) of the Flags AD type. */
+#define AD_TYPE_TX_POWER_LEVEL_DATA_SIZE   1UL                                 /**< Data size (in octets) of the TX Power Level AD type. */
+#define AD_TYPE_TX_POWER_LEVEL_SIZE        (ADV_AD_DATA_OFFSET + \
+                                            AD_TYPE_TX_POWER_LEVEL_DATA_SIZE)  /**< Size (in octets) of the TX Power Level AD type. */
+#define AD_TYPE_CONN_INT_DATA_SIZE         4UL                                 /**< Data size (in octets) of the Slave Connection Interval Range AD type. */
+#define AD_TYPE_CONN_INT_SIZE              (ADV_AD_DATA_OFFSET + \
+                                            AD_TYPE_CONN_INT_DATA_SIZE)        /**< Data size (in octets) of the Slave Connection Interval Range AD type. */
+#define AD_TYPE_MANUF_SPEC_DATA_ID_SIZE    2UL                                 /**< Size (in octets) of the Company Identifier Code, which is a part of the Manufacturer Specific Data AD type. */
+#define AD_TYPE_SERV_DATA_16BIT_UUID_SIZE  2UL                                 /**< Size (in octets) of the 16-bit UUID, which is a part of the Service Data AD type. */
+
+/**@brief Security Manager TK value. */
+typedef struct
+{
+  uint8_t tk[BLE_GAP_SEC_KEY_LEN];      /**< Array containing TK value in little-endian format. */
+} ble_advdata_tk_value_t;
+
+/**@brief Advertising data LE Role types. This enumeration contains the options available for the LE role inside
+ *        the advertising data. */
+typedef enum
+{
+    BLE_ADVDATA_ROLE_NOT_PRESENT = 0,                                 /**< LE Role AD structure not present. */
+    BLE_ADVDATA_ROLE_ONLY_PERIPH,                                     /**< Only Peripheral Role supported. */
+    BLE_ADVDATA_ROLE_ONLY_CENTRAL,                                    /**< Only Central Role supported. */
+    BLE_ADVDATA_ROLE_BOTH_PERIPH_PREFERRED,                           /**< Peripheral and Central Role supported. Peripheral Role preferred for connection establishment. */
+    BLE_ADVDATA_ROLE_BOTH_CENTRAL_PREFERRED                           /**< Peripheral and Central Role supported. Central Role preferred for connection establishment */
+} ble_advdata_le_role_t;
+
+/**@brief Advertising data name type. This enumeration contains the options available for the device name inside
+ *        the advertising data. */
+typedef enum
+{
+    BLE_ADVDATA_NO_NAME,                                              /**< Include no device name in advertising data. */
+    BLE_ADVDATA_SHORT_NAME,                                           /**< Include short device name in advertising data. */
+    BLE_ADVDATA_FULL_NAME                                             /**< Include full device name in advertising data. */
+} ble_advdata_name_type_t;
+
+/**@brief UUID list type. */
+typedef struct
+{
+    uint16_t                     uuid_cnt;                            /**< Number of UUID entries. */
+    ble_uuid_t *                 p_uuids;                             /**< Pointer to UUID array entries. */
+} ble_advdata_uuid_list_t;
+
+/**@brief Connection interval range structure. */
+typedef struct
+{
+    uint16_t                     min_conn_interval;                   /**< Minimum connection interval, in units of 1.25 ms, range 6 to 3200 (7.5 ms to 4 s). */
+    uint16_t                     max_conn_interval;                   /**< Maximum connection interval, in units of 1.25 ms, range 6 to 3200 (7.5 ms to 4 s). The value 0xFFFF indicates no specific maximum. */
+} ble_advdata_conn_int_t;
+
+/**@brief Manufacturer specific data structure. */
+typedef struct
+{
+    uint16_t                     company_identifier;                  /**< Company identifier code. */
+    uint8_array_t                data;                                /**< Additional manufacturer specific data. */
+} ble_advdata_manuf_data_t;
+
+/**@brief Service data structure. */
+typedef struct
+{
+    uint16_t                     service_uuid;                        /**< Service UUID. */
+    uint8_array_t                data;                                /**< Additional service data. */
+} ble_advdata_service_data_t;
+
+/**@brief Advertising data structure. This structure contains all options and data needed for encoding and
+ *        setting the advertising data. */
+typedef struct
+{
+    ble_advdata_name_type_t      name_type;                           /**< Type of device name. */
+    uint8_t                      short_name_len;                      /**< Length of short device name (if short type is specified). */
+    bool                         include_appearance;                  /**< Determines if Appearance shall be included. */
+    uint8_t                      flags;                               /**< Advertising data Flags field. */
+    int8_t *                     p_tx_power_level;                    /**< TX Power Level field. */
+    ble_advdata_uuid_list_t      uuids_more_available;                /**< List of UUIDs in the 'More Available' list. */
+    ble_advdata_uuid_list_t      uuids_complete;                      /**< List of UUIDs in the 'Complete' list. */
+    ble_advdata_uuid_list_t      uuids_solicited;                     /**< List of solicited UUIDs. */
+    ble_advdata_conn_int_t *     p_slave_conn_int;                    /**< Slave Connection Interval Range. */
+    ble_advdata_manuf_data_t *   p_manuf_specific_data;               /**< Manufacturer specific data. */
+    ble_advdata_service_data_t * p_service_data_array;                /**< Array of Service data structures. */
+    uint8_t                      service_data_count;                  /**< Number of Service data structures. */
+    bool                         include_ble_device_addr;             /**< Determines if LE Bluetooth Device Address shall be included. */
+    ble_advdata_le_role_t        le_role;                             /**< LE Role field. Included when different from @ref BLE_ADVDATA_ROLE_NOT_PRESENT. @warning This field can be used only for NFC. For BLE advertising, set it to NULL. */
+    ble_advdata_tk_value_t *     p_tk_value;                          /**< Security Manager TK value field. Included when different from NULL. @warning This field can be used only for NFC. For BLE advertising, set it to NULL.*/
+    uint8_t *                    p_sec_mgr_oob_flags;                 /**< Security Manager Out Of Band Flags field. Included when different from NULL. @warning This field can be used only for NFC. For BLE advertising, set it to NULL.*/
+    ble_gap_lesc_oob_data_t *    p_lesc_data;                         /**< LE Secure Connections OOB data. Included when different from NULL. @warning This field can be used only for NFC. For BLE advertising, set it to NULL.*/
+} ble_advdata_t;
+
+/**@brief Function for encoding data in the Advertising and Scan Response data format
+ *        (AD structures).
+ *
+ * @details This function encodes data into the Advertising and Scan Response data format
+ *          (AD structures) based on the selections in the supplied structures. This function can be used to
+ *          create a payload of Advertising packet or Scan Response packet, or a payload of NFC
+ *          message intended for initiating the Out-of-Band pairing.
+ *
+ * @param[in]      p_advdata       Pointer to the structure for specifying the content of encoded data.
+ * @param[out]     p_encoded_data  Pointer to the buffer where encoded data will be returned.
+ * @param[in,out]  p_len           \c in: Size of \p p_encoded_data buffer.
+ *                                 \c out: Length of encoded data.
+ *
+ * @retval NRF_SUCCESS             If the operation was successful.
+ * @retval NRF_ERROR_INVALID_PARAM If the operation failed because a wrong parameter was provided in \p p_advdata.
+ * @retval NRF_ERROR_DATA_SIZE     If the operation failed because not all the requested data could fit into the
+ *                                 provided buffer or some encoded AD structure is too long and its
+ *                                 length cannot be encoded with one octet.
+ *
+ * @warning This API may override the application's request to use the long name and use a short name
+ * instead. This truncation will occur in case the long name does not fit the provided buffer size.
+ * The application can specify a preferred short name length if truncation is required.
+ * For example, if the complete device name is ABCD_HRMonitor, the application can specify the short name
+ * length to be 8, so that the short device name appears as ABCD_HRM instead of ABCD_HRMo or ABCD_HRMoni
+ * if the available size for the short name is 9 or 12 respectively, to have a more appropriate short name.
+ * However, it should be noted that this is just a preference that the application can specify, and
+ * if the preference is too large to fit in the provided buffer, the name can be truncated further.
+ */
+uint32_t adv_data_encode(ble_advdata_t const * const p_advdata,
+                         uint8_t             * const p_encoded_data,
+                         uint16_t            * const p_len);
+
+/**@brief Function for encoding and setting the advertising data and/or scan response data.
+ *
+ * @details This function encodes advertising data and/or scan response data based on the selections
+ *          in the supplied structures, and passes the encoded data to the stack.
+ *
+ * @param[in]   p_advdata   Structure for specifying the content of the advertising data.
+ *                          Set to NULL if advertising data is not to be set.
+ * @param[in]   p_srdata    Structure for specifying the content of the scan response data.
+ *                          Set to NULL if scan response data is not to be set.
+ *
+ * @retval NRF_SUCCESS             If the operation was successful.
+ * @retval NRF_ERROR_INVALID_PARAM If the operation failed because a wrong parameter was provided in \p p_advdata.
+ * @retval NRF_ERROR_DATA_SIZE     If the operation failed because not all the requested data could fit into the
+ *                                 advertising packet. The maximum size of the advertisement packet
+ *                                 is @ref BLE_GAP_ADV_MAX_SIZE.
+ *
+ * @warning This API may override the application's request to use the long name and use a short name
+ * instead. This truncation will occur in case the long name does not fit the provided buffer size.
+ * The application can specify a preferred short name length if truncation is required.
+ * For example, if the complete device name is ABCD_HRMonitor, the application can specify the short name
+ * length to be 8, so that the short device name appears as ABCD_HRM instead of ABCD_HRMo or ABCD_HRMoni
+ * if the available size for the short name is 9 or 12 respectively, to have a more appropriate short name.
+ * However, it should be noted that this is just a preference that the application can specify, and
+ * if the preference is too large to fit in the provided buffer, the name can be truncated further.
+ */
+uint32_t ble_advdata_set(const ble_advdata_t * p_advdata, const ble_advdata_t * p_srdata);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // BLE_ADVDATA_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_conn_params.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,146 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup ble_sdk_lib_conn_params Connection Parameters Negotiation
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Module for initiating and executing a connection parameters negotiation procedure.
+ */
+
+#ifndef BLE_CONN_PARAMS_H__
+#define BLE_CONN_PARAMS_H__
+
+#include <stdint.h>
+#include "headers/ble.h"
+#include "ble_srv_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Connection Parameters Module event type. */
+typedef enum
+{
+    BLE_CONN_PARAMS_EVT_FAILED   ,                                  /**< Negotiation procedure failed. */
+    BLE_CONN_PARAMS_EVT_SUCCEEDED                                   /**< Negotiation procedure succeeded. */
+} ble_conn_params_evt_type_t;
+
+/**@brief Connection Parameters Module event. */
+typedef struct
+{
+    ble_conn_params_evt_type_t evt_type;                            /**< Type of event. */
+} ble_conn_params_evt_t;
+
+/**@brief Connection Parameters Module event handler type. */
+typedef void (*ble_conn_params_evt_handler_t) (ble_conn_params_evt_t * p_evt);
+
+/**@brief Connection Parameters Module init structure. This contains all options and data needed for
+ *        initialization of the connection parameters negotiation module. */
+typedef struct
+{
+    ble_gap_conn_params_t *       p_conn_params;                    /**< Pointer to the connection parameters desired by the application. When calling ble_conn_params_init, if this parameter is set to NULL, the connection parameters will be fetched from host. */
+    uint32_t                      first_conn_params_update_delay;   /**< Time from initiating event (connect or start of notification) to first time sd_ble_gap_conn_param_update is called (in number of timer ticks). */
+    uint32_t                      next_conn_params_update_delay;    /**< Time between each call to sd_ble_gap_conn_param_update after the first (in number of timer ticks). Recommended value 30 seconds as per BLUETOOTH SPECIFICATION Version 4.0. */
+    uint8_t                       max_conn_params_update_count;     /**< Number of attempts before giving up the negotiation. */
+    uint16_t                      start_on_notify_cccd_handle;      /**< If procedure is to be started when notification is started, set this to the handle of the corresponding CCCD. Set to BLE_GATT_HANDLE_INVALID if procedure is to be started on connect event. */
+    bool                          disconnect_on_fail;               /**< Set to TRUE if a failed connection parameters update shall cause an automatic disconnection, set to FALSE otherwise. */
+    ble_conn_params_evt_handler_t evt_handler;                      /**< Event handler to be called for handling events in the Connection Parameters. */
+    ble_srv_error_handler_t       error_handler;                    /**< Function to be called in case of an error. */
+} ble_conn_params_init_t;
+
+
+/**@brief Function for initializing the Connection Parameters module.
+ *
+ * @note If the negotiation procedure should be triggered when notification/indication of
+ *       any characteristic is enabled by the peer, then this function must be called after
+ *       having initialized the services.
+ *
+ * @param[in]   p_init  This contains information needed to initialize this module.
+ *
+ * @return      NRF_SUCCESS on successful initialization, otherwise an error code.
+ */
+uint32_t ble_conn_params_init(const ble_conn_params_init_t * p_init);
+
+/**@brief Function for stopping the Connection Parameters module.
+ *
+ * @details This function is intended to be used by the application to clean up the connection
+ *          parameters update module. This will stop the connection parameters update timer if
+ *          running, thereby preventing any impending connection parameters update procedure. This
+ *          function must be called by the application when it needs to clean itself up (for
+ *          example, before disabling the bluetooth SoftDevice) so that an unwanted timer expiry
+ *          event can be avoided.
+ *
+ * @return      NRF_SUCCESS on successful initialization, otherwise an error code.
+ */
+uint32_t ble_conn_params_stop(void);
+
+/**@brief Function for changing the current connection parameters to a new set.
+ *
+ *  @details Use this function to change the connection parameters to a new set of parameter
+ *       (ie different from the ones given at init of the module).
+ *       This function is usefull for scenario where most of the time the application
+ *       needs a relatively big connection interval, and just sometimes, for a temporary
+ *       period requires shorter connection interval, for example to transfer a higher
+ *       amount of data.
+ *       If the given parameters does not match the current connection's parameters
+ *       this function initiates a new negotiation.
+ *
+ * @param[in]   new_params  This contains the new connections parameters to setup.
+ *
+ * @return      NRF_SUCCESS on successful initialization, otherwise an error code.
+ */
+uint32_t ble_conn_params_change_conn_params(ble_gap_conn_params_t *new_params);
+
+/**@brief Function for handling the Application's BLE Stack events.
+ *
+ * @details Handles all events from the BLE stack that are of interest to this module.
+ *
+ * @param[in]   p_ble_evt  The event received from the BLE stack.
+ */
+void ble_conn_params_on_ble_evt(ble_evt_t * p_ble_evt);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // BLE_CONN_PARAMS_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_conn_state.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,413 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "ble_conn_state.h"
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include "headers/ble.h"
+#include "sdk_mapped_flags.h"
+#include "app_error.h"
+
+
+#if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__ICCARM__)
+  #pragma language=extended
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#endif
+
+
+#define BLE_CONN_STATE_N_DEFAULT_FLAGS 5                                                       /**< The number of flags kept for each connection, excluding user flags. */
+#define BLE_CONN_STATE_N_FLAGS (BLE_CONN_STATE_N_DEFAULT_FLAGS + BLE_CONN_STATE_N_USER_FLAGS)  /**< The number of flags kept for each connection, including user flags. */
+
+
+/**@brief Structure containing all the flag collections maintained by the Connection State module.
+ */
+typedef struct
+{
+    sdk_mapped_flags_t valid_flags;                                 /**< Flags indicating which connection handles are valid. */
+    sdk_mapped_flags_t connected_flags;                             /**< Flags indicating which connections are connected, since disconnected connection handles will not immediately be invalidated. */
+    sdk_mapped_flags_t central_flags;                               /**< Flags indicating in which connections the local device is the central. */
+    sdk_mapped_flags_t encrypted_flags;                             /**< Flags indicating which connections are encrypted. */
+    sdk_mapped_flags_t mitm_protected_flags;                        /**< Flags indicating which connections have encryption with protection from man-in-the-middle attacks. */
+    sdk_mapped_flags_t user_flags[BLE_CONN_STATE_N_USER_FLAGS];     /**< Flags that can be reserved by the user. The flags will be cleared when a connection is invalidated, otherwise, the user is wholly responsible for the flag states. */
+} ble_conn_state_flag_collections_t;
+
+
+/**@brief Structure containing the internal state of the Connection State module.
+ */
+typedef struct
+{
+    uint32_t           acquired_flags;                              /**< Bitmap for keeping track of which user flags have been acquired. */
+    uint16_t           valid_conn_handles[SDK_MAPPED_FLAGS_N_KEYS]; /**< List of connection handles used as keys for the sdk_mapped_flags module. */
+    union
+    {
+        ble_conn_state_flag_collections_t flags;                              /**< Flag collections kept by the Connection State module. */
+        sdk_mapped_flags_t                flag_array[BLE_CONN_STATE_N_FLAGS]; /**< Flag collections as array to allow use of @ref sdk_mapped_flags_bulk_update_by_key() when setting all flags. */
+    };
+} ble_conn_state_t;
+
+
+#if defined(__CC_ARM)
+  #pragma pop
+#elif defined(__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#endif
+
+
+static ble_conn_state_t m_bcs = {0}; /**< Instantiation of the internal state. */
+
+
+/**@brief Function for resetting all internal memory to the values it had at initialization.
+ */
+void bcs_internal_state_reset(void)
+{
+    memset( &m_bcs, 0, sizeof(ble_conn_state_t) );
+}
+
+
+/**@brief Function for activating a connection record.
+ *
+ * @param p_record     The record to activate.
+ * @param conn_handle  The connection handle to copy into the record.
+ * @param role         The role of the connection.
+ *
+ * @return whether the record was activated successfully.
+ */
+static bool record_activate(uint16_t conn_handle)
+{
+    uint16_t available_index = sdk_mapped_flags_first_key_index_get(~m_bcs.flags.valid_flags);
+
+    if (available_index != SDK_MAPPED_FLAGS_INVALID_INDEX)
+    {
+        m_bcs.valid_conn_handles[available_index] = conn_handle;
+        sdk_mapped_flags_update_by_key(m_bcs.valid_conn_handles,
+                                      &m_bcs.flags.connected_flags,
+                                       conn_handle,
+                                       1);
+        sdk_mapped_flags_update_by_key(m_bcs.valid_conn_handles,
+                                      &m_bcs.flags.valid_flags,
+                                       conn_handle,
+                                       1);
+
+        return true;
+    }
+
+    return false;
+}
+
+
+/**@brief Function for marking a connection record as invalid and resetting the values.
+ *
+ * @param p_record  The record to invalidate.
+ */
+static void record_invalidate(uint16_t conn_handle)
+{
+    sdk_mapped_flags_bulk_update_by_key(m_bcs.valid_conn_handles,
+                                        m_bcs.flag_array,
+                                        BLE_CONN_STATE_N_FLAGS,
+                                        conn_handle,
+                                        0);
+}
+
+
+/**@brief Function for marking a connection as disconnected. See @ref BLE_CONN_STATUS_DISCONNECTED.
+ *
+ * @param p_record   The record of the connection to set as disconnected.
+ */
+static void record_set_disconnected(uint16_t conn_handle)
+{
+    sdk_mapped_flags_update_by_key(m_bcs.valid_conn_handles,
+                                  &m_bcs.flags.connected_flags,
+                                   conn_handle,
+                                   0);
+}
+
+
+/**@brief Function for invalidating records with a @ref BLE_CONN_STATUS_DISCONNECTED
+ *        connection status
+ */
+static void record_purge_disconnected()
+{
+    sdk_mapped_flags_key_list_t disconnected_list;
+
+    disconnected_list = sdk_mapped_flags_key_list_get(
+                                   m_bcs.valid_conn_handles,
+                                 (~m_bcs.flags.connected_flags) & (m_bcs.flags.valid_flags));
+
+    for (uint32_t i = 0; i < disconnected_list.len; i++)
+    {
+        record_invalidate(disconnected_list.flag_keys[i]);
+    }
+}
+
+
+/**@brief Function for checking if a user flag has been acquired.
+ *
+ * @param[in]  flag_id  Which flag to check.
+ *
+ * @return  Whether the flag has been acquired.
+ */
+static bool user_flag_is_acquired(ble_conn_state_user_flag_id_t flag_id)
+{
+    return ((m_bcs.acquired_flags & (1 << flag_id)) != 0);
+}
+
+
+/**@brief Function for marking a user flag as acquired.
+ *
+ * @param[in]  flag_id  Which flag to mark.
+ */
+static void user_flag_acquire(ble_conn_state_user_flag_id_t flag_id)
+{
+    m_bcs.acquired_flags |= (1 << flag_id);
+}
+
+
+void ble_conn_state_init(void)
+{
+    bcs_internal_state_reset();
+}
+
+
+void ble_conn_state_on_ble_evt(ble_evt_t * p_ble_evt)
+{
+    switch (p_ble_evt->header.evt_id)
+    {
+        case BLE_GAP_EVT_CONNECTED:
+            record_purge_disconnected();
+
+            if ( !record_activate(p_ble_evt->evt.gap_evt.conn_handle) )
+            {
+                // No more records available. Should not happen.
+                APP_ERROR_HANDLER(NRF_ERROR_NO_MEM);
+            }
+            else
+            {
+                bool is_central =
+                        (p_ble_evt->evt.gap_evt.params.connected.role == BLE_GAP_ROLE_CENTRAL);
+
+                sdk_mapped_flags_update_by_key(m_bcs.valid_conn_handles,
+                                              &m_bcs.flags.central_flags,
+                                               p_ble_evt->evt.gap_evt.conn_handle,
+                                               is_central);
+            }
+
+            break;
+
+        case BLE_GAP_EVT_DISCONNECTED:
+            record_set_disconnected(p_ble_evt->evt.gap_evt.conn_handle);
+            break;
+
+        case BLE_GAP_EVT_CONN_SEC_UPDATE:
+            sdk_mapped_flags_update_by_key(
+                          m_bcs.valid_conn_handles,
+                         &m_bcs.flags.encrypted_flags,
+                          p_ble_evt->evt.gap_evt.conn_handle,
+                         (p_ble_evt->evt.gap_evt.params.conn_sec_update.conn_sec.sec_mode.lv > 1));
+            sdk_mapped_flags_update_by_key(
+                          m_bcs.valid_conn_handles,
+                         &m_bcs.flags.mitm_protected_flags,
+                          p_ble_evt->evt.gap_evt.conn_handle,
+                         (p_ble_evt->evt.gap_evt.params.conn_sec_update.conn_sec.sec_mode.lv > 2));
+            break;
+    }
+}
+
+
+bool ble_conn_state_valid(uint16_t conn_handle)
+{
+    return sdk_mapped_flags_get_by_key(m_bcs.valid_conn_handles,
+                                       m_bcs.flags.valid_flags,
+                                       conn_handle);
+}
+
+
+uint8_t ble_conn_state_role(uint16_t conn_handle)
+{
+    uint8_t role = BLE_GAP_ROLE_INVALID;
+
+    if ( sdk_mapped_flags_get_by_key(m_bcs.valid_conn_handles, m_bcs.flags.valid_flags, conn_handle) )
+    {
+        bool central = sdk_mapped_flags_get_by_key(m_bcs.valid_conn_handles,
+                                                   m_bcs.flags.central_flags,
+                                                   conn_handle);
+
+        role = central ? BLE_GAP_ROLE_CENTRAL : BLE_GAP_ROLE_PERIPH;
+    }
+
+    return role;
+}
+
+
+ble_conn_state_status_t ble_conn_state_status(uint16_t conn_handle)
+{
+    ble_conn_state_status_t conn_status = BLE_CONN_STATUS_INVALID;
+    bool valid = sdk_mapped_flags_get_by_key(m_bcs.valid_conn_handles,
+                                             m_bcs.flags.valid_flags,
+                                             conn_handle);
+
+    if (valid)
+    {
+        bool connected = sdk_mapped_flags_get_by_key(m_bcs.valid_conn_handles,
+                                                     m_bcs.flags.connected_flags,
+                                                     conn_handle);
+
+        conn_status = connected ? BLE_CONN_STATUS_CONNECTED : BLE_CONN_STATUS_DISCONNECTED;
+    }
+
+    return conn_status;
+}
+
+
+bool ble_conn_state_encrypted(uint16_t conn_handle)
+{
+    return sdk_mapped_flags_get_by_key(m_bcs.valid_conn_handles,
+                                       m_bcs.flags.encrypted_flags,
+                                       conn_handle);
+}
+
+
+bool ble_conn_state_mitm_protected(uint16_t conn_handle)
+{
+    return sdk_mapped_flags_get_by_key(m_bcs.valid_conn_handles,
+                                       m_bcs.flags.mitm_protected_flags,
+                                       conn_handle);
+}
+
+
+uint32_t ble_conn_state_n_connections(void)
+{
+    return sdk_mapped_flags_n_flags_set(m_bcs.flags.connected_flags);
+}
+
+
+uint32_t ble_conn_state_n_centrals(void)
+{
+    return sdk_mapped_flags_n_flags_set((m_bcs.flags.central_flags) & (m_bcs.flags.connected_flags));
+}
+
+
+uint32_t ble_conn_state_n_peripherals(void)
+{
+    return sdk_mapped_flags_n_flags_set((~m_bcs.flags.central_flags) & (m_bcs.flags.connected_flags));
+}
+
+
+sdk_mapped_flags_key_list_t ble_conn_state_conn_handles(void)
+{
+    return sdk_mapped_flags_key_list_get(m_bcs.valid_conn_handles, m_bcs.flags.valid_flags);
+}
+
+
+sdk_mapped_flags_key_list_t ble_conn_state_central_handles(void)
+{
+    return sdk_mapped_flags_key_list_get(m_bcs.valid_conn_handles,
+                                        (m_bcs.flags.central_flags) & (m_bcs.flags.connected_flags));
+}
+
+
+sdk_mapped_flags_key_list_t ble_conn_state_periph_handles(void)
+{
+    return sdk_mapped_flags_key_list_get(m_bcs.valid_conn_handles,
+                                        (~m_bcs.flags.central_flags) & (m_bcs.flags.connected_flags));
+}
+
+
+ble_conn_state_user_flag_id_t ble_conn_state_user_flag_acquire(void)
+{
+    for (ble_conn_state_user_flag_id_t i = BLE_CONN_STATE_USER_FLAG0;
+                                       i < BLE_CONN_STATE_N_USER_FLAGS;
+                                       i++)
+    {
+        if ( !user_flag_is_acquired(i) )
+        {
+            user_flag_acquire(i);
+            return i;
+        }
+    }
+
+    return BLE_CONN_STATE_USER_FLAG_INVALID;
+}
+
+
+bool ble_conn_state_user_flag_get(uint16_t conn_handle, ble_conn_state_user_flag_id_t flag_id)
+{
+    if (user_flag_is_acquired(flag_id))
+    {
+        return sdk_mapped_flags_get_by_key(m_bcs.valid_conn_handles,
+                                           m_bcs.flags.user_flags[flag_id],
+                                           conn_handle);
+    }
+    else
+    {
+        return false;
+    }
+}
+
+
+void ble_conn_state_user_flag_set(uint16_t                      conn_handle,
+                                  ble_conn_state_user_flag_id_t flag_id,
+                                  bool                          value)
+{
+    if (user_flag_is_acquired(flag_id))
+    {
+        sdk_mapped_flags_update_by_key(m_bcs.valid_conn_handles,
+                                      &m_bcs.flags.user_flags[flag_id],
+                                       conn_handle,
+                                       value);
+    }
+}
+
+
+sdk_mapped_flags_t ble_conn_state_user_flag_collection(ble_conn_state_user_flag_id_t flag_id)
+{
+    if ( user_flag_is_acquired(flag_id) )
+    {
+        return m_bcs.flags.user_flags[flag_id];
+    }
+    else
+    {
+        return 0;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_conn_state.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,310 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @file
+ *
+ * @defgroup ble_conn_state Connection state
+ * @ingroup ble_sdk_lib
+ * @{
+ * @brief Module for storing data on BLE connections.
+ *
+ * @details This module stores certain states for each connection, which can be queried by
+ *          connection handle. The module uses BLE events to keep the states updated.
+ *
+ *          In addition to the preprogrammed states, this module can also keep track of a number of
+ *          binary user states, or <i>user flags</i>. These are reset to 0 for new connections, but
+ *          otherwise not touched by this module.
+ *
+ *          This module uses the @ref sdk_mapped_flags module, with connection handles as keys and
+ *          the connection states as flags.
+ *
+ * @note A connection handle is not immediately invalidated when it is disconnected. Certain states,
+ *       such as the role, can still be queried until the next time a new connection is established
+ *       to any device.
+ *
+ *          To function properly, this module must be provided with BLE events from the SoftDevice
+ *          through the @ref ble_conn_state_on_ble_evt() function. This module should be the first
+ *          to receive BLE events if they are dispatched to multiple modules.
+ */
+
+#ifndef BLE_CONN_STATE_H__
+#define BLE_CONN_STATE_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "headers/ble.h"
+#include "sdk_mapped_flags.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Connection handle statuses.
+ */
+typedef enum
+{
+    BLE_CONN_STATUS_INVALID,       /**< The connection handle is invalid. */
+    BLE_CONN_STATUS_DISCONNECTED,  /**< The connection handle refers to a connection that has been disconnected, but not yet invalidated. */
+    BLE_CONN_STATUS_CONNECTED,     /**< The connection handle refers to an active connection. */
+} ble_conn_state_status_t;
+
+#define BLE_CONN_STATE_N_USER_FLAGS 24  /**< The number of available user flags. */
+
+
+/**@brief One ID for each user flag collection.
+ *
+ * @details These IDs are used to identify user flag collections in the API calls.
+ */
+typedef enum
+{
+    BLE_CONN_STATE_USER_FLAG0 = 0,
+    BLE_CONN_STATE_USER_FLAG1,
+    BLE_CONN_STATE_USER_FLAG2,
+    BLE_CONN_STATE_USER_FLAG3,
+    BLE_CONN_STATE_USER_FLAG4,
+    BLE_CONN_STATE_USER_FLAG5,
+    BLE_CONN_STATE_USER_FLAG6,
+    BLE_CONN_STATE_USER_FLAG7,
+    BLE_CONN_STATE_USER_FLAG8,
+    BLE_CONN_STATE_USER_FLAG9,
+    BLE_CONN_STATE_USER_FLAG10,
+    BLE_CONN_STATE_USER_FLAG11,
+    BLE_CONN_STATE_USER_FLAG12,
+    BLE_CONN_STATE_USER_FLAG13,
+    BLE_CONN_STATE_USER_FLAG14,
+    BLE_CONN_STATE_USER_FLAG15,
+    BLE_CONN_STATE_USER_FLAG16,
+    BLE_CONN_STATE_USER_FLAG17,
+    BLE_CONN_STATE_USER_FLAG18,
+    BLE_CONN_STATE_USER_FLAG19,
+    BLE_CONN_STATE_USER_FLAG20,
+    BLE_CONN_STATE_USER_FLAG21,
+    BLE_CONN_STATE_USER_FLAG22,
+    BLE_CONN_STATE_USER_FLAG23,
+    BLE_CONN_STATE_USER_FLAG_INVALID,
+} ble_conn_state_user_flag_id_t;
+
+
+/**
+ * @defgroup ble_conn_state_functions BLE connection state functions
+ * @{
+ */
+
+
+/**@brief Function for initializing or resetting the module.
+ *
+ * @details This function sets all states to their default, removing all records of connection handles.
+ */
+void ble_conn_state_init(void);
+
+
+/**@brief Function for providing BLE SoftDevice events to the connection state module.
+ *
+ * @param[in]  p_ble_evt    The SoftDevice event.
+ */
+void ble_conn_state_on_ble_evt(ble_evt_t * p_ble_evt);
+
+
+/**@brief Function for querying whether a connection handle represents a valid connection.
+ *
+ * @details A connection might be valid and have a BLE_CONN_STATUS_DISCONNECTED status.
+ *          Those connections are invalidated after a new connection occurs.
+ *
+ * @param[in]  conn_handle  Handle of the connection.
+ *
+ * @retval true   If conn_handle represents a valid connection, thus a connection for which
+                  we have a record.
+ * @retval false  If conn_handle is @ref BLE_GAP_ROLE_INVALID, or if it has never been recorded.
+ */
+bool ble_conn_state_valid(uint16_t conn_handle);
+
+
+/**@brief Function for querying the role of the local device in a connection.
+ *
+ * @param[in]  conn_handle  Handle of the connection to get the role for.
+ *
+ * @return  The role of the local device in the connection (see @ref BLE_GAP_ROLES).
+ *          If conn_handle is not valid, the function returns BLE_GAP_ROLE_INVALID.
+ */
+uint8_t ble_conn_state_role(uint16_t conn_handle);
+
+
+/**@brief Function for querying the status of a connection.
+ *
+ * @param[in]  conn_handle  Handle of the connection.
+ *
+ * @return  The status of the connection.
+ *          If conn_handle is not valid, the function returns BLE_CONN_STATE_INVALID.
+ */
+ble_conn_state_status_t ble_conn_state_status(uint16_t conn_handle);
+
+
+/**@brief Function for querying whether a connection is encrypted.
+ *
+ * @param[in]  conn_handle  Handle of connection to get the encryption state for.
+ *
+ * @retval true   If the connection is encrypted.
+ * @retval false  If the connection is not encrypted or conn_handle is invalid.
+ */
+bool ble_conn_state_encrypted(uint16_t conn_handle);
+
+
+/**@brief Function for querying whether a connection encryption is protected from Man in the Middle
+ *        attacks.
+ *
+ * @param[in]  conn_handle  Handle of connection to get the MITM state for.
+ *
+ * @retval true   If the connection is encrypted with MITM protection.
+ * @retval false  If the connection is not encrypted, or encryption is not MITM protected, or
+ *                conn_handle is invalid.
+ */
+bool ble_conn_state_mitm_protected(uint16_t conn_handle);
+
+
+/**@brief Function for querying the total number of connections.
+ *
+ * @return  The total number of valid connections for which the module has a record.
+ */
+uint32_t ble_conn_state_n_connections(void);
+
+
+/**@brief Function for querying the total number of connections in which the role of the local
+ *        device is @ref BLE_GAP_ROLE_CENTRAL.
+ *
+ * @return  The number of connections in which the role of the local device is
+ *          @ref BLE_GAP_ROLE_CENTRAL.
+ */
+uint32_t ble_conn_state_n_centrals(void);
+
+
+/**@brief Function for querying the total number of connections in which the role of the local
+ *        device is @ref BLE_GAP_ROLE_PERIPH.
+ *
+ * @return  The number of connections in which the role of the local device is
+ *          @ref BLE_GAP_ROLE_PERIPH.
+ */
+uint32_t ble_conn_state_n_peripherals(void);
+
+
+/**@brief Function for obtaining a list of all connection handles for which the module has a record.
+ *
+ * @details This function takes into account connections whose state is BLE_CONN_STATUS_DISCONNECTED.
+ *
+ * @return  A list of all valid connection handles for which the module has a record.
+ */
+sdk_mapped_flags_key_list_t ble_conn_state_conn_handles(void);
+
+
+/**@brief Function for obtaining a list of connection handles in which the role of the local
+ *        device is @ref BLE_GAP_ROLE_CENTRAL.
+ *
+ * @details This function takes into account connections whose state is BLE_CONN_STATUS_DISCONNECTED.
+ *
+ * @return  A list of all valid connection handles for which the module has a record and in which
+ *          the role of local device is @ref BLE_GAP_ROLE_CENTRAL.
+ */
+sdk_mapped_flags_key_list_t ble_conn_state_central_handles(void);
+
+
+/**@brief Function for obtaining the handle for the connection in which the role of the local device
+ *        is @ref BLE_GAP_ROLE_PERIPH.
+ *
+ * @details This function takes into account connections whose state is BLE_CONN_STATUS_DISCONNECTED.
+ *
+ * @return  A list of all valid connection handles for which the module has a record and in which
+ *          the role of local device is @ref BLE_GAP_ROLE_PERIPH.
+ */
+sdk_mapped_flags_key_list_t ble_conn_state_periph_handles(void);
+
+
+/**@brief Function for obtaining exclusive access to one of the user flag collections.
+ *
+ * @details The acquired collection contains one flag for each connection. These flags can be set
+ *          and read individually for each connection.
+ *
+ *          The state of user flags will not be modified by the connection state module, except to
+ *          set it to 0 for a connection when that connection is invalidated.
+ *
+ * @return  The ID of the acquired flag, or BLE_CONN_STATE_USER_FLAG_INVALID if none are available.
+ */
+ble_conn_state_user_flag_id_t ble_conn_state_user_flag_acquire(void);
+
+
+/**@brief Function for reading the value of a user flag.
+ *
+ * @param[in]  conn_handle  Handle of connection to get the flag state for.
+ * @param[in]  flag_id      Which flag to get the state for.
+ *
+ * @return  The state of the flag. If conn_handle is invalid, the function returns false.
+ */
+bool ble_conn_state_user_flag_get(uint16_t conn_handle, ble_conn_state_user_flag_id_t flag_id);
+
+
+/**@brief Function for setting the value of a user flag.
+ *
+ * @param[in]  conn_handle  Handle of connection to set the flag state for.
+ * @param[in]  flag_id      Which flag to set the state for.
+ * @param[in]  value        Value to set the flag state to.
+ */
+void ble_conn_state_user_flag_set(uint16_t                      conn_handle,
+                                  ble_conn_state_user_flag_id_t flag_id,
+                                  bool                          value);
+
+
+/**@brief Function for getting the state of a user flag for all connection handles.
+ *
+ * @details The returned collection can be used with the @ref sdk_mapped_flags API. The returned
+ *          collection is a copy, so modifying it has no effect on the conn_state module.
+ *
+ * @param[in]  flag_id  Which flag to get states for.
+ *
+ * @return  The collection of flag states. The collection is always all zeros when the flag_id is
+ *          unregistered.
+ */
+sdk_mapped_flags_t ble_conn_state_user_flag_collection(ble_conn_state_user_flag_id_t flag_id);
+
+/** @} */
+/** @} */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BLE_CONN_STATE_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_date_time.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,112 @@
+/* 
+ * Copyright (c) 2011 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/* Attention!
+*  To maintain compliance with Nordic Semiconductor ASA’s Bluetooth profile
+*  qualification listings, this section of source code must not be modified.
+*/
+
+/** @file
+ * @brief Contains definition of ble_date_time structure.
+ */
+
+/** @file
+ *
+ * @defgroup ble_sdk_srv_date_time BLE Date Time characteristic type
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Definition of ble_date_time_t type.
+ */
+
+#ifndef BLE_DATE_TIME_H__
+#define BLE_DATE_TIME_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Date and Time structure. */
+typedef struct
+{
+    uint16_t year;
+    uint8_t  month;
+    uint8_t  day;
+    uint8_t  hours;
+    uint8_t  minutes;
+    uint8_t  seconds;
+} ble_date_time_t;
+
+static __INLINE uint8_t ble_date_time_encode(const ble_date_time_t * p_date_time,
+                                             uint8_t *               p_encoded_data)
+{
+    uint8_t len = uint16_encode(p_date_time->year, p_encoded_data);
+
+    p_encoded_data[len++] = p_date_time->month;
+    p_encoded_data[len++] = p_date_time->day;
+    p_encoded_data[len++] = p_date_time->hours;
+    p_encoded_data[len++] = p_date_time->minutes;
+    p_encoded_data[len++] = p_date_time->seconds;
+
+    return len;
+}
+
+static __INLINE uint8_t ble_date_time_decode(ble_date_time_t * p_date_time,
+                                             const uint8_t *   p_encoded_data)
+{
+    uint8_t len = sizeof(uint16_t);
+
+    p_date_time->year    = uint16_decode(p_encoded_data);
+    p_date_time->month   = p_encoded_data[len++];
+    p_date_time->day     = p_encoded_data[len++];
+    p_date_time->hours   = p_encoded_data[len++];
+    p_date_time->minutes = p_encoded_data[len++];
+    p_date_time->seconds = p_encoded_data[len++];
+
+    return len;
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // BLE_DATE_TIME_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_gatt_db.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,88 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ /**@file
+ *
+ * @defgroup ble_sdk_lib_gatt_db GATT Database Service Structure
+ * @{
+ * @ingroup  app_common
+ */
+
+#ifndef BLE_GATT_DB_H__
+#define BLE_GATT_DB_H__
+
+#include <stdint.h>
+#include "headers/ble.h"
+#include "ble_gattc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BLE_GATT_DB_MAX_CHARS 5        /**< The maximum number of characteristics present in a service record. */
+
+/**@brief Structure for holding the characteristic and the handle of its CCCD present on a server.
+ */
+typedef struct
+{
+    ble_gattc_char_t characteristic;    /**< Structure containing information about the characteristic. */
+    uint16_t         cccd_handle;       /**< CCCD Handle value for this characteristic. This will be set to BLE_GATT_HANDLE_INVALID if a CCCD is not present at the server. */
+    uint16_t         ext_prop_handle;   /**< Extended Properties Handle value for this characteristic. This will be set to BLE_GATT_HANDLE_INVALID if an Extended Properties descriptor is not present at the server. */
+    uint16_t         user_desc_handle;  /**< User Description Handle value for this characteristic. This will be set to BLE_GATT_HANDLE_INVALID if a User Description descriptor is not present at the server. */
+    uint16_t         report_ref_handle; /**< Report Refence Handle value for this characteristic. This will be set to BLE_GATT_HANDLE_INVALID if a Report Reference descriptor is not present at the server. */
+} ble_gatt_db_char_t;
+
+/**@brief Structure for holding information about the service and the characteristics present on a
+ *        server.
+ */
+typedef struct
+{
+    ble_uuid_t               srv_uuid;                                  /**< UUID of the service. */
+    uint8_t                  char_count;                                /**< Number of characteristics present in the service. */
+    ble_gattc_handle_range_t handle_range;                              /**< Service Handle Range. */
+    ble_gatt_db_char_t       charateristics[BLE_GATT_DB_MAX_CHARS];     /**< Array of information related to the characteristics present in the service. This list can extend further than one. */
+} ble_gatt_db_srv_t;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BLE_GATT_DB_H__ */
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_sensor_location.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,75 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ /* Attention!
+*  To maintain compliance with Nordic Semiconductor ASA’s Bluetooth profile
+*  qualification listings, this section of source code must not be modified.
+*/
+
+#ifndef BLE_SENSOR_LOCATION_H__
+#define BLE_SENSOR_LOCATION_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    BLE_SENSOR_LOCATION_OTHER        = 0 ,  /**<-- Other        */
+    BLE_SENSOR_LOCATION_TOP_OF_SHOE  = 1 ,  /**<-- Top of shoe  */
+    BLE_SENSOR_LOCATION_IN_SHOE      = 2 ,  /**<-- In shoe      */
+    BLE_SENSOR_LOCATION_HIP          = 3 ,  /**<-- Hip          */
+    BLE_SENSOR_LOCATION_FRONT_WHEEL  = 4 ,  /**<-- Front Wheel  */
+    BLE_SENSOR_LOCATION_LEFT_CRANK   = 5 ,  /**<-- Left Crank   */
+    BLE_SENSOR_LOCATION_RIGHT_CRANK  = 6 ,  /**<-- Right Crank  */
+    BLE_SENSOR_LOCATION_LEFT_PEDAL   = 7 ,  /**<-- Left Pedal   */
+    BLE_SENSOR_LOCATION_RIGHT_PEDAL  = 8 ,  /**<-- Right Pedal  */
+    BLE_SENSOR_LOCATION_FRONT_HUB    = 9 ,  /**<-- Front Hub    */
+    BLE_SENSOR_LOCATION_REAR_DROPOUT = 10,  /**<-- Rear Dropout */
+    BLE_SENSOR_LOCATION_CHAINSTAY    = 11,  /**<-- Chainstay    */
+    BLE_SENSOR_LOCATION_REAR_WHEEL   = 12,  /**<-- Rear Wheel   */
+    BLE_SENSOR_LOCATION_REAR_HUB     = 13,  /**<-- Rear Hub     */
+}ble_sensor_location_t;
+
+#define BLE_NB_MAX_SENSOR_LOCATIONS 14
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // BLE_SENSOR_LOCATION_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_srv_common.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,236 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/* Attention!
+*  To maintain compliance with Nordic Semiconductor ASA’s Bluetooth profile
+*  qualification listings, this section of source code must not be modified.
+*/
+
+#include "ble_srv_common.h"
+#include <string.h>
+#include "nordic_common.h"
+#include "app_error.h"
+#include "headers/ble.h"
+
+bool ble_srv_is_notification_enabled(uint8_t const * p_encoded_data)
+{
+    uint16_t cccd_value = uint16_decode(p_encoded_data);
+    return ((cccd_value & BLE_GATT_HVX_NOTIFICATION) != 0);
+}
+
+bool ble_srv_is_indication_enabled(uint8_t const * p_encoded_data)
+{
+    uint16_t cccd_value = uint16_decode(p_encoded_data);
+    return ((cccd_value & BLE_GATT_HVX_INDICATION) != 0);
+}
+
+uint8_t ble_srv_report_ref_encode(uint8_t                    * p_encoded_buffer,
+                                  const ble_srv_report_ref_t * p_report_ref)
+{
+    uint8_t len = 0;
+
+    p_encoded_buffer[len++] = p_report_ref->report_id;
+    p_encoded_buffer[len++] = p_report_ref->report_type;
+
+    APP_ERROR_CHECK_BOOL(len == BLE_SRV_ENCODED_REPORT_REF_LEN);
+    return len;
+}
+
+
+void ble_srv_ascii_to_utf8(ble_srv_utf8_str_t * p_utf8, char * p_ascii)
+{
+    p_utf8->length = (uint16_t)strlen(p_ascii);
+    p_utf8->p_str  = (uint8_t *)p_ascii;
+}
+
+
+/**@brief Function for setting security requirements of a characteristic.
+ *
+ * @param[in]  level   required security level.
+ * @param[out] p_perm  Characteristic security requirements.
+ *
+ * @return     encoded security level and security mode.
+ */
+static inline void set_security_req(security_req_t level, ble_gap_conn_sec_mode_t * p_perm)
+{
+
+
+    BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(p_perm);
+    switch (level)
+    {
+        case SEC_NO_ACCESS:
+            BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(p_perm);
+        break;
+        case SEC_OPEN:
+            BLE_GAP_CONN_SEC_MODE_SET_OPEN(p_perm);
+        break;
+        case SEC_JUST_WORKS:
+            BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(p_perm);
+        break;
+        case SEC_MITM:
+            BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(p_perm);
+        break;
+        case SEC_SIGNED:
+            BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(p_perm);
+        break;
+        case SEC_SIGNED_MITM:
+            BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(p_perm);
+        break;
+    }
+    return;
+}
+
+
+uint32_t characteristic_add(uint16_t                   service_handle,
+                            ble_add_char_params_t *    p_char_props,
+                            ble_gatts_char_handles_t * p_char_handle)
+{
+    ble_gatts_char_md_t char_md;
+    ble_gatts_attr_t    attr_char_value;
+    ble_uuid_t          char_uuid;
+    ble_gatts_attr_md_t attr_md;
+    ble_gatts_attr_md_t user_descr_attr_md;
+    ble_gatts_attr_md_t cccd_md;
+
+    if (p_char_props->uuid_type == 0)
+    {
+        char_uuid.type = BLE_UUID_TYPE_BLE;
+    }
+    else
+    {
+        char_uuid.type = p_char_props->uuid_type;
+    }
+    char_uuid.uuid = p_char_props->uuid;
+
+    memset(&attr_md, 0, sizeof(ble_gatts_attr_md_t));
+    set_security_req(p_char_props->read_access, &attr_md.read_perm);
+    set_security_req(p_char_props->write_access, & attr_md.write_perm);
+    attr_md.rd_auth    = (p_char_props->is_defered_read ? 1 : 0);
+    attr_md.wr_auth    = (p_char_props->is_defered_write ? 1 : 0);
+    attr_md.vlen       = (p_char_props->is_var_len ? 1 : 0);
+    attr_md.vloc       = (p_char_props->is_value_user ? BLE_GATTS_VLOC_USER : BLE_GATTS_VLOC_STACK);
+
+
+    memset(&char_md, 0, sizeof(ble_gatts_char_md_t));
+    if ((p_char_props->char_props.notify == 1)||(p_char_props->char_props.indicate == 1))
+    {
+
+        memset(&cccd_md, 0, sizeof(cccd_md));
+        set_security_req(p_char_props->cccd_write_access, &cccd_md.write_perm);
+        BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.read_perm);
+
+        cccd_md.vloc       = BLE_GATTS_VLOC_STACK;
+
+        char_md.p_cccd_md  = &cccd_md;
+    }
+    char_md.char_props     = p_char_props->char_props;
+    char_md.char_ext_props = p_char_props->char_ext_props;
+
+    memset(&attr_char_value, 0, sizeof(ble_gatts_attr_t));
+    attr_char_value.p_uuid    = &char_uuid;
+    attr_char_value.p_attr_md = &attr_md;
+    attr_char_value.max_len   = p_char_props->max_len;
+    if (p_char_props->p_init_value != NULL)
+    {
+        attr_char_value.init_len  = p_char_props->init_len;
+        attr_char_value.p_value   = p_char_props->p_init_value;
+    }
+    if (p_char_props->p_user_descr != NULL)
+    {
+        memset(&user_descr_attr_md, 0, sizeof(ble_gatts_attr_md_t));
+        char_md.char_user_desc_max_size = p_char_props->p_user_descr->max_size;
+        char_md.char_user_desc_size     = p_char_props->p_user_descr->size;
+        char_md.p_char_user_desc        = p_char_props->p_user_descr->p_char_user_desc;
+
+        char_md.p_user_desc_md          = &user_descr_attr_md;
+
+        set_security_req(p_char_props->p_user_descr->read_access, &user_descr_attr_md.read_perm);
+        set_security_req(p_char_props->p_user_descr->write_access, &user_descr_attr_md.write_perm);
+
+        user_descr_attr_md.rd_auth      = (p_char_props->p_user_descr->is_defered_read ? 1 : 0);
+        user_descr_attr_md.wr_auth      = (p_char_props->p_user_descr->is_defered_write ? 1 : 0);
+        user_descr_attr_md.vlen         = (p_char_props->p_user_descr->is_var_len ? 1 : 0);
+        user_descr_attr_md.vloc         = (p_char_props->p_user_descr->is_value_user ? BLE_GATTS_VLOC_USER : BLE_GATTS_VLOC_STACK);
+    }
+    if (p_char_props->p_presentation_format != NULL)
+    {
+        char_md.p_char_pf = p_char_props->p_presentation_format;
+    }
+    return sd_ble_gatts_characteristic_add(service_handle,
+                                           &char_md,
+                                           &attr_char_value,
+                                           p_char_handle);
+}
+
+
+uint32_t descriptor_add(uint16_t                   char_handle,
+                        ble_add_descr_params_t *   p_descr_props,
+                        uint16_t *                 p_descr_handle)
+{
+    ble_gatts_attr_t    descr_params;
+    ble_uuid_t          desc_uuid;
+    ble_gatts_attr_md_t attr_md;
+
+    memset(&descr_params, 0, sizeof(descr_params));
+    if (p_descr_props->uuid_type == 0)
+    {
+        desc_uuid.type = BLE_UUID_TYPE_BLE;
+    }
+    else
+    {
+        desc_uuid.type = p_descr_props->uuid_type;
+    }
+    desc_uuid.uuid = p_descr_props->uuid;
+    descr_params.p_uuid = &desc_uuid;
+
+    set_security_req(p_descr_props->read_access, &attr_md.read_perm);
+    set_security_req(p_descr_props->write_access,&attr_md.write_perm);
+
+    attr_md.rd_auth        = (p_descr_props->is_defered_read ? 1 : 0);
+    attr_md.wr_auth        = (p_descr_props->is_defered_write ? 1 : 0);
+    attr_md.vlen           = (p_descr_props->is_var_len ? 1 : 0);
+    attr_md.vloc           = (p_descr_props->is_value_user ? BLE_GATTS_VLOC_USER : BLE_GATTS_VLOC_STACK);
+    descr_params.p_attr_md = &attr_md;
+
+    descr_params.init_len  = p_descr_props->init_len;
+    descr_params.init_offs = p_descr_props->init_offs;
+    descr_params.max_len   = p_descr_props->max_len;
+    descr_params.p_value   = p_descr_props->p_value;
+
+    return sd_ble_gatts_descriptor_add(char_handle, &descr_params, p_descr_handle);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_srv_common.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,397 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup ble_sdk_srv_common Common service definitions
+ * @{
+ * @ingroup ble_sdk_srv
+ * @brief Constants, type definitions, and functions that are common to all services.
+ */
+
+#ifndef BLE_SRV_COMMON_H__
+#define BLE_SRV_COMMON_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "ble_types.h"
+#include "app_util.h"
+#include "headers/ble.h"
+#include "ble_gap.h"
+#include "ble_gatt.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup UUID_SERVICES Service UUID definitions
+ * @{ */
+#define BLE_UUID_ALERT_NOTIFICATION_SERVICE                      0x1811     /**< Alert Notification service UUID. */
+#define BLE_UUID_BATTERY_SERVICE                                 0x180F     /**< Battery service UUID. */
+#define BLE_UUID_BLOOD_PRESSURE_SERVICE                          0x1810     /**< Blood Pressure service UUID. */
+#define BLE_UUID_CURRENT_TIME_SERVICE                            0x1805     /**< Current Time service UUID. */
+#define BLE_UUID_CYCLING_SPEED_AND_CADENCE                       0x1816     /**< Cycling Speed and Cadence service UUID. */
+#define BLE_UUID_LOCATION_AND_NAVIGATION_SERVICE                 0x1819     /**< Location and Navigation service UUID. */
+#define BLE_UUID_DEVICE_INFORMATION_SERVICE                      0x180A     /**< Device Information service UUID. */
+#define BLE_UUID_GLUCOSE_SERVICE                                 0x1808     /**< Glucose service UUID. */
+#define BLE_UUID_HEALTH_THERMOMETER_SERVICE                      0x1809     /**< Health Thermometer service UUID. */
+#define BLE_UUID_HEART_RATE_SERVICE                              0x180D     /**< Heart Rate service UUID. */
+#define BLE_UUID_HUMAN_INTERFACE_DEVICE_SERVICE                  0x1812     /**< Human Interface Device service UUID. */
+#define BLE_UUID_IMMEDIATE_ALERT_SERVICE                         0x1802     /**< Immediate Alert service UUID. */
+#define BLE_UUID_LINK_LOSS_SERVICE                               0x1803     /**< Link Loss service UUID. */
+#define BLE_UUID_NEXT_DST_CHANGE_SERVICE                         0x1807     /**< Next Dst Change service UUID. */
+#define BLE_UUID_PHONE_ALERT_STATUS_SERVICE                      0x180E     /**< Phone Alert Status service UUID. */
+#define BLE_UUID_REFERENCE_TIME_UPDATE_SERVICE                   0x1806     /**< Reference Time Update service UUID. */
+#define BLE_UUID_RUNNING_SPEED_AND_CADENCE                       0x1814     /**< Running Speed and Cadence service UUID. */
+#define BLE_UUID_SCAN_PARAMETERS_SERVICE                         0x1813     /**< Scan Parameters service UUID. */
+#define BLE_UUID_TX_POWER_SERVICE                                0x1804     /**< TX Power service UUID. */
+#define BLE_UUID_IPSP_SERVICE                                    0x1820     /**< Internet Protocol Support service UUID. */
+#define BLE_UUID_BMS_SERVICE                                     0x181E     /**< BOND MANAGEMENT service UUID*/
+#define BLE_UUID_CGM_SERVICE                                     0x181F     /**< Contiunous Glucose Monitoring service UUID*/
+#define BLE_UUID_PLX_SERVICE                                     0x1822     /**< Pulse Oximeter Service UUID*/
+
+
+/** @} */
+
+/** @defgroup UUID_CHARACTERISTICS Characteristic UUID definitions
+ * @{ */
+#define BLE_UUID_REMOVABLE_CHAR                                  0x2A3A     /**< Removable characteristic UUID. */
+#define BLE_UUID_SERVICE_REQUIRED_CHAR                           0x2A3B     /**< Service Required characteristic UUID. */
+#define BLE_UUID_ALERT_CATEGORY_ID_CHAR                          0x2A43     /**< Alert Category Id characteristic UUID. */
+#define BLE_UUID_ALERT_CATEGORY_ID_BIT_MASK_CHAR                 0x2A42     /**< Alert Category Id Bit Mask characteristic UUID. */
+#define BLE_UUID_ALERT_LEVEL_CHAR                                0x2A06     /**< Alert Level characteristic UUID. */
+#define BLE_UUID_ALERT_NOTIFICATION_CONTROL_POINT_CHAR           0x2A44     /**< Alert Notification Control Point characteristic UUID. */
+#define BLE_UUID_ALERT_STATUS_CHAR                               0x2A3F     /**< Alert Status characteristic UUID. */
+#define BLE_UUID_BATTERY_LEVEL_CHAR                              0x2A19     /**< Battery Level characteristic UUID. */
+#define BLE_UUID_BLOOD_PRESSURE_FEATURE_CHAR                     0x2A49     /**< Blood Pressure Feature characteristic UUID. */
+#define BLE_UUID_BLOOD_PRESSURE_MEASUREMENT_CHAR                 0x2A35     /**< Blood Pressure Measurement characteristic UUID. */
+#define BLE_UUID_BODY_SENSOR_LOCATION_CHAR                       0x2A38     /**< Body Sensor Location characteristic UUID. */
+#define BLE_UUID_BOOT_KEYBOARD_INPUT_REPORT_CHAR                 0x2A22     /**< Boot Keyboard Input Report characteristic UUID. */
+#define BLE_UUID_BOOT_KEYBOARD_OUTPUT_REPORT_CHAR                0x2A32     /**< Boot Keyboard Output Report characteristic UUID. */
+#define BLE_UUID_BOOT_MOUSE_INPUT_REPORT_CHAR                    0x2A33     /**< Boot Mouse Input Report characteristic UUID. */
+#define BLE_UUID_CURRENT_TIME_CHAR                               0x2A2B     /**< Current Time characteristic UUID. */
+#define BLE_UUID_DATE_TIME_CHAR                                  0x2A08     /**< Date Time characteristic UUID. */
+#define BLE_UUID_DAY_DATE_TIME_CHAR                              0x2A0A     /**< Day Date Time characteristic UUID. */
+#define BLE_UUID_DAY_OF_WEEK_CHAR                                0x2A09     /**< Day Of Week characteristic UUID. */
+#define BLE_UUID_DST_OFFSET_CHAR                                 0x2A0D     /**< Dst Offset characteristic UUID. */
+#define BLE_UUID_EXACT_TIME_256_CHAR                             0x2A0C     /**< Exact Time 256 characteristic UUID. */
+#define BLE_UUID_FIRMWARE_REVISION_STRING_CHAR                   0x2A26     /**< Firmware Revision String characteristic UUID. */
+#define BLE_UUID_GLUCOSE_FEATURE_CHAR                            0x2A51     /**< Glucose Feature characteristic UUID. */
+#define BLE_UUID_GLUCOSE_MEASUREMENT_CHAR                        0x2A18     /**< Glucose Measurement characteristic UUID. */
+#define BLE_UUID_GLUCOSE_MEASUREMENT_CONTEXT_CHAR                0x2A34     /**< Glucose Measurement Context characteristic UUID. */
+#define BLE_UUID_HARDWARE_REVISION_STRING_CHAR                   0x2A27     /**< Hardware Revision String characteristic UUID. */
+#define BLE_UUID_HEART_RATE_CONTROL_POINT_CHAR                   0x2A39     /**< Heart Rate Control Point characteristic UUID. */
+#define BLE_UUID_HEART_RATE_MEASUREMENT_CHAR                     0x2A37     /**< Heart Rate Measurement characteristic UUID. */
+#define BLE_UUID_HID_CONTROL_POINT_CHAR                          0x2A4C     /**< Hid Control Point characteristic UUID. */
+#define BLE_UUID_HID_INFORMATION_CHAR                            0x2A4A     /**< Hid Information characteristic UUID. */
+#define BLE_UUID_IEEE_REGULATORY_CERTIFICATION_DATA_LIST_CHAR    0x2A2A     /**< IEEE Regulatory Certification Data List characteristic UUID. */
+#define BLE_UUID_INTERMEDIATE_CUFF_PRESSURE_CHAR                 0x2A36     /**< Intermediate Cuff Pressure characteristic UUID. */
+#define BLE_UUID_INTERMEDIATE_TEMPERATURE_CHAR                   0x2A1E     /**< Intermediate Temperature characteristic UUID. */
+#define BLE_UUID_LOCAL_TIME_INFORMATION_CHAR                     0x2A0F     /**< Local Time Information characteristic UUID. */
+#define BLE_UUID_MANUFACTURER_NAME_STRING_CHAR                   0x2A29     /**< Manufacturer Name String characteristic UUID. */
+#define BLE_UUID_MEASUREMENT_INTERVAL_CHAR                       0x2A21     /**< Measurement Interval characteristic UUID. */
+#define BLE_UUID_MODEL_NUMBER_STRING_CHAR                        0x2A24     /**< Model Number String characteristic UUID. */
+#define BLE_UUID_UNREAD_ALERT_CHAR                               0x2A45     /**< Unread Alert characteristic UUID. */
+#define BLE_UUID_NEW_ALERT_CHAR                                  0x2A46     /**< New Alert characteristic UUID. */
+#define BLE_UUID_PNP_ID_CHAR                                     0x2A50     /**< PNP Id characteristic UUID. */
+#define BLE_UUID_PROTOCOL_MODE_CHAR                              0x2A4E     /**< Protocol Mode characteristic UUID. */
+#define BLE_UUID_RECORD_ACCESS_CONTROL_POINT_CHAR                0x2A52     /**< Record Access Control Point characteristic UUID. */
+#define BLE_UUID_REFERENCE_TIME_INFORMATION_CHAR                 0x2A14     /**< Reference Time Information characteristic UUID. */
+#define BLE_UUID_REPORT_CHAR                                     0x2A4D     /**< Report characteristic UUID. */
+#define BLE_UUID_REPORT_MAP_CHAR                                 0x2A4B     /**< Report Map characteristic UUID. */
+#define BLE_UUID_RINGER_CONTROL_POINT_CHAR                       0x2A40     /**< Ringer Control Point characteristic UUID. */
+#define BLE_UUID_RINGER_SETTING_CHAR                             0x2A41     /**< Ringer Setting characteristic UUID. */
+#define BLE_UUID_SCAN_INTERVAL_WINDOW_CHAR                       0x2A4F     /**< Scan Interval Window characteristic UUID. */
+#define BLE_UUID_SCAN_REFRESH_CHAR                               0x2A31     /**< Scan Refresh characteristic UUID. */
+#define BLE_UUID_SERIAL_NUMBER_STRING_CHAR                       0x2A25     /**< Serial Number String characteristic UUID. */
+#define BLE_UUID_SOFTWARE_REVISION_STRING_CHAR                   0x2A28     /**< Software Revision String characteristic UUID. */
+#define BLE_UUID_SUPPORTED_NEW_ALERT_CATEGORY_CHAR               0x2A47     /**< Supported New Alert Category characteristic UUID. */
+#define BLE_UUID_SUPPORTED_UNREAD_ALERT_CATEGORY_CHAR            0x2A48     /**< Supported Unread Alert Category characteristic UUID. */
+#define BLE_UUID_SYSTEM_ID_CHAR                                  0x2A23     /**< System Id characteristic UUID. */
+#define BLE_UUID_TEMPERATURE_MEASUREMENT_CHAR                    0x2A1C     /**< Temperature Measurement characteristic UUID. */
+#define BLE_UUID_TEMPERATURE_TYPE_CHAR                           0x2A1D     /**< Temperature Type characteristic UUID. */
+#define BLE_UUID_TIME_ACCURACY_CHAR                              0x2A12     /**< Time Accuracy characteristic UUID. */
+#define BLE_UUID_TIME_SOURCE_CHAR                                0x2A13     /**< Time Source characteristic UUID. */
+#define BLE_UUID_TIME_UPDATE_CONTROL_POINT_CHAR                  0x2A16     /**< Time Update Control Point characteristic UUID. */
+#define BLE_UUID_TIME_UPDATE_STATE_CHAR                          0x2A17     /**< Time Update State characteristic UUID. */
+#define BLE_UUID_TIME_WITH_DST_CHAR                              0x2A11     /**< Time With Dst characteristic UUID. */
+#define BLE_UUID_TIME_ZONE_CHAR                                  0x2A0E     /**< Time Zone characteristic UUID. */
+#define BLE_UUID_TX_POWER_LEVEL_CHAR                             0x2A07     /**< TX Power Level characteristic UUID. */
+#define BLE_UUID_CSC_FEATURE_CHAR                                0x2A5C     /**< Cycling Speed and Cadence Feature characteristic UUID. */
+#define BLE_UUID_CSC_MEASUREMENT_CHAR                            0x2A5B     /**< Cycling Speed and Cadence Measurement characteristic UUID. */
+#define BLE_UUID_RSC_FEATURE_CHAR                                0x2A54     /**< Running Speed and Cadence Feature characteristic UUID. */
+#define BLE_UUID_SC_CTRLPT_CHAR                                  0x2A55     /**< Speed and Cadence Control Point UUID. */
+#define BLE_UUID_RSC_MEASUREMENT_CHAR                            0x2A53     /**< Running Speed and Cadence Measurement characteristic UUID. */
+#define BLE_UUID_SENSOR_LOCATION_CHAR                            0x2A5D     /**< Sensor Location characteristic UUID. */
+#define BLE_UUID_EXTERNAL_REPORT_REF_DESCR                       0x2907     /**< External Report Reference descriptor UUID. */
+#define BLE_UUID_REPORT_REF_DESCR                                0x2908     /**< Report Reference descriptor UUID. */
+#define BLE_UUID_LN_FEATURE_CHAR                                 0x2A6A     /**< Location Navigation Service, Feature characteristic UUID. */
+#define BLE_UUID_LN_POSITION_QUALITY_CHAR                        0x2A69     /**< Location Navigation Service, Position quality UUID. */
+#define BLE_UUID_LN_LOCATION_AND_SPEED_CHAR                      0x2A67     /**< Location Navigation Service, Location and Speed characteristic UUID. */
+#define BLE_UUID_LN_NAVIGATION_CHAR                              0x2A68     /**< Location Navigation Service, Navigation characteristic UUID. */
+#define BLE_UUID_LN_CONTROL_POINT_CHAR                           0x2A6B     /**< Location Navigation Service, Control point characteristic UUID. */
+#define BLE_UUID_BMS_CTRLPT                                      0x2AA4     /**< BMS Control Point characteristic UUID. */
+#define BLE_UUID_BMS_FEATURE                                     0x2AA5     /**< BMS Feature characteristic UUID. */
+#define BLE_UUID_CGM_MEASUREMENT                                 0x2AA7     /**< CGM Service, Measurement characteristic UUID*/
+#define BLE_UUID_CGM_FEATURE                                     0x2AA8     /**< CGM Service, Feature characteristic UUID*/
+#define BLE_UUID_CGM_STATUS                                      0x2AA9     /**< CGM Service, Status characteristic UUID*/
+#define BLE_UUID_CGM_SESSION_START_TIME                          0x2AAA     /**< CGM Service, session start time characteristic UUID*/
+#define BLE_UUID_CGM_SESSION_RUN_TIME                            0x2AAB     /**< CGM Service, session run time characteristic UUID*/
+#define BLE_UUID_CGM_SPECIFIC_OPS_CTRLPT                         0x2AAC     /**< CGM Service, specific ops ctrlpt characteristic UUID*/
+#define BLE_UUID_PLX_SPOT_CHECK_MEAS                             0x2A5E     /**< PLX Service, spot check measurement characteristic UUID*/
+#define BLE_UUID_PLX_CONTINUOUS_MEAS                             0x2A5F     /**< PLX Service, continuous measurement characteristic UUID*/
+#define BLE_UUID_PLX_FEATURES                                    0x2A60     /**< PLX Service, feature characteristic UUID*/
+
+
+
+
+
+/** @} */
+
+/** @defgroup ALERT_LEVEL_VALUES Definitions for the Alert Level characteristic values
+ * @{ */
+#define BLE_CHAR_ALERT_LEVEL_NO_ALERT                            0x00       /**< No Alert. */
+#define BLE_CHAR_ALERT_LEVEL_MILD_ALERT                          0x01       /**< Mild Alert. */
+#define BLE_CHAR_ALERT_LEVEL_HIGH_ALERT                          0x02       /**< High Alert. */
+/** @} */
+
+#define BLE_SRV_ENCODED_REPORT_REF_LEN                           2          /**< The length of an encoded Report Reference Descriptor. */
+#define BLE_CCCD_VALUE_LEN                                       2          /**< The length of a CCCD value. */
+
+/**@brief Type definition for error handler function that will be called in case of an error in
+ *        a service or a service library module. */
+typedef void (*ble_srv_error_handler_t) (uint32_t nrf_error);
+
+
+
+/**@brief Value of a Report Reference descriptor.
+ *
+ * @details This is mapping information that maps the parent characteristic to the Report ID(s) and
+ *          Report Type(s) defined within a Report Map characteristic.
+ */
+typedef struct
+{
+    uint8_t report_id;                                  /**< Non-zero value if there is more than one instance of the same Report Type */
+    uint8_t report_type;                                /**< Type of Report characteristic (see @ref BLE_HIDS_REPORT_TYPE) */
+} ble_srv_report_ref_t;
+
+/**@brief UTF-8 string data type.
+ *
+ * @note The type can only hold a pointer to the string data (i.e. not the actual data).
+ */
+typedef struct
+{
+    uint16_t  length;                                   /**< String length. */
+    uint8_t * p_str;                                    /**< String data. */
+} ble_srv_utf8_str_t;
+
+
+/**@brief Security settings structure.
+ * @details This structure contains the security options needed during initialization of the
+ *          service.
+ */
+typedef struct
+{
+    ble_gap_conn_sec_mode_t read_perm;                  /**< Read permissions. */
+    ble_gap_conn_sec_mode_t write_perm;                 /**< Write permissions. */
+} ble_srv_security_mode_t;
+
+/**@brief Security settings structure.
+ * @details This structure contains the security options needed during initialization of the
+ *          service. It can be used when the characteristics contains a CCCD.
+ */
+typedef struct
+{
+    ble_gap_conn_sec_mode_t cccd_write_perm;            /**< Write permissions for Client Characteristic Configuration Descriptor. */
+    ble_gap_conn_sec_mode_t read_perm;                  /**< Read permissions. */
+    ble_gap_conn_sec_mode_t write_perm;                 /**< Write permissions. */
+} ble_srv_cccd_security_mode_t;
+
+/**@brief Function for decoding a CCCD value, and then testing if notification is
+ *        enabled.
+ *
+ * @param[in]   p_encoded_data   Buffer where the encoded CCCD is stored.
+ *
+ * @retval      TRUE If notification is enabled.
+ * @retval      FALSE Otherwise.
+ */
+bool ble_srv_is_notification_enabled(uint8_t const * p_encoded_data);
+
+
+/**@brief Function for decoding a CCCD value, and then testing if indication is
+ *        enabled.
+ *
+ * @param[in]   p_encoded_data   Buffer where the encoded CCCD is stored.
+ *
+ * @retval      TRUE If indication is enabled.
+ * @retval      FALSE Otherwise.
+ */
+bool ble_srv_is_indication_enabled(uint8_t const * p_encoded_data);
+
+
+/**@brief Function for encoding a Report Reference Descriptor.
+ *
+ * @param[in]   p_encoded_buffer  The buffer of the encoded data.
+ * @param[in]   p_report_ref      Report Reference value to be encoded.
+ *
+ * @return      Length of the encoded data.
+ */
+uint8_t ble_srv_report_ref_encode(uint8_t *                    p_encoded_buffer,
+                                  const ble_srv_report_ref_t * p_report_ref);
+
+/**@brief Function for making a UTF-8 structure refer to an ASCII string.
+ *
+ * @param[out]  p_utf8   UTF-8 structure to be set.
+ * @param[in]   p_ascii  ASCII string to be referred to.
+ */
+void ble_srv_ascii_to_utf8(ble_srv_utf8_str_t * p_utf8, char * p_ascii);
+
+
+/**@brief Security Access enumeration.
+ * @details This enumeration gives the possible requirements for accessing a characteristic value.
+ */
+typedef enum
+{
+    SEC_NO_ACCESS    = 0,            /**< Not possible to access. */
+    SEC_OPEN         = 1,            /**< Access open. */
+    SEC_JUST_WORKS   = 2,            /**< Access possible with 'Just Works' security at least. */
+    SEC_MITM         = 3,            /**< Access possible with 'MITM' security at least. */
+    SEC_SIGNED       = 4,            /**< Access possible with 'signed' security at least. */
+    SEC_SIGNED_MITM  = 5             /**< Access possible with 'signed and MITM' security at least. */
+}security_req_t;
+
+
+/**@brief Characteristic User Descriptor parameters.
+ * @details This structure contains the parameters for User Descriptor.
+ */
+typedef struct
+{
+    uint16_t               max_size;                      /**< Maximum size of the user descriptor*/
+    uint16_t               size;                          /**< Size of the user descriptor*/
+    uint8_t                *p_char_user_desc;             /**< User descriptor content, pointer to a UTF-8 encoded string (non-NULL terminated)*/
+    bool                   is_var_len;                    /**< Indicates if the user descriptor has variable length.*/
+    ble_gatt_char_props_t  char_props;                    /**< user descriptor properties.*/
+    bool                   is_defered_read;               /**< Indicate if deferred read operations are supported.*/
+    bool                   is_defered_write;              /**< Indicate if deferred write operations are supported.*/
+    security_req_t         read_access;                   /**< Security requirement for reading the user descriptor.*/
+    security_req_t         write_access;                  /**< Security requirement for writing the user descriptor.*/
+    bool                   is_value_user;                 /**< Indicate if the content of the characteristic is to be stored in the application (user) or in the stack.*/
+}ble_add_char_user_desc_t;
+
+
+/**@brief Add characteristic parameters structure.
+ * @details This structure contains the parameters needed to use the @ref characteristic_add function.
+ */
+typedef struct
+{
+    uint16_t                    uuid;                     /**< Characteristic UUID (16 bits UUIDs).*/
+    uint8_t                     uuid_type;                /**< Base UUID. If 0, the Bluetooth SIG UUID will be used. Otherwise, this should be a value returned by @ref sd_ble_uuid_vs_add when adding the base UUID.*/
+    uint16_t                    max_len;                  /**< Maximum length of the characteristic value.*/
+    uint16_t                    init_len;                 /**< Initial length of the characteristic value.*/
+    uint8_t *                   p_init_value;             /**< Initial encoded value of the characteristic.*/
+    bool                        is_var_len;               /**< Indicates if the characteristic value has variable length.*/
+    ble_gatt_char_props_t       char_props;               /**< Characteristic properties.*/
+    ble_gatt_char_ext_props_t   char_ext_props;           /**< Characteristic extended properties.*/
+    bool                        is_defered_read;          /**< Indicate if deferred read operations are supported.*/
+    bool                        is_defered_write;         /**< Indicate if deferred write operations are supported.*/
+    security_req_t              read_access;              /**< Security requirement for reading the characteristic value.*/
+    security_req_t              write_access;             /**< Security requirement for writing the characteristic value.*/
+    security_req_t              cccd_write_access;        /**< Security requirement for writing the characteristic's CCCD.*/
+    bool                        is_value_user;            /**< Indicate if the content of the characteristic is to be stored in the application (user) or in the stack.*/
+    ble_add_char_user_desc_t    *p_user_descr;            /**< Pointer to user descriptor if needed*/
+    ble_gatts_char_pf_t         *p_presentation_format;   /**< Pointer to characteristic format if needed*/
+} ble_add_char_params_t;
+
+
+/**@brief Add descriptor parameters structure.
+ * @details This structure contains the parameters needed to use the @ref descriptor_add function.
+ */
+typedef struct
+{
+    uint16_t       uuid;                     /**< descriptor UUID (16 bits UUIDs).*/
+    uint8_t        uuid_type;                /**< Base UUID. If 0, the Bluetooth SIG UUID will be used. Otherwise, this should be a value returned by @ref sd_ble_uuid_vs_add when adding the base UUID.*/
+    bool           is_defered_read;          /**< Indicate if deferred read operations are supported.*/
+    bool           is_defered_write;         /**< Indicate if deferred write operations are supported.*/
+    bool           is_var_len;               /**< Indicates if the descriptor value has variable length.*/
+    security_req_t read_access;              /**< Security requirement for reading the descriptor value.*/
+    security_req_t write_access;             /**< Security requirement for writing the descriptor value.*/
+    bool           is_value_user;            /**< Indicate if the content of the characteristic is to be stored in the application (user) or in the stack.*/
+    uint16_t       init_len;                 /**< Initial descriptor value length in bytes. */
+    uint16_t       init_offs;                /**< Initial descriptor value offset in bytes. If different from zero, the first init_offs bytes of the attribute value will be left uninitialized. */
+    uint16_t       max_len;                  /**< Maximum descriptor value length in bytes, see @ref BLE_GATTS_ATTR_LENS_MAX for maximum values. */
+    uint8_t*       p_value;                  /**< Pointer to the value of the descriptor*/
+} ble_add_descr_params_t;
+
+
+/**@brief Function for adding a characteristic to a given service.
+ *
+ * If no pointer is given for the initial value,
+ * the initial length parameter will be ignored and the initial length will be 0.
+ *
+ * @param[in]  service_handle Handle of the service to which the characteristic is to be added.
+ * @param[in]  p_char_props   Information needed to add the characteristic.
+ * @param[out] p_char_handle  Handle of the added characteristic.
+ *
+ * @retval      NRF_SUCCESS If the characteristic was added successfully. Otherwise, an error code is returned.
+ */
+uint32_t characteristic_add(uint16_t                   service_handle,
+                            ble_add_char_params_t *    p_char_props,
+                            ble_gatts_char_handles_t * p_char_handle);
+
+
+/**@brief Function for adding a characteristic's descriptor to a given characteristic.
+ *
+ * @param[in]  char_handle    Handle of the characteristic to which the descriptor is to be added, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially.
+ * @param[in]  p_descr_props  Information needed to add the descriptor.
+ * @param[out] p_descr_handle Handle of the added descriptor.
+ *
+ * @retval      NRF_SUCCESS If the characteristic was added successfully. Otherwise, an error code is returned.
+ */
+uint32_t descriptor_add(uint16_t                   char_handle,
+                        ble_add_descr_params_t *   p_descr_props,
+                        uint16_t *                 p_descr_handle);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // BLE_SRV_COMMON_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/gatt_cache_manager.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,560 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(PEER_MANAGER)
+#include "gatt_cache_manager.h"
+
+#include "ble_gap.h"
+#include "ble_conn_state.h"
+#include "peer_manager_types.h"
+#include "peer_manager_internal.h"
+#include "id_manager.h"
+#include "security_dispatcher.h"
+#include "gatts_cache_manager.h"
+
+
+// The number of registered event handlers.
+#define GCM_EVENT_HANDLERS_CNT      (sizeof(m_evt_handlers) / sizeof(m_evt_handlers[0]))
+
+// GATT Cache Manager event handler in Peer Manager.
+extern void pm_gcm_evt_handler(gcm_evt_t const * p_gcm_evt);
+
+// GATT Cache Manager events' handlers.
+// The number of elements in this array is GCM_EVENT_HANDLERS_CNT.
+static gcm_evt_handler_t m_evt_handlers[] =
+{
+    pm_gcm_evt_handler
+};
+
+static bool                           m_module_initialized;
+static ble_conn_state_user_flag_id_t  m_flag_local_db_update_pending; /**< Flag ID for flag collection to keep track of which connections need a local DB update procedure. */
+static ble_conn_state_user_flag_id_t  m_flag_local_db_apply_pending;  /**< Flag ID for flag collection to keep track of which connections need a local DB apply procedure. */
+static ble_conn_state_user_flag_id_t  m_flag_service_changed_pending; /**< Flag ID for flag collection to keep track of which connections need to be sent a service changed indication. */
+static ble_conn_state_user_flag_id_t  m_flag_service_changed_sent;    /**< Flag ID for flag collection to keep track of which connections have been sent a service changed indication and are waiting for a handle value confirmation. */
+
+
+static void service_changed_pending_flags_check(void);
+
+
+/**@brief Function for resetting the module variable(s) of the GSCM module.
+ *
+ * @param[out]  The instance to reset.
+ */
+static void internal_state_reset()
+{
+    m_module_initialized = false;
+}
+
+
+static void evt_send(gcm_evt_t const * p_gcm_evt)
+{
+    for (uint32_t i = 0; i < GCM_EVENT_HANDLERS_CNT; i++)
+    {
+        m_evt_handlers[i](p_gcm_evt);
+    }
+}
+
+
+/**@brief Function for checking a write event for whether a CCCD was written during the write
+ *        operation.
+ *
+ * @param[in]  p_write_evt  The parameters of the write event.
+ *
+ * @return  Whether the write was on a CCCD.
+ */
+static bool cccd_written(ble_gatts_evt_write_t * p_write_evt)
+{
+    return (    (p_write_evt->op        == BLE_GATTS_OP_WRITE_REQ)
+             && (p_write_evt->uuid.type == BLE_UUID_TYPE_BLE)
+             && (p_write_evt->uuid.uuid == BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG)
+           );
+}
+
+
+/**@brief Function for performing the local DB update procedure in an event context, where no return
+ *        code can be given.
+ *
+ * @details This function will do the procedure, and check the result, set a flag if needed, and
+ *          send an event if needed.
+ *
+ * @param[in]  conn_handle  The connection to perform the procedure on.
+ */
+static void local_db_apply_in_evt(uint16_t conn_handle)
+{
+    bool set_procedure_as_pending = false;
+    ret_code_t err_code;
+    gcm_evt_t event;
+
+    if (conn_handle == BLE_CONN_HANDLE_INVALID)
+    {
+        return;
+    }
+
+    err_code = gscm_local_db_cache_apply(conn_handle);
+
+    switch (err_code)
+    {
+        case NRF_SUCCESS:
+            event.evt_id                                    = GCM_EVT_LOCAL_DB_CACHE_APPLIED;
+            event.peer_id                                   = im_peer_id_get_by_conn_handle(conn_handle);
+            event.params.local_db_cache_applied.conn_handle = conn_handle;
+
+            evt_send(&event);
+            break;
+
+        case NRF_ERROR_BUSY:
+            set_procedure_as_pending = true;
+            break;
+
+        case NRF_ERROR_INVALID_DATA:
+            event.evt_id                                        = GCM_EVT_ERROR_LOCAL_DB_CACHE_APPLY;
+            event.peer_id                                       = im_peer_id_get_by_conn_handle(conn_handle);
+            event.params.error_local_db_cache_apply.conn_handle = conn_handle;
+
+            evt_send(&event);
+            break;
+
+        case BLE_ERROR_INVALID_CONN_HANDLE:
+            /* Do nothing */
+            break;
+
+        default:
+            event.evt_id                              = GCM_EVT_ERROR_UNEXPECTED;
+            event.peer_id                             = im_peer_id_get_by_conn_handle(conn_handle);
+            event.params.error_unexpected.conn_handle = conn_handle;
+            event.params.error_unexpected.error       = err_code;
+
+            evt_send(&event);
+            break;
+    }
+
+    ble_conn_state_user_flag_set(conn_handle, m_flag_local_db_apply_pending, set_procedure_as_pending);
+}
+
+
+/**@brief Function for performing the local DB apply procedure in an event context, where no return
+ *        code can be given.
+ *
+ * @details This function will do the procedure, and check the result, set a flag if needed, and
+ *          send an event if needed.
+ *
+ * @param[in]  conn_handle  The connection to perform the procedure on.
+ */
+static void local_db_update_in_evt(uint16_t conn_handle)
+{
+    gcm_evt_t event;
+    bool set_procedure_as_pending = false;
+    ret_code_t err_code = gscm_local_db_cache_update(conn_handle);
+
+    switch (err_code)
+    {
+        case NRF_SUCCESS:
+            event.evt_id                                    = GCM_EVT_LOCAL_DB_CACHE_UPDATED;
+            event.params.local_db_cache_applied.conn_handle = conn_handle;
+            event.peer_id                                   = im_peer_id_get_by_conn_handle(conn_handle);
+
+            evt_send(&event);
+            break;
+
+        case BLE_ERROR_INVALID_CONN_HANDLE:
+            /* Do nothing */
+            break;
+
+        case NRF_ERROR_BUSY:
+            set_procedure_as_pending = true;
+            break;
+
+        case NRF_ERROR_DATA_SIZE:
+            event.evt_id = GCM_EVT_ERROR_DATA_SIZE;
+            event.params.error_data_size.conn_handle = conn_handle;
+            event.peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+
+            evt_send(&event);
+            break;
+
+        case NRF_ERROR_STORAGE_FULL:
+            event.evt_id = GCM_EVT_ERROR_STORAGE_FULL;
+            event.params.error_no_mem.conn_handle = conn_handle;
+            event.peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+
+            evt_send(&event);
+            break;
+
+        default:
+            event.evt_id                              = GCM_EVT_ERROR_UNEXPECTED;
+            event.peer_id                             = im_peer_id_get_by_conn_handle(conn_handle);
+            event.params.error_unexpected.conn_handle = conn_handle;
+            event.params.error_unexpected.error       = err_code;
+
+            evt_send(&event);
+            break;
+    }
+
+    ble_conn_state_user_flag_set(conn_handle, m_flag_local_db_update_pending, set_procedure_as_pending);
+}
+
+
+/**@brief Function for sending a service changed indication in an event context, where no return
+ *        code can be given.
+ *
+ * @details This function will do the procedure, and check the result, set a flag if needed, and
+ *          send an event if needed.
+ *
+ * @param[in]  conn_handle  The connection to perform the procedure on.
+ */
+static void service_changed_send_in_evt(uint16_t conn_handle)
+{
+    gcm_evt_t event;
+    bool sc_pending_state = true;
+    bool sc_sent_state = false;
+    ret_code_t err_code = gscm_service_changed_ind_send(conn_handle);
+
+    switch (err_code)
+    {
+        case NRF_SUCCESS:
+            sc_sent_state = true;
+
+            event.evt_id = GCM_EVT_SERVICE_CHANGED_IND_SENT;
+            event.peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+            event.params.service_changed_ind_sent.conn_handle = conn_handle;
+
+            evt_send(&event);
+            break;
+
+        case NRF_ERROR_BUSY:
+            // Do nothing.
+            break;
+
+        case NRF_ERROR_INVALID_STATE:
+            // CCCDs not enabled. Drop indication.
+            // Fallthrough.
+
+        case NRF_ERROR_NOT_SUPPORTED:
+            // Service changed not supported. Drop indication.
+            sc_pending_state = false;
+            gscm_db_change_notification_done(im_peer_id_get_by_conn_handle(conn_handle));
+            break;
+
+        case BLE_ERROR_GATTS_SYS_ATTR_MISSING:
+            local_db_apply_in_evt(conn_handle);
+            break;
+
+        case BLE_ERROR_INVALID_CONN_HANDLE:
+            // Do nothing.
+            break;
+
+        default:
+            event.evt_id = GCM_EVT_ERROR_UNEXPECTED;
+            event.params.error_unexpected.conn_handle = conn_handle;
+            event.params.error_unexpected.error = err_code;
+            event.peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+
+            evt_send(&event);
+            break;
+    }
+
+    ble_conn_state_user_flag_set(conn_handle, m_flag_service_changed_pending, sc_pending_state);
+    ble_conn_state_user_flag_set(conn_handle, m_flag_service_changed_sent, sc_sent_state);
+}
+
+
+/**@brief Callback function for events from the GATT Cache Server Manager module.
+ *        This handler is extern in GATTS Cache Manager module.
+ *
+ * @param[in]  p_event  The event from the GATT Cache Server Manager module.
+ */
+void gcm_gscm_evt_handler(gscm_evt_t const * p_event)
+{
+    gcm_evt_t event;
+    event.peer_id = p_event->peer_id;
+
+    switch (p_event->evt_id)
+    {
+        case GSCM_EVT_LOCAL_DB_CACHE_STORED:
+            event.evt_id = GCM_EVT_LOCAL_DB_CACHE_STORED;
+
+            evt_send(&event);
+            local_db_apply_in_evt(im_conn_handle_get(p_event->peer_id));
+            break;
+
+        case GSCM_EVT_LOCAL_DB_CACHE_UPDATED:
+            event.evt_id = GCM_EVT_LOCAL_DB_CACHE_UPDATED;
+            event.params.local_db_cache_updated.conn_handle = p_event->params.local_db_cache_updated.conn_handle;
+
+            evt_send(&event);
+            break;
+
+        case GSCM_EVT_SC_STATE_STORED:
+            if (p_event->params.sc_state_stored.state)
+            {
+                uint16_t conn_handle = im_conn_handle_get(p_event->peer_id);
+                if (conn_handle != BLE_CONN_HANDLE_INVALID)
+                {
+                    ble_conn_state_user_flag_set(conn_handle, m_flag_service_changed_pending, true);
+                    service_changed_pending_flags_check();
+                }
+            }
+            break;
+    }
+}
+
+
+/**@brief Callback function for events from the ID Manager module.
+ *        This function is registered in the ID Manager module.
+ *
+ * @param[in]  p_event  The event from the ID Manager module.
+ */
+void gcm_im_evt_handler(im_evt_t const * p_event)
+{
+    switch (p_event->evt_id)
+    {
+        case IM_EVT_BONDED_PEER_CONNECTED:
+            local_db_apply_in_evt(p_event->conn_handle);
+            if (gscm_service_changed_ind_needed(p_event->conn_handle))
+            {
+                ble_conn_state_user_flag_set(p_event->conn_handle, m_flag_service_changed_pending, true);
+            }
+            break;
+        default:
+            break;
+    }
+}
+
+
+/**@brief Callback function for events from the Security Dispatcher module.
+ *        This handler is extern in Security Dispatcher.
+ *
+ * @param[in]  p_event  The event from the Security Dispatcher module.
+ */
+void gcm_smd_evt_handler(smd_evt_t const * p_event)
+{
+    switch (p_event->evt_id)
+    {
+        case SMD_EVT_BONDING_INFO_STORED:
+            local_db_update_in_evt(p_event->conn_handle);
+            break;
+        default:
+            break;
+    }
+}
+
+
+ret_code_t gcm_init()
+{
+    NRF_PM_DEBUG_CHECK(!m_module_initialized);
+
+    internal_state_reset();
+
+    m_flag_local_db_update_pending = ble_conn_state_user_flag_acquire();
+    m_flag_local_db_apply_pending  = ble_conn_state_user_flag_acquire();
+    m_flag_service_changed_pending = ble_conn_state_user_flag_acquire();
+    m_flag_service_changed_sent    = ble_conn_state_user_flag_acquire();
+
+    if  ((m_flag_local_db_update_pending  == BLE_CONN_STATE_USER_FLAG_INVALID)
+      || (m_flag_local_db_apply_pending   == BLE_CONN_STATE_USER_FLAG_INVALID)
+      || (m_flag_service_changed_pending  == BLE_CONN_STATE_USER_FLAG_INVALID)
+      || (m_flag_service_changed_sent     == BLE_CONN_STATE_USER_FLAG_INVALID))
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    m_module_initialized = true;
+
+    return NRF_SUCCESS;
+}
+
+
+// @todo emdi: apply_pending_flags_check() and update_pending_flags_check() should really be
+// refactored into one function..
+
+/**@brief Function for performing the Local DB apply procedure if it is pending on any connections.
+ */
+static void apply_pending_flags_check(void)
+{
+    sdk_mapped_flags_t apply_pending_flags;
+
+    apply_pending_flags = ble_conn_state_user_flag_collection(m_flag_local_db_apply_pending);
+    if (sdk_mapped_flags_any_set(apply_pending_flags))
+    {
+        sdk_mapped_flags_key_list_t conn_handle_list;
+        conn_handle_list = ble_conn_state_conn_handles();
+
+        for (uint32_t i = 0; i < conn_handle_list.len; i++)
+        {
+            if (ble_conn_state_user_flag_get(conn_handle_list.flag_keys[i], m_flag_local_db_apply_pending))
+            {
+                local_db_apply_in_evt(conn_handle_list.flag_keys[i]);
+            }
+        }
+    }
+}
+
+
+/**@brief Function for performing the Local DB update procedure if it is pending on any connections.
+ */
+static void update_pending_flags_check(void)
+{
+    sdk_mapped_flags_t update_pending_flags;
+
+    update_pending_flags = ble_conn_state_user_flag_collection(m_flag_local_db_update_pending);
+    if (sdk_mapped_flags_any_set(update_pending_flags))
+    {
+        sdk_mapped_flags_key_list_t conn_handle_list;
+        conn_handle_list = ble_conn_state_conn_handles();
+
+        for (uint32_t i = 0; i < conn_handle_list.len; i++)
+        {
+            if (ble_conn_state_user_flag_get(conn_handle_list.flag_keys[i], m_flag_local_db_update_pending))
+            {
+                local_db_update_in_evt(conn_handle_list.flag_keys[i]);
+            }
+        }
+    }
+}
+
+
+/**@brief Function for sending service changed indications if it is pending on any connections.
+ */
+static void service_changed_pending_flags_check(void)
+{
+    sdk_mapped_flags_t service_changed_pending_flags;
+
+    service_changed_pending_flags = ble_conn_state_user_flag_collection(m_flag_service_changed_pending);
+    if (sdk_mapped_flags_any_set(service_changed_pending_flags))
+    {
+        sdk_mapped_flags_key_list_t conn_handle_list;
+        conn_handle_list = ble_conn_state_conn_handles();
+
+        for (uint32_t i = 0; i < conn_handle_list.len; i++)
+        {
+            if (    ble_conn_state_user_flag_get(conn_handle_list.flag_keys[i],
+                                                 m_flag_service_changed_pending)
+                && !ble_conn_state_user_flag_get(conn_handle_list.flag_keys[i],
+                                                 m_flag_service_changed_sent))
+            {
+                service_changed_send_in_evt(conn_handle_list.flag_keys[i]);
+            }
+        }
+    }
+}
+
+
+/**@brief Callback function for BLE events from the SoftDevice.
+ *
+ * @param[in]  p_ble_evt  The BLE event from the SoftDevice.
+ */
+void gcm_ble_evt_handler(ble_evt_t * p_ble_evt)
+{
+    gcm_evt_t event;
+
+    switch (p_ble_evt->header.evt_id)
+    {
+        case BLE_GATTS_EVT_SYS_ATTR_MISSING:
+            local_db_apply_in_evt(p_ble_evt->evt.gatts_evt.conn_handle);
+            break;
+
+        case BLE_GATTS_EVT_SC_CONFIRM:
+            event.evt_id = GCM_EVT_SERVICE_CHANGED_IND_CONFIRMED;
+            event.peer_id = im_peer_id_get_by_conn_handle(p_ble_evt->evt.gatts_evt.conn_handle);
+            event.params.service_changed_ind_sent.conn_handle = p_ble_evt->evt.gatts_evt.conn_handle;
+
+            gscm_db_change_notification_done(event.peer_id);
+            ble_conn_state_user_flag_set(p_ble_evt->evt.gatts_evt.conn_handle, m_flag_service_changed_pending, false);
+
+            evt_send(&event);
+            break;
+
+        case BLE_GATTS_EVT_WRITE:
+            if (cccd_written(&p_ble_evt->evt.gatts_evt.params.write))
+            {
+                local_db_update_in_evt(p_ble_evt->evt.gatts_evt.conn_handle);
+            }
+            break;
+    }
+
+    apply_pending_flags_check();
+    update_pending_flags_check();
+    service_changed_pending_flags_check();
+}
+
+
+ret_code_t gcm_local_db_cache_update(uint16_t conn_handle)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    ret_code_t err_code = gscm_local_db_cache_update(conn_handle);
+    bool set_procedure_as_pending = false;
+
+    if (err_code == NRF_ERROR_BUSY)
+    {
+        set_procedure_as_pending = true;
+        err_code = NRF_SUCCESS;
+    }
+
+    ble_conn_state_user_flag_set(conn_handle, m_flag_local_db_update_pending, set_procedure_as_pending);
+
+    return err_code;
+}
+
+
+ret_code_t gcm_local_db_cache_set(pm_peer_id_t peer_id, pm_peer_data_local_gatt_db_t * p_local_db)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    return gscm_local_db_cache_set(peer_id, p_local_db);
+}
+
+
+void gcm_local_database_has_changed(void)
+{
+    gscm_local_database_has_changed();
+
+    sdk_mapped_flags_key_list_t conn_handles = ble_conn_state_conn_handles();
+
+    for (uint16_t i = 0; i < conn_handles.len; i++)
+    {
+        if (im_peer_id_get_by_conn_handle(conn_handles.flag_keys[i]) == PM_PEER_ID_INVALID)
+        {
+            ble_conn_state_user_flag_set(conn_handles.flag_keys[i], m_flag_service_changed_pending, true);
+        }
+    }
+
+    service_changed_pending_flags_check();
+}
+#endif // NRF_MODULE_ENABLED(PEER_MANAGER)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/gatt_cache_manager.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,242 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef GATT_CACHE_MANAGER_H__
+#define GATT_CACHE_MANAGER_H__
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "headers/ble.h"
+#include "ble_gap.h"
+#include "peer_manager_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup gatt_cache_manager GATT Cache Manager
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. A module for managing persistent storing of GATT
+ *        attributes.
+ */
+
+
+/**@brief Events that can come from the GATT Cache Manager module.
+ */
+typedef enum
+{
+    GCM_EVT_LOCAL_DB_CACHE_STORED,           /**< The persistent cache for the local database has been updated with provided values, for one peer. */
+    GCM_EVT_LOCAL_DB_CACHE_UPDATED,          /**< The persistent cache for the local database has been updated with values from the SoftDevice, for one peer. */
+    GCM_EVT_LOCAL_DB_CACHE_APPLIED,          /**< The SoftDevice has been given local database values from the persistent cache, for one peer. */
+    GCM_EVT_ERROR_LOCAL_DB_CACHE_APPLY,      /**< The stored local database values for a peer were rejected by the SoftDevice, which means the database has changed. */
+    GCM_EVT_REMOTE_DB_CACHE_UPDATED,         /**< The persistent cache for the remote database has been updated with provided values, for one peer. */
+    GCM_EVT_SERVICE_CHANGED_IND_SENT,        /**< A service changed indication has been sent to a peer. */
+    GCM_EVT_SERVICE_CHANGED_IND_CONFIRMED,   /**< A sent service changed indication has been confirmed by a peer. */
+    GCM_EVT_ERROR_DATA_SIZE,                 /**< An operation failed because the write buffer of the Peer Database module was not large enough. This is a fatal error. */
+    GCM_EVT_ERROR_STORAGE_FULL,              /**< An operation failed because there was no available storage room in persistent storage. Please free up room, and the operation will automatically continue. */
+    GCM_EVT_ERROR_UNEXPECTED,                /**< An operation failed with an unexpected error. The error is provided. This is possibly a fatal error. */
+} gcm_evt_id_t;
+
+
+/**@brief A structure meant to be used for event parameters for multiple event types.
+ */
+typedef struct
+{
+    uint16_t conn_handle;  /**< The connection handle. Likely the connection handle an event pertains to. */
+} gcm_evt_param_conn_handle_t;
+
+
+/**@brief Structure containing an event from the GCM module.
+ */
+typedef struct
+{
+    gcm_evt_id_t   evt_id;  /**< The type of event this is. */
+    pm_peer_id_t   peer_id; /**< The peer ID this event pertains to. */
+    union
+    {
+        gcm_evt_param_conn_handle_t local_db_cache_updated;
+        gcm_evt_param_conn_handle_t local_db_cache_applied;
+        gcm_evt_param_conn_handle_t error_local_db_cache_apply;
+        gcm_evt_param_conn_handle_t service_changed_ind_sent;
+        gcm_evt_param_conn_handle_t service_changed_ind_confirmed;
+        gcm_evt_param_conn_handle_t error_data_size;
+        gcm_evt_param_conn_handle_t error_no_mem;
+        struct
+        {
+            uint16_t   conn_handle; /**< The handle of the connection the event pertains to. */
+            ret_code_t error;       /**< The unexpected error that occurred. */
+        } error_unexpected;
+    } params; /**< Event specific parameters. Chosen based on evt_id. */
+} gcm_evt_t;
+
+/**@brief Event handler for events from the GATT Cache Manager module.
+ *
+ * @param[in]  event   The event that has happened.
+ * @param[in]  peer  The id of the peer the event pertains to.
+ * @param[in]  flags   The data the event pertains to.
+ */
+typedef void (*gcm_evt_handler_t)(gcm_evt_t const * p_event);
+
+
+/**@brief Function for initializing the GATT Cache Manager module.
+ *
+ * @retval NRF_SUCCESS         Initialization was successful.
+ * @retval NRF_ERROR_INTERNAL  If an internal error occurred.
+ */
+ret_code_t gcm_init(void);
+
+
+/**@brief Function for dispatching SoftDevice events to the GATT Cache Manager module.
+ *
+ * @param[in]  p_ble_evt  The SoftDevice event.
+ */
+void gcm_ble_evt_handler(ble_evt_t * p_ble_evt);
+
+
+
+/**@brief Function for storing a discovered remote database persistently.
+ *
+ * @param[in]  peer_id      Peer to store the database for.
+ * @param[in]  p_remote_db  Database values to store as an array. Can be NULL if n_services is 0.
+ * @param[in]  n_services   Number of services in p_remote_db array. If 0, values are cleared.
+ *
+ * @retval NRF_SUCCESS              Store procedure successfully started.
+ * @retval NRF_ERROR_NOT_FOUND      The peer id is invalid or unallocated.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t gcm_remote_db_store(pm_peer_id_t        peer_id,
+                               ble_gatt_db_srv_t * p_remote_db,
+                               uint32_t            n_services);
+
+
+/**@brief Function for retrieving a persistently stored remote database.
+ *
+ * @param[in]    peer_id      Peer to retrieve data for.
+ * @param[out]   p_remote_db  If p_n_services was large enough: Copied database values.
+ * @param[inout] p_n_services In: Size of provided p_remote_db array. Out: Size of data in flash.
+ *
+ * @note p_n_services is always updated with the size of the data to be retrieved. The data is only
+ *       copied if p_remote_db is large enough (p_n_services is large enough initially).
+ *
+ * @retval NRF_SUCCESS              Data retrieved successfully.
+ * @retval NRF_ERROR_NOT_FOUND      The peer ID is invalid or unallocated.
+ * @retval NRF_ERROR_NULL           p_remote_db is NULL.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t gcm_remote_db_retrieve(pm_peer_id_t        peer_id,
+                                  ble_gatt_db_srv_t * p_remote_db,
+                                  uint32_t          * p_n_services);
+
+
+/**@brief Function for triggering local GATT database data to be stored persistently. Values are
+ *        retrieved from SoftDevice and written to persistent storage.
+ *
+ * @note This function is only needed when you want to override the regular functionality of the
+ *       module, e.g. to immediately store to flash instead of waiting for the native logic to
+ *       perform the update.
+ *
+ * @param[in]  conn_handle  Connection handle to perform update on.
+ *
+ * @retval NRF_SUCCESS                    Store operation started.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE  conn_handle does not refer to an active, bonded connection.
+ * @retval NRF_ERROR_DATA_SIZE            Write buffer not large enough. Call will never work with
+ *                                        this GATT database.
+ * @retval NRF_ERROR_STORAGE_FULL         No room in persistent_storage. Free up space; the
+ *                                        operation will be automatically reattempted after the
+ *                                        next FDS garbage collection procedure.
+ * @retval NRF_ERROR_INVALID_STATE        Module is not initialized.
+ */
+ret_code_t gcm_local_db_cache_update(uint16_t conn_handle);
+
+
+/**@brief Function for setting new values in the local database cache.
+ *
+ * @note If the peer is connected, the values will also be applied immediately to the connection.
+ * @note This function is only needed when you want to override the regular functionality of the
+ *       module.
+ * @note The data in the pointer must be available until the GCM_EVT_LOCAL_DB_CACHE_SET event is
+ *       received.
+ *
+ * @param[in]  peer_id     Peer to set values for.
+ * @param[in]  p_local_db  Database values to apply. If NULL, the values will instead be cleared.
+ *
+ * @retval NRF_SUCCESS              Operation started, and values were applied (if connected).
+ * @retval NRF_ERROR_NOT_FOUND      The peer ID was invalid or unallocated.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t gcm_local_db_cache_set(pm_peer_id_t peer_id, pm_peer_data_local_gatt_db_t * p_local_db);
+
+
+/**@brief Function for retrieving values in the local database cache.
+ *
+ * @note This function is not needed for regular operation of the module.
+ *
+ * @param[in]  peer_id     Peer to get values for.
+ * @param[out] p_local_db  Database values.
+ *
+ * @retval NRF_SUCCESS              Values retrieved successfully.
+ * @retval NRF_ERROR_NOT_FOUND      The peer ID was invalid or unallocated.
+ * @retval NRF_ERROR_NULL           p_local_db was NULL.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t gcm_local_db_cache_get(pm_peer_id_t peer_id, pm_peer_data_local_gatt_db_t * p_local_db);
+
+
+/**@brief Function for manually informing that the local database has changed.
+ *
+ * @details This causes a service changed notification to be sent to all bonded peers that
+ *          subscribe to it.
+ */
+void gcm_local_database_has_changed(void);
+
+/** @}
+  * @endcond
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GATT_CACHE_MANAGER_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/gatts_cache_manager.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,389 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(PEER_MANAGER)
+#include "gatts_cache_manager.h"
+
+#include <string.h>
+#include "ble_gap.h"
+#include "peer_manager_types.h"
+#include "peer_manager_internal.h"
+#include "peer_database.h"
+#include "id_manager.h"
+
+
+// Syntactic sugar, two spoons.
+#define SYS_ATTR_SYS                    (BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS)
+#define SYS_ATTR_USR                    (BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS)
+#define SYS_ATTR_BOTH                   (SYS_ATTR_SYS | SYS_ATTR_USR)
+
+// The number of registered event handlers.
+#define GSCM_EVENT_HANDLERS_CNT         (sizeof(m_evt_handler) / sizeof(m_evt_handler[0]))
+
+
+// GATTS Cache Manager event handler in Peer Manager.
+extern void gcm_gscm_evt_handler(gscm_evt_t const * p_event);
+
+// GATTS Cache Manager events' handlers.
+// The number of elements in this array is GSCM_EVENT_HANDLERS_CNT.
+static gscm_evt_handler_t m_evt_handler[] =
+{
+    gcm_gscm_evt_handler
+};
+
+static bool               m_module_initialized;
+static pm_peer_id_t       m_current_sc_store_peer_id;
+
+
+/**@brief Function for resetting the module variable(s) of the GSCM module.
+ */
+static void internal_state_reset()
+{
+    m_module_initialized       = false;
+    m_current_sc_store_peer_id = PM_PEER_ID_INVALID;
+}
+
+
+static void evt_send(gscm_evt_t const * p_event)
+{
+    for (uint32_t i = 0; i < GSCM_EVENT_HANDLERS_CNT; i++)
+    {
+        m_evt_handler[i](p_event);
+    }
+}
+
+
+//lint -save -e550
+/**@brief Function for storing service_changed_pending = true to flash for all peers, in sequence.
+ *
+ * This function aborts if it gets @ref NRF_ERROR_BUSY when trying to store. A subsequent call will
+ * continue where the last call was aborted.
+ */
+static void service_changed_pending_set(void)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    ret_code_t err_code;
+    // Use a uint32_t to enforce 4-byte alignment.
+    static const uint32_t service_changed_pending = true;
+
+    //lint -save -e65 -e64
+    pm_peer_data_const_t peer_data =
+    {
+        .data_id                   = PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING,
+        .length_words              = PM_SC_STATE_N_WORDS(),
+        .p_service_changed_pending = (bool*)&service_changed_pending,
+    };
+    //lint -restore
+
+    err_code = pdb_raw_store(m_current_sc_store_peer_id, &peer_data, NULL);
+    while ((m_current_sc_store_peer_id != PM_PEER_ID_INVALID) && (err_code != NRF_ERROR_BUSY))
+    {
+        m_current_sc_store_peer_id = pdb_next_peer_id_get(m_current_sc_store_peer_id);
+        err_code = pdb_raw_store(m_current_sc_store_peer_id, &peer_data, NULL);
+    }
+}
+//lint -restore
+
+
+
+/**@brief Event handler for events from the Peer Database module.
+ *        This function is extern in Peer Database.
+ *
+ * @param[in]  p_event The event that has happend with peer id and flags.
+ */
+void gscm_pdb_evt_handler(pdb_evt_t const * p_event)
+{
+    if (p_event->evt_id == PDB_EVT_RAW_STORED)
+    {
+        if (p_event->data_id == PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING)
+        {
+            ret_code_t           err_code;
+            pm_peer_data_flash_t peer_data;
+
+            err_code = pdb_peer_data_ptr_get(p_event->peer_id,
+                                             PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING,
+                                             &peer_data);
+
+            if (err_code == NRF_SUCCESS)
+            {
+                gscm_evt_t gscm_evt;
+                gscm_evt.evt_id = GSCM_EVT_SC_STATE_STORED;
+                gscm_evt.peer_id = p_event->peer_id;
+                gscm_evt.params.sc_state_stored.state = &peer_data.p_service_changed_pending;
+
+                evt_send(&gscm_evt);
+            }
+        }
+    }
+
+    if (m_current_sc_store_peer_id != PM_PEER_ID_INVALID)
+    {
+        service_changed_pending_set();
+    }
+}
+
+
+ret_code_t gscm_init()
+{
+    NRF_PM_DEBUG_CHECK(!m_module_initialized);
+
+    internal_state_reset();
+    m_module_initialized = true;
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t gscm_local_db_cache_update(uint16_t conn_handle)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    pm_peer_id_t peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+    ret_code_t   err_code;
+
+    if (peer_id == PM_PEER_ID_INVALID)
+    {
+        return BLE_ERROR_INVALID_CONN_HANDLE;
+    }
+    else
+    {
+        pm_peer_data_t peer_data;
+        uint16_t       n_bufs = 1;
+        bool           retry_with_bigger_buffer = false;
+
+        do
+        {
+            retry_with_bigger_buffer = false;
+
+            err_code = pdb_write_buf_get(peer_id, PM_PEER_DATA_ID_GATT_LOCAL, n_bufs++, &peer_data);
+            if (err_code == NRF_SUCCESS)
+            {
+                pm_peer_data_local_gatt_db_t * p_local_gatt_db = peer_data.p_local_gatt_db;
+
+                p_local_gatt_db->flags = SYS_ATTR_BOTH;
+
+                err_code = sd_ble_gatts_sys_attr_get(conn_handle, &p_local_gatt_db->data[0], &p_local_gatt_db->len, p_local_gatt_db->flags);
+
+                if (err_code == NRF_SUCCESS)
+                {
+                    err_code = pdb_write_buf_store(peer_id, PM_PEER_DATA_ID_GATT_LOCAL);
+                }
+                else
+                {
+                    if (err_code == NRF_ERROR_DATA_SIZE)
+                    {
+                        // The sys attributes are bigger than the requested write buffer.
+                        retry_with_bigger_buffer = true;
+                    }
+                    else if (err_code == NRF_ERROR_NOT_FOUND)
+                    {
+                        // There are no sys attributes in the GATT db, so nothing needs to be stored.
+                        err_code = NRF_SUCCESS;
+                    }
+
+                    ret_code_t err_code_release = pdb_write_buf_release(peer_id, PM_PEER_DATA_ID_GATT_LOCAL);
+                    if (err_code_release != NRF_SUCCESS)
+                    {
+                        err_code = NRF_ERROR_INTERNAL;
+                    }
+                }
+            }
+            else if (err_code == NRF_ERROR_INVALID_PARAM)
+            {
+                // The sys attributes are bigger than the entire write buffer.
+                err_code = NRF_ERROR_DATA_SIZE;
+            }
+        } while (retry_with_bigger_buffer);
+    }
+
+    return err_code;
+}
+
+
+ret_code_t gscm_local_db_cache_apply(uint16_t conn_handle)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    pm_peer_id_t         peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+    ret_code_t           err_code;
+    pm_peer_data_flash_t peer_data;
+    uint8_t      const * p_sys_attr_data = NULL;
+    uint16_t             sys_attr_len    = 0;
+    uint32_t             sys_attr_flags  = (SYS_ATTR_BOTH);
+    bool                 all_attributes_applied = true;
+
+    if (peer_id != PM_PEER_ID_INVALID)
+    {
+        err_code = pdb_peer_data_ptr_get(peer_id, PM_PEER_DATA_ID_GATT_LOCAL, &peer_data);
+        if (err_code == NRF_SUCCESS)
+        {
+            pm_peer_data_local_gatt_db_t const * p_local_gatt_db;
+
+            p_local_gatt_db = peer_data.p_local_gatt_db;
+            p_sys_attr_data = p_local_gatt_db->data;
+            sys_attr_len    = p_local_gatt_db->len;
+            sys_attr_flags  = p_local_gatt_db->flags;
+        }
+    }
+
+    do
+    {
+        err_code = sd_ble_gatts_sys_attr_set(conn_handle, p_sys_attr_data, sys_attr_len, sys_attr_flags);
+
+        if (err_code == NRF_ERROR_NO_MEM)
+        {
+            err_code = NRF_ERROR_BUSY;
+        }
+        else if (err_code == NRF_ERROR_INVALID_STATE)
+        {
+            err_code = NRF_SUCCESS;
+        }
+        else if (err_code == NRF_ERROR_INVALID_DATA)
+        {
+            all_attributes_applied = false;
+
+            if (sys_attr_flags & SYS_ATTR_USR)
+            {
+                // Try setting only system attributes.
+                sys_attr_flags = SYS_ATTR_SYS;
+            }
+            else if (p_sys_attr_data || sys_attr_len)
+            {
+                // Try reporting that none exist.
+                p_sys_attr_data = NULL;
+                sys_attr_len    = 0;
+                sys_attr_flags  = SYS_ATTR_BOTH;
+            }
+            else
+            {
+                err_code = NRF_ERROR_INTERNAL;
+            }
+        }
+    } while (err_code == NRF_ERROR_INVALID_DATA);
+
+    if (!all_attributes_applied)
+    {
+        err_code = NRF_ERROR_INVALID_DATA;
+    }
+
+    return err_code;
+}
+
+
+ret_code_t gscm_local_db_cache_set(pm_peer_id_t peer_id, pm_peer_data_local_gatt_db_t * p_local_db)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    pm_peer_data_const_t peer_data;
+
+    memset(&peer_data, 0, sizeof(pm_peer_data_const_t));
+    peer_data.data_id = PM_PEER_DATA_ID_GATT_LOCAL;
+    peer_data.p_local_gatt_db = p_local_db;
+
+    return pdb_raw_store(peer_id, &peer_data, NULL);
+}
+
+
+void gscm_local_database_has_changed(void)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    m_current_sc_store_peer_id = pdb_next_peer_id_get(PM_PEER_ID_INVALID);
+    service_changed_pending_set();
+}
+
+
+bool gscm_service_changed_ind_needed(uint16_t conn_handle)
+{
+    ret_code_t err_code;
+    pm_peer_data_flash_t peer_data;
+    pm_peer_id_t peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+
+    err_code = pdb_peer_data_ptr_get(peer_id, PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING, &peer_data);
+
+    if (err_code != NRF_SUCCESS)
+    {
+        return false;
+    }
+
+    return *peer_data.p_service_changed_pending;
+}
+
+
+ret_code_t gscm_service_changed_ind_send(uint16_t conn_handle)
+{
+    static uint16_t start_handle = 0x0000;
+    const  uint16_t end_handle   = 0xFFFF;
+    ret_code_t err_code;
+
+    do
+    {
+        err_code = sd_ble_gatts_service_changed(conn_handle, start_handle, end_handle);
+        if (err_code == BLE_ERROR_INVALID_ATTR_HANDLE)
+        {
+            start_handle += 1;
+        }
+    } while (err_code == BLE_ERROR_INVALID_ATTR_HANDLE);
+
+    return err_code;
+}
+
+
+void gscm_db_change_notification_done(pm_peer_id_t peer_id)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    // Use a uint32_t to enforce 4-byte alignment.
+    static const uint32_t service_changed_pending = false;
+
+    //lint -save -e65 -e64
+    pm_peer_data_const_t peer_data =
+    {
+        .data_id                   = PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING,
+        .length_words              = PM_SC_STATE_N_WORDS(),
+        .p_service_changed_pending = (bool*)&service_changed_pending,
+    };
+    //lint -restore
+
+    // Don't need to check return code, because all error conditions can be ignored.
+    //lint -save -e550
+    (void) pdb_raw_store(peer_id, &peer_data, NULL);
+    //lint -restore
+}
+#endif // NRF_MODULE_ENABLED(PEER_MANAGER)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/gatts_cache_manager.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,234 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef GATTS_CACHE_MANAGER_H__
+#define GATTS_CACHE_MANAGER_H__
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "headers/ble.h"
+#include "ble_gap.h"
+#include "peer_manager_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup gatts_cache_manager GATT Server Cache Manager
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. A module for managing persistent storing of GATT
+ *        attributes pertaining to the GATT server role of the local device.
+ */
+
+
+/**@brief Events that can come from the GATT Server Cache Manager module.
+ */
+typedef enum
+{
+    GSCM_EVT_LOCAL_DB_CACHE_STORED,  /**< The persistent cache for the local database has been updated with provided values, for one peer. */
+    GSCM_EVT_LOCAL_DB_CACHE_UPDATED, /**< The persistent cache for the local database has been updated with values from the SoftDevice, for one peer. */
+    GSCM_EVT_SC_STATE_STORED,        /**< The service changed pending flag in persistent storage has been updated, for one peer. */
+} gscm_evt_id_t;
+
+
+/**@brief Structure containing an event from the GSCM module.
+ */
+typedef struct
+{
+    gscm_evt_id_t evt_id;          /**< The type of event this is. */
+    pm_peer_id_t  peer_id;         /**< The peer ID this event pertains to. */
+    union
+    {
+        struct
+        {
+            uint16_t conn_handle;  /**< The connection this event pertains to. */
+        } local_db_cache_updated;
+        struct
+        {
+            bool state;            /**< The newly stored state of the Service Changed pending flag. */
+        } sc_state_stored;
+    } params;                      /**< Event parameters specific to certain event types. */
+} gscm_evt_t;
+
+/**@brief Event handler for events from the GATT Server Cache Manager module.
+ *
+ * @param[in]  event   The event that has happened.
+ * @param[in]  peer  The id of the peer the event pertains to.
+ * @param[in]  flags   The data the event pertains to.
+ */
+typedef void (*gscm_evt_handler_t)(gscm_evt_t const * p_event);
+
+
+/**@brief Function for initializing the GATT Server Cache Manager module.
+ *
+ * @retval NRF_SUCCESS         Initialization was successful.
+ * @retval NRF_ERROR_INTERNAL  If an internal error occurred.
+ */
+ret_code_t gscm_init(void);
+
+
+/**@brief Function for triggering local GATT database data to be stored persistently. Values are
+ *        retrieved from the SoftDevice and written to persistent storage.
+ *
+ * @param[in]  conn_handle  Connection handle to perform update on.
+ *
+ * @retval NRF_SUCCESS                    Store operation started.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE  conn_handle does not refer to an active connection with a
+ *                                        bonded peer.
+ * @retval NRF_ERROR_BUSY                 Unable to perform operation at this time. Reattempt later.
+ * @retval NRF_ERROR_DATA_SIZE            Write buffer not large enough. Call will never work with
+ *                                        this GATT database.
+ * @retval NRF_ERROR_STORAGE_FULL         No room in persistent_storage. Free up space; the
+ *                                        operation will be automatically reattempted after the
+ *                                        next FDS garbage collection procedure.
+ * @retval NRF_ERROR_INVALID_STATE        Module is not initialized.
+ */
+ret_code_t gscm_local_db_cache_update(uint16_t conn_handle);
+
+
+/**@brief Function for applying stored local GATT database data to the SoftDevice. Values are
+ *        retrieved from persistent storage and given to the SoftDevice.
+ *
+ * @param[in]  conn_handle  Connection handle to apply values to.
+ *
+ * @retval NRF_SUCCESS                    Store operation started.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE  conn_handle does not refer to an active connection with a
+ *                                        bonded peer.
+ * @retval NRF_ERROR_INVALID_DATA         The stored data was rejected by the SoftDevice, which
+ *                                        probably means that the local database has changed. The
+ *                                        system part of the sys_attributes was attempted applied,
+ *                                        so service changed indications can be sent to subscribers.
+ * @retval NRF_ERROR_BUSY                 Unable to perform operation at this time. Reattempt later.
+ * @retval NRF_ERROR_INVALID_STATE        Module is not initialized.
+ * @return An unexpected return value from an internal function call.
+ */
+ret_code_t gscm_local_db_cache_apply(uint16_t conn_handle);
+
+
+/**@brief Function for setting new values in the local database cache.
+ *
+ * @note If the peer is connected, the values will also be applied immediately to the connection.
+ * @note The data in the pointer must be available until the GSCM_EVT_LOCAL_DB_STORED event is
+ *       received.
+ *
+ * @param[in]  peer_id     Peer to set values for.
+ * @param[in]  p_local_db  Database values to apply. If NULL, the values will instead be cleared.
+ *
+ * @retval NRF_SUCCESS              Operation started, and values were applied (if connected).
+ * @retval NRF_ERROR_NOT_FOUND      The peer ID was invalid or unallocated.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ * @return An unexpected return value from an internal function call.
+ */
+ret_code_t gscm_local_db_cache_set(pm_peer_id_t peer_id, pm_peer_data_local_gatt_db_t * p_local_db);
+
+
+/**@brief Function for retrieving values in the local database cache.
+ *
+ * @param[in]    peer_id     Peer to get values for.
+ * @param[inout] p_local_db  Where to store the data. The length field needs to reflect the
+ *                           available buffer space. On a successful read, the length field is
+ *                           updated to match the length of the read data.
+ *
+ * @retval NRF_SUCCESS              Values retrieved successfully.
+ * @retval NRF_ERROR_NOT_FOUND      The peer ID was invalid or unallocated.
+ * @retval NRF_ERROR_NULL           p_local_db was NULL.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t gscm_local_db_cache_get(pm_peer_id_t peer_id, pm_peer_data_local_gatt_db_t * p_local_db);
+
+
+/**@brief Function for storing the fact that the local database has changed, for all currently
+ *        bonded peers.
+ *
+ * @note This will cause a later call to @ref gscm_service_changed_ind_needed to return true for
+ *       a connection with a currently bonded peer.
+ */
+void gscm_local_database_has_changed(void);
+
+
+/**@brief Function for checking if a service changed indication should be sent.
+ *
+ * @param[in]  conn_handle  The connection to check.
+ *
+ * @return true if a service changed indication should be sent, false if not.
+ */
+bool gscm_service_changed_ind_needed(uint16_t conn_handle);
+
+
+/**@brief Function for sending a service changed indication to a connected peer.
+ *
+ * @param[in]  conn_handle  The connection to send the indication on.
+ *
+ * @retval NRF_SUCCESS                       Indication sent or not needed.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE     conn_handle does not refer to an active connection.
+ * @retval NRF_ERROR_BUSY                    Unable to send indication at this time. Reattempt later.
+ * @retval BLE_ERROR_GATTS_SYS_ATTR_MISSING  Information missing. Apply local cache, then reattempt.
+ * @retval NRF_ERROR_INVALID_PARAM           From @ref sd_ble_gatts_service_changed. Unexpected.
+ * @retval NRF_ERROR_NOT_SUPPORTED           Service changed characteristic is not present.
+ * @retval NRF_ERROR_INVALID_STATE           Service changed cannot be indicated to this peer
+ *                                           because the peer has not subscribed to it.
+ */
+ret_code_t gscm_service_changed_ind_send(uint16_t conn_handle);
+
+
+/**@brief Function for specifying that a peer has been made aware of the latest local database
+ *        change.
+ *
+ * @note After calling this, a later call to @ref gscm_service_changed_ind_needed will to return
+ *       false for this peer unless @ref gscm_local_database_has_changed is called again.
+ *
+ * @param[in]  peer_id  The connection to send the indication on.
+ */
+void gscm_db_change_notification_done(pm_peer_id_t peer_id);
+
+/** @}
+ * @endcond
+*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GATTS_CACHE_MANAGER_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/id_manager.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,1093 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(PEER_MANAGER)
+#include "id_manager.h"
+
+#include <string.h>
+#include "headers/ble.h"
+#include "ble_gap.h"
+#include "ble_conn_state.h"
+#include "peer_manager_types.h"
+#include "peer_database.h"
+#include "peer_data_storage.h"
+#include "nrf_soc.h"
+
+
+#define IM_MAX_CONN_HANDLES             (8)
+#define IM_NO_INVALID_CONN_HANDLES      (0xFF)
+#define IM_ADDR_CLEARTEXT_LENGTH        (3)
+#define IM_ADDR_CIPHERTEXT_LENGTH       (3)
+
+// The number of registered event handlers.
+#define IM_EVENT_HANDLERS_CNT           (sizeof(m_evt_handlers) / sizeof(m_evt_handlers[0]))
+
+
+// Identity Manager event handlers in Peer Manager and GATT Cache Manager.
+extern void pm_im_evt_handler(im_evt_t const * p_event);
+extern void gcm_im_evt_handler(im_evt_t const * p_event);
+
+// Identity Manager events' handlers.
+// The number of elements in this array is IM_EVENT_HANDLERS_CNT.
+static im_evt_handler_t const m_evt_handlers[] =
+{
+    pm_im_evt_handler,
+    gcm_im_evt_handler
+};
+
+
+typedef struct
+{
+    pm_peer_id_t   peer_id;
+    uint16_t       conn_handle;
+    ble_gap_addr_t peer_address;
+} im_connection_t;
+
+static bool                             m_module_initialized;
+static im_connection_t                  m_connections[8];
+static ble_conn_state_user_flag_id_t    m_conn_state_user_flag_id;
+
+static uint8_t                          m_wlisted_peer_cnt;
+static pm_peer_id_t                     m_wlisted_peers[BLE_GAP_WHITELIST_ADDR_MAX_COUNT];
+
+#if (NRF_SD_BLE_API_VERSION <= 2)
+    static ble_gap_addr_t               m_current_id_addr;
+#endif
+
+
+static void internal_state_reset()
+{
+    m_conn_state_user_flag_id = BLE_CONN_STATE_USER_FLAG_INVALID;
+
+    for (uint32_t i = 0; i < IM_MAX_CONN_HANDLES; i++)
+    {
+        m_connections[i].conn_handle = BLE_CONN_HANDLE_INVALID;
+    }
+}
+
+
+/**@brief Function for sending an event to all registered event handlers.
+ *
+ * @param[in] p_event The event to distribute.
+ */
+static void evt_send(im_evt_t * p_event)
+{
+    for (uint32_t i = 0; i < IM_EVENT_HANDLERS_CNT; i++)
+    {
+        m_evt_handlers[i](p_event);
+    }
+}
+
+/**@brief Function finding a free position in m_connections.
+ *
+ * @detail All connection handles in the m_connections array are checked against the connection
+ *         state module. The index of the first one that is not a connection handle for a current
+ *         connection is returned. This position in the array can safely be used for a new connection.
+ *
+ * @return Either the index of a free position in the array or IM_NO_INVALID_CONN_HANDLES if no free
+           position exists.
+ */
+uint8_t get_free_connection()
+{
+    for (uint32_t i = 0; i < IM_MAX_CONN_HANDLES; i++)
+    {
+        // Query the connection state module to check if the
+        // connection handle does not belong to a valid connection.
+        if (!ble_conn_state_user_flag_get(m_connections[i].conn_handle, m_conn_state_user_flag_id))
+        {
+            return i;
+        }
+    }
+    // If all connection handles belong to a valid connection, return IM_NO_INVALID_CONN_HANDLES.
+    return IM_NO_INVALID_CONN_HANDLES;
+}
+
+
+/**@brief Function finding a particular connection handle m_connections.
+ *
+ * @param[in]  conn_handle  The handle to find.
+ *
+ * @return Either the index of the conn_handle in the array or IM_NO_INVALID_CONN_HANDLES if the
+ *         handle was not found.
+ */
+uint8_t get_connection_by_conn_handle(uint16_t conn_handle)
+{
+    if (ble_conn_state_user_flag_get(conn_handle, m_conn_state_user_flag_id))
+    {
+        for (uint32_t i = 0; i < IM_MAX_CONN_HANDLES; i++)
+        {
+            if (m_connections[i].conn_handle == conn_handle)
+            {
+                return i;
+            }
+        }
+    }
+    // If all connection handles belong to a valid connection, return IM_NO_INVALID_CONN_HANDLES.
+    return IM_NO_INVALID_CONN_HANDLES;
+}
+
+
+/**@brief Function for registering a new connection instance.
+ *
+ * @param[in]  conn_handle  The handle of the new connection.
+ * @param[in]  p_ble_addr   The address used to connect.
+ *
+ * @return Either the index of the new connection in the array or IM_NO_INVALID_CONN_HANDLES if no
+ *         free position exists.
+ */
+uint8_t new_connection(uint16_t conn_handle, ble_gap_addr_t * p_ble_addr)
+{
+    uint8_t conn_index = IM_NO_INVALID_CONN_HANDLES;
+
+    if ((p_ble_addr != NULL) && (conn_handle != BLE_CONN_HANDLE_INVALID))
+    {
+        ble_conn_state_user_flag_set(conn_handle, m_conn_state_user_flag_id, true);
+
+        conn_index = get_connection_by_conn_handle(conn_handle);
+        if (conn_index == IM_NO_INVALID_CONN_HANDLES)
+        {
+            conn_index = get_free_connection();
+        }
+
+        if (conn_index != IM_NO_INVALID_CONN_HANDLES)
+        {
+            m_connections[conn_index].conn_handle  = conn_handle;
+            m_connections[conn_index].peer_id      = PM_PEER_ID_INVALID;
+            m_connections[conn_index].peer_address = *p_ble_addr;
+        }
+    }
+    return conn_index;
+}
+
+
+/**@brief Function checking the validity of an IRK
+ *
+ * @detail An all-zero IRK is not valid. This function will check if a given IRK is valid.
+ *
+ * @param[in] p_irk The IRK for which the validity is going to be checked.
+ *
+ * @retval true  The IRK is valid.
+ * @retval false The IRK is invalid.
+ */
+bool is_valid_irk(ble_gap_irk_t const * p_irk)
+{
+    NRF_PM_DEBUG_CHECK(p_irk != NULL);
+
+    for (uint32_t i = 0; i < BLE_GAP_SEC_KEY_LEN; i++)
+    {
+        if (p_irk->irk[i] != 0)
+        {
+            return true;
+        }
+    }
+    return false;
+}
+
+
+/**@brief Function for comparing two addresses to determine if they are identical
+ *
+ * @note The address type need to be identical, as well as every bit in the address itself.
+ *
+ * @param[in] p_addr1 The first address to be compared.
+ * @param[in] p_addr2 The second address to be compared.
+ *
+ * @retval true  The addresses are identical.
+ * @retval false The addresses are not identical.
+ */
+bool addr_compare(ble_gap_addr_t const * p_addr1, ble_gap_addr_t const * p_addr2)
+{
+    // @note emdi: use NRF_PM_DEBUG_CHECK ?
+    if ((p_addr1 == NULL) || (p_addr2 == NULL))
+    {
+        return false;
+    }
+
+    // Check that the addr type is identical, return false if it is not
+    if (p_addr1->addr_type != p_addr2->addr_type)
+    {
+        return false;
+    }
+    // Check if the addr bytes are is identical
+    return (memcmp(p_addr1->addr, p_addr2->addr, BLE_GAP_ADDR_LEN) == 0);
+}
+
+
+void im_ble_evt_handler(ble_evt_t * ble_evt)
+{
+    ble_gap_evt_t gap_evt;
+    pm_peer_id_t  bonded_matching_peer_id;
+
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    if (ble_evt->header.evt_id != BLE_GAP_EVT_CONNECTED)
+    {
+        // Nothing to do.
+        return;
+    }
+
+    gap_evt                 = ble_evt->evt.gap_evt;
+    bonded_matching_peer_id = PM_PEER_ID_INVALID;
+
+    if (   gap_evt.params.connected.peer_addr.addr_type
+        != BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE)
+    {
+        /* Search the database for bonding data matching the one that triggered the event.
+         * Public and static addresses can be matched on address alone, while resolvable
+         * random addresses can be resolved agains known IRKs. Non-resolvable random addresses
+         * are never matching because they are not longterm form of identification.
+         */
+
+        pm_peer_id_t         peer_id;
+        pm_peer_data_flash_t peer_data;
+
+        pds_peer_data_iterate_prepare();
+
+        switch (gap_evt.params.connected.peer_addr.addr_type)
+        {
+            case BLE_GAP_ADDR_TYPE_PUBLIC:
+            case BLE_GAP_ADDR_TYPE_RANDOM_STATIC:
+            {
+                while (pds_peer_data_iterate(PM_PEER_DATA_ID_BONDING, &peer_id, &peer_data))
+                {
+                    if (addr_compare(&gap_evt.params.connected.peer_addr,
+                                     &peer_data.p_bonding_data->peer_ble_id.id_addr_info))
+                    {
+                        bonded_matching_peer_id = peer_id;
+                        break;
+                    }
+                }
+            }
+            break;
+
+            case BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE:
+            {
+                while (pds_peer_data_iterate(PM_PEER_DATA_ID_BONDING, &peer_id, &peer_data))
+                {
+                    if (im_address_resolve(&gap_evt.params.connected.peer_addr,
+                                           &peer_data.p_bonding_data->peer_ble_id.id_info))
+                    {
+                        bonded_matching_peer_id = peer_id;
+                        break;
+                    }
+                }
+            }
+            break;
+
+            default:
+                NRF_PM_DEBUG_CHECK(false);
+                break;
+        }
+    }
+
+    uint8_t new_index = new_connection(gap_evt.conn_handle,
+                                       &gap_evt.params.connected.peer_addr);
+    UNUSED_VARIABLE(new_index);
+
+    if (bonded_matching_peer_id != PM_PEER_ID_INVALID)
+    {
+        im_new_peer_id(gap_evt.conn_handle, bonded_matching_peer_id);
+
+        // Send a bonded peer event
+        im_evt_t im_evt;
+        im_evt.conn_handle = gap_evt.conn_handle;
+        im_evt.evt_id      = IM_EVT_BONDED_PEER_CONNECTED;
+        evt_send(&im_evt);
+    }
+}
+
+
+/**@brief Function to compare two sets of bonding data to check if they belong to the same device.
+ * @note  Invalid irks will never match even though they are identical.
+ *
+ * @param[in]  p_bonding_data1 First bonding data for comparison
+ * @param[in]  p_bonding_data2 Second bonding data for comparison
+ *
+ * @return     True if the input matches, false if it does not.
+ */
+bool im_is_duplicate_bonding_data(pm_peer_data_bonding_t const * p_bonding_data1,
+                                  pm_peer_data_bonding_t const * p_bonding_data2)
+{
+    NRF_PM_DEBUG_CHECK(p_bonding_data1 != NULL);
+    NRF_PM_DEBUG_CHECK(p_bonding_data2 != NULL);
+
+    if (!is_valid_irk(&p_bonding_data1->peer_ble_id.id_info))
+    {
+        return false;
+    }
+
+    bool duplicate_irk = (memcmp(p_bonding_data1->peer_ble_id.id_info.irk,
+                                 p_bonding_data2->peer_ble_id.id_info.irk,
+                                 BLE_GAP_SEC_KEY_LEN) == 0);
+
+    bool duplicate_addr = addr_compare(&p_bonding_data1->peer_ble_id.id_addr_info,
+                                       &p_bonding_data2->peer_ble_id.id_addr_info);
+
+    return duplicate_irk || duplicate_addr;
+}
+
+
+/**@brief Event handler for events from the Peer Database module.
+ *        This function is extern in Peer Database.
+ *
+ * @param[in]  p_event The event that has happend with peer id and flags.
+ */
+void im_pdb_evt_handler(pdb_evt_t const * p_event)
+{
+    ret_code_t           ret;
+    pm_peer_id_t         peer_id;
+    pm_peer_data_flash_t peer_data;
+    pm_peer_data_flash_t peer_data_duplicate;
+
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    NRF_PM_DEBUG_CHECK(p_event != NULL);
+
+    if ((p_event->evt_id  != PDB_EVT_WRITE_BUF_STORED) ||
+        (p_event->data_id != PM_PEER_DATA_ID_BONDING))
+    {
+        return;
+    }
+
+    // If new data about peer id has been stored it is compared to other peers peer ids in
+    // search of duplicates.
+
+    ret = pdb_peer_data_ptr_get(p_event->peer_id, PM_PEER_DATA_ID_BONDING, &peer_data);
+
+    if (ret != NRF_SUCCESS)
+    {
+        // @note emdi: this shouldn't happen, since the data was just stored, right?
+        NRF_PM_DEBUG_CHECK(false);
+        return;
+    }
+
+    pds_peer_data_iterate_prepare();
+
+    while (pds_peer_data_iterate(PM_PEER_DATA_ID_BONDING, &peer_id, &peer_data_duplicate))
+    {
+        if (p_event->peer_id == peer_id)
+        {
+            // Skip the iteration if the bonding data retrieved is for a peer
+            // with the same ID as the one contained in the event.
+            continue;
+        }
+
+        if (im_is_duplicate_bonding_data(peer_data.p_bonding_data,
+                                         peer_data_duplicate.p_bonding_data))
+        {
+            im_evt_t im_evt;
+            im_evt.conn_handle                   = im_conn_handle_get(p_event->peer_id);
+            im_evt.evt_id                        = IM_EVT_DUPLICATE_ID;
+            im_evt.params.duplicate_id.peer_id_1 = p_event->peer_id;
+            im_evt.params.duplicate_id.peer_id_2 = peer_id;
+            evt_send(&im_evt);
+            break;
+        }
+    }
+}
+
+
+ret_code_t im_init(void)
+{
+    NRF_PM_DEBUG_CHECK(!m_module_initialized);
+
+    internal_state_reset();
+
+    m_conn_state_user_flag_id = ble_conn_state_user_flag_acquire();
+    if (m_conn_state_user_flag_id == BLE_CONN_STATE_USER_FLAG_INVALID)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    #if (NRF_SD_BLE_API_VERSION <= 2)
+        ret_code_t ret_code = sd_ble_gap_address_get(&m_current_id_addr);
+        if (ret_code != NRF_SUCCESS)
+        {
+            return NRF_ERROR_INTERNAL;
+        }
+    #endif
+
+    m_module_initialized = true;
+
+    return NRF_SUCCESS;
+}
+
+
+pm_peer_id_t im_peer_id_get_by_conn_handle(uint16_t conn_handle)
+{
+    uint8_t conn_index;
+
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    conn_index = get_connection_by_conn_handle(conn_handle);
+
+    if (conn_index != IM_NO_INVALID_CONN_HANDLES)
+    {
+        return m_connections[conn_index].peer_id;
+    }
+
+    return PM_PEER_ID_INVALID;
+}
+
+
+ret_code_t im_ble_addr_get(uint16_t conn_handle, ble_gap_addr_t * p_ble_addr)
+{
+    uint8_t conn_index;
+
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    NRF_PM_DEBUG_CHECK(p_ble_addr != NULL);
+
+    conn_index = get_connection_by_conn_handle(conn_handle);
+
+    if (conn_index != IM_NO_INVALID_CONN_HANDLES)
+    {
+        *p_ble_addr = m_connections[conn_index].peer_address;
+        return NRF_SUCCESS;
+    }
+
+    return NRF_ERROR_NOT_FOUND;
+}
+
+
+bool im_master_ids_compare(ble_gap_master_id_t const * p_master_id1,
+                           ble_gap_master_id_t const * p_master_id2)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    NRF_PM_DEBUG_CHECK(p_master_id1 != NULL);
+    NRF_PM_DEBUG_CHECK(p_master_id2 != NULL);
+
+    if (!im_master_id_is_valid(p_master_id1))
+    {
+        return false;
+    }
+
+    if (p_master_id1->ediv != p_master_id2->ediv)
+    {
+        return false;
+    }
+
+    return (memcmp(p_master_id1->rand, p_master_id2->rand, BLE_GAP_SEC_RAND_LEN) == 0);
+}
+
+
+pm_peer_id_t im_peer_id_get_by_master_id(ble_gap_master_id_t * p_master_id)
+{
+    pm_peer_id_t         peer_id;
+    pm_peer_data_flash_t peer_data;
+
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    NRF_PM_DEBUG_CHECK(p_master_id != NULL);
+
+    pds_peer_data_iterate_prepare();
+
+    // For each stored peer, check if the master_id matches p_master_id
+    while (pds_peer_data_iterate(PM_PEER_DATA_ID_BONDING, &peer_id, &peer_data))
+    {
+        if (im_master_ids_compare(p_master_id, &peer_data.p_bonding_data->own_ltk.master_id) ||
+            im_master_ids_compare(p_master_id, &peer_data.p_bonding_data->peer_ltk.master_id))
+        {
+            // If a matching master ID is found then return the peer ID.
+            return peer_id;
+        }
+    }
+
+    // If no matching master ID is found return PM_PEER_ID_INVALID.
+    return PM_PEER_ID_INVALID;
+}
+
+
+uint16_t im_conn_handle_get(pm_peer_id_t peer_id)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    for (uint32_t i = 0; i < IM_MAX_CONN_HANDLES; i++)
+    {
+        if (peer_id == m_connections[i].peer_id)
+        {
+            return m_connections[i].conn_handle;
+        }
+    }
+    return BLE_CONN_HANDLE_INVALID;
+}
+
+
+bool im_master_id_is_valid(ble_gap_master_id_t const * p_master_id)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    if (p_master_id->ediv != 0)
+    {
+        return true;
+    }
+
+    for (uint32_t i = 0; i < BLE_GAP_SEC_RAND_LEN; i++)
+    {
+        if (p_master_id->rand[i] != 0)
+        {
+            return true;
+        }
+    }
+    return false;
+}
+
+
+/**@brief Function to set the peer ID associated with a connection handle.
+ *
+ * @param[in]  conn_handle  The connection handle.
+ * @param[in]  peer_id      The peer ID to associate with @c conn_handle.
+ */
+static void peer_id_set(uint16_t conn_handle, pm_peer_id_t peer_id)
+{
+    uint8_t conn_index = get_connection_by_conn_handle(conn_handle);
+    if (conn_index != IM_NO_INVALID_CONN_HANDLES)
+    {
+        m_connections[conn_index].peer_id = peer_id;
+    }
+}
+
+
+void im_new_peer_id(uint16_t conn_handle, pm_peer_id_t peer_id)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    peer_id_set(conn_handle, peer_id);
+}
+
+
+ret_code_t im_peer_free(pm_peer_id_t peer_id)
+{
+    uint16_t   conn_handle;
+    ret_code_t ret;
+
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    conn_handle = im_conn_handle_get(peer_id);
+    ret         = pdb_peer_free(peer_id);
+
+    if ((conn_handle != BLE_CONN_HANDLE_INVALID) && (ret == NRF_SUCCESS))
+    {
+        peer_id_set(conn_handle, PM_PEER_ID_INVALID);
+    }
+    return ret;
+}
+
+
+/**@brief Given a list of peers, loads their GAP address and IRK into the provided buffers.
+ */
+static ret_code_t peers_id_keys_get(pm_peer_id_t   const * p_peers,
+                                    uint32_t               peer_cnt,
+                                    ble_gap_addr_t       * p_gap_addrs,
+                                    uint32_t             * p_addr_cnt,
+                                    ble_gap_irk_t        * p_gap_irks,
+                                    uint32_t             * p_irk_cnt)
+{
+    ret_code_t ret;
+
+    pm_peer_data_bonding_t bond_data;
+    pm_peer_data_t         peer_data;
+
+    uint32_t const buf_size = sizeof(bond_data);
+
+    bool copy_addrs = false;
+    bool copy_irks  = false;
+
+    NRF_PM_DEBUG_CHECK(p_peers != NULL);
+
+    // One of these two has to be provided.
+    NRF_PM_DEBUG_CHECK((p_gap_addrs != NULL) || (p_gap_irks != NULL));
+
+    if ((p_gap_addrs != NULL) && (p_addr_cnt != NULL))
+    {
+        NRF_PM_DEBUG_CHECK((*p_addr_cnt) >= peer_cnt);
+
+        copy_addrs  = true;
+        *p_addr_cnt = 0;
+    }
+
+    if ((p_gap_irks != NULL) && (p_irk_cnt != NULL))
+    {
+        NRF_PM_DEBUG_CHECK((*p_irk_cnt) >= peer_cnt);
+
+        copy_irks  = true;
+        *p_irk_cnt = 0;
+    }
+
+    memset(&peer_data, 0x00, sizeof(peer_data));
+    peer_data.p_bonding_data = &bond_data;
+
+    // Read through flash memory and look for peers ID keys.
+
+    for (uint32_t i = 0; i < peer_cnt; i++)
+    {
+        memset(&bond_data, 0x00, sizeof(bond_data));
+
+        // Read peer data from flash.
+        ret = pds_peer_data_read(p_peers[i], PM_PEER_DATA_ID_BONDING,
+                                 &peer_data, &buf_size);
+
+        if ((ret == NRF_ERROR_NOT_FOUND) || (ret == NRF_ERROR_INVALID_PARAM))
+        {
+            // Peer data coulnd't be found in flash or peer ID is not valid.
+            return NRF_ERROR_NOT_FOUND;
+        }
+
+        uint8_t const addr_type = bond_data.peer_ble_id.id_addr_info.addr_type;
+
+        if ((addr_type != BLE_GAP_ADDR_TYPE_PUBLIC) &&
+            (addr_type != BLE_GAP_ADDR_TYPE_RANDOM_STATIC))
+        {
+            // The address shared by the peer during bonding can't be used for whitelisting.
+            return BLE_ERROR_GAP_INVALID_BLE_ADDR;
+        }
+
+        // Copy the GAP address.
+        if (copy_addrs)
+        {
+            memcpy(&p_gap_addrs[i], &bond_data.peer_ble_id.id_addr_info, sizeof(ble_gap_addr_t));
+            (*p_addr_cnt)++;
+        }
+
+        // Copy the IRK.
+        if (copy_irks)
+        {
+            memcpy(&p_gap_irks[i], bond_data.peer_ble_id.id_info.irk, BLE_GAP_SEC_KEY_LEN);
+            (*p_irk_cnt)++;
+        }
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t im_device_identities_list_set(pm_peer_id_t const * p_peers,
+                                         uint32_t             peer_cnt)
+{
+    #if (NRF_SD_BLE_API_VERSION >= 3)
+
+        ret_code_t             ret;
+        pm_peer_data_t         peer_data;
+        pm_peer_data_bonding_t bond_data;
+
+        ble_gap_id_key_t         keys[BLE_GAP_DEVICE_IDENTITIES_MAX_COUNT];
+        ble_gap_id_key_t const * key_ptrs[BLE_GAP_DEVICE_IDENTITIES_MAX_COUNT];
+
+        if ((p_peers == NULL) || (peer_cnt == 0))
+        {
+            // Clear the device identities list.
+            return sd_ble_gap_device_identities_set(NULL, NULL, 0);
+        }
+
+        peer_data.p_bonding_data = &bond_data;
+        uint32_t const buf_size  = sizeof(bond_data);
+
+        memset(keys, 0x00, sizeof(keys));
+        for (uint32_t i = 0; i < BLE_GAP_DEVICE_IDENTITIES_MAX_COUNT; i++)
+        {
+            key_ptrs[i] = &keys[i];
+        }
+
+        for (uint32_t i = 0; i < peer_cnt; i++)
+        {
+            memset(&bond_data, 0x00, sizeof(bond_data));
+
+            // Read peer data from flash.
+            ret = pds_peer_data_read(p_peers[i], PM_PEER_DATA_ID_BONDING,
+                                     &peer_data, &buf_size);
+
+            if ((ret == NRF_ERROR_NOT_FOUND) || (ret == NRF_ERROR_INVALID_PARAM))
+            {
+                // Peer data coulnd't be found in flash or peer ID is not valid.
+                return NRF_ERROR_NOT_FOUND;
+            }
+
+            uint8_t const addr_type = bond_data.peer_ble_id.id_addr_info.addr_type;
+
+            if ((addr_type != BLE_GAP_ADDR_TYPE_PUBLIC) &&
+                (addr_type != BLE_GAP_ADDR_TYPE_RANDOM_STATIC))
+            {
+                // The address shared by the peer during bonding can't be whitelisted.
+                return BLE_ERROR_GAP_INVALID_BLE_ADDR;
+            }
+
+            // Copy data to the buffer.
+            memcpy(&keys[i], &bond_data.peer_ble_id, sizeof(ble_gap_id_key_t));
+        }
+
+        return sd_ble_gap_device_identities_set(key_ptrs, NULL, peer_cnt);
+
+    #else
+
+        return NRF_ERROR_NOT_SUPPORTED;
+
+    #endif
+}
+
+
+#if (NRF_SD_BLE_API_VERSION <= 2)
+
+static ret_code_t address_set_v2(uint8_t cycle_mode, ble_gap_addr_t * p_addr)
+{
+    NRF_PM_DEBUG_CHECK(p_addr != NULL);
+
+    ret_code_t ret = sd_ble_gap_address_set(cycle_mode, p_addr);
+
+    switch (ret)
+    {
+        case NRF_SUCCESS:
+        case NRF_ERROR_BUSY:
+        case NRF_ERROR_INVALID_STATE:
+        case NRF_ERROR_INVALID_PARAM:           // If cycle_mode is not AUTO or NONE.
+        case BLE_ERROR_GAP_INVALID_BLE_ADDR:    // If the GAP address is not valid.
+            return ret;
+
+        default:
+            return NRF_ERROR_INTERNAL;
+    }
+}
+
+#endif
+
+
+ret_code_t im_id_addr_set(ble_gap_addr_t const * p_addr)
+{
+    #if (NRF_SD_BLE_API_VERSION <= 2)
+
+        ret_code_t     ret;
+        ble_gap_addr_t current_addr;
+
+        NRF_PM_DEBUG_CHECK(p_addr != NULL);
+
+        (void) sd_ble_gap_address_get(&current_addr);
+
+        ret = address_set_v2(BLE_GAP_ADDR_CYCLE_MODE_NONE, (ble_gap_addr_t *)p_addr);
+        if (ret != NRF_SUCCESS)
+        {
+            return ret;
+        }
+
+        if (   current_addr.addr_type == BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE
+            || current_addr.addr_type == BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE)
+        {
+            // If currently using privacy, it must be re-enabled.
+            // We force AUTO when privacy is enabled.
+            ret = address_set_v2(BLE_GAP_ADDR_CYCLE_MODE_AUTO, &current_addr);
+            if (ret != NRF_SUCCESS)
+            {
+                return ret;
+            }
+        }
+
+        memcpy(&m_current_id_addr, p_addr, sizeof(ble_gap_addr_t));
+
+        return NRF_SUCCESS;
+
+    #else
+
+        return sd_ble_gap_addr_set(p_addr);
+
+    #endif
+}
+
+
+ret_code_t im_id_addr_get(ble_gap_addr_t * p_addr)
+{
+    NRF_PM_DEBUG_CHECK(p_addr != NULL);
+
+    #if (NRF_SD_BLE_API_VERSION <= 2)
+        memcpy(p_addr, &m_current_id_addr, sizeof(ble_gap_addr_t));
+        return NRF_SUCCESS;
+    #else
+        return sd_ble_gap_addr_get(p_addr);
+    #endif
+}
+
+
+ret_code_t im_privacy_set(pm_privacy_params_t const * p_privacy_params)
+{
+    #if (NRF_SD_BLE_API_VERSION <= 2)
+
+        ret_code_t     ret;
+        ble_gap_addr_t privacy_addr;
+        ble_gap_irk_t  current_irk;
+        ble_opt_t      privacy_options;
+        ble_opt_t      current_privacy_options;
+
+        NRF_PM_DEBUG_CHECK(p_privacy_params != NULL);
+
+        privacy_addr.addr_type                        = p_privacy_params->private_addr_type;
+        privacy_options.gap_opt.privacy.p_irk         = p_privacy_params->p_device_irk;
+        privacy_options.gap_opt.privacy.interval_s    = p_privacy_params->private_addr_cycle_s;
+        current_privacy_options.gap_opt.privacy.p_irk = &current_irk;
+
+        // Can not fail.
+        (void) sd_ble_opt_get(BLE_GAP_OPT_PRIVACY, &current_privacy_options);
+        (void) sd_ble_opt_set(BLE_GAP_OPT_PRIVACY, &privacy_options);
+
+        if (p_privacy_params->privacy_mode == BLE_GAP_PRIVACY_MODE_OFF)
+        {
+            ret = address_set_v2(BLE_GAP_ADDR_CYCLE_MODE_NONE, &m_current_id_addr);
+        }
+        else
+        {
+            ret = address_set_v2(BLE_GAP_ADDR_CYCLE_MODE_AUTO, &privacy_addr);
+        }
+
+        if (ret != NRF_SUCCESS)
+        {
+            // Restore previous settings.
+            (void) sd_ble_opt_set(BLE_GAP_OPT_PRIVACY, &current_privacy_options);
+        }
+
+        // NRF_ERROR_BUSY,
+        // NRF_ERROR_INVALID_STATE,
+        // NRF_ERROR_INVALID_PARAM, if address type is not valid.
+        return ret;
+
+    #else
+
+        return sd_ble_gap_privacy_set(p_privacy_params);
+
+    #endif
+}
+
+
+ret_code_t im_privacy_get(pm_privacy_params_t * p_privacy_params)
+{
+    #if (NRF_SD_BLE_API_VERSION <= 2)
+
+        ble_gap_addr_t cur_addr;
+        ble_opt_t      cur_privacy_opt;
+
+        NRF_PM_DEBUG_CHECK(p_privacy_params               != NULL);
+        NRF_PM_DEBUG_CHECK(p_privacy_params->p_device_irk != NULL);
+
+        cur_privacy_opt.gap_opt.privacy.p_irk = p_privacy_params->p_device_irk;
+
+        // Can not fail.
+        (void) sd_ble_gap_address_get(&cur_addr);
+
+        if (   cur_addr.addr_type == BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE
+            || cur_addr.addr_type == BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE)
+        {
+            p_privacy_params->privacy_mode      = BLE_GAP_PRIVACY_MODE_DEVICE_PRIVACY;
+            p_privacy_params->private_addr_type = cur_addr.addr_type;
+        }
+        else
+        {
+            p_privacy_params->privacy_mode = BLE_GAP_PRIVACY_MODE_OFF;
+        }
+
+        // Can not fail.
+        (void) sd_ble_opt_get(BLE_GAP_OPT_PRIVACY, &cur_privacy_opt);
+
+        p_privacy_params->private_addr_cycle_s = cur_privacy_opt.gap_opt.privacy.interval_s;
+
+        return NRF_SUCCESS;
+
+    #else
+
+        return sd_ble_gap_privacy_get(p_privacy_params);
+
+    #endif
+}
+
+
+/* Create a whitelist for the user using the cached list of peers.
+ * This whitelist is meant to be provided by the application to the Advertising module.
+ */
+ret_code_t im_whitelist_get(ble_gap_addr_t * p_addrs,
+                            uint32_t       * p_addr_cnt,
+                            ble_gap_irk_t  * p_irks,
+                            uint32_t       * p_irk_cnt)
+{
+    // One of the two buffers has to be provided.
+    NRF_PM_DEBUG_CHECK((p_addrs    != NULL) || (p_irks    != NULL));
+    NRF_PM_DEBUG_CHECK((p_addr_cnt != NULL) || (p_irk_cnt != NULL));
+
+    if (((p_addr_cnt != NULL) && (m_wlisted_peer_cnt > *p_addr_cnt)) ||
+        ((p_irk_cnt  != NULL) && (m_wlisted_peer_cnt > *p_irk_cnt)))
+    {
+        // The size of the cached list of peers is larger than the provided buffers.
+        return NRF_ERROR_NO_MEM;
+    }
+
+    // NRF_SUCCESS or
+    // NRF_ERROR_NOT_FOUND,            if a peer or its data were not found.
+    // BLE_ERROR_GAP_INVALID_BLE_ADDR, if a peer address can not be used for whitelisting.
+    return peers_id_keys_get(m_wlisted_peers, m_wlisted_peer_cnt,
+                             p_addrs, p_addr_cnt,
+                             p_irks,  p_irk_cnt);
+}
+
+
+/* Copies the peers to whitelist into a local cache.
+ * The cached list will be used by im_whitelist_get() to retrieve the active whitelist.
+ * For SoftDevices 3x, also loads the peers' GAP addresses and whitelists them using
+ * sd_ble_gap_whitelist_set().
+ */
+ret_code_t im_whitelist_set(pm_peer_id_t const * p_peers,
+                            uint32_t             peer_cnt)
+{
+    // Clear the cache of whitelisted peers.
+    memset(m_wlisted_peers, 0x00, sizeof(m_wlisted_peers));
+
+    if ((p_peers == NULL) || (peer_cnt == 0))
+    {
+        // Clear the current whitelist.
+        m_wlisted_peer_cnt = 0;
+        #if (NRF_SD_BLE_API_VERSION >= 3)
+            // NRF_SUCCESS, or
+            // BLE_GAP_ERROR_WHITELIST_IN_USE
+            return sd_ble_gap_whitelist_set(NULL, 0);
+        #else
+            // The cached list of whitelisted peers is already cleared; nothing to do.
+            return NRF_SUCCESS;
+        #endif
+    }
+
+    // @todo emdi: should not ever cache more than BLE_GAP_WHITELIST_ADDR_MAX_COUNT...
+
+    // Copy the new whitelisted peers.
+    m_wlisted_peer_cnt = peer_cnt;
+    memcpy(m_wlisted_peers, p_peers, sizeof(pm_peer_id_t) * peer_cnt);
+
+    #if (NRF_SD_BLE_API_VERSION >= 3)
+
+        ret_code_t ret;
+        uint32_t   wlist_addr_cnt = 0;
+
+        ble_gap_addr_t const * addr_ptrs[BLE_GAP_WHITELIST_ADDR_MAX_COUNT];
+        ble_gap_addr_t         addrs[BLE_GAP_WHITELIST_ADDR_MAX_COUNT];
+
+        memset(addrs, 0x00, sizeof(addrs));
+
+        // Fetch GAP addresses for these peers, but don't fetch IRKs.
+        ret = peers_id_keys_get(p_peers, peer_cnt, addrs, &wlist_addr_cnt, NULL, NULL);
+
+        if (ret != NRF_SUCCESS)
+        {
+            // NRF_ERROR_NOT_FOUND,            if a peer or its data were not found.
+            // BLE_ERROR_GAP_INVALID_BLE_ADDR, if a peer address can not be used for whitelisting.
+            return ret;
+        }
+
+        for (uint32_t i = 0; i < BLE_GAP_WHITELIST_ADDR_MAX_COUNT; i++)
+        {
+            addr_ptrs[i] = &addrs[i];
+        }
+
+        // NRF_ERROR_DATA_SIZE,             if peer_cnt > BLE_GAP_WHITELIST_ADDR_MAX_COUNT.
+        // BLE_ERROR_GAP_WHITELIST_IN_USE,  if a whitelist is in use.
+        return sd_ble_gap_whitelist_set(addr_ptrs, peer_cnt);
+
+    #else
+
+        return NRF_SUCCESS;
+
+    #endif
+}
+
+
+/**@brief Function for calculating the ah() hash function described in Bluetooth core specification
+ *        4.2 section 3.H.2.2.2.
+ *
+ * @detail  BLE uses a hash function to calculate the first half of a resolvable address
+ *          from the second half of the address and an irk. This function will use the ECB
+ *          periferal to hash these data acording to the Bluetooth core specification.
+ *
+ * @note The ECB expect little endian input and output.
+ *       This function expect big endian and will reverse the data as necessary.
+ *
+ * @param[in]  p_k          The key used in the hash function.
+ *                          For address resolution this is should be the irk.
+ *                          The array must have a length of 16.
+ * @param[in]  p_r          The rand used in the hash function. For generating a new address
+ *                          this would be a random number. For resolving a resolvable address
+ *                          this would be the last half of the address being resolved.
+ *                          The array must have a length of 3.
+ * @param[out] p_local_hash The result of the hash operation. For address resolution this
+ *                          will match the first half of the address being resolved if and only
+ *                          if the irk used in the hash function is the same one used to generate
+ *                          the address.
+ *                          The array must have a length of 16.
+ */
+void ah(uint8_t const * p_k, uint8_t const * p_r, uint8_t * p_local_hash)
+{
+    nrf_ecb_hal_data_t ecb_hal_data;
+
+    for (uint32_t i = 0; i < SOC_ECB_KEY_LENGTH; i++)
+    {
+        ecb_hal_data.key[i] = p_k[SOC_ECB_KEY_LENGTH - 1 - i];
+    }
+
+    memset(ecb_hal_data.cleartext, 0, SOC_ECB_KEY_LENGTH - IM_ADDR_CLEARTEXT_LENGTH);
+
+    for (uint32_t i = 0; i < IM_ADDR_CLEARTEXT_LENGTH; i++)
+    {
+        ecb_hal_data.cleartext[SOC_ECB_KEY_LENGTH - 1 - i] = p_r[i];
+    }
+
+    // Can only return NRF_SUCCESS.
+    (void) sd_ecb_block_encrypt(&ecb_hal_data);
+
+    for (uint32_t i = 0; i < IM_ADDR_CIPHERTEXT_LENGTH; i++)
+    {
+        p_local_hash[i] = ecb_hal_data.ciphertext[SOC_ECB_KEY_LENGTH - 1 - i];
+    }
+}
+
+
+bool im_address_resolve(ble_gap_addr_t const * p_addr, ble_gap_irk_t const * p_irk)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    uint8_t hash[IM_ADDR_CIPHERTEXT_LENGTH];
+    uint8_t local_hash[IM_ADDR_CIPHERTEXT_LENGTH];
+    uint8_t prand[IM_ADDR_CLEARTEXT_LENGTH];
+
+    if (p_addr->addr_type != BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE)
+    {
+        return false;
+    }
+
+    memcpy(hash, p_addr->addr, IM_ADDR_CIPHERTEXT_LENGTH);
+    memcpy(prand, &p_addr->addr[IM_ADDR_CIPHERTEXT_LENGTH], IM_ADDR_CLEARTEXT_LENGTH);
+    ah(p_irk->irk, prand, local_hash);
+
+    return (memcmp(hash, local_hash, IM_ADDR_CIPHERTEXT_LENGTH) == 0);
+}
+#endif // NRF_MODULE_ENABLED(PEER_MANAGER)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/id_manager.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,370 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef PEER_ID_MANAGER_H__
+#define PEER_ID_MANAGER_H__
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "headers/ble.h"
+#include "ble_gap.h"
+#include "peer_manager_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup id_manager ID Manager
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. A module for keeping track of peer identities
+ *       (IRK and peer address).
+ */
+
+
+/**@brief Events that can come from the ID Manager module.
+ */
+typedef enum
+{
+    IM_EVT_DUPLICATE_ID,          /**< The ID Manager module has detected that two stored peers represent the same peer. */
+    IM_EVT_BONDED_PEER_CONNECTED, /**< A connected peer has been identified as one of the bonded peers. This can happen immediately on connection, or at a later time. */
+} im_evt_id_t;
+
+
+typedef struct
+{
+    im_evt_id_t evt_id;
+    uint16_t    conn_handle;
+    union
+    {
+        struct
+        {
+            pm_peer_id_t peer_id_1;
+            pm_peer_id_t peer_id_2;
+        } duplicate_id;
+    } params;
+} im_evt_t;
+
+
+/**@brief Event handler for events from the ID Manager module.
+ *
+ * @param[in]  p_event   The event that has happened.
+ */
+typedef void (*im_evt_handler_t)(im_evt_t const * p_event);
+
+
+/**@brief Function for initializing the Identity manager.
+ *
+ * @retval NRF_SUCCESS          If initialization was successful.
+ * @retval NRF_ERROR_INTERNAL   If an error occurred.
+ */
+ret_code_t im_init(void);
+
+
+/**@brief Function for dispatching SoftDevice events to the ID Manager module.
+ *
+ * @param[in]  p_ble_evt  The SoftDevice event.
+ */
+void im_ble_evt_handler(ble_evt_t * p_ble_evt);
+
+
+/**@brief Function for getting the corresponding peer ID from a connection handle.
+ *
+ * @param[in]  conn_handle  The connection handle.
+ *
+ * @return The corresponding peer ID, or @ref PM_PEER_ID_INVALID if none could be resolved.
+ */
+pm_peer_id_t im_peer_id_get_by_conn_handle(uint16_t conn_handle);
+
+
+/**@brief Function for getting the corresponding peer ID from a master ID (EDIV and rand).
+ *
+ * @param[in]  p_master_id  The master ID.
+ *
+ * @return The corresponding peer ID, or @ref PM_PEER_ID_INVALID if none could be resolved.
+ */
+pm_peer_id_t im_peer_id_get_by_master_id(ble_gap_master_id_t * p_master_id);
+
+
+/**@brief Function for getting the corresponding connection handle from a peer ID.
+ *
+ * @param[in] peer_id  The peer ID.
+ *
+ * @return The corresponding connection handle, or @ref BLE_CONN_HANDLE_INVALID if none could be
+ *         resolved.
+ */
+uint16_t im_conn_handle_get(pm_peer_id_t peer_id);
+
+
+/**@brief Function for comparing two master ids
+ * @note  Two invalid master IDs will not match.
+ *
+ * @param[in]  p_master_id1 First master id for comparison
+ * @param[in]  p_master_id2 Second master id for comparison
+ *
+ * @return     True if the input matches, false if it does not.
+ */
+bool im_master_ids_compare(ble_gap_master_id_t const * p_master_id1,
+                           ble_gap_master_id_t const * p_master_id2);
+
+
+/**@brief Function for getting the BLE address used by the peer when connecting.
+ *
+ * @param[in]  conn_handle  The connection handle.
+ * @param[out] p_ble_addr   The BLE address used by the peer when the connection specified by
+ *                          conn_handle was established.
+ *
+ * @retval NRF_SUCCESS                   The address was found and copied.
+ * @retval NRF_ERROR_INVALID_STATE       Module not initialized.
+ * @retval BLE_ERROR_CONN_HANDLE_INVALID conn_handle does not refer to an active connection.
+ * @retval NRF_ERROR_NULL                p_ble_addr was NULL.
+ */
+ret_code_t im_ble_addr_get(uint16_t conn_handle, ble_gap_addr_t * p_ble_addr);
+
+
+/**@brief Function for checking whether a master ID is valid or invalid
+ *
+ * @param[in]  p_master_id  The master ID.
+ *
+ * @retval true   The master id is valid.
+ * @retval true   The master id is invalid (i.e. all zeros).
+ */
+bool im_master_id_is_valid(ble_gap_master_id_t const * p_master_id);
+
+
+bool im_is_duplicate_bonding_data(pm_peer_data_bonding_t const * p_bonding_data1,
+                                  pm_peer_data_bonding_t const * p_bonding_data2);
+
+
+/**@brief Function for reporting that a new peer ID has been allocated for a specified connection.
+ *
+ * @param[in]  conn_handle  The connection.
+ * @param[in]  peer_id      The new peer ID.
+ */
+void im_new_peer_id(uint16_t conn_handle, pm_peer_id_t peer_id);
+
+
+/**@brief Function for deleting all of a peer's data from flash and disassociating it from any
+ *        connection handles it is associated with.
+ *
+ * @param[in]  peer_id  The peer to free.
+ *
+ * @return Any error code returned by @ref pdb_peer_free.
+ */
+ret_code_t im_peer_free(pm_peer_id_t peer_id);
+
+
+/**@brief Function to set the local Bluetooth identity address.
+ *
+ * @details The local Bluetooth identity address is the address that identifies this device to other
+ *          peers. The address type must be either @ref BLE_GAP_ADDR_TYPE_PUBLIC or @ref
+ *          BLE_GAP_ADDR_TYPE_RANDOM_STATIC. The identity address cannot be changed while roles are
+ *          running.
+ *
+ * @note This address will be distributed to the peer during bonding.
+ *       If the address changes, the address stored in the peer device will not be valid and the
+ *       ability to reconnect using the old address will be lost.
+ *
+ * @note By default the SoftDevice will set an address of type @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC
+ *       upon being enabled. The address is a random number populated during the IC manufacturing
+ *       process and remains unchanged for the lifetime of each IC.
+ *
+ * @param[in] p_addr Pointer to address structure.
+ *
+ * @retval NRF_SUCCESS                     Address successfully set.
+ * @retval BLE_ERROR_GAP_INVALID_BLE_ADDR  If the GAP address is invalid.
+ * @retval NRF_ERROR_BUSY                  Could not process at this time. Process SoftDevice events
+ *                                         and retry.
+ * @retval NRF_ERROR_INVALID_STATE         The identity address cannot be changed while advertising,
+ *                                         scanning, or while in a connection.
+ * @retval NRF_ERROR_INTERNAL              If an internal error occurred.
+ */
+ret_code_t im_id_addr_set(ble_gap_addr_t const * p_addr);
+
+
+/**@brief Function to get the local Bluetooth identity address.
+ *
+ * @note This will always return the identity address irrespective of the privacy settings,
+ *       i.e. the address type will always be either @ref BLE_GAP_ADDR_TYPE_PUBLIC or @ref
+ *       BLE_GAP_ADDR_TYPE_RANDOM_STATIC.
+ *
+ * @param[out] p_addr Pointer to address structure to be filled in.
+ *
+ * @retval NRF_SUCCESS  If the address was successfully retrieved.
+ */
+ret_code_t im_id_addr_get(ble_gap_addr_t * p_addr);
+
+
+/**@brief Function to set privacy settings.
+ *
+ * @details Privacy settings cannot be set while advertising, scanning, or while in a connection.
+ *
+ * @param[in] p_privacy_params Privacy settings.
+ *
+ * @retval NRF_SUCCESS              If privacy options were set successfully.
+ * @retval NRF_ERROR_NULL           If @p p_privacy_params is NULL.
+ * @retval NRF_ERROR_INVALID_PARAM  If the address type is not valid.
+ * @retval NRF_ERROR_BUSY           If the request could not be processed at this time.
+ *                                  Process SoftDevice events and retry.
+ * @retval NRF_ERROR_INVALID_STATE  Privacy settings cannot be changed while BLE roles using
+ *                                  privacy are enabled.
+ */
+ret_code_t im_privacy_set(pm_privacy_params_t const * p_privacy_params);
+
+
+/**@brief Function to retrieve the current privacy settings.
+ *
+ * @details The privacy settings returned include the current device irk as well.
+ *
+ * @param[in] p_privacy_params Privacy settings.
+ *
+ * @retval NRF_SUCCESS            Successfully retrieved privacy settings.
+ * @retval NRF_ERROR_NULL         @c p_privacy_params is NULL.
+ * @retval NRF_ERROR_INTERNAL     If an internal error occurred.
+ */
+ret_code_t im_privacy_get(pm_privacy_params_t * p_privacy_params);
+
+
+/**@brief Function for resolving a resolvable address with an identity resolution key (IRK).
+ *
+ * @details This function will use the ECB peripheral to resolve a resolvable address.
+ *          This can be used to resolve the identity of a device distributing a random
+ *          resolvable address based on any IRKs you have received earlier. If an address is
+ *          resolved by an IRK, the device disributing the address must also know the IRK.
+ *
+ * @param[in] p_addr  A random resolvable address.
+ * @param[in] p_irk   An identity resolution key (IRK).
+ *
+ * @retval true   The irk used matched the one used to create the address.
+ * @retval false  The irk used did not match the one used to create the address, or an argument was
+ *                NULL.
+ */
+bool im_address_resolve(ble_gap_addr_t const * p_addr, ble_gap_irk_t const * p_irk);
+
+/**@brief Function for calculating the ah() hash function described in Bluetooth core specification
+ *        4.2 section 3.H.2.2.2.
+ *
+ * @detail  BLE uses a hash function to calculate the first half of a resolvable address
+ *          from the second half of the address and an IRK. This function uses the ECB
+ *          peripheral to hash this data according to the Bluetooth core specification.
+ *
+ * @note The ECB expects little endian input and output.
+ *       This function expects big endian and will reverse the data as necessary.
+ *
+ * @param[in]  p_k          The key used in the hash function.
+ *                          For address resolution this must be the IRK.
+ *                          The array must have a length of 16.
+ * @param[in]  p_r          The rand used in the hash function. For generating a new address
+ *                          this would be a random number. For resolving a resolvable address
+ *                          this would be the last half of the address being resolved.
+ *                          The array must have a length of 3.
+ * @param[out] p_local_hash The result of the hash operation. For address resolution this
+ *                          will match the first half of the address being resolved if and only
+ *                          if the irk used in the hash function is the same one that was used to generate
+ *                          the address.
+ *                          The array must have a length of 16.
+ *
+ * @note    ====IMPORTANT====
+ *          This is a special modification to the original nRF5 SDK. It is required by the mbed BLE API
+ *          to generate BLE private resolvable addresses. This function is used by
+ *          the BLE API implementation for nRF5xSecurityManager::getAddressFromBondTable() in the target's
+ *          BLE implementation.
+ *          =================
+ */
+void ah(uint8_t const * p_k, uint8_t const * p_r, uint8_t * p_local_hash);  
+
+/**@brief Function for setting / clearing the whitelist.
+ *
+ * @param p_peers   The peers to whitelist. Pass NULL to clear the whitelist.
+ * @param peer_cnt  The number of peers to whitelist. Pass zero to clear the whitelist.
+ *
+ * @retval NRF_SUCCESS                      If the whitelist was successfully set or cleared.
+ * @retval BLE_GAP_ERROR_WHITELIST_IN_USE   If a whitelist is in use.
+ * @retval BLE_ERROR_GAP_INVALID_BLE_ADDR   If any peer has an address which can not be used
+ *                                          for whitelisting.
+ * @retval NRF_ERROR_NOT_FOUND              If any peer or its data could not be found.
+ * @retval NRF_ERROR_DATA_SIZE              If @p peer_cnt is greater than
+ *                                          @ref BLE_GAP_WHITELIST_ADDR_MAX_COUNT.
+ */
+ret_code_t im_whitelist_set(pm_peer_id_t const * p_peers,
+                            uint32_t     const   peer_cnt);
+
+
+/**@brief Retrieves the current whitelist, set by a previous call to @ref im_whitelist_set.
+ *
+ * @param[out]   A buffer where to copy the GAP addresses.
+ * @param[inout] In: the size of the @p p_addrs buffer.
+ *               Out: the number of address copied into the buffer.
+ * @param[out]   A buffer where to copy the IRKs.
+ * @param[inout] In: the size of the @p p_irks buffer.
+ *               Out: the number of IRKs copied into the buffer.
+ *
+ * @retval NRF_SUCCESS                      If the whitelist was successfully retreived.
+ * @retval BLE_ERROR_GAP_INVALID_BLE_ADDR   If any peer has an address which can not be used for
+ *                                          whitelisting.
+ * @retval NRF_ERROR_NOT_FOUND              If the data for any of the cached whitelisted peers
+ *                                          can not be found anymore. It might have been deleted in
+ *                                          the meanwhile.
+ * @retval NRF_ERROR_NO_MEM                 If the provided buffers are too small.
+ */
+ret_code_t im_whitelist_get(ble_gap_addr_t * p_addrs,
+                            uint32_t       * p_addr_cnt,
+                            ble_gap_irk_t  * p_irks,
+                            uint32_t       * p_irk_cnt);
+
+
+/**@brief Set the device identities list.
+ */
+ret_code_t im_device_identities_list_set(pm_peer_id_t const * p_peers,
+                                         uint32_t             peer_cnt);
+
+
+/** @}
+ * @endcond
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PEER_ID_MANAGER_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_data.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,90 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(PEER_MANAGER)
+#include "peer_data.h"
+
+#include "peer_manager_types.h"
+#include "fds.h"
+
+
+void peer_data_parts_get(pm_peer_data_const_t const * p_peer_data, fds_record_chunk_t * p_chunks, uint16_t * p_n_chunks)
+{
+    if (p_n_chunks == NULL)
+    {
+    }
+    else if ((p_peer_data == NULL) || (p_chunks == NULL))
+    {
+        *p_n_chunks = 0;
+    }
+    else
+    {
+        p_chunks[0].p_data       = p_peer_data->p_all_data;
+        p_chunks[0].length_words = p_peer_data->length_words;
+        *p_n_chunks = 1;
+    }
+}
+
+
+ret_code_t peer_data_deserialize(pm_peer_data_flash_t const * p_in_data, pm_peer_data_t * p_out_data)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+
+    if ((p_in_data == NULL) || (p_out_data == NULL))
+    {
+        err_code = NRF_ERROR_NULL;
+    }
+    else
+    {
+        if (p_out_data->length_words < p_in_data->length_words)
+        {
+            p_out_data->length_words = p_in_data->length_words;
+            err_code = NRF_ERROR_NO_MEM;
+        }
+        else
+        {
+            p_out_data->length_words = p_in_data->length_words;
+            p_out_data->data_id      = p_in_data->data_id;
+
+            memcpy(p_out_data->p_all_data, p_in_data->p_all_data, p_in_data->length_words * 4);
+        }
+    }
+    return err_code;
+}
+#endif // NRF_MODULE_ENABLED(PEER_MANAGER)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_data.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,92 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef PEER_DATA_H__
+#define PEER_DATA_H__
+
+#include <stdint.h>
+#include "peer_manager_types.h"
+#include "peer_manager_internal.h"
+#include "fds.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup peer_data Peer Data
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. This module defines the structure of the data
+ *        that is managed by the @ref peer_manager. It also provides functions for parsing the data.
+ */
+
+
+/**@brief Function for enumerating the separate (non-contiguous) parts of the peer data.
+ *
+ * @param[in]  p_peer_data  The peer data to enumerate.
+ * @param[out] p_chunks      The resulting chunks. This must be an array of at least 2 elements.
+ * @param[out] p_n_chunks    The number of chunks. If this is 0, something went wrong.
+ */
+void peer_data_parts_get(pm_peer_data_const_t const * p_peer_data, fds_record_chunk_t * p_chunks, uint16_t * p_n_chunks);
+
+
+/**@brief Function for converting @ref pm_peer_data_flash_t into @ref pm_peer_data_t.
+ *
+ * @param[in]  p_in_data   The source data.
+ * @param[out] p_out_data  The target data structure.
+ *
+ * @retval NRF_SUCCESS       Successful conversion.
+ * @retval NRF_ERROR_NULL    A parameter was NULL.
+ * @retval NRF_ERROR_NO_MEM  A buffer was not large enough.
+ */
+ret_code_t peer_data_deserialize(pm_peer_data_flash_t const * p_in_data, pm_peer_data_t * p_out_data);
+
+/** @}
+ * @endcond
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PEER_DATA_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_data_storage.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,691 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(PEER_MANAGER)
+#include "peer_data_storage.h"
+
+#include <stdint.h>
+#include <string.h>
+#include "sdk_errors.h"
+#include "peer_manager_types.h"
+#include "peer_manager_internal.h"
+#include "peer_id.h"
+#include "peer_data.h"
+#include "fds.h"
+
+
+// Macro for verifying that the peer id is within a valid range.
+#define VERIFY_PEER_ID_IN_RANGE(id)         VERIFY_FALSE((id >= PM_PEER_ID_N_AVAILABLE_IDS), \
+                                            NRF_ERROR_INVALID_PARAM)
+
+// Macro for verifying that the peer data id is withing a valid range.
+#define VERIFY_PEER_DATA_ID_IN_RANGE(id)    VERIFY_TRUE(peer_data_id_is_valid(id), \
+                                            NRF_ERROR_INVALID_PARAM)
+
+// The number of registered event handlers.
+#define PDS_EVENT_HANDLERS_CNT              (sizeof(m_evt_handlers) / sizeof(m_evt_handlers[0]))
+
+
+// Peer Data Storage event handler in Peer Database.
+extern void pdb_pds_evt_handler(pds_evt_t const *);
+
+// Peer Data Storage events' handlers.
+// The number of elements in this array is PDS_EVENT_HANDLERS_CNT.
+static pds_evt_handler_t const m_evt_handlers[] =
+{
+    pdb_pds_evt_handler,
+};
+
+static bool m_module_initialized  = false;
+static bool m_peer_delete_queued  = false;
+static bool m_peer_delete_ongoing = false;
+
+// A token used for Flash Data Storage searches.
+static fds_find_token_t m_fds_ftok;
+
+
+// Function for dispatching events to all registered event handlers.
+static void pds_evt_send(pds_evt_t * p_event)
+{
+    for (uint32_t i = 0; i < PDS_EVENT_HANDLERS_CNT; i++)
+    {
+        m_evt_handlers[i](p_event);
+    }
+}
+
+
+// Function to convert peer IDs to file IDs.
+static uint16_t peer_id_to_file_id(pm_peer_id_t peer_id)
+{
+    return (uint16_t)(peer_id + PEER_ID_TO_FILE_ID);
+}
+
+
+// Function to convert peer data id to type id.
+static pm_peer_id_t file_id_to_peer_id(uint16_t file_id)
+{
+    return (pm_peer_id_t)(file_id + FILE_ID_TO_PEER_ID);
+}
+
+
+// Function to convert peer data IDs to record keys.
+static uint16_t peer_data_id_to_record_key(pm_peer_data_id_t peer_data_id)
+{
+    return (uint16_t)(peer_data_id + DATA_ID_TO_RECORD_KEY);
+}
+
+
+// Function to convert record keys to peer data IDs.
+static pm_peer_data_id_t record_key_to_peer_data_id(uint16_t record_key)
+{
+    return (pm_peer_data_id_t)(record_key + RECORD_KEY_TO_DATA_ID);
+}
+
+
+// Function for checking whether a file ID is relevant for the Peer Manager.
+static bool file_id_within_pm_range(uint16_t file_id)
+{
+    return ((PDS_FIRST_RESERVED_FILE_ID <= file_id)
+         && (file_id <= PDS_LAST_RESERVED_FILE_ID));
+}
+
+
+// Function for checking whether a record key is relevant for the Peer Manager.
+static bool record_key_within_pm_range(uint16_t record_key)
+{
+    return ((PDS_FIRST_RESERVED_RECORD_KEY <= record_key)
+         && (record_key <= PDS_LAST_RESERVED_RECORD_KEY));
+}
+
+
+static bool peer_data_id_is_valid(pm_peer_data_id_t data_id)
+{
+    return ((data_id == PM_PEER_DATA_ID_BONDING)                 ||
+            (data_id == PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING) ||
+            (data_id == PM_PEER_DATA_ID_GATT_LOCAL)              ||
+            (data_id == PM_PEER_DATA_ID_GATT_REMOTE)             ||
+            (data_id == PM_PEER_DATA_ID_PEER_RANK)               ||
+            (data_id == PM_PEER_DATA_ID_APPLICATION));
+}
+
+
+// Function for deleting all data beloning to a peer.
+// These operations will be sent to FDS one at a time.
+static void peer_data_delete()
+{
+    ret_code_t        ret;
+    pm_peer_id_t      peer_id;
+    uint16_t          file_id;
+    fds_record_desc_t desc;
+    fds_find_token_t  ftok;
+
+    memset(&ftok, 0x00, sizeof(fds_find_token_t));
+    peer_id = peer_id_get_next_deleted(PM_PEER_ID_INVALID);
+
+    while (    (peer_id != PM_PEER_ID_INVALID)
+            && (fds_record_find_in_file(peer_id_to_file_id(peer_id), &desc, &ftok)
+            == FDS_ERR_NOT_FOUND))
+    {
+        peer_id_free(peer_id);
+        peer_id = peer_id_get_next_deleted(peer_id);
+    }
+
+    if (!m_peer_delete_ongoing && (peer_id != PM_PEER_ID_INVALID))
+    {
+        m_peer_delete_ongoing = true;
+
+        file_id = peer_id_to_file_id(peer_id);
+        ret     = fds_file_delete(file_id);
+
+        if (ret == FDS_ERR_NO_SPACE_IN_QUEUES)
+        {
+            m_peer_delete_queued = true;
+        }
+        else if (ret != NRF_SUCCESS)
+        {
+            m_peer_delete_ongoing = false;
+
+            pds_evt_t pds_evt;
+
+            pds_evt.evt_id      = PDS_EVT_ERROR_UNEXPECTED;
+            pds_evt.peer_id     = peer_id;
+            pds_evt.data_id     = PM_PEER_DATA_ID_INVALID;
+            pds_evt.store_token = PM_STORE_TOKEN_INVALID;
+            pds_evt.result      = ret;
+
+            pds_evt_send(&pds_evt);
+        }
+    }
+}
+
+
+static ret_code_t peer_data_find(pm_peer_id_t              peer_id,
+                                 pm_peer_data_id_t         data_id,
+                                 fds_record_desc_t * const p_desc)
+{
+    ret_code_t       ret;
+    fds_find_token_t ftok;
+
+    NRF_PM_DEBUG_CHECK(peer_id < PM_PEER_ID_N_AVAILABLE_IDS);
+    NRF_PM_DEBUG_CHECK(peer_data_id_is_valid(data_id));
+    NRF_PM_DEBUG_CHECK(p_desc != NULL);
+
+    memset(&ftok, 0x00, sizeof(fds_find_token_t));
+
+    uint16_t file_id    = peer_id_to_file_id(peer_id);
+    uint16_t record_key = peer_data_id_to_record_key(data_id);
+
+    ret = fds_record_find(file_id, record_key, p_desc, &ftok);
+
+    if (ret != FDS_SUCCESS)
+    {
+        return NRF_ERROR_NOT_FOUND;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+static void peer_ids_load()
+{
+    fds_record_desc_t  record_desc;
+    fds_flash_record_t record;
+    fds_find_token_t   ftok;
+
+    memset(&ftok, 0x00, sizeof(fds_find_token_t));
+
+    uint16_t const record_key = peer_data_id_to_record_key(PM_PEER_DATA_ID_BONDING);
+
+    while (fds_record_find_by_key(record_key, &record_desc, &ftok) == FDS_SUCCESS)
+    {
+        pm_peer_id_t peer_id;
+
+        // It is safe to ignore the return value since the descriptor was
+        // just obtained and also 'record' is different from NULL.
+        (void)fds_record_open(&record_desc, &record);
+        peer_id = file_id_to_peer_id(record.p_header->ic.file_id);
+        (void)fds_record_close(&record_desc);
+
+        (void)peer_id_allocate(peer_id);
+    }
+}
+
+
+static void fds_evt_handler(fds_evt_t const * const p_fds_evt)
+{
+    pds_evt_t pds_evt;
+
+    pds_evt.result = (p_fds_evt->result == FDS_SUCCESS);
+
+    switch (p_fds_evt->id)
+    {
+        case FDS_EVT_WRITE:
+        case FDS_EVT_UPDATE:
+            if (   file_id_within_pm_range(p_fds_evt->write.file_id)
+                || record_key_within_pm_range(p_fds_evt->write.record_key))
+            {
+                pds_evt.peer_id = file_id_to_peer_id(p_fds_evt->write.file_id);
+                pds_evt.data_id = record_key_to_peer_data_id(p_fds_evt->write.record_key);
+
+                if (p_fds_evt->id == FDS_EVT_WRITE)
+                {
+                    pds_evt.evt_id = (p_fds_evt->result == FDS_SUCCESS) ? PDS_EVT_STORED :
+                                                                          PDS_EVT_ERROR_STORE;
+                }
+                else
+                {
+                    pds_evt.evt_id = (p_fds_evt->result == FDS_SUCCESS) ? PDS_EVT_UPDATED :
+                                                                          PDS_EVT_ERROR_UPDATE;
+                }
+
+                pds_evt.result      = p_fds_evt->result;
+                pds_evt.store_token = p_fds_evt->write.record_id;
+
+                pds_evt_send(&pds_evt);
+            }
+            break;
+
+        case FDS_EVT_DEL_RECORD:
+            if (   file_id_within_pm_range(p_fds_evt->del.file_id)
+                || record_key_within_pm_range(p_fds_evt->del.record_key))
+            {
+                pds_evt.peer_id = file_id_to_peer_id(p_fds_evt->del.file_id);
+                pds_evt.data_id = record_key_to_peer_data_id(p_fds_evt->del.record_key);
+
+                pds_evt.evt_id = (p_fds_evt->result == FDS_SUCCESS) ? PDS_EVT_CLEARED :
+                                                                      PDS_EVT_ERROR_CLEAR;
+
+                pds_evt.store_token = p_fds_evt->del.record_id;
+
+                pds_evt_send(&pds_evt);
+            }
+            break;
+
+        case FDS_EVT_DEL_FILE:
+            {
+                if (    file_id_within_pm_range(p_fds_evt->del.file_id)
+                    && (p_fds_evt->del.record_key == FDS_RECORD_KEY_DIRTY))
+                {
+                    pds_evt.peer_id = file_id_to_peer_id(p_fds_evt->del.file_id);
+                    pds_evt.data_id = record_key_to_peer_data_id(p_fds_evt->del.record_key);
+
+                    pds_evt.data_id = PM_PEER_DATA_ID_INVALID;
+                    if (p_fds_evt->result == FDS_SUCCESS)
+                    {
+                        pds_evt.evt_id = PDS_EVT_PEER_ID_CLEAR;
+                        peer_id_free(pds_evt.peer_id);
+                    }
+                    else
+                    {
+                        pds_evt.evt_id = PDS_EVT_ERROR_PEER_ID_CLEAR;
+                    }
+
+                    m_peer_delete_queued  = false;
+                    m_peer_delete_ongoing = false;
+
+                    peer_data_delete();
+
+                    pds_evt_send(&pds_evt);
+                }
+            }
+            break;
+
+        case FDS_EVT_GC:
+            pds_evt.evt_id = PDS_EVT_COMPRESSED;
+            pds_evt_send(&pds_evt);
+            break;
+
+        default:
+            break;
+    }
+
+    if (m_peer_delete_queued)
+    {
+        m_peer_delete_queued  = false;
+        peer_data_delete();
+    }
+}
+
+
+ret_code_t pds_init()
+{
+    ret_code_t ret;
+
+    // Check for re-initialization if debugging.
+    NRF_PM_DEBUG_CHECK(!m_module_initialized);
+
+    ret = fds_register(fds_evt_handler);
+    if (ret != NRF_SUCCESS)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    ret = fds_init();
+    if (ret != NRF_SUCCESS)
+    {
+        return NRF_ERROR_STORAGE_FULL;
+    }
+
+    peer_id_init();
+    peer_ids_load();
+
+    m_module_initialized = true;
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pds_peer_data_read(pm_peer_id_t                    peer_id,
+                              pm_peer_data_id_t               data_id,
+                              pm_peer_data_t          * const p_data,
+                              uint32_t          const * const p_buf_len)
+{
+    ret_code_t         ret;
+    fds_record_desc_t  rec_desc;
+    fds_flash_record_t rec_flash;
+
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    NRF_PM_DEBUG_CHECK(p_data != NULL);
+
+    VERIFY_PEER_ID_IN_RANGE(peer_id);
+    VERIFY_PEER_DATA_ID_IN_RANGE(data_id);
+
+    ret = peer_data_find(peer_id, data_id, &rec_desc);
+
+    if (ret != NRF_SUCCESS)
+    {
+        return NRF_ERROR_NOT_FOUND;
+    }
+
+    // Shouldn't fail, unless the record was deleted in the meanwhile or the CRC check has failed.
+    ret = fds_record_open(&rec_desc, &rec_flash);
+
+    if (ret != NRF_SUCCESS)
+    {
+        return NRF_ERROR_NOT_FOUND;
+    }
+
+    // @note emdi: could this actually be set by the caller and used instead
+    // of an additional parameter (data_id) ?
+    p_data->data_id      = data_id;
+    p_data->length_words = rec_flash.p_header->tl.length_words;
+
+    // If p_buf_len is NULL, provide a pointer to data in flash, otherwise,
+    // check that the buffer is large enough and copy the data in flash into the buffer.
+    if (p_buf_len != NULL)
+    {
+        uint32_t const data_len_bytes = (p_data->length_words * sizeof(uint32_t));
+
+        if ((*p_buf_len) <= data_len_bytes)
+        {
+            memcpy(p_data->p_all_data, rec_flash.p_data, data_len_bytes);
+        }
+        else
+        {
+            return NRF_ERROR_NO_MEM;
+        }
+    }
+    else
+    {
+        // The cast is necessary because if no buffer is provided, we just copy the pointer,
+        // but it that case it should be considered a pointer to const data by the caller,
+        // since it is a pointer to data in flash.
+        p_data->p_all_data = (void*)rec_flash.p_data;
+    }
+
+    // Shouldn't fail unless the record was already closed, in which case it can be ignored.
+    (void)fds_record_close(&rec_desc);
+
+    return NRF_SUCCESS;
+}
+
+
+void pds_peer_data_iterate_prepare(void)
+{
+    memset(&m_fds_ftok, 0x00, sizeof(fds_find_token_t));
+}
+
+
+bool pds_peer_data_iterate(pm_peer_data_id_t            data_id,
+                           pm_peer_id_t         * const p_peer_id,
+                           pm_peer_data_flash_t * const p_data)
+{
+    ret_code_t         ret;
+    uint16_t           rec_key;
+    fds_record_desc_t  rec_desc;
+    fds_flash_record_t rec_flash;
+
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    NRF_PM_DEBUG_CHECK(p_peer_id != NULL);
+    NRF_PM_DEBUG_CHECK(p_data    != NULL);
+
+    // @note emdi: should we check the data_id ?
+    rec_key = peer_data_id_to_record_key(data_id);
+
+    if (fds_record_find_by_key(rec_key, &rec_desc, &m_fds_ftok) != NRF_SUCCESS)
+    {
+        return false;
+    }
+
+    ret = fds_record_open(&rec_desc, &rec_flash);
+
+    if (ret != NRF_SUCCESS)
+    {
+        // It can only happen if the record was deleted after the call to fds_record_find_by_key(),
+        // before we could open it, or if CRC support was enabled in Flash Data Storage at compile
+        // time and the CRC check failed.
+        return false;
+    }
+
+    p_data->data_id      = data_id;
+    p_data->length_words = rec_flash.p_header->tl.length_words;
+    p_data->p_all_data   = rec_flash.p_data;
+
+    *p_peer_id           = file_id_to_peer_id(rec_flash.p_header->ic.file_id);
+
+    (void)fds_record_close(&rec_desc);
+
+    return true;
+}
+
+
+ret_code_t pds_space_reserve(pm_peer_data_const_t const * p_peer_data,
+                             pm_prepare_token_t         * p_prepare_token)
+{
+    ret_code_t ret;
+
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    NRF_PM_DEBUG_CHECK(p_peer_data     != NULL);
+    NRF_PM_DEBUG_CHECK(p_prepare_token != NULL);
+
+    VERIFY_PEER_DATA_ID_IN_RANGE(p_peer_data->data_id);
+
+    ret = fds_reserve((fds_reserve_token_t*)p_prepare_token, p_peer_data->length_words);
+
+    switch (ret)
+    {
+        case FDS_SUCCESS:
+            return NRF_SUCCESS;
+
+        case FDS_ERR_RECORD_TOO_LARGE:
+            return NRF_ERROR_INVALID_LENGTH;
+
+        case FDS_ERR_NO_SPACE_IN_FLASH:
+            return NRF_ERROR_STORAGE_FULL;
+
+        default:
+            return NRF_ERROR_INTERNAL;
+    }
+}
+
+
+ret_code_t pds_space_reserve_cancel(pm_prepare_token_t prepare_token)
+{
+    ret_code_t ret;
+
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    NRF_PM_DEBUG_CHECK(prepare_token != PDS_PREPARE_TOKEN_INVALID);
+
+    ret = fds_reserve_cancel((fds_reserve_token_t*)&prepare_token);
+
+    if (ret != FDS_SUCCESS)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pds_peer_data_store(pm_peer_id_t                 peer_id,
+                               pm_peer_data_const_t const * p_peer_data,
+                               pm_prepare_token_t           prepare_token,
+                               pm_store_token_t           * p_store_token)
+{
+    ret_code_t         ret;
+    fds_record_t       rec;
+    fds_record_desc_t  rec_desc;
+    fds_record_chunk_t rec_chunk;
+
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    NRF_PM_DEBUG_CHECK(p_peer_data != NULL);
+
+    VERIFY_PEER_ID_IN_RANGE(peer_id);
+    VERIFY_PEER_DATA_ID_IN_RANGE(p_peer_data->data_id);
+
+    // Prepare chunk.
+    rec_chunk.p_data       = p_peer_data->p_all_data;
+    rec_chunk.length_words = p_peer_data->length_words;
+
+    // Prepare the record to be stored in flash.
+    rec.file_id         = peer_id_to_file_id(peer_id);
+    rec.key             = peer_data_id_to_record_key(p_peer_data->data_id);
+    rec.data.p_chunks   = &rec_chunk;
+    rec.data.num_chunks = 1;
+
+    ret = peer_data_find(peer_id, p_peer_data->data_id, &rec_desc);
+
+    if (ret == NRF_ERROR_NOT_FOUND)
+    {
+        // No previous data exists in flash.
+        if (prepare_token == PDS_PREPARE_TOKEN_INVALID)
+        {
+            // No space was previously reserved.
+            ret = fds_record_write(&rec_desc, &rec);
+        }
+        else
+        {
+            // Space for this record was previously reserved.
+            ret = fds_record_write_reserved(&rec_desc, &rec, (fds_reserve_token_t*)&prepare_token);
+        }
+    }
+    else // NRF_SUCCESS
+    {
+        // Token shouldn't be zero at this point.
+        // NRF_PM_DEBUG_CHECK(prepare_token != PDS_PREPARE_TOKEN_INVALID);
+
+        (void)fds_reserve_cancel((fds_reserve_token_t*)&prepare_token);
+
+        // Update existing record.
+        ret = fds_record_update(&rec_desc, &rec);
+    }
+
+    switch (ret)
+    {
+        case FDS_SUCCESS:
+            if (p_store_token != NULL)
+            {
+                // Update the store token.
+                (void)fds_record_id_from_desc(&rec_desc, (uint32_t*)p_store_token);
+            }
+            return NRF_SUCCESS;
+
+        case FDS_ERR_BUSY:
+        case FDS_ERR_NO_SPACE_IN_QUEUES:
+            return NRF_ERROR_BUSY;
+
+        case FDS_ERR_NO_SPACE_IN_FLASH:
+            return NRF_ERROR_STORAGE_FULL;
+
+        default:
+            return NRF_ERROR_INTERNAL;
+    }
+}
+
+
+// @note emdi: unused..
+ret_code_t pds_peer_data_delete(pm_peer_id_t peer_id, pm_peer_data_id_t data_id)
+{
+    ret_code_t        ret;
+    fds_record_desc_t record_desc;
+
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    VERIFY_PEER_ID_IN_RANGE(peer_id);
+    VERIFY_PEER_DATA_ID_IN_RANGE(data_id);
+
+    ret = peer_data_find(peer_id, data_id, &record_desc);
+
+    if (ret != NRF_SUCCESS)
+    {
+        return NRF_ERROR_NOT_FOUND;
+    }
+
+    ret = fds_record_delete(&record_desc);
+
+    switch (ret)
+    {
+        case FDS_SUCCESS:
+            return NRF_SUCCESS;
+
+        case FDS_ERR_NO_SPACE_IN_QUEUES:
+            return NRF_ERROR_BUSY;
+
+        default:
+            return NRF_ERROR_INTERNAL;
+    }
+}
+
+
+pm_peer_id_t pds_peer_id_allocate(void)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    return peer_id_allocate(PM_PEER_ID_INVALID);
+}
+
+
+ret_code_t pds_peer_id_free(pm_peer_id_t peer_id)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    VERIFY_PEER_ID_IN_RANGE(peer_id);
+
+    (void)peer_id_delete(peer_id);
+    peer_data_delete();
+
+    return NRF_SUCCESS;
+}
+
+
+bool pds_peer_id_is_allocated(pm_peer_id_t peer_id)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    return peer_id_is_allocated(peer_id);
+}
+
+
+pm_peer_id_t pds_next_peer_id_get(pm_peer_id_t prev_peer_id)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    return peer_id_get_next_used(prev_peer_id);
+}
+
+
+pm_peer_id_t pds_next_deleted_peer_id_get(pm_peer_id_t prev_peer_id)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    return peer_id_get_next_deleted(prev_peer_id);
+}
+
+
+uint32_t pds_peer_count_get(void)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    return peer_id_n_ids();
+}
+#endif // NRF_MODULE_ENABLED(PEER_MANAGER)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_data_storage.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,306 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef PEER_DATA_STORAGE_H__
+#define PEER_DATA_STORAGE_H__
+
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "ble_gap.h"
+#include "peer_manager_types.h"
+#include "peer_manager_internal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup peer_data_storage Peer Data Storage
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. This module provides a Peer Manager-specific API
+ *        to the persistent storage.
+ *
+ * @details This module uses Flash Data Storage (FDS) to interface with persistent storage.
+ */
+
+#define PDS_PREPARE_TOKEN_INVALID     (0)       /**< Invalid value for prepare token. */
+#define PDS_FIRST_RESERVED_FILE_ID    (0xC000)  /**< The beginning of the range of file IDs reserved for Peer Manager. */
+#define PDS_LAST_RESERVED_FILE_ID     (0xFFFE)  /**< The end of the range of file IDs reserved for Peer Manager. */
+#define PDS_FIRST_RESERVED_RECORD_KEY (0xC000)  /**< The beginning of the range of record keys reserved for Peer Manager. */
+#define PDS_LAST_RESERVED_RECORD_KEY  (0xFFFE)  /**< The end of the range of record keys reserved for Peer Manager. */
+
+#define PEER_ID_TO_FILE_ID            ( PDS_FIRST_RESERVED_FILE_ID)    //!< Macro for converting a @ref pm_peer_id_t to an FDS file ID.
+#define FILE_ID_TO_PEER_ID            (-PDS_FIRST_RESERVED_FILE_ID)    //!< Macro for converting an FDS file ID to a @ref pm_peer_id_t.
+#define DATA_ID_TO_RECORD_KEY         ( PDS_FIRST_RESERVED_RECORD_KEY) //!< Macro for converting a @ref pm_peer_data_id_t to an FDS record ID.
+#define RECORD_KEY_TO_DATA_ID         (-PDS_FIRST_RESERVED_RECORD_KEY) //!< Macro for converting an FDS record ID to a @ref pm_peer_data_id_t.
+
+
+/**@brief The events that come from this module.
+ */
+typedef enum
+{
+    PDS_EVT_STORED,                 //!< The specified data has been successfully stored.
+    PDS_EVT_UPDATED,                //!< The specified data has been successfully updated.
+    PDS_EVT_CLEARED,                //!< The specified data has been successfully cleared.
+    PDS_EVT_ERROR_STORE,            //!< The specified data could not be stored.
+    PDS_EVT_ERROR_UPDATE,           //!< The specified data could not be updated.
+    PDS_EVT_ERROR_CLEAR,            //!< The specified data could not be cleared.
+    PDS_EVT_PEER_ID_CLEAR,          //!< The peer id has been successfully cleared.
+    PDS_EVT_ERROR_PEER_ID_CLEAR,    //!< The peer id has been successfully cleared.
+    PDS_EVT_COMPRESSED,             //!< A compress procedure has finished successfully.
+    PDS_EVT_ERROR_UNEXPECTED,       //!< An unexpected, possibly fatal error occurred.
+} pds_evt_id_t;
+
+
+/**@brief The event structure for events generated by the this module.
+ */
+typedef struct
+{
+    pds_evt_id_t      evt_id;      /**< The type of event. */
+    pm_peer_id_t      peer_id;     /**< The peer the event pertains to. */
+    pm_peer_data_id_t data_id;     /**< The data the event pertains to. */
+    pm_store_token_t  store_token; /**< A unique identifier for the operation. Can be compare to the token received when starting the operation. */
+    ret_code_t        result;      /**< The result of the operation, or the unexpected error. */
+} pds_evt_t;
+
+
+/**@brief Event handler for events from the peer_data_storage module.
+ *
+ * @param[in]  event    The event that has happened.
+ * @param[in]  peer_id  The id of the peer the event pertains to.
+ * @param[in]  flags    The data the event pertains to.
+ */
+typedef void (*pds_evt_handler_t)(pds_evt_t const * p_event);
+
+
+/**@brief Function for initializing the module.
+ *
+ * @retval NRF_SUCCESS             If initialization was successful.
+ * @retval NRF_ERROR_STORAGE_FULL  If no flash pages were available for use.
+ * @retval NRF_ERROR_INTERNAL      If the module couldn't register with the flash filesystem.
+ */
+ret_code_t pds_init(void);
+
+
+/**@brief Function for reading peer data in flash.
+ *
+ * @param[in]  peer_id     The peer the data belongs to.
+ * @param[in]  data_id     The data to retrieve.
+ * @param[out] p_data      The peer data. May not be @c NULL.
+ * @param[in]  p_buf_len   Length of the provided buffer, in bytes. Pass @c NULL to only copy
+ *                         a pointer to the data in flash.
+ *
+ * @retval NRF_SUCCESS              If the operation was successful.
+ * @retval NRF_ERROR_INVALID_PARAM  If @p peer_id or @p data_id are invalid.
+ * @retval NRF_ERROR_NOT_FOUND      If the data was not found in flash.
+ * @retval NRF_ERROR_NO_MEM         If the provided buffer is too small.
+ */
+ret_code_t pds_peer_data_read(pm_peer_id_t                    peer_id,
+                              pm_peer_data_id_t               data_id,
+                              pm_peer_data_t          * const p_data,
+                              uint32_t          const * const p_buf_len);
+
+
+/**@brief Function to prepare iterating over peer data in flash using @ref pds_peer_data_iterate.
+ *        Call this function once each time before iterating using @ref pds_peer_data_iterate.
+ */
+void pds_peer_data_iterate_prepare(void);
+
+
+/**@brief Function for iterating peers' data in flash.
+ *        Always call @ref pds_peer_data_iterate_prepare before starting iterating.
+ *
+ * @param[in]  data_id    The peer data to iterate over.
+ * @param[out] p_peer_id  The peer the data belongs to.
+ * @param[out] p_data     The peer data in flash.
+ *
+ * @retval true   If the operation was successful.
+ * @retval false  If the data was not found in flash, or another error occurred.
+ */
+bool pds_peer_data_iterate(pm_peer_data_id_t            data_id,
+                           pm_peer_id_t         * const p_peer_id,
+                           pm_peer_data_flash_t * const p_data);
+
+
+/**@brief Function for reserving space in flash to store data.
+ *
+ * @param[in]  p_peer_data      The data to be stored in flash. Only data length and type (ID) are
+ *                              relevant for this operation. May not be @c NULL.
+ * @param[out] p_prepare_token  A token identifying the reserved space. May not be @c NULL.
+ *
+ * @retval NRF_SUCCESS               If the operation was successful.
+ * @retval NRF_ERROR_INVALID_PARAM   If the data ID in @p p_peer_data is invalid.
+ * @retval NRF_ERROR_INVALID_LENGTH  If data length exceeds the maximum allowed length.
+ * @retval NRF_ERROR_STORAGE_FULL    If no space is available in flash.
+ * @retval NRF_ERROR_INTERNAL        If an unexpected error occurred.
+ */
+ret_code_t pds_space_reserve(pm_peer_data_const_t const * p_peer_data,
+                             pm_prepare_token_t         * p_prepare_token);
+
+
+/**@brief Function for undoing a previous call to @ref pds_space_reserve.
+ *
+ * @param[in]  prepare_token  A token identifying the reservation to cancel.
+ *
+ * @retval NRF_SUCCESS          If the operation was successful.
+ * @retval NRF_ERROR_INTERNAL   If an unexpected error occurred.
+ */
+ret_code_t pds_space_reserve_cancel(pm_prepare_token_t prepare_token);
+
+
+/**@brief Function for storing peer data in flash. If the same piece of data already exists for the
+ *        given peer, it will be updated. This operation is asynchronous.
+ *        Expect a @ref PDS_EVT_STORED or @ref PDS_EVT_ERROR_STORE event.
+ *
+ * @param[in]  peer_id        The peer the data belongs to.
+ * @param[in]  p_peer_data    The peer data. May not be @c NULL.
+ * @param[in]  prepare_token  A token identifying the reservation made in flash to store the data.
+ *                            Pass @ref PDS_PREPARE_TOKEN_INVALID if no space was reserved.
+ * @param[out] p_store_token  A token identifying this particular store operation. The token can be
+ *                            used to identify events pertaining to this operation. Pass @p NULL
+ *                            if not used.
+ *
+ * @retval NRF_SUCCESS              If the operation was initiated successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  If @p peer_id or the data ID in @p_peer_data are invalid.
+ * @retval NRF_ERROR_STORAGE_FULL   If no space is available in flash. This can only happen if
+ *                                  @p p_prepare_token is @ref PDS_PREPARE_TOKEN_INVALID.
+ * @retval NRF_ERROR_BUSY           If the flash filesystem was busy.
+ * @retval NRF_ERROR_INTERNAL       If an unexpected error occurred.
+ */
+ret_code_t pds_peer_data_store(pm_peer_id_t                 peer_id,
+                               pm_peer_data_const_t const * p_peer_data,
+                               pm_prepare_token_t           prepare_token,
+                               pm_store_token_t           * p_store_token);
+
+
+/**@brief Function for deleting peer data in flash. This operation is asynchronous.
+ *        Expect a @ref PDS_EVT_CLEARED or @ref PDS_EVT_ERROR_CLEAR event.
+ *
+ * @param[in]  peer_id  The peer the data belongs to
+ * @param[in]  data_id  The data to delete.
+ *
+ * @retval NRF_SUCCESS              If the operation was initiated successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  If @p peer_id or @p data_id are invalid.
+ * @retval NRF_ERROR_NOT_FOUND      If data was not found in flash.
+ * @retval NRF_ERROR_BUSY           If the flash filesystem was busy.
+ * @retval NRF_ERROR_INTERNAL       If an unexpected error occurred.
+ */
+ret_code_t pds_peer_data_delete(pm_peer_id_t peer_id, pm_peer_data_id_t data_id);
+
+
+/**@brief Function for claiming an unused peer ID.
+ *
+ * @retval  PM_PEER_ID_INVALID  If no peer ID was available.
+ */
+pm_peer_id_t pds_peer_id_allocate(void);
+
+
+/**@brief Function for freeing a peer ID and deleting all data associated with it in flash.
+ *
+ * @param[in]  peer_id  The ID of the peer to free.
+ *
+ * @retval NRF_SUCCESS             The operation was initiated successfully.
+ * @retval NRF_ERROR_INVALID_PARAM If @p peer_id is invalid.
+ */
+ret_code_t pds_peer_id_free(pm_peer_id_t peer_id);
+
+
+/**@brief Function for finding out whether a peer ID is in use.
+ *
+ * @param[in]  peer_id  The peer ID to inquire about.
+ *
+ * @retval  true   @p peer_id is in use.
+ * @retval  false  @p peer_id is free.
+ */
+bool pds_peer_id_is_allocated(pm_peer_id_t peer_id);
+
+
+/**@brief Function for getting the next peer ID in the sequence of all used peer IDs. Can be
+ *        used to loop through all used peer IDs.
+ *
+ * @note @ref PM_PEER_ID_INVALID is considered to be before the first and after the last ordinary
+ *       peer ID.
+ *
+ * @param[in]  prev_peer_id  The previous peer ID.
+ *
+ * @return  The first ordinary peer ID  If @p prev_peer_id is @ref PM_PEER_ID_INVALID.
+ * @retval  PM_PEER_ID_INVALID          If @p prev_peer_id is the last ordinary peer ID or the module
+ *                                      is not initialized.
+ */
+pm_peer_id_t pds_next_peer_id_get(pm_peer_id_t prev_peer_id);
+
+
+/**@brief Function for getting the next peer ID in the sequence of all peer IDs pending deletion.
+ *        Can be used to loop through all used peer IDs.
+ *
+ * @note @ref PM_PEER_ID_INVALID is considered to be before the first and after the last ordinary
+ *       peer ID.
+ *
+ * @param[in]  prev_peer_id  The previous peer ID.
+ *
+ * @return  The next peer ID pending deletion.
+ * @return  The first ordinary peer ID  if prev_peer_id was @ref PM_PEER_ID_INVALID.
+ * @retval  PM_PEER_ID_INVALID          if prev_peer_id was the last ordinary peer ID or the module
+ *                                      is not initialized.
+ */
+pm_peer_id_t pds_next_deleted_peer_id_get(pm_peer_id_t prev_peer_id);
+
+
+/**@brief Function for querying the number of valid peer IDs available. I.E the number of peers
+ *        in persistent storage.
+ *
+ * @return  The number of valid peer IDs.
+ */
+uint32_t pds_peer_count_get(void);
+
+
+/** @}
+ * @endcond
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PEER_DATA_STORAGE_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_database.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,782 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(PEER_MANAGER)
+#include "peer_database.h"
+
+#include <string.h>
+#include "peer_manager_types.h"
+#include "peer_manager_internal.h"
+#include "peer_data_storage.h"
+#include "pm_buffer.h"
+
+
+#define N_WRITE_BUFFERS             (8)                 /**< The number of write buffers available. */
+#define N_WRITE_BUFFER_RECORDS      (N_WRITE_BUFFERS)   /**< The number of write buffer records. */
+
+
+/**@brief Macro for verifying that the data ID is among the values eligible for using the write buffer.
+ *
+ * @param[in] data_id  The data ID to verify.
+ */
+// @note emdi: could this maybe be a function?
+#define VERIFY_DATA_ID_WRITE_BUF(data_id)                                                    \
+do                                                                                           \
+{                                                                                            \
+    if (((data_id) != PM_PEER_DATA_ID_BONDING) && ((data_id) != PM_PEER_DATA_ID_GATT_LOCAL)) \
+    {                                                                                        \
+        return NRF_ERROR_INVALID_PARAM;                                                      \
+    }                                                                                        \
+} while (0)
+
+
+// The number of registered event handlers.
+#define PDB_EVENT_HANDLERS_CNT      (sizeof(m_evt_handlers) / sizeof(m_evt_handlers[0]))
+
+
+// Peer Database event handlers in other Peer Manager submodules.
+extern void pm_pdb_evt_handler(pdb_evt_t const * p_event);
+extern void im_pdb_evt_handler(pdb_evt_t const * p_event);
+extern void sm_pdb_evt_handler(pdb_evt_t const * p_event);
+extern void smd_pdb_evt_handler(pdb_evt_t const * p_event);
+extern void gscm_pdb_evt_handler(pdb_evt_t const * p_event);
+
+// Peer Database events' handlers.
+// The number of elements in this array is PDB_EVENT_HANDLERS_CNT.
+static pdb_evt_handler_t const m_evt_handlers[] =
+{
+    pm_pdb_evt_handler,
+    im_pdb_evt_handler,
+    sm_pdb_evt_handler,
+    smd_pdb_evt_handler,
+    gscm_pdb_evt_handler,
+};
+
+
+/**@brief Struct for keeping track of one write buffer, from allocation, until it is fully written
+ *        or cancelled.
+ */
+typedef struct
+{
+    pm_peer_id_t        peer_id;               /**< The peer ID this buffer belongs to. */
+    pm_peer_data_id_t   data_id;               /**< The data ID this buffer belongs to. */
+    pm_prepare_token_t  prepare_token;         /**< Token given by Peer Data Storage if room in flash has been reserved. */
+    pm_store_token_t    store_token;           /**< Token given by Peer Data Storage when a flash write has been successfully requested. */
+    uint32_t            n_bufs;                /**< The number of buffer blocks containing peer data. */
+    uint8_t             buffer_block_id;       /**< The index of the first (or only) buffer block containing peer data. */
+    uint8_t             store_requested  : 1;  /**< Flag indicating that the buffer is being written to flash. */
+    uint8_t             store_flash_full : 1;  /**< Flag indicating that the buffer was attempted written to flash, but a flash full error was returned and the operation should be retried after room has been made. */
+    uint8_t             store_busy       : 1;  /**< Flag indicating that the buffer was attempted written to flash, but a busy error was returned and the operation should be retried. */
+} pdb_buffer_record_t;
+
+
+static bool                m_module_initialized;
+static pm_buffer_t         m_write_buffer;                                 /**< The state of the write buffer. */
+static pdb_buffer_record_t m_write_buffer_records[N_WRITE_BUFFER_RECORDS]; /**< The available write buffer records. */
+static uint32_t            m_n_writes;                                     /**< The number of pending (Not yet successfully requested in Peer Data Storage) store operations. */
+
+
+
+/**@brief Function for invalidating a record of a write buffer allocation.
+ *
+ * @param[in]  p_record  The record to invalidate.
+ */
+static void write_buffer_record_invalidate(pdb_buffer_record_t * p_record)
+{
+    p_record->peer_id          = PM_PEER_ID_INVALID;
+    p_record->data_id          = PM_PEER_DATA_ID_INVALID;
+    p_record->buffer_block_id  = PM_BUFFER_INVALID_ID;
+    p_record->store_busy       = false;
+    p_record->store_flash_full = false;
+    p_record->store_requested  = false;
+    p_record->n_bufs           = 0;
+    p_record->prepare_token    = PDS_PREPARE_TOKEN_INVALID;
+    p_record->store_token      = PM_STORE_TOKEN_INVALID;
+}
+
+
+/**@brief Function for finding a record of a write buffer allocation.
+ *
+ * @param[in]    peer_id  The peer ID in the record.
+ * @param[inout] p_index  In: The starting index, out: The index of the record
+ *
+ * @return  A pointer to the matching record, or NULL if none was found.
+ */
+static pdb_buffer_record_t * write_buffer_record_find_next(pm_peer_id_t peer_id, int * p_index)
+{
+    for (uint32_t i = *p_index; i < N_WRITE_BUFFER_RECORDS; i++)
+    {
+        if ((m_write_buffer_records[i].peer_id == peer_id))
+        {
+            return &m_write_buffer_records[i];
+        }
+    }
+    return NULL;
+}
+
+
+/**@brief Function for finding a record of a write buffer allocation.
+ *
+ * @param[in]  peer_id  The peer ID in the record.
+ * @param[in]  data_id  The data ID in the record.
+ *
+ * @return  A pointer to the matching record, or NULL if none was found.
+ */
+static pdb_buffer_record_t * write_buffer_record_find(pm_peer_id_t      peer_id,
+                                                      pm_peer_data_id_t data_id)
+{
+    int index = 0;
+    pdb_buffer_record_t * p_record = write_buffer_record_find_next(peer_id, &index);
+
+    while ((p_record != NULL) && (p_record->data_id != data_id))
+    {
+        index++;
+        p_record = write_buffer_record_find_next(peer_id, &index);
+    }
+
+    return p_record;
+}
+
+
+/**@brief Function for finding an available record for write buffer allocation.
+ *
+ * @return  A pointer to the available record, or NULL if none was found.
+ */
+static pdb_buffer_record_t * write_buffer_record_find_unused(void)
+{
+    return write_buffer_record_find(PM_PEER_ID_INVALID, PM_PEER_DATA_ID_INVALID);
+}
+
+
+/**@brief Function for gracefully deactivating a write buffer record.
+ *
+ * @details This function will first release any buffers, then invalidate the record.
+ *
+ * @param[inout] p_write_buffer_record  The record to release.
+ *
+ * @return  A pointer to the matching record, or NULL if none was found.
+ */
+static void write_buffer_record_release(pdb_buffer_record_t * p_write_buffer_record)
+{
+    for (uint32_t i = 0; i < p_write_buffer_record->n_bufs; i++)
+    {
+        pm_buffer_release(&m_write_buffer, p_write_buffer_record->buffer_block_id + i);
+    }
+
+    write_buffer_record_invalidate(p_write_buffer_record);
+}
+
+
+/**@brief Function for claiming and activating a write buffer record.
+ *
+ * @param[out] pp_write_buffer_record  The claimed record.
+ * @param[in]   peer_id                 The peer ID this record should have.
+ * @param[in]  data_id                 The data ID this record should have.
+ */
+static void write_buffer_record_get(pdb_buffer_record_t ** pp_write_buffer_record, pm_peer_id_t peer_id, pm_peer_data_id_t data_id)
+{
+    if (pp_write_buffer_record == NULL)
+    {
+        return;
+    }
+    *pp_write_buffer_record = write_buffer_record_find_unused();
+    if (*pp_write_buffer_record == NULL)
+    {
+        // This also means the buffer is full.
+        return;
+    }
+    (*pp_write_buffer_record)->peer_id = peer_id;
+    (*pp_write_buffer_record)->data_id = data_id;
+}
+
+
+/**@brief Function for dispatching outbound events to all registered event handlers.
+ *
+ * @param[in]  p_event  The event to dispatch.
+ */
+static void pdb_evt_send(pdb_evt_t * p_event)
+{
+    for (uint32_t i = 0; i < PDB_EVENT_HANDLERS_CNT; i++)
+    {
+        m_evt_handlers[i](p_event);
+    }
+}
+
+
+/**@brief Function for resetting the internal state of the Peer Database module.
+ *
+ * @param[out] p_event  The event to dispatch.
+ */
+static void internal_state_reset()
+{
+    for (uint32_t i = 0; i < N_WRITE_BUFFER_RECORDS; i++)
+    {
+        write_buffer_record_invalidate(&m_write_buffer_records[i]);
+    }
+}
+
+
+/**@brief Function for handling events from the Peer Data Storage module.
+ *        This function is extern in Peer Data Storage.
+ *
+ * @param[in]  p_event  The event to handle.
+ */
+void pdb_pds_evt_handler(pds_evt_t const * p_event)
+{
+    ret_code_t            err_code;
+    pdb_buffer_record_t * p_write_buffer_record;
+    bool                  retry_flash_full = false;
+    pdb_evt_t             event =
+    {
+        .peer_id = p_event->peer_id,
+        .data_id = p_event->data_id,
+    };
+
+    p_write_buffer_record = write_buffer_record_find(p_event->peer_id, p_event->data_id);
+
+    switch (p_event->evt_id)
+    {
+        case PDS_EVT_STORED:
+        case PDS_EVT_UPDATED:
+            if (   (p_write_buffer_record != NULL)
+                //&& (p_write_buffer_record->store_token == p_event->store_token)
+                && (p_write_buffer_record->store_requested))
+            {
+                write_buffer_record_release(p_write_buffer_record);
+                event.evt_id = PDB_EVT_WRITE_BUF_STORED;
+                event.params.write_buf_stored_evt.update = (p_event->evt_id == PDS_EVT_UPDATED);
+                pdb_evt_send(&event);
+            }
+            else
+            {
+                event.evt_id = PDB_EVT_RAW_STORED;
+                event.params.raw_stored_evt.store_token = p_event->store_token;
+                pdb_evt_send(&event);
+            }
+            break;
+        case PDS_EVT_ERROR_STORE:
+        case PDS_EVT_ERROR_UPDATE:
+            if (   (p_write_buffer_record != NULL)
+                && (p_write_buffer_record->store_token == p_event->store_token)
+                && (p_write_buffer_record->store_requested))
+            {
+                // Retry if internal buffer.
+                m_n_writes++;
+                p_write_buffer_record->store_requested = false;
+                p_write_buffer_record->store_busy      = true;
+            }
+            else
+            {
+                event.evt_id                              = PDB_EVT_RAW_STORE_FAILED;
+                event.params.error_raw_store_evt.err_code = p_event->result;
+                pdb_evt_send(&event);
+            }
+            break;
+        case PDS_EVT_CLEARED:
+            event.evt_id = PDB_EVT_CLEARED;
+            pdb_evt_send(&event);
+            break;
+        case PDS_EVT_ERROR_CLEAR:
+            event.evt_id = PDB_EVT_CLEAR_FAILED;
+            event.params.clear_failed_evt.err_code = p_event->result;
+            pdb_evt_send(&event);
+            break;
+        case PDS_EVT_PEER_ID_CLEAR:
+            event.evt_id = PDB_EVT_PEER_FREED;
+            pdb_evt_send(&event);
+            break;
+        case PDS_EVT_ERROR_PEER_ID_CLEAR:
+            event.evt_id = PDB_EVT_PEER_FREE_FAILED;
+            event.params.peer_free_failed_evt.err_code = p_event->result;
+            pdb_evt_send(&event);
+            break;
+        case PDS_EVT_COMPRESSED:
+            retry_flash_full = true;
+            event.evt_id = PDB_EVT_COMPRESSED;
+            pdb_evt_send(&event);
+            break;
+        case PDS_EVT_ERROR_UNEXPECTED:
+            event.params.error_unexpected.err_code = p_event->result;
+            break;
+        default:
+            break;
+    }
+
+    if (m_n_writes > 0)
+    {
+        for (uint32_t i = 0; i < N_WRITE_BUFFER_RECORDS; i++)
+        {
+            if  ((m_write_buffer_records[i].store_busy)
+              || (m_write_buffer_records[i].store_flash_full && retry_flash_full))
+            {
+                err_code = pdb_write_buf_store(m_write_buffer_records[i].peer_id,
+                                               m_write_buffer_records[i].data_id);
+                if (err_code != NRF_SUCCESS)
+                {
+                    event.peer_id = m_write_buffer_records[i].peer_id;
+                    event.data_id = m_write_buffer_records[i].data_id;
+                    if (err_code == NRF_ERROR_STORAGE_FULL)
+                    {
+                        event.evt_id = PDB_EVT_ERROR_NO_MEM;
+                    }
+                    else
+                    {
+                        event.evt_id                           = PDB_EVT_ERROR_UNEXPECTED;
+                        event.params.error_unexpected.err_code = err_code;
+                    }
+
+                    pdb_evt_send(&event);
+                    break;
+                }
+            }
+        }
+    }
+}
+
+
+ret_code_t pdb_init()
+{
+    ret_code_t ret;
+
+    NRF_PM_DEBUG_CHECK(!m_module_initialized);
+
+    internal_state_reset();
+
+    PM_BUFFER_INIT(&m_write_buffer, N_WRITE_BUFFERS, PDB_WRITE_BUF_SIZE, ret);
+
+    if (ret != NRF_SUCCESS)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    m_module_initialized = true;
+
+    return NRF_SUCCESS;
+}
+
+
+pm_peer_id_t pdb_peer_allocate(void)
+{
+    #if 0
+    if (!MODULE_INITIALIZED)
+    {
+        return PM_PEER_ID_INVALID;
+    }
+    #endif
+
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    return pds_peer_id_allocate();
+}
+
+
+ret_code_t pdb_peer_free(pm_peer_id_t peer_id)
+{
+    ret_code_t err_code_in  = NRF_SUCCESS;
+    ret_code_t err_code_out = NRF_SUCCESS;
+
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    int index = 0;
+    pdb_buffer_record_t * p_record = write_buffer_record_find_next(peer_id, &index);
+
+    while (p_record != NULL)
+    {
+        err_code_in = pdb_write_buf_release(peer_id, p_record->data_id);
+
+        if (   (err_code_in != NRF_SUCCESS)
+            && (err_code_in != NRF_ERROR_NOT_FOUND))
+        {
+            err_code_out = NRF_ERROR_INTERNAL;
+        }
+
+        index++;
+        p_record = write_buffer_record_find_next(peer_id, &index);
+    }
+
+    if (err_code_out == NRF_SUCCESS)
+    {
+        err_code_in = pds_peer_id_free(peer_id);
+
+        if (err_code_in == NRF_SUCCESS)
+        {
+            // No action needed.
+        }
+        else if (err_code_in == NRF_ERROR_INVALID_PARAM)
+        {
+            err_code_out = NRF_ERROR_INVALID_PARAM;
+        }
+        else
+        {
+            err_code_out = NRF_ERROR_INTERNAL;
+        }
+    }
+
+    return err_code_out;
+}
+
+
+ret_code_t pdb_peer_data_ptr_get(pm_peer_id_t                 peer_id,
+                                 pm_peer_data_id_t            data_id,
+                                 pm_peer_data_flash_t * const p_peer_data)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    NRF_PM_DEBUG_CHECK(p_peer_data != NULL);
+
+    // Pass NULL to only retrieve a pointer.
+    return pds_peer_data_read(peer_id, data_id, (pm_peer_data_t*)p_peer_data, NULL);
+}
+
+
+static void peer_data_point_to_buffer(pm_peer_data_t * p_peer_data, pm_peer_data_id_t data_id, uint8_t * p_buffer_memory, uint16_t n_bufs)
+{
+    uint16_t n_bytes = n_bufs * PDB_WRITE_BUF_SIZE;
+    p_peer_data->data_id    = data_id;
+
+    p_peer_data->p_all_data   = (pm_peer_data_bonding_t *)p_buffer_memory;
+    p_peer_data->length_words = BYTES_TO_WORDS(n_bytes);
+}
+
+
+static void peer_data_const_point_to_buffer(pm_peer_data_const_t * p_peer_data, pm_peer_data_id_t data_id,  uint8_t * p_buffer_memory, uint32_t n_bufs)
+{
+    peer_data_point_to_buffer((pm_peer_data_t*)p_peer_data, data_id, p_buffer_memory, n_bufs);
+}
+
+
+static void write_buf_length_words_set(pm_peer_data_const_t * p_peer_data)
+{
+    switch (p_peer_data->data_id)
+    {
+        case PM_PEER_DATA_ID_BONDING:
+            p_peer_data->length_words = PM_BONDING_DATA_N_WORDS();
+            break;
+        case PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING:
+            p_peer_data->length_words = PM_SC_STATE_N_WORDS();
+            break;
+        case PM_PEER_DATA_ID_PEER_RANK:
+            p_peer_data->length_words = PM_USAGE_INDEX_N_WORDS();
+            break;
+        case PM_PEER_DATA_ID_GATT_LOCAL:
+            p_peer_data->length_words = PM_LOCAL_DB_N_WORDS(p_peer_data->p_local_gatt_db->len);
+            break;
+        default:
+            // No action needed.
+            break;
+    }
+}
+
+
+ret_code_t pdb_write_buf_get(pm_peer_id_t       peer_id,
+                             pm_peer_data_id_t  data_id,
+                             uint32_t           n_bufs,
+                             pm_peer_data_t   * p_peer_data)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    VERIFY_PARAM_NOT_NULL(p_peer_data);
+    VERIFY_DATA_ID_WRITE_BUF(data_id);
+
+    if (   (n_bufs == 0)
+        || (n_bufs > N_WRITE_BUFFERS)
+        || !pds_peer_id_is_allocated(peer_id))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    pdb_buffer_record_t * write_buffer_record;
+    uint8_t             * p_buffer_memory;
+    bool                  new_record = false;
+
+    write_buffer_record = write_buffer_record_find(peer_id, data_id);
+
+    if ((write_buffer_record != NULL) && (write_buffer_record->n_bufs < n_bufs))
+    {
+        // @TODO: Copy?
+        // Existing buffer is too small.
+        for (uint8_t i = 0; i < write_buffer_record->n_bufs; i++)
+        {
+            pm_buffer_release(&m_write_buffer, write_buffer_record->buffer_block_id + i);
+        }
+        write_buffer_record_invalidate(write_buffer_record);
+        write_buffer_record = NULL;
+    }
+    else if ((write_buffer_record != NULL) && write_buffer_record->n_bufs > n_bufs)
+    {
+        // Release excess blocks.
+        for (uint8_t i = n_bufs; i < write_buffer_record->n_bufs; i++)
+        {
+            pm_buffer_release(&m_write_buffer, write_buffer_record->buffer_block_id + i);
+        }
+    }
+
+    if (write_buffer_record == NULL)
+    {
+        write_buffer_record_get(&write_buffer_record, peer_id, data_id);
+        if (write_buffer_record == NULL)
+        {
+            return NRF_ERROR_BUSY;
+        }
+    }
+
+    if (write_buffer_record->buffer_block_id == PM_BUFFER_INVALID_ID)
+    {
+        write_buffer_record->buffer_block_id = pm_buffer_block_acquire(&m_write_buffer, n_bufs);
+
+        if (write_buffer_record->buffer_block_id == PM_BUFFER_INVALID_ID)
+        {
+            write_buffer_record_invalidate(write_buffer_record);
+            return NRF_ERROR_BUSY;
+        }
+
+        new_record = true;
+    }
+
+    write_buffer_record->n_bufs = n_bufs;
+
+    p_buffer_memory = pm_buffer_ptr_get(&m_write_buffer, write_buffer_record->buffer_block_id);
+
+    if (p_buffer_memory == NULL)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    peer_data_point_to_buffer(p_peer_data, data_id, p_buffer_memory, n_bufs);
+    if (new_record && (data_id == PM_PEER_DATA_ID_GATT_LOCAL))
+    {
+        p_peer_data->p_local_gatt_db->len = PM_LOCAL_DB_LEN(p_peer_data->length_words);
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pdb_write_buf_release(pm_peer_id_t peer_id, pm_peer_data_id_t data_id)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    ret_code_t            err_code = NRF_SUCCESS;
+    pdb_buffer_record_t * p_write_buffer_record;
+    p_write_buffer_record = write_buffer_record_find(peer_id, data_id);
+
+    if (p_write_buffer_record == NULL)
+    {
+        return NRF_ERROR_NOT_FOUND;
+    }
+
+    if (p_write_buffer_record->prepare_token != PDS_PREPARE_TOKEN_INVALID)
+    {
+        err_code = pds_space_reserve_cancel(p_write_buffer_record->prepare_token);
+        if (err_code != NRF_SUCCESS)
+        {
+            err_code = NRF_ERROR_INTERNAL;
+        }
+    }
+
+    write_buffer_record_release(p_write_buffer_record);
+
+    return err_code;
+}
+
+
+ret_code_t pdb_write_buf_store_prepare(pm_peer_id_t peer_id, pm_peer_data_id_t data_id)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    VERIFY_DATA_ID_WRITE_BUF(data_id);
+
+    ret_code_t            err_code = NRF_SUCCESS;
+    pdb_buffer_record_t * p_write_buffer_record;
+    p_write_buffer_record = write_buffer_record_find(peer_id, data_id);
+
+    if (p_write_buffer_record == NULL)
+    {
+        return NRF_ERROR_NOT_FOUND;
+    }
+
+    if (p_write_buffer_record->prepare_token == PDS_PREPARE_TOKEN_INVALID)
+    {
+        uint8_t * p_buffer_memory = pm_buffer_ptr_get(&m_write_buffer, p_write_buffer_record->buffer_block_id);
+        pm_peer_data_const_t peer_data = {.data_id = data_id};
+
+        if (p_buffer_memory == NULL)
+        {
+            return NRF_ERROR_INTERNAL;
+        }
+
+        peer_data_const_point_to_buffer(&peer_data, data_id, p_buffer_memory, p_write_buffer_record->n_bufs);
+
+        write_buf_length_words_set(&peer_data);
+
+        err_code = pds_space_reserve(&peer_data, &p_write_buffer_record->prepare_token);
+        if (err_code == NRF_ERROR_INVALID_LENGTH)
+        {
+            return NRF_ERROR_INTERNAL;
+        }
+    }
+
+    return err_code;
+}
+
+
+ret_code_t pdb_write_buf_store(pm_peer_id_t      peer_id,
+                               pm_peer_data_id_t data_id)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    VERIFY_DATA_ID_WRITE_BUF(data_id);
+
+    ret_code_t            err_code = NRF_SUCCESS;
+    pdb_buffer_record_t * p_write_buffer_record;
+    uint8_t             * p_buffer_memory;
+    pm_peer_data_const_t  peer_data = {.data_id = data_id};
+
+
+    p_write_buffer_record = write_buffer_record_find(peer_id, data_id);
+
+    if (p_write_buffer_record == NULL)
+    {
+        return NRF_ERROR_NOT_FOUND;
+    }
+
+    if (p_write_buffer_record->store_requested)
+    {
+        return NRF_SUCCESS;
+    }
+
+    p_buffer_memory = pm_buffer_ptr_get(&m_write_buffer, p_write_buffer_record->buffer_block_id);
+
+    if (p_buffer_memory == NULL)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    peer_data_const_point_to_buffer(&peer_data, data_id, p_buffer_memory, p_write_buffer_record->n_bufs);
+
+    write_buf_length_words_set(&peer_data);
+
+    err_code = pds_peer_data_store(peer_id,
+                                   &peer_data,
+                                   p_write_buffer_record->prepare_token,
+                                   &p_write_buffer_record->store_token);
+
+    if (p_write_buffer_record->store_busy && p_write_buffer_record->store_flash_full)
+    {
+        m_n_writes--;
+    }
+
+    if (err_code == NRF_SUCCESS)
+    {
+        p_write_buffer_record->store_requested  = true;
+        p_write_buffer_record->store_busy       = false;
+        p_write_buffer_record->store_flash_full = false;
+    }
+    else
+    {
+        if (err_code == NRF_ERROR_BUSY)
+        {
+            m_n_writes++;
+            p_write_buffer_record->store_busy       = true;
+            p_write_buffer_record->store_flash_full = false;
+            err_code = NRF_SUCCESS;
+        }
+        else if (err_code == NRF_ERROR_STORAGE_FULL)
+        {
+            m_n_writes++;
+            p_write_buffer_record->store_busy       = false;
+            p_write_buffer_record->store_flash_full = true;
+        }
+        else if (err_code != NRF_ERROR_INVALID_PARAM)
+        {
+            err_code = NRF_ERROR_INTERNAL;
+        }
+    }
+
+    return err_code;
+}
+
+
+ret_code_t pdb_clear(pm_peer_id_t peer_id, pm_peer_data_id_t data_id)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    return pds_peer_data_delete(peer_id, data_id);
+}
+
+
+uint32_t pdb_n_peers(void)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    return pds_peer_count_get();
+}
+
+
+pm_peer_id_t pdb_next_peer_id_get(pm_peer_id_t prev_peer_id)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    return pds_next_peer_id_get(prev_peer_id);
+}
+
+
+pm_peer_id_t pdb_next_deleted_peer_id_get(pm_peer_id_t prev_peer_id)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    return pds_next_deleted_peer_id_get(prev_peer_id);
+}
+
+
+ret_code_t pdb_peer_data_load(pm_peer_id_t              peer_id,
+                              pm_peer_data_id_t         data_id,
+                              pm_peer_data_t    * const p_peer_data)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    NRF_PM_DEBUG_CHECK(p_peer_data != NULL);
+
+    // Provide the buffer length in bytes.
+    uint32_t const data_len_bytes = (p_peer_data->length_words * sizeof(uint32_t));
+    return pds_peer_data_read(peer_id, data_id, p_peer_data, &data_len_bytes);
+}
+
+
+ret_code_t pdb_raw_store(pm_peer_id_t           peer_id,
+                         pm_peer_data_const_t * p_peer_data,
+                         pm_store_token_t     * p_store_token)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    return pds_peer_data_store(peer_id, p_peer_data, PDS_PREPARE_TOKEN_INVALID, p_store_token);
+}
+#endif // NRF_MODULE_ENABLED(PEER_MANAGER)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_database.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,393 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef PEER_DATABASE_H__
+#define PEER_DATABASE_H__
+
+#include <stdint.h>
+#include "peer_manager_types.h"
+#include "peer_manager_internal.h"
+#include "sdk_errors.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup peer_database Peer Database
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. A module for simple management of reading and
+ *        writing of peer data into persistent storage.
+ *
+ */
+
+#define PDB_WRITE_BUF_SIZE (sizeof(pm_peer_data_bonding_t)) //!< The size (in bytes) of each block in the internal buffer accessible via @ref pdb_write_buf_get.
+
+/**@brief Events that can come from the peer_database module.
+ */
+typedef enum
+{
+    PDB_EVT_WRITE_BUF_STORED,   /**< A @ref pdb_write_buf_store operation has completed successfully. */
+    PDB_EVT_RAW_STORED,         /**< A @ref pdb_raw_store operation has completed successfully. */
+    PDB_EVT_RAW_STORE_FAILED,   /**< A @ref pdb_raw_store operation has failed. */
+    PDB_EVT_CLEARED,            /**< A @ref pdb_clear operation has completed successfully. */
+    PDB_EVT_CLEAR_FAILED,       /**< A @ref pdb_clear operation has failed. */
+    PDB_EVT_PEER_FREED,         /**< A @ref pdb_peer_free operation has completed successfully. All associated data has been erased. */
+    PDB_EVT_PEER_FREE_FAILED,   /**< A @ref pdb_peer_free operation has failed. */
+    PDB_EVT_COMPRESSED,         /**< A compress procedure has completed. */
+    PDB_EVT_ERROR_NO_MEM,       /**< An operation is blocked because the flash is full. It will be reattempted automatically after the next compress procedure. */
+    PDB_EVT_ERROR_UNEXPECTED,   /**< An unexpected error occurred. This is a fatal error. */
+} pdb_evt_id_t;
+
+/**@brief Events that can come from the peer_database module.
+ */
+typedef struct
+{
+    pdb_evt_id_t      evt_id;  /**< The event that has happened. */
+    pm_peer_id_t      peer_id; /**< The id of the peer the event pertains to. */
+    pm_peer_data_id_t data_id; /**< The data the event pertains to. */
+    union
+    {
+        struct
+        {
+            bool update;                   /**< If true, an existing value was overwritten. */
+        } write_buf_stored_evt;            /**< Additional information pertaining to the @ref PDB_EVT_WRITE_BUF_STORED event. */
+        struct
+        {
+            pm_store_token_t store_token;  /**< A token identifying the store operation this event pertains to. */
+        } raw_stored_evt;                  /**< Additional information pertaining to the @ref PDB_EVT_RAW_STORED event. */
+        struct
+        {
+            pm_store_token_t store_token;  /**< A token identifying the store operation this event pertains to. */
+            ret_code_t       err_code;     /**< Error code specifying what went wrong. */
+        } error_raw_store_evt;             /**< Additional information pertaining to the @ref PDB_EVT_RAW_STORE_FAILED event. */
+        struct
+        {
+            ret_code_t err_code;           /**< The error that occurred. */
+        } clear_failed_evt;                /**< Additional information pertaining to the @ref PDB_EVT_CLEAR_FAILED event. */
+        struct
+        {
+            ret_code_t err_code;           /**< The error that occurred. */
+        } peer_free_failed_evt;            /**< Additional information pertaining to the @ref PDB_EVT_PEER_FREE_FAILED event. */
+        struct
+        {
+            ret_code_t err_code;           /**< The unexpected error that occurred. */
+        } error_unexpected;                /**< Additional information pertaining to the @ref PDB_EVT_ERROR_UNEXPECTED event. */
+    } params;
+} pdb_evt_t;
+
+/**@brief Event handler for events from the peer_data_storage module.
+ *
+ * @param[in]  p_event   The event that has happened.
+ */
+typedef void (*pdb_evt_handler_t)(pdb_evt_t const * p_event);
+
+
+/**@brief Function for initializing the module.
+ *
+ * @retval NRF_SUCCESS          If initialization was successful.
+ * @retval NRF_ERROR_INTERNAL   An unexpected error happened.
+ */
+ret_code_t pdb_init(void);
+
+
+/**@brief Function for allocating persistent bond storage for a peer.
+ *
+ * @return  The ID of the newly allocated storage.
+ * @retval  PM_PEER_ID_INVALID  If no peer ID is available.
+ */
+pm_peer_id_t pdb_peer_allocate(void);
+
+
+/**@brief Function for freeing a peer's persistent bond storage.
+ *
+ * @note This function will call @ref pdb_write_buf_release on the data for this peer.
+ *
+ * @param[in] peer_id  ID to be freed.
+ *
+ * @retval NRF_SUCCESS              Peer ID was released and clear operation was initiated successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  Peer ID was invalid.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t pdb_peer_free(pm_peer_id_t peer_id);
+
+
+/**@brief Function for retrieving a pointer to peer data in flash (read-only).
+ *
+ * @note  Dereferencing this pointer is not the safest thing to do if interrupts are enabled,
+ *        because Flash Data Storage garbage collection might move the data around. Either disable
+ *        interrupts while using the data, or use @ref pdb_peer_data_load.
+ *
+ * @param[in]  peer_id      The peer the data belongs to.
+ * @param[in]  data_id      The data to read.
+ * @param[out] p_peer_data  The peer data, read-only.
+ *
+ * @retval NRF_SUCCESS              If the pointer to the data was retrieved successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  If either @p peer_id or @p data_id are invalid.
+ * @retval NRF_ERROR_NOT_FOUND      If data was not found in flash.
+ */
+ret_code_t pdb_peer_data_ptr_get(pm_peer_id_t                 peer_id,
+                                 pm_peer_data_id_t            data_id,
+                                 pm_peer_data_flash_t * const p_peer_data);
+
+
+/**@brief Function for retrieving pointers to a write buffer for peer data.
+ *
+ * @details This function will provide pointers to a buffer of the data. The data buffer will not be
+ *          written to persistent storage until @ref pdb_write_buf_store is called. The buffer is
+ *          released by calling either @ref pdb_write_buf_release, @ref pdb_write_buf_store, or
+ *          @ref pdb_peer_free.
+ *
+ *          When the data_id refers to a variable length data type, the available size is written
+ *          to the data, both the top-level, and any internal length fields.
+ *
+ * @note Calling this function on a peer_id/data_id pair that already has a buffer created will
+ *       give the same buffer, not create a new one. If n_bufs was increased since last time, the
+ *       buffer might be relocated to be able to provide additional room. In this case, the data
+ *       will be copied. If n_bufs was increased since last time, this function might return @ref
+ *       NRF_ERROR_BUSY. In that case, the buffer is automatically released.
+ *
+ * @param[in]  peer_id      ID of peer to get a write buffer for.
+ * @param[in]  data_id      Which piece of data to get.
+ * @param[in]  n_bufs       The number of contiguous buffers needed.
+ * @param[out] p_peer_data  Pointers to mutable peer data.
+ *
+ * @retval NRF_SUCCESS              Data retrieved successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  Data ID or Peer ID was invalid or unallocated, or n_bufs was 0
+ *                                  or more than the total available buffers.
+ * @retval NRF_ERROR_NULL           p_peer_data was NULL.
+ * @retval NRF_ERROR_BUSY           Not enough buffer(s) available.
+ * @retval NRF_ERROR_INTERNAL       Unexpected internal error.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t pdb_write_buf_get(pm_peer_id_t      peer_id,
+                             pm_peer_data_id_t data_id,
+                             uint32_t          n_bufs,
+                             pm_peer_data_t  * p_peer_data);
+
+
+/**@brief Function for freeing a write buffer allocated with @ref pdb_write_buf_get.
+ *
+ * @note This function will not write peer data to persistent memory. Data in released buffer will
+ *       be lost.
+ *
+ * @note This function will undo any previous call to @ref pdb_write_buf_store_prepare for this
+ *       piece of data.
+ *
+ * @param[in]  peer_id  ID of peer to release buffer for.
+ * @param[in]  data_id  Which piece of data to release buffer for.
+ *
+ * @retval NRF_SUCCESS              Successfully released buffer.
+ * @retval NRF_ERROR_NOT_FOUND      No buffer was allocated for this peer ID/data ID pair.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ * @retval NRF_ERROR_INTERNAL       Unexpected internal error.
+ */
+ret_code_t pdb_write_buf_release(pm_peer_id_t peer_id, pm_peer_data_id_t data_id);
+
+
+/**@brief Function for reserving space in persistent storage for data in a buffer.
+ *
+ * @note This function only works for data which has a write buffer allocated. If the write buffer
+ *       is released, this prepare is undone.
+ *
+ * @note If space has already been reserved for this data, nothing is done.
+ *
+ * @param[in]  peer_id  The peer whose data to reserve space for.
+ * @param[in]  data_id  The type of data to reserve space for.
+ *
+ * @retval NRF_SUCCESS              Successfully reserved space in persistent storage.
+ * @retval NRF_ERROR_STORAGE_FULL   Not enough room in persistent storage.
+ * @retval NRF_ERROR_BUSY           Could not process request at this time. Reattempt later.
+ * @retval NRF_ERROR_NOT_FOUND      No buffer has been allocated for this peer ID/data ID pair.
+ * @retval NRF_ERROR_INVALID_PARAM  Data ID or Peer ID was invalid or unallocated.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t pdb_write_buf_store_prepare(pm_peer_id_t peer_id, pm_peer_data_id_t data_id);
+
+
+/**@brief Function for writing data into persistent storage. Writing happens asynchronously.
+ *
+ * @note This will unlock the data after it has been written.
+ *
+ * @param[in]  peer_id      ID of peer to store data for.
+ * @param[in]  data_id      Which piece of data to store.
+ *
+ * @retval NRF_SUCCESS              Data storing was successfully started.
+ * @retval NRF_ERROR_STORAGE_FULL   No space available in persistent storage. Please clear some
+ *                                  space, the operation will be reattempted after the next compress
+ *                                  procedure. This error will not happen if
+ *                                  @ref pdb_write_buf_store_prepare is called beforehand.
+ * @retval NRF_ERROR_INVALID_PARAM  Data ID was invalid.
+ * @retval NRF_ERROR_NOT_FOUND      No buffer has been allocated for this peer ID/data ID pair.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ * @retval NRF_ERROR_INTERNAL       Unexpected internal error.
+ */
+ret_code_t pdb_write_buf_store(pm_peer_id_t      peer_id,
+                               pm_peer_data_id_t data_id);
+
+
+/**@brief Function for clearing data from persistent storage.
+ *
+ * @param[in]  peer_id  ID of peer to clear data for.
+ * @param[in]  data_id  Which piece of data to clear.
+ *
+ * @retval NRF_SUCCESS              The clear was initiated successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  Data ID or peer ID was invalid.
+ * @retval NRF_ERROR_NOT_FOUND      Nothing to clear for this peer ID/data ID combination.
+ * @retval NRF_ERROR_BUSY           Underlying modules are busy and can't take any more requests at
+ *                                  this moment.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ * @retval NRF_ERROR_INTERNAL       Internal error.
+ */
+ret_code_t pdb_clear(pm_peer_id_t peer_id, pm_peer_data_id_t data_id);
+
+
+/**@brief Function for querying the number of valid peer IDs available. I.E the number of peers
+ *        in persistent storage.
+ *
+ * @return  The number of valid peer IDs.
+ */
+uint32_t pdb_n_peers(void);
+
+
+/**@brief Function for getting the next peer ID in the sequence of all used peer IDs. Can be
+ *        used to loop through all used peer IDs.
+ *
+ * @note @ref PM_PEER_ID_INVALID is considered to be before the first and after the last ordinary
+ *       peer ID.
+ *
+ * @param[in]  prev_peer_id  The previous peer ID.
+ *
+ * @return  The next peer ID.
+ * @return  The first ordinary peer ID  if prev_peer_id was @ref PM_PEER_ID_INVALID.
+ * @retval  PM_PEER_ID_INVALID          if prev_peer_id was the last ordinary peer ID.
+ */
+pm_peer_id_t pdb_next_peer_id_get(pm_peer_id_t prev_peer_id);
+
+
+/**@brief Function for getting the next peer ID in the sequence of all peer IDs pending deletion.
+ *        Can be used to loop through all used peer IDs.
+ *
+ * @note @ref PM_PEER_ID_INVALID is considered to be before the first and after the last ordinary
+ *       peer ID.
+ *
+ * @param[in]  prev_peer_id  The previous peer ID.
+ *
+ * @return  The next peer ID pending deletion.
+ * @return  The first ordinary peer ID  if prev_peer_id was @ref PM_PEER_ID_INVALID.
+ * @retval  PM_PEER_ID_INVALID          if prev_peer_id was the last ordinary peer ID.
+ */
+pm_peer_id_t pdb_next_deleted_peer_id_get(pm_peer_id_t prev_peer_id);
+
+
+/**@brief Function for updating currently stored peer data to a new version
+ *
+ * @details Updating happens asynchronously.
+ *          Expect a @ref PDS_EVT_STORED or @ref PDS_EVT_ERROR_STORE for the store token
+ *          and a @ref PDS_EVT_ERROR_CLEAR or @ref PDS_EVT_ERROR_CLEAR for the old token
+ *
+ * @param[in]   peer_data           New data
+ * @param[in]   old_token           Store token for the old data
+ * @param[out]  p_store_token       Store token for the new data
+ *
+ * @retval NRF_SUCESS               The update was initiated successfully
+ * @retval NRF_ERROR_NOT_FOUND      The old store token was invalid.
+ * @retval NRF_ERROR_NULL           Data contained a NULL pointer.
+ * @retval NRF_ERROR_STORAGE_FULL   No space available in persistent storage.
+ * @retval NRF_ERROR_BUSY           FDS or underlying modules are busy and can't take any
+ *                                  more requests
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t pdb_peer_data_update(pm_peer_data_const_t        peer_data,
+                                pm_store_token_t            old_token,
+                                pm_store_token_t          * p_store_token);
+
+
+/**@brief Function for copy peer data from flash into a provided buffer.
+ *
+ * @param[in]    peer_id      The peer the data belongs to.
+ * @param[in]    data_id      The data to read.
+ * @param[inout] p_peer_data  The buffer where to copy data into. The field @c length_words in this
+ *                            parameter must represent the buffer length in words.
+ *
+ * @note Actually, it represents the buffer length in bytes upon entering the function,
+ * and upon exit it represents the length of the data in words.. not good. Fix this.
+ *
+ * @retval NRF_SUCCESS              If the operation was successful.
+ * @retval NRF_ERROR_INVALID_PARAM  If @p peer_id or @p data_id are invalid.
+ * @retval NRF_ERROR_NOT_FOUND      If the data was not found in flash.
+ * @retval NRF_ERROR_NO_MEM         If the provided buffer is too small.
+ */
+ret_code_t pdb_peer_data_load(pm_peer_id_t              peer_id,
+                              pm_peer_data_id_t         data_id,
+                              pm_peer_data_t    * const p_peer_data);
+
+
+/**@brief Function for writing data directly to persistent storage from external memory.
+ *
+ * @param[in]  peer_id        ID of peer to write data for.
+ * @param[in]  p_peer_data    Data to store.
+ * @param[out] p_store_token  A token identifying this particular store operation. The token can be
+ *                            used to identify events pertaining to this operation.
+ *
+ * @retval NRF_SUCCESS               Data successfully written.
+ * @retval NRF_ERROR_INVALID_PARAM   Data ID or Peer ID was invalid or unallocated.
+ * @retval NRF_ERROR_NULL            p_peer_data contained a NULL pointer.
+ * @retval NRF_ERROR_STORAGE_FULL    No space available in persistent storage.
+ * @retval NRF_ERROR_INVALID_LENGTH  Data length above the maximum allowed.
+ * @retval NRF_ERROR_BUSY            Unable to perform operation at this time.
+ */
+ret_code_t pdb_raw_store(pm_peer_id_t           peer_id,
+                         pm_peer_data_const_t * p_peer_data,
+                         pm_store_token_t     * p_store_token);
+
+/** @}
+ * @endcond
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PEER_DATABASE_H__ */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_id.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,201 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(PEER_MANAGER)
+#include "peer_id.h"
+
+#include <stdint.h>
+#include <string.h>
+#include "sdk_errors.h"
+#include "peer_manager_types.h"
+#include "pm_mutex.h"
+
+
+typedef struct
+{
+    uint8_t used_peer_ids[MUTEX_STORAGE_SIZE(PM_PEER_ID_N_AVAILABLE_IDS)];  /**< Bitmap designating which peer IDs are in use. */
+    uint8_t deleted_peer_ids[MUTEX_STORAGE_SIZE(PM_PEER_ID_N_AVAILABLE_IDS)]; /**< Bitmap designating which peer IDs are marked for deletion. */
+} pi_t;
+
+
+static pi_t m_pi = {{0}, {0}};
+
+
+static void internal_state_reset(pi_t * p_pi)
+{
+    memset(p_pi, 0, sizeof(pi_t));
+}
+
+
+void peer_id_init(void)
+{
+    internal_state_reset(&m_pi);
+    pm_mutex_init(m_pi.used_peer_ids, PM_PEER_ID_N_AVAILABLE_IDS);
+    pm_mutex_init(m_pi.deleted_peer_ids, PM_PEER_ID_N_AVAILABLE_IDS);
+}
+
+
+static pm_peer_id_t claim(pm_peer_id_t peer_id, uint8_t * mutex_group)
+{
+    pm_peer_id_t allocated_peer_id = PM_PEER_ID_INVALID;
+    if (peer_id == PM_PEER_ID_INVALID)
+    {
+        allocated_peer_id = pm_mutex_lock_first_available(mutex_group, PM_PEER_ID_N_AVAILABLE_IDS);
+        if (allocated_peer_id == PM_PEER_ID_N_AVAILABLE_IDS)
+        {
+            allocated_peer_id = PM_PEER_ID_INVALID;
+        }
+    }
+    else if (peer_id < PM_PEER_ID_N_AVAILABLE_IDS)
+    {
+        bool lock_success = pm_mutex_lock(mutex_group, peer_id);
+        allocated_peer_id = lock_success ? peer_id : PM_PEER_ID_INVALID;
+    }
+    return allocated_peer_id;
+}
+
+
+static void release(pm_peer_id_t peer_id, uint8_t * mutex_group)
+{
+    if (peer_id < PM_PEER_ID_N_AVAILABLE_IDS)
+    {
+        pm_mutex_unlock(mutex_group, peer_id);
+    }
+}
+
+
+pm_peer_id_t peer_id_allocate(pm_peer_id_t peer_id)
+{
+    return claim(peer_id, m_pi.used_peer_ids);
+}
+
+
+bool peer_id_delete(pm_peer_id_t peer_id)
+{
+    pm_peer_id_t deleted_peer_id;
+
+    if (peer_id == PM_PEER_ID_INVALID)
+    {
+        return false;
+    }
+
+    deleted_peer_id = claim(peer_id, m_pi.deleted_peer_ids);
+
+    return (deleted_peer_id == peer_id);
+}
+
+
+void peer_id_free(pm_peer_id_t peer_id)
+{
+    release(peer_id, m_pi.used_peer_ids);
+    release(peer_id, m_pi.deleted_peer_ids);
+}
+
+
+bool peer_id_is_allocated(pm_peer_id_t peer_id)
+{
+    if (peer_id < PM_PEER_ID_N_AVAILABLE_IDS)
+    {
+        return pm_mutex_lock_status_get(m_pi.used_peer_ids, peer_id);
+    }
+    return false;
+}
+
+
+bool peer_id_is_deleted(pm_peer_id_t peer_id)
+{
+    if (peer_id < PM_PEER_ID_N_AVAILABLE_IDS)
+    {
+        return pm_mutex_lock_status_get(m_pi.deleted_peer_ids, peer_id);
+    }
+    return false;
+}
+
+
+pm_peer_id_t next_id_get(pm_peer_id_t prev_peer_id, uint8_t * mutex_group)
+{
+    pm_peer_id_t i = (prev_peer_id == PM_PEER_ID_INVALID) ? 0 : (prev_peer_id + 1);
+    for (; i < PM_PEER_ID_N_AVAILABLE_IDS; i++)
+    {
+        if (pm_mutex_lock_status_get(mutex_group, i))
+        {
+            return i;
+        }
+    }
+
+    return PM_PEER_ID_INVALID;
+}
+
+
+pm_peer_id_t peer_id_get_next_used(pm_peer_id_t peer_id)
+{
+    peer_id = next_id_get(peer_id, m_pi.used_peer_ids);
+
+    while (peer_id != PM_PEER_ID_INVALID)
+    {
+        if (!peer_id_is_deleted(peer_id))
+        {
+            return peer_id;
+        }
+
+        peer_id = next_id_get(peer_id, m_pi.used_peer_ids);
+    }
+
+    return peer_id;
+}
+
+
+pm_peer_id_t peer_id_get_next_deleted(pm_peer_id_t prev_peer_id)
+{
+    return next_id_get(prev_peer_id, m_pi.deleted_peer_ids);
+}
+
+
+uint32_t peer_id_n_ids(void)
+{
+    uint32_t n_ids = 0;
+
+    for (pm_peer_id_t i = 0; i < PM_PEER_ID_N_AVAILABLE_IDS; i++)
+    {
+        n_ids += pm_mutex_lock_status_get(m_pi.used_peer_ids, i);
+    }
+
+    return n_ids;
+}
+#endif // NRF_MODULE_ENABLED(PEER_MANAGER)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_id.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,167 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef PEER_ID_H__
+#define PEER_ID_H__
+
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "ble_gap.h"
+#include "peer_manager_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup peer_id Peer IDs
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. This module keeps track of which peer IDs are in
+ *        use and which are free.
+ */
+
+
+/**@brief Function for initializing the module.
+ */
+void peer_id_init(void);
+
+
+/**@brief Function for claiming an unused peer ID.
+ *
+ * @param peer_id  The peer ID to allocate. If this is @ref PM_PEER_ID_INVALID, the first available
+ *                 will be allocated.
+ *
+ * @return  The allocated peer ID.
+ * @retval  PM_PEER_ID_INVALID  If no peer ID could be allocated or module is not initialized.
+ */
+pm_peer_id_t peer_id_allocate(pm_peer_id_t peer_id);
+
+
+/**@brief Function for marking a peer ID for deletion.
+ *
+ * @param peer_id  The peer ID to delete.
+ *
+ * @retval  true   Deletion was successful.
+ * @retval  false  Peer ID already marked for deletion, peer_id was PM_PEER_ID_INVALID, or module is
+ *                 not initialized.
+ */
+bool peer_id_delete(pm_peer_id_t peer_id);
+
+
+/**@brief Function for freeing a peer ID and clearing all data associated with it in persistent
+ *        storage.
+ *
+ * @param[in]  peer_id  Peer ID to free.
+ */
+void peer_id_free(pm_peer_id_t peer_id);
+
+
+/**@brief Function for finding out whether a peer ID is marked for deletion.
+ *
+ * @param[in]  peer_id  The peer ID to inquire about.
+ *
+ * @retval  true   peer_id is in marked for deletion.
+ * @retval  false  peer_id is not marked for deletion, or the module is not initialized.
+ */
+bool peer_id_is_deleted(pm_peer_id_t peer_id);
+
+
+/**@brief Function for finding out whether a peer ID is in use.
+ *
+ * @param[in]  peer_id  The peer ID to inquire about.
+ *
+ * @retval  true   peer_id is in use.
+ * @retval  false  peer_id is free, or the module is not initialized.
+ */
+bool peer_id_is_allocated(pm_peer_id_t peer_id);
+
+
+/**@brief Function for getting the next peer ID in the sequence of all used peer IDs. Can be
+ *        used to loop through all used peer IDs.
+ *
+ * @note @ref PM_PEER_ID_INVALID is considered to be before the first and after the last ordinary
+ *       peer ID.
+ *
+ * @param[in]  prev_peer_id  The previous peer ID.
+ *
+ * @return  The next peer ID.
+ * @return  The first used peer ID  if prev_peer_id was @ref PM_PEER_ID_INVALID.
+ * @retval  PM_PEER_ID_INVALID      if prev_peer_id was the last ordinary peer ID or the module is
+ *                                  not initialized.
+ */
+pm_peer_id_t peer_id_get_next_used(pm_peer_id_t prev_peer_id);
+
+
+/**@brief Function for getting the next peer ID in the sequence of all peer IDs marked for deletion.
+ *        Can be used to loop through all peer IDs marked for deletion.
+ *
+ * @note @ref PM_PEER_ID_INVALID is considered to be before the first and after the last ordinary
+ *       peer ID.
+ *
+ * @param[in]  prev_peer_id  The previous peer ID.
+ *
+ * @return  The next peer ID.
+ * @return  The first used peer ID  if prev_peer_id was @ref PM_PEER_ID_INVALID.
+ * @retval  PM_PEER_ID_INVALID      if prev_peer_id was the last ordinary peer ID or the module is
+ *                                  not initialized.
+ */
+pm_peer_id_t peer_id_get_next_deleted(pm_peer_id_t prev_peer_id);
+
+
+/**@brief Function for querying the number of valid peer IDs available. I.E the number of peers
+ *        in persistent storage.
+ *
+ * @return  The number of valid peer IDs, or 0 if module is not initialized.
+ */
+uint32_t peer_id_n_ids(void);
+
+/** @}
+ * @endcond
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PEER_ID_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_manager.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,1121 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(PEER_MANAGER)
+#include "peer_manager.h"
+#include <string.h>
+#include "security_manager.h"
+#include "security_dispatcher.h"
+#include "gatt_cache_manager.h"
+#include "gatts_cache_manager.h"
+#include "peer_database.h"
+#include "peer_data_storage.h"
+#include "id_manager.h"
+#include "ble_conn_state.h"
+#include "peer_manager_internal.h"
+
+
+/**< The number of event handlers that can be registered with the module. */
+#define MAX_REGISTRANTS         (3)
+/**< Macro indicating whether the module has been initialized properly. */
+#define MODULE_INITIALIZED      (m_module_initialized)
+
+
+static bool                          m_module_initialized;              /**< Whether or not @ref pm_init has been called successfully. */
+static bool                          m_peer_rank_initialized;           /**< Whether or not @ref rank_init has been called successfully. */
+static bool                          m_deleting_all;                    /**< True from when @ref pm_peers_delete is called until all peers have been deleted. */
+static pm_store_token_t              m_peer_rank_token;                 /**< The store token of an ongoing peer rank update via a call to @ref pm_peer_rank_highest. If @ref PM_STORE_TOKEN_INVALID, there is no ongoing update. */
+static uint32_t                      m_current_highest_peer_rank;       /**< The current highest peer rank. Used by @ref pm_peer_rank_highest. */
+static pm_peer_id_t                  m_highest_ranked_peer;             /**< The peer with the highest peer rank. Used by @ref pm_peer_rank_highest. */
+static pm_evt_handler_t              m_evt_handlers[MAX_REGISTRANTS];   /**< The subscribers to Peer Manager events, as registered through @ref pm_register. */
+static uint8_t                       m_n_registrants;                   /**< The number of event handlers registered through @ref pm_register. */
+static ble_conn_state_user_flag_id_t m_pairing_flag_id;                 /**< The flag ID for which connections are paired. */
+static ble_conn_state_user_flag_id_t m_bonding_flag_id;                 /**< The flag ID for which connections are bonded. */
+
+
+/**@brief Function for sending a Peer Manager event to all subscribers.
+ *
+ * @param[in]  p_pm_evt  The event to send.
+ */
+static void evt_send(pm_evt_t * p_pm_evt)
+{
+    for (int i = 0; i < m_n_registrants; i++)
+    {
+        m_evt_handlers[i](p_pm_evt);
+    }
+}
+
+
+/**@brief Event handler for events from the Peer Database module.
+ *        This handler is extern in the Peer Database module.
+ *
+ * @param[in]  p_pdb_evt  The incoming Peer Database event.
+ */
+void pm_pdb_evt_handler(pdb_evt_t const * p_pdb_evt)
+{
+    bool send_evt = true;
+    pm_evt_t pm_evt;
+
+    memset(&pm_evt, 0, sizeof(pm_evt_t));
+    pm_evt.peer_id = p_pdb_evt->peer_id;
+    pm_evt.conn_handle = im_conn_handle_get(pm_evt.peer_id);
+
+    switch (p_pdb_evt->evt_id)
+    {
+        case PDB_EVT_WRITE_BUF_STORED:
+            pm_evt.evt_id = PM_EVT_PEER_DATA_UPDATE_SUCCEEDED;
+            pm_evt.params.peer_data_update_succeeded.data_id       = p_pdb_evt->data_id;
+            pm_evt.params.peer_data_update_succeeded.action        = PM_PEER_DATA_OP_UPDATE;
+            pm_evt.params.peer_data_update_succeeded.token         = PM_STORE_TOKEN_INVALID;
+            pm_evt.params.peer_data_update_succeeded.flash_changed = true;
+            break;
+
+        case PDB_EVT_RAW_STORED:
+            pm_evt.evt_id = PM_EVT_PEER_DATA_UPDATE_SUCCEEDED;
+            pm_evt.params.peer_data_update_succeeded.data_id = p_pdb_evt->data_id;
+            pm_evt.params.peer_data_update_succeeded.action  = PM_PEER_DATA_OP_UPDATE;
+            pm_evt.params.peer_data_update_succeeded.token
+                                            = p_pdb_evt->params.raw_stored_evt.store_token;
+            pm_evt.params.peer_data_update_succeeded.flash_changed = true;
+
+            if (    (m_peer_rank_token != PM_STORE_TOKEN_INVALID)
+                && (m_peer_rank_token == p_pdb_evt->params.raw_stored_evt.store_token))
+            {
+                m_peer_rank_token     = PM_STORE_TOKEN_INVALID;
+                m_highest_ranked_peer = pm_evt.peer_id;
+
+                pm_evt.params.peer_data_update_succeeded.token = PM_STORE_TOKEN_INVALID;
+            }
+            break;
+
+        case PDB_EVT_RAW_STORE_FAILED:
+            pm_evt.evt_id = PM_EVT_PEER_DATA_UPDATE_FAILED;
+            pm_evt.params.peer_data_update_failed.data_id = p_pdb_evt->data_id;
+            pm_evt.params.peer_data_update_failed.action  = PM_PEER_DATA_OP_UPDATE;
+            pm_evt.params.peer_data_update_failed.token
+                                            = p_pdb_evt->params.error_raw_store_evt.store_token;
+            pm_evt.params.peer_data_update_failed.error
+                                            = p_pdb_evt->params.error_raw_store_evt.err_code;
+
+            if (    (m_peer_rank_token != PM_STORE_TOKEN_INVALID)
+                && (m_peer_rank_token == p_pdb_evt->params.raw_stored_evt.store_token))
+            {
+                m_peer_rank_token            = PM_STORE_TOKEN_INVALID;
+                m_current_highest_peer_rank -= 1;
+
+                pm_evt.params.peer_data_update_succeeded.token = PM_STORE_TOKEN_INVALID;
+            }
+            break;
+
+        case PDB_EVT_CLEARED:
+            pm_evt.evt_id = PM_EVT_PEER_DATA_UPDATE_SUCCEEDED;
+            pm_evt.params.peer_data_update_succeeded.data_id = p_pdb_evt->data_id;
+            pm_evt.params.peer_data_update_succeeded.action  = PM_PEER_DATA_OP_DELETE;
+            pm_evt.params.peer_data_update_succeeded.token   = PM_STORE_TOKEN_INVALID;
+            break;
+
+        case PDB_EVT_CLEAR_FAILED:
+            pm_evt.evt_id = PM_EVT_PEER_DATA_UPDATE_FAILED;
+            pm_evt.params.peer_data_update_failed.data_id = p_pdb_evt->data_id;
+            pm_evt.params.peer_data_update_failed.action  = PM_PEER_DATA_OP_DELETE;
+            pm_evt.params.peer_data_update_failed.error
+                                                    = p_pdb_evt->params.clear_failed_evt.err_code;
+            break;
+
+        case PDB_EVT_PEER_FREED:
+            pm_evt.evt_id = PM_EVT_PEER_DELETE_SUCCEEDED;
+            // Check that no peers marked for deletion are left.
+            if (m_deleting_all
+                && (pdb_next_peer_id_get(PM_PEER_ID_INVALID) == PM_PEER_ID_INVALID)
+                && (pdb_next_deleted_peer_id_get(PM_PEER_ID_INVALID) == PM_PEER_ID_INVALID))
+            {
+                // pm_peers_delete() has been called and this is the last peer to be deleted.
+                m_deleting_all = false;
+
+                pm_evt_t pm_delete_all_evt;
+                memset(&pm_delete_all_evt, 0, sizeof(pm_evt_t));
+                pm_delete_all_evt.evt_id      = PM_EVT_PEERS_DELETE_SUCCEEDED;
+                pm_delete_all_evt.peer_id     = PM_PEER_ID_INVALID;
+                pm_delete_all_evt.conn_handle = BLE_CONN_HANDLE_INVALID;
+
+                evt_send(&pm_delete_all_evt);
+            }
+            break;
+
+        case PDB_EVT_PEER_FREE_FAILED:
+            pm_evt.evt_id = PM_EVT_PEER_DELETE_FAILED;
+            pm_evt.params.peer_delete_failed.error
+                                                = p_pdb_evt->params.peer_free_failed_evt.err_code;
+            if (m_deleting_all)
+            {
+                // pm_peers_delete() has been called and has thus failed.
+
+                m_deleting_all = false;
+
+                pm_evt_t pm_delete_all_evt;
+                memset(&pm_delete_all_evt, 0, sizeof(pm_evt_t));
+                pm_delete_all_evt.evt_id      = PM_EVT_PEERS_DELETE_FAILED;
+                pm_delete_all_evt.peer_id     = PM_PEER_ID_INVALID;
+                pm_delete_all_evt.conn_handle = BLE_CONN_HANDLE_INVALID;
+                pm_delete_all_evt.params.peers_delete_failed_evt.error
+                                              = p_pdb_evt->params.peer_free_failed_evt.err_code;
+
+                evt_send(&pm_delete_all_evt);
+            }
+            break;
+
+        case PDB_EVT_COMPRESSED:
+            send_evt = false;
+            // Do nothing
+            break;
+
+        case PDB_EVT_ERROR_NO_MEM:
+            pm_evt.evt_id = PM_EVT_STORAGE_FULL;
+            break;
+
+        case PDB_EVT_ERROR_UNEXPECTED:
+            pm_evt.evt_id = PM_EVT_ERROR_UNEXPECTED;
+            break;
+
+        default:
+            send_evt = false;
+            break;
+    }
+
+    if (send_evt)
+    {
+        evt_send(&pm_evt);
+    }
+}
+
+
+/**@brief Event handler for events from the Security Manager module.
+ *        This handler is extern in the Security Manager module.
+ *
+ * @param[in]  p_sm_evt  The incoming Security Manager event.
+ */
+void pm_sm_evt_handler(sm_evt_t const * p_sm_evt)
+{
+    bool find_peer_id = true;
+    bool send_evt     = true;
+    pm_evt_t pm_evt;
+    memset(&pm_evt, 0, sizeof(pm_evt_t));
+    pm_evt.conn_handle = p_sm_evt->conn_handle;
+
+    switch (p_sm_evt->evt_id)
+    {
+        case SM_EVT_SLAVE_SECURITY_REQ:
+            find_peer_id = false;
+            send_evt     = false;
+            break;
+
+        case SM_EVT_SEC_PROCEDURE_START:
+        {
+            pm_evt.evt_id = PM_EVT_CONN_SEC_START;
+            bool pairing = p_sm_evt->params.sec_procedure_start.procedure
+                                != PM_LINK_SECURED_PROCEDURE_ENCRYPTION;
+            bool bonding = p_sm_evt->params.sec_procedure_start.procedure
+                                == PM_LINK_SECURED_PROCEDURE_BONDING;
+            ble_conn_state_user_flag_set(p_sm_evt->conn_handle, m_pairing_flag_id, pairing);
+            ble_conn_state_user_flag_set(p_sm_evt->conn_handle, m_bonding_flag_id, bonding);
+            break;
+        }
+
+        case SM_EVT_PAIRING_SUCCESS:
+            pm_evt.evt_id = PM_EVT_CONN_SEC_SUCCEEDED;
+            pm_evt.params.conn_sec_succeeded.procedure =
+                        p_sm_evt->params.pairing_success.bonded
+                        ? PM_LINK_SECURED_PROCEDURE_BONDING
+                        : PM_LINK_SECURED_PROCEDURE_PAIRING;
+            ble_conn_state_user_flag_set(p_sm_evt->conn_handle, m_pairing_flag_id, true);
+            ble_conn_state_user_flag_set(p_sm_evt->conn_handle,
+                                         m_bonding_flag_id,
+                                         p_sm_evt->params.pairing_success.bonded
+            );
+            break;
+
+        case SM_EVT_PAIRING_FAIL:
+            pm_evt.evt_id = PM_EVT_CONN_SEC_FAILED;
+            pm_evt.params.conn_sec_failed.procedure =
+                        ble_conn_state_user_flag_get(p_sm_evt->conn_handle, m_bonding_flag_id)
+                        ? PM_LINK_SECURED_PROCEDURE_BONDING
+                        : PM_LINK_SECURED_PROCEDURE_PAIRING;
+            pm_evt.params.conn_sec_failed.error_src
+                = p_sm_evt->params.pairing_failed.error_src;
+            pm_evt.params.conn_sec_failed.error
+                = p_sm_evt->params.pairing_failed.error;
+            break;
+
+        case SM_EVT_LINK_ENCRYPTION_UPDATE:
+            if (!ble_conn_state_user_flag_get(p_sm_evt->conn_handle, m_pairing_flag_id))
+            {
+                pm_evt.evt_id = PM_EVT_CONN_SEC_SUCCEEDED;
+                pm_evt.params.conn_sec_succeeded.procedure = PM_LINK_SECURED_PROCEDURE_ENCRYPTION;
+            }
+            else
+            {
+                find_peer_id = false;
+                send_evt     = false;
+            }
+            break;
+
+        case SM_EVT_LINK_ENCRYPTION_FAILED:
+            pm_evt.evt_id = PM_EVT_CONN_SEC_FAILED;
+            pm_evt.params.conn_sec_failed.procedure
+                            = PM_LINK_SECURED_PROCEDURE_ENCRYPTION;
+            pm_evt.params.conn_sec_failed.error_src
+                            = p_sm_evt->params.link_encryption_failed.error_src;
+            pm_evt.params.conn_sec_failed.error
+                            = p_sm_evt->params.link_encryption_failed.error;
+            break;
+
+        case SM_EVT_BONDING_INFO_STORED:
+            pm_evt.evt_id  = PM_EVT_PEER_DATA_UPDATE_SUCCEEDED;
+            pm_evt.peer_id = p_sm_evt->params.bonding_info_stored.peer_id;
+            pm_evt.params.peer_data_update_succeeded.data_id = PM_PEER_DATA_ID_BONDING;
+            pm_evt.params.peer_data_update_succeeded.action  = PM_PEER_DATA_OP_UPDATE;
+            find_peer_id = false;
+            break;
+
+        case SM_EVT_ERROR_BONDING_INFO:
+            pm_evt.evt_id = PM_EVT_PEER_DATA_UPDATE_FAILED;
+            pm_evt.peer_id = p_sm_evt->params.error_bonding_info.peer_id;
+            pm_evt.params.peer_data_update_failed.data_id = PM_PEER_DATA_ID_BONDING;
+            pm_evt.params.peer_data_update_failed.action  = PM_PEER_DATA_OP_UPDATE;
+            pm_evt.params.peer_data_update_failed.error
+                = p_sm_evt->params.error_bonding_info.error;
+            find_peer_id = false;
+            break;
+
+        case SM_EVT_ERROR_UNEXPECTED:
+            pm_evt.evt_id = PM_EVT_ERROR_UNEXPECTED;
+            pm_evt.params.error_unexpected.error = p_sm_evt->params.error_unexpected.error;
+            break;
+
+        case SM_EVT_ERROR_NO_MEM:
+            pm_evt.evt_id = PM_EVT_STORAGE_FULL;
+            break;
+
+        case SM_EVT_ERROR_SMP_TIMEOUT:
+            pm_evt.evt_id = PM_EVT_CONN_SEC_FAILED;
+            pm_evt.params.conn_sec_failed.procedure
+                        = ble_conn_state_user_flag_get(p_sm_evt->conn_handle, m_bonding_flag_id)
+                        ? PM_LINK_SECURED_PROCEDURE_BONDING
+                        : PM_LINK_SECURED_PROCEDURE_PAIRING;
+            pm_evt.params.conn_sec_failed.error_src  = BLE_GAP_SEC_STATUS_SOURCE_LOCAL;
+            pm_evt.params.conn_sec_failed.error      = PM_CONN_SEC_ERROR_SMP_TIMEOUT;
+            break;
+
+        case SM_EVT_CONN_SEC_CONFIG_REQ:
+            pm_evt.evt_id = PM_EVT_CONN_SEC_CONFIG_REQ;
+            break;
+
+        default:
+            send_evt = false;
+            break;
+    }
+
+    if (find_peer_id)
+    {
+        pm_evt.peer_id = im_peer_id_get_by_conn_handle(p_sm_evt->conn_handle);
+    }
+
+    if (send_evt)
+    {
+        evt_send(&pm_evt);
+    }
+}
+
+
+/**@brief Event handler for events from the GATT Cache Manager module.
+ *        This handler is extern in GATT Cache Manager.
+ *
+ * @param[in]  p_gcm_evt  The incoming GATT Cache Manager event.
+ */
+void pm_gcm_evt_handler(gcm_evt_t const * p_gcm_evt)
+{
+    bool send_evt = true;
+    pm_evt_t pm_evt;
+
+    memset(&pm_evt, 0, sizeof(pm_evt_t));
+    pm_evt.peer_id = p_gcm_evt->peer_id;
+    pm_evt.conn_handle = im_conn_handle_get(pm_evt.peer_id);
+
+    switch (p_gcm_evt->evt_id)
+    {
+        case GCM_EVT_LOCAL_DB_CACHE_STORED:
+            pm_evt.evt_id = PM_EVT_PEER_DATA_UPDATE_SUCCEEDED;
+            pm_evt.params.peer_data_update_succeeded.action = PM_PEER_DATA_OP_UPDATE;
+            pm_evt.params.peer_data_update_succeeded.data_id =  PM_PEER_DATA_ID_GATT_LOCAL;
+            break;
+
+        case GCM_EVT_LOCAL_DB_CACHE_UPDATED:
+            pm_evt.evt_id = PM_EVT_PEER_DATA_UPDATE_SUCCEEDED;
+            pm_evt.params.peer_data_update_succeeded.action = PM_PEER_DATA_OP_UPDATE;
+            pm_evt.params.peer_data_update_succeeded.data_id =  PM_PEER_DATA_ID_GATT_LOCAL;
+            break;
+
+        case GCM_EVT_LOCAL_DB_CACHE_APPLIED:
+            pm_evt.evt_id = PM_EVT_LOCAL_DB_CACHE_APPLIED;
+            break;
+
+        case GCM_EVT_ERROR_LOCAL_DB_CACHE_APPLY:
+            pm_evt.evt_id = PM_EVT_LOCAL_DB_CACHE_APPLY_FAILED;
+            break;
+
+        case GCM_EVT_REMOTE_DB_CACHE_UPDATED:
+            pm_evt.evt_id = PM_EVT_PEER_DATA_UPDATE_SUCCEEDED;
+            pm_evt.params.peer_data_update_succeeded.action = PM_PEER_DATA_OP_UPDATE;
+            pm_evt.params.peer_data_update_succeeded.data_id =  PM_PEER_DATA_ID_GATT_REMOTE;
+            break;
+
+        case GCM_EVT_SERVICE_CHANGED_IND_SENT:
+            pm_evt.evt_id = PM_EVT_SERVICE_CHANGED_IND_SENT;
+            break;
+
+        case GCM_EVT_SERVICE_CHANGED_IND_CONFIRMED:
+            pm_evt.evt_id = PM_EVT_SERVICE_CHANGED_IND_CONFIRMED;
+            break;
+
+        case GCM_EVT_ERROR_DATA_SIZE:
+            send_evt = false;
+            break;
+
+        case GCM_EVT_ERROR_STORAGE_FULL:
+            pm_evt.evt_id = PM_EVT_STORAGE_FULL;
+            break;
+
+        case GCM_EVT_ERROR_UNEXPECTED:
+            pm_evt.evt_id = PM_EVT_ERROR_UNEXPECTED;
+            pm_evt.params.error_unexpected.error = p_gcm_evt->params.error_unexpected.error;
+            pm_evt.conn_handle = p_gcm_evt->params.error_unexpected.conn_handle;
+            break;
+    }
+
+    if (send_evt)
+    {
+        evt_send(&pm_evt);
+    }
+}
+
+
+/**@brief Event handler for events from the ID Manager module.
+ *        This function is registered in the ID Manager.
+ *
+ * @param[in]  p_im_evt  The incoming ID Manager event.
+ */
+void pm_im_evt_handler(im_evt_t const * p_im_evt)
+{
+    pm_evt_t pm_evt;
+    ret_code_t err_code;
+
+    switch (p_im_evt->evt_id)
+    {
+        case IM_EVT_DUPLICATE_ID:
+            // Attempt to delete the duplicate data to free space and avoid finding old data when
+            // scanning in the future
+            err_code = pm_peer_delete(p_im_evt->params.duplicate_id.peer_id_2);
+            UNUSED_VARIABLE(err_code);
+            break;
+
+        case IM_EVT_BONDED_PEER_CONNECTED:
+            ble_conn_state_user_flag_set(p_im_evt->conn_handle, m_bonding_flag_id, true);
+            memset(&pm_evt, 0, sizeof(pm_evt_t));
+            pm_evt.conn_handle = p_im_evt->conn_handle;
+            pm_evt.peer_id = im_peer_id_get_by_conn_handle(p_im_evt->conn_handle);
+            pm_evt.evt_id = PM_EVT_BONDED_PEER_CONNECTED;
+            evt_send(&pm_evt);
+            break;
+    }
+}
+
+
+void pm_on_ble_evt(ble_evt_t * p_ble_evt)
+{
+    VERIFY_MODULE_INITIALIZED_VOID();
+
+    im_ble_evt_handler(p_ble_evt);
+    sm_ble_evt_handler(p_ble_evt);
+    gcm_ble_evt_handler(p_ble_evt);
+}
+
+
+/**@brief Function for resetting the internal state of this module.
+ */
+static void internal_state_reset()
+{
+    m_highest_ranked_peer = PM_PEER_ID_INVALID;
+    m_peer_rank_token     = PM_STORE_TOKEN_INVALID;
+    m_pairing_flag_id     = BLE_CONN_STATE_USER_FLAG_INVALID;
+    m_bonding_flag_id     = BLE_CONN_STATE_USER_FLAG_INVALID;
+}
+
+
+ret_code_t pm_init(void)
+{
+    ret_code_t err_code;
+
+    err_code = pds_init();
+    if (err_code != NRF_SUCCESS)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    err_code = pdb_init();
+    if (err_code != NRF_SUCCESS)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    err_code = sm_init();
+    if (err_code != NRF_SUCCESS)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    err_code = smd_init();
+    if (err_code != NRF_SUCCESS)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    err_code = gcm_init();
+    if (err_code != NRF_SUCCESS)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    err_code = gscm_init();
+    if (err_code != NRF_SUCCESS)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    err_code = im_init();
+    if (err_code != NRF_SUCCESS)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    internal_state_reset();
+
+    m_pairing_flag_id = ble_conn_state_user_flag_acquire();
+    if (m_pairing_flag_id == BLE_CONN_STATE_USER_FLAG_INVALID)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    m_bonding_flag_id = ble_conn_state_user_flag_acquire();
+    if (m_bonding_flag_id == BLE_CONN_STATE_USER_FLAG_INVALID)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    m_peer_rank_initialized = false;
+    m_module_initialized    = true;
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pm_register(pm_evt_handler_t event_handler)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    if (m_n_registrants >= MAX_REGISTRANTS)
+    {
+        return NRF_ERROR_NO_MEM;
+    }
+
+    m_evt_handlers[m_n_registrants] = event_handler;
+    m_n_registrants += 1;
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pm_sec_params_set(ble_gap_sec_params_t * p_sec_params)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    ret_code_t err_code;
+
+    err_code = sm_sec_params_set(p_sec_params);
+
+    // NRF_ERROR_INVALID_PARAM if parameters are invalid,
+    // NRF_SUCCESS             otherwise.
+    return err_code;
+}
+
+
+ret_code_t pm_conn_secure(uint16_t conn_handle, bool force_repairing)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    ret_code_t err_code;
+
+    err_code = sm_link_secure(conn_handle, force_repairing);
+
+    return err_code;
+}
+
+
+void pm_conn_sec_config_reply(uint16_t conn_handle, pm_conn_sec_config_t * p_conn_sec_config)
+{
+    sm_conn_sec_config_reply(conn_handle, p_conn_sec_config);
+}
+
+
+ret_code_t pm_sec_params_reply(uint16_t conn_handle, ble_gap_sec_params_t * p_sec_params)
+{
+    VERIFY_MODULE_INITIALIZED();
+    return NRF_SUCCESS;
+}
+
+
+void pm_local_database_has_changed(void)
+{
+    VERIFY_MODULE_INITIALIZED_VOID();
+    gcm_local_database_has_changed();
+}
+
+
+ret_code_t pm_id_addr_set(ble_gap_addr_t const * p_addr)
+{
+    VERIFY_MODULE_INITIALIZED();
+    return im_id_addr_set(p_addr);
+}
+
+
+ret_code_t pm_id_addr_get(ble_gap_addr_t * p_addr)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_addr);
+    return im_id_addr_get(p_addr);
+}
+
+
+ret_code_t pm_privacy_set(pm_privacy_params_t const * p_privacy_params)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_privacy_params);
+    return im_privacy_set(p_privacy_params);
+}
+
+
+ret_code_t pm_privacy_get(pm_privacy_params_t * p_privacy_params)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_privacy_params);
+    VERIFY_PARAM_NOT_NULL(p_privacy_params->p_device_irk);
+    return im_privacy_get(p_privacy_params);
+}
+
+
+ret_code_t pm_whitelist_set(pm_peer_id_t const * p_peers,
+                            uint32_t             peer_cnt)
+{
+    VERIFY_MODULE_INITIALIZED();
+    return im_whitelist_set(p_peers, peer_cnt);
+}
+
+
+ret_code_t pm_whitelist_get(ble_gap_addr_t * p_addrs,
+                            uint32_t       * p_addr_cnt,
+                            ble_gap_irk_t  * p_irks,
+                            uint32_t       * p_irk_cnt)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    if (((p_addrs == NULL) && (p_irks     == NULL)) ||
+        ((p_addrs != NULL) && (p_addr_cnt == NULL)) ||
+        ((p_irks  != NULL) && (p_irk_cnt  == NULL)))
+    {
+        // The buffers can't be both NULL, and if a buffer is provided its size must be specified.
+        return NRF_ERROR_NULL;
+    }
+
+    return im_whitelist_get(p_addrs, p_addr_cnt, p_irks, p_irk_cnt);
+}
+
+
+ret_code_t pm_device_identities_list_set(pm_peer_id_t const * p_peers,
+                                         uint32_t             peer_cnt)
+{
+    VERIFY_MODULE_INITIALIZED();
+    return im_device_identities_list_set(p_peers, peer_cnt);
+}
+
+
+ret_code_t pm_conn_sec_status_get(uint16_t conn_handle, pm_conn_sec_status_t * p_conn_sec_status)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_conn_sec_status);
+
+    ble_conn_state_status_t status = ble_conn_state_status(conn_handle);
+
+    if (status == BLE_CONN_STATUS_INVALID)
+    {
+        return BLE_ERROR_INVALID_CONN_HANDLE;
+    }
+
+    p_conn_sec_status->connected      = (status == BLE_CONN_STATUS_CONNECTED);
+    p_conn_sec_status->bonded         = ble_conn_state_user_flag_get(conn_handle, m_bonding_flag_id);
+    p_conn_sec_status->encrypted      = ble_conn_state_encrypted(conn_handle);
+    p_conn_sec_status->mitm_protected = ble_conn_state_mitm_protected(conn_handle);
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pm_lesc_public_key_set(ble_gap_lesc_p256_pk_t * p_public_key)
+{
+    VERIFY_MODULE_INITIALIZED();
+    return sm_lesc_public_key_set(p_public_key);
+}
+
+
+ret_code_t pm_conn_handle_get(pm_peer_id_t peer_id, uint16_t * p_conn_handle)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_conn_handle);
+    *p_conn_handle = im_conn_handle_get(peer_id);
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pm_peer_id_get(uint16_t conn_handle, pm_peer_id_t * p_peer_id)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_peer_id);
+    *p_peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+    return NRF_SUCCESS;
+}
+
+
+uint32_t pm_peer_count(void)
+{
+    if (!MODULE_INITIALIZED)
+    {
+        return 0;
+    }
+    return pdb_n_peers();
+}
+
+
+pm_peer_id_t pm_next_peer_id_get(pm_peer_id_t prev_peer_id)
+{
+    if (!MODULE_INITIALIZED)
+    {
+        return PM_PEER_ID_INVALID;
+    }
+    return pdb_next_peer_id_get(prev_peer_id);
+}
+
+
+ret_code_t pm_peer_data_load(pm_peer_id_t       peer_id,
+                             pm_peer_data_id_t  data_id,
+                             void             * p_data,
+                             uint16_t         * p_length)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_data);
+    VERIFY_PARAM_NOT_NULL(p_length);
+    if (ALIGN_NUM(4, *p_length) != *p_length)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    pm_peer_data_t peer_data;
+    memset(&peer_data, 0, sizeof(peer_data));
+    peer_data.length_words = BYTES_TO_WORDS(*p_length);
+    peer_data.data_id      = data_id;
+    peer_data.p_all_data   = p_data;
+
+    ret_code_t err_code = pdb_peer_data_load(peer_id, data_id, &peer_data);
+
+    *p_length = peer_data.length_words * BYTES_PER_WORD;
+
+    return err_code;
+}
+
+
+ret_code_t pm_peer_data_bonding_load(pm_peer_id_t             peer_id,
+                                     pm_peer_data_bonding_t * p_data)
+{
+    uint16_t length = sizeof(pm_peer_data_bonding_t);
+    return pm_peer_data_load(peer_id,
+                             PM_PEER_DATA_ID_BONDING,
+                             p_data,
+                             &length);
+}
+
+
+ret_code_t pm_peer_data_remote_db_load(pm_peer_id_t        peer_id,
+                                       ble_gatt_db_srv_t * p_data,
+                                       uint16_t          * p_length)
+{
+    return pm_peer_data_load(peer_id,
+                             PM_PEER_DATA_ID_GATT_REMOTE,
+                             p_data,
+                             p_length);
+}
+
+
+ret_code_t pm_peer_data_app_data_load(pm_peer_id_t       peer_id,
+                                      uint8_t          * p_data,
+                                      uint16_t         * p_length)
+{
+    return pm_peer_data_load(peer_id,
+                             PM_PEER_DATA_ID_APPLICATION,
+                             p_data,
+                             p_length);
+}
+
+
+ret_code_t pm_peer_data_store(pm_peer_id_t       peer_id,
+                              pm_peer_data_id_t  data_id,
+                              void       const * p_data,
+                              uint16_t           length,
+                              pm_store_token_t * p_token)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_data);
+    if (ALIGN_NUM(4, length) != length)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    pm_peer_data_flash_t peer_data;
+    memset(&peer_data, 0, sizeof(peer_data));
+    peer_data.length_words = BYTES_TO_WORDS(length);
+    peer_data.data_id      = data_id;
+    peer_data.p_all_data   = p_data;
+
+    return pdb_raw_store(peer_id, &peer_data, p_token);
+}
+
+
+ret_code_t pm_peer_data_bonding_store(pm_peer_id_t                   peer_id,
+                                      pm_peer_data_bonding_t const * p_data,
+                                      pm_store_token_t             * p_token)
+{
+    return pm_peer_data_store(peer_id,
+                              PM_PEER_DATA_ID_BONDING,
+                              p_data,
+                              ALIGN_NUM(4, sizeof(pm_peer_data_bonding_t)),
+                              p_token);
+}
+
+
+ret_code_t pm_peer_data_remote_db_store(pm_peer_id_t              peer_id,
+                                        ble_gatt_db_srv_t const * p_data,
+                                        uint16_t                  length,
+                                        pm_store_token_t        * p_token)
+{
+    return pm_peer_data_store(peer_id,
+                              PM_PEER_DATA_ID_GATT_REMOTE,
+                              p_data,
+                              length,
+                              p_token);
+}
+
+
+ret_code_t pm_peer_data_app_data_store(pm_peer_id_t       peer_id,
+                                       uint8_t    const * p_data,
+                                       uint16_t           length,
+                                       pm_store_token_t * p_token)
+{
+    return pm_peer_data_store(peer_id,
+                              PM_PEER_DATA_ID_APPLICATION,
+                              p_data,
+                              length,
+                              p_token);
+}
+
+
+ret_code_t pm_peer_data_delete(pm_peer_id_t peer_id, pm_peer_data_id_t data_id)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    if (data_id == PM_PEER_DATA_ID_BONDING)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    return pdb_clear(peer_id, data_id);
+}
+
+
+ret_code_t pm_peer_new(pm_peer_id_t           * p_new_peer_id,
+                       pm_peer_data_bonding_t * p_bonding_data,
+                       pm_store_token_t       * p_token)
+{
+    ret_code_t           err_code;
+    pm_peer_id_t         peer_id;
+    pm_peer_data_flash_t peer_data;
+
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_bonding_data);
+    VERIFY_PARAM_NOT_NULL(p_new_peer_id);
+
+    memset(&peer_data, 0, sizeof(pm_peer_data_flash_t));
+
+    // Search through existing bonds to look for a duplicate.
+    pds_peer_data_iterate_prepare();
+
+    // @note emdi: should maybe use a critical section, since data is not copied while iterating.
+    while (pds_peer_data_iterate(PM_PEER_DATA_ID_BONDING, &peer_id, &peer_data))
+    {
+        if (im_is_duplicate_bonding_data(p_bonding_data, peer_data.p_bonding_data))
+        {
+            *p_new_peer_id = peer_id;
+            return NRF_SUCCESS;
+        }
+    }
+
+    // If no duplicate data is found, prepare to write a new bond to flash.
+
+    *p_new_peer_id = pdb_peer_allocate();
+
+    if (*p_new_peer_id == PM_PEER_ID_INVALID)
+    {
+        return NRF_ERROR_NO_MEM;
+    }
+
+    memset(&peer_data, 0, sizeof(pm_peer_data_flash_t));
+
+    peer_data.data_id        = PM_PEER_DATA_ID_BONDING;
+    peer_data.p_bonding_data = p_bonding_data;
+    peer_data.length_words   = BYTES_TO_WORDS(sizeof(pm_peer_data_bonding_t));
+
+    err_code = pdb_raw_store(*p_new_peer_id, &peer_data, p_token);
+
+    if (err_code != NRF_SUCCESS)
+    {
+        if (im_peer_free(*p_new_peer_id) != NRF_SUCCESS)
+        {
+            return NRF_ERROR_INTERNAL;
+        }
+
+        // NRF_ERROR_STORAGE_FULL, if no space in flash.
+        // NRF_ERROR_BUSY,         if flash filesystem was busy.
+        // NRF_ERROR_INTENRAL,     on internal error.
+        return err_code;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pm_peer_delete(pm_peer_id_t peer_id)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    return im_peer_free(peer_id);
+}
+
+
+ret_code_t pm_peers_delete(void)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    m_deleting_all = true;
+
+    pm_peer_id_t current_peer_id = pdb_next_peer_id_get(PM_PEER_ID_INVALID);
+    while (current_peer_id != PM_PEER_ID_INVALID)
+    {
+        ret_code_t err_code = pm_peer_delete(current_peer_id);
+        if (err_code != NRF_SUCCESS)
+        {
+            return NRF_ERROR_INTERNAL;
+        }
+
+        current_peer_id = pdb_next_peer_id_get(current_peer_id);
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pm_peer_ranks_get(pm_peer_id_t * p_highest_ranked_peer,
+                             uint32_t     * p_highest_rank,
+                             pm_peer_id_t * p_lowest_ranked_peer,
+                             uint32_t     * p_lowest_rank)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    pm_peer_id_t         peer_id      = pdb_next_peer_id_get(PM_PEER_ID_INVALID);
+    uint32_t             peer_rank    = 0;
+    //lint -save -e65 -e64
+    pm_peer_data_t       peer_data    = {.length_words = BYTES_TO_WORDS(sizeof(peer_rank)),
+                                         .p_peer_rank  = &peer_rank};
+    //lint -restore
+    ret_code_t           err_code     = pdb_peer_data_load(peer_id, PM_PEER_DATA_ID_PEER_RANK, &peer_data);
+    uint32_t             highest_rank = 0;
+    uint32_t             lowest_rank  = 0xFFFFFFFF;
+    pm_peer_id_t         highest_ranked_peer = PM_PEER_ID_INVALID;
+    pm_peer_id_t         lowest_ranked_peer  = PM_PEER_ID_INVALID;
+
+    if (err_code == NRF_ERROR_INVALID_PARAM)
+    {
+        // No peer IDs exist.
+        return NRF_ERROR_NOT_FOUND;
+    }
+
+    while ((err_code == NRF_SUCCESS) || (err_code == NRF_ERROR_NOT_FOUND))
+    {
+        if (err_code == NRF_ERROR_NOT_FOUND)
+        {
+            peer_rank = 0;
+        }
+        if (peer_rank >= highest_rank)
+        {
+            highest_rank      = peer_rank;
+            highest_ranked_peer = peer_id;
+        }
+        if (peer_rank < lowest_rank)
+        {
+            lowest_rank      = peer_rank;
+            lowest_ranked_peer = peer_id;
+        }
+        peer_id = pdb_next_peer_id_get(peer_id);
+        err_code = pdb_peer_data_load(peer_id, PM_PEER_DATA_ID_PEER_RANK, &peer_data);
+    }
+    if (peer_id == PM_PEER_ID_INVALID)
+    {
+        err_code = NRF_SUCCESS;
+        if (p_highest_ranked_peer != NULL)
+        {
+            *p_highest_ranked_peer = highest_ranked_peer;
+        }
+        if (p_highest_rank != NULL)
+        {
+            *p_highest_rank = highest_rank;
+        }
+        if (p_lowest_ranked_peer != NULL)
+        {
+            *p_lowest_ranked_peer = lowest_ranked_peer;
+        }
+        if (p_lowest_rank != NULL)
+        {
+            *p_lowest_rank = lowest_rank;
+        }
+    }
+    else
+    {
+        err_code = NRF_ERROR_INTERNAL;
+    }
+    return err_code;
+}
+
+
+/**@brief Function for initializing peer rank statistics.
+ */
+static void rank_init(void)
+{
+    ret_code_t err_code = pm_peer_ranks_get(&m_highest_ranked_peer,
+                                            &m_current_highest_peer_rank,
+                                            NULL,
+                                            NULL);
+    if ((err_code == NRF_SUCCESS) || (err_code == NRF_ERROR_NOT_FOUND))
+    {
+        m_peer_rank_initialized = true;
+    }
+}
+
+
+ret_code_t pm_peer_rank_highest(pm_peer_id_t peer_id)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    ret_code_t err_code;
+    //lint -save -e65 -e64
+    pm_peer_data_flash_t peer_data   = {.length_words = BYTES_TO_WORDS(sizeof(m_current_highest_peer_rank)),
+                                        .data_id      = PM_PEER_DATA_ID_PEER_RANK,
+                                        .p_peer_rank  = &m_current_highest_peer_rank};
+    //lint -restore
+
+
+    if (!m_peer_rank_initialized)
+    {
+        rank_init();
+    }
+
+    if (!m_peer_rank_initialized || (m_peer_rank_token != PM_STORE_TOKEN_INVALID))
+    {
+        err_code = NRF_ERROR_BUSY;
+    }
+    else
+    {
+        if ((peer_id == m_highest_ranked_peer) && (m_current_highest_peer_rank > 0))
+        {
+            pm_evt_t pm_evt;
+
+            // The reported peer is already regarded as highest (provided it has an index at all)
+            err_code = NRF_SUCCESS;
+
+            memset(&pm_evt, 0, sizeof(pm_evt));
+            pm_evt.evt_id      = PM_EVT_PEER_DATA_UPDATE_SUCCEEDED;
+            pm_evt.conn_handle = im_conn_handle_get(peer_id);
+            pm_evt.peer_id     = peer_id;
+            pm_evt.params.peer_data_update_succeeded.data_id       = PM_PEER_DATA_ID_PEER_RANK;
+            pm_evt.params.peer_data_update_succeeded.action        = PM_PEER_DATA_OP_UPDATE;
+            pm_evt.params.peer_data_update_succeeded.token         = PM_STORE_TOKEN_INVALID;
+            pm_evt.params.peer_data_update_succeeded.flash_changed = false;
+
+            evt_send(&pm_evt);
+        }
+        else
+        {
+            m_current_highest_peer_rank += 1;
+            err_code = pdb_raw_store(peer_id, &peer_data, &m_peer_rank_token);
+            if (err_code != NRF_SUCCESS)
+            {
+                m_peer_rank_token    = PM_STORE_TOKEN_INVALID;
+                m_current_highest_peer_rank -= 1;
+                {
+                if ((err_code != NRF_ERROR_BUSY) && (err_code != NRF_ERROR_STORAGE_FULL))
+                    err_code = NRF_ERROR_INTERNAL;
+                }
+            }
+        }
+    }
+    return err_code;
+}
+#endif // NRF_MODULE_ENABLED(PEER_MANAGER)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_manager.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,858 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+ * @file peer_manager.h
+ *
+ * @defgroup peer_manager Peer Manager
+ * @ingroup ble_sdk_lib
+ * @{
+ * @brief Module for managing BLE bonding, which includes controlling encryption and pairing
+ *        procedures as well as persistently storing different pieces of data that must be stored
+ *        when bonded.
+ *
+ * @details The API consists of functions for configuring the pairing and encryption behavior of the
+ *          device and functions for manipulating the stored data.
+ *
+ *          This module uses Flash Data Storage (FDS) to interface with persistent storage. The
+ *          Peer Manager needs exclusive use of certain FDS file IDs and record keys. See 
+ *          @ref lib_fds_functionality_keys for more information.
+ */
+
+
+#ifndef PEER_MANAGER_H__
+#define PEER_MANAGER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "sdk_common.h"
+#include "headers/ble.h"
+#include "ble_gap.h"
+#include "peer_manager_types.h"
+#include "peer_database.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+/**@brief Security status of a connection.
+ */
+typedef struct
+{
+    uint8_t connected      : 1; /**< @brief The connection is active (not disconnected). */
+    uint8_t encrypted      : 1; /**< @brief Communication on this link is encrypted. */
+    uint8_t mitm_protected : 1; /**< @brief The encrypted communication is also protected against man-in-the-middle attacks. */
+    uint8_t bonded         : 1; /**< @brief The peer is bonded with us. */
+} pm_conn_sec_status_t;
+
+
+/**@brief Types of events that can come from the @ref peer_manager module.
+ */
+typedef enum
+{
+    PM_EVT_BONDED_PEER_CONNECTED,           /**< @brief A connected peer has been identified as one with which we have a bond. When performing bonding with a peer for the first time, this event will not be sent until a new connection is established with the peer. When we are central, this event is always sent when the Peer Manager receives the @ref BLE_GAP_EVT_CONNECTED event. When we are peripheral, this event might in rare cases arrive later. */
+    PM_EVT_CONN_SEC_START,                  /**< @brief A security procedure has started on a link, initiated either locally or remotely. The security procedure is using the last parameters provided via @ref pm_sec_params_set. This event is always followed by either a @ref PM_EVT_CONN_SEC_SUCCEEDED or a @ref PM_EVT_CONN_SEC_FAILED event. This is an informational event; no action is needed for the procedure to proceed. */
+    PM_EVT_CONN_SEC_SUCCEEDED,              /**< @brief A link has been encrypted, either as a result of a call to @ref pm_conn_secure or a result of an action by the peer. The event structure contains more information about the circumstances. This event might contain a peer ID with the value @ref PM_PEER_ID_INVALID, which means that the peer (central) used an address that could not be identified, but it used an encryption key (LTK) that is present in the database. */
+    PM_EVT_CONN_SEC_FAILED,                 /**< @brief A pairing or encryption procedure has failed. In some cases, this means that security is not possible on this link (temporarily or permanently). How to handle this error depends on the application. */
+    PM_EVT_CONN_SEC_CONFIG_REQ,             /**< @brief The peer (central) has requested pairing, but a bond already exists with that peer. Reply by calling @ref pm_conn_sec_config_reply before the event handler returns. If no reply is sent, a default is used. */
+    PM_EVT_STORAGE_FULL,                    /**< @brief There is no more room for peer data in flash storage. To solve this problem, delete data that is not needed anymore and run a garbage collection procedure in FDS. */
+    PM_EVT_ERROR_UNEXPECTED,                /**< @brief An unrecoverable error happened inside Peer Manager. An operation failed with the provided error. */
+    PM_EVT_PEER_DATA_UPDATE_SUCCEEDED,      /**< @brief A piece of peer data was stored, updated, or cleared in flash storage. This event is sent for all successful changes to peer data, also those initiated internally in Peer Manager. To identify an operation, compare the store token in the event with the store token received during the initiating function call. Events from internally initiated changes might have invalid store tokens. */
+    PM_EVT_PEER_DATA_UPDATE_FAILED,         /**< @brief A piece of peer data could not be stored, updated, or cleared in flash storage. This event is sent instead of @ref PM_EVT_PEER_DATA_UPDATE_SUCCEEDED for the failed operation. */
+    PM_EVT_PEER_DELETE_SUCCEEDED,           /**< @brief A peer was cleared from flash storage, for example because a call to @ref pm_peer_delete succeeded. This event can also be sent as part of a call to @ref pm_peers_delete or internal cleanup. */
+    PM_EVT_PEER_DELETE_FAILED,              /**< @brief A peer could not be cleared from flash storage. This event is sent instead of @ref PM_EVT_PEER_DELETE_SUCCEEDED for the failed operation. */
+    PM_EVT_PEERS_DELETE_SUCCEEDED,          /**< @brief A call to @ref pm_peers_delete has completed successfully. Flash storage now contains no peer data. */
+    PM_EVT_PEERS_DELETE_FAILED,             /**< @brief A call to @ref pm_peers_delete has failed, which means that at least one of the peers could not be deleted. Other peers might have been deleted, or might still be queued to be deleted. No more @ref PM_EVT_PEERS_DELETE_SUCCEEDED or @ref PM_EVT_PEERS_DELETE_FAILED events are sent until the next time @ref pm_peers_delete is called. */
+    PM_EVT_LOCAL_DB_CACHE_APPLIED,          /**< @brief Local database values for a peer (taken from flash storage) have been provided to the SoftDevice. */
+    PM_EVT_LOCAL_DB_CACHE_APPLY_FAILED,     /**< @brief Local database values for a peer (taken from flash storage) were rejected by the SoftDevice, which means that either the database has changed or the user has manually set the local database to an invalid value (using @ref pm_peer_data_store). */
+    PM_EVT_SERVICE_CHANGED_IND_SENT,        /**< @brief A service changed indication has been sent to a peer, as a result of a call to @ref pm_local_database_has_changed. This event will be followed by a @ref PM_EVT_SERVICE_CHANGED_IND_CONFIRMED event if the peer acknowledges the indication. */
+    PM_EVT_SERVICE_CHANGED_IND_CONFIRMED,   /**< @brief A service changed indication that was sent has been confirmed by a peer. The peer can now be considered aware that the local database has changed. */
+} pm_evt_id_t;
+
+
+/**@brief Parameters specific to the @ref PM_EVT_CONN_SEC_SUCCEEDED event.
+ */
+typedef struct
+{
+    pm_conn_sec_procedure_t procedure; /**< @brief The procedure that led to securing the link. */
+} pm_conn_secured_evt_t;
+
+
+/**@brief Parameters specific to the @ref PM_EVT_CONN_SEC_FAILED event.
+ */
+typedef struct
+{
+    pm_conn_sec_procedure_t  procedure; /**< @brief The procedure that failed. */
+    pm_sec_error_code_t error;          /**< @brief An error code that describes the failure. */
+    uint8_t             error_src;      /**< @brief The party that raised the error, see @ref BLE_GAP_SEC_STATUS_SOURCES. */
+} pm_conn_secure_failed_evt_t;
+
+
+/**@brief Actions that can be performed to peer data in persistent storage.
+ */
+typedef enum
+{
+    PM_PEER_DATA_OP_UPDATE, /**< @brief Writing or overwriting the data. */
+    PM_PEER_DATA_OP_DELETE, /**< @brief Removing the data. */
+} pm_peer_data_op_t;
+
+
+/**@brief Parameters specific to the @ref PM_EVT_PEER_DATA_UPDATE_SUCCEEDED event.
+ */
+typedef struct
+{
+    pm_peer_data_id_t data_id;           /**< @brief The type of the data that was changed. */
+    pm_peer_data_op_t action;            /**< @brief What happened to the data. */
+    uint8_t           flash_changed : 1; /**< @brief If this is false, no operation was done in flash, because the value was already what it should be. Please note that in certain scenarios, this flag will be true even if the new value is the same as the old. */
+    pm_store_token_t  token;             /**< @brief Token that identifies the operation. For @ref PM_PEER_DATA_OP_DELETE actions, this token can be disregarded. For @ref PM_PEER_DATA_OP_UPDATE actions, compare this token with the token that is received from a call to a @ref PM_PEER_DATA_FUNCTIONS function. */
+} pm_peer_data_update_succeeded_evt_t;
+
+
+/**@brief Parameters specific to the @ref PM_EVT_PEER_DATA_UPDATE_FAILED event.
+ */
+typedef struct
+{
+    pm_peer_data_id_t data_id; /**< @brief The type of the data that was supposed to be changed. */
+    pm_peer_data_op_t action;  /**< @brief The action that failed. */
+    pm_store_token_t  token;   /**< @brief Token that identifies the operation. For @ref PM_PEER_DATA_OP_DELETE actions, this token can be disregarded. For @ref PM_PEER_DATA_OP_UPDATE actions, compare this token with the token that is received from a call to a @ref PM_PEER_DATA_FUNCTIONS function. */
+    ret_code_t        error;   /**< @brief An error code that describes the failure. */
+} pm_peer_data_update_failed_t;
+
+
+/**@brief Standard parameters for failure events.
+ */
+typedef struct
+{
+    ret_code_t error; /**< @brief The error that occurred. */
+} pm_failure_evt_t;
+
+
+/**@brief An event from the @ref peer_manager module.
+ *
+ * @details The structure contains both standard parameters and parameters that are specific to some events.
+ */
+typedef struct
+{
+    pm_evt_id_t  evt_id;      /**< @brief The type of the event. */
+    uint16_t     conn_handle; /**< @brief The connection that this event pertains to, or @ref BLE_CONN_HANDLE_INVALID. */
+    pm_peer_id_t peer_id;     /**< @brief The bonded peer that this event pertains to, or @ref PM_PEER_ID_INVALID. */
+    union
+    {
+        pm_conn_secured_evt_t               conn_sec_succeeded;         /**< @brief Parameters specific to the @ref PM_EVT_CONN_SEC_SUCCEEDED event. */
+        pm_conn_secure_failed_evt_t         conn_sec_failed;            /**< @brief Parameters specific to the @ref PM_EVT_CONN_SEC_FAILED event. */
+        pm_peer_data_update_succeeded_evt_t peer_data_update_succeeded; /**< @brief Parameters specific to the @ref PM_EVT_PEER_DATA_UPDATE_SUCCEEDED event. */
+        pm_peer_data_update_failed_t        peer_data_update_failed;    /**< @brief Parameters specific to the @ref PM_EVT_PEER_DATA_UPDATE_FAILED event. */
+        pm_failure_evt_t                    peer_delete_failed;         /**< @brief Parameters specific to the @ref PM_EVT_PEER_DELETE_FAILED event. */
+        pm_failure_evt_t                    peers_delete_failed_evt;    /**< @brief Parameters specific to the @ref PM_EVT_PEERS_DELETE_FAILED event. */
+        pm_failure_evt_t                    error_unexpected;           /**< @brief Parameters specific to the @ref PM_EVT_PEER_DELETE_FAILED event. */
+    } params;
+} pm_evt_t;
+
+
+/**@brief Event handler for events from the @ref peer_manager module.
+ *
+ * @sa pm_register
+ *
+ * @param[in]  p_event  The event that has occurred.
+ */
+typedef void (*pm_evt_handler_t)(pm_evt_t const * p_event);
+
+
+/**@brief Function for initializing the Peer Manager.
+ *
+ * @details You must initialize the Peer Manager before you can call any other Peer Manager
+ *          functions.
+ *
+ * @retval NRF_SUCCESS              If initialization was successful.
+ * @retval NRF_ERROR_INTERNAL       If an internal error occurred.
+ */
+ret_code_t pm_init(void);
+
+
+/**@brief Function for registering an event handler with the Peer Manager.
+ *
+ * @param[in] event_handler  Callback for events from the @ref peer_manager module. @p event_handler
+ *                           is called for every event that the Peer Manager sends after this
+ *                           function is called.
+ *
+ * @retval NRF_SUCCESS              If initialization was successful.
+ * @retval NRF_ERROR_NULL           If @p event_handler was NULL.
+ * @retval NRF_ERROR_NO_MEM         If no more registrations can happen.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ */
+ret_code_t pm_register(pm_evt_handler_t event_handler);
+
+
+/**@brief Function for providing pairing and bonding parameters to use for pairing procedures.
+ *
+ * @details Until this function is called, all bonding procedures that are initiated by the
+ *          peer are rejected.
+ *
+ *          This function can be called multiple times with different parameters, even with NULL as
+ *          @p p_sec_params, in which case the Peer Manager starts rejecting all procedures again.
+ *
+ * @param[in]  p_sec_params  Security parameters to be used for subsequent security procedures.
+ *
+ * @retval NRF_SUCCESS              If the parameters were set successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  If the combination of parameters is invalid.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ * @retval NRF_ERROR_INTERNAL       If an internal error occurred.
+ */
+ret_code_t pm_sec_params_set(ble_gap_sec_params_t * p_sec_params);
+
+
+/**@brief Function for passing BLE events to the Peer Manager.
+ *
+ * @details For the module to work as expected, this function must be called with each BLE event
+ *          from the SoftDevice. It must be called after @ref ble_conn_state_on_ble_evt, but before
+ *          the application processes the event.
+ *
+ *          Calling this function before @ref pm_init is safe, but without effect.
+ *
+ * @param[in]  p_ble_evt  BLE stack event that is dispatched to the function.
+ */
+void pm_on_ble_evt(ble_evt_t * p_ble_evt);
+
+
+/**@brief Function for establishing encryption on a connection, and optionally establishing a bond.
+ *
+ * @details This function attempts to secure the link that is specified by @p conn_handle. It uses
+ *          the parameters that were previously provided in a call to @ref pm_sec_params_set.
+ *
+ *          If the connection is a master connection, calling this function starts a security
+ *          procedure on the link. If we have keys from a previous bonding procedure with this peer
+ *          and the keys meet the security requirements in the currently active sec_params, the
+ *          function attempts to establish encryption with the existing keys. If no key exists, the
+ *          function attempts to pair and bond according to the currently active sec_params.
+ *
+ *          If the function completes successfully, a @ref PM_EVT_CONN_SEC_START event is sent.
+ *          The procedure might be queued, in which case the @ref PM_EVT_CONN_SEC_START event is
+ *          delayed until the procedure is initiated in the SoftDevice.
+ *
+ *          If the connection is a slave connection, the function sends a security request to
+ *          the peer (master). It is up to the peer then to initiate pairing or encryption.
+ *          If the peer ignores the request, a @ref BLE_GAP_EVT_TIMEOUT event occurs
+ *          with the source @ref BLE_GAP_TIMEOUT_SRC_SECURITY_REQUEST. Otherwise, the peer initiates
+ *          security, in which case things happen as if the peer had initiated security itself.
+ *          See @ref PM_EVT_CONN_SEC_START for information about peer-initiated security.
+ *
+ * @param[in]  conn_handle      Connection handle of the link as provided by the SoftDevice.
+ * @param[in]  force_repairing  Whether to force a pairing procedure even if there is an existing
+ *                              encryption key. This argument is relevant only for
+ *                              the central role. Recommended value: false.
+ *
+ * @retval NRF_SUCCESS                    If the operation completed successfully.
+ * @retval NRF_ERROR_TIMEOUT              If there was an SMP time-out, so that no more SMP
+ *                                        operations can be performed on this link.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE  If the connection handle is invalid.
+ * @retval NRF_ERROR_NOT_FOUND            If the security parameters have not been set.
+ * @retval NRF_ERROR_STORAGE_FULL         If there is no more space in persistent storage.
+ * @retval NRF_ERROR_NO_MEM               If no more authentication procedures can run in parallel
+ *                                        for the given role. See @ref sd_ble_gap_authenticate.
+ * @retval NRF_ERROR_INVALID_STATE        If the Peer Manager is not initialized, or the peer is
+ *                                        disconnected or in the process of disconnecting.
+ * @retval NRF_ERROR_INTERNAL             If an internal error occurred.
+ */
+ret_code_t pm_conn_secure(uint16_t conn_handle, bool force_repairing);
+
+
+/**@brief Function for providing security configuration for a link.
+ *
+ * @details This function is optional, and must be called in reply to a @ref
+ *          PM_EVT_CONN_SEC_CONFIG_REQ event, before the Peer Manager event handler returns. If it
+ *          is not called in time, a default configuration is used. See @ref pm_conn_sec_config_t
+ *          for the value of the default.
+ *
+ * @param[in]  conn_handle        The connection to set the configuration for.
+ * @param[in]  p_conn_sec_config  The configuration.
+ */
+void pm_conn_sec_config_reply(uint16_t conn_handle, pm_conn_sec_config_t * p_conn_sec_config);
+
+
+/**@brief Function for manually informing that the local database has changed.
+ *
+ * @details This function sends a service changed indication to all bonded and/or connected peers
+ *          that subscribe to this indication. If a bonded peer is not connected, the indication is
+ *          sent when it reconnects. Every time an indication is sent, a @ref
+ *          PM_EVT_SERVICE_CHANGED_IND_SENT event occurs, followed by a @ref
+ *          PM_EVT_SERVICE_CHANGED_IND_CONFIRMED when the peer sends its confirmation. Peers that
+ *          are not subscribed to the service changed indication when this function is called do not
+ *          receive an indication, and no events are sent to the user. Likewise, if the service
+ *          changed characteristic is not present in the local database, this no indications are
+ *          sent peers, and no events are sent to the user.
+ */
+void pm_local_database_has_changed(void);
+
+
+/**@brief Function for getting the security status of a connection.
+ *
+ * @param[in]  conn_handle    Connection handle of the link as provided by the SoftDevice.
+ * @param[out] p_conn_sec_status  Security status of the link.
+ *
+ * @retval NRF_SUCCESS                    If pairing was initiated successfully.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE  If the connection handle is invalid.
+ * @retval NRF_ERROR_NULL                 If @p p_conn_sec_status was NULL.
+ * @retval NRF_ERROR_INVALID_STATE        If the Peer Manager is not initialized.
+ */
+ret_code_t pm_conn_sec_status_get(uint16_t conn_handle, pm_conn_sec_status_t * p_conn_sec_status);
+
+
+/**@brief Experimental function for specifying the public key to use for LESC operations.
+ *
+ * @details This function can be called multiple times. The specified public key will be used for
+ *          all subsequent LESC (LE Secure Connections) operations until the next time this function
+ *          is called.
+ *
+ * @note The key must continue to reside in application memory as it is not copied by Peer Manager.
+ *
+ * @param[in]  p_public_key  The public key to use for all subsequent LESC operations.
+ *
+ * @retval NRF_SUCCESS                    If pairing was initiated successfully.
+ * @retval NRF_ERROR_INVALID_STATE        If the Peer Manager is not initialized.
+ */
+ret_code_t pm_lesc_public_key_set(ble_gap_lesc_p256_pk_t * p_public_key);
+
+
+/**@brief Function for setting or clearing the whitelist.
+ *
+ * When using the S13x SoftDevice v3.x, this function sets or clears the whitelist.
+ * When using the S13x SoftDevice v2.x, this function caches a list of
+ * peers that can be retrieved later by @ref pm_whitelist_get to pass to the @ref lib_ble_advertising.
+ *
+ * To clear the current whitelist, pass either NULL as @p p_peers or zero as @p peer_cnt.
+ *
+ * @param[in] p_peers   The peers to add to the whitelist. Pass NULL to clear the current whitelist.
+ * @param[in] peer_cnt  The number of peers to add to the whitelist. The number must not be greater than
+ *                      @ref BLE_GAP_WHITELIST_ADDR_MAX_COUNT. Pass zero to clear the current
+ *                      whitelist.
+ *
+ * @retval NRF_SUCCESS                      If the whitelist was successfully set or cleared.
+ * @retval BLE_GAP_ERROR_WHITELIST_IN_USE   If a whitelist is already in use and cannot be set.
+ * @retval BLE_ERROR_GAP_INVALID_BLE_ADDR   If a peer in @p p_peers has an address that cannot
+ *                                          be used for whitelisting.
+ * @retval NRF_ERROR_NOT_FOUND              If any of the peers in @p p_peers cannot be found.
+ * @retval NRF_ERROR_DATA_SIZE              If @p peer_cnt is greater than
+ *                                          @ref BLE_GAP_WHITELIST_ADDR_MAX_COUNT.
+ * @retval NRF_ERROR_INVALID_STATE          If the Peer Manager is not initialized.
+ */
+ret_code_t pm_whitelist_set(pm_peer_id_t const * p_peers,
+                            uint32_t             peer_cnt);
+
+
+/**@brief Function for retrieving the previously set whitelist.
+ *
+ * The function retrieves the whitelist of GAP addresses and IRKs that was
+ * previously set by @ref pm_whitelist_set.
+ *
+ * To retrieve only GAP addresses or only IRKs, provide only one of the
+ * buffers. If a buffer is provided, its size must be specified.
+ *
+ * @param[out]   p_addrs    The buffer where to store GAP addresses. Pass NULL to retrieve
+ *                          only IRKs (in that case, @p p_irks must not be NULL).
+ * @param[in,out] p_addr_cnt In: The size of the @p p_addrs buffer.
+ *                          May be NULL if and only if @p p_addrs is NULL.
+ *                          Out: The number of GAP addresses copied into the buffer.
+ *                          If @p p_addrs is NULL, this parameter remains unchanged.
+ * @param[out]   p_irks     The buffer where to store IRKs. Pass NULL to retrieve
+ *                          only GAP addresses (in that case, @p p_addrs must not NULL).
+ * @param[in,out] p_irk_cnt  In: The size of the @p p_irks buffer.
+ *                          May be NULL if and only if @p p_irks is NULL.
+ *                          Out: The number of IRKs copied into the buffer.
+ *                          If @p p_irks is NULL, this paramater remains unchanged.
+ *
+ * @retval NRF_SUCCESS                      If the whitelist was successfully retrieved.
+ * @retval BLE_ERROR_GAP_INVALID_BLE_ADDR   If a peer has an address that cannot be used for
+ *                                          whitelisting (this error can occur only
+ *                                          when using the S13x SoftDevice v2.x).
+ * @retval NRF_ERROR_NULL                   If a required parameter is NULL.
+ * @retval NRF_ERROR_NO_MEM                 If the provided buffers are too small.
+ * @retval NRF_ERROR_NOT_FOUND              If the data for any of the cached whitelisted peers
+ *                                          cannot be found. It might have been deleted.
+ * @retval NRF_ERROR_INVALID_STATE          If the Peer Manager is not initialized.
+ */
+ret_code_t pm_whitelist_get(ble_gap_addr_t * p_addrs,
+                            uint32_t       * p_addr_cnt,
+                            ble_gap_irk_t  * p_irks,
+                            uint32_t       * p_irk_cnt);
+
+
+/**@brief Function for setting and clearing the device identities list.
+ *
+ * @param[in]   p_peers     The peers to add to the device identities list. Pass NULL to clear
+ *                          the device identities list.
+ * @param[in]   peer_cnt    The number of peers. Pass zero to clear the device identities list.
+ *
+ * @retval NRF_SUCCESS                              If the device identities list was successfully
+ *                                                  set or cleared.
+ * @retval NRF_ERROR_NOT_FOUND                      If a peer is invalid or its data could not
+ *                                                  be found in flash.
+ * @retval BLE_ERROR_GAP_INVALID_BLE_ADDR           If a peer has an address that cannot be
+ *                                                  used for whitelisting.
+ * @retval BLE_ERROR_GAP_DEVICE_IDENTITIES_IN_USE   If the device identities list is in use and
+ *                                                  cannot be set.
+ * @retval NRF_ERROR_INVALID_STATE                  If the Peer Manager is not initialized.
+ * @retval NRF_ERROR_NOT_SUPPORTED                  If using a SoftDevice that does not support
+ *                                                  device identities, e.g. S130 v2.0.
+ */
+ret_code_t pm_device_identities_list_set(pm_peer_id_t const * p_peers,
+                                         uint32_t             peer_cnt);
+
+
+/**@brief Function for setting the local <em>Bluetooth</em> identity address.
+ *
+ * @details The local <em>Bluetooth</em> identity address is the address that identifies the device to other
+ * peers. The address type must be either @ref BLE_GAP_ADDR_TYPE_PUBLIC or @ref
+ * BLE_GAP_ADDR_TYPE_RANDOM_STATIC. The identity address cannot be changed while roles are
+ * running.
+ *
+ * The SoftDevice sets a default address of type @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC
+ * when it is enabled. This default address is a random number that is populated during
+ * the IC manufacturing process. It remains unchanged for the lifetime of each IC, but the application can assign a different identity address.
+ *
+ * The identity address is distributed to the peer during bonding.
+ * If the address changes, the address stored in the peer device will not be valid and the
+ * ability to reconnect using the old address will be lost.
+ *
+ *
+ * @note The SoftDevice functions @ref sd_ble_gap_addr_set
+ *       and @ref sd_ble_gap_privacy_set must not be called when using the Peer Manager.
+ *       Use this function instead.
+ *
+ * @param[in] p_addr The GAP address to be set.
+ *
+ * @retval NRF_SUCCESS                     If the identity address was set successfully.
+ * @retval NRF_ERROR_NULL                  If @p p_addr is NULL.
+ * @retval NRF_ERROR_INVALID_ADDR          If the @p p_addr pointer is invalid.
+ * @retval BLE_ERROR_GAP_INVALID_BLE_ADDR  If the BLE address is invalid.
+ * @retval NRF_ERROR_BUSY                  If the SoftDevice was busy. Process SoftDevice events
+ *                                         and retry.
+ * @retval NRF_ERROR_INVALID_STATE         If the Peer Manager is not initialized or if this function
+ *                                         was called while advertising, scanning, or while connected.
+ * @retval NRF_ERROR_INTERNAL              If an internal error occurred.
+ */
+ret_code_t pm_id_addr_set(ble_gap_addr_t const * p_addr);
+
+
+/**@brief Function for retrieving the local <em>Bluetooth</em> identity address.
+ *
+ * This function always returns the identity address, irrespective of the privacy settings.
+ * This means that the address type will always be either @ref BLE_GAP_ADDR_TYPE_PUBLIC or @ref
+ * BLE_GAP_ADDR_TYPE_RANDOM_STATIC.
+ *
+ * @param[out] p_addr Pointer to the address structure to be filled in.
+ *
+ * @retval NRF_SUCCESS             If the address was retrieved successfully.
+ * @retval NRF_ERROR_NULL          If @p p_addr is NULL.
+ * @retval NRF_ERROR_INVALID_STATE If the Peer Manager is not initialized.
+ */
+ret_code_t pm_id_addr_get(ble_gap_addr_t * p_addr);
+
+
+/**@brief Function for configuring privacy settings.
+ *
+ * The privacy settings cannot be configured while advertising, scanning, or while in a connection.
+ *
+ * @note The SoftDevice functions @ref sd_ble_gap_addr_set
+ *       and @ref sd_ble_gap_privacy_set must not be called when using the Peer Manager.
+ *       Use this function instead.
+ *
+ * @param[in] p_privacy_params Privacy settings.
+ *
+ * @retval NRF_SUCCESS                     If the privacy settings were configured successfully.
+ * @retval NRF_ERROR_NULL                  If @p p_privacy_params is NULL.
+ * @retval NRF_ERROR_BUSY                  If the operation could not be performed at this time.
+ *                                         Process SoftDevice events and retry.
+ * @retval NRF_ERROR_INVALID_PARAM         If the address type is invalid.
+ * @retval NRF_ERROR_INVALID_STATE         If this function is called while BLE roles using
+ *                                         privacy are enabled.
+ * @retval NRF_ERROR_INVALID_STATE         If the Peer Manager is not initialized.
+ */
+ret_code_t pm_privacy_set(pm_privacy_params_t const * p_privacy_params);
+
+
+/**@brief Function for retrieving privacy settings.
+ *
+ * The privacy settings that are returned include the current IRK as well.
+ *
+ * @param[out] p_privacy_params Privacy settings.
+ *
+ * @retval NRF_SUCCESS              If the privacy settings were retrieved successfully.
+ * @retval NRF_ERROR_NULL           If @p p_privacy_params or @p p_privacy_params->p_device_irk is
+ *                                  NULL.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ */
+ret_code_t pm_privacy_get(pm_privacy_params_t * p_privacy_params);
+
+
+/**@brief Function for getting the connection handle of the connection with a bonded peer.
+ *
+ * @param[in]  peer_id        The peer ID of the bonded peer.
+ * @param[out] p_conn_handle  Connection handle, or @ref BLE_ERROR_INVALID_CONN_HANDLE if the peer
+ *                            is not connected.
+ *
+ * @retval NRF_SUCCESS              If the connection handle was retrieved successfully.
+ * @retval NRF_ERROR_NULL           If @p p_conn_handle was NULL.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ */
+ret_code_t pm_conn_handle_get(pm_peer_id_t peer_id, uint16_t * p_conn_handle);
+
+
+/**@brief Function for retrieving the ID of a peer, given its connection handle.
+ *
+ * @param[in]  conn_handle  The connection handle of the peer.
+ * @param[out] p_peer_id    The peer ID, or @ref PM_PEER_ID_INVALID if the peer is not bonded or
+ *                          @p conn_handle does not refer to a valid connection.
+ *
+ * @retval NRF_SUCCESS              If the peer ID was retrieved successfully.
+ * @retval NRF_ERROR_NULL           If @p p_peer_id was NULL.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ */
+ret_code_t pm_peer_id_get(uint16_t conn_handle, pm_peer_id_t * p_peer_id);
+
+
+/**@brief Function for getting the next peer ID in the sequence of all used peer IDs.
+ *
+ * @details This function can be used to loop through all used peer IDs. The order in which
+ *          peer IDs are returned should be considered unpredictable. @ref PM_PEER_ID_INVALID
+ *          is considered to be before the first and after the last used peer ID.
+ *
+ * @details To loop through all peer IDs exactly once, use the following constuct:
+ *          @code{c}
+ *              pm_peer_id_t current_peer_id = pm_next_peer_id_get(PM_PEER_ID_INVALID);
+ *              while (current_peer_id != PM_PEER_ID_INVALID)
+ *              {
+ *                  // Do something with current_peer_id.
+ *                  current_peer_id = pm_next_peer_id_get(current_peer_id)
+ *              }
+ *          @endcode
+ *
+ * @param[in]  prev_peer_id  The previous peer ID.
+ *
+ * @return  The next peer ID. If @p prev_peer_id was @ref PM_PEER_ID_INVALID, the
+ *          next peer ID is the first used peer ID. If @p prev_peer_id was the last
+ *          used peer ID, the function returns @ref PM_PEER_ID_INVALID.
+ */
+pm_peer_id_t pm_next_peer_id_get(pm_peer_id_t prev_peer_id);
+
+
+/**@brief Function for querying the number of valid peer IDs that are available.
+ *
+ * @details This function returns the number of peers for which there is data in persistent storage.
+ *
+ * @return  The number of valid peer IDs.
+ */
+uint32_t pm_peer_count(void);
+
+
+
+
+/**@anchor PM_PEER_DATA_FUNCTIONS
+ * @name Functions (Peer Data)
+ * Functions for manipulating peer data.
+ * @{
+ */
+
+/**
+ * @{
+ */
+
+/**@brief Function for retrieving stored data of a peer.
+ *
+ * @note The length of the provided buffer must be a multiple of 4.
+ *
+ * @param[in]    peer_id   Peer ID to get data for.
+ * @param[in]    data_id   Which type of data to read.
+ * @param[out]   p_data    Where to put the retrieved data.
+ * @param[inout] p_len     In: The length in bytes of @p p_data.
+ *                         Out: The length in bytes of the read data, if the read was successful.
+ *
+ * @retval NRF_SUCCESS              If the data was read successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  If the the data type or the peer ID was invalid or unallocated,
+ *                                  or if the length in @p p_length was not a multiple of 4.
+ * @retval NRF_ERROR_NULL           If a pointer parameter was NULL.
+ * @retval NRF_ERROR_NOT_FOUND      If no stored data was found for this peer ID/data ID combination.
+ * @retval NRF_ERROR_DATA_SIZE      If the provided buffer was not large enough.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ */
+ret_code_t pm_peer_data_load(pm_peer_id_t      peer_id,
+                             pm_peer_data_id_t data_id,
+                             void            * p_data,
+                             uint16_t        * p_len);
+
+/**@brief Function for reading a peer's bonding data (@ref PM_PEER_DATA_ID_BONDING).
+ * @details See @ref pm_peer_data_load for parameters and return values. */
+ret_code_t pm_peer_data_bonding_load(pm_peer_id_t             peer_id,
+                                     pm_peer_data_bonding_t * p_data);
+
+/**@brief Function for reading a peer's remote DB values. (@ref PM_PEER_DATA_ID_GATT_REMOTE).
+ * @details See @ref pm_peer_data_load for parameters and return values. */
+ret_code_t pm_peer_data_remote_db_load(pm_peer_id_t        peer_id,
+                                       ble_gatt_db_srv_t * p_data,
+                                       uint16_t          * p_len);
+
+/**@brief Function for reading a peer's application data. (@ref PM_PEER_DATA_ID_APPLICATION).
+ * @details See @ref pm_peer_data_load for parameters and return values. */
+ret_code_t pm_peer_data_app_data_load(pm_peer_id_t peer_id,
+                                      uint8_t    * p_data,
+                                      uint16_t   * p_len);
+/** @}*/
+
+
+/**
+ * @{
+ */
+
+/**@brief Function for setting or updating stored data of a peer.
+ *
+ * @note Writing the data to persistent storage happens asynchronously. Therefore, the buffer
+ *       that contains the data must be kept alive until the operation has completed.
+ *
+ * @note The data written using this function might later be overwritten as a result of internal
+ *       operations in the Peer Manager. A Peer Manager event is sent each time data is updated,
+ *       regardless of whether the operation originated internally or from action by the user.
+ *
+ * @param[in]  peer_id  Peer ID to set data for.
+ * @param[in]  data_id  Which type of data to set.
+ * @param[in]  p_data   New value to set.
+ * @param[in]  len      The length in bytes of @p p_data.
+ * @param[out] p_token  A token that identifies this particular store operation. The token can be
+ *                      used to identify events that pertain to this operation. This parameter can
+ *                      be NULL.
+ *
+ * @retval NRF_SUCCESS              If the data is scheduled to be written to persistent storage.
+ * @retval NRF_ERROR_NULL           If @p p_data is NULL.
+ * @retval NRF_ERROR_NOT_FOUND      If no peer was found for the peer ID.
+ * @retval NRF_ERROR_BUSY           If the underlying flash handler is busy with other flash
+ *                                  operations. Try again after receiving a Peer Manager event.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ */
+ret_code_t pm_peer_data_store(pm_peer_id_t       peer_id,
+                              pm_peer_data_id_t  data_id,
+                              void       const * p_data,
+                              uint16_t           len,
+                              pm_store_token_t * p_token);
+
+/**@brief Function for setting or updating a peer's bonding data (@ref PM_PEER_DATA_ID_BONDING).
+ * @details See @ref pm_peer_data_store for parameters and return values. */
+ret_code_t pm_peer_data_bonding_store(pm_peer_id_t                   peer_id,
+                                      pm_peer_data_bonding_t const * p_data,
+                                      pm_store_token_t             * p_token);
+
+/**@brief Function for setting or updating a peer's remote DB values. (@ref PM_PEER_DATA_ID_GATT_REMOTE).
+ * @details See @ref pm_peer_data_store for parameters and return values. */
+ret_code_t pm_peer_data_remote_db_store(pm_peer_id_t              peer_id,
+                                        ble_gatt_db_srv_t const * p_data,
+                                        uint16_t                  len,
+                                        pm_store_token_t        * p_token);
+
+/**@brief Function for setting or updating a peer's application data. (@ref PM_PEER_DATA_ID_APPLICATION).
+ * @details See @ref pm_peer_data_store for parameters and return values. */
+ret_code_t pm_peer_data_app_data_store(pm_peer_id_t       peer_id,
+                                       uint8_t    const * p_data,
+                                       uint16_t           len,
+                                       pm_store_token_t * p_token);
+/** @}*/
+
+
+/**
+ * @{
+ */
+
+/**@brief Function for deleting a peer's stored pieces of data.
+ *
+ * @details This function deletes specific data that is stored for a peer. Note that bonding data
+ *          cannot be cleared separately.
+ *
+ *          To delete all data for a peer (including bonding data), use @ref pm_peer_delete.
+ *
+ * @note Clearing data in persistent storage happens asynchronously.
+ *
+ * @param[in]  peer_id  Peer ID to clear data for.
+ * @param[in]  data_id  Which data to clear.
+ *
+ * @retval NRF_SUCCESS              If the clear procedure was initiated successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  If @p data_id was PM_PEER_DATA_ID_BONDING or invalid, or
+ *                                  @p peer_id was invalid.
+ * @retval NRF_ERROR_NOT_FOUND      If there was no data to clear for this peer ID/data ID combination.
+ * @retval NRF_ERROR_BUSY           If the underlying flash handler is busy with other flash
+ *                                  operations. Try again after receiving a Peer Manager event.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ * @retval NRF_ERROR_INTERNAL       If an internal error occurred.
+ */
+ret_code_t pm_peer_data_delete(pm_peer_id_t peer_id, pm_peer_data_id_t data_id);
+
+
+/**@brief Function for manually adding a peer to the persistent storage.
+ *
+ * @details This function allocates a new peer ID and stores bonding data for the new peer. The
+ *          bonding data is necessary to prevent ambiguity/inconsistency in peer data.
+ *
+ * @param[in]  p_bonding_data  The bonding data of the new peer (must contain a public/static
+ *                             address or a non-zero IRK).
+ * @param[out] p_new_peer_id   Peer ID for the new peer, or an existing peer if a match was found.
+ * @param[out] p_token         A token that identifies this particular store operation (storing the
+ *                             bonding data). The token can be used to identify events that pertain
+ *                             to this operation. This parameter can be NULL.
+ *
+ * @retval NRF_SUCCESS              If the store operation for bonding data was initiated successfully.
+ * @retval NRF_ERROR_NULL           If @p p_bonding_data or @p p_new_peer_id is NULL.
+ * @retval NRF_ERROR_STORAGE_FULL   If there is no more space in persistent storage.
+ * @retval NRF_ERROR_NO_MEM         If there are no more available peer IDs.
+ * @retval NRF_ERROR_BUSY           If the underlying flash filesystem is busy with other flash
+ *                                  operations. Try again after receiving a Peer Manager event.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ * @retval NRF_ERROR_INTERNAL       If an internal error occurred.
+ */
+ret_code_t pm_peer_new(pm_peer_id_t           * p_new_peer_id,
+                       pm_peer_data_bonding_t * p_bonding_data,
+                       pm_store_token_t       * p_token);
+
+
+/**@brief Function for freeing persistent storage for a peer.
+ *
+ * @details This function deletes every piece of data that is associated with the specified peer and
+ *          frees the peer ID to be used for another peer. The deletion happens asynchronously, and
+ *          the peer ID is not freed until the data is deleted. When the operation finishes, a @ref
+ *          PM_EVT_PEER_DELETE_SUCCEEDED or @ref PM_EVT_PEER_DELETE_FAILED event is sent.
+ *
+ * @warning Use this function only when not connected to or connectable for the peer that is being
+ *          deleted. If the peer is or becomes connected or data is manually written in flash during
+ *          this procedure (until the success or failure event happens), the behavior is undefined.
+ *
+ * @param[in]  peer_id  Peer ID to be freed and have all associated data deleted.
+ *
+ * @retval NRF_SUCCESS              If the operation was initiated successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  If the peer ID was not valid.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ */
+ret_code_t pm_peer_delete(pm_peer_id_t peer_id);
+
+
+/**@brief Function for deleting all data stored for all peers.
+ *
+ * @details This function sends either a @ref PM_EVT_PEERS_DELETE_SUCCEEDED or a @ref
+ *          PM_EVT_PEERS_DELETE_FAILED event. In addition, a @ref PM_EVT_PEER_DELETE_SUCCEEDED or
+ *          @ref PM_EVT_PEER_DELETE_FAILED event is sent for each deleted peer.
+ *
+ * @note No event is sent when there is no peer data in flash.
+ *
+ * @warning Use this function only when not connected or connectable. If a peer is or becomes
+ *          connected or a @ref PM_PEER_DATA_FUNCTIONS function is used during this procedure (until
+ *          the success or failure event happens), the behavior is undefined.
+ *
+ * @retval NRF_SUCCESS              If the deletion process was initiated successfully.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ * @retval NRF_ERROR_INTERNAL       If an internal error occurred.
+ */
+ret_code_t pm_peers_delete(void);
+/** @}*/
+
+
+/**
+ * @{
+ */
+
+
+/**@brief Function for finding the highest and lowest ranked peers.
+ *
+ * @details The rank is saved in persistent storage under the data ID @ref PM_PEER_DATA_ID_PEER_RANK.
+ *
+ * @details The interpretation of rank is up to the user, because the rank is only updated by
+ *          calling @ref pm_peer_rank_highest or by manipulating the value using a @ref
+ *          PM_PEER_DATA_FUNCTIONS function.
+ *
+ * @note Any argument that is NULL is ignored.
+ *
+ * @param[out] p_highest_ranked_peer  The peer ID with the highest rank of all peers, for example,
+ *                                    the most recently used peer.
+ * @param[out] p_highest_rank         The highest rank.
+ * @param[out] p_lowest_ranked_peer   The peer ID with the lowest rank of all peers, for example,
+ *                                    the least recently used peer.
+ * @param[out] p_lowest_rank          The lowest rank.
+ *
+ * @retval NRF_SUCCESS              If the operation completed successfully.
+ * @retval NRF_ERROR_NOT_FOUND      If no peers were found.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ * @retval NRF_ERROR_INTERNAL       If an internal error occurred.
+ */
+ret_code_t pm_peer_ranks_get(pm_peer_id_t * p_highest_ranked_peer,
+                             uint32_t     * p_highest_rank,
+                             pm_peer_id_t * p_lowest_ranked_peer,
+                             uint32_t     * p_lowest_rank);
+
+
+/**@brief Function for updating the rank of a peer to be highest among all stored peers.
+ *
+ * @details If this function returns @ref NRF_SUCCESS, either a @ref PM_EVT_PEER_DATA_UPDATE_SUCCEEDED or a
+ *          @ref PM_EVT_PEER_DATA_UPDATE_FAILED event is sent with a @ref
+ *          PM_STORE_TOKEN_INVALID store token when the operation is complete. Until the operation
+ *          is complete, this function returns @ref NRF_ERROR_BUSY.
+ *
+ *          When the operation is complete, the peer is the highest ranked peer as reported by
+ *          @ref pm_peer_ranks_get.
+ *
+ * @note The @ref PM_EVT_PEER_DATA_UPDATE_SUCCEEDED event can arrive before the function returns if the peer
+ *       is already ranked highest. In this case, the @ref pm_peer_data_update_succeeded_evt_t::flash_changed flag
+ *       in the event will be false.
+ *
+ * @param[in]  peer_id  The peer to rank highest.
+ *
+ * @retval NRF_SUCCESS              If the peer's rank is, or will be updated to be highest.
+ * @retval NRF_ERROR_BUSY           If the underlying flash handler is busy with other flash
+ *                                  operations, or if a previous call to this function has not
+ *                                  completed. Try again after receiving a Peer Manager event.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ * @retval NRF_ERROR_INTERNAL       If an internal error occurred.
+ */
+ret_code_t pm_peer_rank_highest(pm_peer_id_t peer_id);
+
+/** @}*/
+
+/** @} */
+
+/** @} */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // PEER_MANAGER_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_manager_internal.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,198 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef PEER_MANAGER_INTERNAL_H__
+#define PEER_MANAGER_INTERNAL_H__
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "headers/ble.h"
+#include "ble_gap.h"
+#include "peer_manager_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @file peer_manager_types.h
+ *
+ * @addtogroup peer_manager
+ * @brief File containing definitions used solely inside the Peer Manager's modules.
+ * @{
+ */
+
+ANON_UNIONS_ENABLE
+
+/**@brief One piece of data associated with a peer, together with its type.
+ *
+ * @note This type is deprecated.
+ */
+typedef struct
+{
+    uint16_t              length_words; /**< @brief The length of the data in words. */
+    pm_peer_data_id_t     data_id;      /**< @brief ID that specifies the type of data (defines which member of the union is used). */
+    union
+    {
+        pm_peer_data_bonding_t       * p_bonding_data;            /**< @brief The exchanged bond information in addition to metadata of the bonding. */
+        uint32_t                     * p_peer_rank;               /**< @brief A value locally assigned to this peer. Its interpretation is up to the user. The rank is not set automatically by the Peer Manager, but it is assigned by the user using either @ref pm_peer_rank_highest or a @ref PM_PEER_DATA_FUNCTIONS function. */
+        bool                         * p_service_changed_pending; /**< @brief Whether a service changed indication should be sent to the peer. */
+        pm_peer_data_local_gatt_db_t * p_local_gatt_db;           /**< @brief Persistent information pertaining to a peer GATT client. */
+        ble_gatt_db_srv_t            * p_remote_gatt_db;          /**< @brief Persistent information pertaining to a peer GATT server. */
+        uint8_t                      * p_application_data;        /**< @brief Arbitrary data to associate with the peer. This data can be freely used by the application. */
+        void                         * p_all_data;                /**< @brief Generic access pointer to the data. It is used only to handle the data without regard to type. */
+    }; /**< @brief The data. */
+} pm_peer_data_t;
+
+
+/**@brief Immutable version of @ref pm_peer_data_t.
+ *
+ * @note This type is deprecated.
+ */
+typedef struct
+{
+    uint16_t                    length_words; /**< @brief The length of the data in words. */
+    pm_peer_data_id_t           data_id;      /**< @brief ID that specifies the type of data (defines which member of the union is used). */
+    union
+    {
+        pm_peer_data_bonding_t       const * p_bonding_data;            /**< @brief Immutable @ref pm_peer_data_t::p_bonding_data. */
+        uint32_t                     const * p_peer_rank;               /**< @brief Immutable @ref pm_peer_data_t::p_peer_rank. */
+        bool                         const * p_service_changed_pending; /**< @brief Immutable @ref pm_peer_data_t::p_service_changed_pending. */
+        pm_peer_data_local_gatt_db_t const * p_local_gatt_db;           /**< @brief Immutable @ref pm_peer_data_t::p_local_gatt_db. */
+        ble_gatt_db_srv_t            const * p_remote_gatt_db;          /**< @brief Immutable @ref pm_peer_data_t::p_remote_gatt_db. */
+        uint8_t                      const * p_application_data;        /**< @brief Immutable @ref pm_peer_data_t::p_application_data. */
+        void                         const * p_all_data;                /**< @brief Immutable @ref pm_peer_data_t::p_all_data. */
+    }; /**< @brief The data. */
+} pm_peer_data_const_t;
+
+ANON_UNIONS_DISABLE
+
+
+/**@brief Version of @ref pm_peer_data_t that reflects the structure of peer data in flash.
+ *
+ * @note This type is deprecated.
+ */
+typedef pm_peer_data_const_t pm_peer_data_flash_t;
+
+
+/**@brief Macro for calculating the flash size of bonding data.
+ *
+ * @return The number of words that the data takes in flash.
+ */
+#define PM_BONDING_DATA_N_WORDS() BYTES_TO_WORDS(sizeof(pm_peer_data_bonding_t))
+
+
+/**@brief Macro for calculating the flash size of service changed pending state.
+ *
+ * @return The number of words that the data takes in flash.
+ */
+#define PM_SC_STATE_N_WORDS() BYTES_TO_WORDS(sizeof(bool))
+
+
+/**@brief Macro for calculating the flash size of local GATT database data.
+ *
+ * @param[in]  local_db_len  The length, in bytes, of the database as reported by the SoftDevice.
+ *
+ * @return The number of words that the data takes in flash.
+ */
+#define PM_LOCAL_DB_N_WORDS(local_db_len) \
+                                    BYTES_TO_WORDS((local_db_len) + PM_LOCAL_DB_LEN_OVERHEAD_BYTES)
+
+
+/**@brief Macro for calculating the length of a local GATT database attribute array.
+ *
+ * @param[in]  n_words  The number of words that the data takes in flash.
+ *
+ * @return The length of the database attribute array.
+ */
+#define PM_LOCAL_DB_LEN(n_words) (((n_words) * BYTES_PER_WORD) - PM_LOCAL_DB_LEN_OVERHEAD_BYTES)
+
+
+/**@brief Macro for calculating the flash size of remote GATT database data.
+ *
+ * @param[in]  service_count  The number of services in the service array.
+ *
+ * @return The number of words that the data takes in flash.
+ */
+#define PM_REMOTE_DB_N_WORDS(service_count) BYTES_TO_WORDS(sizeof(ble_gatt_db_srv_t) * (service_count))
+
+
+/**@brief Macro for calculating the flash size of remote GATT database data.
+ *
+ * @param[in]  n_words  The length in number of words.
+ *
+ * @return The number of words that the data takes in flash.
+ */
+#define PM_REMOTE_DB_N_SERVICES(n_words) (((n_words) * BYTES_PER_WORD) / sizeof(ble_gatt_db_srv_t))
+
+
+/**@brief Function for calculating the flash size of the usage index.
+ *
+ * @return The number of words that the data takes in flash.
+ */
+#define PM_USAGE_INDEX_N_WORDS() BYTES_TO_WORDS(sizeof(uint32_t))
+
+/** @}
+ * @endcond
+ */
+
+
+#ifdef NRF_PM_DEBUG
+
+    #define NRF_PM_DEBUG_CHECK(condition)   \
+        if (!(condition))                   \
+        {                                   \
+            __asm("bkpt #0");               \
+        }
+
+#else
+
+    // Prevent "variable set but never used" compiler warnings.
+    #define NRF_PM_DEBUG_CHECK(condition)   (void)(condition)
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PEER_MANAGER_INTERNAL_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_manager_types.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,233 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+ * @file peer_manager_types.h
+ *
+ * @addtogroup peer_manager
+ * @{
+ */
+
+#ifndef PEER_MANAGER_TYPES_H__
+#define PEER_MANAGER_TYPES_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include "nrf.h"
+#include "ble_gap.h"
+#include "ble_hci.h"
+#include "ble_gatt_db.h"
+#include "app_util.h"
+#include "app_util_platform.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**@brief Handle to uniquely identify a peer for which we have persistently stored data.
+ */
+typedef uint16_t pm_peer_id_t;
+
+/**@brief Type that is used for write prepares (used to reserve space in flash).
+ */
+typedef uint32_t pm_prepare_token_t;
+
+/**@brief Type that is used to hold a reference to a stored item in flash.
+ */
+typedef uint32_t pm_store_token_t;
+
+/**@brief Errors from security procedures in Peer Manager.
+ *
+ * @details Possible values are defined in @ref PM_SEC_ERRORS and @ref BLE_GAP_SEC_STATUS.
+ */
+typedef uint16_t pm_sec_error_code_t;
+
+
+//lint -emacro(516,PM_LOCAL_DB_LEN_OVERHEAD_BYTES)
+
+#define PM_PEER_ID_INVALID              0xFFFF                                         /**< @brief Invalid value for @ref pm_peer_id_t. */
+#define PM_STORE_TOKEN_INVALID          0                                              /**< @brief Invalid value for store token. */
+#define PM_PEER_ID_N_AVAILABLE_IDS      256                                            /**< @brief The number of available peer IDs. */
+#define PM_LOCAL_DB_LEN_OVERHEAD_BYTES  offsetof(pm_peer_data_local_gatt_db_t, data)   /**< @brief The static-length part of the local GATT data struct. */
+
+
+#define PM_CONN_SEC_ERROR_BASE 0x1000  /**< @brief The base for Peer Manager defined errors. See @ref PM_SEC_ERRORS and @ref pm_sec_error_code_t. */
+
+
+/**@defgroup PM_SEC_ERRORS Peer Manager defined security errors
+ *
+ * @details The first 256 numbers in this range correspond to the status codes in
+ *          @ref BLE_HCI_STATUS_CODES.
+ * @{ */
+#define PM_CONN_SEC_ERROR_PIN_OR_KEY_MISSING (PM_CONN_SEC_ERROR_BASE + 0x06)  /**< @brief Encryption failed because the peripheral has lost the LTK for this bond. See also @ref BLE_HCI_STATUS_CODE_PIN_OR_KEY_MISSING and Table 3.7 ("Pairing Failed Reason Codes") in the Bluetooth Core Specification 4.2, section 3.H.3.5.5 (@linkBLEcore).  */
+#define PM_CONN_SEC_ERROR_MIC_FAILURE        (PM_CONN_SEC_ERROR_BASE + 0x3D)  /**< @brief Encryption ended with disconnection because of mismatching keys or a stray packet during a procedure. See the SoftDevice GAP Message Sequence Charts on encryption (@linkBLEMSCgap), the Bluetooth Core Specification 4.2, sections 6.B.5.1.3.1 and 3.H.3.5.5 (@linkBLEcore), and @ref BLE_HCI_CONN_TERMINATED_DUE_TO_MIC_FAILURE. */
+#define PM_CONN_SEC_ERROR_DISCONNECT         (PM_CONN_SEC_ERROR_BASE + 0x100) /**< @brief Pairing or encryption did not finish before the link disconnected for an unrelated reason. */
+#define PM_CONN_SEC_ERROR_SMP_TIMEOUT        (PM_CONN_SEC_ERROR_BASE + 0x101) /**< @brief Pairing/bonding could not start because an SMP time-out has already happened on this link. This means that no more pairing or bonding can happen on this link. To be able to pair or bond, the link must be disconnected and then reconnected. See Bluetooth Core Specification 4.2 section 3.H.3.4 (@linkBLEcore). */
+ /** @} */
+
+
+
+/**@defgroup PM_PEER_ID_VERSIONS All versions of Peer IDs.
+ * @brief The data ID for each iteration of the data formats in flash.
+ * @details Each time the format (in flash) of a piece of peer data changes, the data ID will also
+ *          be updated. This list of defines is a record of each data ID that has ever existed, and
+ *          code that caters to legacy formats can find the relevant IDs here.
+ * @{ */
+#define PM_PEER_DATA_ID_FIRST_VX                   0     /**< @brief The smallest data ID. */
+#define PM_PEER_DATA_ID_BONDING_V1                 0     /**< @brief The data ID of the first version of bonding data. */
+#define PM_PEER_DATA_ID_BONDING_V2                 7     /**< @brief The data ID of the second version of bonding data. */
+#define PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING_V1 1     /**< @brief The data ID of the first version of the service changed pending flag. */
+#define PM_PEER_DATA_ID_GATT_LOCAL_V1              2     /**< @brief The data ID of the first version of local GATT data. */
+#define PM_PEER_DATA_ID_GATT_LOCAL_V2              8     /**< @brief The data ID of the second version of local GATT data. */
+#define PM_PEER_DATA_ID_GATT_REMOTE_V1             3     /**< @brief The data ID of the first version of remote GATT data. */
+#define PM_PEER_DATA_ID_APPLICATION_V1             4     /**< @brief The data ID of the first version of application data. */
+#define PM_PEER_DATA_ID_GATT_REMOTE_V2             5     /**< @brief The data ID of the second version of remote GATT data. */
+#define PM_PEER_DATA_ID_PEER_RANK_V1               6     /**< @brief The data ID of the first version of the rank. */
+#define PM_PEER_DATA_ID_LAST_VX                    9     /**< @brief The data ID after the last valid one. */
+#define PM_PEER_DATA_ID_INVALID_VX                 0xFF  /**< @brief A data ID guaranteed to be invalid. */
+/**@}*/
+
+
+/**@brief The different types of data associated with a peer.
+ */
+typedef enum
+{
+    PM_PEER_DATA_ID_FIRST                   = PM_PEER_DATA_ID_FIRST_VX,                   /**< @brief The smallest data ID. */
+    PM_PEER_DATA_ID_BONDING                 = PM_PEER_DATA_ID_BONDING_V2,                 /**< @brief The data ID for bonding data. See @ref pm_peer_data_bonding_t. */
+    PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING = PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING_V1, /**< @brief The data ID for service changed state. */
+    PM_PEER_DATA_ID_GATT_LOCAL              = PM_PEER_DATA_ID_GATT_LOCAL_V2,              /**< @brief The data ID for local GATT data (sys attributes). See @ref pm_peer_data_local_gatt_db_t. */
+    PM_PEER_DATA_ID_GATT_REMOTE             = PM_PEER_DATA_ID_GATT_REMOTE_V2,             /**< @brief The data ID for remote GATT data. */
+    PM_PEER_DATA_ID_PEER_RANK               = PM_PEER_DATA_ID_PEER_RANK_V1,               /**< @brief The data ID for peer rank. See @ref pm_peer_rank_highest. */
+    PM_PEER_DATA_ID_APPLICATION             = PM_PEER_DATA_ID_APPLICATION_V1,             /**< @brief The data ID for application data. */
+    PM_PEER_DATA_ID_LAST                    = PM_PEER_DATA_ID_LAST_VX,                    /**< @brief One more than the highest data ID. */
+    PM_PEER_DATA_ID_INVALID                 = PM_PEER_DATA_ID_INVALID_VX,                 /**< @brief A data ID guaranteed to be invalid. */
+} pm_peer_data_id_t;
+
+
+/**@brief Different procedures that can lead to an encrypted link.
+ */
+typedef enum
+{
+    PM_LINK_SECURED_PROCEDURE_ENCRYPTION, /**< @brief Using an LTK that was shared during a previous bonding procedure to encrypt the link. */
+    PM_LINK_SECURED_PROCEDURE_BONDING,    /**< @brief A pairing procedure, followed by a bonding procedure. */
+    PM_LINK_SECURED_PROCEDURE_PAIRING,    /**< @brief A pairing procedure with no bonding. */
+} pm_conn_sec_procedure_t;
+
+
+/**@brief Configuration of a security procedure.
+ */
+typedef struct
+{
+    bool allow_repairing; /** @brief Whether to allow the peer to pair if it wants to, but is already bonded. If this is false, the procedure is rejected, and no more events are sent. Default: false. */
+} pm_conn_sec_config_t;
+
+
+/**@brief Data associated with a bond to a peer.
+ */
+typedef struct
+{
+    uint8_t           own_role;    /**< @brief The BLE role of the local device during bonding. See @ref BLE_GAP_ROLES. */
+    ble_gap_id_key_t  peer_ble_id; /**< @brief The peer's Bluetooth address and identity resolution key (IRK). */
+    ble_gap_enc_key_t peer_ltk;    /**< @brief The peer's long-term encryption key (LTK) and master ID. */
+    ble_gap_enc_key_t own_ltk;     /**< @brief Locally generated long-term encryption key (LTK) and master ID, distributed to the peer. */
+} pm_peer_data_bonding_t;
+
+
+/**@brief Data on a local GATT database.
+ */
+typedef struct
+{
+    uint32_t flags;       /**< @brief Flags that describe the database attributes. */
+    uint16_t len;         /**< @brief Size of the attribute array. */
+    uint8_t  data[1];     /**< @brief Array to hold the database attributes. */
+} pm_peer_data_local_gatt_db_t;
+
+
+/**@brief Device Privacy.
+ *
+ *        The privacy feature provides a way for the device to avoid being tracked over a period of
+ *        time. The privacy feature, when enabled, hides the local device identity and replaces it
+ *        with a private address that is automatically refreshed at a specified interval.
+ *
+ *        If a device still wants to be recognized by other peers, it needs to share it's Identity
+ *        Resolving Key (IRK). With this key, a device can generate a random private address that
+ *        can only be recognized by peers in possession of that key, and devices can establish
+ *        connections without revealing their real identities.
+ *
+ * @note  If the device IRK is updated, the new IRK becomes the one to be distributed in all
+ *        bonding procedures performed after @ref sd_ble_gap_privacy_set returns.
+ *        The IRK distributed during bonding procedure is the device IRK that is active when @ref
+ *        sd_ble_gap_sec_params_reply is called.
+ */
+#if (NRF_SD_BLE_API_VERSION < 3)
+
+typedef struct
+{
+    uint8_t         privacy_mode;           /**< Privacy mode, see @ref BLE_GAP_PRIVACY_MODES. Default is @ref BLE_GAP_PRIVACY_MODE_OFF. */
+    uint8_t         private_addr_type;      /**< The private address type must be either @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE or @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE. */
+    uint16_t        private_addr_cycle_s;   /**< Private address cycle interval in seconds. Providing an address cycle value of 0 will use the default value defined by @ref BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S. */
+    ble_gap_irk_t * p_device_irk;           /**< When used as input, pointer to IRK structure that will be used as the default IRK. If NULL, the device default IRK will be used.
+                                                 When used as output, pointer to IRK structure where the current default IRK will be written to. If NULL, this argument is ignored.
+                                                 By default, the default IRK is used to generate random private resolvable addresses for the local device unless instructed otherwise. */
+} pm_privacy_params_t;
+
+
+/**@defgroup BLE_GAP_PRIVACY_MODES Privacy modes
+ * @{ */
+#define BLE_GAP_PRIVACY_MODE_OFF                0x00 /**< Device will send and accept its identity address for its own address. */
+#define BLE_GAP_PRIVACY_MODE_DEVICE_PRIVACY     0x01 /**< Device will send and accept only private addresses for its own address. */
+/**@} */
+
+#else
+
+typedef ble_gap_privacy_params_t pm_privacy_params_t;
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PEER_MANAGER_TYPES_H__ */
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/pm_buffer.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,150 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(PEER_MANAGER)
+#include "pm_buffer.h"
+
+#include <stdbool.h>
+#include <string.h>
+#include "nrf_error.h"
+#include "pm_mutex.h"
+
+
+#define BUFFER_IS_VALID(p_buffer) ((p_buffer != NULL)             \
+                                && (p_buffer->p_memory != NULL)   \
+                                && (p_buffer->p_mutex  != NULL))
+
+
+
+ret_code_t pm_buffer_init(pm_buffer_t * p_buffer,
+                          uint8_t     * p_buffer_memory,
+                          uint32_t      buffer_memory_size,
+                          uint8_t     * p_mutex_memory,
+                          uint32_t      mutex_memory_size,
+                          uint32_t      n_blocks,
+                          uint32_t      block_size)
+{
+    if (   (p_buffer           != NULL)
+        && (p_buffer_memory    != NULL)
+        && (p_mutex_memory     != NULL)
+        && (buffer_memory_size >= (n_blocks * block_size))
+        && (mutex_memory_size  >= MUTEX_STORAGE_SIZE(n_blocks))
+        && (n_blocks           != 0)
+        && (block_size         != 0))
+    {
+        p_buffer->p_memory   = p_buffer_memory;
+        p_buffer->p_mutex    = p_mutex_memory;
+        p_buffer->n_blocks   = n_blocks;
+        p_buffer->block_size = block_size;
+        pm_mutex_init(p_buffer->p_mutex, n_blocks);
+
+        return NRF_SUCCESS;
+    }
+    else
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+}
+
+
+uint8_t pm_buffer_block_acquire(pm_buffer_t * p_buffer, uint32_t n_blocks)
+{
+    if (!BUFFER_IS_VALID(p_buffer))
+    {
+        return ( PM_BUFFER_INVALID_ID );
+    }
+
+    uint8_t first_locked_mutex = PM_BUFFER_INVALID_ID;
+
+    for (uint8_t i = 0; i < p_buffer->n_blocks; i++)
+    {
+        if (pm_mutex_lock(p_buffer->p_mutex, i))
+        {
+            if (first_locked_mutex == PM_BUFFER_INVALID_ID)
+            {
+                first_locked_mutex = i;
+            }
+            if ((i - first_locked_mutex + 1) == n_blocks)
+            {
+                return first_locked_mutex;
+            }
+        }
+        else if (first_locked_mutex != PM_BUFFER_INVALID_ID)
+        {
+            for (uint8_t j = first_locked_mutex; j < i; j++)
+            {
+                pm_buffer_release(p_buffer, j);
+            }
+            first_locked_mutex = PM_BUFFER_INVALID_ID;
+        }
+    }
+
+    return ( PM_BUFFER_INVALID_ID );
+}
+
+
+uint8_t * pm_buffer_ptr_get(pm_buffer_t * p_buffer, uint8_t id)
+{
+    if (!BUFFER_IS_VALID(p_buffer))
+    {
+        return ( NULL );
+    }
+
+    if ( (id != PM_BUFFER_INVALID_ID)
+    &&   pm_mutex_lock_status_get(p_buffer->p_mutex, id) )
+    {
+        return ( &p_buffer->p_memory[id * p_buffer->block_size] );
+    }
+    else
+    {
+        return ( NULL );
+    }
+}
+
+
+void pm_buffer_release(pm_buffer_t * p_buffer, uint8_t id)
+{
+    if (    BUFFER_IS_VALID(p_buffer)
+       &&  (id != PM_BUFFER_INVALID_ID)
+       &&   pm_mutex_lock_status_get(p_buffer->p_mutex, id))
+    {
+        pm_mutex_unlock(p_buffer->p_mutex, id);
+    }
+}
+#endif // NRF_MODULE_ENABLED(PEER_MANAGER)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/pm_buffer.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,159 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef BUFFER_H__
+#define BUFFER_H__
+
+#include <stdint.h>
+#include "compiler_abstraction.h"
+#include "sdk_errors.h"
+#include "pm_mutex.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup pm_buffer Buffer
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. This module provides a simple buffer.
+ */
+
+
+#define PM_BUFFER_INVALID_ID 0xFF //!< Invalid buffer block ID.
+
+
+/**@brief Convenience macro for declaring memory and initializing a buffer instance.
+ *
+ * @param[out] p_buffer    The buffer instance to initialize.
+ * @param[in]  n_blocks    The desired number of blocks in the buffer.
+ * @param[in]  block_size  The desired block size of the buffer.
+ * @param[out] err_code    The return code from @ref pm_buffer_init.
+ */
+#define PM_BUFFER_INIT(p_buffer, n_blocks, block_size, err_code)          \
+do                                                                        \
+{                                                                         \
+    __ALIGN(4) static uint8_t buffer_memory[(n_blocks) * (block_size)];   \
+    __ALIGN(4) static uint8_t mutex_memory[MUTEX_STORAGE_SIZE(n_blocks)]; \
+    err_code = pm_buffer_init((p_buffer),                                 \
+                               buffer_memory,                             \
+                              (n_blocks) * (block_size),                  \
+                               mutex_memory,                              \
+                               MUTEX_STORAGE_SIZE(n_blocks),              \
+                              (n_blocks),                                 \
+                              (block_size));                              \
+} while (0)
+
+
+typedef struct
+{
+    uint8_t * p_memory;   /**< The storage for all buffer entries. The size of the buffer must be n_blocks*block_size. */
+    uint8_t * p_mutex;    /**< A mutex group with one mutex for each buffer entry. */
+    uint32_t  n_blocks;   /**< The number of allocatable blocks in the buffer. */
+    uint32_t  block_size; /**< The size of each block in the buffer. */
+} pm_buffer_t;
+
+/**@brief Function for initializing a buffer instance.
+ *
+ * @param[out] p_buffer            The buffer instance to initialize.
+ * @param[in]  p_buffer_memory     The memory this buffer will use.
+ * @param[in]  buffer_memory_size  The size of p_buffer_memory. This must be at least
+ *                                 n_blocks*block_size.
+ * @param[in]  p_mutex_memory      The memory for the mutexes. This must be at least
+ *                                 @ref MUTEX_STORAGE_SIZE(n_blocks).
+ * @param[in]  mutex_memory_size   The size of p_mutex_memory.
+ * @param[in]  n_blocks            The number of blocks in the buffer.
+ * @param[in]  block_size          The size of each block.
+ *
+ * @retval NRF_SUCCESS              Successfully initialized buffer instance.
+ * @retval NRF_ERROR_INVALID_PARAM  A parameter was 0 or NULL or a size was too small.
+ */
+ret_code_t pm_buffer_init(pm_buffer_t * p_buffer,
+                          uint8_t     * p_buffer_memory,
+                          uint32_t      buffer_memory_size,
+                          uint8_t     * p_mutex_memory,
+                          uint32_t      mutex_memory_size,
+                          uint32_t      n_blocks,
+                          uint32_t      block_size);
+
+
+/**@brief Function for acquiring a buffer block in a buffer.
+ *
+ * @param[in]  p_buffer  The buffer instance acquire from.
+ * @param[in]  n_blocks  The number of contiguous blocks to acquire.
+ *
+ * @return The id of the acquired block, if successful.
+ * @retval PM_BUFFER_INVALID_ID  If unsuccessful.
+ */
+uint8_t pm_buffer_block_acquire(pm_buffer_t * p_buffer, uint32_t n_blocks);
+
+
+/**@brief Function for getting a pointer to a specific buffer block.
+ *
+ * @param[in]  p_buffer  The buffer instance get from.
+ * @param[in]  id        The id of the buffer to get the pointer for.
+ *
+ * @return A pointer to the buffer for the specified id, if the id is valid.
+ * @retval NULL  If the id is invalid.
+ */
+uint8_t * pm_buffer_ptr_get(pm_buffer_t * p_buffer, uint8_t id);
+
+
+/**@brief Function for releasing a buffer block.
+ *
+ * @param[in]  p_buffer  The buffer instance containing the block to release.
+ * @param[in]  id        The id of the block to release.
+ */
+void pm_buffer_release(pm_buffer_t * p_buffer, uint8_t id);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // BUFFER_H__
+
+/**
+ * @}
+ * @endcond
+ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/pm_mutex.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,143 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(PEER_MANAGER)
+#include "pm_mutex.h"
+
+#include <stdbool.h>
+#include <string.h>
+#include "nrf_error.h"
+#include "app_util_platform.h"
+
+
+
+/**@brief Locks the mutex defined by the mask.
+ *
+ * @param p_mutex pointer to the mutex storage.
+ * @param mutex_mask the mask identifying the mutex position.
+ *
+ * @retval true if the mutex could be locked.
+ * @retval false if the mutex was already locked.
+ */
+static bool lock_by_mask(uint8_t * p_mutex, uint8_t mutex_mask)
+{
+    bool success = false;
+
+    if ( (*p_mutex & mutex_mask) == 0 )
+    {
+        CRITICAL_REGION_ENTER();
+        if ( (*p_mutex & mutex_mask) == 0 )
+        {
+            *p_mutex |= mutex_mask;
+
+            success = true;
+        }
+        CRITICAL_REGION_EXIT();
+    }
+
+    return ( success );
+}
+
+
+void pm_mutex_init(uint8_t * p_mutex, uint16_t mutex_size)
+{
+    if (p_mutex != NULL)
+    {
+        memset(&p_mutex[0], 0, MUTEX_STORAGE_SIZE(mutex_size));
+    }
+}
+
+
+bool pm_mutex_lock(uint8_t * p_mutex, uint16_t mutex_id)
+{
+    if (p_mutex != NULL)
+    {
+        return ( lock_by_mask(&(p_mutex[mutex_id >> 3]), (1 << (mutex_id & 0x07))) );
+    }
+    else
+    {
+        return false;
+    }
+}
+
+
+void pm_mutex_unlock(uint8_t * p_mutex, uint16_t mutex_id)
+{
+    uint8_t mutex_base = mutex_id >> 3;
+    uint8_t mutex_mask = (1 << (mutex_id & 0x07));
+
+    if   ((p_mutex != NULL)
+       && (p_mutex[mutex_base] & mutex_mask))
+    {
+        CRITICAL_REGION_ENTER();
+        p_mutex[mutex_base] &= ~mutex_mask;
+        CRITICAL_REGION_EXIT();
+    }
+}
+
+
+uint16_t pm_mutex_lock_first_available(uint8_t * p_mutex, uint16_t mutex_size)
+{
+    if (p_mutex != NULL)
+    {
+        for ( uint16_t i = 0; i < mutex_size; i++ )
+        {
+            if ( lock_by_mask(&(p_mutex[i >> 3]), 1 << (i & 0x07)) )
+            {
+                return ( i );
+            }
+        }
+    }
+
+    return ( mutex_size );
+}
+
+
+bool pm_mutex_lock_status_get(uint8_t * p_mutex, uint16_t mutex_id)
+{
+    if (p_mutex != NULL)
+    {
+        return ( (p_mutex[mutex_id >> 3] & (1 << (mutex_id & 0x07))) );
+    }
+    else
+    {
+        return true;
+    }
+}
+#endif // NRF_MODULE_ENABLED(PEER_MANAGER)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/pm_mutex.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,125 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef MUTEX_H__
+#define MUTEX_H__
+
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup pm_mutex Mutex
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. This module provides thread-safe mutexes.
+ */
+
+
+/**@brief Defines the storage size of a specified mutex group.
+ *
+ * @param number_of_mutexes the number of mutexes in the group.
+ */
+#define MUTEX_STORAGE_SIZE(number_of_mutexes) ((7 + (number_of_mutexes)) >> 3)
+
+
+/**@brief Initializes a mutex group.
+ *
+ * @param[in] p_mutex     Pointer to the mutex group. See @ref MUTEX_STORAGE_SIZE().
+ * @param[in] mutex_size  The size of the mutex group in number of mutexes.
+ */
+void pm_mutex_init(uint8_t * p_mutex, uint16_t mutex_size);
+
+
+/**@brief Locks the mutex specified by the bit id.
+ *
+ * @param[inout] p_mutex       Pointer to the mutex group.
+ * @param[in]    mutex_bit_id  The bit id of the mutex.
+ *
+ * @retval true   if it was possible to lock the mutex.
+ * @retval false  otherwise.
+ */
+bool pm_mutex_lock(uint8_t * p_mutex, uint16_t mutex_bit_id);
+
+
+/**@brief Locks the first unlocked mutex within the mutex group.
+ *
+ * @param[in, out] p_mutex     Pointer to the mutex group.
+ * @param[in]      mutex_size  The size of the mutex group.
+ *
+ * @return The first unlocked mutex id in the group.
+ * @retval group-size  if there was no unlocked mutex available.
+ */
+uint16_t pm_mutex_lock_first_available(uint8_t * p_mutex, uint16_t mutex_size);
+
+
+/**@brief Unlocks the mutex specified by the bit id.
+ *
+ * @param[in, out] p_mutex       Pointer to the mutex group.
+ * @param[in]      mutex_bit_id  The bit id of the mutex.
+ */
+void pm_mutex_unlock(uint8_t * p_mutex, uint16_t mutex_bit_id);
+
+
+/**@brief Gets the locking status of the specified mutex.
+ *
+ * @param[in, out] p_mutex      Pointer to the mutex group.
+ * @param[in]      mutex_bit_id The bit id of the mutex.
+ *
+ * @retval true   if the mutex was locked.
+ * @retval false  otherwise.
+ */
+bool pm_mutex_lock_status_get(uint8_t * p_mutex, uint16_t mutex_bit_id);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // MUTEX_H__
+
+/** @}
+ * @endcond
+ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/security_dispatcher.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,897 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(PEER_MANAGER)
+#include "security_dispatcher.h"
+
+#include <string.h>
+#include "headers/ble.h"
+#include "ble_gap.h"
+#include "ble_conn_state.h"
+#include "peer_manager_types.h"
+#include "peer_database.h"
+#include "id_manager.h"
+
+
+// The number of registered event handlers.
+#define SMD_EVENT_HANDLERS_CNT      (sizeof(m_evt_handlers) / sizeof(m_evt_handlers[0]))
+
+
+// Security Dispacher event handlers in Security Manager and GATT Cache Manager.
+extern void sm_smd_evt_handler(smd_evt_t const * p_event);
+extern void gcm_smd_evt_handler(smd_evt_t const * p_event);
+
+// Security Dispatcher events' handlers.
+// The number of elements in this array is SMD_EVENT_HANDLERS_CNT.
+static smd_evt_handler_t const m_evt_handlers[] =
+{
+    sm_smd_evt_handler,
+    gcm_smd_evt_handler
+};
+
+static bool                          m_module_initialized;
+
+static ble_conn_state_user_flag_id_t m_flag_sec_proc          = BLE_CONN_STATE_USER_FLAG_INVALID;
+static ble_conn_state_user_flag_id_t m_flag_sec_proc_pairing  = BLE_CONN_STATE_USER_FLAG_INVALID;
+static ble_conn_state_user_flag_id_t m_flag_sec_proc_new_peer = BLE_CONN_STATE_USER_FLAG_INVALID;
+
+static ble_gap_lesc_p256_pk_t        m_peer_pk;
+
+
+static void evt_send(smd_evt_t * p_event)
+{
+    for (uint32_t i = 0; i < SMD_EVENT_HANDLERS_CNT; i++)
+    {
+        m_evt_handlers[i](p_event);
+    }
+}
+
+
+static void sec_start_send(uint16_t conn_handle, pm_conn_sec_procedure_t procedure)
+{
+    smd_evt_t evt =
+    {
+        .evt_id      = SMD_EVT_SEC_PROCEDURE_START,
+        .conn_handle = conn_handle,
+        .params      = {.sec_procedure_start = {.procedure = procedure}}
+    };
+    evt_send(&evt);
+}
+
+
+/**@brief Event handler for events from the Peer Database module.
+ *        This handler is extern in Peer Database.
+ *
+ * @param[in]  p_event   The event that has happened.
+ */
+void smd_pdb_evt_handler(pdb_evt_t const * p_event)
+{
+    if ((p_event->evt_id == PDB_EVT_WRITE_BUF_STORED) && (p_event->data_id == PM_PEER_DATA_ID_BONDING))
+    {
+        smd_evt_t evt =
+        {
+            .evt_id      = SMD_EVT_BONDING_INFO_STORED,
+            .conn_handle = im_conn_handle_get(p_event->peer_id),
+            .params      = {.bonding_info_stored = {.peer_id = p_event->peer_id}}
+        };
+        evt_send(&evt);
+    }
+}
+
+
+/**@brief Function for processing the @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST event from the SoftDevice.
+ *
+ * @param[in]  p_gap_evt  The event from the SoftDevice.
+ */
+static void sec_params_request_process(ble_gap_evt_t * p_gap_evt)
+{
+    smd_evt_t evt =
+    {
+        .evt_id      = SMD_EVT_PARAMS_REQ,
+        .conn_handle = p_gap_evt->conn_handle
+    };
+    evt_send(&evt);
+    return;
+}
+
+
+/**@brief Function for administrative actions to be taken when a security process has been attempted.
+ *
+ * @param[in]  conn_handle       The connection the security process was attempted on.
+ * @param[in]  peer_id           The peer ID given to the connected peer.
+ * @param[in]  success           Whether the process was started successfully.
+ * @param[in]  pairing           Whether the process was a pairing process.
+ * @param[in]  new_peer_created  Whether a new peer was created during the process attempt.
+ */
+static void sec_proc_start(uint16_t     conn_handle,
+                           pm_peer_id_t peer_id,
+                           bool         success,
+                           bool         pairing,
+                           bool         new_peer_created)
+{
+    ble_conn_state_user_flag_set(conn_handle, m_flag_sec_proc, success);
+
+    if (success)
+    {
+        ble_conn_state_user_flag_set(conn_handle, m_flag_sec_proc_pairing, pairing);
+        ble_conn_state_user_flag_set(conn_handle, m_flag_sec_proc_new_peer, new_peer_created);
+
+        if (new_peer_created)
+        {
+            im_new_peer_id(conn_handle, peer_id);
+        }
+    }
+    else
+    {
+        if (new_peer_created)
+        {
+            ret_code_t err_code = im_peer_free(peer_id); // Attempt to free allocated peer.
+            UNUSED_VARIABLE(err_code);
+        }
+    }
+}
+
+
+
+/**@brief Function for processing the @ref BLE_GAP_EVT_SEC_INFO_REQUEST event from the SoftDevice.
+ *
+ * @param[in]  p_gap_evt  The event from the SoftDevice.
+ */
+static void sec_info_request_process(ble_gap_evt_t * p_gap_evt)
+{
+    ret_code_t                 err_code;
+    ble_gap_enc_info_t const * p_enc_info = NULL;
+    pm_peer_data_flash_t       peer_data;
+    pm_peer_id_t               peer_id = im_peer_id_get_by_master_id(&p_gap_evt->params.sec_info_request.master_id);
+    smd_evt_t evt;
+
+    evt.conn_handle = p_gap_evt->conn_handle;
+
+    if (peer_id == PM_PEER_ID_INVALID)
+    {
+        peer_id = im_peer_id_get_by_conn_handle(p_gap_evt->conn_handle);
+    }
+
+    if (peer_id != PM_PEER_ID_INVALID)
+    {
+        err_code = pdb_peer_data_ptr_get(peer_id, PM_PEER_DATA_ID_BONDING, &peer_data);
+
+        if (err_code == NRF_SUCCESS)
+        {
+            // There is stored bonding data for this peer.
+            ble_gap_enc_key_t const * p_existing_key = &peer_data.p_bonding_data->own_ltk;
+
+            if (   p_existing_key->enc_info.lesc
+                || (im_master_ids_compare(&p_existing_key->master_id,
+                                          &p_gap_evt->params.sec_info_request.master_id)))
+            {
+                p_enc_info = &p_existing_key->enc_info;
+            }
+        }
+    }
+
+    // All return values from the following can be safely ignored.
+    err_code = sd_ble_gap_sec_info_reply(p_gap_evt->conn_handle, p_enc_info, NULL, NULL);
+
+    if (err_code != NRF_SUCCESS)
+    {
+        evt.evt_id                        = SMD_EVT_ERROR_UNEXPECTED;
+        evt.params.error_unexpected.error = err_code;
+
+        evt_send(&evt);
+    }
+    else if (p_enc_info == NULL)
+    {
+        evt.evt_id                                  = SMD_EVT_LINK_ENCRYPTION_FAILED;
+        evt.params.link_encryption_failed.error     = PM_CONN_SEC_ERROR_PIN_OR_KEY_MISSING;
+        evt.params.link_encryption_failed.error_src = BLE_GAP_SEC_STATUS_SOURCE_LOCAL;
+
+        evt_send(&evt);
+
+        sec_proc_start(p_gap_evt->conn_handle, peer_id, false, false, false);
+    }
+    else
+    {
+        sec_start_send(p_gap_evt->conn_handle, PM_LINK_SECURED_PROCEDURE_ENCRYPTION);
+
+        sec_proc_start(p_gap_evt->conn_handle, peer_id, err_code == NRF_SUCCESS, false, false);
+    }
+
+
+    return;
+}
+
+
+/**@brief Function for processing the @ref BLE_GAP_EVT_SEC_REQUEST event from the SoftDevice.
+ *
+ * @param[in]  p_gap_evt  The event from the SoftDevice.
+ */
+static void sec_request_process(ble_gap_evt_t * p_gap_evt)
+{
+    smd_evt_t evt =
+    {
+        .evt_id = SMD_EVT_SLAVE_SECURITY_REQ,
+        .conn_handle = p_gap_evt->conn_handle,
+        .params =
+        {
+            .slave_security_req =
+            {
+                .bond = p_gap_evt->params.sec_request.bond,
+                .mitm = p_gap_evt->params.sec_request.mitm,
+            }
+        }
+    };
+    evt_send(&evt);
+    return;
+}
+
+
+/**@brief Function for processing the @ref BLE_GAP_EVT_AUTH_STATUS event from the SoftDevice, when
+ *        the auth_status is success.
+ *
+ * @param[in]  p_gap_evt  The event from the SoftDevice.
+ */
+static void auth_status_success_process(ble_gap_evt_t * p_gap_evt)
+{
+    ret_code_t           err_code   = NRF_SUCCESS;
+    uint8_t              role       = ble_conn_state_role(p_gap_evt->conn_handle);
+    pm_peer_id_t         peer_id    = im_peer_id_get_by_conn_handle(p_gap_evt->conn_handle);
+    ble_gap_sec_kdist_t  kdist_own  = p_gap_evt->params.auth_status.kdist_own;
+    ble_gap_sec_kdist_t  kdist_peer = p_gap_evt->params.auth_status.kdist_peer;
+
+    ble_conn_state_user_flag_set(p_gap_evt->conn_handle, m_flag_sec_proc, false);
+
+    if (role == BLE_GAP_ROLE_INVALID)
+    {
+        /* Unlikely, but maybe possible? */
+        return;
+    }
+
+    if (p_gap_evt->params.auth_status.bonded)
+    {
+
+        err_code = pdb_write_buf_store(peer_id, PM_PEER_DATA_ID_BONDING);
+        if (err_code != NRF_SUCCESS)
+        {
+            /* Unexpected */
+            smd_evt_t error_evt;
+
+            error_evt.evt_id                            = SMD_EVT_ERROR_BONDING_INFO;
+            error_evt.conn_handle                       = p_gap_evt->conn_handle;
+            error_evt.params.error_bonding_info.peer_id = peer_id;
+            error_evt.params.error_bonding_info.error   = err_code;
+
+            evt_send(&error_evt);
+        }
+
+    }
+    else if (ble_conn_state_user_flag_get(p_gap_evt->conn_handle, m_flag_sec_proc_new_peer))
+    {
+        ret_code_t err_code_free = im_peer_free(peer_id);
+        UNUSED_VARIABLE(err_code_free); // Errors can be safely ignored.
+    }
+
+    smd_evt_t pairing_success_evt;
+
+    pairing_success_evt.evt_id                            = SMD_EVT_PAIRING_SUCCESS;
+    pairing_success_evt.conn_handle                       = p_gap_evt->conn_handle;
+    pairing_success_evt.params.pairing_success.bonded     = p_gap_evt->params.auth_status.bonded;
+    pairing_success_evt.params.pairing_success.mitm       = p_gap_evt->params.auth_status.sm1_levels.lv3;
+    pairing_success_evt.params.pairing_success.kdist_own  = kdist_own;
+    pairing_success_evt.params.pairing_success.kdist_peer = kdist_peer;
+
+    evt_send(&pairing_success_evt);
+    return;
+}
+
+
+/**@brief Function for cleaning up after a failed pairing procedure.
+ *
+ * @param[in]  conn_handle  The handle of the connection the pairing procedure happens on.
+ * @param[in]  peer_id      The peer id used in the pairing procedure.
+ * @param[in]  error        The error the procedure failed with.
+ * @param[in]  error_src    The party that raised the error. See @ref BLE_GAP_SEC_STATUS_SOURCES.
+ */
+static void pairing_failure(uint16_t            conn_handle,
+                            pm_peer_id_t        peer_id,
+                            pm_sec_error_code_t error,
+                            uint8_t             error_src)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+
+    smd_evt_t evt =
+    {
+        .evt_id      = SMD_EVT_PAIRING_FAIL,
+        .conn_handle = conn_handle,
+        .params =
+        {
+            .pairing_failed =
+            {
+                .error     = error,
+                .error_src = error_src,
+            }
+        }
+    };
+
+    if (ble_conn_state_user_flag_get(conn_handle, m_flag_sec_proc_new_peer))
+    {
+        // The peer_id was created during the procedure, and should be freed, because no data is
+        // stored under it.
+        err_code = im_peer_free(peer_id);  // Attempt to free allocated peer.
+        UNUSED_VARIABLE(err_code);
+    }
+    else
+    {
+        err_code = pdb_write_buf_release(peer_id, PM_PEER_DATA_ID_BONDING);
+        if ((err_code != NRF_SUCCESS) && (err_code == NRF_ERROR_NOT_FOUND /* No buffer was allocated */))
+        {
+            smd_evt_t error_evt;
+            error_evt.evt_id = SMD_EVT_ERROR_UNEXPECTED;
+            error_evt.conn_handle = conn_handle;
+            error_evt.params.error_unexpected.error = err_code;
+            evt_send(&error_evt);
+        }
+    }
+
+    ble_conn_state_user_flag_set(conn_handle, m_flag_sec_proc, false);
+
+    evt_send(&evt);
+    return;
+}
+
+
+/**@brief Function for cleaning up after a failed encryption procedure.
+ *
+ * @param[in]  conn_handle  The handle of the connection the encryption procedure happens on.
+ * @param[in]  error        The error the procedure failed with.
+ * @param[in]  error_src    The party that raised the error. See @ref BLE_GAP_SEC_STATUS_SOURCES.
+ */
+static void encryption_failure(uint16_t            conn_handle,
+                               pm_sec_error_code_t error,
+                               uint8_t             error_src)
+{
+    smd_evt_t evt =
+    {
+        .evt_id = SMD_EVT_LINK_ENCRYPTION_FAILED,
+        .conn_handle = conn_handle,
+        .params =
+        {
+            .link_encryption_failed =
+            {
+                .error     = error,
+                .error_src = error_src,
+            }
+        }
+    };
+
+    ble_conn_state_user_flag_set(conn_handle, m_flag_sec_proc, false);
+
+    evt_send(&evt);
+    return;
+}
+
+
+/**@brief Function for possibly cleaning up after a failed pairing or encryption procedure.
+ *
+ * @param[in]  conn_handle  The handle of the connection the pairing procedure happens on.
+ * @param[in]  peer_id      The peer id used in the pairing procedure.
+ * @param[in]  error        The error the procedure failed with.
+ * @param[in]  error_src    The party that raised the error. See @ref BLE_GAP_SEC_STATUS_SOURCES.
+ */
+static void link_secure_failure(uint16_t            conn_handle,
+                                pm_sec_error_code_t error,
+                                uint8_t             error_src)
+{
+    if (ble_conn_state_user_flag_get(conn_handle, m_flag_sec_proc))
+    {
+        pm_peer_id_t  peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+
+        if (peer_id != PM_PEER_ID_INVALID)
+        {
+            if (ble_conn_state_user_flag_get(conn_handle, m_flag_sec_proc_pairing))
+            {
+                pairing_failure(conn_handle, peer_id, error, error_src);
+            }
+            else
+            {
+                encryption_failure(conn_handle, error, error_src);
+            }
+        }
+    }
+}
+
+
+/**@brief Function for processing the @ref BLE_GAP_EVT_DISCONNECT event from the SoftDevice.
+ *
+ * @param[in]  p_gap_evt  The event from the SoftDevice.
+ */
+static void disconnect_process(ble_gap_evt_t * p_gap_evt)
+{
+    pm_sec_error_code_t error = (p_gap_evt->params.disconnected.reason
+                                        == BLE_HCI_CONN_TERMINATED_DUE_TO_MIC_FAILURE)
+                                ? PM_CONN_SEC_ERROR_MIC_FAILURE : PM_CONN_SEC_ERROR_DISCONNECT;
+
+    link_secure_failure(p_gap_evt->conn_handle, error, BLE_GAP_SEC_STATUS_SOURCE_LOCAL);
+}
+
+
+/**@brief Function for processing the @ref BLE_GAP_EVT_AUTH_STATUS event from the SoftDevice, when
+ *        the auth_status is failure.
+ *
+ * @param[in]  p_gap_evt  The event from the SoftDevice.
+ */
+static void auth_status_failure_process(ble_gap_evt_t * p_gap_evt)
+{
+    link_secure_failure(p_gap_evt->conn_handle,
+                        p_gap_evt->params.auth_status.auth_status,
+                        p_gap_evt->params.auth_status.error_src);
+}
+
+
+/**@brief Function for processing the @ref BLE_GAP_EVT_AUTH_STATUS event from the SoftDevice.
+ *
+ * @param[in]  p_gap_evt  The event from the SoftDevice.
+ */
+static void auth_status_process(ble_gap_evt_t * p_gap_evt)
+{
+    switch (p_gap_evt->params.auth_status.auth_status)
+    {
+        case BLE_GAP_SEC_STATUS_SUCCESS:
+            auth_status_success_process(p_gap_evt);
+            break;
+
+        default:
+            auth_status_failure_process(p_gap_evt);
+            break;
+    }
+}
+
+
+/**@brief Function for processing the @ref BLE_GAP_EVT_CONN_SEC_UPDATE event from the SoftDevice.
+ *
+ * @param[in]  p_gap_evt  The event from the SoftDevice.
+ */
+static void conn_sec_update_process(ble_gap_evt_t * p_gap_evt)
+{
+    if (ble_conn_state_encrypted(p_gap_evt->conn_handle))
+    {
+        if (!ble_conn_state_user_flag_get(p_gap_evt->conn_handle, m_flag_sec_proc_pairing))
+        {
+            ble_conn_state_user_flag_set(p_gap_evt->conn_handle, m_flag_sec_proc, false);
+        }
+
+        smd_evt_t evt;
+
+        evt.conn_handle = p_gap_evt->conn_handle;
+        evt.evt_id = SMD_EVT_LINK_ENCRYPTION_UPDATE;
+        evt.params.link_encryption_update.mitm_protected
+                                = ble_conn_state_mitm_protected(p_gap_evt->conn_handle);
+        evt_send(&evt);
+    }
+    else
+    {
+        encryption_failure(p_gap_evt->conn_handle,
+                           PM_CONN_SEC_ERROR_PIN_OR_KEY_MISSING,
+                           BLE_GAP_SEC_STATUS_SOURCE_REMOTE);
+    }
+}
+
+
+/**@brief Funtion for initializing a BLE Connection State user flag.
+ *
+ * @param[out] flag_id  The flag to initialize.
+ */
+static void flag_id_init(ble_conn_state_user_flag_id_t * p_flag_id)
+{
+    if (*p_flag_id == BLE_CONN_STATE_USER_FLAG_INVALID)
+    {
+        *p_flag_id = ble_conn_state_user_flag_acquire();
+    }
+}
+
+
+ret_code_t smd_init(void)
+{
+    NRF_PM_DEBUG_CHECK(!m_module_initialized);
+
+    flag_id_init(&m_flag_sec_proc);
+    flag_id_init(&m_flag_sec_proc_pairing);
+    flag_id_init(&m_flag_sec_proc_new_peer);
+
+    if ((m_flag_sec_proc          == BLE_CONN_STATE_USER_FLAG_INVALID) ||
+        (m_flag_sec_proc_pairing  == BLE_CONN_STATE_USER_FLAG_INVALID) ||
+        (m_flag_sec_proc_new_peer == BLE_CONN_STATE_USER_FLAG_INVALID))
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    m_module_initialized = true;
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t smd_params_reply(uint16_t                 conn_handle,
+                            ble_gap_sec_params_t   * p_sec_params,
+                            ble_gap_lesc_p256_pk_t * p_public_key)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    uint8_t              role = ble_conn_state_role(conn_handle);
+    pm_peer_id_t         peer_id = PM_PEER_ID_INVALID;
+    ret_code_t           err_code = NRF_SUCCESS;
+    uint8_t              sec_status = BLE_GAP_SEC_STATUS_SUCCESS;
+    ble_gap_sec_keyset_t sec_keyset;
+    bool                 new_peer_created = false;
+
+    memset(&sec_keyset, 0, sizeof(ble_gap_sec_keyset_t));
+
+    if (role == BLE_GAP_ROLE_INVALID)
+    {
+        return BLE_ERROR_INVALID_CONN_HANDLE;
+    }
+
+    if (p_sec_params == NULL)
+    {
+        // NULL params means reject pairing.
+        sec_status = BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP;
+    }
+    else if (p_sec_params->bond)
+    {
+        // Bonding is to be performed, prepare to receive bonding data.
+        pm_peer_data_t       peer_data;
+
+        peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+
+        if (peer_id == PM_PEER_ID_INVALID)
+        {
+            // Peer is unknown to us, allocate a new peer ID for it.
+            peer_id = pdb_peer_allocate();
+            if (peer_id != PM_PEER_ID_INVALID)
+            {
+                new_peer_created = true;
+            }
+            else
+            {
+                err_code = NRF_ERROR_INTERNAL;
+            }
+        }
+
+        if (err_code == NRF_SUCCESS)
+        {
+            // Peer ID is ready, acquire a memory buffer to receive bonding data into.
+            err_code = pdb_write_buf_get(peer_id, PM_PEER_DATA_ID_BONDING, 1, &peer_data);
+            if (err_code == NRF_SUCCESS)
+            {
+                memset(peer_data.p_bonding_data, 0, sizeof(pm_peer_data_bonding_t));
+
+                peer_data.p_bonding_data->own_role = role;
+
+                sec_keyset.keys_own.p_enc_key  = &peer_data.p_bonding_data->own_ltk;
+                sec_keyset.keys_own.p_pk       = p_public_key;
+                sec_keyset.keys_peer.p_enc_key = &peer_data.p_bonding_data->peer_ltk;
+                sec_keyset.keys_peer.p_id_key  = &peer_data.p_bonding_data->peer_ble_id;
+                sec_keyset.keys_peer.p_pk      = &m_peer_pk;
+
+                // Retrieve the address the peer used during connection establishment.
+                // This address will be overwritten if ID is shared. Should not fail.
+                ret_code_t err_code_addr = im_ble_addr_get(conn_handle,
+                    &peer_data.p_bonding_data->peer_ble_id.id_addr_info);
+                UNUSED_VARIABLE(err_code_addr);
+
+                // Buffer is OK, reserve room in flash for the data.
+                err_code = pdb_write_buf_store_prepare(peer_id, PM_PEER_DATA_ID_BONDING);
+            }
+        }
+    }
+    else
+    {
+        // Pairing, no bonding.
+
+        sec_keyset.keys_own.p_pk  = p_public_key;
+        sec_keyset.keys_peer.p_pk = &m_peer_pk;
+    }
+
+    if (err_code == NRF_SUCCESS)
+    {
+        // Everything OK, reply to SoftDevice. If an error happened, the user is given an
+        // opportunity to change the parameters and retry the call.
+        if (role == BLE_GAP_ROLE_CENTRAL)
+        {
+            err_code = sd_ble_gap_sec_params_reply(conn_handle, sec_status, NULL, &sec_keyset);
+        }
+        else
+        {
+            err_code = sd_ble_gap_sec_params_reply(conn_handle, sec_status, p_sec_params, &sec_keyset);
+
+            if ((p_sec_params != NULL) && (err_code == NRF_SUCCESS))
+            {
+                pm_conn_sec_procedure_t procedure = p_sec_params->bond
+                                               ? PM_LINK_SECURED_PROCEDURE_BONDING
+                                               : PM_LINK_SECURED_PROCEDURE_PAIRING;
+                sec_start_send(conn_handle, procedure);
+            }
+        }
+    }
+
+    sec_proc_start(conn_handle,
+                   peer_id,
+                   (err_code == NRF_SUCCESS) && (sec_status != BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP),
+                   true,
+                   new_peer_created);
+
+    return err_code;
+}
+
+
+static ret_code_t link_secure_central_existing_peer(uint16_t                  conn_handle,
+                                                    ble_gap_sec_params_t    * p_sec_params,
+                                                    bool                      force_repairing,
+                                                    pm_peer_id_t              peer_id,
+                                                    pm_conn_sec_procedure_t * procedure)
+{
+    pm_peer_data_flash_t      peer_data;
+    pm_peer_data_t            dummy_peer_data;
+    ret_code_t                err_code;
+    ble_gap_enc_key_t const * p_existing_key = NULL;
+    bool                      lesc = false;
+
+    err_code = pdb_peer_data_ptr_get(peer_id, PM_PEER_DATA_ID_BONDING, &peer_data);
+
+    if (err_code == NRF_SUCCESS)
+    {
+        // Use peer's key since they are peripheral.
+        p_existing_key = &(peer_data.p_bonding_data->peer_ltk);
+
+        lesc = peer_data.p_bonding_data->own_ltk.enc_info.lesc;
+        if  (lesc) // LESC was used during bonding.
+        {
+            // For LESC, always use own key.
+            p_existing_key = &(peer_data.p_bonding_data->own_ltk);
+        }
+    }
+
+    if     (!force_repairing
+         && (err_code == NRF_SUCCESS)
+         && (p_existing_key != NULL)
+         && (lesc || im_master_id_is_valid(&(p_existing_key->master_id)))) /* There is a valid LTK stored. */
+         //&& (p_existing_key->enc_info.auth >= p_sec_params->mitm)          /* The requested MITM security is at or below the existing level. */
+         //&& (!p_sec_params->mitm || (lesc >= p_sec_params->lesc)))         /* The requested LESC security is at or below the existing level. We only care about LESC if MITM is required. */
+    {
+        err_code = sd_ble_gap_encrypt(conn_handle, &(p_existing_key->master_id), &(p_existing_key->enc_info));
+
+        *procedure = PM_LINK_SECURED_PROCEDURE_ENCRYPTION;
+    }
+    else if ((err_code == NRF_SUCCESS) || (err_code == NRF_ERROR_NOT_FOUND))
+    {
+        /* Re-pairing is needed, because there is no LTK available or the existing key is not
+           secure enough */
+        err_code = NRF_SUCCESS;
+
+        if (p_sec_params->bond)
+        {
+            err_code = pdb_write_buf_get(peer_id, PM_PEER_DATA_ID_BONDING, 1, &dummy_peer_data);
+            if (err_code == NRF_SUCCESS)
+            {
+                err_code = pdb_write_buf_store_prepare(peer_id, PM_PEER_DATA_ID_BONDING);
+            }
+        }
+
+        if (err_code == NRF_SUCCESS)
+        {
+            err_code = sd_ble_gap_authenticate(conn_handle, p_sec_params);
+        }
+
+        if (err_code != NRF_SUCCESS)
+        {
+            ret_code_t err_code_release = pdb_write_buf_release(peer_id, PM_PEER_DATA_ID_BONDING);
+            if ((err_code_release != NRF_SUCCESS) && (err_code_release != NRF_ERROR_NOT_FOUND))
+            {
+                err_code = NRF_ERROR_INTERNAL;
+            }
+        }
+    }
+
+    sec_proc_start(conn_handle,
+                   peer_id,
+                   err_code == NRF_SUCCESS,
+                   *procedure != PM_LINK_SECURED_PROCEDURE_ENCRYPTION,
+                   false);
+
+    return err_code;
+}
+
+
+static ret_code_t link_secure_central_new_peer(uint16_t               conn_handle,
+                                               ble_gap_sec_params_t * p_sec_params)
+{
+    pm_peer_id_t    peer_id = pdb_peer_allocate();
+    pm_peer_data_t  dummy_peer_data;
+    ret_code_t      err_code;
+
+    if (peer_id != PM_PEER_ID_INVALID)
+    {
+        err_code = pdb_write_buf_get(peer_id, PM_PEER_DATA_ID_BONDING, 1, &dummy_peer_data);
+        if (err_code == NRF_SUCCESS)
+        {
+            err_code = pdb_write_buf_store_prepare(peer_id, PM_PEER_DATA_ID_BONDING);
+        }
+
+        if (err_code == NRF_SUCCESS)
+        {
+            err_code = sd_ble_gap_authenticate(conn_handle, p_sec_params);
+        }
+
+        if (err_code != NRF_SUCCESS)
+        {
+            ret_code_t err_code_free = pdb_write_buf_release(peer_id, PM_PEER_DATA_ID_BONDING);
+            if ((err_code_free != NRF_SUCCESS) && (err_code_free != NRF_ERROR_NOT_FOUND))
+            {
+                err_code = NRF_ERROR_INTERNAL;
+            }
+        }
+    }
+    else
+    {
+        err_code = NRF_ERROR_INTERNAL;
+    }
+
+    sec_proc_start(conn_handle,
+                   peer_id,
+                   err_code == NRF_SUCCESS,
+                   true,
+                   peer_id != PM_PEER_ID_INVALID);
+
+    return err_code;
+}
+
+
+static ret_code_t link_secure_central(uint16_t               conn_handle,
+                                      ble_gap_sec_params_t * p_sec_params,
+                                      bool                   force_repairing)
+{
+    ret_code_t           err_code;
+    pm_peer_id_t         peer_id;
+
+    if (p_sec_params == NULL)
+    {
+        return sd_ble_gap_authenticate(conn_handle, NULL);
+    }
+
+    pm_conn_sec_procedure_t procedure = p_sec_params->bond ? PM_LINK_SECURED_PROCEDURE_BONDING
+                                                           : PM_LINK_SECURED_PROCEDURE_PAIRING;
+
+    peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+
+    if (peer_id != PM_PEER_ID_INVALID)
+    {
+        // There is already data in flash for this peer.
+        err_code = link_secure_central_existing_peer(conn_handle,
+                                                     p_sec_params,
+                                                     force_repairing,
+                                                     peer_id,
+                                                     &procedure);
+    }
+    else if (p_sec_params->bond)
+    {
+        // New peer is required.
+        err_code = link_secure_central_new_peer(conn_handle, p_sec_params);
+    }
+    else
+    {
+        // No bonding, only pairing.
+        err_code = sd_ble_gap_authenticate(conn_handle, p_sec_params);
+
+        sec_proc_start(conn_handle, peer_id, err_code == NRF_SUCCESS, true, false);
+    }
+
+    if (err_code == NRF_SUCCESS)
+    {
+        sec_start_send(conn_handle, procedure);
+    }
+
+    return err_code;
+}
+
+
+static ret_code_t link_secure_peripheral(uint16_t conn_handle, ble_gap_sec_params_t * p_sec_params)
+{
+    // This should never happen for a peripheral.
+    NRF_PM_DEBUG_CHECK(p_sec_params != NULL);
+
+    // VERIFY_PARAM_NOT_NULL(p_sec_params);
+
+    ret_code_t err_code = sd_ble_gap_authenticate(conn_handle, p_sec_params);
+
+    return err_code;
+}
+
+
+ret_code_t smd_link_secure(uint16_t               conn_handle,
+                           ble_gap_sec_params_t * p_sec_params,
+                           bool                   force_repairing)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    uint8_t role = ble_conn_state_role(conn_handle);
+
+    switch (role)
+    {
+        case BLE_GAP_ROLE_CENTRAL:
+            return link_secure_central(conn_handle, p_sec_params, force_repairing);
+
+        case BLE_GAP_ROLE_PERIPH:
+            return link_secure_peripheral(conn_handle, p_sec_params);
+
+        default:
+            return BLE_ERROR_INVALID_CONN_HANDLE;
+    }
+}
+
+
+void smd_ble_evt_handler(ble_evt_t * p_ble_evt)
+{
+    switch (p_ble_evt->header.evt_id)
+    {
+        case BLE_GAP_EVT_DISCONNECTED:
+            disconnect_process(&(p_ble_evt->evt.gap_evt));
+            break;
+
+        case BLE_GAP_EVT_SEC_PARAMS_REQUEST:
+            sec_params_request_process(&(p_ble_evt->evt.gap_evt));
+            break;
+
+        case BLE_GAP_EVT_SEC_INFO_REQUEST:
+            sec_info_request_process(&(p_ble_evt->evt.gap_evt));
+            break;
+
+        case BLE_GAP_EVT_SEC_REQUEST:
+            sec_request_process(&(p_ble_evt->evt.gap_evt));
+            break;
+
+        case BLE_GAP_EVT_AUTH_STATUS:
+            auth_status_process(&(p_ble_evt->evt.gap_evt));
+            break;
+
+        case BLE_GAP_EVT_CONN_SEC_UPDATE:
+            conn_sec_update_process(&(p_ble_evt->evt.gap_evt));
+            break;
+    };
+}
+#endif //NRF_MODULE_ENABLED(PEER_MANAGER)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/security_dispatcher.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,296 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef SECURITY_DISPATCHER_H__
+#define SECURITY_DISPATCHER_H__
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "headers/ble.h"
+#include "ble_gap.h"
+#include "peer_manager_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup security_dispatcher Security Dispatcher
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. A module for streamlining pairing, bonding, and
+ *        encryption, including flash storage of shared data.
+ *
+ */
+
+
+/**@brief Events that can come from the Security Dispatcher module.
+ */
+typedef enum
+{
+    SMD_EVT_PARAMS_REQ,             /**< Parameters are required for a pairing procedure on the specified connection. The user must provide them using @ref smd_params_reply. */
+    SMD_EVT_SLAVE_SECURITY_REQ,     /**< The peer (slave) has requested link encryption. Call @ref smd_link_secure to honor the request. The data in the event structure must be used in the parameters. */
+    SMD_EVT_SEC_PROCEDURE_START,    /**< A security procedure has started. */
+    SMD_EVT_PAIRING_SUCCESS,        /**< A pairing procedure (and bonding if applicable) has completed with success. */
+    SMD_EVT_PAIRING_FAIL,           /**< A pairing procedure has failed which means no encryption and no bond could be established. */
+    SMD_EVT_LINK_ENCRYPTION_UPDATE, /**< The security level of the link has been updated. The link is encrypted. */
+    SMD_EVT_LINK_ENCRYPTION_FAILED, /**< An attempt to start encryption on an unencrypted link failed because the peripheral did not have the correct keys. If the peer is the peripheral, the force_repairing flag should be set when reattempting @ref smd_link_secure. */
+    SMD_EVT_BONDING_INFO_STORED,    /**< Information exchanged during bonding with a peer has been stored persistently. */
+    SMD_EVT_ERROR_BONDING_INFO,     /**< Information exchanged during bonding with a peer could not be stored persistently, because of an unexpected error. */
+    // SMD_EVT_ERROR_NO_MEM,           /**< An operation failed because there was no available storage room in persistent storage. Please free up room, and the operation will automatically continue. */
+    SMD_EVT_ERROR_UNEXPECTED,       /**< An operation failed with an unexpected error. The error is provided. This is possibly a fatal error. */
+} smd_evt_id_t;
+
+
+/**@brief Events parameters specific to the @ref SMD_EVT_SLAVE_SECURITY_REQ event.
+ */
+typedef struct
+{
+    bool bond;
+    bool mitm;
+} smd_evt_slave_security_req_t;
+
+
+/**@brief Events parameters specific to the @ref SMD_EVT_SEC_PROCEDURE_START event.
+ */
+typedef struct
+{
+    pm_conn_sec_procedure_t procedure; /**< The procedure that has started. */
+} smd_evt_sec_procedure_start_t;
+
+
+/**@brief Events parameters specific to the @ref SMD_EVT_PAIRING_SUCCESS event.
+ */
+typedef struct
+{
+    bool                bonded;     /**< Whether bonding was performed. */
+    bool                mitm;       /**< Whether MITM protection was used during pairing. */
+    ble_gap_sec_kdist_t kdist_own;  /**< Which keys were distributed to the peer. Only relevant if bonding was performed. */
+    ble_gap_sec_kdist_t kdist_peer; /**< Which keys were distributed by the peer. Only relevant if bonding was performed. */
+} smd_evt_pairing_success_t;
+
+
+/**@brief Events parameters specific to the @ref SMD_EVT_PAIRING_FAIL event.
+ */
+typedef struct
+{
+    pm_sec_error_code_t error;     /**< What went wrong. */
+    uint8_t             error_src; /**< The party that raised the error, see @ref BLE_GAP_SEC_STATUS_SOURCES. */
+} smd_evt_pairing_failed_t;
+
+
+/**@brief Events parameters specific to the @ref SMD_EVT_LINK_ENCRYPTION_UPDATE event.
+ */
+typedef struct
+{
+    bool mitm_protected;  /**< Whether the link is now MITM protected. */
+} smd_evt_link_encryption_update_t;
+
+
+/**@brief Events parameters specific to the @ref SMD_EVT_LINK_ENCRYPTION_FAILED event.
+ */
+typedef struct
+{
+    pm_sec_error_code_t error;     /**< What went wrong. */
+    uint8_t             error_src; /**< The party that raised the error, see @ref BLE_GAP_SEC_STATUS_SOURCES. */
+} smd_evt_link_encryption_failed_t;
+
+
+/**@brief Events parameters specific to the @ref SMD_EVT_BONDING_INFO_STORED event.
+ */
+typedef struct
+{
+    pm_peer_id_t peer_id; /**< The peer this event pertains to. */
+} smd_evt_bonding_info_stored_t;
+
+
+/**@brief Events parameters specific to the @ref SMD_EVT_ERROR_BONDING_INFO event.
+ */
+typedef struct
+{
+    pm_peer_id_t peer_id; /**< The peer this event pertains to, if previously bonded. @ref PM_PEER_ID_INVALID if no successful bonding has happened with the peer before. */
+    ret_code_t   error;   /**< The unexpected error that occurred. */
+} smd_evt_error_bonding_info_t;
+
+
+// typedef struct
+// {
+    // pm_peer_id_t peer_id; /**< The peer this event pertains to. */
+// } smd_evt_error_no_mem_t;
+
+
+/**@brief Events parameters specific to the @ref SMD_EVT_ERROR_UNEXPECTED event.
+ */
+typedef struct
+{
+    ret_code_t error; /**< The unexpected error that occurred. */
+} smd_evt_error_unexpected_t;
+
+
+typedef union
+{
+    smd_evt_slave_security_req_t     slave_security_req;
+    smd_evt_sec_procedure_start_t    sec_procedure_start;
+    smd_evt_pairing_success_t        pairing_success;
+    smd_evt_pairing_failed_t         pairing_failed;
+    smd_evt_link_encryption_update_t link_encryption_update;
+    smd_evt_link_encryption_failed_t link_encryption_failed;
+    smd_evt_bonding_info_stored_t    bonding_info_stored;
+    smd_evt_error_bonding_info_t     error_bonding_info;
+    //  smd_evt_error_no_mem_t          error_no_mem;
+    smd_evt_error_unexpected_t       error_unexpected;
+} smd_evt_params_t; /**< Event specific parameters. Chosen based on evt_id. */
+
+
+/**@brief Structure describing events from the Security Dispatcher module.
+ */
+typedef struct
+{
+    smd_evt_id_t evt_id;     /**< The type of event. */
+    uint16_t conn_handle;    /**< The connection this event pertains to. */
+    smd_evt_params_t params; /**< Event specific parameters. Chosen based on evt_id. */
+} smd_evt_t;
+
+
+
+/**@brief Event handler for events from the Security Dispatcher module.
+ *
+ * @param[in]  p_event  The event that has happened.
+ */
+typedef void (*smd_evt_handler_t)(smd_evt_t const * p_event);
+
+
+#if 0
+/**@brief Function for registering with the Security Dispatcher module. This function also
+ *        initializes the module if uninitialized.
+ *
+ * @param[in]  evt_handler  Callback for events from the Security Dispatcher module.
+ *
+ * @retval NRF_SUCCESS       Registration was successful.
+ * @retval NRF_ERROR_NO_MEM  No more registrations possible.
+ * @retval NRF_ERROR_NULL    evt_handler was NULL.
+ */
+ret_code_t smd_register(smd_evt_handler_t evt_handler);
+#endif
+
+
+ret_code_t smd_init(void);
+
+
+/**@brief Function for dispatching SoftDevice events to the Security Dispatcher module.
+ *
+ * @param[in]  ble_evt    The SoftDevice event.
+ */
+void smd_ble_evt_handler(ble_evt_t * ble_evt);
+
+
+/**@brief Function for providing pairing and bonding parameters to use for the current pairing
+ *        procedure on a connection.
+ *
+ * @note If this function returns an @ref NRF_ERROR_NULL, @ref NRF_ERROR_INVALID_PARAM, @ref
+ *       BLE_ERROR_INVALID_CONN_HANDLE, or @ref NRF_ERROR_STORAGE_FULL, this function can be called
+ *       again after corrective action.
+ *
+ * @note To reject a request, call this function with NULL p_sec_params.
+ *
+ * @param[in]  conn_handle   The connection handle of the connection the pairing is happening on.
+ * @param[in]  p_sec_params  The security parameters to use for this link.
+ * @param[in]  p_public_key  A pointer to the public key to use if using LESC, or NULL.
+ *
+ * @retval NRF_SUCCESS                    Success.
+ * @retval NRF_ERROR_INVALID_STATE        Module is not initialized, or no parameters have been
+ *                                        requested on that conn_handle, or this error originates
+ *                                        from the SoftDevice.
+ * @retval NRF_ERROR_INVALID_PARAM        Invalid combination of parameters (not including conn_handle).
+ * @retval NRF_ERROR_TIMEOUT              There has been an SMP timeout, so no more SMP operations
+ *                                        can be performed on this link.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE  Invalid connection handle.
+ * @retval NRF_ERROR_STORAGE_FULL         No more room in flash. Fix and reattempt after the next
+ *                                        FDS garbage collection procedure.
+ * @retval NRF_ERROR_BUSY                 No write buffer. Reattempt later.
+ */
+ret_code_t smd_params_reply(uint16_t                 conn_handle,
+                            ble_gap_sec_params_t   * p_sec_params,
+                            ble_gap_lesc_p256_pk_t * p_public_key);
+
+
+/**@brief Function for initiating security on the link, with the specified parameters.
+ *
+ * @note If the connection is a peripheral connection, this will send a security request to the
+ *       master, but the master is not obligated to initiate pairing or encryption in response.
+ * @note If the connection is a central connection and a key is available, the parameters will be
+ *       used to determine whether to re-pair or to encrypt using the existing key. If no key is
+ *       available, pairing will be started.
+ *
+ * @param[in]  conn_handle      Handle of the connection to initiate pairing on.
+ * @param[in]  p_sec_params     The security parameters to use for this link. As a central, this can
+ *                              be NULL to reject a slave security request.
+ * @param[in]  force_repairing  Whether to force a pairing procedure to happen regardless of whether
+ *                              an encryption key already exists. This argument is only relevant for
+ *                              the central role. Recommended value: false
+ *
+ * @retval NRF_SUCCESS                    Success.
+ * @retval NRF_ERROR_NULL                 p_sec_params was NULL (peripheral only).
+ * @retval NRF_ERROR_INVALID_STATE        Module is not initialized, or this error originates from
+ *                                        the SoftDevice.
+ * @retval NRF_ERROR_INVALID_PARAM        Invalid combination of parameters (not including conn_handle).
+ * @retval NRF_ERROR_BUSY                 Unable to initiate procedure at this time.
+ * @retval NRF_ERROR_TIMEOUT              There has been an SMP timeout, so no more SMP operations
+ *                                        can be performed on this link.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE  Invalid connection handle.
+ * @retval NRF_ERROR_STORAGE_FULL         No more room in flash. Fix and reattempt after the next
+ *                                        FDS garbage collection procedure.
+ * @retval NRF_ERROR_INTERNAL             No more available peer IDs.
+ */
+ret_code_t smd_link_secure(uint16_t               conn_handle,
+                           ble_gap_sec_params_t * p_sec_params,
+                           bool                   force_repairing);
+
+/** @}
+ * @endcond
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SECURITY_DISPATCHER_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/security_manager.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,569 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(PEER_MANAGER)
+#include "security_manager.h"
+
+#include <string.h>
+#include "security_dispatcher.h"
+#include "peer_database.h"
+#include "ble_conn_state.h"
+#include "id_manager.h"
+
+
+// The number of registered event handlers.
+#define SM_EVENT_HANDLERS_CNT       (sizeof(m_evt_handlers) / sizeof(m_evt_handlers[0]))
+
+
+// Security Manager event handler in Peer Manager.
+extern void pm_sm_evt_handler(sm_evt_t const * p_sm_evt);
+
+// Security Manager events' handlers.
+// The number of elements in this array is SM_EVENT_HANDLERS_CNT.
+static sm_evt_handler_t const m_evt_handlers[] =
+{
+    pm_sm_evt_handler
+};
+
+static bool                            m_module_initialized;
+
+static ble_gap_sec_params_t            m_sec_params;
+static bool                            m_sec_params_valid;
+
+static ble_gap_lesc_p256_pk_t        * m_p_public_key;
+static ble_conn_state_user_flag_id_t   m_flag_link_secure_pending_busy        = BLE_CONN_STATE_USER_FLAG_INVALID;
+static ble_conn_state_user_flag_id_t   m_flag_link_secure_pending_flash_full  = BLE_CONN_STATE_USER_FLAG_INVALID;
+static ble_conn_state_user_flag_id_t   m_flag_link_secure_force_repairing     = BLE_CONN_STATE_USER_FLAG_INVALID;
+static ble_conn_state_user_flag_id_t   m_flag_link_secure_null_params         = BLE_CONN_STATE_USER_FLAG_INVALID;
+static ble_conn_state_user_flag_id_t   m_flag_params_reply_pending_busy       = BLE_CONN_STATE_USER_FLAG_INVALID;
+static ble_conn_state_user_flag_id_t   m_flag_params_reply_pending_flash_full = BLE_CONN_STATE_USER_FLAG_INVALID;
+static ble_conn_state_user_flag_id_t   m_flag_reject_pairing                  = BLE_CONN_STATE_USER_FLAG_INVALID;
+
+
+static void evt_send(sm_evt_t * p_event)
+{
+    for (uint32_t i = 0; i < SM_EVENT_HANDLERS_CNT; i++)
+    {
+        m_evt_handlers[i](p_event);
+    }
+}
+
+
+static void flags_set_from_err_code(uint16_t conn_handle, ret_code_t err_code, bool params_reply)
+{
+    bool flag_value_flash_full = false;
+    bool flag_value_busy       = false;
+
+    if (    (err_code == NRF_ERROR_STORAGE_FULL)
+         || (err_code == NRF_ERROR_BUSY)
+         || (err_code == NRF_SUCCESS))
+    {
+        if ((err_code == NRF_ERROR_STORAGE_FULL))
+        {
+            flag_value_busy       = false;
+            flag_value_flash_full = true;
+        }
+        else if (err_code == NRF_ERROR_BUSY)
+        {
+            flag_value_busy       = true;
+            flag_value_flash_full = false;
+        }
+        else if (err_code == NRF_SUCCESS)
+        {
+            flag_value_busy       = false;
+            flag_value_flash_full = false;
+        }
+
+        if (params_reply)
+        {
+            ble_conn_state_user_flag_set(conn_handle,
+                                         m_flag_params_reply_pending_flash_full,
+                                         flag_value_flash_full);
+            ble_conn_state_user_flag_set(conn_handle,
+                                         m_flag_params_reply_pending_busy,
+                                         flag_value_busy);
+            ble_conn_state_user_flag_set(conn_handle,
+                                         m_flag_link_secure_pending_flash_full,
+                                         false);
+            ble_conn_state_user_flag_set(conn_handle,
+                                         m_flag_link_secure_pending_busy,
+                                         false);
+        }
+        else
+        {
+            ble_conn_state_user_flag_set(conn_handle,
+                                         m_flag_link_secure_pending_flash_full,
+                                         flag_value_flash_full);
+            ble_conn_state_user_flag_set(conn_handle,
+                                         m_flag_link_secure_pending_busy,
+                                         flag_value_busy);
+        }
+    }
+}
+
+
+static void events_send_from_err_code(uint16_t conn_handle, ret_code_t err_code)
+{
+     if ((err_code != NRF_SUCCESS) && (err_code != NRF_ERROR_BUSY))
+     {
+        sm_evt_t evt =
+        {
+            .conn_handle = conn_handle,
+            .params = {.error_unexpected = {
+                .error = err_code
+            }}
+        };
+        if (err_code == NRF_ERROR_TIMEOUT)
+        {
+            evt.evt_id = SM_EVT_ERROR_SMP_TIMEOUT;
+        }
+        else if (err_code == NRF_ERROR_STORAGE_FULL)
+        {
+            evt.evt_id = SM_EVT_ERROR_NO_MEM;
+        }
+        else
+        {
+            evt.evt_id = SM_EVT_ERROR_UNEXPECTED;
+        }
+        evt_send(&evt);
+     }
+}
+
+
+static ret_code_t link_secure(uint16_t conn_handle, bool null_params, bool force_repairing, bool send_events)
+{
+    ret_code_t err_code;
+
+    if (!null_params && !m_sec_params_valid)
+    {
+        return NRF_ERROR_NOT_FOUND;
+    }
+
+    if (null_params)
+    {
+        err_code = smd_link_secure(conn_handle, NULL, force_repairing);
+    }
+    else
+    {
+        err_code = smd_link_secure(conn_handle, &m_sec_params, force_repairing);
+    }
+
+    flags_set_from_err_code(conn_handle, err_code, false);
+
+    if (send_events)
+    {
+        events_send_from_err_code(conn_handle, err_code);
+    }
+
+    switch (err_code)
+    {
+        case NRF_ERROR_BUSY:
+            ble_conn_state_user_flag_set(conn_handle, m_flag_link_secure_null_params, null_params);
+            ble_conn_state_user_flag_set(conn_handle, m_flag_link_secure_force_repairing, force_repairing);
+            err_code = NRF_SUCCESS;
+            break;
+        case NRF_ERROR_STORAGE_FULL:
+            ble_conn_state_user_flag_set(conn_handle, m_flag_link_secure_null_params, null_params);
+            ble_conn_state_user_flag_set(conn_handle, m_flag_link_secure_force_repairing, force_repairing);
+            break;
+        case NRF_SUCCESS:
+        case NRF_ERROR_TIMEOUT:
+        case BLE_ERROR_INVALID_CONN_HANDLE:
+        case NRF_ERROR_INVALID_STATE:
+            /* No action */
+            break;
+        default:
+            err_code = NRF_ERROR_INTERNAL;
+            break;
+    }
+
+    return err_code;
+}
+
+
+static void send_config_req(uint16_t conn_handle)
+{
+    sm_evt_t sm_evt;
+    memset(&sm_evt, 0, sizeof(sm_evt));
+
+    sm_evt.evt_id      = SM_EVT_CONN_SEC_CONFIG_REQ;
+    sm_evt.conn_handle = conn_handle;
+
+    evt_send(&sm_evt);
+}
+
+
+static void smd_params_reply_perform(uint16_t conn_handle)
+{
+    ret_code_t err_code;
+
+    if (  (ble_conn_state_role(conn_handle) == BLE_GAP_ROLE_PERIPH)
+        && im_peer_id_get_by_conn_handle(conn_handle) != PM_PEER_ID_INVALID)
+    {
+        // Bond already exists. Reject the pairing request if the user doesn't intervene.
+        ble_conn_state_user_flag_set(conn_handle, m_flag_reject_pairing, true);
+        send_config_req(conn_handle);
+    }
+    else
+    {
+        ble_conn_state_user_flag_set(conn_handle, m_flag_reject_pairing, false);
+    }
+
+    if (   m_sec_params_valid
+        && !ble_conn_state_user_flag_get(conn_handle, m_flag_reject_pairing))
+    {
+        err_code = smd_params_reply(conn_handle, &m_sec_params, m_p_public_key);
+    }
+    else
+    {
+        err_code = smd_params_reply(conn_handle, NULL, NULL);
+    }
+
+    flags_set_from_err_code(conn_handle, err_code, true);
+    events_send_from_err_code(conn_handle, err_code);
+}
+
+
+/**@brief Event handler for events from the Security Dispatcher module.
+ *        This handler is extern in Security Dispatcher.
+ *
+ * @param[in]  p_event   The event that has happened.
+ */
+void sm_smd_evt_handler(smd_evt_t const * p_event)
+{
+    switch (p_event->evt_id)
+    {
+        case SMD_EVT_PARAMS_REQ:
+            smd_params_reply_perform(p_event->conn_handle);
+            break;
+        case SMD_EVT_SLAVE_SECURITY_REQ:
+        {
+            bool null_params = false;
+            if (!m_sec_params_valid)
+            {
+                null_params = true;
+            }
+            else if ((bool)m_sec_params.bond < (bool)p_event->params.slave_security_req.bond)
+            {
+                null_params = true;
+            }
+            else if ((bool)m_sec_params.mitm < (bool)p_event->params.slave_security_req.mitm)
+            {
+                null_params = true;
+            }
+            ret_code_t err_code = link_secure(p_event->conn_handle, null_params, false, true);
+            UNUSED_VARIABLE(err_code); // It is acceptable to ignore the return code because it is
+                                       // acceptable to ignore a security request.
+        }
+        /* fallthrough */
+        case SMD_EVT_PAIRING_SUCCESS:
+        case SMD_EVT_PAIRING_FAIL:
+        case SMD_EVT_LINK_ENCRYPTION_UPDATE:
+        case SMD_EVT_LINK_ENCRYPTION_FAILED:
+        case SMD_EVT_BONDING_INFO_STORED:
+        case SMD_EVT_ERROR_BONDING_INFO:
+        case SMD_EVT_ERROR_UNEXPECTED:
+        case SMD_EVT_SEC_PROCEDURE_START:
+        {
+            sm_evt_t evt;
+            evt.evt_id = (sm_evt_id_t)p_event->evt_id;
+            evt.conn_handle = p_event->conn_handle;
+            evt.params = p_event->params;
+
+            evt_send(&evt);
+        }
+            break;
+    }
+}
+
+
+static void link_secure_pending_process(ble_conn_state_user_flag_id_t flag_id)
+{
+    sdk_mapped_flags_t flag_collection = ble_conn_state_user_flag_collection(flag_id);
+    if (sdk_mapped_flags_any_set(flag_collection))
+    {
+        sdk_mapped_flags_key_list_t conn_handle_list = ble_conn_state_conn_handles();
+
+        for (uint32_t i = 0; i < conn_handle_list.len; i++)
+        {
+            bool pending = ble_conn_state_user_flag_get(conn_handle_list.flag_keys[i], flag_id);
+            if (pending)
+            {
+                bool force_repairing = ble_conn_state_user_flag_get(conn_handle_list.flag_keys[i], m_flag_link_secure_force_repairing);
+                bool null_params     = ble_conn_state_user_flag_get(conn_handle_list.flag_keys[i], m_flag_link_secure_null_params);
+
+                ret_code_t err_code = link_secure(conn_handle_list.flag_keys[i], null_params, force_repairing, true); // If this fails, it will be automatically retried.
+                UNUSED_VARIABLE(err_code);
+            }
+        }
+    }
+}
+
+
+static void params_reply_pending_process(ble_conn_state_user_flag_id_t flag_id)
+{
+    sdk_mapped_flags_t flag_collection = ble_conn_state_user_flag_collection(flag_id);
+    if (sdk_mapped_flags_any_set(flag_collection))
+    {
+        sdk_mapped_flags_key_list_t conn_handle_list = ble_conn_state_conn_handles();
+
+        for (uint32_t i = 0; i < conn_handle_list.len; i++)
+        {
+            bool pending = ble_conn_state_user_flag_get(conn_handle_list.flag_keys[i], flag_id);
+            if (pending)
+            {
+                smd_params_reply_perform(conn_handle_list.flag_keys[i]);
+            }
+        }
+    }
+}
+
+
+/**@brief Event handler for events from the Peer Database module.
+ *        This handler is extern in Peer Database.
+ *
+ * @param[in]  p_event   The event that has happened.
+ */
+void sm_pdb_evt_handler(pdb_evt_t const * p_event)
+{
+    switch (p_event->evt_id)
+    {
+        case PDB_EVT_COMPRESSED:
+            params_reply_pending_process(m_flag_params_reply_pending_flash_full);
+            link_secure_pending_process(m_flag_link_secure_pending_flash_full);
+            /* fallthrough */
+        case PDB_EVT_WRITE_BUF_STORED:
+        case PDB_EVT_RAW_STORED:
+        case PDB_EVT_RAW_STORE_FAILED:
+        case PDB_EVT_CLEARED:
+        case PDB_EVT_CLEAR_FAILED:
+        case PDB_EVT_PEER_FREED:
+        case PDB_EVT_PEER_FREE_FAILED:
+            params_reply_pending_process(m_flag_params_reply_pending_busy);
+            link_secure_pending_process(m_flag_link_secure_pending_busy);
+            break;
+        case PDB_EVT_ERROR_NO_MEM:
+        case PDB_EVT_ERROR_UNEXPECTED:
+            break;
+    }
+}
+
+
+/**@brief Funtion for initializing a BLE Connection State user flag.
+ *
+ * @param[out] flag_id  The flag to initialize.
+ */
+static void flag_id_init(ble_conn_state_user_flag_id_t * p_flag_id)
+{
+    if (*p_flag_id == BLE_CONN_STATE_USER_FLAG_INVALID)
+    {
+        *p_flag_id = ble_conn_state_user_flag_acquire();
+    }
+}
+
+
+ret_code_t sm_init(void)
+{
+    NRF_PM_DEBUG_CHECK(!m_module_initialized);
+
+    flag_id_init(&m_flag_link_secure_pending_busy);
+    flag_id_init(&m_flag_link_secure_pending_flash_full);
+    flag_id_init(&m_flag_link_secure_force_repairing);
+    flag_id_init(&m_flag_link_secure_null_params);
+    flag_id_init(&m_flag_params_reply_pending_busy);
+    flag_id_init(&m_flag_params_reply_pending_flash_full);
+    flag_id_init(&m_flag_reject_pairing);
+
+    if (m_flag_reject_pairing == BLE_CONN_STATE_USER_FLAG_INVALID)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    m_module_initialized = true;
+
+    return NRF_SUCCESS;
+}
+
+
+void sm_ble_evt_handler(ble_evt_t * p_ble_evt)
+{
+    NRF_PM_DEBUG_CHECK(p_ble_evt != NULL);
+
+    smd_ble_evt_handler(p_ble_evt);
+    link_secure_pending_process(m_flag_link_secure_pending_busy);
+}
+
+
+static bool sec_params_verify(ble_gap_sec_params_t * p_sec_params)
+{
+    // NULL check.
+    if (p_sec_params == NULL)
+    {
+        return false;
+    }
+
+    // OOB not allowed unless MITM.
+    if (!p_sec_params->mitm && p_sec_params->oob)
+    {
+        return false;
+    }
+
+    // IO Capabilities must be one of the valid values from @ref BLE_GAP_IO_CAPS.
+    if (p_sec_params->io_caps > BLE_GAP_IO_CAPS_KEYBOARD_DISPLAY)
+    {
+        return false;
+    }
+
+    // Must have either IO capabilities or OOB if MITM.
+    if (p_sec_params->mitm && (p_sec_params->io_caps == BLE_GAP_IO_CAPS_NONE) && !p_sec_params->oob)
+    {
+        return false;
+    }
+
+    // Minimum key size cannot be larger than maximum key size.
+    if (p_sec_params->min_key_size > p_sec_params->max_key_size)
+    {
+        return false;
+    }
+
+    // Key size cannot be below 7 bytes.
+    if (p_sec_params->min_key_size < 7)
+    {
+        return false;
+    }
+
+    // Key size cannot be above 16 bytes.
+    if (p_sec_params->max_key_size > 16)
+    {
+        return false;
+    }
+
+    // Signing is not supported.
+    if (p_sec_params->kdist_own.sign || p_sec_params->kdist_peer.sign)
+    {
+        return false;
+    }
+
+    // link bit must be 0.
+    if (p_sec_params->kdist_own.link || p_sec_params->kdist_peer.link)
+    {
+        return false;
+    }
+
+    // If bonding is not enabled, no keys can be distributed.
+    if (!p_sec_params->bond && (   p_sec_params->kdist_own.enc
+                                || p_sec_params->kdist_own.id
+                                || p_sec_params->kdist_peer.enc
+                                || p_sec_params->kdist_peer.id))
+    {
+        return false;
+    }
+
+    // If bonding is enabled, one or more keys must be distributed.
+    if (    p_sec_params->bond
+        && !p_sec_params->kdist_own.enc
+        && !p_sec_params->kdist_own.id
+        && !p_sec_params->kdist_peer.enc
+        && !p_sec_params->kdist_peer.id)
+    {
+        return false;
+    }
+
+    return true;
+}
+
+
+ret_code_t sm_sec_params_set(ble_gap_sec_params_t * p_sec_params)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    if (p_sec_params == NULL)
+    {
+        m_sec_params_valid = false;
+        return NRF_SUCCESS;
+    }
+    else if (sec_params_verify(p_sec_params))
+    {
+        m_sec_params       = *p_sec_params;
+        m_sec_params_valid = true;
+        return NRF_SUCCESS;
+    }
+    else
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+}
+
+
+void sm_conn_sec_config_reply(uint16_t conn_handle, pm_conn_sec_config_t * p_conn_sec_config)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    NRF_PM_DEBUG_CHECK(p_conn_sec_config != NULL);
+
+    ble_conn_state_user_flag_set(conn_handle, m_flag_reject_pairing, !p_conn_sec_config->allow_repairing);
+}
+
+
+ret_code_t sm_lesc_public_key_set(ble_gap_lesc_p256_pk_t * p_public_key)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    m_p_public_key = p_public_key;
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t sm_sec_params_reply(uint16_t conn_handle, ble_gap_sec_params_t * p_sec_params)
+{
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t sm_link_secure(uint16_t conn_handle, bool force_repairing)
+{
+    ret_code_t ret;
+
+    NRF_PM_DEBUG_CHECK(m_module_initialized);
+
+    ret = link_secure(conn_handle, false, force_repairing, false);
+    return ret;
+}
+#endif // NRF_MODULE_ENABLED(PEER_MANAGER)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/security_manager.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,221 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef SECURITY_MANAGER_H__
+#define SECURITY_MANAGER_H__
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "headers/ble.h"
+#include "ble_gap.h"
+#include "peer_manager_types.h"
+#include "security_dispatcher.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup security_manager Security Manager
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. A module for streamlining pairing, bonding, and
+ *        encryption, including flash storage of shared data.
+ */
+
+
+/**@brief Events that can come from the Security Manager module.
+ */
+typedef enum
+{
+    // SM_EVT_PARAMS_REQ             = SMD_EVT_PARAMS_REQ,             /**< Parameters are required for a pairing procedure on the specified connection. The user must provide them using @ref sm_sec_params_set or @ref sm_sec_params_reply (only this procedure, currently unimplemented). */
+    SM_EVT_SLAVE_SECURITY_REQ     = SMD_EVT_SLAVE_SECURITY_REQ,     /**< The peer (peripheral) has requested link encryption, which has been enabled. */
+    SM_EVT_SEC_PROCEDURE_START    = SMD_EVT_SEC_PROCEDURE_START,    /**< A security procedure has started. */
+    SM_EVT_PAIRING_SUCCESS        = SMD_EVT_PAIRING_SUCCESS,        /**< A pairing procedure (and bonding if applicable) has completed with success. */
+    SM_EVT_PAIRING_FAIL           = SMD_EVT_PAIRING_FAIL,           /**< A pairing procedure has failed which means no encryption and no bond could be established. */
+    SM_EVT_LINK_ENCRYPTION_UPDATE = SMD_EVT_LINK_ENCRYPTION_UPDATE, /**< The security level of the link has been updated. The link is encrypted. */
+    SM_EVT_LINK_ENCRYPTION_FAILED = SMD_EVT_LINK_ENCRYPTION_FAILED, /**< An attempt to start encryption on an unencrypted link failed because the peripheral did not have the correct keys. If the peer is the peripheral, the force_repairing flag should be set when reattempting @ref sm_link_secure. */
+    SM_EVT_BONDING_INFO_STORED    = SMD_EVT_BONDING_INFO_STORED,    /**< Information exchanged during bonding with a peer has been stored persistently. */
+    SM_EVT_ERROR_BONDING_INFO     = SMD_EVT_ERROR_BONDING_INFO,     /**< Information exchanged during bonding with a peer could not be stored persistently, because of an unexpected error. */
+    SM_EVT_ERROR_UNEXPECTED       = SMD_EVT_ERROR_UNEXPECTED,       /**< An operation failed with an unexpected error. The error is provided. This is possibly a fatal error. */
+    SM_EVT_ERROR_NO_MEM           /*= SMD_EVT_ERROR_NO_MEM*/,       /**< An operation failed because there was no available storage room in persistent storage. Please free up room and the operation will automatically continue after the next compression. */
+    SM_EVT_ERROR_SMP_TIMEOUT,                                       /**< An operation failed because there has been an SMP timeout on the link, which entails that no more security operations can be performed on it. */
+    SM_EVT_CONN_SEC_CONFIG_REQ,                                     /**< The peer (central) has requested pairing, but a bond already exists with that peer. Reply by calling @ref sm_conn_sec_config_reply before the event handler returns. If no reply is sent, a default is used. */
+} sm_evt_id_t;
+
+
+typedef struct
+{
+    sm_evt_id_t      evt_id;
+    uint16_t         conn_handle;
+    smd_evt_params_t params;
+} sm_evt_t;
+
+
+/**@brief Event handler for events from the Security Manager module.
+ *
+ * @param[in]  event        The event that has happened.
+ * @param[in]  conn_handle  The connection handle the event pertains to.
+ */
+typedef void (*sm_evt_handler_t)(sm_evt_t const * p_event);
+
+
+/**@brief Function for initializing the Security Manager module.
+ *
+ * @retval NRF_SUCCESS        If initialization was successful.
+ * @retval NRF_ERROR_INTERNAL If an unexpected error occurred.
+ */
+ret_code_t sm_init(void);
+
+
+/**@brief Function for dispatching SoftDevice events to the Security Manager module.
+ *
+ * @param[in]  ble_evt    The SoftDevice event.
+ */
+void sm_ble_evt_handler(ble_evt_t * ble_evt);
+
+
+/**@brief Function for providing pairing and bonding parameters to use for pairing procedures.
+ *
+ * @details Until this is called, all bonding procedures initiated by the peer will be rejected.
+ *          This function can be called multiple times, even with NULL p_sec_params, in which case
+ *          it will go back to rejecting all procedures.
+ *
+ * @param[in]  p_sec_params  The security parameters to use for this link. Can be NULL to reject
+ *                           all pairing procedures.
+ *
+ * @retval NRF_SUCCESS                    Success.
+ * @retval NRF_ERROR_INVALID_PARAM        Invalid combination of parameters.
+ * @retval NRF_ERROR_INVALID_STATE        Module is not initialized.
+ */
+ret_code_t sm_sec_params_set(ble_gap_sec_params_t * p_sec_params);
+
+
+/**@brief Function for providing security configuration for a link.
+ *
+ * @details This function is optional, and must be called in reply to a @ref
+ *          SM_EVT_CONN_SEC_CONFIG_REQ event, before the Peer Manager event handler returns. If it
+ *          is not called in time, a default configuration is used. See @ref pm_conn_sec_config_t
+ *          for the value of the default.
+ *
+ * @param[in]  conn_handle        The connection to set the configuration for.
+ * @param[in]  p_conn_sec_config  The configuration.
+ */
+void sm_conn_sec_config_reply(uint16_t conn_handle, pm_conn_sec_config_t * p_conn_sec_config);
+
+
+/**@brief Experimental function for specifying the public key to use for LESC operations.
+ *
+ * @details This function can be called multiple times. The specified public key will be used for
+ *          all subsequent LESC (LE Secure Connections) operations until the next time this function
+ *          is called.
+ *
+ * @note The key must continue to reside in application memory as it is not copied by Peer Manager.
+ *
+ * @param[in]  p_public_key  The public key to use for all subsequent LESC operations.
+ *
+ * @retval NRF_SUCCESS                    Pairing initiated successfully.
+ * @retval NRF_ERROR_INVALID_STATE        Peer Manager is not initialized.
+ */
+ret_code_t sm_lesc_public_key_set(ble_gap_lesc_p256_pk_t * p_public_key);
+
+
+/**@brief Function for providing pairing and bonding parameters to use for the current pairing
+ *        procedure on a connection.
+ *
+ * @warning This function is not yet implemented.
+ *
+ * @note If this function returns an @ref NRF_ERROR_NULL, @ref NRF_ERROR_INVALID_PARAM, @ref
+ *       BLE_ERROR_INVALID_CONN_HANDLE, or @ref NRF_ERROR_STORAGE_FULL, this function can be called
+ *       again after corrective action.
+ *
+ * @note To reject a request, call this function with NULL p_sec_params.
+ *
+ * @param[in]  conn_handle   The connection handle of the connection the pairing is happening on.
+ * @param[in]  p_sec_params  The security parameters to use for this link.
+ *
+ * @retval NRF_SUCCESS                    Success.
+ * @retval NRF_ERROR_INVALID_STATE        Module is not initialized, or no parameters have been
+ *                                        requested on that conn_handle, or this error originates
+ *                                        from the SoftDevice.
+ * @retval NRF_ERROR_INVALID_PARAM        Invalid combination of parameters (not including conn_handle).
+ * @retval NRF_ERROR_TIMEOUT              There has been an SMP timeout, so no more SMP operations
+ *                                        can be performed on this link.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE  Invalid connection handle.
+ * @retval NRF_ERROR_STORAGE_FULL         No more room in flash. Fix and reattempt later.
+ * @retval NRF_ERROR_BUSY                 No write buffer. Reattempt later.
+ */
+ret_code_t sm_sec_params_reply(uint16_t conn_handle, ble_gap_sec_params_t * p_sec_params);
+
+
+/**@brief Function for initiating security on the link, with the specified parameters.
+ *
+ * @note If the connection is a peripheral connection, this will send a security request to the
+ *       master, but the master is not obligated to initiate pairing or encryption in response.
+ * @note If the connection is a central connection and a key is available, the parameters will be
+ *       used to determine whether to re-pair or to encrypt using the existing key. If no key is
+ *       available, pairing will be started.
+ *
+ * @param[in]  conn_handle      Handle of the connection to initiate pairing on.
+ * @param[in]  force_repairing  Whether to force a pairing procedure to happen regardless of whether
+ *                              an encryption key already exists. This argument is only relevant for
+ *                              the central role. Recommended value: false
+ *
+ * @retval NRF_SUCCESS                    Success.
+ * @retval NRF_ERROR_TIMEOUT              There has been an SMP timeout, so no more SMP operations
+ *                                        can be performed on this link.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE  Invalid connection handle.
+ * @retval NRF_ERROR_NOT_FOUND            Security parameters have not been set.
+ * @retval NRF_ERROR_INVALID_STATE        Module is not initialized.
+ * @retval NRF_ERROR_INTERNAL             An unexpected error occurred.
+ */
+ret_code_t sm_link_secure(uint16_t conn_handle, bool force_repairing);
+
+/** @}
+ * @endcond
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SECURITY_MANAGER_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/arduino_primo.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,115 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef ARDUINO_PRIMO_H
+#define ARDUINO_PRIMO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LEDs definitions
+#define LEDS_NUMBER    1
+
+#define LED_1          25
+
+#define LEDS_ACTIVE_STATE 0
+
+#define LEDS_LIST { LED_1}
+
+#define BSP_LED_0      LED_1
+
+#define LEDS_INV_MASK  0
+
+#define BUTTONS_NUMBER 1
+
+#define BUTTON_START   7
+#define BUTTON_1       7
+#define BUTTON_STOP    7
+#define BUTTON_PULL    NRF_GPIO_PIN_PULLUP
+
+#define BUTTONS_ACTIVE_STATE 0
+
+#define BUTTONS_LIST { BUTTON_1 }
+
+#define BSP_BUTTON_0   BUTTON_1
+
+#define RX_PIN_NUMBER  11
+#define TX_PIN_NUMBER  12
+#define CTS_PIN_NUMBER UART_PIN_DISCONNECTED
+#define RTS_PIN_NUMBER UART_PIN_DISCONNECTED
+#define HWFC           false
+
+// Arduino board mappings
+#define ARDUINO_SCL_PIN             27    // SCL signal pin
+#define ARDUINO_SDA_PIN             26    // SDA signal pin
+#define ARDUINO_AREF_PIN            2     // Aref pin
+#define ARDUINO_13_PIN              25    // Digital pin 13
+#define ARDUINO_12_PIN              24    // Digital pin 12
+#define ARDUINO_11_PIN              23    // Digital pin 11
+#define ARDUINO_10_PIN              22    // Digital pin 10
+#define ARDUINO_9_PIN               20    // Digital pin 9
+#define ARDUINO_8_PIN               19    // Digital pin 8
+
+#define ARDUINO_7_PIN               18    // Digital pin 7
+#define ARDUINO_6_PIN               17    // Digital pin 6
+#define ARDUINO_5_PIN               16    // Digital pin 5
+#define ARDUINO_4_PIN               15    // Digital pin 4
+#define ARDUINO_3_PIN               14    // Digital pin 3
+#define ARDUINO_2_PIN               13    // Digital pin 2
+#define ARDUINO_1_PIN               12    // Digital pin 1
+#define ARDUINO_0_PIN               11    // Digital pin 0
+
+#define ARDUINO_A0_PIN              3     // Analog channel 0
+#define ARDUINO_A1_PIN              4     // Analog channel 1
+#define ARDUINO_A2_PIN              28    // Analog channel 2
+#define ARDUINO_A3_PIN              29    // Analog channel 3
+#define ARDUINO_A4_PIN              30    // Analog channel 4
+#define ARDUINO_A5_PIN              31    // Analog channel 5
+
+// Low frequency clock source to be used by the SoftDevice
+#define NRF_CLOCK_LFCLKSRC      {.source        = NRF_CLOCK_LF_SRC_XTAL,            \
+                                 .rc_ctiv       = 0,                                \
+                                 .rc_temp_ctiv  = 0,                                \
+                                 .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // ARDUINO_PRIMO_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/boards.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,163 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "boards.h"
+#include <stdint.h>
+#include <stdbool.h>
+
+#if LEDS_NUMBER > 0
+static const uint8_t m_board_led_list[LEDS_NUMBER] = LEDS_LIST;
+#endif
+
+#if BUTTONS_NUMBER > 0
+static const uint8_t m_board_btn_list[BUTTONS_NUMBER] = BUTTONS_LIST;
+#endif
+
+#if LEDS_NUMBER > 0
+bool bsp_board_led_state_get(uint32_t led_idx)
+{
+    ASSERT(led_idx < LEDS_NUMBER);
+    bool pin_set = nrf_gpio_pin_out_read(m_board_led_list[led_idx]) ? true : false;
+    return (pin_set == (LEDS_ACTIVE_STATE ? true : false));
+}
+
+void bsp_board_led_on(uint32_t led_idx)
+{
+        ASSERT(led_idx < LEDS_NUMBER);
+        nrf_gpio_pin_write(m_board_led_list[led_idx], LEDS_ACTIVE_STATE ? 1 : 0);
+}
+
+void bsp_board_led_off(uint32_t led_idx)
+{
+    ASSERT(led_idx < LEDS_NUMBER);
+    nrf_gpio_pin_write(m_board_led_list[led_idx], LEDS_ACTIVE_STATE ? 0 : 1);
+}
+
+void bsp_board_leds_off(void)
+{
+    uint32_t i;
+    for(i = 0; i < LEDS_NUMBER; ++i)
+    {
+        bsp_board_led_off(i);
+    }
+}
+
+void bsp_board_leds_on(void)
+{
+    uint32_t i;
+    for(i = 0; i < LEDS_NUMBER; ++i)
+    {
+        bsp_board_led_on(i);
+    }
+}
+
+void bsp_board_led_invert(uint32_t led_idx)
+{
+    ASSERT(led_idx < LEDS_NUMBER);
+    nrf_gpio_pin_toggle(m_board_led_list[led_idx]);
+}
+
+void bsp_board_leds_init(void)
+{
+    uint32_t i;
+    for(i = 0; i < LEDS_NUMBER; ++i)
+    {
+        nrf_gpio_cfg_output(m_board_led_list[i]);
+    }
+    bsp_board_leds_off();
+}
+
+uint32_t bsp_board_led_idx_to_pin(uint32_t led_idx)
+{
+    ASSERT(led_idx < LEDS_NUMBER);
+    return m_board_led_list[led_idx];
+}
+
+uint32_t bsp_board_pin_to_led_idx(uint32_t pin_number)
+{
+    uint32_t ret = 0xFFFFFFFF;
+    uint32_t i;
+    for(i = 0; i < LEDS_NUMBER; ++i)
+    {
+        if (m_board_led_list[i] == pin_number)
+        {
+            ret = i;
+            break;
+        }
+    }
+    return ret;
+}
+#endif //LEDS_NUMBER > 0
+
+#if BUTTONS_NUMBER > 0
+bool bsp_board_button_state_get(uint32_t button_idx)
+{
+    ASSERT(button_idx < BUTTONS_NUMBER);
+    bool pin_set = nrf_gpio_pin_read(m_board_btn_list[button_idx]) ? true : false;
+    return (pin_set == (BUTTONS_ACTIVE_STATE ? true : false));
+}
+
+void bsp_board_buttons_init(void)
+{
+    uint32_t i;
+    for(i = 0; i < BUTTONS_NUMBER; ++i)
+    {
+        nrf_gpio_cfg_input(m_board_btn_list[i], BUTTON_PULL);
+    }
+}
+
+uint32_t bsp_board_pin_to_button_idx(uint32_t pin_number)
+{
+    uint32_t i;
+    uint32_t ret = 0xFFFFFFFF;
+    for(i = 0; i < BUTTONS_NUMBER; ++i)
+    {
+        if (m_board_btn_list[i] == pin_number)
+        {
+            ret = i;
+            break;
+        }
+    }
+    return ret;
+}
+
+uint32_t bsp_board_button_idx_to_pin(uint32_t button_idx)
+{
+    ASSERT(button_idx < BUTTONS_NUMBER);
+    return m_board_btn_list[button_idx];
+}
+#endif //BUTTONS_NUMBER > 0

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/boards.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,317 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef BOARDS_H
+#define BOARDS_H
+
+#include "nrf_gpio.h"
+
+#if defined(BOARD_NRF6310)
+  #include "nrf6310.h"
+#elif defined(BOARD_PCA10000)
+  #include "pca10000.h"
+#elif defined(BOARD_PCA10001)
+  #include "pca10001.h"
+#elif defined(BOARD_PCA10002)
+  #include "pca10000.h"
+#elif defined(BOARD_PCA10003)
+  #include "pca10003.h"
+#elif defined(BOARD_PCA20006)
+  #include "pca20006.h"
+#elif defined(BOARD_PCA10028)
+  #include "pca10028.h"
+#elif defined(BOARD_PCA10031)
+  #include "pca10031.h"
+#elif defined(BOARD_PCA10036)
+  #include "pca10036.h"
+#elif defined(BOARD_PCA10040)
+  #include "pca10040.h"
+#elif defined(BOARD_PCA10056)
+  #include "pca10056.h"
+#elif defined(BOARD_WT51822)
+  #include "wt51822.h"
+#elif defined(BOARD_N5DK1)
+  #include "n5_starterkit.h"
+#elif defined (BOARD_D52DK1)
+  #include "d52_starterkit.h"
+#elif defined (BOARD_ARDUINO_PRIMO)
+  #include "arduino_primo.h"
+#elif defined(BOARD_CUSTOM)
+  #include "custom_board.h"
+#else
+#error "Board is not defined"
+
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Function for returning the state of an LED.
+ *
+ * @param led_idx LED index (starting from 0), as defined in the board-specific header.
+ *
+ * @return True if the LED is turned on.
+ */
+bool bsp_board_led_state_get(uint32_t led_idx);
+
+/**
+ * Function for turning on an LED.
+ *
+ * @param led_idx LED index (starting from 0), as defined in the board-specific header.
+ */
+void bsp_board_led_on(uint32_t led_idx);
+
+/**
+ * Function for turning off an LED.
+ *
+ * @param led_idx LED index (starting from 0), as defined in the board-specific header.
+ */
+void bsp_board_led_off(uint32_t led_idx);
+
+/**
+ * Function for inverting the state of an LED.
+ *
+ * @param led_idx LED index (starting from 0), as defined in the board-specific header.
+ */
+void bsp_board_led_invert(uint32_t led_idx);
+/**
+ * Function for turning off all LEDs.
+ */
+void bsp_board_leds_off(void);
+
+/**
+ * Function for turning on all LEDs.
+ */
+void bsp_board_leds_on(void);
+
+/**
+ * Function for initializing LEDs.
+ */
+void bsp_board_leds_init(void);
+
+/**
+ * Function for converting pin number to LED index.
+ *
+ * @param pin_number Pin number.
+ *
+ * @return LED index of the given pin or 0xFFFFFFFF if invalid pin provided.
+ */
+uint32_t bsp_board_pin_to_led_idx(uint32_t pin_number);
+
+/**
+ * Function for converting LED index to pin number.
+ *
+ * @param led_idx LED index.
+ *
+ * @return Pin number.
+ */
+uint32_t bsp_board_led_idx_to_pin(uint32_t led_idx);
+
+/**
+ * Function for returning the state of a button.
+ *
+ * @param button_idx Button index (starting from 0), as defined in the board-specific header.
+ *
+ * @return True if the button is pressed.
+ */
+bool bsp_board_button_state_get(uint32_t button_idx);
+
+/**
+ * Function for initializing buttons.
+ */
+void bsp_board_buttons_init(void);
+
+/**
+ * Function for converting pin number to button index.
+ *
+ * @param pin_number Pin number.
+ *
+ * @return Button index of the given pin or 0xFFFFFFFF if invalid pin provided.
+ */
+uint32_t bsp_board_pin_to_button_idx(uint32_t pin_number);
+
+
+/**
+ * Function for converting button index to pin number.
+ *
+ * @param button_idx Button index.
+ *
+ * @return Pin number.
+ */
+uint32_t bsp_board_button_idx_to_pin(uint32_t button_idx);
+
+#define BSP_BOARD_LED_0 0
+#define BSP_BOARD_LED_1 1
+#define BSP_BOARD_LED_2 2
+#define BSP_BOARD_LED_3 3
+#define BSP_BOARD_LED_4 4
+#define BSP_BOARD_LED_5 5
+#define BSP_BOARD_LED_6 6
+#define BSP_BOARD_LED_7 7
+
+#ifdef BSP_LED_0
+#define BSP_LED_0_MASK (1<<BSP_LED_0)
+#else
+#define BSP_LED_0_MASK 0
+#endif
+#ifdef BSP_LED_1
+#define BSP_LED_1_MASK (1<<BSP_LED_1)
+#else
+#define BSP_LED_1_MASK 0
+#endif
+#ifdef BSP_LED_2
+#define BSP_LED_2_MASK (1<<BSP_LED_2)
+#else
+#define BSP_LED_2_MASK 0
+#endif
+#ifdef BSP_LED_3
+#define BSP_LED_3_MASK (1<<BSP_LED_3)
+#else
+#define BSP_LED_3_MASK 0
+#endif
+#ifdef BSP_LED_4
+#define BSP_LED_4_MASK (1<<BSP_LED_4)
+#else
+#define BSP_LED_4_MASK 0
+#endif
+#ifdef BSP_LED_5
+#define BSP_LED_5_MASK (1<<BSP_LED_5)
+#else
+#define BSP_LED_5_MASK 0
+#endif
+#ifdef BSP_LED_6
+#define BSP_LED_6_MASK (1<<BSP_LED_6)
+#else
+#define BSP_LED_6_MASK 0
+#endif
+#ifdef BSP_LED_7
+#define BSP_LED_7_MASK (1<<BSP_LED_7)
+#else
+#define BSP_LED_7_MASK 0
+#endif
+
+
+#define LEDS_MASK      (BSP_LED_0_MASK | BSP_LED_1_MASK | \
+                        BSP_LED_2_MASK | BSP_LED_3_MASK | \
+                        BSP_LED_4_MASK | BSP_LED_5_MASK | \
+                        BSP_LED_6_MASK | BSP_LED_7_MASK)
+
+#define BSP_BOARD_BUTTON_0 0
+#define BSP_BOARD_BUTTON_1 1
+#define BSP_BOARD_BUTTON_2 2
+#define BSP_BOARD_BUTTON_3 3
+#define BSP_BOARD_BUTTON_4 4
+#define BSP_BOARD_BUTTON_5 5
+#define BSP_BOARD_BUTTON_6 6
+#define BSP_BOARD_BUTTON_7 7
+
+
+#ifdef BSP_BUTTON_0
+#define BSP_BUTTON_0_MASK (1<<BSP_BUTTON_0)
+#else
+#define BSP_BUTTON_0_MASK 0
+#endif
+#ifdef BSP_BUTTON_1
+#define BSP_BUTTON_1_MASK (1<<BSP_BUTTON_1)
+#else
+#define BSP_BUTTON_1_MASK 0
+#endif
+#ifdef BSP_BUTTON_2
+#define BSP_BUTTON_2_MASK (1<<BSP_BUTTON_2)
+#else
+#define BSP_BUTTON_2_MASK 0
+#endif
+#ifdef BSP_BUTTON_3
+#define BSP_BUTTON_3_MASK (1<<BSP_BUTTON_3)
+#else
+#define BSP_BUTTON_3_MASK 0
+#endif
+#ifdef BSP_BUTTON_4
+#define BSP_BUTTON_4_MASK (1<<BSP_BUTTON_4)
+#else
+#define BSP_BUTTON_4_MASK 0
+#endif
+#ifdef BSP_BUTTON_5
+#define BSP_BUTTON_5_MASK (1<<BSP_BUTTON_5)
+#else
+#define BSP_BUTTON_5_MASK 0
+#endif
+#ifdef BSP_BUTTON_6
+#define BSP_BUTTON_6_MASK (1<<BSP_BUTTON_6)
+#else
+#define BSP_BUTTON_6_MASK 0
+#endif
+#ifdef BSP_BUTTON_7
+#define BSP_BUTTON_7_MASK (1<<BSP_BUTTON_7)
+#else
+#define BSP_BUTTON_7_MASK 0
+#endif
+
+#define BUTTONS_MASK   (BSP_BUTTON_0_MASK | BSP_BUTTON_1_MASK | \
+                        BSP_BUTTON_2_MASK | BSP_BUTTON_3_MASK | \
+                        BSP_BUTTON_4_MASK | BSP_BUTTON_5_MASK | \
+                        BSP_BUTTON_6_MASK | BSP_BUTTON_7_MASK)
+
+
+#define LEDS_OFF(leds_mask) do {  ASSERT(sizeof(leds_mask) == 4);                     \
+                        NRF_GPIO->OUTSET = (leds_mask) & (LEDS_MASK & LEDS_INV_MASK); \
+                        NRF_GPIO->OUTCLR = (leds_mask) & (LEDS_MASK & ~LEDS_INV_MASK); } while (0)
+
+#define LEDS_ON(leds_mask) do {  ASSERT(sizeof(leds_mask) == 4);                     \
+                       NRF_GPIO->OUTCLR = (leds_mask) & (LEDS_MASK & LEDS_INV_MASK); \
+                       NRF_GPIO->OUTSET = (leds_mask) & (LEDS_MASK & ~LEDS_INV_MASK); } while (0)
+
+#define LED_IS_ON(leds_mask) ((leds_mask) & (NRF_GPIO->OUT ^ LEDS_INV_MASK) )
+
+#define LEDS_INVERT(leds_mask) do { uint32_t gpio_state = NRF_GPIO->OUT;      \
+                              ASSERT(sizeof(leds_mask) == 4);                 \
+                              NRF_GPIO->OUTSET = ((leds_mask) & ~gpio_state); \
+                              NRF_GPIO->OUTCLR = ((leds_mask) & gpio_state); } while (0)
+
+#define LEDS_CONFIGURE(leds_mask) do { uint32_t pin;                  \
+                                  ASSERT(sizeof(leds_mask) == 4);     \
+                                  for (pin = 0; pin < 32; pin++)      \
+                                      if ( (leds_mask) & (1 << pin) ) \
+                                          nrf_gpio_cfg_output(pin); } while (0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/d52_starterkit.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,98 @@
+/*
+This software is subject to the license described in the License.txt file
+included with this software distribution. You may not use this file except in compliance
+with this license.
+
+Copyright (c) Dynastream Innovations Inc. 2016
+All rights reserved.
+*/
+
+#ifndef D52STARTERKIT_H
+#define D52STARTERKIT_H
+
+#include "nrf_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LEDs definitions for D52DK1
+#define LEDS_NUMBER    4
+
+// IO board active low leds
+// D52DK1 does not define LED_START or LED_STOP since the LEDS are not on sequential pins
+#define LED_A        24 //LED A on D52 Starter Kit IO Board
+#define LED_B        31 //LED B on D52 Starter Kit IO Board
+#define LED_C        17 //LED C on D52 Starter Kit IO Board
+#define LED_D        20 //LED D on D52 Starter Kit IO Board
+
+#define LEDS_ACTIVE_STATE 0
+
+#define LEDS_LIST { LED_A, LED_B, LED_C, LED_D }
+
+#define BSP_LED_0      LED_A
+#define BSP_LED_1      LED_B
+#define BSP_LED_2      LED_C
+#define BSP_LED_3      LED_D
+
+#define LEDS_INV_MASK  LEDS_MASK
+
+#define BUTTONS_NUMBER 4
+
+// IO board pull-up buttons
+#define BUTTON_A     6  //BUTTON A on D52 Starter Kit IO Board
+#define BUTTON_B     7  //BUTTON B on D52 Starter Kit IO Board
+#define BUTTON_C     16 //BUTTON C on D52 Starter Kit IO Board
+#define BUTTON_D     19 //BUTTON D on D52 Starter Kit IO Board
+#define BUTTON_PULL  NRF_GPIO_PIN_PULLUP
+
+#define BUTTONS_ACTIVE_STATE 0
+
+#define BSP_BUTTON_0   BUTTON_A
+#define BSP_BUTTON_1   BUTTON_B
+#define BSP_BUTTON_2   BUTTON_C
+#define BSP_BUTTON_3   BUTTON_D
+
+#define BUTTONS_LIST { BUTTON_A, BUTTON_B, BUTTON_C, BUTTON_D }
+
+// Battery board pull-up switches
+#define SWITCH_1     12 // Switch 1 on D52 Starter Kit Battery Board
+#define SWITCH_2     8  // Switch 2 on D52 Starter Kit Battery Board
+#define SWITCH_3     15 // Switch 3 on D52 Starter Kit Battery Board
+#define SWITCH_4     11 // Switch 4 on D52 Starter Kit Battery Board
+#define SWITCH_5     14 // Switch 5 on D52 Starter Kit Battery Board
+#define SWITCH_PULL  NRF_GPIO_PIN_PULLUP
+
+#define SWITCHES_NUMBER 5
+
+#define BSP_SWITCH_0 SWITCH_1
+#define BSP_SWITCH_1 SWITCH_2
+#define BSP_SWITCH_2 SWITCH_3
+#define BSP_SWITCH_3 SWITCH_4
+#define BSP_SWITCH_4 SWITCH_5
+
+#define BSP_SWITCH_0_MASK   (1<<BSP_SWITCH_0)
+#define BSP_SWITCH_1_MASK   (1<<BSP_SWITCH_1)
+#define BSP_SWITCH_2_MASK   (1<<BSP_SWITCH_2)
+#define BSP_SWITCH_3_MASK   (1<<BSP_SWITCH_3)
+#define BSP_SWITCH_4_MASK   (1<<BSP_SWITCH_4)
+
+#define SWITCHES_MASK (BSP_SWITCH_0_MASK | BSP_SWITCH_1_MASK | BSP_SWITCH_2_MASK | BSP_SWITCH_3_MASK | BSP_SWITCH_4_MASK)
+
+// D52DK1 does not have UART peripheral. Dummy defines for compilation.
+#define RX_PIN_NUMBER  UART_PIN_DISCONNECTED
+#define TX_PIN_NUMBER  UART_PIN_DISCONNECTED
+#define CTS_PIN_NUMBER UART_PIN_DISCONNECTED
+#define RTS_PIN_NUMBER UART_PIN_DISCONNECTED
+
+// Low frequency clock source to be used by the SoftDevice
+#define NRF_CLOCK_LFCLKSRC      {.source        = NRF_CLOCK_LF_SRC_XTAL,            \
+                                 .rc_ctiv       = 0,                                \
+                                 .rc_temp_ctiv  = 0,                                \
+                                 .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/n5_starterkit.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,97 @@
+/*
+This software is subject to the license described in the License.txt file
+included with this software distribution. You may not use this file except in compliance
+with this license.
+
+Copyright (c) Dynastream Innovations Inc. 2015
+All rights reserved.
+*/
+
+#ifndef N5STARTERKIT_H
+#define N5STARTERKIT_H
+
+#include "nrf_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LEDs definitions for N5DK1
+#define LEDS_NUMBER    4
+
+// IO board active low leds
+// N5DK1 does not define LED_START or LED_STOP since the LEDS are not on sequential pins
+#define LED_A        8  //LED A on N5 Starter Kit IO Board
+#define LED_B        3  //LED B on N5 Starter Kit IO Board
+#define LED_C        15 //LED C on N5 Starter Kit IO Board
+#define LED_D        30 //LED D on N5 Starter Kit IO Board
+
+#define LEDS_ACTIVE_STATE 0
+
+#define LEDS_LIST { LED_A, LED_B, LED_C, LED_D }
+
+#define LEDS_INV_MASK  LEDS_MASK
+
+#define BSP_LED_0      LED_A
+#define BSP_LED_1      LED_B
+#define BSP_LED_2      LED_C
+#define BSP_LED_3      LED_D
+
+#define BUTTONS_NUMBER 4
+
+// IO board pull-up buttons
+#define BUTTON_A     23 //BUTTON A on N5 Starter Kit IO Board
+#define BUTTON_B     2  //BUTTON B on N5 Starter Kit IO Board
+#define BUTTON_C     12 //BUTTON C on N5 Starter Kit IO Board
+#define BUTTON_D     11 //BUTTON D on N5 Starter Kit IO Board
+#define BUTTON_PULL  NRF_GPIO_PIN_PULLUP
+
+#define BUTTONS_ACTIVE_STATE 0
+
+#define BSP_BUTTON_0   BUTTON_A
+#define BSP_BUTTON_1   BUTTON_B
+#define BSP_BUTTON_2   BUTTON_C
+#define BSP_BUTTON_3   BUTTON_D
+
+#define BUTTONS_LIST { BUTTON_A, BUTTON_B, BUTTON_C, BUTTON_D }
+
+// Battery board pull-up switches
+#define SWITCH_1     5  // Switch 1 on N5 Starter Kit Battery Board
+#define SWITCH_2     0  // Switch 2 on N5 Starter Kit Battery Board
+#define SWITCH_3     6  // Switch 3 on N5 Starter Kit Battery Board
+#define SWITCH_4     24 // Switch 4 on N5 Starter Kit Battery Board
+#define SWITCH_5     9  // Switch 5 on N5 Starter Kit Battery Board
+#define SWITCH_PULL  NRF_GPIO_PIN_PULLUP
+
+#define SWITCHES_NUMBER 5
+
+#define BSP_SWITCH_0 SWITCH_1
+#define BSP_SWITCH_1 SWITCH_2
+#define BSP_SWITCH_2 SWITCH_3
+#define BSP_SWITCH_3 SWITCH_4
+#define BSP_SWITCH_4 SWITCH_5
+
+#define SWITCHES_MASK 0x01000261
+
+// N5DK1 does not have UART peripheral. Dummy defines for compilation.
+#define RX_PIN_NUMBER  UART_PIN_DISCONNECTED
+#define TX_PIN_NUMBER  UART_PIN_DISCONNECTED
+#define CTS_PIN_NUMBER UART_PIN_DISCONNECTED
+#define RTS_PIN_NUMBER UART_PIN_DISCONNECTED
+
+// Low frequency clock source to be used by the SoftDevice
+#ifdef S210
+#define NRF_CLOCK_LFCLKSRC      NRF_CLOCK_LFCLKSRC_XTAL_50_PPM
+#else
+#define NRF_CLOCK_LFCLKSRC      {.source        = NRF_CLOCK_LF_SRC_XTAL,            \
+                                 .rc_ctiv       = 0,                                \
+                                 .rc_temp_ctiv  = 0,                                \
+                                 .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_50_PPM}
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/nrf6310.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,184 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef NRF6310_H__
+#define NRF6310_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_START      8
+#define LED_0          8
+#define LED_1          9
+#define LED_2          10
+#define LED_3          11
+#define LED_4          12
+#define LED_5          13
+#define LED_6          14
+#define LED_7          15
+#define LED_STOP       15
+
+#define BSP_LED_0      LED_0
+#define BSP_LED_1      LED_1
+#define BSP_LED_2      LED_2
+#define BSP_LED_3      LED_3
+#define BSP_LED_4      LED_4
+#define BSP_LED_5      LED_5
+#define BSP_LED_6      LED_6
+#define BSP_LED_7      LED_7
+
+#define LEDS_ACTIVE_STATE 1
+
+#define BUTTON_START   0
+#define BUTTON_0       0
+#define BUTTON_1       1
+#define BUTTON_2       2
+#define BUTTON_3       3
+#define BUTTON_4       4
+#define BUTTON_5       5
+#define BUTTON_6       6
+#define BUTTON_7       7
+#define BUTTON_STOP    7
+#define BUTTON_PULL    NRF_GPIO_PIN_NOPULL
+
+#define BSP_BUTTON_0   BUTTON_0
+#define BSP_BUTTON_1   BUTTON_1
+#define BSP_BUTTON_2   BUTTON_2
+#define BSP_BUTTON_3   BUTTON_3
+#define BSP_BUTTON_4   BUTTON_4
+#define BSP_BUTTON_5   BUTTON_5
+#define BSP_BUTTON_6   BUTTON_6
+#define BSP_BUTTON_7   BUTTON_7
+
+#define BUTTONS_ACTIVE_STATE 1
+
+#define BUTTONS_LIST {BUTTON_0, BUTTON_1, BUTTON_2, BUTTON_3, BUTTON_4, BUTTON_5, BUTTON_6, BUTTON_7}
+#define LEDS_LIST {LED_0, LED_1, LED_2, LED_3, LED_4, LED_5, LED_6, LED_7}
+
+#define LEDS_INV_MASK  0x00000000
+
+#define BUTTONS_NUMBER 8
+#define LEDS_NUMBER    8
+
+#define RX_PIN_NUMBER  16    // UART RX pin number.
+#define TX_PIN_NUMBER  17    // UART TX pin number.
+#define CTS_PIN_NUMBER 18    // UART Clear To Send pin number. Not used if HWFC is set to false.
+#define RTS_PIN_NUMBER 19    // UART Request To Send pin number. Not used if HWFC is set to false.
+#define HWFC           false // UART hardware flow control.
+
+#define SPIS_MISO_PIN  20    // SPI MISO signal.
+#define SPIS_CSN_PIN   21    // SPI CSN signal.
+#define SPIS_MOSI_PIN  22    // SPI MOSI signal.
+#define SPIS_SCK_PIN   23    // SPI SCK signal.
+
+#define SPIM0_SCK_PIN       23u     /**< SPI clock GPIO pin number. */
+#define SPIM0_MOSI_PIN      20u     /**< SPI Master Out Slave In GPIO pin number. */
+#define SPIM0_MISO_PIN      22u     /**< SPI Master In Slave Out GPIO pin number. */
+#define SPIM0_SS_PIN        21u     /**< SPI Slave Select GPIO pin number. */
+
+#define SPIM1_SCK_PIN       16u     /**< SPI clock GPIO pin number. */
+#define SPIM1_MOSI_PIN      18u     /**< SPI Master Out Slave In GPIO pin number. */
+#define SPIM1_MISO_PIN      17u     /**< SPI Master In Slave Out GPIO pin number. */
+#define SPIM1_SS_PIN        19u     /**< SPI Slave Select GPIO pin number. */
+
+// serialization APPLICATION board
+#define SER_APP_RX_PIN              16    // UART RX pin number.
+#define SER_APP_TX_PIN              17    // UART TX pin number.
+#define SER_APP_CTS_PIN             18    // UART Clear To Send pin number.
+#define SER_APP_RTS_PIN             19    // UART Request To Send pin number.
+
+#if 0
+#define SER_APP_SPIM0_SCK_PIN       20     // SPI clock GPIO pin number.
+#define SER_APP_SPIM0_MOSI_PIN      17     // SPI Master Out Slave In GPIO pin number
+#define SER_APP_SPIM0_MISO_PIN      16     // SPI Master In Slave Out GPIO pin number
+#define SER_APP_SPIM0_SS_PIN        21     // SPI Slave Select GPIO pin number
+#define SER_APP_SPIM0_RDY_PIN       19     // SPI READY GPIO pin number
+#define SER_APP_SPIM0_REQ_PIN       18     // SPI REQUEST GPIO pin number
+#else
+#define SER_APP_SPIM0_SCK_PIN       23     // SPI clock GPIO pin number.
+#define SER_APP_SPIM0_MOSI_PIN      20     // SPI Master Out Slave In GPIO pin number
+#define SER_APP_SPIM0_MISO_PIN      22     // SPI Master In Slave Out GPIO pin number
+#define SER_APP_SPIM0_SS_PIN        21     // SPI Slave Select GPIO pin number
+#define SER_APP_SPIM0_RDY_PIN       29     // SPI READY GPIO pin number
+#define SER_APP_SPIM0_REQ_PIN       28     // SPI REQUEST GPIO pin number
+
+#endif
+
+// serialization CONNECTIVITY board
+#if 0
+#define SER_CON_RX_PIN              17    // UART RX pin number.
+#define SER_CON_TX_PIN              16    // UART TX pin number.
+#define SER_CON_CTS_PIN             19    // UART Clear To Send pin number. Not used if HWFC is set to false.
+#define SER_CON_RTS_PIN             18    // UART Request To Send pin number. Not used if HWFC is set to false.
+#else
+#define SER_CON_RX_PIN              16    // UART RX pin number.
+#define SER_CON_TX_PIN              17    // UART TX pin number.
+#define SER_CON_CTS_PIN             18    // UART Clear To Send pin number. Not used if HWFC is set to false.
+#define SER_CON_RTS_PIN             19    // UART Request To Send pin number. Not used if HWFC is set to false.
+#endif
+
+#if 0
+#define SER_CON_SPIS_SCK_PIN        20    // SPI SCK signal.
+#define SER_CON_SPIS_MISO_PIN       16    // SPI MISO signal.
+#define SER_CON_SPIS_MOSI_PIN       17    // SPI MOSI signal.
+#define SER_CON_SPIS_CSN_PIN        21    // SPI CSN signal.
+#define SER_CON_SPIS_RDY_PIN        19     // SPI READY GPIO pin number.
+#define SER_CON_SPIS_REQ_PIN        18     // SPI REQUEST GPIO pin number.
+#else
+#define SER_CON_SPIS_SCK_PIN        23    // SPI SCK signal.
+#define SER_CON_SPIS_MOSI_PIN       22    // SPI MOSI signal.
+#define SER_CON_SPIS_MISO_PIN       20    // SPI MISO signal.
+#define SER_CON_SPIS_CSN_PIN        21    // SPI CSN signal.
+#define SER_CON_SPIS_RDY_PIN        29     // SPI READY GPIO pin number.
+#define SER_CON_SPIS_REQ_PIN        28     // SPI REQUEST GPIO pin number.
+#endif
+
+#define SER_CONN_ASSERT_LED_PIN     LED_2
+
+// Low frequency clock source to be used by the SoftDevice
+#define NRF_CLOCK_LFCLKSRC      {.source        = NRF_CLOCK_LF_SRC_XTAL,            \
+                                 .rc_ctiv       = 0,                                \
+                                 .rc_temp_ctiv  = 0,                                \
+                                 .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // NRF6310_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10000.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,101 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef PCA10000_H
+#define PCA10000_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nrf_gpio.h"
+
+// Definitions for PCA10000 v2.0.0 or higher
+#if 1
+
+#define LEDS_NUMBER    3
+
+// there is RGB LED on this board
+#define LED_RGB_RED    21
+#define LED_RGB_GREEN  22
+#define LED_RGB_BLUE   23
+
+#define LED_START  LED_RGB_RED
+#define BSP_LED_0  LED_RGB_RED
+#define BSP_LED_1  LED_RGB_GREEN
+#define BSP_LED_2  LED_RGB_BLUE
+#define LED_STOP   LED_RGB_BLUE
+
+#define LEDS_ACTIVE_STATE 0
+
+#define BUTTONS_LIST {}
+#define LEDS_LIST { LED_RGB_RED, LED_RGB_GREEN, LED_RGB_BLUE }
+
+#define LEDS_INV_MASK  LEDS_MASK
+
+// there are no buttons on this board
+#define BUTTONS_NUMBER 0
+
+// UART pins connected to J-Link
+#define RX_PIN_NUMBER  11
+#define TX_PIN_NUMBER  9
+#define CTS_PIN_NUMBER 10
+#define RTS_PIN_NUMBER 8
+#define HWFC           true
+
+// Definitions for PCA10000 v1.0
+#else
+
+#define RX_PIN_NUMBER  3
+#define TX_PIN_NUMBER  1
+#define CTS_PIN_NUMBER 2
+#define RTS_PIN_NUMBER 0
+#define HWFC           true
+
+#endif
+
+// Low frequency clock source to be used by the SoftDevice
+#define NRF_CLOCK_LFCLKSRC      {.source        = NRF_CLOCK_LF_SRC_XTAL,            \
+                                 .rc_ctiv       = 0,                                \
+                                 .rc_temp_ctiv  = 0,                                \
+                                 .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10001.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,168 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef PCA10001_H
+#define PCA10001_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nrf_gpio.h"
+
+#define LED_START      18
+#define LED_0          18
+#define LED_1          19
+#define LED_STOP       19
+
+#define LEDS_ACTIVE_STATE 1
+
+#define BSP_LED_0      LED_0
+#define BSP_LED_1      LED_1
+
+#define LEDS_INV_MASK  0x00000000
+
+#define BUTTON_START   16
+#define BUTTON_0       16
+#define BUTTON_1       17
+#define BUTTON_STOP    17
+#define BUTTON_PULL    NRF_GPIO_PIN_PULLUP
+
+#define BUTTONS_ACTIVE_STATE 0
+
+#define BSP_BUTTON_0   BUTTON_0
+#define BSP_BUTTON_1   BUTTON_1
+
+#define BUTTONS_NUMBER 2
+#define LEDS_NUMBER    2
+
+#define BUTTONS_LIST { BUTTON_0, BUTTON_1 }
+#define LEDS_LIST { LED_0, LED_1 }
+
+#define RX_PIN_NUMBER  11
+#define TX_PIN_NUMBER  9
+#define CTS_PIN_NUMBER 10
+#define RTS_PIN_NUMBER 8
+#define HWFC           true
+
+#define SPIS_MISO_PIN  20    // SPI MISO signal.
+#define SPIS_CSN_PIN   21    // SPI CSN signal.
+#define SPIS_MOSI_PIN  22    // SPI MOSI signal.
+#define SPIS_SCK_PIN   23    // SPI SCK signal.
+
+#define SPIM0_SCK_PIN       23u     /**< SPI clock GPIO pin number. */
+#define SPIM0_MOSI_PIN      20u     /**< SPI Master Out Slave In GPIO pin number. */
+#define SPIM0_MISO_PIN      22u     /**< SPI Master In Slave Out GPIO pin number. */
+#define SPIM0_SS_PIN        21u     /**< SPI Slave Select GPIO pin number. */
+
+#define SPIM1_SCK_PIN       29u     /**< SPI clock GPIO pin number. */
+#define SPIM1_MOSI_PIN      24u     /**< SPI Master Out Slave In GPIO pin number. */
+#define SPIM1_MISO_PIN      28u     /**< SPI Master In Slave Out GPIO pin number. */
+#define SPIM1_SS_PIN        25u     /**< SPI Slave Select GPIO pin number. */
+
+// serialization APPLICATION board
+
+// UART
+// this configuration works with the SPI wires setup
+#define SER_APP_RX_PIN              20     // UART RX pin number.
+#define SER_APP_TX_PIN              22     // UART TX pin number.
+#define SER_APP_CTS_PIN             23     // UART Clear To Send pin number.
+#define SER_APP_RTS_PIN             21     // UART Request To Send pin number.
+
+// SPI
+#if 0
+#define SER_APP_SPIM0_SCK_PIN       20     // SPI clock GPIO pin number.
+#define SER_APP_SPIM0_MOSI_PIN      17     // SPI Master Out Slave In GPIO pin number
+#define SER_APP_SPIM0_MISO_PIN      16     // SPI Master In Slave Out GPIO pin number
+#define SER_APP_SPIM0_SS_PIN        21     // SPI Slave Select GPIO pin number
+#define SER_APP_SPIM0_RDY_PIN       19     // SPI READY GPIO pin number
+#define SER_APP_SPIM0_REQ_PIN       18     // SPI REQUEST GPIO pin number
+#else
+#define SER_APP_SPIM0_SCK_PIN       23     // SPI clock GPIO pin number.
+#define SER_APP_SPIM0_MOSI_PIN      20     // SPI Master Out Slave In GPIO pin number
+#define SER_APP_SPIM0_MISO_PIN      22     // SPI Master In Slave Out GPIO pin number
+#define SER_APP_SPIM0_SS_PIN        21     // SPI Slave Select GPIO pin number
+#define SER_APP_SPIM0_RDY_PIN       25     // SPI READY GPIO pin number
+#define SER_APP_SPIM0_REQ_PIN       24     // SPI REQUEST GPIO pin number
+#endif
+
+// serialization CONNECTIVITY board
+
+// UART
+#if 0
+#define SER_CON_RX_PIN              22    // UART RX pin number.
+#define SER_CON_TX_PIN              20    // UART TX pin number.
+#define SER_CON_CTS_PIN             21    // UART Clear To Send pin number. Not used if HWFC is set to false.
+#define SER_CON_RTS_PIN             23    // UART Request To Send pin number. Not used if HWFC is set to false.
+#else
+// this configuration works with the SPI wires setup
+#define SER_CON_RX_PIN              20    // UART RX pin number.
+#define SER_CON_TX_PIN              22    // UART TX pin number.
+#define SER_CON_CTS_PIN             21    // UART Clear To Send pin number. Not used if HWFC is set to false.
+#define SER_CON_RTS_PIN             23    // UART Request To Send pin number. Not used if HWFC is set to false.
+#endif
+
+//SPI
+#if 0
+#define SER_CON_SPIS_SCK_PIN        20    // SPI SCK signal.
+#define SER_CON_SPIS_MISO_PIN       16    // SPI MISO signal.
+#define SER_CON_SPIS_MOSI_PIN       17    // SPI MOSI signal.
+#define SER_CON_SPIS_CSN_PIN        21    // SPI CSN signal.
+#define SER_CON_SPIS_RDY_PIN        19     // SPI READY GPIO pin number.
+#define SER_CON_SPIS_REQ_PIN        18     // SPI REQUEST GPIO pin number.
+#else
+#define SER_CON_SPIS_SCK_PIN        23    // SPI SCK signal.
+#define SER_CON_SPIS_MOSI_PIN       22    // SPI MOSI signal.
+#define SER_CON_SPIS_MISO_PIN       20    // SPI MISO signal.
+#define SER_CON_SPIS_CSN_PIN        21    // SPI CSN signal.
+#define SER_CON_SPIS_RDY_PIN        25     // SPI READY GPIO pin number.
+#define SER_CON_SPIS_REQ_PIN        24     // SPI REQUEST GPIO pin number.
+#endif
+
+#define SER_CONN_ASSERT_LED_PIN     LED_0
+
+// Low frequency clock source to be used by the SoftDevice
+#define NRF_CLOCK_LFCLKSRC      {.source        = NRF_CLOCK_LF_SRC_XTAL,            \
+                                 .rc_ctiv       = 0,                                \
+                                 .rc_temp_ctiv  = 0,                                \
+                                 .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10003.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,96 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef PCA10003_H
+#define PCA10003_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nrf_gpio.h"
+
+#define LED_START      18
+#define LED_0          18
+#define LED_1          19
+#define LED_STOP       19
+
+#define LEDS_ACTIVE_STATE 1
+
+#define LEDS_INV_MASK  0x00000000
+
+#define BSP_LED_0      LED_0
+#define BSP_LED_1      LED_1
+
+#define BUTTON_START   16
+#define BUTTON_0       16
+#define BUTTON_1       17
+#define BUTTON_STOP    17
+#define BUTTON_PULL    NRF_GPIO_PIN_PULLUP
+
+#define BUTTONS_ACTIVE_STATE 0
+
+#define BSP_BUTTON_0   BUTTON_0
+#define BSP_BUTTON_1   BUTTON_1
+
+#define BUTTONS_NUMBER 2
+#define LEDS_NUMBER    2
+#define LEDS_LIST { LED_0, LED_1 }
+
+#define BUTTONS_LIST { BUTTON_0, BUTTON_1 }
+
+#define RX_PIN_NUMBER  11
+#define TX_PIN_NUMBER  9
+#define CTS_PIN_NUMBER 10
+#define RTS_PIN_NUMBER 8
+#define HWFC           true
+
+// Low frequency clock source to be used by the SoftDevice
+#ifdef S210
+#define NRF_CLOCK_LFCLKSRC      NRF_CLOCK_LFCLKSRC_XTAL_20_PPM
+#else
+#define NRF_CLOCK_LFCLKSRC      {.source        = NRF_CLOCK_LF_SRC_XTAL,            \
+                                 .rc_ctiv       = 0,                                \
+                                 .rc_temp_ctiv  = 0,                                \
+                                 .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM}
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10028.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,178 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef PCA10028_H
+#define PCA10028_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nrf_gpio.h"
+
+// LEDs definitions for PCA10028
+#define LEDS_NUMBER    4
+
+#define LED_START      21
+#define LED_1          21
+#define LED_2          22
+#define LED_3          23
+#define LED_4          24
+#define LED_STOP       24
+
+#define LEDS_ACTIVE_STATE 0
+
+#define LEDS_LIST { LED_1, LED_2, LED_3, LED_4 }
+
+#define LEDS_INV_MASK  LEDS_MASK
+
+#define BSP_LED_0      LED_1
+#define BSP_LED_1      LED_2
+#define BSP_LED_2      LED_3
+#define BSP_LED_3      LED_4
+
+#define BUTTONS_NUMBER 4
+
+#define BUTTON_START   17
+#define BUTTON_1       17
+#define BUTTON_2       18
+#define BUTTON_3       19
+#define BUTTON_4       20
+#define BUTTON_STOP    20
+#define BUTTON_PULL    NRF_GPIO_PIN_PULLUP
+
+#define BUTTONS_ACTIVE_STATE 0
+
+#define BUTTONS_LIST { BUTTON_1, BUTTON_2, BUTTON_3, BUTTON_4 }
+
+#define BSP_BUTTON_0   BUTTON_1
+#define BSP_BUTTON_1   BUTTON_2
+#define BSP_BUTTON_2   BUTTON_3
+#define BSP_BUTTON_3   BUTTON_4
+
+#define RX_PIN_NUMBER  11
+#define TX_PIN_NUMBER  9
+#define CTS_PIN_NUMBER 10
+#define RTS_PIN_NUMBER 8
+#define HWFC           true
+
+#define SPIS_MISO_PIN  28    // SPI MISO signal.
+#define SPIS_CSN_PIN   12    // SPI CSN signal.
+#define SPIS_MOSI_PIN  25    // SPI MOSI signal.
+#define SPIS_SCK_PIN   29    // SPI SCK signal.
+
+#define SPIM0_SCK_PIN       4     /**< SPI clock GPIO pin number. */
+#define SPIM0_MOSI_PIN      1     /**< SPI Master Out Slave In GPIO pin number. */
+#define SPIM0_MISO_PIN      3     /**< SPI Master In Slave Out GPIO pin number. */
+#define SPIM0_SS_PIN        2     /**< SPI Slave Select GPIO pin number. */
+
+#define SPIM1_SCK_PIN       15     /**< SPI clock GPIO pin number. */
+#define SPIM1_MOSI_PIN      12     /**< SPI Master Out Slave In GPIO pin number. */
+#define SPIM1_MISO_PIN      14     /**< SPI Master In Slave Out GPIO pin number. */
+#define SPIM1_SS_PIN        13     /**< SPI Slave Select GPIO pin number. */
+
+// serialization APPLICATION board
+#define SER_CONN_CHIP_RESET_PIN     12    // Pin used to reset connectivity chip
+
+#define SER_APP_RX_PIN              25    // UART RX pin number.
+#define SER_APP_TX_PIN              28    // UART TX pin number.
+#define SER_APP_CTS_PIN             0     // UART Clear To Send pin number.
+#define SER_APP_RTS_PIN             29    // UART Request To Send pin number.
+
+#define SER_APP_SPIM0_SCK_PIN       7     // SPI clock GPIO pin number.
+#define SER_APP_SPIM0_MOSI_PIN      0     // SPI Master Out Slave In GPIO pin number
+#define SER_APP_SPIM0_MISO_PIN      30    // SPI Master In Slave Out GPIO pin number
+#define SER_APP_SPIM0_SS_PIN        25    // SPI Slave Select GPIO pin number
+#define SER_APP_SPIM0_RDY_PIN       29    // SPI READY GPIO pin number
+#define SER_APP_SPIM0_REQ_PIN       28    // SPI REQUEST GPIO pin number
+
+// serialization CONNECTIVITY board
+#define SER_CON_RX_PIN              28    // UART RX pin number.
+#define SER_CON_TX_PIN              25    // UART TX pin number.
+#define SER_CON_CTS_PIN             29    // UART Clear To Send pin number. Not used if HWFC is set to false.
+#define SER_CON_RTS_PIN             0    // UART Request To Send pin number. Not used if HWFC is set to false.
+
+
+#define SER_CON_SPIS_SCK_PIN        7     // SPI SCK signal.
+#define SER_CON_SPIS_MOSI_PIN       0     // SPI MOSI signal.
+#define SER_CON_SPIS_MISO_PIN       30    // SPI MISO signal.
+#define SER_CON_SPIS_CSN_PIN        25    // SPI CSN signal.
+#define SER_CON_SPIS_RDY_PIN        29    // SPI READY GPIO pin number.
+#define SER_CON_SPIS_REQ_PIN        28    // SPI REQUEST GPIO pin number.
+
+// Arduino board mappings
+#define ARDUINO_SCL_PIN             7     // SCL signal pin
+#define ARDUINO_SDA_PIN             30    // SDA signal pin
+#define ARDUINO_AREF_PIN            0     // Aref pin
+#define ARDUINO_13_PIN              29    // Digital pin 13
+#define ARDUINO_12_PIN              28    // Digital pin 12
+#define ARDUINO_11_PIN              25    // Digital pin 11
+#define ARDUINO_10_PIN              24    // Digital pin 10
+#define ARDUINO_9_PIN               23    // Digital pin 9
+#define ARDUINO_8_PIN               20    // Digital pin 8
+
+#define ARDUINO_7_PIN               19    // Digital pin 7
+#define ARDUINO_6_PIN               18    // Digital pin 6
+#define ARDUINO_5_PIN               17    // Digital pin 5
+#define ARDUINO_4_PIN               16    // Digital pin 4
+#define ARDUINO_3_PIN               15    // Digital pin 3
+#define ARDUINO_2_PIN               14    // Digital pin 2
+#define ARDUINO_1_PIN               13    // Digital pin 1
+#define ARDUINO_0_PIN               12    // Digital pin 0
+
+#define ARDUINO_A0_PIN              1     // Analog channel 0
+#define ARDUINO_A1_PIN              2     // Analog channel 1
+#define ARDUINO_A2_PIN              3     // Analog channel 2
+#define ARDUINO_A3_PIN              4     // Analog channel 3
+#define ARDUINO_A4_PIN              5     // Analog channel 4
+#define ARDUINO_A5_PIN              6     // Analog channel 5
+
+// Low frequency clock source to be used by the SoftDevice
+#ifdef S210
+#define NRF_CLOCK_LFCLKSRC      NRF_CLOCK_LFCLKSRC_XTAL_20_PPM
+#else
+#define NRF_CLOCK_LFCLKSRC      {.source        = NRF_CLOCK_LF_SRC_XTAL,            \
+                                 .rc_ctiv       = 0,                                \
+                                 .rc_temp_ctiv  = 0,                                \
+                                 .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM}
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // PCA10028_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10031.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,95 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef PCA10031_H
+#define PCA10031_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nrf_gpio.h"
+
+// LEDs definitions for PCA10031
+#define LEDS_NUMBER    3
+
+#define LED_START      21
+#define LED_RGB_RED    21
+#define LED_RGB_GREEN  22
+#define LED_RGB_BLUE   23
+#define LED_STOP       23
+
+#define LEDS_ACTIVE_STATE 1
+
+#define LEDS_INV_MASK  LEDS_MASK
+
+#define LED_RGB_RED_MASK    (1<<LED_RGB_RED)
+#define LED_RGB_GREEN_MASK  (1<<LED_RGB_GREEN)
+#define LED_RGB_BLUE_MASK   (1<<LED_RGB_BLUE)
+
+#define LEDS_LIST { LED_RGB_RED, LED_RGB_GREEN, LED_RGB_BLUE}
+// defining RGB led as 3 single LEDs
+#define BSP_LED_0 LED_RGB_RED
+#define BSP_LED_1 LED_RGB_GREEN
+#define BSP_LED_2 LED_RGB_BLUE
+
+// there are no user buttons
+#define BUTTONS_NUMBER 0
+#define BUTTONS_LIST {}
+
+// UART connection with J-Link
+#define RX_PIN_NUMBER  11
+#define TX_PIN_NUMBER  9
+#define CTS_PIN_NUMBER 10
+#define RTS_PIN_NUMBER 8
+#define HWFC           true
+
+// Low frequency clock source to be used by the SoftDevice
+#ifdef S210
+#define NRF_CLOCK_LFCLKSRC      NRF_CLOCK_LFCLKSRC_XTAL_20_PPM
+#else
+#define NRF_CLOCK_LFCLKSRC      {.source        = NRF_CLOCK_LF_SRC_XTAL,            \
+                                 .rc_ctiv       = 0,                                \
+                                 .rc_temp_ctiv  = 0,                                \
+                                 .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM}
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10036.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,180 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef PCA10036_H
+#define PCA10036_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nrf_gpio.h"
+
+// LEDs definitions for PCA10036
+#define LEDS_NUMBER    4
+
+#define LED_START      17
+#define LED_1          17
+#define LED_2          18
+#define LED_3          19
+#define LED_4          20
+#define LED_STOP       20
+
+#define LEDS_ACTIVE_STATE 0
+
+#define LEDS_INV_MASK  LEDS_MASK
+
+#define LEDS_LIST { LED_1, LED_2, LED_3, LED_4 }
+
+#define BSP_LED_0      LED_1
+#define BSP_LED_1      LED_2
+#define BSP_LED_2      LED_3
+#define BSP_LED_3      LED_4
+
+#define BUTTONS_NUMBER 4
+
+#define BUTTON_START   13
+#define BUTTON_1       13
+#define BUTTON_2       14
+#define BUTTON_3       15
+#define BUTTON_4       16
+#define BUTTON_STOP    16
+#define BUTTON_PULL    NRF_GPIO_PIN_PULLUP
+
+#define BUTTONS_ACTIVE_STATE 0
+
+#define BUTTONS_LIST { BUTTON_1, BUTTON_2, BUTTON_3, BUTTON_4 }
+
+#define BSP_BUTTON_0   BUTTON_1
+#define BSP_BUTTON_1   BUTTON_2
+#define BSP_BUTTON_2   BUTTON_3
+#define BSP_BUTTON_3   BUTTON_4
+
+#define RX_PIN_NUMBER  8
+#define TX_PIN_NUMBER  6
+#define CTS_PIN_NUMBER 7
+#define RTS_PIN_NUMBER 5
+#define HWFC           true
+
+#define SPIS_MISO_PIN   28  // SPI MISO signal.
+#define SPIS_CSN_PIN    12  // SPI CSN signal.
+#define SPIS_MOSI_PIN   25  // SPI MOSI signal.
+#define SPIS_SCK_PIN    29  // SPI SCK signal.
+
+#define SPIM0_SCK_PIN   29  // SPI clock GPIO pin number.
+#define SPIM0_MOSI_PIN  25  // SPI Master Out Slave In GPIO pin number.
+#define SPIM0_MISO_PIN  28  // SPI Master In Slave Out GPIO pin number.
+#define SPIM0_SS_PIN    12  // SPI Slave Select GPIO pin number.
+
+#define SPIM1_SCK_PIN   2   // SPI clock GPIO pin number.
+#define SPIM1_MOSI_PIN  3   // SPI Master Out Slave In GPIO pin number.
+#define SPIM1_MISO_PIN  4   // SPI Master In Slave Out GPIO pin number.
+#define SPIM1_SS_PIN    5   // SPI Slave Select GPIO pin number.
+
+#define SPIM2_SCK_PIN   12  // SPI clock GPIO pin number.
+#define SPIM2_MOSI_PIN  13  // SPI Master Out Slave In GPIO pin number.
+#define SPIM2_MISO_PIN  14  // SPI Master In Slave Out GPIO pin number.
+#define SPIM2_SS_PIN    15  // SPI Slave Select GPIO pin number.
+
+// serialization APPLICATION board - temp. setup for running serialized MEMU tests
+#define SER_APP_RX_PIN              23    // UART RX pin number.
+#define SER_APP_TX_PIN              24    // UART TX pin number.
+#define SER_APP_CTS_PIN             2     // UART Clear To Send pin number.
+#define SER_APP_RTS_PIN             25    // UART Request To Send pin number.
+
+#define SER_APP_SPIM0_SCK_PIN       27     // SPI clock GPIO pin number.
+#define SER_APP_SPIM0_MOSI_PIN      2      // SPI Master Out Slave In GPIO pin number
+#define SER_APP_SPIM0_MISO_PIN      26     // SPI Master In Slave Out GPIO pin number
+#define SER_APP_SPIM0_SS_PIN        23     // SPI Slave Select GPIO pin number
+#define SER_APP_SPIM0_RDY_PIN       25     // SPI READY GPIO pin number
+#define SER_APP_SPIM0_REQ_PIN       24     // SPI REQUEST GPIO pin number
+
+// serialization CONNECTIVITY board
+#define SER_CON_RX_PIN              24    // UART RX pin number.
+#define SER_CON_TX_PIN              23    // UART TX pin number.
+#define SER_CON_CTS_PIN             25    // UART Clear To Send pin number. Not used if HWFC is set to false.
+#define SER_CON_RTS_PIN             2     // UART Request To Send pin number. Not used if HWFC is set to false.
+
+
+#define SER_CON_SPIS_SCK_PIN        27    // SPI SCK signal.
+#define SER_CON_SPIS_MOSI_PIN       2     // SPI MOSI signal.
+#define SER_CON_SPIS_MISO_PIN       26    // SPI MISO signal.
+#define SER_CON_SPIS_CSN_PIN        23    // SPI CSN signal.
+#define SER_CON_SPIS_RDY_PIN        25    // SPI READY GPIO pin number.
+#define SER_CON_SPIS_REQ_PIN        24    // SPI REQUEST GPIO pin number.
+
+#define SER_CONN_CHIP_RESET_PIN     11    // Pin used to reset connectivity chip
+
+// Arduino board mappings
+#define ARDUINO_SCL_PIN             27    // SCL signal pin
+#define ARDUINO_SDA_PIN             26    // SDA signal pin
+#define ARDUINO_AREF_PIN            2     // Aref pin
+#define ARDUINO_13_PIN              25    // Digital pin 13
+#define ARDUINO_12_PIN              24    // Digital pin 12
+#define ARDUINO_11_PIN              23    // Digital pin 11
+#define ARDUINO_10_PIN              22    // Digital pin 10
+#define ARDUINO_9_PIN               20    // Digital pin 9
+#define ARDUINO_8_PIN               19    // Digital pin 8
+
+#define ARDUINO_7_PIN               18    // Digital pin 7
+#define ARDUINO_6_PIN               17    // Digital pin 6
+#define ARDUINO_5_PIN               16    // Digital pin 5
+#define ARDUINO_4_PIN               15    // Digital pin 4
+#define ARDUINO_3_PIN               14    // Digital pin 3
+#define ARDUINO_2_PIN               13    // Digital pin 2
+#define ARDUINO_1_PIN               12    // Digital pin 1
+#define ARDUINO_0_PIN               11    // Digital pin 0
+
+#define ARDUINO_A0_PIN              3     // Analog channel 0
+#define ARDUINO_A1_PIN              4     // Analog channel 1
+#define ARDUINO_A2_PIN              28    // Analog channel 2
+#define ARDUINO_A3_PIN              29    // Analog channel 3
+#define ARDUINO_A4_PIN              30    // Analog channel 4
+#define ARDUINO_A5_PIN              31    // Analog channel 5
+
+// Low frequency clock source to be used by the SoftDevice
+#define NRF_CLOCK_LFCLKSRC      {.source        = NRF_CLOCK_LF_SRC_XTAL,            \
+                                 .rc_ctiv       = 0,                                \
+                                 .rc_temp_ctiv  = 0,                                \
+                                 .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // PCA10036_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10040.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,180 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef PCA10040_H
+#define PCA10040_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nrf_gpio.h"
+
+// LEDs definitions for PCA10040
+#define LEDS_NUMBER    4
+
+#define LED_START      17
+#define LED_1          17
+#define LED_2          18
+#define LED_3          19
+#define LED_4          20
+#define LED_STOP       20
+   
+#define LEDS_ACTIVE_STATE 0
+
+#define LEDS_INV_MASK  LEDS_MASK
+
+#define LEDS_LIST { LED_1, LED_2, LED_3, LED_4 }
+
+#define BSP_LED_0      LED_1
+#define BSP_LED_1      LED_2
+#define BSP_LED_2      LED_3
+#define BSP_LED_3      LED_4
+
+#define BUTTONS_NUMBER 4
+
+#define BUTTON_START   13
+#define BUTTON_1       13
+#define BUTTON_2       14
+#define BUTTON_3       15
+#define BUTTON_4       16
+#define BUTTON_STOP    16
+#define BUTTON_PULL    NRF_GPIO_PIN_PULLUP
+
+#define BUTTONS_ACTIVE_STATE 0
+
+#define BUTTONS_LIST { BUTTON_1, BUTTON_2, BUTTON_3, BUTTON_4 }
+
+#define BSP_BUTTON_0   BUTTON_1
+#define BSP_BUTTON_1   BUTTON_2
+#define BSP_BUTTON_2   BUTTON_3
+#define BSP_BUTTON_3   BUTTON_4
+
+#define RX_PIN_NUMBER  8
+#define TX_PIN_NUMBER  6
+#define CTS_PIN_NUMBER 7
+#define RTS_PIN_NUMBER 5
+#define HWFC           true
+
+#define SPIS_MISO_PIN   28  // SPI MISO signal.
+#define SPIS_CSN_PIN    12  // SPI CSN signal.
+#define SPIS_MOSI_PIN   25  // SPI MOSI signal.
+#define SPIS_SCK_PIN    29  // SPI SCK signal.
+
+#define SPIM0_SCK_PIN   29  // SPI clock GPIO pin number.
+#define SPIM0_MOSI_PIN  25  // SPI Master Out Slave In GPIO pin number.
+#define SPIM0_MISO_PIN  28  // SPI Master In Slave Out GPIO pin number.
+#define SPIM0_SS_PIN    12  // SPI Slave Select GPIO pin number.
+
+#define SPIM1_SCK_PIN   2   // SPI clock GPIO pin number.
+#define SPIM1_MOSI_PIN  3   // SPI Master Out Slave In GPIO pin number.
+#define SPIM1_MISO_PIN  4   // SPI Master In Slave Out GPIO pin number.
+#define SPIM1_SS_PIN    5   // SPI Slave Select GPIO pin number.
+
+#define SPIM2_SCK_PIN   12  // SPI clock GPIO pin number.
+#define SPIM2_MOSI_PIN  13  // SPI Master Out Slave In GPIO pin number.
+#define SPIM2_MISO_PIN  14  // SPI Master In Slave Out GPIO pin number.
+#define SPIM2_SS_PIN    15  // SPI Slave Select GPIO pin number.
+
+// serialization APPLICATION board - temp. setup for running serialized MEMU tests
+#define SER_APP_RX_PIN              23    // UART RX pin number.
+#define SER_APP_TX_PIN              24    // UART TX pin number.
+#define SER_APP_CTS_PIN             2     // UART Clear To Send pin number.
+#define SER_APP_RTS_PIN             25    // UART Request To Send pin number.
+
+#define SER_APP_SPIM0_SCK_PIN       27     // SPI clock GPIO pin number.
+#define SER_APP_SPIM0_MOSI_PIN      2      // SPI Master Out Slave In GPIO pin number
+#define SER_APP_SPIM0_MISO_PIN      26     // SPI Master In Slave Out GPIO pin number
+#define SER_APP_SPIM0_SS_PIN        23     // SPI Slave Select GPIO pin number
+#define SER_APP_SPIM0_RDY_PIN       25     // SPI READY GPIO pin number
+#define SER_APP_SPIM0_REQ_PIN       24     // SPI REQUEST GPIO pin number
+
+// serialization CONNECTIVITY board
+#define SER_CON_RX_PIN              24    // UART RX pin number.
+#define SER_CON_TX_PIN              23    // UART TX pin number.
+#define SER_CON_CTS_PIN             25    // UART Clear To Send pin number. Not used if HWFC is set to false.
+#define SER_CON_RTS_PIN             2     // UART Request To Send pin number. Not used if HWFC is set to false.
+
+
+#define SER_CON_SPIS_SCK_PIN        27    // SPI SCK signal.
+#define SER_CON_SPIS_MOSI_PIN       2     // SPI MOSI signal.
+#define SER_CON_SPIS_MISO_PIN       26    // SPI MISO signal.
+#define SER_CON_SPIS_CSN_PIN        23    // SPI CSN signal.
+#define SER_CON_SPIS_RDY_PIN        25    // SPI READY GPIO pin number.
+#define SER_CON_SPIS_REQ_PIN        24    // SPI REQUEST GPIO pin number.
+
+#define SER_CONN_CHIP_RESET_PIN     11    // Pin used to reset connectivity chip
+
+
+// Arduino board mappings
+#define ARDUINO_SCL_PIN             27    // SCL signal pin
+#define ARDUINO_SDA_PIN             26    // SDA signal pin
+#define ARDUINO_AREF_PIN            2     // Aref pin
+#define ARDUINO_13_PIN              25    // Digital pin 13
+#define ARDUINO_12_PIN              24    // Digital pin 12
+#define ARDUINO_11_PIN              23    // Digital pin 11
+#define ARDUINO_10_PIN              22    // Digital pin 10
+#define ARDUINO_9_PIN               20    // Digital pin 9
+#define ARDUINO_8_PIN               19    // Digital pin 8
+
+#define ARDUINO_7_PIN               18    // Digital pin 7
+#define ARDUINO_6_PIN               17    // Digital pin 6
+#define ARDUINO_5_PIN               16    // Digital pin 5
+#define ARDUINO_4_PIN               15    // Digital pin 4
+#define ARDUINO_3_PIN               14    // Digital pin 3
+#define ARDUINO_2_PIN               13    // Digital pin 2
+#define ARDUINO_1_PIN               12    // Digital pin 1
+#define ARDUINO_0_PIN               11    // Digital pin 0
+
+#define ARDUINO_A0_PIN              3     // Analog channel 0
+#define ARDUINO_A1_PIN              4     // Analog channel 1
+#define ARDUINO_A2_PIN              28    // Analog channel 2
+#define ARDUINO_A3_PIN              29    // Analog channel 3
+#define ARDUINO_A4_PIN              30    // Analog channel 4
+#define ARDUINO_A5_PIN              31    // Analog channel 5
+
+// Low frequency clock source to be used by the SoftDevice
+#define NRF_CLOCK_LFCLKSRC      {.source        = NRF_CLOCK_LF_SRC_XTAL,            \
+                                 .rc_ctiv       = 0,                                \
+                                 .rc_temp_ctiv  = 0,                                \
+                                 .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // PCA10040_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10056.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,164 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef PCA10056_H
+#define PCA10056_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nrf_gpio.h"
+
+// LEDs definitions for PCA10056
+#define LEDS_NUMBER    4
+
+#define LED_1          NRF_GPIO_PIN_MAP(0,13)
+#define LED_2          NRF_GPIO_PIN_MAP(0,14)
+#define LED_3          NRF_GPIO_PIN_MAP(0,15)
+#define LED_4          NRF_GPIO_PIN_MAP(0,16)
+
+#define LEDS_ACTIVE_STATE 0
+
+#define LEDS_LIST { LED_1, LED_2, LED_3, LED_4 }
+
+#define LEDS_INV_MASK  LEDS_MASK
+
+#define BSP_LED_0      13
+#define BSP_LED_1      14
+#define BSP_LED_2      15
+#define BSP_LED_3      16
+
+#define BUTTONS_NUMBER 4
+
+#define BUTTON_1       11
+#define BUTTON_2       12
+#define BUTTON_3       24
+#define BUTTON_4       25
+#define BUTTON_PULL    NRF_GPIO_PIN_PULLUP
+
+#define BUTTONS_ACTIVE_STATE 0
+
+#define BUTTONS_LIST { BUTTON_1, BUTTON_2, BUTTON_3, BUTTON_4 }
+
+#define BSP_BUTTON_0   BUTTON_1
+#define BSP_BUTTON_1   BUTTON_2
+#define BSP_BUTTON_2   BUTTON_3
+#define BSP_BUTTON_3   BUTTON_4
+
+#define RX_PIN_NUMBER  8
+#define TX_PIN_NUMBER  6
+#define CTS_PIN_NUMBER 7
+#define RTS_PIN_NUMBER 5
+#define HWFC           true
+
+#define BSP_QSPI_SCK_PIN   19
+#define BSP_QSPI_CSN_PIN   17
+#define BSP_QSPI_IO0_PIN   20
+#define BSP_QSPI_IO1_PIN   21
+#define BSP_QSPI_IO2_PIN   22
+#define BSP_QSPI_IO3_PIN   23
+
+
+// serialization APPLICATION board - temp. setup for running serialized MEMU tests
+#define SER_APP_RX_PIN              NRF_GPIO_PIN_MAP(1,13)    // UART RX pin number.
+#define SER_APP_TX_PIN              NRF_GPIO_PIN_MAP(1,14)    // UART TX pin number.
+#define SER_APP_CTS_PIN             NRF_GPIO_PIN_MAP(0,2)     // UART Clear To Send pin number.
+#define SER_APP_RTS_PIN             NRF_GPIO_PIN_MAP(1,15)    // UART Request To Send pin number.
+
+#define SER_APP_SPIM0_SCK_PIN       NRF_GPIO_PIN_MAP(0,27)     // SPI clock GPIO pin number.
+#define SER_APP_SPIM0_MOSI_PIN      NRF_GPIO_PIN_MAP(0,2)      // SPI Master Out Slave In GPIO pin number
+#define SER_APP_SPIM0_MISO_PIN      NRF_GPIO_PIN_MAP(0,26)     // SPI Master In Slave Out GPIO pin number
+#define SER_APP_SPIM0_SS_PIN        NRF_GPIO_PIN_MAP(1,13)     // SPI Slave Select GPIO pin number
+#define SER_APP_SPIM0_RDY_PIN       NRF_GPIO_PIN_MAP(1,15)     // SPI READY GPIO pin number
+#define SER_APP_SPIM0_REQ_PIN       NRF_GPIO_PIN_MAP(1,14)     // SPI REQUEST GPIO pin number
+
+// serialization CONNECTIVITY board
+#define SER_CON_RX_PIN              NRF_GPIO_PIN_MAP(1,14)    // UART RX pin number.
+#define SER_CON_TX_PIN              NRF_GPIO_PIN_MAP(1,13)    // UART TX pin number.
+#define SER_CON_CTS_PIN             NRF_GPIO_PIN_MAP(1,15)    // UART Clear To Send pin number. Not used if HWFC is set to false.
+#define SER_CON_RTS_PIN             NRF_GPIO_PIN_MAP(0,2)     // UART Request To Send pin number. Not used if HWFC is set to false.
+
+
+#define SER_CON_SPIS_SCK_PIN        NRF_GPIO_PIN_MAP(0,27)    // SPI SCK signal.
+#define SER_CON_SPIS_MOSI_PIN       NRF_GPIO_PIN_MAP(0,2)     // SPI MOSI signal.
+#define SER_CON_SPIS_MISO_PIN       NRF_GPIO_PIN_MAP(0,26)    // SPI MISO signal.
+#define SER_CON_SPIS_CSN_PIN        NRF_GPIO_PIN_MAP(1,13)    // SPI CSN signal.
+#define SER_CON_SPIS_RDY_PIN        NRF_GPIO_PIN_MAP(1,15)    // SPI READY GPIO pin number.
+#define SER_CON_SPIS_REQ_PIN        NRF_GPIO_PIN_MAP(1,14)    // SPI REQUEST GPIO pin number.
+
+#define SER_CONN_CHIP_RESET_PIN     NRF_GPIO_PIN_MAP(1,1)    // Pin used to reset connectivity chip
+
+// Arduino board mappings
+#define ARDUINO_SCL_PIN             27    // SCL signal pin
+#define ARDUINO_SDA_PIN             26    // SDA signal pin
+#define ARDUINO_AREF_PIN            2     // Aref pin
+
+#define ARDUINO_13_PIN              NRF_GPIO_PIN_MAP(1, 15)  // Digital pin 13
+#define ARDUINO_12_PIN              NRF_GPIO_PIN_MAP(1, 14)  // Digital pin 12
+#define ARDUINO_11_PIN              NRF_GPIO_PIN_MAP(1, 13)  // Digital pin 11
+#define ARDUINO_10_PIN              NRF_GPIO_PIN_MAP(1, 12)  // Digital pin 10
+#define ARDUINO_9_PIN               NRF_GPIO_PIN_MAP(1, 11)  // Digital pin 9
+#define ARDUINO_8_PIN               NRF_GPIO_PIN_MAP(1, 10)  // Digital pin 8
+
+#define ARDUINO_7_PIN               NRF_GPIO_PIN_MAP(1, 8) // Digital pin 7
+#define ARDUINO_6_PIN               NRF_GPIO_PIN_MAP(1, 7) // Digital pin 6
+#define ARDUINO_5_PIN               NRF_GPIO_PIN_MAP(1, 6) // Digital pin 5
+#define ARDUINO_4_PIN               NRF_GPIO_PIN_MAP(1, 5) // Digital pin 4
+#define ARDUINO_3_PIN               NRF_GPIO_PIN_MAP(1, 4) // Digital pin 3
+#define ARDUINO_2_PIN               NRF_GPIO_PIN_MAP(1, 3) // Digital pin 2
+#define ARDUINO_1_PIN               NRF_GPIO_PIN_MAP(1, 2) // Digital pin 1
+#define ARDUINO_0_PIN               NRF_GPIO_PIN_MAP(1, 1) // Digital pin 0
+
+#define ARDUINO_A0_PIN              3     // Analog channel 0
+#define ARDUINO_A1_PIN              4     // Analog channel 1
+#define ARDUINO_A2_PIN              28    // Analog channel 2
+#define ARDUINO_A3_PIN              29    // Analog channel 3
+#define ARDUINO_A4_PIN              30    // Analog channel 4
+#define ARDUINO_A5_PIN              31    // Analog channel 5
+
+// Low frequency clock source to be used by the SoftDevice
+#define NRF_CLOCK_LFCLKSRC      {.source        = NRF_CLOCK_LF_SRC_XTAL,            \
+                                 .rc_ctiv       = 0,                                \
+                                 .rc_temp_ctiv  = 0,                                \
+                                 .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // PCA10056_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca20006.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,97 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef PCA20006_H
+#define PCA20006_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "nrf_gpio.h"
+
+// LEDs and buttons definition for PCA20006 board (beacon)
+#define LEDS_NUMBER    3
+
+#define LED_RGB_RED    16
+#define LED_RGB_GREEN  12
+#define LED_RGB_BLUE   15
+
+#define LEDS_ACTIVE_STATE 0
+
+#define BSP_LED_0 LED_RGB_RED
+#define BSP_LED_1 LED_RGB_GREEN
+#define BSP_LED_2 LED_RGB_BLUE
+
+#define LEDS_LIST { LED_RGB_RED, LED_RGB_GREEN, LED_RGB_BLUE}
+
+#define LEDS_INV_MASK  LEDS_MASK
+
+#define BUTTON_0       8
+#define BUTTON_1       18
+#define BUTTON_PULL    NRF_GPIO_PIN_PULLUP
+
+#define BUTTONS_ACTIVE_STATE 0
+
+#define BSP_BUTTON_0   BUTTON_0
+#define BSP_BUTTON_1   BUTTON_1
+
+#define BUTTONS_NUMBER 2
+
+#define BUTTONS_LIST { BUTTON_0, BUTTON_1 }
+
+#define RX_PIN_NUMBER  24
+#define TX_PIN_NUMBER  9
+#define CTS_PIN_NUMBER 21
+#define RTS_PIN_NUMBER 11
+#define HWFC           true
+
+// Low frequency clock source to be used by the SoftDevice
+#ifdef S210
+#define NRF_CLOCK_LFCLKSRC      NRF_CLOCK_LFCLKSRC_XTAL_20_PPM
+#else
+#define NRF_CLOCK_LFCLKSRC      {.source = NRF_CLOCK_LF_SRC_XTAL, .rc_ctiv = 0, .rc_temp_ctiv = 0, .xtal_accuracy=NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM}
+#endif
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/wt51822.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,92 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef WT51822_H
+#define WT51822_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LEDS_NUMBER    3
+
+#define LED_1          3
+#define LED_2          4
+#define LED_3          5
+
+#define LEDS_LIST { LED_1, LED_2, LED_3 }
+
+#define LEDS_ACTIVE_STATE 0
+
+#define BSP_LED_0      LED_1
+#define BSP_LED_1      LED_2
+#define BSP_LED_2      LED_3
+
+#define LEDS_INV_MASK  LEDS_MASK
+
+#define BUTTONS_NUMBER 3
+
+#define SW_1           0
+#define SW_2           1
+#define SW_3           2
+#define BUTTON_PULL    NRF_GPIO_PIN_PULLUP
+
+#define BUTTONS_LIST { SW_1, SW_2, SW_3 }
+
+#define BUTTONS_ACTIVE_STATE 0
+
+#define BSP_BUTTON_0   SW_1
+#define BSP_BUTTON_1   SW_2
+#define BSP_BUTTON_2   SW_3
+
+#define RX_PIN_NUMBER  13
+#define TX_PIN_NUMBER  12
+#define CTS_PIN_NUMBER 14
+#define RTS_PIN_NUMBER 15
+#define HWFC           true
+
+#define SER_CON_RX_PIN              13
+#define SER_CON_TX_PIN              12
+#define SER_CON_CTS_PIN             14
+#define SER_CON_RTS_PIN             15
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/compiler_abstraction.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,152 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+#ifndef _COMPILER_ABSTRACTION_H
+#define _COMPILER_ABSTRACTION_H
+
+/*lint ++flb "Enter library region" */
+
+#if defined ( __CC_ARM )
+
+    #ifndef __ASM
+        #define __ASM               __asm
+    #endif
+
+    #ifndef __INLINE
+        #define __INLINE            __inline
+    #endif
+
+    #ifndef __WEAK
+        #define __WEAK              __weak
+    #endif
+
+    #ifndef __ALIGN
+        #define __ALIGN(n)          __align(n)
+    #endif
+
+    #ifndef __PACKED
+        #define __PACKED            __packed
+    #endif
+
+    #define GET_SP()                __current_sp()
+
+#elif defined ( __ICCARM__ )
+
+    #ifndef __ASM
+        #define __ASM               __asm
+    #endif
+
+    #ifndef __INLINE
+        #define __INLINE            inline
+    #endif
+
+    #ifndef __WEAK
+        #define __WEAK              __weak
+    #endif
+
+    #ifndef __ALIGN
+        #define STRING_PRAGMA(x) _Pragma(#x)
+        #define __ALIGN(n) STRING_PRAGMA(data_alignment = n)
+    #endif
+
+    #ifndef __PACKED
+        #define __PACKED            __packed
+    #endif
+    
+    #define GET_SP()                __get_SP()
+
+#elif defined   ( __GNUC__ )
+
+    #ifndef __ASM
+        #define __ASM               __asm
+    #endif
+
+    #ifndef __INLINE
+        #define __INLINE            inline
+    #endif
+
+    #ifndef __WEAK
+        #define __WEAK              __attribute__((weak))
+    #endif
+
+    #ifndef __ALIGN
+        #define __ALIGN(n)          __attribute__((aligned(n)))
+    #endif
+
+    #ifndef __PACKED
+        #define __PACKED           __attribute__((packed)) 
+    #endif
+
+    #define GET_SP()                gcc_current_sp()
+
+    static inline unsigned int gcc_current_sp(void)
+    {
+        register unsigned sp __ASM("sp");
+        return sp;
+    }
+
+#elif defined   ( __TASKING__ )
+
+    #ifndef __ASM
+        #define __ASM               __asm
+    #endif
+
+    #ifndef __INLINE
+        #define __INLINE            inline
+    #endif
+
+    #ifndef __WEAK
+        #define __WEAK              __attribute__((weak))
+    #endif
+
+    #ifndef __ALIGN
+        #define __ALIGN(n)          __align(n)
+    #endif
+    
+    /* Not defined for TASKING. */
+    #ifndef __PACKED
+        #define __PACKED
+    #endif
+
+    #define GET_SP()                __get_MSP()
+
+#endif
+
+/*lint --flb "Leave library region" */
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,93 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+#ifndef NRF_H
+#define NRF_H
+
+/* MDK version */
+#define MDK_MAJOR_VERSION   8
+#define MDK_MINOR_VERSION   11
+#define MDK_MICRO_VERSION   1
+
+/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */
+#if defined (NRF52)
+    #ifndef NRF52832_XXAA
+        #define NRF52832_XXAA
+    #endif
+#endif
+
+/* Define NRF52_SERIES for common use in nRF52 series devices. */
+#if defined (NRF52832_XXAA) || defined (NRF52840_XXAA)
+    #define NRF52_SERIES
+#endif
+
+
+#if defined(_WIN32)
+    /* Do not include nrf specific files when building for PC host */
+#elif defined(__unix)
+    /* Do not include nrf specific files when building for PC host */
+#elif defined(__APPLE__)
+    /* Do not include nrf specific files when building for PC host */
+#else
+
+    /* Device selection for device includes. */
+    #if defined (NRF51)
+        #include "nrf51.h"
+        #include "nrf51_bitfields.h"
+        #include "nrf51_deprecated.h"
+    #elif defined (NRF52840_XXAA)
+        #include "nrf52840.h"
+        #include "nrf52840_bitfields.h"
+        #include "nrf51_to_nrf52840.h"
+        #include "nrf52_to_nrf52840.h"
+    #elif defined (NRF52832_XXAA)
+        #include "nrf52.h"
+        #include "nrf52_bitfields.h"
+        #include "nrf51_to_nrf52.h"
+        #include "nrf52_name_change.h"
+    #else
+        #error "Device must be defined. See nrf.h."
+    #endif /* NRF51, NRF52832_XXAA, NRF52840_XXAA */
+
+    #include "compiler_abstraction.h"
+    #include "irq_handlers_hw.h"
+
+#endif /* _WIN32 || __unix || __APPLE__ */
+
+#endif /* NRF_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,1193 @@
+
+/****************************************************************************************************//**
+ * @file     nrf51.h
+ *
+ * @brief    CMSIS Cortex-M0 Peripheral Access Layer Header File for
+ *           nrf51 from Nordic Semiconductor.
+ *
+ * @version  V522
+ * @date     18. November 2016
+ *
+ * @note     Generated with SVDConv V2.81d 
+ *           from CMSIS SVD File 'nrf51.svd' Version 522,
+ *
+ * @par      Copyright (c) 2016, Nordic Semiconductor ASA
+ *           All rights reserved.
+ *           
+ *           Redistribution and use in source and binary forms, with or without
+ *           modification, are permitted provided that the following conditions are met:
+ *           
+ *           * Redistributions of source code must retain the above copyright notice, this
+ *           list of conditions and the following disclaimer.
+ *           
+ *           * Redistributions in binary form must reproduce the above copyright notice,
+ *           this list of conditions and the following disclaimer in the documentation
+ *           and/or other materials provided with the distribution.
+ *           
+ *           * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *           contributors may be used to endorse or promote products derived from
+ *           this software without specific prior written permission.
+ *           
+ *           THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *           AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *           IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *           DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ *           FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *           DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ *           SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ *           CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ *           OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *           OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *           
+ *
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup Nordic Semiconductor
+  * @{
+  */
+
+/** @addtogroup nrf51
+  * @{
+  */
+
+#ifndef NRF51_H
+#define NRF51_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum {
+/* -------------------  Cortex-M0 Processor Exceptions Numbers  ------------------- */
+  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */
+  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */
+  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
+  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */
+  DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */
+  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */
+  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */
+/* ----------------------  nrf51 Specific Interrupt Numbers  ---------------------- */
+  POWER_CLOCK_IRQn              =   0,              /*!<   0  POWER_CLOCK                                                      */
+  RADIO_IRQn                    =   1,              /*!<   1  RADIO                                                            */
+  UART0_IRQn                    =   2,              /*!<   2  UART0                                                            */
+  SPI0_TWI0_IRQn                =   3,              /*!<   3  SPI0_TWI0                                                        */
+  SPI1_TWI1_IRQn                =   4,              /*!<   4  SPI1_TWI1                                                        */
+  GPIOTE_IRQn                   =   6,              /*!<   6  GPIOTE                                                           */
+  ADC_IRQn                      =   7,              /*!<   7  ADC                                                              */
+  TIMER0_IRQn                   =   8,              /*!<   8  TIMER0                                                           */
+  TIMER1_IRQn                   =   9,              /*!<   9  TIMER1                                                           */
+  TIMER2_IRQn                   =  10,              /*!<  10  TIMER2                                                           */
+  RTC0_IRQn                     =  11,              /*!<  11  RTC0                                                             */
+  TEMP_IRQn                     =  12,              /*!<  12  TEMP                                                             */
+  RNG_IRQn                      =  13,              /*!<  13  RNG                                                              */
+  ECB_IRQn                      =  14,              /*!<  14  ECB                                                              */
+  CCM_AAR_IRQn                  =  15,              /*!<  15  CCM_AAR                                                          */
+  WDT_IRQn                      =  16,              /*!<  16  WDT                                                              */
+  RTC1_IRQn                     =  17,              /*!<  17  RTC1                                                             */
+  QDEC_IRQn                     =  18,              /*!<  18  QDEC                                                             */
+  LPCOMP_IRQn                   =  19,              /*!<  19  LPCOMP                                                           */
+  SWI0_IRQn                     =  20,              /*!<  20  SWI0                                                             */
+  SWI1_IRQn                     =  21,              /*!<  21  SWI1                                                             */
+  SWI2_IRQn                     =  22,              /*!<  22  SWI2                                                             */
+  SWI3_IRQn                     =  23,              /*!<  23  SWI3                                                             */
+  SWI4_IRQn                     =  24,              /*!<  24  SWI4                                                             */
+  SWI5_IRQn                     =  25               /*!<  25  SWI5                                                             */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
+#define __CM0_REV                 0x0301            /*!< Cortex-M0 Core Revision                                               */
+#define __MPU_PRESENT                  0            /*!< MPU present or not                                                    */
+#define __NVIC_PRIO_BITS               2            /*!< Number of Bits used for Priority Levels                               */
+#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0.h"                               /*!< Cortex-M0 processor and core peripherals                              */
+#include "system_nrf51.h"                           /*!< nrf51 System                                                          */
+
+
+/* ================================================================================ */
+/* ================       Device Specific Peripheral Section       ================ */
+/* ================================================================================ */
+
+
+/** @addtogroup Device_Peripheral_Registers
+  * @{
+  */
+
+
+/* -------------------  Start of section using anonymous unions  ------------------ */
+#if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__ICCARM__)
+  #pragma language=extended
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+  #pragma warning 586
+#else
+  #warning Not supported compiler type
+#endif
+
+
+typedef struct {
+  __O  uint32_t  EN;                                /*!< Enable channel group.                                                 */
+  __O  uint32_t  DIS;                               /*!< Disable channel group.                                                */
+} PPI_TASKS_CHG_Type;
+
+typedef struct {
+  __IO uint32_t  EEP;                               /*!< Channel event end-point.                                              */
+  __IO uint32_t  TEP;                               /*!< Channel task end-point.                                               */
+} PPI_CH_Type;
+
+
+/* ================================================================================ */
+/* ================                      POWER                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Power Control. (POWER)
+  */
+
+typedef struct {                                    /*!< POWER Structure                                                       */
+  __I  uint32_t  RESERVED0[30];
+  __O  uint32_t  TASKS_CONSTLAT;                    /*!< Enable constant latency mode.                                         */
+  __O  uint32_t  TASKS_LOWPWR;                      /*!< Enable low power mode (variable latency).                             */
+  __I  uint32_t  RESERVED1[34];
+  __IO uint32_t  EVENTS_POFWARN;                    /*!< Power failure warning.                                                */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[61];
+  __IO uint32_t  RESETREAS;                         /*!< Reset reason.                                                         */
+  __I  uint32_t  RESERVED4[9];
+  __I  uint32_t  RAMSTATUS;                         /*!< Ram status register.                                                  */
+  __I  uint32_t  RESERVED5[53];
+  __O  uint32_t  SYSTEMOFF;                         /*!< System off register.                                                  */
+  __I  uint32_t  RESERVED6[3];
+  __IO uint32_t  POFCON;                            /*!< Power failure configuration.                                          */
+  __I  uint32_t  RESERVED7[2];
+  __IO uint32_t  GPREGRET;                          /*!< General purpose retention register. This register is a retained
+                                                         register.                                                             */
+  __I  uint32_t  RESERVED8;
+  __IO uint32_t  RAMON;                             /*!< Ram on/off.                                                           */
+  __I  uint32_t  RESERVED9[7];
+  __IO uint32_t  RESET;                             /*!< Pin reset functionality configuration register. This register
+                                                         is a retained register.                                               */
+  __I  uint32_t  RESERVED10[3];
+  __IO uint32_t  RAMONB;                            /*!< Ram on/off.                                                           */
+  __I  uint32_t  RESERVED11[8];
+  __IO uint32_t  DCDCEN;                            /*!< DCDC converter enable configuration register.                         */
+  __I  uint32_t  RESERVED12[291];
+  __IO uint32_t  DCDCFORCE;                         /*!< DCDC power-up force register.                                         */
+} NRF_POWER_Type;
+
+
+/* ================================================================================ */
+/* ================                      CLOCK                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Clock control. (CLOCK)
+  */
+
+typedef struct {                                    /*!< CLOCK Structure                                                       */
+  __O  uint32_t  TASKS_HFCLKSTART;                  /*!< Start HFCLK clock source.                                             */
+  __O  uint32_t  TASKS_HFCLKSTOP;                   /*!< Stop HFCLK clock source.                                              */
+  __O  uint32_t  TASKS_LFCLKSTART;                  /*!< Start LFCLK clock source.                                             */
+  __O  uint32_t  TASKS_LFCLKSTOP;                   /*!< Stop LFCLK clock source.                                              */
+  __O  uint32_t  TASKS_CAL;                         /*!< Start calibration of LFCLK RC oscillator.                             */
+  __O  uint32_t  TASKS_CTSTART;                     /*!< Start calibration timer.                                              */
+  __O  uint32_t  TASKS_CTSTOP;                      /*!< Stop calibration timer.                                               */
+  __I  uint32_t  RESERVED0[57];
+  __IO uint32_t  EVENTS_HFCLKSTARTED;               /*!< HFCLK oscillator started.                                             */
+  __IO uint32_t  EVENTS_LFCLKSTARTED;               /*!< LFCLK oscillator started.                                             */
+  __I  uint32_t  RESERVED1;
+  __IO uint32_t  EVENTS_DONE;                       /*!< Calibration of LFCLK RC oscillator completed.                         */
+  __IO uint32_t  EVENTS_CTTO;                       /*!< Calibration timer timeout.                                            */
+  __I  uint32_t  RESERVED2[124];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[63];
+  __I  uint32_t  HFCLKRUN;                          /*!< Task HFCLKSTART trigger status.                                       */
+  __I  uint32_t  HFCLKSTAT;                         /*!< High frequency clock status.                                          */
+  __I  uint32_t  RESERVED4;
+  __I  uint32_t  LFCLKRUN;                          /*!< Task LFCLKSTART triggered status.                                     */
+  __I  uint32_t  LFCLKSTAT;                         /*!< Low frequency clock status.                                           */
+  __I  uint32_t  LFCLKSRCCOPY;                      /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
+                                                         triggered.                                                            */
+  __I  uint32_t  RESERVED5[62];
+  __IO uint32_t  LFCLKSRC;                          /*!< Clock source for the LFCLK clock.                                     */
+  __I  uint32_t  RESERVED6[7];
+  __IO uint32_t  CTIV;                              /*!< Calibration timer interval.                                           */
+  __I  uint32_t  RESERVED7[5];
+  __IO uint32_t  XTALFREQ;                          /*!< Crystal frequency.                                                    */
+} NRF_CLOCK_Type;
+
+
+/* ================================================================================ */
+/* ================                       MPU                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Memory Protection Unit. (MPU)
+  */
+
+typedef struct {                                    /*!< MPU Structure                                                         */
+  __I  uint32_t  RESERVED0[330];
+  __IO uint32_t  PERR0;                             /*!< Configuration of peripherals in mpu regions.                          */
+  __IO uint32_t  RLENR0;                            /*!< Length of RAM region 0.                                               */
+  __I  uint32_t  RESERVED1[52];
+  __IO uint32_t  PROTENSET0;                        /*!< Erase and write protection bit enable set register.                   */
+  __IO uint32_t  PROTENSET1;                        /*!< Erase and write protection bit enable set register.                   */
+  __IO uint32_t  DISABLEINDEBUG;                    /*!< Disable erase and write protection mechanism in debug mode.           */
+  __IO uint32_t  PROTBLOCKSIZE;                     /*!< Erase and write protection block size.                                */
+} NRF_MPU_Type;
+
+
+/* ================================================================================ */
+/* ================                      RADIO                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief The radio. (RADIO)
+  */
+
+typedef struct {                                    /*!< RADIO Structure                                                       */
+  __O  uint32_t  TASKS_TXEN;                        /*!< Enable radio in TX mode.                                              */
+  __O  uint32_t  TASKS_RXEN;                        /*!< Enable radio in RX mode.                                              */
+  __O  uint32_t  TASKS_START;                       /*!< Start radio.                                                          */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop radio.                                                           */
+  __O  uint32_t  TASKS_DISABLE;                     /*!< Disable radio.                                                        */
+  __O  uint32_t  TASKS_RSSISTART;                   /*!< Start the RSSI and take one sample of the receive signal strength.    */
+  __O  uint32_t  TASKS_RSSISTOP;                    /*!< Stop the RSSI measurement.                                            */
+  __O  uint32_t  TASKS_BCSTART;                     /*!< Start the bit counter.                                                */
+  __O  uint32_t  TASKS_BCSTOP;                      /*!< Stop the bit counter.                                                 */
+  __I  uint32_t  RESERVED0[55];
+  __IO uint32_t  EVENTS_READY;                      /*!< Ready event.                                                          */
+  __IO uint32_t  EVENTS_ADDRESS;                    /*!< Address event.                                                        */
+  __IO uint32_t  EVENTS_PAYLOAD;                    /*!< Payload event.                                                        */
+  __IO uint32_t  EVENTS_END;                        /*!< End event.                                                            */
+  __IO uint32_t  EVENTS_DISABLED;                   /*!< Disable event.                                                        */
+  __IO uint32_t  EVENTS_DEVMATCH;                   /*!< A device address match occurred on the last received packet.          */
+  __IO uint32_t  EVENTS_DEVMISS;                    /*!< No device address match occurred on the last received packet.         */
+  __IO uint32_t  EVENTS_RSSIEND;                    /*!< Sampling of the receive signal strength complete. A new RSSI
+                                                         sample is ready for readout at the RSSISAMPLE register.               */
+  __I  uint32_t  RESERVED1[2];
+  __IO uint32_t  EVENTS_BCMATCH;                    /*!< Bit counter reached bit count value specified in BCC register.        */
+  __I  uint32_t  RESERVED2[53];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the radio.                                              */
+  __I  uint32_t  RESERVED3[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED4[61];
+  __I  uint32_t  CRCSTATUS;                         /*!< CRC status of received packet.                                        */
+  __I  uint32_t  RESERVED5;
+  __I  uint32_t  RXMATCH;                           /*!< Received address.                                                     */
+  __I  uint32_t  RXCRC;                             /*!< Received CRC.                                                         */
+  __I  uint32_t  DAI;                               /*!< Device address match index.                                           */
+  __I  uint32_t  RESERVED6[60];
+  __IO uint32_t  PACKETPTR;                         /*!< Packet pointer. Decision point: START task.                           */
+  __IO uint32_t  FREQUENCY;                         /*!< Frequency.                                                            */
+  __IO uint32_t  TXPOWER;                           /*!< Output power.                                                         */
+  __IO uint32_t  MODE;                              /*!< Data rate and modulation.                                             */
+  __IO uint32_t  PCNF0;                             /*!< Packet configuration 0.                                               */
+  __IO uint32_t  PCNF1;                             /*!< Packet configuration 1.                                               */
+  __IO uint32_t  BASE0;                             /*!< Radio base address 0. Decision point: START task.                     */
+  __IO uint32_t  BASE1;                             /*!< Radio base address 1. Decision point: START task.                     */
+  __IO uint32_t  PREFIX0;                           /*!< Prefixes bytes for logical addresses 0 to 3.                          */
+  __IO uint32_t  PREFIX1;                           /*!< Prefixes bytes for logical addresses 4 to 7.                          */
+  __IO uint32_t  TXADDRESS;                         /*!< Transmit address select.                                              */
+  __IO uint32_t  RXADDRESSES;                       /*!< Receive address select.                                               */
+  __IO uint32_t  CRCCNF;                            /*!< CRC configuration.                                                    */
+  __IO uint32_t  CRCPOLY;                           /*!< CRC polynomial.                                                       */
+  __IO uint32_t  CRCINIT;                           /*!< CRC initial value.                                                    */
+  __IO uint32_t  TEST;                              /*!< Test features enable register.                                        */
+  __IO uint32_t  TIFS;                              /*!< Inter Frame Spacing in microseconds.                                  */
+  __I  uint32_t  RSSISAMPLE;                        /*!< RSSI sample.                                                          */
+  __I  uint32_t  RESERVED7;
+  __I  uint32_t  STATE;                             /*!< Current radio state.                                                  */
+  __IO uint32_t  DATAWHITEIV;                       /*!< Data whitening initial value.                                         */
+  __I  uint32_t  RESERVED8[2];
+  __IO uint32_t  BCC;                               /*!< Bit counter compare.                                                  */
+  __I  uint32_t  RESERVED9[39];
+  __IO uint32_t  DAB[8];                            /*!< Device address base segment.                                          */
+  __IO uint32_t  DAP[8];                            /*!< Device address prefix.                                                */
+  __IO uint32_t  DACNF;                             /*!< Device address match configuration.                                   */
+  __I  uint32_t  RESERVED10[56];
+  __IO uint32_t  OVERRIDE0;                         /*!< Trim value override register 0.                                       */
+  __IO uint32_t  OVERRIDE1;                         /*!< Trim value override register 1.                                       */
+  __IO uint32_t  OVERRIDE2;                         /*!< Trim value override register 2.                                       */
+  __IO uint32_t  OVERRIDE3;                         /*!< Trim value override register 3.                                       */
+  __IO uint32_t  OVERRIDE4;                         /*!< Trim value override register 4.                                       */
+  __I  uint32_t  RESERVED11[561];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_RADIO_Type;
+
+
+/* ================================================================================ */
+/* ================                      UART                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Universal Asynchronous Receiver/Transmitter. (UART)
+  */
+
+typedef struct {                                    /*!< UART Structure                                                        */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start UART receiver.                                                  */
+  __O  uint32_t  TASKS_STOPRX;                      /*!< Stop UART receiver.                                                   */
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start UART transmitter.                                               */
+  __O  uint32_t  TASKS_STOPTX;                      /*!< Stop UART transmitter.                                                */
+  __I  uint32_t  RESERVED0[3];
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend UART.                                                         */
+  __I  uint32_t  RESERVED1[56];
+  __IO uint32_t  EVENTS_CTS;                        /*!< CTS activated.                                                        */
+  __IO uint32_t  EVENTS_NCTS;                       /*!< CTS deactivated.                                                      */
+  __IO uint32_t  EVENTS_RXDRDY;                     /*!< Data received in RXD.                                                 */
+  __I  uint32_t  RESERVED2[4];
+  __IO uint32_t  EVENTS_TXDRDY;                     /*!< Data sent from TXD.                                                   */
+  __I  uint32_t  RESERVED3;
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Error detected.                                                       */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_RXTO;                       /*!< Receiver timeout.                                                     */
+  __I  uint32_t  RESERVED5[46];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for UART.                                                   */
+  __I  uint32_t  RESERVED6[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED7[93];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source. Write error field to 1 to clear error.                  */
+  __I  uint32_t  RESERVED8[31];
+  __IO uint32_t  ENABLE;                            /*!< Enable UART and acquire IOs.                                          */
+  __I  uint32_t  RESERVED9;
+  __IO uint32_t  PSELRTS;                           /*!< Pin select for RTS.                                                   */
+  __IO uint32_t  PSELTXD;                           /*!< Pin select for TXD.                                                   */
+  __IO uint32_t  PSELCTS;                           /*!< Pin select for CTS.                                                   */
+  __IO uint32_t  PSELRXD;                           /*!< Pin select for RXD.                                                   */
+  __I  uint32_t  RXD;                               /*!< RXD register. On read action the buffer pointer is displaced.
+                                                         Once read the character is consumed. If read when no character
+                                                          available, the UART will stop working.                               */
+  __O  uint32_t  TXD;                               /*!< TXD register.                                                         */
+  __I  uint32_t  RESERVED10;
+  __IO uint32_t  BAUDRATE;                          /*!< UART Baudrate.                                                        */
+  __I  uint32_t  RESERVED11[17];
+  __IO uint32_t  CONFIG;                            /*!< Configuration of parity and hardware flow control register.           */
+  __I  uint32_t  RESERVED12[675];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_UART_Type;
+
+
+/* ================================================================================ */
+/* ================                       SPI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief SPI master 0. (SPI)
+  */
+
+typedef struct {                                    /*!< SPI Structure                                                         */
+  __I  uint32_t  RESERVED0[66];
+  __IO uint32_t  EVENTS_READY;                      /*!< TXD byte sent and RXD byte received.                                  */
+  __I  uint32_t  RESERVED1[126];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED2[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPI.                                                           */
+  __I  uint32_t  RESERVED3;
+  __IO uint32_t  PSELSCK;                           /*!< Pin select for SCK.                                                   */
+  __IO uint32_t  PSELMOSI;                          /*!< Pin select for MOSI.                                                  */
+  __IO uint32_t  PSELMISO;                          /*!< Pin select for MISO.                                                  */
+  __I  uint32_t  RESERVED4;
+  __I  uint32_t  RXD;                               /*!< RX data.                                                              */
+  __IO uint32_t  TXD;                               /*!< TX data.                                                              */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency                                                         */
+  __I  uint32_t  RESERVED6[11];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
+  __I  uint32_t  RESERVED7[681];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_SPI_Type;
+
+
+/* ================================================================================ */
+/* ================                       TWI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Two-wire interface master 0. (TWI)
+  */
+
+typedef struct {                                    /*!< TWI Structure                                                         */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start 2-Wire master receive sequence.                                 */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start 2-Wire master transmit sequence.                                */
+  __I  uint32_t  RESERVED1[2];
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop 2-Wire transaction.                                              */
+  __I  uint32_t  RESERVED2;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend 2-Wire transaction.                                           */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume 2-Wire transaction.                                            */
+  __I  uint32_t  RESERVED3[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< Two-wire stopped.                                                     */
+  __IO uint32_t  EVENTS_RXDREADY;                   /*!< Two-wire ready to deliver new RXD byte received.                      */
+  __I  uint32_t  RESERVED4[4];
+  __IO uint32_t  EVENTS_TXDSENT;                    /*!< Two-wire finished sending last TXD byte.                              */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Two-wire error detected.                                              */
+  __I  uint32_t  RESERVED6[4];
+  __IO uint32_t  EVENTS_BB;                         /*!< Two-wire byte boundary.                                               */
+  __I  uint32_t  RESERVED7[3];
+  __IO uint32_t  EVENTS_SUSPENDED;                  /*!< Two-wire suspended.                                                   */
+  __I  uint32_t  RESERVED8[45];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for TWI.                                                    */
+  __I  uint32_t  RESERVED9[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED10[110];
+  __IO uint32_t  ERRORSRC;                          /*!< Two-wire error source. Write error field to 1 to clear error.         */
+  __I  uint32_t  RESERVED11[14];
+  __IO uint32_t  ENABLE;                            /*!< Enable two-wire master.                                               */
+  __I  uint32_t  RESERVED12;
+  __IO uint32_t  PSELSCL;                           /*!< Pin select for SCL.                                                   */
+  __IO uint32_t  PSELSDA;                           /*!< Pin select for SDA.                                                   */
+  __I  uint32_t  RESERVED13[2];
+  __I  uint32_t  RXD;                               /*!< RX data register.                                                     */
+  __IO uint32_t  TXD;                               /*!< TX data register.                                                     */
+  __I  uint32_t  RESERVED14;
+  __IO uint32_t  FREQUENCY;                         /*!< Two-wire frequency.                                                   */
+  __I  uint32_t  RESERVED15[24];
+  __IO uint32_t  ADDRESS;                           /*!< Address used in the two-wire transfer.                                */
+  __I  uint32_t  RESERVED16[668];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_TWI_Type;
+
+
+/* ================================================================================ */
+/* ================                      SPIS                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief SPI slave 1. (SPIS)
+  */
+
+typedef struct {                                    /*!< SPIS Structure                                                        */
+  __I  uint32_t  RESERVED0[9];
+  __O  uint32_t  TASKS_ACQUIRE;                     /*!< Acquire SPI semaphore.                                                */
+  __O  uint32_t  TASKS_RELEASE;                     /*!< Release SPI semaphore.                                                */
+  __I  uint32_t  RESERVED1[54];
+  __IO uint32_t  EVENTS_END;                        /*!< Granted transaction completed.                                        */
+  __I  uint32_t  RESERVED2[2];
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached                                             */
+  __I  uint32_t  RESERVED3[5];
+  __IO uint32_t  EVENTS_ACQUIRED;                   /*!< Semaphore acquired.                                                   */
+  __I  uint32_t  RESERVED4[53];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for SPIS.                                                   */
+  __I  uint32_t  RESERVED5[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED6[61];
+  __I  uint32_t  SEMSTAT;                           /*!< Semaphore status.                                                     */
+  __I  uint32_t  RESERVED7[15];
+  __IO uint32_t  STATUS;                            /*!< Status from last transaction.                                         */
+  __I  uint32_t  RESERVED8[47];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPIS.                                                          */
+  __I  uint32_t  RESERVED9;
+  __IO uint32_t  PSELSCK;                           /*!< Pin select for SCK.                                                   */
+  __IO uint32_t  PSELMISO;                          /*!< Pin select for MISO.                                                  */
+  __IO uint32_t  PSELMOSI;                          /*!< Pin select for MOSI.                                                  */
+  __IO uint32_t  PSELCSN;                           /*!< Pin select for CSN.                                                   */
+  __I  uint32_t  RESERVED10[7];
+  __IO uint32_t  RXDPTR;                            /*!< RX data pointer.                                                      */
+  __IO uint32_t  MAXRX;                             /*!< Maximum number of bytes in the receive buffer.                        */
+  __I  uint32_t  AMOUNTRX;                          /*!< Number of bytes received in last granted transaction.                 */
+  __I  uint32_t  RESERVED11;
+  __IO uint32_t  TXDPTR;                            /*!< TX data pointer.                                                      */
+  __IO uint32_t  MAXTX;                             /*!< Maximum number of bytes in the transmit buffer.                       */
+  __I  uint32_t  AMOUNTTX;                          /*!< Number of bytes transmitted in last granted transaction.              */
+  __I  uint32_t  RESERVED12;
+  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
+  __I  uint32_t  RESERVED13;
+  __IO uint32_t  DEF;                               /*!< Default character.                                                    */
+  __I  uint32_t  RESERVED14[24];
+  __IO uint32_t  ORC;                               /*!< Over-read character.                                                  */
+  __I  uint32_t  RESERVED15[654];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_SPIS_Type;
+
+
+/* ================================================================================ */
+/* ================                     GPIOTE                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief GPIO tasks and events. (GPIOTE)
+  */
+
+typedef struct {                                    /*!< GPIOTE Structure                                                      */
+  __O  uint32_t  TASKS_OUT[4];                      /*!< Tasks asssociated with GPIOTE channels.                               */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_IN[4];                      /*!< Tasks asssociated with GPIOTE channels.                               */
+  __I  uint32_t  RESERVED1[27];
+  __IO uint32_t  EVENTS_PORT;                       /*!< Event generated from multiple pins.                                   */
+  __I  uint32_t  RESERVED2[97];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[129];
+  __IO uint32_t  CONFIG[4];                         /*!< Channel configuration registers.                                      */
+  __I  uint32_t  RESERVED4[695];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_GPIOTE_Type;
+
+
+/* ================================================================================ */
+/* ================                       ADC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Analog to digital converter. (ADC)
+  */
+
+typedef struct {                                    /*!< ADC Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start an ADC conversion.                                              */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop ADC.                                                             */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_END;                        /*!< ADC conversion complete.                                              */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED2[61];
+  __I  uint32_t  BUSY;                              /*!< ADC busy register.                                                    */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  ENABLE;                            /*!< ADC enable.                                                           */
+  __IO uint32_t  CONFIG;                            /*!< ADC configuration register.                                           */
+  __I  uint32_t  RESULT;                            /*!< Result of ADC conversion.                                             */
+  __I  uint32_t  RESERVED4[700];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_ADC_Type;
+
+
+/* ================================================================================ */
+/* ================                      TIMER                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Timer 0. (TIMER)
+  */
+
+typedef struct {                                    /*!< TIMER Structure                                                       */
+  __O  uint32_t  TASKS_START;                       /*!< Start Timer.                                                          */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop Timer.                                                           */
+  __O  uint32_t  TASKS_COUNT;                       /*!< Increment Timer (In counter mode).                                    */
+  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear timer.                                                          */
+  __O  uint32_t  TASKS_SHUTDOWN;                    /*!< Shutdown timer.                                                       */
+  __I  uint32_t  RESERVED0[11];
+  __O  uint32_t  TASKS_CAPTURE[4];                  /*!< Capture Timer value to CC[n] registers.                               */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  EVENTS_COMPARE[4];                 /*!< Compare event on CC[n] match.                                         */
+  __I  uint32_t  RESERVED2[44];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for Timer.                                                  */
+  __I  uint32_t  RESERVED3[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED4[126];
+  __IO uint32_t  MODE;                              /*!< Timer Mode selection.                                                 */
+  __IO uint32_t  BITMODE;                           /*!< Sets timer behaviour.                                                 */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  PRESCALER;                         /*!< 4-bit prescaler to source clock frequency (max value 9). Source
+                                                         clock frequency is divided by 2^SCALE.                                */
+  __I  uint32_t  RESERVED6[11];
+  __IO uint32_t  CC[4];                             /*!< Capture/compare registers.                                            */
+  __I  uint32_t  RESERVED7[683];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_TIMER_Type;
+
+
+/* ================================================================================ */
+/* ================                       RTC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Real time counter 0. (RTC)
+  */
+
+typedef struct {                                    /*!< RTC Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start RTC Counter.                                                    */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop RTC Counter.                                                     */
+  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear RTC Counter.                                                    */
+  __O  uint32_t  TASKS_TRIGOVRFLW;                  /*!< Set COUNTER to 0xFFFFFFF0.                                            */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_TICK;                       /*!< Event on COUNTER increment.                                           */
+  __IO uint32_t  EVENTS_OVRFLW;                     /*!< Event on COUNTER overflow.                                            */
+  __I  uint32_t  RESERVED1[14];
+  __IO uint32_t  EVENTS_COMPARE[4];                 /*!< Compare event on CC[n] match.                                         */
+  __I  uint32_t  RESERVED2[109];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[13];
+  __IO uint32_t  EVTEN;                             /*!< Configures event enable routing to PPI for each RTC event.            */
+  __IO uint32_t  EVTENSET;                          /*!< Enable events routing to PPI. The reading of this register gives
+                                                         the value of EVTEN.                                                   */
+  __IO uint32_t  EVTENCLR;                          /*!< Disable events routing to PPI. The reading of this register
+                                                         gives the value of EVTEN.                                             */
+  __I  uint32_t  RESERVED4[110];
+  __I  uint32_t  COUNTER;                           /*!< Current COUNTER value.                                                */
+  __IO uint32_t  PRESCALER;                         /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
+                                                         Must be written when RTC is STOPed.                                   */
+  __I  uint32_t  RESERVED5[13];
+  __IO uint32_t  CC[4];                             /*!< Capture/compare registers.                                            */
+  __I  uint32_t  RESERVED6[683];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_RTC_Type;
+
+
+/* ================================================================================ */
+/* ================                      TEMP                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Temperature Sensor. (TEMP)
+  */
+
+typedef struct {                                    /*!< TEMP Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Start temperature measurement.                                        */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop temperature measurement.                                         */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_DATARDY;                    /*!< Temperature measurement complete, data ready event.                   */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED2[127];
+  __I  int32_t   TEMP;                              /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision.   */
+  __I  uint32_t  RESERVED3[700];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_TEMP_Type;
+
+
+/* ================================================================================ */
+/* ================                       RNG                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Random Number Generator. (RNG)
+  */
+
+typedef struct {                                    /*!< RNG Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start the random number generator.                                    */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop the random number generator.                                     */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_VALRDY;                     /*!< New random number generated and written to VALUE register.            */
+  __I  uint32_t  RESERVED1[63];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the RNG.                                                */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register                                         */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register                                       */
+  __I  uint32_t  RESERVED3[126];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
+  __I  uint32_t  VALUE;                             /*!< RNG random number.                                                    */
+  __I  uint32_t  RESERVED4[700];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_RNG_Type;
+
+
+/* ================================================================================ */
+/* ================                       ECB                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief AES ECB Mode Encryption. (ECB)
+  */
+
+typedef struct {                                    /*!< ECB Structure                                                         */
+  __O  uint32_t  TASKS_STARTECB;                    /*!< Start ECB block encrypt. If a crypto operation is running, this
+                                                         will not initiate a new encryption and the ERRORECB event will
+                                                          be triggered.                                                        */
+  __O  uint32_t  TASKS_STOPECB;                     /*!< Stop current ECB encryption. If a crypto operation is running,
+                                                         this will will trigger the ERRORECB event.                            */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_ENDECB;                     /*!< ECB block encrypt complete.                                           */
+  __IO uint32_t  EVENTS_ERRORECB;                   /*!< ECB block encrypt aborted due to a STOPECB task or due to an
+                                                         error.                                                                */
+  __I  uint32_t  RESERVED1[127];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  ECBDATAPTR;                        /*!< ECB block encrypt memory pointer.                                     */
+  __I  uint32_t  RESERVED3[701];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_ECB_Type;
+
+
+/* ================================================================================ */
+/* ================                       AAR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Accelerated Address Resolver. (AAR)
+  */
+
+typedef struct {                                    /*!< AAR Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start resolving addresses based on IRKs specified in the IRK
+                                                         data structure.                                                       */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop resolving addresses.                                             */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  EVENTS_END;                        /*!< Address resolution procedure completed.                               */
+  __IO uint32_t  EVENTS_RESOLVED;                   /*!< Address resolved.                                                     */
+  __IO uint32_t  EVENTS_NOTRESOLVED;                /*!< Address not resolved.                                                 */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  STATUS;                            /*!< Resolution status.                                                    */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable AAR.                                                           */
+  __IO uint32_t  NIRK;                              /*!< Number of Identity root Keys in the IRK data structure.               */
+  __IO uint32_t  IRKPTR;                            /*!< Pointer to the IRK data structure.                                    */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  ADDRPTR;                           /*!< Pointer to the resolvable address (6 bytes).                          */
+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to a scratch data area used for temporary storage during
+                                                         resolution. A minimum of 3 bytes must be reserved.                    */
+  __I  uint32_t  RESERVED6[697];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_AAR_Type;
+
+
+/* ================================================================================ */
+/* ================                       CCM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief AES CCM Mode Encryption. (CCM)
+  */
+
+typedef struct {                                    /*!< CCM Structure                                                         */
+  __O  uint32_t  TASKS_KSGEN;                       /*!< Start generation of key-stream. This operation will stop by
+                                                         itself when completed.                                                */
+  __O  uint32_t  TASKS_CRYPT;                       /*!< Start encrypt/decrypt. This operation will stop by itself when
+                                                         completed.                                                            */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop encrypt/decrypt.                                                 */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_ENDKSGEN;                   /*!< Keystream generation completed.                                       */
+  __IO uint32_t  EVENTS_ENDCRYPT;                   /*!< Encrypt/decrypt completed.                                            */
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Error happened.                                                       */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the CCM.                                                */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  MICSTATUS;                         /*!< CCM RX MIC check result.                                              */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< CCM enable.                                                           */
+  __IO uint32_t  MODE;                              /*!< Operation mode.                                                       */
+  __IO uint32_t  CNFPTR;                            /*!< Pointer to a data structure holding AES key and NONCE vector.         */
+  __IO uint32_t  INPTR;                             /*!< Pointer to the input packet.                                          */
+  __IO uint32_t  OUTPTR;                            /*!< Pointer to the output packet.                                         */
+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to a scratch data area used for temporary storage during
+                                                         resolution. A minimum of 43 bytes must be reserved.                   */
+  __I  uint32_t  RESERVED5[697];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_CCM_Type;
+
+
+/* ================================================================================ */
+/* ================                       WDT                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Watchdog Timer. (WDT)
+  */
+
+typedef struct {                                    /*!< WDT Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start the watchdog.                                                   */
+  __I  uint32_t  RESERVED0[63];
+  __IO uint32_t  EVENTS_TIMEOUT;                    /*!< Watchdog timeout.                                                     */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED2[61];
+  __I  uint32_t  RUNSTATUS;                         /*!< Watchdog running status.                                              */
+  __I  uint32_t  REQSTATUS;                         /*!< Request status.                                                       */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  CRV;                               /*!< Counter reload value in number of 32kiHz clock cycles.                */
+  __IO uint32_t  RREN;                              /*!< Reload request enable.                                                */
+  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
+  __I  uint32_t  RESERVED4[60];
+  __O  uint32_t  RR[8];                             /*!< Reload requests registers.                                            */
+  __I  uint32_t  RESERVED5[631];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_WDT_Type;
+
+
+/* ================================================================================ */
+/* ================                      QDEC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Rotary decoder. (QDEC)
+  */
+
+typedef struct {                                    /*!< QDEC Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Start the quadrature decoder.                                         */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop the quadrature decoder.                                          */
+  __O  uint32_t  TASKS_READCLRACC;                  /*!< Transfers the content from ACC registers to ACCREAD registers,
+                                                         and clears the ACC registers.                                         */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_SAMPLERDY;                  /*!< A new sample is written to the sample register.                       */
+  __IO uint32_t  EVENTS_REPORTRDY;                  /*!< REPORTPER number of samples accumulated in ACC register, and
+                                                         ACC register different than zero.                                     */
+  __IO uint32_t  EVENTS_ACCOF;                      /*!< ACC or ACCDBL register overflow.                                      */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the QDEC.                                               */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable the QDEC.                                                      */
+  __IO uint32_t  LEDPOL;                            /*!< LED output pin polarity.                                              */
+  __IO uint32_t  SAMPLEPER;                         /*!< Sample period.                                                        */
+  __I  int32_t   SAMPLE;                            /*!< Motion sample value.                                                  */
+  __IO uint32_t  REPORTPER;                         /*!< Number of samples to generate an EVENT_REPORTRDY.                     */
+  __I  int32_t   ACC;                               /*!< Accumulated valid transitions register.                               */
+  __I  int32_t   ACCREAD;                           /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
+                                                         task.                                                                 */
+  __IO uint32_t  PSELLED;                           /*!< Pin select for LED output.                                            */
+  __IO uint32_t  PSELA;                             /*!< Pin select for phase A input.                                         */
+  __IO uint32_t  PSELB;                             /*!< Pin select for phase B input.                                         */
+  __IO uint32_t  DBFEN;                             /*!< Enable debouncer input filters.                                       */
+  __I  uint32_t  RESERVED4[5];
+  __IO uint32_t  LEDPRE;                            /*!< Time LED is switched ON before the sample.                            */
+  __I  uint32_t  ACCDBL;                            /*!< Accumulated double (error) transitions register.                      */
+  __I  uint32_t  ACCDBLREAD;                        /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
+                                                         task.                                                                 */
+  __I  uint32_t  RESERVED5[684];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_QDEC_Type;
+
+
+/* ================================================================================ */
+/* ================                     LPCOMP                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Low power comparator. (LPCOMP)
+  */
+
+typedef struct {                                    /*!< LPCOMP Structure                                                      */
+  __O  uint32_t  TASKS_START;                       /*!< Start the comparator.                                                 */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop the comparator.                                                  */
+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Sample comparator value.                                              */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_READY;                      /*!< LPCOMP is ready and output is valid.                                  */
+  __IO uint32_t  EVENTS_DOWN;                       /*!< Input voltage crossed the threshold going down.                       */
+  __IO uint32_t  EVENTS_UP;                         /*!< Input voltage crossed the threshold going up.                         */
+  __IO uint32_t  EVENTS_CROSS;                      /*!< Input voltage crossed the threshold in any direction.                 */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the LPCOMP.                                             */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  RESULT;                            /*!< Result of last compare.                                               */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable the LPCOMP.                                                    */
+  __IO uint32_t  PSEL;                              /*!< Input pin select.                                                     */
+  __IO uint32_t  REFSEL;                            /*!< Reference select.                                                     */
+  __IO uint32_t  EXTREFSEL;                         /*!< External reference select.                                            */
+  __I  uint32_t  RESERVED5[4];
+  __IO uint32_t  ANADETECT;                         /*!< Analog detect configuration.                                          */
+  __I  uint32_t  RESERVED6[694];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_LPCOMP_Type;
+
+
+/* ================================================================================ */
+/* ================                       SWI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief SW Interrupts. (SWI)
+  */
+
+typedef struct {                                    /*!< SWI Structure                                                         */
+  __I  uint32_t  UNUSED;                            /*!< Unused.                                                               */
+} NRF_SWI_Type;
+
+
+/* ================================================================================ */
+/* ================                      NVMC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Non Volatile Memory Controller. (NVMC)
+  */
+
+typedef struct {                                    /*!< NVMC Structure                                                        */
+  __I  uint32_t  RESERVED0[256];
+  __I  uint32_t  READY;                             /*!< Ready flag.                                                           */
+  __I  uint32_t  RESERVED1[64];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
+  
+  union {
+    __IO uint32_t  ERASEPCR1;                       /*!< Register for erasing a non-protected non-volatile memory page.        */
+    __IO uint32_t  ERASEPAGE;                       /*!< Register for erasing a non-protected non-volatile memory page.        */
+  };
+  __IO uint32_t  ERASEALL;                          /*!< Register for erasing all non-volatile user memory.                    */
+  __IO uint32_t  ERASEPCR0;                         /*!< Register for erasing a protected non-volatile memory page.            */
+  __IO uint32_t  ERASEUICR;                         /*!< Register for start erasing User Information Congfiguration Registers. */
+} NRF_NVMC_Type;
+
+
+/* ================================================================================ */
+/* ================                       PPI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief PPI controller. (PPI)
+  */
+
+typedef struct {                                    /*!< PPI Structure                                                         */
+  PPI_TASKS_CHG_Type TASKS_CHG[4];                  /*!< Channel group tasks.                                                  */
+  __I  uint32_t  RESERVED0[312];
+  __IO uint32_t  CHEN;                              /*!< Channel enable.                                                       */
+  __IO uint32_t  CHENSET;                           /*!< Channel enable set.                                                   */
+  __IO uint32_t  CHENCLR;                           /*!< Channel enable clear.                                                 */
+  __I  uint32_t  RESERVED1;
+  PPI_CH_Type CH[16];                               /*!< PPI Channel.                                                          */
+  __I  uint32_t  RESERVED2[156];
+  __IO uint32_t  CHG[4];                            /*!< Channel group configuration.                                          */
+} NRF_PPI_Type;
+
+
+/* ================================================================================ */
+/* ================                      FICR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Factory Information Configuration. (FICR)
+  */
+
+typedef struct {                                    /*!< FICR Structure                                                        */
+  __I  uint32_t  RESERVED0[4];
+  __I  uint32_t  CODEPAGESIZE;                      /*!< Code memory page size in bytes.                                       */
+  __I  uint32_t  CODESIZE;                          /*!< Code memory size in pages.                                            */
+  __I  uint32_t  RESERVED1[4];
+  __I  uint32_t  CLENR0;                            /*!< Length of code region 0 in bytes.                                     */
+  __I  uint32_t  PPFC;                              /*!< Pre-programmed factory code present.                                  */
+  __I  uint32_t  RESERVED2;
+  __I  uint32_t  NUMRAMBLOCK;                       /*!< Number of individualy controllable RAM blocks.                        */
+  
+  union {
+    __I  uint32_t  SIZERAMBLOCK[4];                 /*!< Deprecated array of size of RAM block in bytes. This name is
+                                                         kept for backward compatinility purposes. Use SIZERAMBLOCKS
+                                                          instead.                                                             */
+    __I  uint32_t  SIZERAMBLOCKS;                   /*!< Size of RAM blocks in bytes.                                          */
+  };
+  __I  uint32_t  RESERVED3[5];
+  __I  uint32_t  CONFIGID;                          /*!< Configuration identifier.                                             */
+  __I  uint32_t  DEVICEID[2];                       /*!< Device identifier.                                                    */
+  __I  uint32_t  RESERVED4[6];
+  __I  uint32_t  ER[4];                             /*!< Encryption root.                                                      */
+  __I  uint32_t  IR[4];                             /*!< Identity root.                                                        */
+  __I  uint32_t  DEVICEADDRTYPE;                    /*!< Device address type.                                                  */
+  __I  uint32_t  DEVICEADDR[2];                     /*!< Device address.                                                       */
+  __I  uint32_t  OVERRIDEEN;                        /*!< Radio calibration override enable.                                    */
+  __I  uint32_t  NRF_1MBIT[5];                      /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
+                                                         mode.                                                                 */
+  __I  uint32_t  RESERVED5[10];
+  __I  uint32_t  BLE_1MBIT[5];                      /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
+                                                         mode.                                                                 */
+} NRF_FICR_Type;
+
+
+/* ================================================================================ */
+/* ================                      UICR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief User Information Configuration. (UICR)
+  */
+
+typedef struct {                                    /*!< UICR Structure                                                        */
+  __IO uint32_t  CLENR0;                            /*!< Length of code region 0.                                              */
+  __IO uint32_t  RBPCONF;                           /*!< Readback protection configuration.                                    */
+  __IO uint32_t  XTALFREQ;                          /*!< Reset value for CLOCK XTALFREQ register.                              */
+  __I  uint32_t  RESERVED0;
+  __I  uint32_t  FWID;                              /*!< Firmware ID.                                                          */
+  
+  union {
+    __IO uint32_t  NRFFW[15];                       /*!< Reserved for Nordic firmware design.                                  */
+    __IO uint32_t  BOOTLOADERADDR;                  /*!< Bootloader start address.                                             */
+  };
+  __IO uint32_t  NRFHW[12];                         /*!< Reserved for Nordic hardware design.                                  */
+  __IO uint32_t  CUSTOMER[32];                      /*!< Reserved for customer.                                                */
+} NRF_UICR_Type;
+
+
+/* ================================================================================ */
+/* ================                      GPIO                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief General purpose input and output. (GPIO)
+  */
+
+typedef struct {                                    /*!< GPIO Structure                                                        */
+  __I  uint32_t  RESERVED0[321];
+  __IO uint32_t  OUT;                               /*!< Write GPIO port.                                                      */
+  __IO uint32_t  OUTSET;                            /*!< Set individual bits in GPIO port.                                     */
+  __IO uint32_t  OUTCLR;                            /*!< Clear individual bits in GPIO port.                                   */
+  __I  uint32_t  IN;                                /*!< Read GPIO port.                                                       */
+  __IO uint32_t  DIR;                               /*!< Direction of GPIO pins.                                               */
+  __IO uint32_t  DIRSET;                            /*!< DIR set register.                                                     */
+  __IO uint32_t  DIRCLR;                            /*!< DIR clear register.                                                   */
+  __I  uint32_t  RESERVED1[120];
+  __IO uint32_t  PIN_CNF[32];                       /*!< Configuration of GPIO pins.                                           */
+} NRF_GPIO_Type;
+
+
+/* --------------------  End of section using anonymous unions  ------------------- */
+#if defined(__CC_ARM)
+  #pragma pop
+#elif defined(__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+  #pragma warning restore
+#else
+  #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================              Peripheral memory map             ================ */
+/* ================================================================================ */
+
+#define NRF_POWER_BASE                  0x40000000UL
+#define NRF_CLOCK_BASE                  0x40000000UL
+#define NRF_MPU_BASE                    0x40000000UL
+#define NRF_RADIO_BASE                  0x40001000UL
+#define NRF_UART0_BASE                  0x40002000UL
+#define NRF_SPI0_BASE                   0x40003000UL
+#define NRF_TWI0_BASE                   0x40003000UL
+#define NRF_SPI1_BASE                   0x40004000UL
+#define NRF_TWI1_BASE                   0x40004000UL
+#define NRF_SPIS1_BASE                  0x40004000UL
+#define NRF_GPIOTE_BASE                 0x40006000UL
+#define NRF_ADC_BASE                    0x40007000UL
+#define NRF_TIMER0_BASE                 0x40008000UL
+#define NRF_TIMER1_BASE                 0x40009000UL
+#define NRF_TIMER2_BASE                 0x4000A000UL
+#define NRF_RTC0_BASE                   0x4000B000UL
+#define NRF_TEMP_BASE                   0x4000C000UL
+#define NRF_RNG_BASE                    0x4000D000UL
+#define NRF_ECB_BASE                    0x4000E000UL
+#define NRF_AAR_BASE                    0x4000F000UL
+#define NRF_CCM_BASE                    0x4000F000UL
+#define NRF_WDT_BASE                    0x40010000UL
+#define NRF_RTC1_BASE                   0x40011000UL
+#define NRF_QDEC_BASE                   0x40012000UL
+#define NRF_LPCOMP_BASE                 0x40013000UL
+#define NRF_SWI_BASE                    0x40014000UL
+#define NRF_NVMC_BASE                   0x4001E000UL
+#define NRF_PPI_BASE                    0x4001F000UL
+#define NRF_FICR_BASE                   0x10000000UL
+#define NRF_UICR_BASE                   0x10001000UL
+#define NRF_GPIO_BASE                   0x50000000UL
+
+
+/* ================================================================================ */
+/* ================             Peripheral declaration             ================ */
+/* ================================================================================ */
+
+#define NRF_POWER                       ((NRF_POWER_Type          *) NRF_POWER_BASE)
+#define NRF_CLOCK                       ((NRF_CLOCK_Type          *) NRF_CLOCK_BASE)
+#define NRF_MPU                         ((NRF_MPU_Type            *) NRF_MPU_BASE)
+#define NRF_RADIO                       ((NRF_RADIO_Type          *) NRF_RADIO_BASE)
+#define NRF_UART0                       ((NRF_UART_Type           *) NRF_UART0_BASE)
+#define NRF_SPI0                        ((NRF_SPI_Type            *) NRF_SPI0_BASE)
+#define NRF_TWI0                        ((NRF_TWI_Type            *) NRF_TWI0_BASE)
+#define NRF_SPI1                        ((NRF_SPI_Type            *) NRF_SPI1_BASE)
+#define NRF_TWI1                        ((NRF_TWI_Type            *) NRF_TWI1_BASE)
+#define NRF_SPIS1                       ((NRF_SPIS_Type           *) NRF_SPIS1_BASE)
+#define NRF_GPIOTE                      ((NRF_GPIOTE_Type         *) NRF_GPIOTE_BASE)
+#define NRF_ADC                         ((NRF_ADC_Type            *) NRF_ADC_BASE)
+#define NRF_TIMER0                      ((NRF_TIMER_Type          *) NRF_TIMER0_BASE)
+#define NRF_TIMER1                      ((NRF_TIMER_Type          *) NRF_TIMER1_BASE)
+#define NRF_TIMER2                      ((NRF_TIMER_Type          *) NRF_TIMER2_BASE)
+#define NRF_RTC0                        ((NRF_RTC_Type            *) NRF_RTC0_BASE)
+#define NRF_TEMP                        ((NRF_TEMP_Type           *) NRF_TEMP_BASE)
+#define NRF_RNG                         ((NRF_RNG_Type            *) NRF_RNG_BASE)
+#define NRF_ECB                         ((NRF_ECB_Type            *) NRF_ECB_BASE)
+#define NRF_AAR                         ((NRF_AAR_Type            *) NRF_AAR_BASE)
+#define NRF_CCM                         ((NRF_CCM_Type            *) NRF_CCM_BASE)
+#define NRF_WDT                         ((NRF_WDT_Type            *) NRF_WDT_BASE)
+#define NRF_RTC1                        ((NRF_RTC_Type            *) NRF_RTC1_BASE)
+#define NRF_QDEC                        ((NRF_QDEC_Type           *) NRF_QDEC_BASE)
+#define NRF_LPCOMP                      ((NRF_LPCOMP_Type         *) NRF_LPCOMP_BASE)
+#define NRF_SWI                         ((NRF_SWI_Type            *) NRF_SWI_BASE)
+#define NRF_NVMC                        ((NRF_NVMC_Type           *) NRF_NVMC_BASE)
+#define NRF_PPI                         ((NRF_PPI_Type            *) NRF_PPI_BASE)
+#define NRF_FICR                        ((NRF_FICR_Type           *) NRF_FICR_BASE)
+#define NRF_UICR                        ((NRF_UICR_Type           *) NRF_UICR_BASE)
+#define NRF_GPIO                        ((NRF_GPIO_Type           *) NRF_GPIO_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group nrf51 */
+/** @} */ /* End of group Nordic Semiconductor */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif  /* nrf51_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51422_peripherals.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,152 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+#ifndef _NRF51422_PERIPHERALS_H
+#define _NRF51422_PERIPHERALS_H
+
+
+/* Software Interrupts */
+#define SWI_PRESENT
+#define SWI_COUNT 6
+
+/* GPIO */
+#define GPIO_PRESENT
+#define GPIO_COUNT 1
+
+#define P0_PIN_NUM 32
+
+/* MPU and BPROT */
+#define BPROT_PRESENT
+
+#define BPROT_REGIONS_SIZE 4096
+#define BPROT_REGIONS_NUM 64
+
+/* Radio */
+#define RADIO_PRESENT
+#define RADIO_COUNT 1
+
+/* Accelerated Address Resolver */
+#define AAR_PRESENT
+#define AAR_COUNT 1
+
+#define AAR_MAX_IRK_NUM 8
+
+/* AES Electronic CodeBook mode encryption */
+#define ECB_PRESENT
+#define ECB_COUNT 1
+
+/* AES CCM mode encryption */
+#define CCM_PRESENT
+#define CCM_COUNT 1
+
+/* Peripheral to Peripheral Interconnect */
+#define PPI_PRESENT
+#define PPI_COUNT 1
+
+#define PPI_CH_NUM 16
+#define PPI_GROUP_NUM 4
+
+/* Timer/Counter */
+#define TIMER_PRESENT
+#define TIMER_COUNT 3
+
+#define TIMER0_MAX_SIZE 32
+#define TIMER1_MAX_SIZE 16
+#define TIMER2_MAX_SIZE 16
+
+#define TIMER0_CC_NUM 4
+#define TIMER1_CC_NUM 4
+#define TIMER2_CC_NUM 4
+
+/* Real Time Counter */
+#define RTC_PRESENT
+#define RTC_COUNT 2
+
+#define RTC0_CC_NUM 3
+#define RTC1_CC_NUM 4
+
+/* RNG */
+#define RNG_PRESENT
+#define RNG_COUNT 1
+
+/* Watchdog Timer */
+#define WDT_PRESENT
+#define WDT_COUNT 1
+
+/* Temperature Sensor */
+#define TEMP_PRESENT
+#define TEMP_COUNT 1
+
+/* Serial Peripheral Interface Master */
+#define SPI_PRESENT
+#define SPI_COUNT 2
+
+/* Serial Peripheral Interface Slave with DMA */
+#define SPIS_PRESENT
+#define SPIS_COUNT 1
+
+/* Two Wire Interface Master */
+#define TWI_PRESENT
+#define TWI_COUNT 2
+
+/* Universal Asynchronous Receiver-Transmitter */
+#define UART_PRESENT
+#define UART_COUNT 1
+
+/* Quadrature Decoder */
+#define QDEC_PRESENT
+#define QDEC_COUNT 1
+
+/* Analog to Digital Converter */
+#define ADC_PRESENT
+#define ADC_COUNT 1
+
+/* GPIO Tasks and Events */
+#define GPIOTE_PRESENT
+#define GPIOTE_COUNT 1
+
+#define GPIOTE_CH_NUM 4
+
+/* Low Power Comparator */
+#define LPCOMP_PRESENT
+#define LPCOMP_COUNT 1
+
+#define LPCOMP_REFSEL_RESOLUTION 8
+
+
+#endif      // _NRF51422_PERIPHERALS_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51802_peripherals.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,152 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+#ifndef _NRF51802_PERIPHERALS_H
+#define _NRF51802_PERIPHERALS_H
+
+
+/* Software Interrupts */
+#define SWI_PRESENT
+#define SWI_COUNT 6
+
+/* GPIO */
+#define GPIO_PRESENT
+#define GPIO_COUNT 1
+
+#define P0_PIN_NUM 32
+
+/* MPU and BPROT */
+#define BPROT_PRESENT
+
+#define BPROT_REGIONS_SIZE 4096
+#define BPROT_REGIONS_NUM 64
+
+/* Radio */
+#define RADIO_PRESENT
+#define RADIO_COUNT 1
+
+/* Accelerated Address Resolver */
+#define AAR_PRESENT
+#define AAR_COUNT 1
+
+#define AAR_MAX_IRK_NUM 8
+
+/* AES Electronic CodeBook mode encryption */
+#define ECB_PRESENT
+#define ECB_COUNT 1
+
+/* AES CCM mode encryption */
+#define CCM_PRESENT
+#define CCM_COUNT 1
+
+/* Peripheral to Peripheral Interconnect */
+#define PPI_PRESENT
+#define PPI_COUNT 1
+
+#define PPI_CH_NUM 16
+#define PPI_GROUP_NUM 4
+
+/* Timer/Counter */
+#define TIMER_PRESENT
+#define TIMER_COUNT 3
+
+#define TIMER0_MAX_SIZE 32
+#define TIMER1_MAX_SIZE 16
+#define TIMER2_MAX_SIZE 16
+
+#define TIMER0_CC_NUM 4
+#define TIMER1_CC_NUM 4
+#define TIMER2_CC_NUM 4
+
+/* Real Time Counter */
+#define RTC_PRESENT
+#define RTC_COUNT 2
+
+#define RTC0_CC_NUM 3
+#define RTC1_CC_NUM 4
+
+/* RNG */
+#define RNG_PRESENT
+#define RNG_COUNT 1
+
+/* Watchdog Timer */
+#define WDT_PRESENT
+#define WDT_COUNT 1
+
+/* Temperature Sensor */
+#define TEMP_PRESENT
+#define TEMP_COUNT 1
+
+/* Serial Peripheral Interface Master */
+#define SPI_PRESENT
+#define SPI_COUNT 2
+
+/* Serial Peripheral Interface Slave with DMA */
+#define SPIS_PRESENT
+#define SPIS_COUNT 1
+
+/* Two Wire Interface Master */
+#define TWI_PRESENT
+#define TWI_COUNT 2
+
+/* Universal Asynchronous Receiver-Transmitter */
+#define UART_PRESENT
+#define UART_COUNT 1
+
+/* Quadrature Decoder */
+#define QDEC_PRESENT
+#define QDEC_COUNT 1
+
+/* Analog to Digital Converter */
+#define ADC_PRESENT
+#define ADC_COUNT 1
+
+/* GPIO Tasks and Events */
+#define GPIOTE_PRESENT
+#define GPIOTE_COUNT 1
+
+#define GPIOTE_CH_NUM 4
+
+/* Low Power Comparator */
+#define LPCOMP_PRESENT
+#define LPCOMP_COUNT 1
+
+#define LPCOMP_REFSEL_RESOLUTION 8
+
+
+#endif      // _NRF51802_PERIPHERALS_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51822_peripherals.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,152 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+#ifndef _NRF51822_PERIPHERALS_H
+#define _NRF51822_PERIPHERALS_H
+
+
+/* Software Interrupts */
+#define SWI_PRESENT
+#define SWI_COUNT 6
+
+/* GPIO */
+#define GPIO_PRESENT
+#define GPIO_COUNT 1
+
+#define P0_PIN_NUM 32
+
+/* MPU and BPROT */
+#define BPROT_PRESENT
+
+#define BPROT_REGIONS_SIZE 4096
+#define BPROT_REGIONS_NUM 64
+
+/* Radio */
+#define RADIO_PRESENT
+#define RADIO_COUNT 1
+
+/* Accelerated Address Resolver */
+#define AAR_PRESENT
+#define AAR_COUNT 1
+
+#define AAR_MAX_IRK_NUM 8
+
+/* AES Electronic CodeBook mode encryption */
+#define ECB_PRESENT
+#define ECB_COUNT 1
+
+/* AES CCM mode encryption */
+#define CCM_PRESENT
+#define CCM_COUNT 1
+
+/* Peripheral to Peripheral Interconnect */
+#define PPI_PRESENT
+#define PPI_COUNT 1
+
+#define PPI_CH_NUM 16
+#define PPI_GROUP_NUM 4
+
+/* Timer/Counter */
+#define TIMER_PRESENT
+#define TIMER_COUNT 3
+
+#define TIMER0_MAX_SIZE 32
+#define TIMER1_MAX_SIZE 16
+#define TIMER2_MAX_SIZE 16
+
+#define TIMER0_CC_NUM 4
+#define TIMER1_CC_NUM 4
+#define TIMER2_CC_NUM 4
+
+/* Real Time Counter */
+#define RTC_PRESENT
+#define RTC_COUNT 2
+
+#define RTC0_CC_NUM 3
+#define RTC1_CC_NUM 4
+
+/* RNG */
+#define RNG_PRESENT
+#define RNG_COUNT 1
+
+/* Watchdog Timer */
+#define WDT_PRESENT
+#define WDT_COUNT 1
+
+/* Temperature Sensor */
+#define TEMP_PRESENT
+#define TEMP_COUNT 1
+
+/* Serial Peripheral Interface Master */
+#define SPI_PRESENT
+#define SPI_COUNT 2
+
+/* Serial Peripheral Interface Slave with DMA */
+#define SPIS_PRESENT
+#define SPIS_COUNT 1
+
+/* Two Wire Interface Master */
+#define TWI_PRESENT
+#define TWI_COUNT 2
+
+/* Universal Asynchronous Receiver-Transmitter */
+#define UART_PRESENT
+#define UART_COUNT 1
+
+/* Quadrature Decoder */
+#define QDEC_PRESENT
+#define QDEC_COUNT 1
+
+/* Analog to Digital Converter */
+#define ADC_PRESENT
+#define ADC_COUNT 1
+
+/* GPIO Tasks and Events */
+#define GPIOTE_PRESENT
+#define GPIOTE_COUNT 1
+
+#define GPIOTE_CH_NUM 4
+
+/* Low Power Comparator */
+#define LPCOMP_PRESENT
+#define LPCOMP_COUNT 1
+
+#define LPCOMP_REFSEL_RESOLUTION 8
+
+
+#endif      // _NRF51822_PERIPHERALS_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51_bitfields.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,6137 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+#ifndef __NRF51_BITS_H
+#define __NRF51_BITS_H
+
+/*lint ++flb "Enter library region" */
+
+/* Peripheral: AAR */
+/* Description: Accelerated Address Resolver. */
+
+/* Register: AAR_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
+#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on RESOLVED event. */
+#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on END event. */
+#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: AAR_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
+#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on RESOLVED event. */
+#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on ENDKSGEN event. */
+#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: AAR_STATUS */
+/* Description: Resolution status. */
+
+/* Bits 3..0 : The IRK used last time an address was resolved. */
+#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+
+/* Register: AAR_ENABLE */
+/* Description: Enable AAR. */
+
+/* Bits 1..0 : Enable AAR. */
+#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
+#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
+
+/* Register: AAR_NIRK */
+/* Description: Number of Identity root Keys in the IRK data structure. */
+
+/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
+#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
+#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
+
+/* Register: AAR_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: ADC */
+/* Description: Analog to digital converter. */
+
+/* Register: ADC_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 0 : Enable interrupt on END event. */
+#define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */
+#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: ADC_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 0 : Disable interrupt on END event. */
+#define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
+#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: ADC_BUSY */
+/* Description: ADC busy register. */
+
+/* Bit 0 : ADC busy register. */
+#define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */
+#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */
+#define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */
+#define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */
+
+/* Register: ADC_ENABLE */
+/* Description: ADC enable. */
+
+/* Bits 1..0 : ADC enable. */
+#define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
+#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */
+
+/* Register: ADC_CONFIG */
+/* Description: ADC configuration register. */
+
+/* Bits 17..16 : ADC external reference pin selection. */
+#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */
+#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
+#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */
+#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
+
+/* Bits 15..8 : ADC analog pin selection. */
+#define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
+#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
+#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */
+
+/* Bits 6..5 : ADC reference selection. */
+#define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */
+#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */
+#define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */
+#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */
+#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */
+
+/* Bits 4..2 : ADC input selection. */
+#define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
+#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */
+#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */
+#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */
+#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */
+#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */
+#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */
+
+/* Bits 1..0 : ADC resolution. */
+#define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */
+#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */
+#define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */
+#define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */
+#define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */
+
+/* Register: ADC_RESULT */
+/* Description: Result of ADC conversion. */
+
+/* Bits 9..0 : Result of ADC conversion. */
+#define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+
+/* Register: ADC_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: CCM */
+/* Description: AES CCM Mode Encryption. */
+
+/* Register: CCM_SHORTS */
+/* Description: Shortcuts for the CCM. */
+
+/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: CCM_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on ERROR event. */
+#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on ENDCRYPT event. */
+#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on ENDKSGEN event. */
+#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: CCM_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on ERROR event. */
+#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on ENDCRYPT event. */
+#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on ENDKSGEN event. */
+#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: CCM_MICSTATUS */
+/* Description: CCM RX MIC check result. */
+
+/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
+#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */
+#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */
+
+/* Register: CCM_ENABLE */
+/* Description: CCM enable. */
+
+/* Bits 1..0 : CCM enable. */
+#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
+#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
+
+/* Register: CCM_MODE */
+/* Description: Operation mode. */
+
+/* Bit 0 : CCM mode operation. */
+#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */
+#define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */
+
+/* Register: CCM_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: CLOCK */
+/* Description: Clock control. */
+
+/* Register: CLOCK_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 4 : Enable interrupt on CTTO event. */
+#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 3 : Enable interrupt on DONE event. */
+#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: CLOCK_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 4 : Disable interrupt on CTTO event. */
+#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 3 : Disable interrupt on DONE event. */
+#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: CLOCK_HFCLKRUN */
+/* Description: Task HFCLKSTART trigger status. */
+
+/* Bit 0 : Task HFCLKSTART trigger status. */
+#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */
+#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */
+
+/* Register: CLOCK_HFCLKSTAT */
+/* Description: High frequency clock status. */
+
+/* Bit 16 : State for the HFCLK. */
+#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */
+#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */
+
+/* Bit 0 : Active clock source for the HF clock. */
+#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */
+#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */
+
+/* Register: CLOCK_LFCLKRUN */
+/* Description: Task LFCLKSTART triggered status. */
+
+/* Bit 0 : Task LFCLKSTART triggered status. */
+#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */
+#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */
+
+/* Register: CLOCK_LFCLKSTAT */
+/* Description: Low frequency clock status. */
+
+/* Bit 16 : State for the LF clock. */
+#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */
+#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */
+
+/* Bits 1..0 : Active clock source for the LF clock. */
+#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */
+#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */
+#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */
+
+/* Register: CLOCK_LFCLKSRCCOPY */
+/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
+
+/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
+
+/* Register: CLOCK_LFCLKSRC */
+/* Description: Clock source for the LFCLK clock. */
+
+/* Bits 1..0 : Clock source. */
+#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
+#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
+#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
+
+/* Register: CLOCK_CTIV */
+/* Description: Calibration timer interval. */
+
+/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
+#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
+#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
+
+/* Register: CLOCK_XTALFREQ */
+/* Description: Crystal frequency. */
+
+/* Bits 7..0 : External Xtal frequency selection. */
+#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
+#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
+#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */
+#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */
+
+
+/* Peripheral: ECB */
+/* Description: AES ECB Mode Encryption. */
+
+/* Register: ECB_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 1 : Enable interrupt on ERRORECB event. */
+#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
+#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
+#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on ENDECB event. */
+#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
+#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
+#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: ECB_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 1 : Disable interrupt on ERRORECB event. */
+#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
+#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
+#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on ENDECB event. */
+#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
+#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
+#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: ECB_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: FICR */
+/* Description: Factory Information Configuration. */
+
+/* Register: FICR_PPFC */
+/* Description: Pre-programmed factory code present. */
+
+/* Bits 7..0 : Pre-programmed factory code present. */
+#define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
+#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
+#define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
+#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
+
+/* Register: FICR_CONFIGID */
+/* Description: Configuration identifier. */
+
+/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
+#define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
+#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
+
+/* Bits 15..0 : Hardware Identification Number. */
+#define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
+#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
+
+/* Register: FICR_DEVICEADDRTYPE */
+/* Description: Device address type. */
+
+/* Bit 0 : Device address type. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */
+
+/* Register: FICR_OVERRIDEEN */
+/* Description: Radio calibration override enable. */
+
+/* Bit 3 : Override default values for BLE_1Mbit mode. */
+#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */
+#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */
+#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */
+#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */
+
+/* Bit 0 : Override default values for NRF_1Mbit mode. */
+#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */
+#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */
+#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */
+#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */
+
+
+/* Peripheral: GPIO */
+/* Description: General purpose input and output. */
+
+/* Register: GPIO_OUT */
+/* Description: Write GPIO port. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */
+
+/* Register: GPIO_OUTSET */
+/* Description: Set individual bits in GPIO port. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */
+
+/* Register: GPIO_OUTCLR */
+/* Description: Clear individual bits in GPIO port. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */
+
+/* Register: GPIO_IN */
+/* Description: Read GPIO port. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */
+
+/* Register: GPIO_DIR */
+/* Description: Direction of GPIO pins. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */
+
+/* Register: GPIO_DIRSET */
+/* Description: DIR set register. */
+
+/* Bit 31 : Set as output pin 31. */
+#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 30 : Set as output pin 30. */
+#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 29 : Set as output pin 29. */
+#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 28 : Set as output pin 28. */
+#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 27 : Set as output pin 27. */
+#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 26 : Set as output pin 26. */
+#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 25 : Set as output pin 25. */
+#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 24 : Set as output pin 24. */
+#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 23 : Set as output pin 23. */
+#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 22 : Set as output pin 22. */
+#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 21 : Set as output pin 21. */
+#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 20 : Set as output pin 20. */
+#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 19 : Set as output pin 19. */
+#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 18 : Set as output pin 18. */
+#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 17 : Set as output pin 17. */
+#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 16 : Set as output pin 16. */
+#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 15 : Set as output pin 15. */
+#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 14 : Set as output pin 14. */
+#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 13 : Set as output pin 13. */
+#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 12 : Set as output pin 12. */
+#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 11 : Set as output pin 11. */
+#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 10 : Set as output pin 10. */
+#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 9 : Set as output pin 9. */
+#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 8 : Set as output pin 8. */
+#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 7 : Set as output pin 7. */
+#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 6 : Set as output pin 6. */
+#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 5 : Set as output pin 5. */
+#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 4 : Set as output pin 4. */
+#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 3 : Set as output pin 3. */
+#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 2 : Set as output pin 2. */
+#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 1 : Set as output pin 1. */
+#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 0 : Set as output pin 0. */
+#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */
+
+/* Register: GPIO_DIRCLR */
+/* Description: DIR clear register. */
+
+/* Bit 31 : Set as input pin 31. */
+#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 30 : Set as input pin 30. */
+#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 29 : Set as input pin 29. */
+#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 28 : Set as input pin 28. */
+#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 27 : Set as input pin 27. */
+#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 26 : Set as input pin 26. */
+#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 25 : Set as input pin 25. */
+#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 24 : Set as input pin 24. */
+#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 23 : Set as input pin 23. */
+#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 22 : Set as input pin 22. */
+#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 21 : Set as input pin 21. */
+#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 20 : Set as input pin 20. */
+#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 19 : Set as input pin 19. */
+#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 18 : Set as input pin 18. */
+#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 17 : Set as input pin 17. */
+#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 16 : Set as input pin 16. */
+#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 15 : Set as input pin 15. */
+#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 14 : Set as input pin 14. */
+#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 13 : Set as input pin 13. */
+#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 12 : Set as input pin 12. */
+#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 11 : Set as input pin 11. */
+#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 10 : Set as input pin 10. */
+#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 9 : Set as input pin 9. */
+#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 8 : Set as input pin 8. */
+#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 7 : Set as input pin 7. */
+#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 6 : Set as input pin 6. */
+#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 5 : Set as input pin 5. */
+#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 4 : Set as input pin 4. */
+#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 3 : Set as input pin 3. */
+#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 2 : Set as input pin 2. */
+#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 1 : Set as input pin 1. */
+#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 0 : Set as input pin 0. */
+#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */
+
+/* Register: GPIO_PIN_CNF */
+/* Description: Configuration of GPIO pins. */
+
+/* Bits 17..16 : Pin sensing mechanism. */
+#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
+#define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
+#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
+
+/* Bits 10..8 : Drive configuration. */
+#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */
+#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */
+#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */
+#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */
+#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */
+#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */
+#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */
+#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */
+
+/* Bits 3..2 : Pull-up or -down configuration. */
+#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
+#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
+#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */
+#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
+#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
+
+/* Bit 1 : Connect or disconnect input path. */
+#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */
+#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */
+
+/* Bit 0 : Pin direction. */
+#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
+#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
+#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */
+#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */
+
+
+/* Peripheral: GPIOTE */
+/* Description: GPIO tasks and events. */
+
+/* Register: GPIOTE_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 31 : Enable interrupt on PORT event. */
+#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 3 : Enable interrupt on IN[3] event. */
+#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on IN[2] event. */
+#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on IN[1] event. */
+#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on IN[0] event. */
+#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: GPIOTE_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 31 : Disable interrupt on PORT event. */
+#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 3 : Disable interrupt on IN[3] event. */
+#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on IN[2] event. */
+#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on IN[1] event. */
+#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on IN[0] event. */
+#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: GPIOTE_CONFIG */
+/* Description: Channel configuration registers. */
+
+/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
+#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */
+#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */
+
+/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
+#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /*!< No task or event. */
+#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
+#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
+#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
+
+/* Bits 12..8 : Pin select. */
+#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
+#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
+
+/* Bits 1..0 : Mode */
+#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
+#define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
+#define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
+
+/* Register: GPIOTE_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: LPCOMP */
+/* Description: Low power comparator. */
+
+/* Register: LPCOMP_SHORTS */
+/* Description: Shortcuts for the LPCOMP. */
+
+/* Bit 4 : Shortcut between CROSS event and STOP task. */
+#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 3 : Shortcut between UP event and STOP task. */
+#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 2 : Shortcut between DOWN event and STOP task. */
+#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 1 : Shortcut between RADY event and STOP task. */
+#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between READY event and SAMPLE task. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: LPCOMP_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 3 : Enable interrupt on CROSS event. */
+#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on UP event. */
+#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on DOWN event. */
+#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on READY event. */
+#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: LPCOMP_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 3 : Disable interrupt on CROSS event. */
+#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on UP event. */
+#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on DOWN event. */
+#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on READY event. */
+#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: LPCOMP_RESULT */
+/* Description: Result of last compare. */
+
+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
+#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is bellow the reference threshold. */
+#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
+
+/* Register: LPCOMP_ENABLE */
+/* Description: Enable the LPCOMP. */
+
+/* Bits 1..0 : Enable or disable LPCOMP. */
+#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
+#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
+
+/* Register: LPCOMP_PSEL */
+/* Description: Input pin select. */
+
+/* Bits 2..0 : Analog input pin select. */
+#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
+#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
+
+/* Register: LPCOMP_REFSEL */
+/* Description: Reference select. */
+
+/* Bits 2..0 : Reference select. */
+#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */
+
+/* Register: LPCOMP_EXTREFSEL */
+/* Description: External reference select. */
+
+/* Bit 0 : External analog reference pin selection. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
+
+/* Register: LPCOMP_ANADETECT */
+/* Description: Analog detect configuration. */
+
+/* Bits 1..0 : Analog detect configuration. */
+#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */
+#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
+#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
+
+/* Register: LPCOMP_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: MPU */
+/* Description: Memory Protection Unit. */
+
+/* Register: MPU_PERR0 */
+/* Description: Configuration of peripherals in mpu regions. */
+
+/* Bit 31 : PPI region configuration. */
+#define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
+#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
+#define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 30 : NVMC region configuration. */
+#define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */
+#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */
+#define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 19 : LPCOMP region configuration. */
+#define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */
+#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
+#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 18 : QDEC region configuration. */
+#define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */
+#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */
+#define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 17 : RTC1 region configuration. */
+#define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */
+#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */
+#define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 16 : WDT region configuration. */
+#define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */
+#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */
+#define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 15 : CCM and AAR region configuration. */
+#define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */
+#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */
+#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 14 : ECB region configuration. */
+#define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */
+#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */
+#define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 13 : RNG region configuration. */
+#define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */
+#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */
+#define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 12 : TEMP region configuration. */
+#define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */
+#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */
+#define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 11 : RTC0 region configuration. */
+#define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */
+#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */
+#define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 10 : TIMER2 region configuration. */
+#define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */
+#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */
+#define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 9 : TIMER1 region configuration. */
+#define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */
+#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */
+#define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 8 : TIMER0 region configuration. */
+#define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */
+#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */
+#define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 7 : ADC region configuration. */
+#define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */
+#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */
+#define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 6 : GPIOTE region configuration. */
+#define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */
+#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */
+#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 4 : SPI1 and TWI1 region configuration. */
+#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */
+#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */
+#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 3 : SPI0 and TWI0 region configuration. */
+#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */
+#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */
+#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 2 : UART0 region configuration. */
+#define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
+#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */
+#define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 1 : RADIO region configuration. */
+#define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */
+#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */
+#define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 0 : POWER_CLOCK region configuration. */
+#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */
+#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */
+#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Register: MPU_PROTENSET0 */
+/* Description: Erase and write protection bit enable set register. */
+
+/* Bit 31 : Protection enable for region 31. */
+#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */
+#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */
+#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 30 : Protection enable for region 30. */
+#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */
+#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */
+#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 29 : Protection enable for region 29. */
+#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */
+#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */
+#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 28 : Protection enable for region 28. */
+#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */
+#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */
+#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 27 : Protection enable for region 27. */
+#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */
+#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */
+#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 26 : Protection enable for region 26. */
+#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */
+#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */
+#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 25 : Protection enable for region 25. */
+#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */
+#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */
+#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 24 : Protection enable for region 24. */
+#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */
+#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */
+#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 23 : Protection enable for region 23. */
+#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */
+#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */
+#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 22 : Protection enable for region 22. */
+#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */
+#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */
+#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 21 : Protection enable for region 21. */
+#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */
+#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */
+#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 20 : Protection enable for region 20. */
+#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */
+#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */
+#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 19 : Protection enable for region 19. */
+#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */
+#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */
+#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 18 : Protection enable for region 18. */
+#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */
+#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */
+#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 17 : Protection enable for region 17. */
+#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */
+#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */
+#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 16 : Protection enable for region 16. */
+#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */
+#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */
+#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 15 : Protection enable for region 15. */
+#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */
+#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */
+#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 14 : Protection enable for region 14. */
+#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */
+#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */
+#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 13 : Protection enable for region 13. */
+#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */
+#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */
+#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 12 : Protection enable for region 12. */
+#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */
+#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */
+#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 11 : Protection enable for region 11. */
+#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */
+#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */
+#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 10 : Protection enable for region 10. */
+#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */
+#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */
+#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 9 : Protection enable for region 9. */
+#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */
+#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */
+#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 8 : Protection enable for region 8. */
+#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */
+#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */
+#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 7 : Protection enable for region 7. */
+#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */
+#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */
+#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 6 : Protection enable for region 6. */
+#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */
+#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */
+#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 5 : Protection enable for region 5. */
+#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */
+#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */
+#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 4 : Protection enable for region 4. */
+#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */
+#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */
+#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 3 : Protection enable for region 3. */
+#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */
+#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */
+#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 2 : Protection enable for region 2. */
+#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */
+#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */
+#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 1 : Protection enable for region 1. */
+#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */
+#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */
+#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 0 : Protection enable for region 0. */
+#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */
+#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */
+#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
+
+/* Register: MPU_PROTENSET1 */
+/* Description: Erase and write protection bit enable set register. */
+
+/* Bit 31 : Protection enable for region 63. */
+#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */
+#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */
+#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 30 : Protection enable for region 62. */
+#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */
+#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */
+#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 29 : Protection enable for region 61. */
+#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */
+#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */
+#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 28 : Protection enable for region 60. */
+#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */
+#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */
+#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 27 : Protection enable for region 59. */
+#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */
+#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */
+#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 26 : Protection enable for region 58. */
+#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */
+#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */
+#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 25 : Protection enable for region 57. */
+#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */
+#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */
+#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 24 : Protection enable for region 56. */
+#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */
+#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */
+#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 23 : Protection enable for region 55. */
+#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */
+#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */
+#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 22 : Protection enable for region 54. */
+#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */
+#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */
+#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 21 : Protection enable for region 53. */
+#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */
+#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */
+#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 20 : Protection enable for region 52. */
+#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */
+#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */
+#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 19 : Protection enable for region 51. */
+#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */
+#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */
+#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 18 : Protection enable for region 50. */
+#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */
+#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */
+#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 17 : Protection enable for region 49. */
+#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */
+#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */
+#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 16 : Protection enable for region 48. */
+#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */
+#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */
+#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 15 : Protection enable for region 47. */
+#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */
+#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */
+#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 14 : Protection enable for region 46. */
+#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */
+#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */
+#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 13 : Protection enable for region 45. */
+#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */
+#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */
+#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 12 : Protection enable for region 44. */
+#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */
+#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */
+#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 11 : Protection enable for region 43. */
+#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */
+#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */
+#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 10 : Protection enable for region 42. */
+#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */
+#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */
+#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 9 : Protection enable for region 41. */
+#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */
+#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */
+#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 8 : Protection enable for region 40. */
+#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */
+#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */
+#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 7 : Protection enable for region 39. */
+#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */
+#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */
+#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 6 : Protection enable for region 38. */
+#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */
+#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */
+#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 5 : Protection enable for region 37. */
+#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */
+#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */
+#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 4 : Protection enable for region 36. */
+#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */
+#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */
+#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 3 : Protection enable for region 35. */
+#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */
+#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */
+#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 2 : Protection enable for region 34. */
+#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */
+#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */
+#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 1 : Protection enable for region 33. */
+#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */
+#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */
+#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 0 : Protection enable for region 32. */
+#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */
+#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */
+#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
+
+/* Register: MPU_DISABLEINDEBUG */
+/* Description: Disable erase and write protection mechanism in debug mode. */
+
+/* Bit 0 : Disable protection mechanism in debug mode. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */
+
+/* Register: MPU_PROTBLOCKSIZE */
+/* Description: Erase and write protection block size. */
+
+/* Bits 1..0 : Erase and write protection block size. */
+#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */
+#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */
+#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */
+
+
+/* Peripheral: NVMC */
+/* Description: Non Volatile Memory Controller. */
+
+/* Register: NVMC_READY */
+/* Description: Ready flag. */
+
+/* Bit 0 : NVMC ready. */
+#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
+#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
+#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */
+#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */
+
+/* Register: NVMC_CONFIG */
+/* Description: Configuration register. */
+
+/* Bits 1..0 : Program write enable. */
+#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
+#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
+#define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */
+#define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */
+#define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */
+
+/* Register: NVMC_ERASEALL */
+/* Description: Register for erasing all non-volatile user memory. */
+
+/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
+#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */
+#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */
+
+/* Register: NVMC_ERASEUICR */
+/* Description: Register for start erasing User Information Congfiguration Registers. */
+
+/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
+#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */
+#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */
+
+
+/* Peripheral: POWER */
+/* Description: Power Control. */
+
+/* Register: POWER_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on POFWARN event. */
+#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
+#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
+#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: POWER_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on POFWARN event. */
+#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
+#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
+#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: POWER_RESETREAS */
+/* Description: Reset reason. */
+
+/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
+#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
+#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
+#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Reset detected. */
+
+/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
+#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Reset detected. */
+
+/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
+#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
+#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
+#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Reset detected. */
+
+/* Bit 3 : Reset from CPU lock-up detected. */
+#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Reset detected. */
+
+/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
+#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
+#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
+#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Reset detected. */
+
+/* Bit 1 : Reset from watchdog detected. */
+#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
+#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
+#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Reset detected. */
+
+/* Bit 0 : Reset from pin-reset detected. */
+#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Reset detected. */
+
+/* Register: POWER_RAMSTATUS */
+/* Description: Ram status register. */
+
+/* Bit 3 : RAM block 3 status. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */
+#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */
+
+/* Bit 2 : RAM block 2 status. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */
+#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */
+
+/* Bit 1 : RAM block 1 status. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */
+#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */
+
+/* Bit 0 : RAM block 0 status. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */
+#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */
+
+/* Register: POWER_SYSTEMOFF */
+/* Description: System off register. */
+
+/* Bit 0 : Enter system off mode. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */
+
+/* Register: POWER_POFCON */
+/* Description: Power failure configuration. */
+
+/* Bits 2..1 : Set threshold level. */
+#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */
+#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */
+#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */
+#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */
+
+/* Bit 0 : Power failure comparator enable. */
+#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
+#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
+#define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */
+#define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */
+
+/* Register: POWER_GPREGRET */
+/* Description: General purpose retention register. This register is a retained register. */
+
+/* Bits 7..0 : General purpose retention register. */
+#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_RAMON */
+/* Description: Ram on/off. */
+
+/* Bit 17 : RAM block 1 behaviour in OFF mode. */
+#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
+#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
+#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */
+#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */
+
+/* Bit 16 : RAM block 0 behaviour in OFF mode. */
+#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
+#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
+#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */
+#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */
+
+/* Bit 1 : RAM block 1 behaviour in ON mode. */
+#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
+#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
+#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */
+#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */
+
+/* Bit 0 : RAM block 0 behaviour in ON mode. */
+#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
+#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
+#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */
+#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */
+
+/* Register: POWER_RESET */
+/* Description: Pin reset functionality configuration register. This register is a retained register. */
+
+/* Bit 0 : Enable or disable pin reset in debug interface mode. */
+#define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
+#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
+#define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */
+#define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */
+
+/* Register: POWER_RAMONB */
+/* Description: Ram on/off. */
+
+/* Bit 17 : RAM block 3 behaviour in OFF mode. */
+#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
+#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
+#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */
+#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */
+
+/* Bit 16 : RAM block 2 behaviour in OFF mode. */
+#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
+#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
+#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */
+#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
+
+/* Bit 1 : RAM block 3 behaviour in ON mode. */
+#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
+#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
+#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */
+#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */
+
+/* Bit 0 : RAM block 2 behaviour in ON mode. */
+#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
+#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
+#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
+#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
+
+/* Register: POWER_DCDCEN */
+/* Description: DCDC converter enable configuration register. */
+
+/* Bit 0 : Enable DCDC converter. */
+#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */
+#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */
+
+/* Register: POWER_DCDCFORCE */
+/* Description: DCDC power-up force register. */
+
+/* Bit 1 : DCDC power-up force on. */
+#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */
+#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */
+#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */
+#define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */
+
+/* Bit 0 : DCDC power-up force off. */
+#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
+#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
+#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */
+#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */
+
+
+/* Peripheral: PPI */
+/* Description: PPI controller. */
+
+/* Register: PPI_CHEN */
+/* Description: Channel enable. */
+
+/* Bit 31 : Enable PPI channel 31. */
+#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 30 : Enable PPI channel 30. */
+#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 29 : Enable PPI channel 29. */
+#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 28 : Enable PPI channel 28. */
+#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 27 : Enable PPI channel 27. */
+#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 26 : Enable PPI channel 26. */
+#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 25 : Enable PPI channel 25. */
+#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 24 : Enable PPI channel 24. */
+#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 23 : Enable PPI channel 23. */
+#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 22 : Enable PPI channel 22. */
+#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 21 : Enable PPI channel 21. */
+#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 20 : Enable PPI channel 20. */
+#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 15 : Enable PPI channel 15. */
+#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 14 : Enable PPI channel 14. */
+#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 13 : Enable PPI channel 13. */
+#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 12 : Enable PPI channel 12. */
+#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 11 : Enable PPI channel 11. */
+#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 10 : Enable PPI channel 10. */
+#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 9 : Enable PPI channel 9. */
+#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 8 : Enable PPI channel 8. */
+#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 7 : Enable PPI channel 7. */
+#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 6 : Enable PPI channel 6. */
+#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 5 : Enable PPI channel 5. */
+#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 4 : Enable PPI channel 4. */
+#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 3 : Enable PPI channel 3. */
+#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
+#define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
+
+/* Bit 2 : Enable PPI channel 2. */
+#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 1 : Enable PPI channel 1. */
+#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 0 : Enable PPI channel 0. */
+#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
+
+/* Register: PPI_CHENSET */
+/* Description: Channel enable set. */
+
+/* Bit 31 : Enable PPI channel 31. */
+#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 30 : Enable PPI channel 30. */
+#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 29 : Enable PPI channel 29. */
+#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 28 : Enable PPI channel 28. */
+#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 27 : Enable PPI channel 27. */
+#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 26 : Enable PPI channel 26. */
+#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 25 : Enable PPI channel 25. */
+#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 24 : Enable PPI channel 24. */
+#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 23 : Enable PPI channel 23. */
+#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 22 : Enable PPI channel 22. */
+#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 21 : Enable PPI channel 21. */
+#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 20 : Enable PPI channel 20. */
+#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 15 : Enable PPI channel 15. */
+#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 14 : Enable PPI channel 14. */
+#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 13 : Enable PPI channel 13. */
+#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 12 : Enable PPI channel 12. */
+#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 11 : Enable PPI channel 11. */
+#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 10 : Enable PPI channel 10. */
+#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 9 : Enable PPI channel 9. */
+#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 8 : Enable PPI channel 8. */
+#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 7 : Enable PPI channel 7. */
+#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 6 : Enable PPI channel 6. */
+#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 5 : Enable PPI channel 5. */
+#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 4 : Enable PPI channel 4. */
+#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 3 : Enable PPI channel 3. */
+#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 2 : Enable PPI channel 2. */
+#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 1 : Enable PPI channel 1. */
+#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 0 : Enable PPI channel 0. */
+#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
+
+/* Register: PPI_CHENCLR */
+/* Description: Channel enable clear. */
+
+/* Bit 31 : Disable PPI channel 31. */
+#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 30 : Disable PPI channel 30. */
+#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 29 : Disable PPI channel 29. */
+#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 28 : Disable PPI channel 28. */
+#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 27 : Disable PPI channel 27. */
+#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 26 : Disable PPI channel 26. */
+#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 25 : Disable PPI channel 25. */
+#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 24 : Disable PPI channel 24. */
+#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 23 : Disable PPI channel 23. */
+#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 22 : Disable PPI channel 22. */
+#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 21 : Disable PPI channel 21. */
+#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 20 : Disable PPI channel 20. */
+#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 15 : Disable PPI channel 15. */
+#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 14 : Disable PPI channel 14. */
+#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 13 : Disable PPI channel 13. */
+#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 12 : Disable PPI channel 12. */
+#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 11 : Disable PPI channel 11. */
+#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 10 : Disable PPI channel 10. */
+#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 9 : Disable PPI channel 9. */
+#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 8 : Disable PPI channel 8. */
+#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 7 : Disable PPI channel 7. */
+#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 6 : Disable PPI channel 6. */
+#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 5 : Disable PPI channel 5. */
+#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 4 : Disable PPI channel 4. */
+#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 3 : Disable PPI channel 3. */
+#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 2 : Disable PPI channel 2. */
+#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 1 : Disable PPI channel 1. */
+#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 0 : Disable PPI channel 0. */
+#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
+
+/* Register: PPI_CHG */
+/* Description: Channel group configuration. */
+
+/* Bit 31 : Include CH31 in channel group. */
+#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */
+
+/* Bit 30 : Include CH30 in channel group. */
+#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */
+
+/* Bit 29 : Include CH29 in channel group. */
+#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */
+
+/* Bit 28 : Include CH28 in channel group. */
+#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */
+
+/* Bit 27 : Include CH27 in channel group. */
+#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */
+
+/* Bit 26 : Include CH26 in channel group. */
+#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */
+
+/* Bit 25 : Include CH25 in channel group. */
+#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */
+
+/* Bit 24 : Include CH24 in channel group. */
+#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */
+
+/* Bit 23 : Include CH23 in channel group. */
+#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */
+
+/* Bit 22 : Include CH22 in channel group. */
+#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */
+
+/* Bit 21 : Include CH21 in channel group. */
+#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */
+
+/* Bit 20 : Include CH20 in channel group. */
+#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */
+
+/* Bit 15 : Include CH15 in channel group. */
+#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */
+
+/* Bit 14 : Include CH14 in channel group. */
+#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */
+
+/* Bit 13 : Include CH13 in channel group. */
+#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */
+
+/* Bit 12 : Include CH12 in channel group. */
+#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */
+
+/* Bit 11 : Include CH11 in channel group. */
+#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */
+
+/* Bit 10 : Include CH10 in channel group. */
+#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */
+
+/* Bit 9 : Include CH9 in channel group. */
+#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */
+
+/* Bit 8 : Include CH8 in channel group. */
+#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */
+
+/* Bit 7 : Include CH7 in channel group. */
+#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */
+
+/* Bit 6 : Include CH6 in channel group. */
+#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */
+
+/* Bit 5 : Include CH5 in channel group. */
+#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */
+
+/* Bit 4 : Include CH4 in channel group. */
+#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */
+
+/* Bit 3 : Include CH3 in channel group. */
+#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */
+
+/* Bit 2 : Include CH2 in channel group. */
+#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */
+
+/* Bit 1 : Include CH1 in channel group. */
+#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */
+
+/* Bit 0 : Include CH0 in channel group. */
+#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
+
+
+/* Peripheral: QDEC */
+/* Description: Rotary decoder. */
+
+/* Register: QDEC_SHORTS */
+/* Description: Shortcuts for the QDEC. */
+
+/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: QDEC_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on ACCOF event. */
+#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on REPORTRDY event. */
+#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on SAMPLERDY event. */
+#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: QDEC_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on ACCOF event. */
+#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on REPORTRDY event. */
+#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on SAMPLERDY event. */
+#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: QDEC_ENABLE */
+/* Description: Enable the QDEC. */
+
+/* Bit 0 : Enable or disable QDEC. */
+#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */
+#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */
+
+/* Register: QDEC_LEDPOL */
+/* Description: LED output pin polarity. */
+
+/* Bit 0 : LED output pin polarity. */
+#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */
+#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */
+
+/* Register: QDEC_SAMPLEPER */
+/* Description: Sample period. */
+
+/* Bits 2..0 : Sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */
+
+/* Register: QDEC_SAMPLE */
+/* Description: Motion sample value. */
+
+/* Bits 31..0 : Last sample taken in compliment to 2. */
+#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
+#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
+
+/* Register: QDEC_REPORTPER */
+/* Description: Number of samples to generate an EVENT_REPORTRDY. */
+
+/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
+#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */
+
+/* Register: QDEC_DBFEN */
+/* Description: Enable debouncer input filters. */
+
+/* Bit 0 : Enable debounce input filters. */
+#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */
+#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */
+
+/* Register: QDEC_LEDPRE */
+/* Description: Time LED is switched ON before the sample. */
+
+/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
+#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
+#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
+
+/* Register: QDEC_ACCDBL */
+/* Description: Accumulated double (error) transitions register. */
+
+/* Bits 3..0 : Accumulated double (error) transitions. */
+#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
+#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
+
+/* Register: QDEC_ACCDBLREAD */
+/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
+
+/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
+
+/* Register: QDEC_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: RADIO */
+/* Description: The radio. */
+
+/* Register: RADIO_SHORTS */
+/* Description: Shortcuts for the radio. */
+
+/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 5 : Shortcut between END event and START task. */
+#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
+#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
+#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 2 : Shortcut between DISABLED event and TXEN task.  */
+#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 1 : Shortcut between END event and DISABLE task. */
+#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between READY event and START task. */
+#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
+#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
+#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: RADIO_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 10 : Enable interrupt on BCMATCH event. */
+#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 7 : Enable interrupt on RSSIEND event. */
+#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 6 : Enable interrupt on DEVMISS event. */
+#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 5 : Enable interrupt on DEVMATCH event. */
+#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 4 : Enable interrupt on DISABLED event. */
+#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 3 : Enable interrupt on END event. */
+#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on PAYLOAD event. */
+#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on ADDRESS event. */
+#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on READY event. */
+#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: RADIO_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 10 : Disable interrupt on BCMATCH event. */
+#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 7 : Disable interrupt on RSSIEND event. */
+#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 6 : Disable interrupt on DEVMISS event. */
+#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 5 : Disable interrupt on DEVMATCH event. */
+#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 4 : Disable interrupt on DISABLED event. */
+#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 3 : Disable interrupt on END event. */
+#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on PAYLOAD event. */
+#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on ADDRESS event. */
+#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on READY event. */
+#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: RADIO_CRCSTATUS */
+/* Description: CRC status of received packet. */
+
+/* Bit 0 : CRC status of received packet. */
+#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
+
+/* Register: RADIO_RXMATCH */
+/* Description: Received address. */
+
+/* Bits 2..0 : Logical address in which previous packet was received. */
+#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
+#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
+
+/* Register: RADIO_RXCRC */
+/* Description: Received CRC. */
+
+/* Bits 23..0 : CRC field of previously received packet. */
+#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
+#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
+
+/* Register: RADIO_DAI */
+/* Description: Device address match index. */
+
+/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
+#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
+#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
+
+/* Register: RADIO_FREQUENCY */
+/* Description: Frequency. */
+
+/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task.  */
+#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+
+/* Register: RADIO_TXPOWER */
+/* Description: Output power. */
+
+/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
+#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */
+#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
+
+/* Register: RADIO_MODE */
+/* Description: Data rate and modulation. */
+
+/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
+#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */
+#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */
+#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */
+#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */
+
+/* Register: RADIO_PCNF0 */
+/* Description: Packet configuration 0. */
+
+/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
+#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
+#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
+
+/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
+#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
+#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
+
+/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
+#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
+#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
+
+/* Register: RADIO_PCNF1 */
+/* Description: Packet configuration 1. */
+
+/* Bit 25 : Packet whitening enable. */
+#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */
+#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */
+
+/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
+#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
+#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
+
+/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
+#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
+#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
+
+/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
+#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
+#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
+
+/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
+#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
+#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
+
+/* Register: RADIO_PREFIX0 */
+/* Description: Prefixes bytes for logical addresses 0 to 3. */
+
+/* Bits 31..24 : Address prefix 3. Decision point: START task. */
+#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
+#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
+
+/* Bits 23..16 : Address prefix 2. Decision point: START task. */
+#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
+#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
+
+/* Bits 15..8 : Address prefix 1. Decision point: START task. */
+#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
+#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
+
+/* Bits 7..0 : Address prefix 0. Decision point: START task. */
+#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
+#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
+
+/* Register: RADIO_PREFIX1 */
+/* Description: Prefixes bytes for logical addresses 4 to 7. */
+
+/* Bits 31..24 : Address prefix 7. Decision point: START task. */
+#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
+#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
+
+/* Bits 23..16 : Address prefix 6. Decision point: START task. */
+#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
+#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
+
+/* Bits 15..8 : Address prefix 5. Decision point: START task. */
+#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
+#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
+
+/* Bits 7..0 : Address prefix 4. Decision point: START task. */
+#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
+#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
+
+/* Register: RADIO_TXADDRESS */
+/* Description: Transmit address select. */
+
+/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
+#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
+#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
+
+/* Register: RADIO_RXADDRESSES */
+/* Description: Receive address select. */
+
+/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */
+
+/* Register: RADIO_CRCCNF */
+/* Description: CRC configuration. */
+
+/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
+#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */
+#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */
+
+/* Bits 1..0 : CRC length. Decision point: START task. */
+#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
+#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
+#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */
+#define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */
+#define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */
+#define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */
+
+/* Register: RADIO_CRCPOLY */
+/* Description: CRC polynomial. */
+
+/* Bits 23..0 : CRC polynomial. Decision point: START task. */
+#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
+#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
+
+/* Register: RADIO_CRCINIT */
+/* Description: CRC initial value. */
+
+/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
+#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
+#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
+
+/* Register: RADIO_TEST */
+/* Description: Test features enable register. */
+
+/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
+#define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */
+#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */
+#define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */
+#define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */
+
+/* Bit 0 : Constant carrier. Decision point: TXEN task. */
+#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */
+#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */
+#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */
+#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */
+
+/* Register: RADIO_TIFS */
+/* Description: Inter Frame Spacing in microseconds. */
+
+/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
+#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
+#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
+
+/* Register: RADIO_RSSISAMPLE */
+/* Description: RSSI sample. */
+
+/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
+
+/* Register: RADIO_STATE */
+/* Description: Current radio state. */
+
+/* Bits 3..0 : Current radio state. */
+#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
+#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
+#define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */
+#define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */
+#define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */
+#define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */
+#define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */
+#define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */
+#define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */
+#define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */
+#define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */
+
+/* Register: RADIO_DATAWHITEIV */
+/* Description: Data whitening initial value. */
+
+/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
+
+/* Register: RADIO_DAP */
+/* Description: Device address prefix. */
+
+/* Bits 15..0 : Device address prefix. */
+#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
+#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
+
+/* Register: RADIO_DACNF */
+/* Description: Device address match configuration. */
+
+/* Bit 15 : TxAdd for device address 7. */
+#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
+#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
+
+/* Bit 14 : TxAdd for device address 6. */
+#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
+#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
+
+/* Bit 13 : TxAdd for device address 5. */
+#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
+#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
+
+/* Bit 12 : TxAdd for device address 4. */
+#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
+#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
+
+/* Bit 11 : TxAdd for device address 3. */
+#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
+#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
+
+/* Bit 10 : TxAdd for device address 2. */
+#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
+#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
+
+/* Bit 9 : TxAdd for device address 1. */
+#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
+#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
+
+/* Bit 8 : TxAdd for device address 0. */
+#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
+#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
+
+/* Bit 7 : Enable or disable device address matching using device address 7. */
+#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
+#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
+#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 6 : Enable or disable device address matching using device address 6. */
+#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
+#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
+#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 5 : Enable or disable device address matching using device address 5. */
+#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
+#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
+#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 4 : Enable or disable device address matching using device address 4. */
+#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
+#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
+#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 3 : Enable or disable device address matching using device address 3. */
+#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
+#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
+#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 2 : Enable or disable device address matching using device address 2. */
+#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
+#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
+#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 1 : Enable or disable device address matching using device address 1. */
+#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
+#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
+#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 0 : Enable or disable device address matching using device address 0. */
+#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
+#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
+#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */
+
+/* Register: RADIO_OVERRIDE0 */
+/* Description: Trim value override register 0. */
+
+/* Bits 31..0 : Trim value override 0. */
+#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */
+#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */
+
+/* Register: RADIO_OVERRIDE1 */
+/* Description: Trim value override register 1. */
+
+/* Bits 31..0 : Trim value override 1. */
+#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */
+#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */
+
+/* Register: RADIO_OVERRIDE2 */
+/* Description: Trim value override register 2. */
+
+/* Bits 31..0 : Trim value override 2. */
+#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */
+#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */
+
+/* Register: RADIO_OVERRIDE3 */
+/* Description: Trim value override register 3. */
+
+/* Bits 31..0 : Trim value override 3. */
+#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */
+#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */
+
+/* Register: RADIO_OVERRIDE4 */
+/* Description: Trim value override register 4. */
+
+/* Bit 31 : Enable or disable override of default trim values. */
+#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */
+#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */
+#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */
+
+/* Bits 27..0 : Trim value override 4. */
+#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */
+#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */
+
+/* Register: RADIO_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: RNG */
+/* Description: Random Number Generator. */
+
+/* Register: RNG_SHORTS */
+/* Description: Shortcuts for the RNG. */
+
+/* Bit 0 : Shortcut between VALRDY event and STOP task. */
+#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: RNG_INTENSET */
+/* Description: Interrupt enable set register */
+
+/* Bit 0 : Enable interrupt on VALRDY event. */
+#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: RNG_INTENCLR */
+/* Description: Interrupt enable clear register */
+
+/* Bit 0 : Disable interrupt on VALRDY event. */
+#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: RNG_CONFIG */
+/* Description: Configuration register. */
+
+/* Bit 0 : Digital error correction enable. */
+#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */
+#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */
+
+/* Register: RNG_VALUE */
+/* Description: RNG random number. */
+
+/* Bits 7..0 : Generated random number. */
+#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
+#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
+
+/* Register: RNG_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: RTC */
+/* Description: Real time counter 0. */
+
+/* Register: RTC_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 19 : Enable interrupt on COMPARE[3] event. */
+#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 18 : Enable interrupt on COMPARE[2] event. */
+#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 17 : Enable interrupt on COMPARE[1] event. */
+#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 16 : Enable interrupt on COMPARE[0] event. */
+#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on OVRFLW event. */
+#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on TICK event. */
+#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: RTC_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 19 : Disable interrupt on COMPARE[3] event. */
+#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 18 : Disable interrupt on COMPARE[2] event. */
+#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 17 : Disable interrupt on COMPARE[1] event. */
+#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 16 : Disable interrupt on COMPARE[0] event. */
+#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on OVRFLW event. */
+#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on TICK event. */
+#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: RTC_EVTEN */
+/* Description: Configures event enable routing to PPI for each RTC event. */
+
+/* Bit 19 : COMPARE[3] event enable. */
+#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 18 : COMPARE[2] event enable. */
+#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 17 : COMPARE[1] event enable. */
+#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 16 : COMPARE[0] event enable. */
+#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 1 : OVRFLW event enable. */
+#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 0 : TICK event enable. */
+#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */
+
+/* Register: RTC_EVTENSET */
+/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
+
+/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
+#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
+#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
+#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
+#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 1 : Enable routing to PPI of OVRFLW event. */
+#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 0 : Enable routing to PPI of TICK event. */
+#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
+
+/* Register: RTC_EVTENCLR */
+/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
+
+/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
+#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
+#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
+#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
+#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 1 : Disable routing to PPI of OVRFLW event. */
+#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 0 : Disable routing to PPI of TICK event. */
+#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */
+
+/* Register: RTC_COUNTER */
+/* Description: Current COUNTER value. */
+
+/* Bits 23..0 : Counter value. */
+#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
+#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
+
+/* Register: RTC_PRESCALER */
+/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
+
+/* Bits 11..0 : RTC PRESCALER value. */
+#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: RTC_CC */
+/* Description: Capture/compare registers. */
+
+/* Bits 23..0 : Compare value. */
+#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
+#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
+
+/* Register: RTC_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: SPI */
+/* Description: SPI master 0. */
+
+/* Register: SPI_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on READY event. */
+#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: SPI_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on READY event. */
+#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: SPI_ENABLE */
+/* Description: Enable SPI. */
+
+/* Bits 2..0 : Enable or disable SPI. */
+#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */
+#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */
+
+/* Register: SPI_RXD */
+/* Description: RX data. */
+
+/* Bits 7..0 : RX data from last transfer. */
+#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: SPI_TXD */
+/* Description: TX data. */
+
+/* Bits 7..0 : TX data for next transfer. */
+#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: SPI_FREQUENCY */
+/* Description: SPI frequency */
+
+/* Bits 31..0 : SPI data rate. */
+#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */
+#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */
+#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */
+#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */
+#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */
+#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */
+#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */
+
+/* Register: SPI_CONFIG */
+/* Description: Configuration register. */
+
+/* Bit 2 : Serial clock (SCK) polarity. */
+#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
+#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
+
+/* Bit 1 : Serial clock (SCK) phase. */
+#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
+#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
+
+/* Bit 0 : Bit order. */
+#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
+#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
+
+/* Register: SPI_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: SPIS */
+/* Description: SPI slave 1. */
+
+/* Register: SPIS_SHORTS */
+/* Description: Shortcuts for SPIS. */
+
+/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
+#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */
+#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: SPIS_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 10 : Enable interrupt on ACQUIRED event. */
+#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 4 : enable interrupt on ENDRX event. */
+#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on END event. */
+#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: SPIS_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 10 : Disable interrupt on ACQUIRED event. */
+#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 4 : Disable interrupt on ENDRX event. */
+#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on END event. */
+#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: SPIS_SEMSTAT */
+/* Description: Semaphore status. */
+
+/* Bits 1..0 : Semaphore status. */
+#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */
+#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */
+#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */
+#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */
+
+/* Register: SPIS_STATUS */
+/* Description: Status from last transaction. */
+
+/* Bit 1 : RX buffer overflow detected, and prevented. */
+#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */
+#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */
+#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */
+
+/* Bit 0 : TX buffer overread detected, and prevented. */
+#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */
+#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */
+#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */
+
+/* Register: SPIS_ENABLE */
+/* Description: Enable SPIS. */
+
+/* Bits 2..0 : Enable or disable SPIS. */
+#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */
+#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */
+
+/* Register: SPIS_MAXRX */
+/* Description: Maximum number of bytes in the receive buffer. */
+
+/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
+#define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */
+#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */
+
+/* Register: SPIS_AMOUNTRX */
+/* Description: Number of bytes received in last granted transaction. */
+
+/* Bits 7..0 : Number of bytes received in last granted transaction. */
+#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */
+#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */
+
+/* Register: SPIS_MAXTX */
+/* Description: Maximum number of bytes in the transmit buffer. */
+
+/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
+#define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */
+#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */
+
+/* Register: SPIS_AMOUNTTX */
+/* Description: Number of bytes transmitted in last granted transaction. */
+
+/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
+#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */
+#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */
+
+/* Register: SPIS_CONFIG */
+/* Description: Configuration register. */
+
+/* Bit 2 : Serial clock (SCK) polarity. */
+#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
+#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
+
+/* Bit 1 : Serial clock (SCK) phase. */
+#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
+#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
+
+/* Bit 0 : Bit order. */
+#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
+#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
+
+/* Register: SPIS_DEF */
+/* Description: Default character. */
+
+/* Bits 7..0 : Default character. */
+#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
+#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
+
+/* Register: SPIS_ORC */
+/* Description: Over-read character. */
+
+/* Bits 7..0 : Over-read character. */
+#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+/* Register: SPIS_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: TEMP */
+/* Description: Temperature Sensor. */
+
+/* Register: TEMP_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 0 : Enable interrupt on DATARDY event. */
+#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: TEMP_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 0 : Disable interrupt on DATARDY event. */
+#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: TEMP_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: TIMER */
+/* Description: Timer 0. */
+
+/* Register: TIMER_SHORTS */
+/* Description: Shortcuts for Timer. */
+
+/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
+#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
+#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
+#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
+#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: TIMER_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 19 : Enable interrupt on COMPARE[3] */
+#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 18 : Enable interrupt on COMPARE[2] */
+#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 17 : Enable interrupt on COMPARE[1] */
+#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 16 : Enable interrupt on COMPARE[0] */
+#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: TIMER_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 19 : Disable interrupt on COMPARE[3] */
+#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 18 : Disable interrupt on COMPARE[2] */
+#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 17 : Disable interrupt on COMPARE[1] */
+#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 16 : Disable interrupt on COMPARE[0] */
+#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: TIMER_MODE */
+/* Description: Timer Mode selection. */
+
+/* Bit 0 : Select Normal or Counter mode. */
+#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */
+#define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */
+
+/* Register: TIMER_BITMODE */
+/* Description: Sets timer behaviour. */
+
+/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
+#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */
+#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */
+#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */
+#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */
+
+/* Register: TIMER_PRESCALER */
+/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
+
+/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
+#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: TIMER_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: TWI */
+/* Description: Two-wire interface master 0. */
+
+/* Register: TWI_SHORTS */
+/* Description: Shortcuts for TWI. */
+
+/* Bit 1 : Shortcut between BB event and the STOP task. */
+#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
+#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */
+#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: TWI_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 18 : Enable interrupt on SUSPENDED event. */
+#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 14 : Enable interrupt on BB event. */
+#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 9 : Enable interrupt on ERROR event. */
+#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 7 : Enable interrupt on TXDSENT event. */
+#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on READY event. */
+#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on STOPPED event. */
+#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: TWI_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 18 : Disable interrupt on SUSPENDED event. */
+#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 14 : Disable interrupt on BB event. */
+#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 9 : Disable interrupt on ERROR event. */
+#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 7 : Disable interrupt on TXDSENT event. */
+#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on RXDREADY event. */
+#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on STOPPED event. */
+#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: TWI_ERRORSRC */
+/* Description: Two-wire error source. Write error field to 1 to clear error. */
+
+/* Bit 2 : NACK received after sending a data byte. */
+#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */
+#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */
+#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 1 : NACK received after sending the address. */
+#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */
+#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */
+#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */
+#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
+#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
+#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
+
+/* Register: TWI_ENABLE */
+/* Description: Enable two-wire master. */
+
+/* Bits 2..0 : Enable or disable W2M */
+#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */
+#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */
+
+/* Register: TWI_RXD */
+/* Description: RX data register. */
+
+/* Bits 7..0 : RX data from last transfer. */
+#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: TWI_TXD */
+/* Description: TX data register. */
+
+/* Bits 7..0 : TX data for next transfer. */
+#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: TWI_FREQUENCY */
+/* Description: Two-wire frequency. */
+
+/* Bits 31..0 : Two-wire master clock frequency. */
+#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */
+#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
+#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps). */
+
+/* Register: TWI_ADDRESS */
+/* Description: Address used in the two-wire transfer. */
+
+/* Bits 6..0 : Two-wire address. */
+#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+/* Register: TWI_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: UART */
+/* Description: Universal Asynchronous Receiver/Transmitter. */
+
+/* Register: UART_SHORTS */
+/* Description: Shortcuts for UART. */
+
+/* Bit 4 : Shortcut between NCTS event and STOPRX task. */
+#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
+#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 3 : Shortcut between CTS event and STARTRX task. */
+#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
+#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: UART_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 17 : Enable interrupt on RXTO event. */
+#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 9 : Enable interrupt on ERROR event. */
+#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 7 : Enable interrupt on TXRDY event. */
+#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on RXRDY event. */
+#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on NCTS event. */
+#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on CTS event. */
+#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: UART_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 17 : Disable interrupt on RXTO event. */
+#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 9 : Disable interrupt on ERROR event. */
+#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 7 : Disable interrupt on TXRDY event. */
+#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on RXRDY event. */
+#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on NCTS event. */
+#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on CTS event. */
+#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: UART_ERRORSRC */
+/* Description: Error source. Write error field to 1 to clear error. */
+
+/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
+#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */
+#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */
+#define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
+#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */
+#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */
+#define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
+#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */
+#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */
+#define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
+#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
+#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
+#define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
+
+/* Register: UART_ENABLE */
+/* Description: Enable UART and acquire IOs. */
+
+/* Bits 2..0 : Enable or disable UART and acquire IOs. */
+#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */
+#define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */
+
+/* Register: UART_RXD */
+/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
+
+/* Bits 7..0 : RX data from previous transfer. Double buffered. */
+#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: UART_TXD */
+/* Description: TXD register. */
+
+/* Bits 7..0 : TX data for transfer. */
+#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: UART_BAUDRATE */
+/* Description: UART Baudrate. */
+
+/* Bits 31..0 : UART baudrate. */
+#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */
+
+/* Register: UART_CONFIG */
+/* Description: Configuration of parity and hardware flow control register. */
+
+/* Bits 3..1 : Include parity bit. */
+#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */
+#define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */
+
+/* Bit 0 : Hardware flow control. */
+#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */
+#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */
+
+/* Register: UART_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: UICR */
+/* Description: User Information Configuration. */
+
+/* Register: UICR_RBPCONF */
+/* Description: Readback protection configuration. */
+
+/* Bits 15..8 : Readback protect all code in the device. */
+#define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */
+#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */
+#define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
+#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
+
+/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
+#define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */
+#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */
+#define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
+#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
+
+/* Register: UICR_XTALFREQ */
+/* Description: Reset value for CLOCK XTALFREQ register. */
+
+/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
+#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
+#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
+#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */
+#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
+
+/* Register: UICR_FWID */
+/* Description: Firmware ID. */
+
+/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
+#define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */
+#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */
+
+
+/* Peripheral: WDT */
+/* Description: Watchdog Timer. */
+
+/* Register: WDT_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 0 : Enable interrupt on TIMEOUT event. */
+#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
+#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
+#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: WDT_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 0 : Disable interrupt on TIMEOUT event. */
+#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
+#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
+#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: WDT_RUNSTATUS */
+/* Description: Watchdog running status. */
+
+/* Bit 0 : Watchdog running status. */
+#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */
+#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */
+
+/* Register: WDT_REQSTATUS */
+/* Description: Request status. */
+
+/* Bit 7 : Request status for RR[7]. */
+#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */
+
+/* Bit 6 : Request status for RR[6]. */
+#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */
+
+/* Bit 5 : Request status for RR[5]. */
+#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */
+
+/* Bit 4 : Request status for RR[4]. */
+#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */
+
+/* Bit 3 : Request status for RR[3]. */
+#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */
+
+/* Bit 2 : Request status for RR[2]. */
+#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */
+
+/* Bit 1 : Request status for RR[1]. */
+#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */
+
+/* Bit 0 : Request status for RR[0]. */
+#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */
+
+/* Register: WDT_RREN */
+/* Description: Reload request enable. */
+
+/* Bit 7 : Enable or disable RR[7] register. */
+#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */
+#define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */
+
+/* Bit 6 : Enable or disable RR[6] register. */
+#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */
+#define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */
+
+/* Bit 5 : Enable or disable RR[5] register. */
+#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */
+#define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */
+
+/* Bit 4 : Enable or disable RR[4] register. */
+#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */
+#define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */
+
+/* Bit 3 : Enable or disable RR[3] register. */
+#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */
+#define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */
+
+/* Bit 2 : Enable or disable RR[2] register. */
+#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
+#define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */
+
+/* Bit 1 : Enable or disable RR[1] register. */
+#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */
+#define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */
+
+/* Bit 0 : Enable or disable RR[0] register. */
+#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */
+#define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */
+
+/* Register: WDT_CONFIG */
+/* Description: Configuration register. */
+
+/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
+#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
+#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
+#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */
+#define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */
+
+/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
+#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */
+#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */
+
+/* Register: WDT_RR */
+/* Description: Reload requests registers. */
+
+/* Bits 31..0 : Reload register. */
+#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
+#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
+#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */
+
+/* Register: WDT_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/*lint --flb "Leave library region" */
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51_deprecated.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,448 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+#ifndef NRF51_DEPRECATED_H
+#define NRF51_DEPRECATED_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and 
+ * nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these
+ * macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead.
+ */
+
+/* NVMC */
+/* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */
+#define ERASEPROTECTEDPAGE   ERASEPCR0
+
+ 
+/* LPCOMP */
+/* The interrupt ISR was renamed. Adding old name to the macros. */
+#define LPCOMP_COMP_IRQHandler          LPCOMP_IRQHandler
+#define LPCOMP_COMP_IRQn                LPCOMP_IRQn
+/* Corrected typo in RESULT register. */
+#define LPCOMP_RESULT_RESULT_Bellow     LPCOMP_RESULT_RESULT_Below
+ 
+ 
+/* MPU */
+/* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */
+#define MPU_PERR0_LPCOMP_COMP_Pos           MPU_PERR0_LPCOMP_Pos
+#define MPU_PERR0_LPCOMP_COMP_Msk           MPU_PERR0_LPCOMP_Msk
+#define MPU_PERR0_LPCOMP_COMP_InRegion1     MPU_PERR0_LPCOMP_InRegion1
+#define MPU_PERR0_LPCOMP_COMP_InRegion0     MPU_PERR0_LPCOMP_InRegion0
+ 
+ 
+/* POWER */
+/* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
+#define POWER_RAMON_OFFRAM3_Pos         (19UL)                                  
+#define POWER_RAMON_OFFRAM3_Msk         (0x1UL << POWER_RAMON_OFFRAM3_Pos)      
+#define POWER_RAMON_OFFRAM3_RAM3Off     (0UL)                                   
+#define POWER_RAMON_OFFRAM3_RAM3On      (1UL)                                   
+/* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
+#define POWER_RAMON_OFFRAM2_Pos         (18UL)                                  
+#define POWER_RAMON_OFFRAM2_Msk         (0x1UL << POWER_RAMON_OFFRAM2_Pos)      
+#define POWER_RAMON_OFFRAM2_RAM2Off     (0UL)                                   
+#define POWER_RAMON_OFFRAM2_RAM2On      (1UL)                                  
+/* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
+#define POWER_RAMON_ONRAM3_Pos          (3UL)                                  
+#define POWER_RAMON_ONRAM3_Msk          (0x1UL << POWER_RAMON_ONRAM3_Pos)      
+#define POWER_RAMON_ONRAM3_RAM3Off      (0UL)                                  
+#define POWER_RAMON_ONRAM3_RAM3On       (1UL)                                  
+/* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
+#define POWER_RAMON_ONRAM2_Pos          (2UL)                                  
+#define POWER_RAMON_ONRAM2_Msk          (0x1UL << POWER_RAMON_ONRAM2_Pos)       
+#define POWER_RAMON_ONRAM2_RAM2Off      (0UL)                                  
+#define POWER_RAMON_ONRAM2_RAM2On       (1UL)                                 
+
+ 
+/* RADIO */
+/* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */
+#define RADIO_TXPOWER_TXPOWER_Neg40dBm  RADIO_TXPOWER_TXPOWER_Neg30dBm      
+/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
+#define RADIO_CRCCNF_SKIP_ADDR_Pos      RADIO_CRCCNF_SKIPADDR_Pos 
+#define RADIO_CRCCNF_SKIP_ADDR_Msk      RADIO_CRCCNF_SKIPADDR_Msk 
+#define RADIO_CRCCNF_SKIP_ADDR_Include  RADIO_CRCCNF_SKIPADDR_Include 
+#define RADIO_CRCCNF_SKIP_ADDR_Skip     RADIO_CRCCNF_SKIPADDR_Skip 
+/* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */
+#define RADIO_TEST_PLL_LOCK_Pos         RADIO_TEST_PLLLOCK_Pos 
+#define RADIO_TEST_PLL_LOCK_Msk         RADIO_TEST_PLLLOCK_Msk 
+#define RADIO_TEST_PLL_LOCK_Disabled    RADIO_TEST_PLLLOCK_Disabled 
+#define RADIO_TEST_PLL_LOCK_Enabled     RADIO_TEST_PLLLOCK_Enabled 
+/* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */
+#define RADIO_TEST_CONST_CARRIER_Pos        RADIO_TEST_CONSTCARRIER_Pos 
+#define RADIO_TEST_CONST_CARRIER_Msk        RADIO_TEST_CONSTCARRIER_Msk 
+#define RADIO_TEST_CONST_CARRIER_Disabled   RADIO_TEST_CONSTCARRIER_Disabled 
+#define RADIO_TEST_CONST_CARRIER_Enabled    RADIO_TEST_CONSTCARRIER_Enabled 
+
+
+/* FICR */
+/* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */
+#define SIZERAMBLOCK0   SIZERAMBLOCKS                   
+#define SIZERAMBLOCK1   SIZERAMBLOCKS                   
+#define SIZERAMBLOCK2   SIZERAMBLOCK[2]                 /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
+#define SIZERAMBLOCK3   SIZERAMBLOCK[3]                 /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
+/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
+#define DEVICEID0       DEVICEID[0]                     
+#define DEVICEID1       DEVICEID[1]                     
+/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
+#define ER0             ER[0]                           
+#define ER1             ER[1]                          
+#define ER2             ER[2]                       
+#define ER3             ER[3]                      
+/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
+#define IR0             IR[0]                         
+#define IR1             IR[1]                         
+#define IR2             IR[2]                         
+#define IR3             IR[3]                          
+/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
+#define DEVICEADDR0     DEVICEADDR[0]                  
+#define DEVICEADDR1     DEVICEADDR[1]                  
+
+
+/* PPI */
+/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
+#define TASKS_CHG0EN     TASKS_CHG[0].EN                    
+#define TASKS_CHG0DIS    TASKS_CHG[0].DIS                  
+#define TASKS_CHG1EN     TASKS_CHG[1].EN                    
+#define TASKS_CHG1DIS    TASKS_CHG[1].DIS                  
+#define TASKS_CHG2EN     TASKS_CHG[2].EN                   
+#define TASKS_CHG2DIS    TASKS_CHG[2].DIS                  
+#define TASKS_CHG3EN     TASKS_CHG[3].EN                    
+#define TASKS_CHG3DIS    TASKS_CHG[3].DIS                  
+/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
+#define CH0_EEP          CH[0].EEP                          
+#define CH0_TEP          CH[0].TEP                          
+#define CH1_EEP          CH[1].EEP                         
+#define CH1_TEP          CH[1].TEP                         
+#define CH2_EEP          CH[2].EEP                          
+#define CH2_TEP          CH[2].TEP                         
+#define CH3_EEP          CH[3].EEP                          
+#define CH3_TEP          CH[3].TEP                         
+#define CH4_EEP          CH[4].EEP                         
+#define CH4_TEP          CH[4].TEP                         
+#define CH5_EEP          CH[5].EEP                          
+#define CH5_TEP          CH[5].TEP                          
+#define CH6_EEP          CH[6].EEP                          
+#define CH6_TEP          CH[6].TEP                         
+#define CH7_EEP          CH[7].EEP                          
+#define CH7_TEP          CH[7].TEP                          
+#define CH8_EEP          CH[8].EEP                         
+#define CH8_TEP          CH[8].TEP                          
+#define CH9_EEP          CH[9].EEP                          
+#define CH9_TEP          CH[9].TEP                          
+#define CH10_EEP         CH[10].EEP                         
+#define CH10_TEP         CH[10].TEP                         
+#define CH11_EEP         CH[11].EEP                         
+#define CH11_TEP         CH[11].TEP                         
+#define CH12_EEP         CH[12].EEP                         
+#define CH12_TEP         CH[12].TEP                         
+#define CH13_EEP         CH[13].EEP                         
+#define CH13_TEP         CH[13].TEP                         
+#define CH14_EEP         CH[14].EEP                         
+#define CH14_TEP         CH[14].TEP                         
+#define CH15_EEP         CH[15].EEP                         
+#define CH15_TEP         CH[15].TEP                        
+/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
+#define CHG0             CHG[0]                            
+#define CHG1             CHG[1]                            
+#define CHG2             CHG[2]                             
+#define CHG3             CHG[3]                           
+/* All bitfield macros for the CHGx registers therefore changed name. */
+#define PPI_CHG0_CH15_Pos       PPI_CHG_CH15_Pos            
+#define PPI_CHG0_CH15_Msk       PPI_CHG_CH15_Msk            
+#define PPI_CHG0_CH15_Excluded  PPI_CHG_CH15_Excluded       
+#define PPI_CHG0_CH15_Included  PPI_CHG_CH15_Included       
+#define PPI_CHG0_CH14_Pos       PPI_CHG_CH14_Pos            
+#define PPI_CHG0_CH14_Msk       PPI_CHG_CH14_Msk           
+#define PPI_CHG0_CH14_Excluded  PPI_CHG_CH14_Excluded       
+#define PPI_CHG0_CH14_Included  PPI_CHG_CH14_Included       
+#define PPI_CHG0_CH13_Pos       PPI_CHG_CH13_Pos            
+#define PPI_CHG0_CH13_Msk       PPI_CHG_CH13_Msk            
+#define PPI_CHG0_CH13_Excluded  PPI_CHG_CH13_Excluded      
+#define PPI_CHG0_CH13_Included  PPI_CHG_CH13_Included       
+#define PPI_CHG0_CH12_Pos       PPI_CHG_CH12_Pos            
+#define PPI_CHG0_CH12_Msk       PPI_CHG_CH12_Msk            
+#define PPI_CHG0_CH12_Excluded  PPI_CHG_CH12_Excluded       
+#define PPI_CHG0_CH12_Included  PPI_CHG_CH12_Included       
+#define PPI_CHG0_CH11_Pos       PPI_CHG_CH11_Pos            
+#define PPI_CHG0_CH11_Msk       PPI_CHG_CH11_Msk            
+#define PPI_CHG0_CH11_Excluded  PPI_CHG_CH11_Excluded       
+#define PPI_CHG0_CH11_Included  PPI_CHG_CH11_Included       
+#define PPI_CHG0_CH10_Pos       PPI_CHG_CH10_Pos            
+#define PPI_CHG0_CH10_Msk       PPI_CHG_CH10_Msk            
+#define PPI_CHG0_CH10_Excluded  PPI_CHG_CH10_Excluded       
+#define PPI_CHG0_CH10_Included  PPI_CHG_CH10_Included       
+#define PPI_CHG0_CH9_Pos        PPI_CHG_CH9_Pos             
+#define PPI_CHG0_CH9_Msk        PPI_CHG_CH9_Msk             
+#define PPI_CHG0_CH9_Excluded   PPI_CHG_CH9_Excluded        
+#define PPI_CHG0_CH9_Included   PPI_CHG_CH9_Included        
+#define PPI_CHG0_CH8_Pos        PPI_CHG_CH8_Pos             
+#define PPI_CHG0_CH8_Msk        PPI_CHG_CH8_Msk             
+#define PPI_CHG0_CH8_Excluded   PPI_CHG_CH8_Excluded        
+#define PPI_CHG0_CH8_Included   PPI_CHG_CH8_Included        
+#define PPI_CHG0_CH7_Pos        PPI_CHG_CH7_Pos             
+#define PPI_CHG0_CH7_Msk        PPI_CHG_CH7_Msk             
+#define PPI_CHG0_CH7_Excluded   PPI_CHG_CH7_Excluded        
+#define PPI_CHG0_CH7_Included   PPI_CHG_CH7_Included        
+#define PPI_CHG0_CH6_Pos        PPI_CHG_CH6_Pos             
+#define PPI_CHG0_CH6_Msk        PPI_CHG_CH6_Msk             
+#define PPI_CHG0_CH6_Excluded   PPI_CHG_CH6_Excluded        
+#define PPI_CHG0_CH6_Included   PPI_CHG_CH6_Included        
+#define PPI_CHG0_CH5_Pos        PPI_CHG_CH5_Pos             
+#define PPI_CHG0_CH5_Msk        PPI_CHG_CH5_Msk             
+#define PPI_CHG0_CH5_Excluded   PPI_CHG_CH5_Excluded       
+#define PPI_CHG0_CH5_Included   PPI_CHG_CH5_Included        
+#define PPI_CHG0_CH4_Pos        PPI_CHG_CH4_Pos             
+#define PPI_CHG0_CH4_Msk        PPI_CHG_CH4_Msk             
+#define PPI_CHG0_CH4_Excluded   PPI_CHG_CH4_Excluded       
+#define PPI_CHG0_CH4_Included   PPI_CHG_CH4_Included       
+#define PPI_CHG0_CH3_Pos        PPI_CHG_CH3_Pos             
+#define PPI_CHG0_CH3_Msk        PPI_CHG_CH3_Msk            
+#define PPI_CHG0_CH3_Excluded   PPI_CHG_CH3_Excluded        
+#define PPI_CHG0_CH3_Included   PPI_CHG_CH3_Included       
+#define PPI_CHG0_CH2_Pos        PPI_CHG_CH2_Pos            
+#define PPI_CHG0_CH2_Msk        PPI_CHG_CH2_Msk             
+#define PPI_CHG0_CH2_Excluded   PPI_CHG_CH2_Excluded       
+#define PPI_CHG0_CH2_Included   PPI_CHG_CH2_Included       
+#define PPI_CHG0_CH1_Pos        PPI_CHG_CH1_Pos            
+#define PPI_CHG0_CH1_Msk        PPI_CHG_CH1_Msk            
+#define PPI_CHG0_CH1_Excluded   PPI_CHG_CH1_Excluded        
+#define PPI_CHG0_CH1_Included   PPI_CHG_CH1_Included       
+#define PPI_CHG0_CH0_Pos        PPI_CHG_CH0_Pos            
+#define PPI_CHG0_CH0_Msk        PPI_CHG_CH0_Msk            
+#define PPI_CHG0_CH0_Excluded   PPI_CHG_CH0_Excluded        
+#define PPI_CHG0_CH0_Included   PPI_CHG_CH0_Included       
+#define PPI_CHG1_CH15_Pos       PPI_CHG_CH15_Pos           
+#define PPI_CHG1_CH15_Msk       PPI_CHG_CH15_Msk           
+#define PPI_CHG1_CH15_Excluded  PPI_CHG_CH15_Excluded       
+#define PPI_CHG1_CH15_Included  PPI_CHG_CH15_Included      
+#define PPI_CHG1_CH14_Pos       PPI_CHG_CH14_Pos           
+#define PPI_CHG1_CH14_Msk       PPI_CHG_CH14_Msk            
+#define PPI_CHG1_CH14_Excluded  PPI_CHG_CH14_Excluded      
+#define PPI_CHG1_CH14_Included  PPI_CHG_CH14_Included       
+#define PPI_CHG1_CH13_Pos       PPI_CHG_CH13_Pos           
+#define PPI_CHG1_CH13_Msk       PPI_CHG_CH13_Msk            
+#define PPI_CHG1_CH13_Excluded  PPI_CHG_CH13_Excluded      
+#define PPI_CHG1_CH13_Included  PPI_CHG_CH13_Included      
+#define PPI_CHG1_CH12_Pos       PPI_CHG_CH12_Pos            
+#define PPI_CHG1_CH12_Msk       PPI_CHG_CH12_Msk           
+#define PPI_CHG1_CH12_Excluded  PPI_CHG_CH12_Excluded      
+#define PPI_CHG1_CH12_Included  PPI_CHG_CH12_Included      
+#define PPI_CHG1_CH11_Pos       PPI_CHG_CH11_Pos            
+#define PPI_CHG1_CH11_Msk       PPI_CHG_CH11_Msk           
+#define PPI_CHG1_CH11_Excluded  PPI_CHG_CH11_Excluded      
+#define PPI_CHG1_CH11_Included  PPI_CHG_CH11_Included      
+#define PPI_CHG1_CH10_Pos       PPI_CHG_CH10_Pos           
+#define PPI_CHG1_CH10_Msk       PPI_CHG_CH10_Msk            
+#define PPI_CHG1_CH10_Excluded  PPI_CHG_CH10_Excluded      
+#define PPI_CHG1_CH10_Included  PPI_CHG_CH10_Included      
+#define PPI_CHG1_CH9_Pos        PPI_CHG_CH9_Pos            
+#define PPI_CHG1_CH9_Msk        PPI_CHG_CH9_Msk            
+#define PPI_CHG1_CH9_Excluded   PPI_CHG_CH9_Excluded       
+#define PPI_CHG1_CH9_Included   PPI_CHG_CH9_Included       
+#define PPI_CHG1_CH8_Pos        PPI_CHG_CH8_Pos            
+#define PPI_CHG1_CH8_Msk        PPI_CHG_CH8_Msk            
+#define PPI_CHG1_CH8_Excluded   PPI_CHG_CH8_Excluded       
+#define PPI_CHG1_CH8_Included   PPI_CHG_CH8_Included       
+#define PPI_CHG1_CH7_Pos        PPI_CHG_CH7_Pos             
+#define PPI_CHG1_CH7_Msk        PPI_CHG_CH7_Msk            
+#define PPI_CHG1_CH7_Excluded   PPI_CHG_CH7_Excluded        
+#define PPI_CHG1_CH7_Included   PPI_CHG_CH7_Included       
+#define PPI_CHG1_CH6_Pos        PPI_CHG_CH6_Pos             
+#define PPI_CHG1_CH6_Msk        PPI_CHG_CH6_Msk            
+#define PPI_CHG1_CH6_Excluded   PPI_CHG_CH6_Excluded       
+#define PPI_CHG1_CH6_Included   PPI_CHG_CH6_Included       
+#define PPI_CHG1_CH5_Pos        PPI_CHG_CH5_Pos             
+#define PPI_CHG1_CH5_Msk        PPI_CHG_CH5_Msk             
+#define PPI_CHG1_CH5_Excluded   PPI_CHG_CH5_Excluded       
+#define PPI_CHG1_CH5_Included   PPI_CHG_CH5_Included        
+#define PPI_CHG1_CH4_Pos        PPI_CHG_CH4_Pos             
+#define PPI_CHG1_CH4_Msk        PPI_CHG_CH4_Msk             
+#define PPI_CHG1_CH4_Excluded   PPI_CHG_CH4_Excluded        
+#define PPI_CHG1_CH4_Included   PPI_CHG_CH4_Included        
+#define PPI_CHG1_CH3_Pos        PPI_CHG_CH3_Pos            
+#define PPI_CHG1_CH3_Msk        PPI_CHG_CH3_Msk             
+#define PPI_CHG1_CH3_Excluded   PPI_CHG_CH3_Excluded        
+#define PPI_CHG1_CH3_Included   PPI_CHG_CH3_Included       
+#define PPI_CHG1_CH2_Pos        PPI_CHG_CH2_Pos            
+#define PPI_CHG1_CH2_Msk        PPI_CHG_CH2_Msk             
+#define PPI_CHG1_CH2_Excluded   PPI_CHG_CH2_Excluded        
+#define PPI_CHG1_CH2_Included   PPI_CHG_CH2_Included        
+#define PPI_CHG1_CH1_Pos        PPI_CHG_CH1_Pos             
+#define PPI_CHG1_CH1_Msk        PPI_CHG_CH1_Msk            
+#define PPI_CHG1_CH1_Excluded   PPI_CHG_CH1_Excluded        
+#define PPI_CHG1_CH1_Included   PPI_CHG_CH1_Included       
+#define PPI_CHG1_CH0_Pos        PPI_CHG_CH0_Pos             
+#define PPI_CHG1_CH0_Msk        PPI_CHG_CH0_Msk            
+#define PPI_CHG1_CH0_Excluded   PPI_CHG_CH0_Excluded       
+#define PPI_CHG1_CH0_Included   PPI_CHG_CH0_Included       
+#define PPI_CHG2_CH15_Pos       PPI_CHG_CH15_Pos           
+#define PPI_CHG2_CH15_Msk       PPI_CHG_CH15_Msk            
+#define PPI_CHG2_CH15_Excluded  PPI_CHG_CH15_Excluded      
+#define PPI_CHG2_CH15_Included  PPI_CHG_CH15_Included      
+#define PPI_CHG2_CH14_Pos       PPI_CHG_CH14_Pos           
+#define PPI_CHG2_CH14_Msk       PPI_CHG_CH14_Msk           
+#define PPI_CHG2_CH14_Excluded  PPI_CHG_CH14_Excluded       
+#define PPI_CHG2_CH14_Included  PPI_CHG_CH14_Included      
+#define PPI_CHG2_CH13_Pos       PPI_CHG_CH13_Pos           
+#define PPI_CHG2_CH13_Msk       PPI_CHG_CH13_Msk            
+#define PPI_CHG2_CH13_Excluded  PPI_CHG_CH13_Excluded       
+#define PPI_CHG2_CH13_Included  PPI_CHG_CH13_Included      
+#define PPI_CHG2_CH12_Pos       PPI_CHG_CH12_Pos            
+#define PPI_CHG2_CH12_Msk       PPI_CHG_CH12_Msk            
+#define PPI_CHG2_CH12_Excluded  PPI_CHG_CH12_Excluded      
+#define PPI_CHG2_CH12_Included  PPI_CHG_CH12_Included       
+#define PPI_CHG2_CH11_Pos       PPI_CHG_CH11_Pos           
+#define PPI_CHG2_CH11_Msk       PPI_CHG_CH11_Msk           
+#define PPI_CHG2_CH11_Excluded  PPI_CHG_CH11_Excluded       
+#define PPI_CHG2_CH11_Included  PPI_CHG_CH11_Included       
+#define PPI_CHG2_CH10_Pos       PPI_CHG_CH10_Pos            
+#define PPI_CHG2_CH10_Msk       PPI_CHG_CH10_Msk            
+#define PPI_CHG2_CH10_Excluded  PPI_CHG_CH10_Excluded      
+#define PPI_CHG2_CH10_Included  PPI_CHG_CH10_Included      
+#define PPI_CHG2_CH9_Pos        PPI_CHG_CH9_Pos            
+#define PPI_CHG2_CH9_Msk        PPI_CHG_CH9_Msk            
+#define PPI_CHG2_CH9_Excluded   PPI_CHG_CH9_Excluded        
+#define PPI_CHG2_CH9_Included   PPI_CHG_CH9_Included       
+#define PPI_CHG2_CH8_Pos        PPI_CHG_CH8_Pos            
+#define PPI_CHG2_CH8_Msk        PPI_CHG_CH8_Msk            
+#define PPI_CHG2_CH8_Excluded   PPI_CHG_CH8_Excluded       
+#define PPI_CHG2_CH8_Included   PPI_CHG_CH8_Included        
+#define PPI_CHG2_CH7_Pos        PPI_CHG_CH7_Pos            
+#define PPI_CHG2_CH7_Msk        PPI_CHG_CH7_Msk            
+#define PPI_CHG2_CH7_Excluded   PPI_CHG_CH7_Excluded       
+#define PPI_CHG2_CH7_Included   PPI_CHG_CH7_Included       
+#define PPI_CHG2_CH6_Pos        PPI_CHG_CH6_Pos            
+#define PPI_CHG2_CH6_Msk        PPI_CHG_CH6_Msk            
+#define PPI_CHG2_CH6_Excluded   PPI_CHG_CH6_Excluded       
+#define PPI_CHG2_CH6_Included   PPI_CHG_CH6_Included       
+#define PPI_CHG2_CH5_Pos        PPI_CHG_CH5_Pos            
+#define PPI_CHG2_CH5_Msk        PPI_CHG_CH5_Msk            
+#define PPI_CHG2_CH5_Excluded   PPI_CHG_CH5_Excluded       
+#define PPI_CHG2_CH5_Included   PPI_CHG_CH5_Included        
+#define PPI_CHG2_CH4_Pos        PPI_CHG_CH4_Pos             
+#define PPI_CHG2_CH4_Msk        PPI_CHG_CH4_Msk             
+#define PPI_CHG2_CH4_Excluded   PPI_CHG_CH4_Excluded        
+#define PPI_CHG2_CH4_Included   PPI_CHG_CH4_Included       
+#define PPI_CHG2_CH3_Pos        PPI_CHG_CH3_Pos            
+#define PPI_CHG2_CH3_Msk        PPI_CHG_CH3_Msk            
+#define PPI_CHG2_CH3_Excluded   PPI_CHG_CH3_Excluded       
+#define PPI_CHG2_CH3_Included   PPI_CHG_CH3_Included       
+#define PPI_CHG2_CH2_Pos        PPI_CHG_CH2_Pos            
+#define PPI_CHG2_CH2_Msk        PPI_CHG_CH2_Msk           
+#define PPI_CHG2_CH2_Excluded   PPI_CHG_CH2_Excluded       
+#define PPI_CHG2_CH2_Included   PPI_CHG_CH2_Included       
+#define PPI_CHG2_CH1_Pos        PPI_CHG_CH1_Pos             
+#define PPI_CHG2_CH1_Msk        PPI_CHG_CH1_Msk             
+#define PPI_CHG2_CH1_Excluded   PPI_CHG_CH1_Excluded       
+#define PPI_CHG2_CH1_Included   PPI_CHG_CH1_Included       
+#define PPI_CHG2_CH0_Pos        PPI_CHG_CH0_Pos            
+#define PPI_CHG2_CH0_Msk        PPI_CHG_CH0_Msk            
+#define PPI_CHG2_CH0_Excluded   PPI_CHG_CH0_Excluded       
+#define PPI_CHG2_CH0_Included   PPI_CHG_CH0_Included        
+#define PPI_CHG3_CH15_Pos       PPI_CHG_CH15_Pos           
+#define PPI_CHG3_CH15_Msk       PPI_CHG_CH15_Msk           
+#define PPI_CHG3_CH15_Excluded  PPI_CHG_CH15_Excluded     
+#define PPI_CHG3_CH15_Included  PPI_CHG_CH15_Included      
+#define PPI_CHG3_CH14_Pos       PPI_CHG_CH14_Pos          
+#define PPI_CHG3_CH14_Msk       PPI_CHG_CH14_Msk           
+#define PPI_CHG3_CH14_Excluded  PPI_CHG_CH14_Excluded      
+#define PPI_CHG3_CH14_Included  PPI_CHG_CH14_Included       
+#define PPI_CHG3_CH13_Pos       PPI_CHG_CH13_Pos           
+#define PPI_CHG3_CH13_Msk       PPI_CHG_CH13_Msk            
+#define PPI_CHG3_CH13_Excluded  PPI_CHG_CH13_Excluded      
+#define PPI_CHG3_CH13_Included  PPI_CHG_CH13_Included      
+#define PPI_CHG3_CH12_Pos       PPI_CHG_CH12_Pos            
+#define PPI_CHG3_CH12_Msk       PPI_CHG_CH12_Msk            
+#define PPI_CHG3_CH12_Excluded  PPI_CHG_CH12_Excluded       
+#define PPI_CHG3_CH12_Included  PPI_CHG_CH12_Included       
+#define PPI_CHG3_CH11_Pos       PPI_CHG_CH11_Pos            
+#define PPI_CHG3_CH11_Msk       PPI_CHG_CH11_Msk            
+#define PPI_CHG3_CH11_Excluded  PPI_CHG_CH11_Excluded      
+#define PPI_CHG3_CH11_Included  PPI_CHG_CH11_Included       
+#define PPI_CHG3_CH10_Pos       PPI_CHG_CH10_Pos            
+#define PPI_CHG3_CH10_Msk       PPI_CHG_CH10_Msk            
+#define PPI_CHG3_CH10_Excluded  PPI_CHG_CH10_Excluded      
+#define PPI_CHG3_CH10_Included  PPI_CHG_CH10_Included      
+#define PPI_CHG3_CH9_Pos        PPI_CHG_CH9_Pos            
+#define PPI_CHG3_CH9_Msk        PPI_CHG_CH9_Msk            
+#define PPI_CHG3_CH9_Excluded   PPI_CHG_CH9_Excluded       
+#define PPI_CHG3_CH9_Included   PPI_CHG_CH9_Included       
+#define PPI_CHG3_CH8_Pos        PPI_CHG_CH8_Pos            
+#define PPI_CHG3_CH8_Msk        PPI_CHG_CH8_Msk             
+#define PPI_CHG3_CH8_Excluded   PPI_CHG_CH8_Excluded       
+#define PPI_CHG3_CH8_Included   PPI_CHG_CH8_Included       
+#define PPI_CHG3_CH7_Pos        PPI_CHG_CH7_Pos             
+#define PPI_CHG3_CH7_Msk        PPI_CHG_CH7_Msk            
+#define PPI_CHG3_CH7_Excluded   PPI_CHG_CH7_Excluded        
+#define PPI_CHG3_CH7_Included   PPI_CHG_CH7_Included       
+#define PPI_CHG3_CH6_Pos        PPI_CHG_CH6_Pos             
+#define PPI_CHG3_CH6_Msk        PPI_CHG_CH6_Msk             
+#define PPI_CHG3_CH6_Excluded   PPI_CHG_CH6_Excluded       
+#define PPI_CHG3_CH6_Included   PPI_CHG_CH6_Included        
+#define PPI_CHG3_CH5_Pos        PPI_CHG_CH5_Pos             
+#define PPI_CHG3_CH5_Msk        PPI_CHG_CH5_Msk             
+#define PPI_CHG3_CH5_Excluded   PPI_CHG_CH5_Excluded        
+#define PPI_CHG3_CH5_Included   PPI_CHG_CH5_Included       
+#define PPI_CHG3_CH4_Pos        PPI_CHG_CH4_Pos             
+#define PPI_CHG3_CH4_Msk        PPI_CHG_CH4_Msk            
+#define PPI_CHG3_CH4_Excluded   PPI_CHG_CH4_Excluded        
+#define PPI_CHG3_CH4_Included   PPI_CHG_CH4_Included        
+#define PPI_CHG3_CH3_Pos        PPI_CHG_CH3_Pos             
+#define PPI_CHG3_CH3_Msk        PPI_CHG_CH3_Msk            
+#define PPI_CHG3_CH3_Excluded   PPI_CHG_CH3_Excluded        
+#define PPI_CHG3_CH3_Included   PPI_CHG_CH3_Included        
+#define PPI_CHG3_CH2_Pos        PPI_CHG_CH2_Pos             
+#define PPI_CHG3_CH2_Msk        PPI_CHG_CH2_Msk             
+#define PPI_CHG3_CH2_Excluded   PPI_CHG_CH2_Excluded        
+#define PPI_CHG3_CH2_Included   PPI_CHG_CH2_Included       
+#define PPI_CHG3_CH1_Pos        PPI_CHG_CH1_Pos             
+#define PPI_CHG3_CH1_Msk        PPI_CHG_CH1_Msk             
+#define PPI_CHG3_CH1_Excluded   PPI_CHG_CH1_Excluded        
+#define PPI_CHG3_CH1_Included   PPI_CHG_CH1_Included        
+#define PPI_CHG3_CH0_Pos        PPI_CHG_CH0_Pos             
+#define PPI_CHG3_CH0_Msk        PPI_CHG_CH0_Msk             
+#define PPI_CHG3_CH0_Excluded   PPI_CHG_CH0_Excluded        
+#define PPI_CHG3_CH0_Included   PPI_CHG_CH0_Included        
+
+
+
+/*lint --flb "Leave library region" */
+
+#endif /* NRF51_DEPRECATED_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51_to_nrf52.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,960 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+#ifndef NRF51_TO_NRF52_H
+#define NRF51_TO_NRF52_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices.
+ * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the
+ * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
+ * from the nrf51_deprecated.h file. */
+
+
+/* IRQ */
+/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */
+#define UART0_IRQHandler        UARTE0_UART0_IRQHandler
+#define SPI0_TWI0_IRQHandler    SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+#define SPI1_TWI1_IRQHandler    SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+#define ADC_IRQHandler          SAADC_IRQHandler
+#define LPCOMP_IRQHandler       COMP_LPCOMP_IRQHandler
+#define SWI0_IRQHandler         SWI0_EGU0_IRQHandler
+#define SWI1_IRQHandler         SWI1_EGU1_IRQHandler
+#define SWI2_IRQHandler         SWI2_EGU2_IRQHandler
+#define SWI3_IRQHandler         SWI3_EGU3_IRQHandler
+#define SWI4_IRQHandler         SWI4_EGU4_IRQHandler
+#define SWI5_IRQHandler         SWI5_EGU5_IRQHandler
+
+#define UART0_IRQn              UARTE0_UART0_IRQn
+#define SPI0_TWI0_IRQn          SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
+#define SPI1_TWI1_IRQn          SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
+#define ADC_IRQn                SAADC_IRQn
+#define LPCOMP_IRQn             COMP_LPCOMP_IRQn
+#define SWI0_IRQn               SWI0_EGU0_IRQn
+#define SWI1_IRQn               SWI1_EGU1_IRQn
+#define SWI2_IRQn               SWI2_EGU2_IRQn
+#define SWI3_IRQn               SWI3_EGU3_IRQn
+#define SWI4_IRQn               SWI4_EGU4_IRQn
+#define SWI5_IRQn               SWI5_EGU5_IRQn
+
+
+/* UICR */
+/* Register RBPCONF was renamed to APPROTECT. */
+#define RBPCONF     APPROTECT
+
+#define UICR_RBPCONF_PALL_Pos           UICR_APPROTECT_PALL_Pos
+#define UICR_RBPCONF_PALL_Msk           UICR_APPROTECT_PALL_Msk
+#define UICR_RBPCONF_PALL_Enabled       UICR_APPROTECT_PALL_Enabled
+#define UICR_RBPCONF_PALL_Disabled      UICR_APPROTECT_PALL_Disabled
+
+
+/* GPIO */
+/* GPIO port was renamed to P0. */
+#define NRF_GPIO        NRF_P0
+#define NRF_GPIO_BASE   NRF_P0_BASE
+
+
+/* QDEC */
+/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */
+#define PSELLED     PSEL.LED
+#define PSELA       PSEL.A
+#define PSELB       PSEL.B
+
+
+/* SPIS */
+/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */
+#define PSELSCK       PSEL.SCK
+#define PSELMISO      PSEL.MISO
+#define PSELMOSI      PSEL.MOSI
+#define PSELCSN       PSEL.CSN
+
+/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */
+#define RXDPTR        RXD.PTR
+#define MAXRX         RXD.MAXCNT
+#define AMOUNTRX      RXD.AMOUNT
+
+#define SPIS_MAXRX_MAXRX_Pos        SPIS_RXD_MAXCNT_MAXCNT_Pos
+#define SPIS_MAXRX_MAXRX_Msk        SPIS_RXD_MAXCNT_MAXCNT_Msk
+
+#define SPIS_AMOUNTRX_AMOUNTRX_Pos  SPIS_RXD_AMOUNT_AMOUNT_Pos
+#define SPIS_AMOUNTRX_AMOUNTRX_Msk  SPIS_RXD_AMOUNT_AMOUNT_Msk
+
+/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */
+#define TXDPTR        TXD.PTR
+#define MAXTX         TXD.MAXCNT
+#define AMOUNTTX      TXD.AMOUNT
+
+#define SPIS_MAXTX_MAXTX_Pos        SPIS_TXD_MAXCNT_MAXCNT_Pos
+#define SPIS_MAXTX_MAXTX_Msk        SPIS_TXD_MAXCNT_MAXCNT_Msk
+
+#define SPIS_AMOUNTTX_AMOUNTTX_Pos  SPIS_TXD_AMOUNT_AMOUNT_Pos
+#define SPIS_AMOUNTTX_AMOUNTTX_Msk  SPIS_TXD_AMOUNT_AMOUNT_Msk
+
+
+/* MPU */
+/* Part of MPU module was renamed BPROT, while the rest was eliminated. */
+#define NRF_MPU     NRF_BPROT
+
+/* Register DISABLEINDEBUG macros were affected. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos       BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk       BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled   BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled  BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled
+
+/* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */
+#define PROTENSET0  CONFIG0
+#define PROTENSET1  CONFIG1
+
+#define MPU_PROTENSET1_PROTREG63_Pos        BPROT_CONFIG1_REGION63_Pos
+#define MPU_PROTENSET1_PROTREG63_Msk        BPROT_CONFIG1_REGION63_Msk
+#define MPU_PROTENSET1_PROTREG63_Disabled   BPROT_CONFIG1_REGION63_Disabled
+#define MPU_PROTENSET1_PROTREG63_Enabled    BPROT_CONFIG1_REGION63_Enabled
+#define MPU_PROTENSET1_PROTREG63_Set        BPROT_CONFIG1_REGION63_Enabled
+
+#define MPU_PROTENSET1_PROTREG62_Pos        BPROT_CONFIG1_REGION62_Pos
+#define MPU_PROTENSET1_PROTREG62_Msk        BPROT_CONFIG1_REGION62_Msk
+#define MPU_PROTENSET1_PROTREG62_Disabled   BPROT_CONFIG1_REGION62_Disabled
+#define MPU_PROTENSET1_PROTREG62_Enabled    BPROT_CONFIG1_REGION62_Enabled
+#define MPU_PROTENSET1_PROTREG62_Set        BPROT_CONFIG1_REGION62_Enabled
+
+#define MPU_PROTENSET1_PROTREG61_Pos        BPROT_CONFIG1_REGION61_Pos
+#define MPU_PROTENSET1_PROTREG61_Msk        BPROT_CONFIG1_REGION61_Msk
+#define MPU_PROTENSET1_PROTREG61_Disabled   BPROT_CONFIG1_REGION61_Disabled
+#define MPU_PROTENSET1_PROTREG61_Enabled    BPROT_CONFIG1_REGION61_Enabled
+#define MPU_PROTENSET1_PROTREG61_Set        BPROT_CONFIG1_REGION61_Enabled
+
+#define MPU_PROTENSET1_PROTREG60_Pos        BPROT_CONFIG1_REGION60_Pos
+#define MPU_PROTENSET1_PROTREG60_Msk        BPROT_CONFIG1_REGION60_Msk
+#define MPU_PROTENSET1_PROTREG60_Disabled   BPROT_CONFIG1_REGION60_Disabled
+#define MPU_PROTENSET1_PROTREG60_Enabled    BPROT_CONFIG1_REGION60_Enabled
+#define MPU_PROTENSET1_PROTREG60_Set        BPROT_CONFIG1_REGION60_Enabled
+
+#define MPU_PROTENSET1_PROTREG59_Pos        BPROT_CONFIG1_REGION59_Pos
+#define MPU_PROTENSET1_PROTREG59_Msk        BPROT_CONFIG1_REGION59_Msk
+#define MPU_PROTENSET1_PROTREG59_Disabled   BPROT_CONFIG1_REGION59_Disabled
+#define MPU_PROTENSET1_PROTREG59_Enabled    BPROT_CONFIG1_REGION59_Enabled
+#define MPU_PROTENSET1_PROTREG59_Set        BPROT_CONFIG1_REGION59_Enabled
+
+#define MPU_PROTENSET1_PROTREG58_Pos        BPROT_CONFIG1_REGION58_Pos
+#define MPU_PROTENSET1_PROTREG58_Msk        BPROT_CONFIG1_REGION58_Msk
+#define MPU_PROTENSET1_PROTREG58_Disabled   BPROT_CONFIG1_REGION58_Disabled
+#define MPU_PROTENSET1_PROTREG58_Enabled    BPROT_CONFIG1_REGION58_Enabled
+#define MPU_PROTENSET1_PROTREG58_Set        BPROT_CONFIG1_REGION58_Enabled
+
+#define MPU_PROTENSET1_PROTREG57_Pos        BPROT_CONFIG1_REGION57_Pos
+#define MPU_PROTENSET1_PROTREG57_Msk        BPROT_CONFIG1_REGION57_Msk
+#define MPU_PROTENSET1_PROTREG57_Disabled   BPROT_CONFIG1_REGION57_Disabled
+#define MPU_PROTENSET1_PROTREG57_Enabled    BPROT_CONFIG1_REGION57_Enabled
+#define MPU_PROTENSET1_PROTREG57_Set        BPROT_CONFIG1_REGION57_Enabled
+
+#define MPU_PROTENSET1_PROTREG56_Pos        BPROT_CONFIG1_REGION56_Pos
+#define MPU_PROTENSET1_PROTREG56_Msk        BPROT_CONFIG1_REGION56_Msk
+#define MPU_PROTENSET1_PROTREG56_Disabled   BPROT_CONFIG1_REGION56_Disabled
+#define MPU_PROTENSET1_PROTREG56_Enabled    BPROT_CONFIG1_REGION56_Enabled
+#define MPU_PROTENSET1_PROTREG56_Set        BPROT_CONFIG1_REGION56_Enabled
+
+#define MPU_PROTENSET1_PROTREG55_Pos        BPROT_CONFIG1_REGION55_Pos
+#define MPU_PROTENSET1_PROTREG55_Msk        BPROT_CONFIG1_REGION55_Msk
+#define MPU_PROTENSET1_PROTREG55_Disabled   BPROT_CONFIG1_REGION55_Disabled
+#define MPU_PROTENSET1_PROTREG55_Enabled    BPROT_CONFIG1_REGION55_Enabled
+#define MPU_PROTENSET1_PROTREG55_Set        BPROT_CONFIG1_REGION55_Enabled
+
+#define MPU_PROTENSET1_PROTREG54_Pos        BPROT_CONFIG1_REGION54_Pos
+#define MPU_PROTENSET1_PROTREG54_Msk        BPROT_CONFIG1_REGION54_Msk
+#define MPU_PROTENSET1_PROTREG54_Disabled   BPROT_CONFIG1_REGION54_Disabled
+#define MPU_PROTENSET1_PROTREG54_Enabled    BPROT_CONFIG1_REGION54_Enabled
+#define MPU_PROTENSET1_PROTREG54_Set        BPROT_CONFIG1_REGION54_Enabled
+
+#define MPU_PROTENSET1_PROTREG53_Pos        BPROT_CONFIG1_REGION53_Pos
+#define MPU_PROTENSET1_PROTREG53_Msk        BPROT_CONFIG1_REGION53_Msk
+#define MPU_PROTENSET1_PROTREG53_Disabled   BPROT_CONFIG1_REGION53_Disabled
+#define MPU_PROTENSET1_PROTREG53_Enabled    BPROT_CONFIG1_REGION53_Enabled
+#define MPU_PROTENSET1_PROTREG53_Set        BPROT_CONFIG1_REGION53_Enabled
+
+#define MPU_PROTENSET1_PROTREG52_Pos        BPROT_CONFIG1_REGION52_Pos
+#define MPU_PROTENSET1_PROTREG52_Msk        BPROT_CONFIG1_REGION52_Msk
+#define MPU_PROTENSET1_PROTREG52_Disabled   BPROT_CONFIG1_REGION52_Disabled
+#define MPU_PROTENSET1_PROTREG52_Enabled    BPROT_CONFIG1_REGION52_Enabled
+#define MPU_PROTENSET1_PROTREG52_Set        BPROT_CONFIG1_REGION52_Enabled
+
+#define MPU_PROTENSET1_PROTREG51_Pos        BPROT_CONFIG1_REGION51_Pos
+#define MPU_PROTENSET1_PROTREG51_Msk        BPROT_CONFIG1_REGION51_Msk
+#define MPU_PROTENSET1_PROTREG51_Disabled   BPROT_CONFIG1_REGION51_Disabled
+#define MPU_PROTENSET1_PROTREG51_Enabled    BPROT_CONFIG1_REGION51_Enabled
+#define MPU_PROTENSET1_PROTREG51_Set        BPROT_CONFIG1_REGION51_Enabled
+
+#define MPU_PROTENSET1_PROTREG50_Pos        BPROT_CONFIG1_REGION50_Pos
+#define MPU_PROTENSET1_PROTREG50_Msk        BPROT_CONFIG1_REGION50_Msk
+#define MPU_PROTENSET1_PROTREG50_Disabled   BPROT_CONFIG1_REGION50_Disabled
+#define MPU_PROTENSET1_PROTREG50_Enabled    BPROT_CONFIG1_REGION50_Enabled
+#define MPU_PROTENSET1_PROTREG50_Set        BPROT_CONFIG1_REGION50_Enabled
+
+#define MPU_PROTENSET1_PROTREG49_Pos        BPROT_CONFIG1_REGION49_Pos
+#define MPU_PROTENSET1_PROTREG49_Msk        BPROT_CONFIG1_REGION49_Msk
+#define MPU_PROTENSET1_PROTREG49_Disabled   BPROT_CONFIG1_REGION49_Disabled
+#define MPU_PROTENSET1_PROTREG49_Enabled    BPROT_CONFIG1_REGION49_Enabled
+#define MPU_PROTENSET1_PROTREG49_Set        BPROT_CONFIG1_REGION49_Enabled
+
+#define MPU_PROTENSET1_PROTREG48_Pos        BPROT_CONFIG1_REGION48_Pos
+#define MPU_PROTENSET1_PROTREG48_Msk        BPROT_CONFIG1_REGION48_Msk
+#define MPU_PROTENSET1_PROTREG48_Disabled   BPROT_CONFIG1_REGION48_Disabled
+#define MPU_PROTENSET1_PROTREG48_Enabled    BPROT_CONFIG1_REGION48_Enabled
+#define MPU_PROTENSET1_PROTREG48_Set        BPROT_CONFIG1_REGION48_Enabled
+
+#define MPU_PROTENSET1_PROTREG47_Pos        BPROT_CONFIG1_REGION47_Pos
+#define MPU_PROTENSET1_PROTREG47_Msk        BPROT_CONFIG1_REGION47_Msk
+#define MPU_PROTENSET1_PROTREG47_Disabled   BPROT_CONFIG1_REGION47_Disabled
+#define MPU_PROTENSET1_PROTREG47_Enabled    BPROT_CONFIG1_REGION47_Enabled
+#define MPU_PROTENSET1_PROTREG47_Set        BPROT_CONFIG1_REGION47_Enabled
+
+#define MPU_PROTENSET1_PROTREG46_Pos        BPROT_CONFIG1_REGION46_Pos
+#define MPU_PROTENSET1_PROTREG46_Msk        BPROT_CONFIG1_REGION46_Msk
+#define MPU_PROTENSET1_PROTREG46_Disabled   BPROT_CONFIG1_REGION46_Disabled
+#define MPU_PROTENSET1_PROTREG46_Enabled    BPROT_CONFIG1_REGION46_Enabled
+#define MPU_PROTENSET1_PROTREG46_Set        BPROT_CONFIG1_REGION46_Enabled
+
+#define MPU_PROTENSET1_PROTREG45_Pos        BPROT_CONFIG1_REGION45_Pos
+#define MPU_PROTENSET1_PROTREG45_Msk        BPROT_CONFIG1_REGION45_Msk
+#define MPU_PROTENSET1_PROTREG45_Disabled   BPROT_CONFIG1_REGION45_Disabled
+#define MPU_PROTENSET1_PROTREG45_Enabled    BPROT_CONFIG1_REGION45_Enabled
+#define MPU_PROTENSET1_PROTREG45_Set        BPROT_CONFIG1_REGION45_Enabled
+
+#define MPU_PROTENSET1_PROTREG44_Pos        BPROT_CONFIG1_REGION44_Pos
+#define MPU_PROTENSET1_PROTREG44_Msk        BPROT_CONFIG1_REGION44_Msk
+#define MPU_PROTENSET1_PROTREG44_Disabled   BPROT_CONFIG1_REGION44_Disabled
+#define MPU_PROTENSET1_PROTREG44_Enabled    BPROT_CONFIG1_REGION44_Enabled
+#define MPU_PROTENSET1_PROTREG44_Set        BPROT_CONFIG1_REGION44_Enabled
+
+#define MPU_PROTENSET1_PROTREG43_Pos        BPROT_CONFIG1_REGION43_Pos
+#define MPU_PROTENSET1_PROTREG43_Msk        BPROT_CONFIG1_REGION43_Msk
+#define MPU_PROTENSET1_PROTREG43_Disabled   BPROT_CONFIG1_REGION43_Disabled
+#define MPU_PROTENSET1_PROTREG43_Enabled    BPROT_CONFIG1_REGION43_Enabled
+#define MPU_PROTENSET1_PROTREG43_Set        BPROT_CONFIG1_REGION43_Enabled
+
+#define MPU_PROTENSET1_PROTREG42_Pos        BPROT_CONFIG1_REGION42_Pos
+#define MPU_PROTENSET1_PROTREG42_Msk        BPROT_CONFIG1_REGION42_Msk
+#define MPU_PROTENSET1_PROTREG42_Disabled   BPROT_CONFIG1_REGION42_Disabled
+#define MPU_PROTENSET1_PROTREG42_Enabled    BPROT_CONFIG1_REGION42_Enabled
+#define MPU_PROTENSET1_PROTREG42_Set        BPROT_CONFIG1_REGION42_Enabled
+
+#define MPU_PROTENSET1_PROTREG41_Pos        BPROT_CONFIG1_REGION41_Pos
+#define MPU_PROTENSET1_PROTREG41_Msk        BPROT_CONFIG1_REGION41_Msk
+#define MPU_PROTENSET1_PROTREG41_Disabled   BPROT_CONFIG1_REGION41_Disabled
+#define MPU_PROTENSET1_PROTREG41_Enabled    BPROT_CONFIG1_REGION41_Enabled
+#define MPU_PROTENSET1_PROTREG41_Set        BPROT_CONFIG1_REGION41_Enabled
+
+#define MPU_PROTENSET1_PROTREG40_Pos        BPROT_CONFIG1_REGION40_Pos
+#define MPU_PROTENSET1_PROTREG40_Msk        BPROT_CONFIG1_REGION40_Msk
+#define MPU_PROTENSET1_PROTREG40_Disabled   BPROT_CONFIG1_REGION40_Disabled
+#define MPU_PROTENSET1_PROTREG40_Enabled    BPROT_CONFIG1_REGION40_Enabled
+#define MPU_PROTENSET1_PROTREG40_Set        BPROT_CONFIG1_REGION40_Enabled
+
+#define MPU_PROTENSET1_PROTREG39_Pos        BPROT_CONFIG1_REGION39_Pos
+#define MPU_PROTENSET1_PROTREG39_Msk        BPROT_CONFIG1_REGION39_Msk
+#define MPU_PROTENSET1_PROTREG39_Disabled   BPROT_CONFIG1_REGION39_Disabled
+#define MPU_PROTENSET1_PROTREG39_Enabled    BPROT_CONFIG1_REGION39_Enabled
+#define MPU_PROTENSET1_PROTREG39_Set        BPROT_CONFIG1_REGION39_Enabled
+
+#define MPU_PROTENSET1_PROTREG38_Pos        BPROT_CONFIG1_REGION38_Pos
+#define MPU_PROTENSET1_PROTREG38_Msk        BPROT_CONFIG1_REGION38_Msk
+#define MPU_PROTENSET1_PROTREG38_Disabled   BPROT_CONFIG1_REGION38_Disabled
+#define MPU_PROTENSET1_PROTREG38_Enabled    BPROT_CONFIG1_REGION38_Enabled
+#define MPU_PROTENSET1_PROTREG38_Set        BPROT_CONFIG1_REGION38_Enabled
+
+#define MPU_PROTENSET1_PROTREG37_Pos        BPROT_CONFIG1_REGION37_Pos
+#define MPU_PROTENSET1_PROTREG37_Msk        BPROT_CONFIG1_REGION37_Msk
+#define MPU_PROTENSET1_PROTREG37_Disabled   BPROT_CONFIG1_REGION37_Disabled
+#define MPU_PROTENSET1_PROTREG37_Enabled    BPROT_CONFIG1_REGION37_Enabled
+#define MPU_PROTENSET1_PROTREG37_Set        BPROT_CONFIG1_REGION37_Enabled
+
+#define MPU_PROTENSET1_PROTREG36_Pos        BPROT_CONFIG1_REGION36_Pos
+#define MPU_PROTENSET1_PROTREG36_Msk        BPROT_CONFIG1_REGION36_Msk
+#define MPU_PROTENSET1_PROTREG36_Disabled   BPROT_CONFIG1_REGION36_Disabled
+#define MPU_PROTENSET1_PROTREG36_Enabled    BPROT_CONFIG1_REGION36_Enabled
+#define MPU_PROTENSET1_PROTREG36_Set        BPROT_CONFIG1_REGION36_Enabled
+
+#define MPU_PROTENSET1_PROTREG35_Pos        BPROT_CONFIG1_REGION35_Pos
+#define MPU_PROTENSET1_PROTREG35_Msk        BPROT_CONFIG1_REGION35_Msk
+#define MPU_PROTENSET1_PROTREG35_Disabled   BPROT_CONFIG1_REGION35_Disabled
+#define MPU_PROTENSET1_PROTREG35_Enabled    BPROT_CONFIG1_REGION35_Enabled
+#define MPU_PROTENSET1_PROTREG35_Set        BPROT_CONFIG1_REGION35_Enabled
+
+#define MPU_PROTENSET1_PROTREG34_Pos        BPROT_CONFIG1_REGION34_Pos
+#define MPU_PROTENSET1_PROTREG34_Msk        BPROT_CONFIG1_REGION34_Msk
+#define MPU_PROTENSET1_PROTREG34_Disabled   BPROT_CONFIG1_REGION34_Disabled
+#define MPU_PROTENSET1_PROTREG34_Enabled    BPROT_CONFIG1_REGION34_Enabled
+#define MPU_PROTENSET1_PROTREG34_Set        BPROT_CONFIG1_REGION34_Enabled
+
+#define MPU_PROTENSET1_PROTREG33_Pos        BPROT_CONFIG1_REGION33_Pos
+#define MPU_PROTENSET1_PROTREG33_Msk        BPROT_CONFIG1_REGION33_Msk
+#define MPU_PROTENSET1_PROTREG33_Disabled   BPROT_CONFIG1_REGION33_Disabled
+#define MPU_PROTENSET1_PROTREG33_Enabled    BPROT_CONFIG1_REGION33_Enabled
+#define MPU_PROTENSET1_PROTREG33_Set        BPROT_CONFIG1_REGION33_Enabled
+
+#define MPU_PROTENSET1_PROTREG32_Pos        BPROT_CONFIG1_REGION32_Pos
+#define MPU_PROTENSET1_PROTREG32_Msk        BPROT_CONFIG1_REGION32_Msk
+#define MPU_PROTENSET1_PROTREG32_Disabled   BPROT_CONFIG1_REGION32_Disabled
+#define MPU_PROTENSET1_PROTREG32_Enabled    BPROT_CONFIG1_REGION32_Enabled
+#define MPU_PROTENSET1_PROTREG32_Set        BPROT_CONFIG1_REGION32_Enabled
+
+#define MPU_PROTENSET0_PROTREG31_Pos        BPROT_CONFIG0_REGION31_Pos
+#define MPU_PROTENSET0_PROTREG31_Msk        BPROT_CONFIG0_REGION31_Msk
+#define MPU_PROTENSET0_PROTREG31_Disabled   BPROT_CONFIG0_REGION31_Disabled
+#define MPU_PROTENSET0_PROTREG31_Enabled    BPROT_CONFIG0_REGION31_Enabled
+#define MPU_PROTENSET0_PROTREG31_Set        BPROT_CONFIG0_REGION31_Enabled
+
+#define MPU_PROTENSET0_PROTREG30_Pos        BPROT_CONFIG0_REGION30_Pos
+#define MPU_PROTENSET0_PROTREG30_Msk        BPROT_CONFIG0_REGION30_Msk
+#define MPU_PROTENSET0_PROTREG30_Disabled   BPROT_CONFIG0_REGION30_Disabled
+#define MPU_PROTENSET0_PROTREG30_Enabled    BPROT_CONFIG0_REGION30_Enabled
+#define MPU_PROTENSET0_PROTREG30_Set        BPROT_CONFIG0_REGION30_Enabled
+
+#define MPU_PROTENSET0_PROTREG29_Pos        BPROT_CONFIG0_REGION29_Pos
+#define MPU_PROTENSET0_PROTREG29_Msk        BPROT_CONFIG0_REGION29_Msk
+#define MPU_PROTENSET0_PROTREG29_Disabled   BPROT_CONFIG0_REGION29_Disabled
+#define MPU_PROTENSET0_PROTREG29_Enabled    BPROT_CONFIG0_REGION29_Enabled
+#define MPU_PROTENSET0_PROTREG29_Set        BPROT_CONFIG0_REGION29_Enabled
+
+#define MPU_PROTENSET0_PROTREG28_Pos        BPROT_CONFIG0_REGION28_Pos
+#define MPU_PROTENSET0_PROTREG28_Msk        BPROT_CONFIG0_REGION28_Msk
+#define MPU_PROTENSET0_PROTREG28_Disabled   BPROT_CONFIG0_REGION28_Disabled
+#define MPU_PROTENSET0_PROTREG28_Enabled    BPROT_CONFIG0_REGION28_Enabled
+#define MPU_PROTENSET0_PROTREG28_Set        BPROT_CONFIG0_REGION28_Enabled
+
+#define MPU_PROTENSET0_PROTREG27_Pos        BPROT_CONFIG0_REGION27_Pos
+#define MPU_PROTENSET0_PROTREG27_Msk        BPROT_CONFIG0_REGION27_Msk
+#define MPU_PROTENSET0_PROTREG27_Disabled   BPROT_CONFIG0_REGION27_Disabled
+#define MPU_PROTENSET0_PROTREG27_Enabled    BPROT_CONFIG0_REGION27_Enabled
+#define MPU_PROTENSET0_PROTREG27_Set        BPROT_CONFIG0_REGION27_Enabled
+
+#define MPU_PROTENSET0_PROTREG26_Pos        BPROT_CONFIG0_REGION26_Pos
+#define MPU_PROTENSET0_PROTREG26_Msk        BPROT_CONFIG0_REGION26_Msk
+#define MPU_PROTENSET0_PROTREG26_Disabled   BPROT_CONFIG0_REGION26_Disabled
+#define MPU_PROTENSET0_PROTREG26_Enabled    BPROT_CONFIG0_REGION26_Enabled
+#define MPU_PROTENSET0_PROTREG26_Set        BPROT_CONFIG0_REGION26_Enabled
+
+#define MPU_PROTENSET0_PROTREG25_Pos        BPROT_CONFIG0_REGION25_Pos
+#define MPU_PROTENSET0_PROTREG25_Msk        BPROT_CONFIG0_REGION25_Msk
+#define MPU_PROTENSET0_PROTREG25_Disabled   BPROT_CONFIG0_REGION25_Disabled
+#define MPU_PROTENSET0_PROTREG25_Enabled    BPROT_CONFIG0_REGION25_Enabled
+#define MPU_PROTENSET0_PROTREG25_Set        BPROT_CONFIG0_REGION25_Enabled
+
+#define MPU_PROTENSET0_PROTREG24_Pos        BPROT_CONFIG0_REGION24_Pos
+#define MPU_PROTENSET0_PROTREG24_Msk        BPROT_CONFIG0_REGION24_Msk
+#define MPU_PROTENSET0_PROTREG24_Disabled   BPROT_CONFIG0_REGION24_Disabled
+#define MPU_PROTENSET0_PROTREG24_Enabled    BPROT_CONFIG0_REGION24_Enabled
+#define MPU_PROTENSET0_PROTREG24_Set        BPROT_CONFIG0_REGION24_Enabled
+
+#define MPU_PROTENSET0_PROTREG23_Pos        BPROT_CONFIG0_REGION23_Pos
+#define MPU_PROTENSET0_PROTREG23_Msk        BPROT_CONFIG0_REGION23_Msk
+#define MPU_PROTENSET0_PROTREG23_Disabled   BPROT_CONFIG0_REGION23_Disabled
+#define MPU_PROTENSET0_PROTREG23_Enabled    BPROT_CONFIG0_REGION23_Enabled
+#define MPU_PROTENSET0_PROTREG23_Set        BPROT_CONFIG0_REGION23_Enabled
+
+#define MPU_PROTENSET0_PROTREG22_Pos        BPROT_CONFIG0_REGION22_Pos
+#define MPU_PROTENSET0_PROTREG22_Msk        BPROT_CONFIG0_REGION22_Msk
+#define MPU_PROTENSET0_PROTREG22_Disabled   BPROT_CONFIG0_REGION22_Disabled
+#define MPU_PROTENSET0_PROTREG22_Enabled    BPROT_CONFIG0_REGION22_Enabled
+#define MPU_PROTENSET0_PROTREG22_Set        BPROT_CONFIG0_REGION22_Enabled
+
+#define MPU_PROTENSET0_PROTREG21_Pos        BPROT_CONFIG0_REGION21_Pos
+#define MPU_PROTENSET0_PROTREG21_Msk        BPROT_CONFIG0_REGION21_Msk
+#define MPU_PROTENSET0_PROTREG21_Disabled   BPROT_CONFIG0_REGION21_Disabled
+#define MPU_PROTENSET0_PROTREG21_Enabled    BPROT_CONFIG0_REGION21_Enabled
+#define MPU_PROTENSET0_PROTREG21_Set        BPROT_CONFIG0_REGION21_Enabled
+
+#define MPU_PROTENSET0_PROTREG20_Pos        BPROT_CONFIG0_REGION20_Pos
+#define MPU_PROTENSET0_PROTREG20_Msk        BPROT_CONFIG0_REGION20_Msk
+#define MPU_PROTENSET0_PROTREG20_Disabled   BPROT_CONFIG0_REGION20_Disabled
+#define MPU_PROTENSET0_PROTREG20_Enabled    BPROT_CONFIG0_REGION20_Enabled
+#define MPU_PROTENSET0_PROTREG20_Set        BPROT_CONFIG0_REGION20_Enabled
+
+#define MPU_PROTENSET0_PROTREG19_Pos        BPROT_CONFIG0_REGION19_Pos
+#define MPU_PROTENSET0_PROTREG19_Msk        BPROT_CONFIG0_REGION19_Msk
+#define MPU_PROTENSET0_PROTREG19_Disabled   BPROT_CONFIG0_REGION19_Disabled
+#define MPU_PROTENSET0_PROTREG19_Enabled    BPROT_CONFIG0_REGION19_Enabled
+#define MPU_PROTENSET0_PROTREG19_Set        BPROT_CONFIG0_REGION19_Enabled
+
+#define MPU_PROTENSET0_PROTREG18_Pos        BPROT_CONFIG0_REGION18_Pos
+#define MPU_PROTENSET0_PROTREG18_Msk        BPROT_CONFIG0_REGION18_Msk
+#define MPU_PROTENSET0_PROTREG18_Disabled   BPROT_CONFIG0_REGION18_Disabled
+#define MPU_PROTENSET0_PROTREG18_Enabled    BPROT_CONFIG0_REGION18_Enabled
+#define MPU_PROTENSET0_PROTREG18_Set        BPROT_CONFIG0_REGION18_Enabled
+
+#define MPU_PROTENSET0_PROTREG17_Pos        BPROT_CONFIG0_REGION17_Pos
+#define MPU_PROTENSET0_PROTREG17_Msk        BPROT_CONFIG0_REGION17_Msk
+#define MPU_PROTENSET0_PROTREG17_Disabled   BPROT_CONFIG0_REGION17_Disabled
+#define MPU_PROTENSET0_PROTREG17_Enabled    BPROT_CONFIG0_REGION17_Enabled
+#define MPU_PROTENSET0_PROTREG17_Set        BPROT_CONFIG0_REGION17_Enabled
+
+#define MPU_PROTENSET0_PROTREG16_Pos        BPROT_CONFIG0_REGION16_Pos
+#define MPU_PROTENSET0_PROTREG16_Msk        BPROT_CONFIG0_REGION16_Msk
+#define MPU_PROTENSET0_PROTREG16_Disabled   BPROT_CONFIG0_REGION16_Disabled
+#define MPU_PROTENSET0_PROTREG16_Enabled    BPROT_CONFIG0_REGION16_Enabled
+#define MPU_PROTENSET0_PROTREG16_Set        BPROT_CONFIG0_REGION16_Enabled
+
+#define MPU_PROTENSET0_PROTREG15_Pos        BPROT_CONFIG0_REGION15_Pos
+#define MPU_PROTENSET0_PROTREG15_Msk        BPROT_CONFIG0_REGION15_Msk
+#define MPU_PROTENSET0_PROTREG15_Disabled   BPROT_CONFIG0_REGION15_Disabled
+#define MPU_PROTENSET0_PROTREG15_Enabled    BPROT_CONFIG0_REGION15_Enabled
+#define MPU_PROTENSET0_PROTREG15_Set        BPROT_CONFIG0_REGION15_Enabled
+
+#define MPU_PROTENSET0_PROTREG14_Pos        BPROT_CONFIG0_REGION14_Pos
+#define MPU_PROTENSET0_PROTREG14_Msk        BPROT_CONFIG0_REGION14_Msk
+#define MPU_PROTENSET0_PROTREG14_Disabled   BPROT_CONFIG0_REGION14_Disabled
+#define MPU_PROTENSET0_PROTREG14_Enabled    BPROT_CONFIG0_REGION14_Enabled
+#define MPU_PROTENSET0_PROTREG14_Set        BPROT_CONFIG0_REGION14_Enabled
+
+#define MPU_PROTENSET0_PROTREG13_Pos        BPROT_CONFIG0_REGION13_Pos
+#define MPU_PROTENSET0_PROTREG13_Msk        BPROT_CONFIG0_REGION13_Msk
+#define MPU_PROTENSET0_PROTREG13_Disabled   BPROT_CONFIG0_REGION13_Disabled
+#define MPU_PROTENSET0_PROTREG13_Enabled    BPROT_CONFIG0_REGION13_Enabled
+#define MPU_PROTENSET0_PROTREG13_Set        BPROT_CONFIG0_REGION13_Enabled
+
+#define MPU_PROTENSET0_PROTREG12_Pos        BPROT_CONFIG0_REGION12_Pos
+#define MPU_PROTENSET0_PROTREG12_Msk        BPROT_CONFIG0_REGION12_Msk
+#define MPU_PROTENSET0_PROTREG12_Disabled   BPROT_CONFIG0_REGION12_Disabled
+#define MPU_PROTENSET0_PROTREG12_Enabled    BPROT_CONFIG0_REGION12_Enabled
+#define MPU_PROTENSET0_PROTREG12_Set        BPROT_CONFIG0_REGION12_Enabled
+
+#define MPU_PROTENSET0_PROTREG11_Pos        BPROT_CONFIG0_REGION11_Pos
+#define MPU_PROTENSET0_PROTREG11_Msk        BPROT_CONFIG0_REGION11_Msk
+#define MPU_PROTENSET0_PROTREG11_Disabled   BPROT_CONFIG0_REGION11_Disabled
+#define MPU_PROTENSET0_PROTREG11_Enabled    BPROT_CONFIG0_REGION11_Enabled
+#define MPU_PROTENSET0_PROTREG11_Set        BPROT_CONFIG0_REGION11_Enabled
+
+#define MPU_PROTENSET0_PROTREG10_Pos        BPROT_CONFIG0_REGION10_Pos
+#define MPU_PROTENSET0_PROTREG10_Msk        BPROT_CONFIG0_REGION10_Msk
+#define MPU_PROTENSET0_PROTREG10_Disabled   BPROT_CONFIG0_REGION10_Disabled
+#define MPU_PROTENSET0_PROTREG10_Enabled    BPROT_CONFIG0_REGION10_Enabled
+#define MPU_PROTENSET0_PROTREG10_Set        BPROT_CONFIG0_REGION10_Enabled
+
+#define MPU_PROTENSET0_PROTREG9_Pos        BPROT_CONFIG0_REGION9_Pos
+#define MPU_PROTENSET0_PROTREG9_Msk        BPROT_CONFIG0_REGION9_Msk
+#define MPU_PROTENSET0_PROTREG9_Disabled   BPROT_CONFIG0_REGION9_Disabled
+#define MPU_PROTENSET0_PROTREG9_Enabled    BPROT_CONFIG0_REGION9_Enabled
+#define MPU_PROTENSET0_PROTREG9_Set        BPROT_CONFIG0_REGION9_Enabled
+
+#define MPU_PROTENSET0_PROTREG8_Pos        BPROT_CONFIG0_REGION8_Pos
+#define MPU_PROTENSET0_PROTREG8_Msk        BPROT_CONFIG0_REGION8_Msk
+#define MPU_PROTENSET0_PROTREG8_Disabled   BPROT_CONFIG0_REGION8_Disabled
+#define MPU_PROTENSET0_PROTREG8_Enabled    BPROT_CONFIG0_REGION8_Enabled
+#define MPU_PROTENSET0_PROTREG8_Set        BPROT_CONFIG0_REGION8_Enabled
+
+#define MPU_PROTENSET0_PROTREG7_Pos        BPROT_CONFIG0_REGION7_Pos
+#define MPU_PROTENSET0_PROTREG7_Msk        BPROT_CONFIG0_REGION7_Msk
+#define MPU_PROTENSET0_PROTREG7_Disabled   BPROT_CONFIG0_REGION7_Disabled
+#define MPU_PROTENSET0_PROTREG7_Enabled    BPROT_CONFIG0_REGION7_Enabled
+#define MPU_PROTENSET0_PROTREG7_Set        BPROT_CONFIG0_REGION7_Enabled
+
+#define MPU_PROTENSET0_PROTREG6_Pos        BPROT_CONFIG0_REGION6_Pos
+#define MPU_PROTENSET0_PROTREG6_Msk        BPROT_CONFIG0_REGION6_Msk
+#define MPU_PROTENSET0_PROTREG6_Disabled   BPROT_CONFIG0_REGION6_Disabled
+#define MPU_PROTENSET0_PROTREG6_Enabled    BPROT_CONFIG0_REGION6_Enabled
+#define MPU_PROTENSET0_PROTREG6_Set        BPROT_CONFIG0_REGION6_Enabled
+
+#define MPU_PROTENSET0_PROTREG5_Pos        BPROT_CONFIG0_REGION5_Pos
+#define MPU_PROTENSET0_PROTREG5_Msk        BPROT_CONFIG0_REGION5_Msk
+#define MPU_PROTENSET0_PROTREG5_Disabled   BPROT_CONFIG0_REGION5_Disabled
+#define MPU_PROTENSET0_PROTREG5_Enabled    BPROT_CONFIG0_REGION5_Enabled
+#define MPU_PROTENSET0_PROTREG5_Set        BPROT_CONFIG0_REGION5_Enabled
+
+#define MPU_PROTENSET0_PROTREG4_Pos        BPROT_CONFIG0_REGION4_Pos
+#define MPU_PROTENSET0_PROTREG4_Msk        BPROT_CONFIG0_REGION4_Msk
+#define MPU_PROTENSET0_PROTREG4_Disabled   BPROT_CONFIG0_REGION4_Disabled
+#define MPU_PROTENSET0_PROTREG4_Enabled    BPROT_CONFIG0_REGION4_Enabled
+#define MPU_PROTENSET0_PROTREG4_Set        BPROT_CONFIG0_REGION4_Enabled
+
+#define MPU_PROTENSET0_PROTREG3_Pos        BPROT_CONFIG0_REGION3_Pos
+#define MPU_PROTENSET0_PROTREG3_Msk        BPROT_CONFIG0_REGION3_Msk
+#define MPU_PROTENSET0_PROTREG3_Disabled   BPROT_CONFIG0_REGION3_Disabled
+#define MPU_PROTENSET0_PROTREG3_Enabled    BPROT_CONFIG0_REGION3_Enabled
+#define MPU_PROTENSET0_PROTREG3_Set        BPROT_CONFIG0_REGION3_Enabled
+
+#define MPU_PROTENSET0_PROTREG2_Pos        BPROT_CONFIG0_REGION2_Pos
+#define MPU_PROTENSET0_PROTREG2_Msk        BPROT_CONFIG0_REGION2_Msk
+#define MPU_PROTENSET0_PROTREG2_Disabled   BPROT_CONFIG0_REGION2_Disabled
+#define MPU_PROTENSET0_PROTREG2_Enabled    BPROT_CONFIG0_REGION2_Enabled
+#define MPU_PROTENSET0_PROTREG2_Set        BPROT_CONFIG0_REGION2_Enabled
+
+#define MPU_PROTENSET0_PROTREG1_Pos        BPROT_CONFIG0_REGION1_Pos
+#define MPU_PROTENSET0_PROTREG1_Msk        BPROT_CONFIG0_REGION1_Msk
+#define MPU_PROTENSET0_PROTREG1_Disabled   BPROT_CONFIG0_REGION1_Disabled
+#define MPU_PROTENSET0_PROTREG1_Enabled    BPROT_CONFIG0_REGION1_Enabled
+#define MPU_PROTENSET0_PROTREG1_Set        BPROT_CONFIG0_REGION1_Enabled
+
+#define MPU_PROTENSET0_PROTREG0_Pos        BPROT_CONFIG0_REGION0_Pos
+#define MPU_PROTENSET0_PROTREG0_Msk        BPROT_CONFIG0_REGION0_Msk
+#define MPU_PROTENSET0_PROTREG0_Disabled   BPROT_CONFIG0_REGION0_Disabled
+#define MPU_PROTENSET0_PROTREG0_Enabled    BPROT_CONFIG0_REGION0_Enabled
+#define MPU_PROTENSET0_PROTREG0_Set        BPROT_CONFIG0_REGION0_Enabled
+
+
+/* From nrf51_deprecated.h */
+
+/* NVMC */
+/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */
+#define ERASEPROTECTEDPAGE      ERASEPCR0
+
+
+/* IRQ */
+/* COMP module was eliminated. Adapted to nrf52 headers. */
+#define LPCOMP_COMP_IRQHandler  COMP_LPCOMP_IRQHandler
+#define LPCOMP_COMP_IRQn        COMP_LPCOMP_IRQn
+
+
+/* REFSEL register redefined enumerated values and added some more. */
+#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling          LPCOMP_REFSEL_REFSEL_Ref1_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling         LPCOMP_REFSEL_REFSEL_Ref2_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling       LPCOMP_REFSEL_REFSEL_Ref3_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling        LPCOMP_REFSEL_REFSEL_Ref4_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling        LPCOMP_REFSEL_REFSEL_Ref5_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling         LPCOMP_REFSEL_REFSEL_Ref6_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling       LPCOMP_REFSEL_REFSEL_Ref7_8Vdd
+
+
+/* RADIO */
+/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
+#define RADIO_CRCCNF_SKIP_ADDR_Pos      RADIO_CRCCNF_SKIPADDR_Pos
+#define RADIO_CRCCNF_SKIP_ADDR_Msk      RADIO_CRCCNF_SKIPADDR_Msk
+#define RADIO_CRCCNF_SKIP_ADDR_Include  RADIO_CRCCNF_SKIPADDR_Include
+#define RADIO_CRCCNF_SKIP_ADDR_Skip     RADIO_CRCCNF_SKIPADDR_Skip
+
+
+/* FICR */
+/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
+#define DEVICEID0       DEVICEID[0]
+#define DEVICEID1       DEVICEID[1]
+
+/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
+#define ER0             ER[0]
+#define ER1             ER[1]
+#define ER2             ER[2]
+#define ER3             ER[3]
+
+/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
+#define IR0             IR[0]
+#define IR1             IR[1]
+#define IR2             IR[2]
+#define IR3             IR[3]
+
+/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
+#define DEVICEADDR0     DEVICEADDR[0]
+#define DEVICEADDR1     DEVICEADDR[1]
+
+
+/* PPI */
+/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
+#define TASKS_CHG0EN     TASKS_CHG[0].EN
+#define TASKS_CHG0DIS    TASKS_CHG[0].DIS
+#define TASKS_CHG1EN     TASKS_CHG[1].EN
+#define TASKS_CHG1DIS    TASKS_CHG[1].DIS
+#define TASKS_CHG2EN     TASKS_CHG[2].EN
+#define TASKS_CHG2DIS    TASKS_CHG[2].DIS
+#define TASKS_CHG3EN     TASKS_CHG[3].EN
+#define TASKS_CHG3DIS    TASKS_CHG[3].DIS
+
+/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
+#define CH0_EEP          CH[0].EEP
+#define CH0_TEP          CH[0].TEP
+#define CH1_EEP          CH[1].EEP
+#define CH1_TEP          CH[1].TEP
+#define CH2_EEP          CH[2].EEP
+#define CH2_TEP          CH[2].TEP
+#define CH3_EEP          CH[3].EEP
+#define CH3_TEP          CH[3].TEP
+#define CH4_EEP          CH[4].EEP
+#define CH4_TEP          CH[4].TEP
+#define CH5_EEP          CH[5].EEP
+#define CH5_TEP          CH[5].TEP
+#define CH6_EEP          CH[6].EEP
+#define CH6_TEP          CH[6].TEP
+#define CH7_EEP          CH[7].EEP
+#define CH7_TEP          CH[7].TEP
+#define CH8_EEP          CH[8].EEP
+#define CH8_TEP          CH[8].TEP
+#define CH9_EEP          CH[9].EEP
+#define CH9_TEP          CH[9].TEP
+#define CH10_EEP         CH[10].EEP
+#define CH10_TEP         CH[10].TEP
+#define CH11_EEP         CH[11].EEP
+#define CH11_TEP         CH[11].TEP
+#define CH12_EEP         CH[12].EEP
+#define CH12_TEP         CH[12].TEP
+#define CH13_EEP         CH[13].EEP
+#define CH13_TEP         CH[13].TEP
+#define CH14_EEP         CH[14].EEP
+#define CH14_TEP         CH[14].TEP
+#define CH15_EEP         CH[15].EEP
+#define CH15_TEP         CH[15].TEP
+
+/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
+#define CHG0             CHG[0]
+#define CHG1             CHG[1]
+#define CHG2             CHG[2]
+#define CHG3             CHG[3]
+
+/* All bitfield macros for the CHGx registers therefore changed name. */
+#define PPI_CHG0_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG0_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG0_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG0_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG0_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG0_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG0_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG0_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG0_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG0_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG0_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG0_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG0_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG0_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG0_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG0_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG0_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG0_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG0_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG0_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG0_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG0_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG0_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG0_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG0_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG0_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG0_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG0_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG0_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG0_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG0_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG0_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG0_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG0_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG0_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG0_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG0_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG0_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG0_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG0_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG0_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG0_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG0_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG0_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG0_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG0_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG0_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG0_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG0_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG0_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG0_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG0_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG0_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG0_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG0_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG0_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG0_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG0_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG0_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG0_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG0_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG0_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG0_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG0_CH0_Included   PPI_CHG_CH0_Included
+
+#define PPI_CHG1_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG1_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG1_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG1_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG1_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG1_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG1_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG1_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG1_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG1_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG1_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG1_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG1_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG1_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG1_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG1_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG1_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG1_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG1_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG1_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG1_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG1_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG1_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG1_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG1_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG1_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG1_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG1_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG1_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG1_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG1_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG1_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG1_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG1_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG1_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG1_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG1_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG1_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG1_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG1_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG1_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG1_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG1_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG1_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG1_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG1_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG1_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG1_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG1_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG1_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG1_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG1_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG1_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG1_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG1_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG1_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG1_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG1_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG1_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG1_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG1_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG1_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG1_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG1_CH0_Included   PPI_CHG_CH0_Included
+
+#define PPI_CHG2_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG2_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG2_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG2_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG2_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG2_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG2_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG2_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG2_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG2_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG2_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG2_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG2_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG2_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG2_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG2_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG2_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG2_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG2_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG2_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG2_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG2_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG2_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG2_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG2_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG2_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG2_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG2_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG2_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG2_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG2_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG2_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG2_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG2_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG2_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG2_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG2_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG2_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG2_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG2_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG2_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG2_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG2_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG2_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG2_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG2_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG2_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG2_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG2_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG2_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG2_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG2_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG2_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG2_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG2_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG2_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG2_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG2_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG2_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG2_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG2_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG2_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG2_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG2_CH0_Included   PPI_CHG_CH0_Included
+
+#define PPI_CHG3_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG3_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG3_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG3_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG3_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG3_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG3_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG3_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG3_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG3_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG3_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG3_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG3_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG3_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG3_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG3_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG3_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG3_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG3_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG3_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG3_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG3_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG3_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG3_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG3_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG3_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG3_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG3_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG3_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG3_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG3_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG3_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG3_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG3_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG3_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG3_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG3_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG3_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG3_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG3_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG3_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG3_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG3_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG3_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG3_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG3_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG3_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG3_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG3_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG3_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG3_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG3_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG3_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG3_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG3_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG3_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG3_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG3_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG3_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG3_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG3_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG3_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG3_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG3_CH0_Included   PPI_CHG_CH0_Included
+
+
+
+
+/*lint --flb "Leave library region" */
+
+#endif /* NRF51_TO_NRF52_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51_to_nrf52840.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,575 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+#ifndef NRF51_TO_NRF52840_H
+#define NRF51_TO_NRF52840_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52840 devices.
+ * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the
+ * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
+ * from the nrf51_deprecated.h file. */
+
+
+/* IRQ */
+/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */
+#define UART0_IRQHandler        UARTE0_UART0_IRQHandler
+#define SPI0_TWI0_IRQHandler    SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+#define SPI1_TWI1_IRQHandler    SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+#define ADC_IRQHandler          SAADC_IRQHandler
+#define LPCOMP_IRQHandler       COMP_LPCOMP_IRQHandler
+#define SWI0_IRQHandler         SWI0_EGU0_IRQHandler
+#define SWI1_IRQHandler         SWI1_EGU1_IRQHandler
+#define SWI2_IRQHandler         SWI2_EGU2_IRQHandler
+#define SWI3_IRQHandler         SWI3_EGU3_IRQHandler
+#define SWI4_IRQHandler         SWI4_EGU4_IRQHandler
+#define SWI5_IRQHandler         SWI5_EGU5_IRQHandler
+
+#define UART0_IRQn              UARTE0_UART0_IRQn
+#define SPI0_TWI0_IRQn          SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
+#define SPI1_TWI1_IRQn          SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
+#define ADC_IRQn                SAADC_IRQn
+#define LPCOMP_IRQn             COMP_LPCOMP_IRQn
+#define SWI0_IRQn               SWI0_EGU0_IRQn
+#define SWI1_IRQn               SWI1_EGU1_IRQn
+#define SWI2_IRQn               SWI2_EGU2_IRQn
+#define SWI3_IRQn               SWI3_EGU3_IRQn
+#define SWI4_IRQn               SWI4_EGU4_IRQn
+#define SWI5_IRQn               SWI5_EGU5_IRQn
+
+
+/* UICR */
+/* Register RBPCONF was renamed to APPROTECT. */
+#define RBPCONF     APPROTECT
+
+#define UICR_RBPCONF_PALL_Pos           UICR_APPROTECT_PALL_Pos
+#define UICR_RBPCONF_PALL_Msk           UICR_APPROTECT_PALL_Msk
+#define UICR_RBPCONF_PALL_Enabled       UICR_APPROTECT_PALL_Enabled
+#define UICR_RBPCONF_PALL_Disabled      UICR_APPROTECT_PALL_Disabled
+
+
+/* GPIO */
+/* GPIO port was renamed to P0. */
+#define NRF_GPIO        NRF_P0
+#define NRF_GPIO_BASE   NRF_P0_BASE
+
+
+/* QDEC */
+/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */
+#define PSELLED     PSEL.LED
+#define PSELA       PSEL.A
+#define PSELB       PSEL.B
+
+
+/* SPIS */
+/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */
+#define PSELSCK       PSEL.SCK
+#define PSELMISO      PSEL.MISO
+#define PSELMOSI      PSEL.MOSI
+#define PSELCSN       PSEL.CSN
+
+/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */
+#define RXDPTR        RXD.PTR
+#define MAXRX         RXD.MAXCNT
+#define AMOUNTRX      RXD.AMOUNT
+
+#define SPIS_MAXRX_MAXRX_Pos        SPIS_RXD_MAXCNT_MAXCNT_Pos
+#define SPIS_MAXRX_MAXRX_Msk        SPIS_RXD_MAXCNT_MAXCNT_Msk
+
+#define SPIS_AMOUNTRX_AMOUNTRX_Pos  SPIS_RXD_AMOUNT_AMOUNT_Pos
+#define SPIS_AMOUNTRX_AMOUNTRX_Msk  SPIS_RXD_AMOUNT_AMOUNT_Msk
+
+/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */
+#define TXDPTR        TXD.PTR
+#define MAXTX         TXD.MAXCNT
+#define AMOUNTTX      TXD.AMOUNT
+
+#define SPIS_MAXTX_MAXTX_Pos        SPIS_TXD_MAXCNT_MAXCNT_Pos
+#define SPIS_MAXTX_MAXTX_Msk        SPIS_TXD_MAXCNT_MAXCNT_Msk
+
+#define SPIS_AMOUNTTX_AMOUNTTX_Pos  SPIS_TXD_AMOUNT_AMOUNT_Pos
+#define SPIS_AMOUNTTX_AMOUNTTX_Msk  SPIS_TXD_AMOUNT_AMOUNT_Msk
+
+
+/* UART */
+/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */
+#define PSELRTS       PSEL.RTS
+#define PSELTXD       PSEL.TXD
+#define PSELCTS       PSEL.CTS
+#define PSELRXD       PSEL.RXD
+
+/* TWI */
+/* The registers PSELSCL, PSELSDA were restructured into a struct. */
+#define PSELSCL       PSEL.SCL
+#define PSELSDA       PSEL.SDA
+
+
+
+/* From nrf51_deprecated.h */
+
+/* NVMC */
+/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */
+#define ERASEPROTECTEDPAGE      ERASEPCR0
+
+
+/* IRQ */
+/* COMP module was eliminated. Adapted to nrf52840 headers. */
+#define LPCOMP_COMP_IRQHandler  COMP_LPCOMP_IRQHandler
+#define LPCOMP_COMP_IRQn        COMP_LPCOMP_IRQn
+
+
+/* REFSEL register redefined enumerated values and added some more. */
+#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling          LPCOMP_REFSEL_REFSEL_Ref1_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling         LPCOMP_REFSEL_REFSEL_Ref2_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling       LPCOMP_REFSEL_REFSEL_Ref3_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling        LPCOMP_REFSEL_REFSEL_Ref4_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling        LPCOMP_REFSEL_REFSEL_Ref5_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling         LPCOMP_REFSEL_REFSEL_Ref6_8Vdd
+#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling       LPCOMP_REFSEL_REFSEL_Ref7_8Vdd
+
+
+/* RADIO */
+/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
+#define RADIO_CRCCNF_SKIP_ADDR_Pos      RADIO_CRCCNF_SKIPADDR_Pos
+#define RADIO_CRCCNF_SKIP_ADDR_Msk      RADIO_CRCCNF_SKIPADDR_Msk
+#define RADIO_CRCCNF_SKIP_ADDR_Include  RADIO_CRCCNF_SKIPADDR_Include
+#define RADIO_CRCCNF_SKIP_ADDR_Skip     RADIO_CRCCNF_SKIPADDR_Skip
+
+
+/* FICR */
+/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
+#define DEVICEID0       DEVICEID[0]
+#define DEVICEID1       DEVICEID[1]
+
+/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
+#define ER0             ER[0]
+#define ER1             ER[1]
+#define ER2             ER[2]
+#define ER3             ER[3]
+
+/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
+#define IR0             IR[0]
+#define IR1             IR[1]
+#define IR2             IR[2]
+#define IR3             IR[3]
+
+/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
+#define DEVICEADDR0     DEVICEADDR[0]
+#define DEVICEADDR1     DEVICEADDR[1]
+
+
+/* PPI */
+/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
+#define TASKS_CHG0EN     TASKS_CHG[0].EN
+#define TASKS_CHG0DIS    TASKS_CHG[0].DIS
+#define TASKS_CHG1EN     TASKS_CHG[1].EN
+#define TASKS_CHG1DIS    TASKS_CHG[1].DIS
+#define TASKS_CHG2EN     TASKS_CHG[2].EN
+#define TASKS_CHG2DIS    TASKS_CHG[2].DIS
+#define TASKS_CHG3EN     TASKS_CHG[3].EN
+#define TASKS_CHG3DIS    TASKS_CHG[3].DIS
+
+/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
+#define CH0_EEP          CH[0].EEP
+#define CH0_TEP          CH[0].TEP
+#define CH1_EEP          CH[1].EEP
+#define CH1_TEP          CH[1].TEP
+#define CH2_EEP          CH[2].EEP
+#define CH2_TEP          CH[2].TEP
+#define CH3_EEP          CH[3].EEP
+#define CH3_TEP          CH[3].TEP
+#define CH4_EEP          CH[4].EEP
+#define CH4_TEP          CH[4].TEP
+#define CH5_EEP          CH[5].EEP
+#define CH5_TEP          CH[5].TEP
+#define CH6_EEP          CH[6].EEP
+#define CH6_TEP          CH[6].TEP
+#define CH7_EEP          CH[7].EEP
+#define CH7_TEP          CH[7].TEP
+#define CH8_EEP          CH[8].EEP
+#define CH8_TEP          CH[8].TEP
+#define CH9_EEP          CH[9].EEP
+#define CH9_TEP          CH[9].TEP
+#define CH10_EEP         CH[10].EEP
+#define CH10_TEP         CH[10].TEP
+#define CH11_EEP         CH[11].EEP
+#define CH11_TEP         CH[11].TEP
+#define CH12_EEP         CH[12].EEP
+#define CH12_TEP         CH[12].TEP
+#define CH13_EEP         CH[13].EEP
+#define CH13_TEP         CH[13].TEP
+#define CH14_EEP         CH[14].EEP
+#define CH14_TEP         CH[14].TEP
+#define CH15_EEP         CH[15].EEP
+#define CH15_TEP         CH[15].TEP
+
+/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
+#define CHG0             CHG[0]
+#define CHG1             CHG[1]
+#define CHG2             CHG[2]
+#define CHG3             CHG[3]
+
+/* All bitfield macros for the CHGx registers therefore changed name. */
+#define PPI_CHG0_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG0_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG0_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG0_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG0_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG0_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG0_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG0_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG0_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG0_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG0_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG0_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG0_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG0_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG0_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG0_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG0_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG0_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG0_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG0_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG0_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG0_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG0_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG0_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG0_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG0_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG0_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG0_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG0_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG0_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG0_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG0_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG0_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG0_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG0_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG0_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG0_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG0_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG0_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG0_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG0_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG0_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG0_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG0_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG0_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG0_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG0_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG0_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG0_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG0_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG0_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG0_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG0_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG0_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG0_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG0_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG0_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG0_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG0_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG0_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG0_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG0_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG0_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG0_CH0_Included   PPI_CHG_CH0_Included
+
+#define PPI_CHG1_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG1_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG1_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG1_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG1_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG1_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG1_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG1_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG1_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG1_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG1_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG1_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG1_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG1_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG1_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG1_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG1_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG1_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG1_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG1_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG1_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG1_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG1_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG1_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG1_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG1_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG1_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG1_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG1_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG1_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG1_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG1_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG1_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG1_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG1_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG1_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG1_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG1_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG1_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG1_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG1_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG1_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG1_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG1_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG1_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG1_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG1_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG1_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG1_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG1_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG1_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG1_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG1_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG1_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG1_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG1_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG1_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG1_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG1_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG1_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG1_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG1_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG1_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG1_CH0_Included   PPI_CHG_CH0_Included
+
+#define PPI_CHG2_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG2_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG2_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG2_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG2_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG2_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG2_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG2_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG2_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG2_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG2_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG2_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG2_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG2_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG2_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG2_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG2_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG2_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG2_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG2_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG2_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG2_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG2_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG2_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG2_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG2_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG2_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG2_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG2_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG2_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG2_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG2_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG2_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG2_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG2_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG2_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG2_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG2_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG2_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG2_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG2_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG2_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG2_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG2_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG2_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG2_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG2_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG2_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG2_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG2_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG2_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG2_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG2_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG2_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG2_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG2_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG2_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG2_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG2_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG2_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG2_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG2_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG2_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG2_CH0_Included   PPI_CHG_CH0_Included
+
+#define PPI_CHG3_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG3_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG3_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG3_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG3_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG3_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG3_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG3_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG3_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG3_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG3_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG3_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG3_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG3_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG3_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG3_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG3_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG3_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG3_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG3_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG3_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG3_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG3_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG3_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG3_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG3_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG3_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG3_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG3_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG3_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG3_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG3_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG3_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG3_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG3_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG3_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG3_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG3_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG3_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG3_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG3_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG3_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG3_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG3_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG3_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG3_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG3_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG3_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG3_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG3_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG3_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG3_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG3_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG3_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG3_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG3_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG3_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG3_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG3_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG3_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG3_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG3_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG3_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG3_CH0_Included   PPI_CHG_CH0_Included
+
+
+
+
+/*lint --flb "Leave library region" */
+
+#endif /* NRF51_TO_NRF52840_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,2091 @@
+
+/****************************************************************************************************//**
+ * @file     nrf52.h
+ *
+ * @brief    CMSIS Cortex-M4 Peripheral Access Layer Header File for
+ *           nrf52 from Nordic Semiconductor.
+ *
+ * @version  V1
+ * @date     18. November 2016
+ *
+ * @note     Generated with SVDConv V2.81d 
+ *           from CMSIS SVD File 'nrf52.svd' Version 1,
+ *
+ * @par      Copyright (c) 2016, Nordic Semiconductor ASA
+ *           All rights reserved.
+ *           
+ *           Redistribution and use in source and binary forms, with or without
+ *           modification, are permitted provided that the following conditions are met:
+ *           
+ *           * Redistributions of source code must retain the above copyright notice, this
+ *           list of conditions and the following disclaimer.
+ *           
+ *           * Redistributions in binary form must reproduce the above copyright notice,
+ *           this list of conditions and the following disclaimer in the documentation
+ *           and/or other materials provided with the distribution.
+ *           
+ *           * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *           contributors may be used to endorse or promote products derived from
+ *           this software without specific prior written permission.
+ *           
+ *           THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *           AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *           IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *           DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ *           FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *           DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ *           SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ *           CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ *           OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *           OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *           
+ *
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup Nordic Semiconductor
+  * @{
+  */
+
+/** @addtogroup nrf52
+  * @{
+  */
+
+#ifndef NRF52_H
+#define NRF52_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum {
+/* -------------------  Cortex-M4 Processor Exceptions Numbers  ------------------- */
+  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */
+  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */
+  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
+  MemoryManagement_IRQn         = -12,              /*!<   4  Memory Management, MPU mismatch, including Access Violation
+                                                         and No Match                                                          */
+  BusFault_IRQn                 = -11,              /*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+                                                         related Fault                                                         */
+  UsageFault_IRQn               = -10,              /*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition    */
+  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */
+  DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */
+  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */
+  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */
+/* ----------------------  nrf52 Specific Interrupt Numbers  ---------------------- */
+  POWER_CLOCK_IRQn              =   0,              /*!<   0  POWER_CLOCK                                                      */
+  RADIO_IRQn                    =   1,              /*!<   1  RADIO                                                            */
+  UARTE0_UART0_IRQn             =   2,              /*!<   2  UARTE0_UART0                                                     */
+  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn=   3,      /*!<   3  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0                                */
+  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn=   4,      /*!<   4  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1                                */
+  NFCT_IRQn                     =   5,              /*!<   5  NFCT                                                             */
+  GPIOTE_IRQn                   =   6,              /*!<   6  GPIOTE                                                           */
+  SAADC_IRQn                    =   7,              /*!<   7  SAADC                                                            */
+  TIMER0_IRQn                   =   8,              /*!<   8  TIMER0                                                           */
+  TIMER1_IRQn                   =   9,              /*!<   9  TIMER1                                                           */
+  TIMER2_IRQn                   =  10,              /*!<  10  TIMER2                                                           */
+  RTC0_IRQn                     =  11,              /*!<  11  RTC0                                                             */
+  TEMP_IRQn                     =  12,              /*!<  12  TEMP                                                             */
+  RNG_IRQn                      =  13,              /*!<  13  RNG                                                              */
+  ECB_IRQn                      =  14,              /*!<  14  ECB                                                              */
+  CCM_AAR_IRQn                  =  15,              /*!<  15  CCM_AAR                                                          */
+  WDT_IRQn                      =  16,              /*!<  16  WDT                                                              */
+  RTC1_IRQn                     =  17,              /*!<  17  RTC1                                                             */
+  QDEC_IRQn                     =  18,              /*!<  18  QDEC                                                             */
+  COMP_LPCOMP_IRQn              =  19,              /*!<  19  COMP_LPCOMP                                                      */
+  SWI0_EGU0_IRQn                =  20,              /*!<  20  SWI0_EGU0                                                        */
+  SWI1_EGU1_IRQn                =  21,              /*!<  21  SWI1_EGU1                                                        */
+  SWI2_EGU2_IRQn                =  22,              /*!<  22  SWI2_EGU2                                                        */
+  SWI3_EGU3_IRQn                =  23,              /*!<  23  SWI3_EGU3                                                        */
+  SWI4_EGU4_IRQn                =  24,              /*!<  24  SWI4_EGU4                                                        */
+  SWI5_EGU5_IRQn                =  25,              /*!<  25  SWI5_EGU5                                                        */
+  TIMER3_IRQn                   =  26,              /*!<  26  TIMER3                                                           */
+  TIMER4_IRQn                   =  27,              /*!<  27  TIMER4                                                           */
+  PWM0_IRQn                     =  28,              /*!<  28  PWM0                                                             */
+  PDM_IRQn                      =  29,              /*!<  29  PDM                                                              */
+  MWU_IRQn                      =  32,              /*!<  32  MWU                                                              */
+  PWM1_IRQn                     =  33,              /*!<  33  PWM1                                                             */
+  PWM2_IRQn                     =  34,              /*!<  34  PWM2                                                             */
+  SPIM2_SPIS2_SPI2_IRQn         =  35,              /*!<  35  SPIM2_SPIS2_SPI2                                                 */
+  RTC2_IRQn                     =  36,              /*!<  36  RTC2                                                             */
+  I2S_IRQn                      =  37,              /*!<  37  I2S                                                              */
+  FPU_IRQn                      =  38               /*!<  38  FPU                                                              */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
+#define __CM4_REV                 0x0001            /*!< Cortex-M4 Core Revision                                               */
+#define __MPU_PRESENT                  1            /*!< MPU present or not                                                    */
+#define __NVIC_PRIO_BITS               3            /*!< Number of Bits used for Priority Levels                               */
+#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
+#define __FPU_PRESENT                  1            /*!< FPU present or not                                                    */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm4.h"                               /*!< Cortex-M4 processor and core peripherals                              */
+#include "system_nrf52.h"                           /*!< nrf52 System                                                          */
+
+
+/* ================================================================================ */
+/* ================       Device Specific Peripheral Section       ================ */
+/* ================================================================================ */
+
+
+/** @addtogroup Device_Peripheral_Registers
+  * @{
+  */
+
+
+/* -------------------  Start of section using anonymous unions  ------------------ */
+#if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__ICCARM__)
+  #pragma language=extended
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+  #pragma warning 586
+#else
+  #warning Not supported compiler type
+#endif
+
+
+typedef struct {
+  __I  uint32_t  PART;                              /*!< Part code                                                             */
+  __I  uint32_t  VARIANT;                           /*!< Part Variant, Hardware version and Production configuration           */
+  __I  uint32_t  PACKAGE;                           /*!< Package option                                                        */
+  __I  uint32_t  RAM;                               /*!< RAM variant                                                           */
+  __I  uint32_t  FLASH;                             /*!< Flash variant                                                         */
+  __IO uint32_t  UNUSED0[3];                        /*!< Description collection[0]: Unspecified                                */
+} FICR_INFO_Type;
+
+typedef struct {
+  __I  uint32_t  A0;                                /*!< Slope definition A0.                                                  */
+  __I  uint32_t  A1;                                /*!< Slope definition A1.                                                  */
+  __I  uint32_t  A2;                                /*!< Slope definition A2.                                                  */
+  __I  uint32_t  A3;                                /*!< Slope definition A3.                                                  */
+  __I  uint32_t  A4;                                /*!< Slope definition A4.                                                  */
+  __I  uint32_t  A5;                                /*!< Slope definition A5.                                                  */
+  __I  uint32_t  B0;                                /*!< y-intercept B0.                                                       */
+  __I  uint32_t  B1;                                /*!< y-intercept B1.                                                       */
+  __I  uint32_t  B2;                                /*!< y-intercept B2.                                                       */
+  __I  uint32_t  B3;                                /*!< y-intercept B3.                                                       */
+  __I  uint32_t  B4;                                /*!< y-intercept B4.                                                       */
+  __I  uint32_t  B5;                                /*!< y-intercept B5.                                                       */
+  __I  uint32_t  T0;                                /*!< Segment end T0.                                                       */
+  __I  uint32_t  T1;                                /*!< Segment end T1.                                                       */
+  __I  uint32_t  T2;                                /*!< Segment end T2.                                                       */
+  __I  uint32_t  T3;                                /*!< Segment end T3.                                                       */
+  __I  uint32_t  T4;                                /*!< Segment end T4.                                                       */
+} FICR_TEMP_Type;
+
+typedef struct {
+  __I  uint32_t  TAGHEADER0;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+  __I  uint32_t  TAGHEADER1;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+  __I  uint32_t  TAGHEADER2;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+  __I  uint32_t  TAGHEADER3;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+} FICR_NFC_Type;
+
+typedef struct {
+  __IO uint32_t  POWER;                             /*!< Description cluster[0]: RAM0 power control register                   */
+  __O  uint32_t  POWERSET;                          /*!< Description cluster[0]: RAM0 power control set register               */
+  __O  uint32_t  POWERCLR;                          /*!< Description cluster[0]: RAM0 power control clear register             */
+  __I  uint32_t  RESERVED0;
+} POWER_RAM_Type;
+
+typedef struct {
+  __IO uint32_t  RTS;                               /*!< Pin select for RTS signal                                             */
+  __IO uint32_t  TXD;                               /*!< Pin select for TXD signal                                             */
+  __IO uint32_t  CTS;                               /*!< Pin select for CTS signal                                             */
+  __IO uint32_t  RXD;                               /*!< Pin select for RXD signal                                             */
+} UARTE_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+} UARTE_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+} UARTE_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */
+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI signal                                            */
+  __IO uint32_t  MISO;                              /*!< Pin select for MISO signal                                            */
+} SPIM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} SPIM_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} SPIM_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */
+  __IO uint32_t  MISO;                              /*!< Pin select for MISO signal                                            */
+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI signal                                            */
+  __IO uint32_t  CSN;                               /*!< Pin select for CSN signal                                             */
+} SPIS_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< RXD data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes received in last granted transaction                  */
+} SPIS_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< TXD data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transmitted in last granted transaction               */
+} SPIS_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCL;                               /*!< Pin select for SCL signal                                             */
+  __IO uint32_t  SDA;                               /*!< Pin select for SDA signal                                             */
+} TWIM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} TWIM_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} TWIM_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCL;                               /*!< Pin select for SCL signal                                             */
+  __IO uint32_t  SDA;                               /*!< Pin select for SDA signal                                             */
+} TWIS_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< RXD Data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in RXD buffer                                 */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last RXD transaction               */
+} TWIS_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< TXD Data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in TXD buffer                                 */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last TXD transaction               */
+} TWIS_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */
+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI                                                   */
+  __IO uint32_t  MISO;                              /*!< Pin select for MISO                                                   */
+} SPI_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  RX;                                /*!< Result of last incoming frames                                        */
+} NFCT_FRAMESTATUS_Type;
+
+typedef struct {
+  __IO uint32_t  FRAMECONFIG;                       /*!< Configuration of outgoing frames                                      */
+  __IO uint32_t  AMOUNT;                            /*!< Size of outgoing frame                                                */
+} NFCT_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  FRAMECONFIG;                       /*!< Configuration of incoming frames                                      */
+  __I  uint32_t  AMOUNT;                            /*!< Size of last incoming frame                                           */
+} NFCT_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  LIMITH;                            /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */
+  __IO uint32_t  LIMITL;                            /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */
+} SAADC_EVENTS_CH_Type;
+
+typedef struct {
+  __IO uint32_t  PSELP;                             /*!< Description cluster[0]: Input positive pin selection for CH[0]        */
+  __IO uint32_t  PSELN;                             /*!< Description cluster[0]: Input negative pin selection for CH[0]        */
+  __IO uint32_t  CONFIG;                            /*!< Description cluster[0]: Input configuration for CH[0]                 */
+  __IO uint32_t  LIMIT;                             /*!< Description cluster[0]: High/low limits for event monitoring
+                                                         a channel                                                             */
+} SAADC_CH_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of buffer words to transfer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of buffer words transferred since last START                   */
+} SAADC_RESULT_Type;
+
+typedef struct {
+  __IO uint32_t  LED;                               /*!< Pin select for LED signal                                             */
+  __IO uint32_t  A;                                 /*!< Pin select for A signal                                               */
+  __IO uint32_t  B;                                 /*!< Pin select for B signal                                               */
+} QDEC_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Description cluster[0]: Beginning address in Data RAM of this
+                                                         sequence                                                              */
+  __IO uint32_t  CNT;                               /*!< Description cluster[0]: Amount of values (duty cycles) in this
+                                                         sequence                                                              */
+  __IO uint32_t  REFRESH;                           /*!< Description cluster[0]: Amount of additional PWM periods between
+                                                         samples loaded into compare register                                  */
+  __IO uint32_t  ENDDELAY;                          /*!< Description cluster[0]: Time added after the sequence                 */
+  __I  uint32_t  RESERVED1[4];
+} PWM_SEQ_Type;
+
+typedef struct {
+  __IO uint32_t  OUT[4];                            /*!< Description collection[0]: Output pin select for PWM channel
+                                                         0                                                                     */
+} PWM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  CLK;                               /*!< Pin number configuration for PDM CLK signal                           */
+  __IO uint32_t  DIN;                               /*!< Pin number configuration for PDM DIN signal                           */
+} PDM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< RAM address pointer to write samples to with EasyDMA                  */
+  __IO uint32_t  MAXCNT;                            /*!< Number of samples to allocate memory for in EasyDMA mode              */
+} PDM_SAMPLE_Type;
+
+typedef struct {
+  __O  uint32_t  EN;                                /*!< Description cluster[0]: Enable channel group 0                        */
+  __O  uint32_t  DIS;                               /*!< Description cluster[0]: Disable channel group 0                       */
+} PPI_TASKS_CHG_Type;
+
+typedef struct {
+  __IO uint32_t  EEP;                               /*!< Description cluster[0]: Channel 0 event end-point                     */
+  __IO uint32_t  TEP;                               /*!< Description cluster[0]: Channel 0 task end-point                      */
+} PPI_CH_Type;
+
+typedef struct {
+  __IO uint32_t  TEP;                               /*!< Description cluster[0]: Channel 0 task end-point                      */
+} PPI_FORK_Type;
+
+typedef struct {
+  __IO uint32_t  WA;                                /*!< Description cluster[0]: Write access to region 0 detected             */
+  __IO uint32_t  RA;                                /*!< Description cluster[0]: Read access to region 0 detected              */
+} MWU_EVENTS_REGION_Type;
+
+typedef struct {
+  __IO uint32_t  WA;                                /*!< Description cluster[0]: Write access to peripheral region 0
+                                                         detected                                                              */
+  __IO uint32_t  RA;                                /*!< Description cluster[0]: Read access to peripheral region 0 detected   */
+} MWU_EVENTS_PREGION_Type;
+
+typedef struct {
+  __IO uint32_t  SUBSTATWA;                         /*!< Description cluster[0]: Source of event/interrupt in region
+                                                         0, write access detected while corresponding subregion was enabled
+                                                          for watching                                                         */
+  __IO uint32_t  SUBSTATRA;                         /*!< Description cluster[0]: Source of event/interrupt in region
+                                                         0, read access detected while corresponding subregion was enabled
+                                                          for watching                                                         */
+} MWU_PERREGION_Type;
+
+typedef struct {
+  __IO uint32_t  START;                             /*!< Description cluster[0]: Start address for region 0                    */
+  __IO uint32_t  END;                               /*!< Description cluster[0]: End address of region 0                       */
+  __I  uint32_t  RESERVED2[2];
+} MWU_REGION_Type;
+
+typedef struct {
+  __I  uint32_t  START;                             /*!< Description cluster[0]: Reserved for future use                       */
+  __I  uint32_t  END;                               /*!< Description cluster[0]: Reserved for future use                       */
+  __IO uint32_t  SUBS;                              /*!< Description cluster[0]: Subregions of region 0                        */
+  __I  uint32_t  RESERVED3;
+} MWU_PREGION_Type;
+
+typedef struct {
+  __IO uint32_t  MODE;                              /*!< I2S mode.                                                             */
+  __IO uint32_t  RXEN;                              /*!< Reception (RX) enable.                                                */
+  __IO uint32_t  TXEN;                              /*!< Transmission (TX) enable.                                             */
+  __IO uint32_t  MCKEN;                             /*!< Master clock generator enable.                                        */
+  __IO uint32_t  MCKFREQ;                           /*!< Master clock generator frequency.                                     */
+  __IO uint32_t  RATIO;                             /*!< MCK / LRCK ratio.                                                     */
+  __IO uint32_t  SWIDTH;                            /*!< Sample width.                                                         */
+  __IO uint32_t  ALIGN;                             /*!< Alignment of sample within a frame.                                   */
+  __IO uint32_t  FORMAT;                            /*!< Frame format.                                                         */
+  __IO uint32_t  CHANNELS;                          /*!< Enable channels.                                                      */
+} I2S_CONFIG_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Receive buffer RAM start address.                                     */
+} I2S_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Transmit buffer RAM start address.                                    */
+} I2S_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  MAXCNT;                            /*!< Size of RXD and TXD buffers.                                          */
+} I2S_RXTXD_Type;
+
+typedef struct {
+  __IO uint32_t  MCK;                               /*!< Pin select for MCK signal.                                            */
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK signal.                                            */
+  __IO uint32_t  LRCK;                              /*!< Pin select for LRCK signal.                                           */
+  __IO uint32_t  SDIN;                              /*!< Pin select for SDIN signal.                                           */
+  __IO uint32_t  SDOUT;                             /*!< Pin select for SDOUT signal.                                          */
+} I2S_PSEL_Type;
+
+
+/* ================================================================================ */
+/* ================                      FICR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Factory Information Configuration Registers (FICR)
+  */
+
+typedef struct {                                    /*!< FICR Structure                                                        */
+  __I  uint32_t  RESERVED0[4];
+  __I  uint32_t  CODEPAGESIZE;                      /*!< Code memory page size                                                 */
+  __I  uint32_t  CODESIZE;                          /*!< Code memory size                                                      */
+  __I  uint32_t  RESERVED1[18];
+  __I  uint32_t  DEVICEID[2];                       /*!< Description collection[0]: Device identifier                          */
+  __I  uint32_t  RESERVED2[6];
+  __I  uint32_t  ER[4];                             /*!< Description collection[0]: Encryption Root, word 0                    */
+  __I  uint32_t  IR[4];                             /*!< Description collection[0]: Identity Root, word 0                      */
+  __I  uint32_t  DEVICEADDRTYPE;                    /*!< Device address type                                                   */
+  __I  uint32_t  DEVICEADDR[2];                     /*!< Description collection[0]: Device address 0                           */
+  __I  uint32_t  RESERVED3[21];
+  FICR_INFO_Type INFO;                              /*!< Device info                                                           */
+  __I  uint32_t  RESERVED4[185];
+  FICR_TEMP_Type TEMP;                              /*!< Registers storing factory TEMP module linearization coefficients      */
+  __I  uint32_t  RESERVED5[2];
+  FICR_NFC_Type NFC;                                /*!< Unspecified                                                           */
+} NRF_FICR_Type;
+
+
+/* ================================================================================ */
+/* ================                      UICR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief User Information Configuration Registers (UICR)
+  */
+
+typedef struct {                                    /*!< UICR Structure                                                        */
+  __IO uint32_t  UNUSED0;                           /*!< Unspecified                                                           */
+  __IO uint32_t  UNUSED1;                           /*!< Unspecified                                                           */
+  __IO uint32_t  UNUSED2;                           /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t  UNUSED3;                           /*!< Unspecified                                                           */
+  __IO uint32_t  NRFFW[15];                         /*!< Description collection[0]: Reserved for Nordic firmware design        */
+  __IO uint32_t  NRFHW[12];                         /*!< Description collection[0]: Reserved for Nordic hardware design        */
+  __IO uint32_t  CUSTOMER[32];                      /*!< Description collection[0]: Reserved for customer                      */
+  __I  uint32_t  RESERVED1[64];
+  __IO uint32_t  PSELRESET[2];                      /*!< Description collection[0]: Mapping of the nRESET function (see
+                                                         POWER chapter for details)                                            */
+  __IO uint32_t  APPROTECT;                         /*!< Access Port protection                                                */
+  __IO uint32_t  NFCPINS;                           /*!< Setting of pins dedicated to NFC functionality: NFC antenna
+                                                         or GPIO                                                               */
+} NRF_UICR_Type;
+
+
+/* ================================================================================ */
+/* ================                      BPROT                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Block Protect (BPROT)
+  */
+
+typedef struct {                                    /*!< BPROT Structure                                                       */
+  __I  uint32_t  RESERVED0[384];
+  __IO uint32_t  CONFIG0;                           /*!< Block protect configuration register 0                                */
+  __IO uint32_t  CONFIG1;                           /*!< Block protect configuration register 1                                */
+  __IO uint32_t  DISABLEINDEBUG;                    /*!< Disable protection mechanism in debug interface mode                  */
+  __IO uint32_t  UNUSED0;                           /*!< Unspecified                                                           */
+  __IO uint32_t  CONFIG2;                           /*!< Block protect configuration register 2                                */
+  __IO uint32_t  CONFIG3;                           /*!< Block protect configuration register 3                                */
+} NRF_BPROT_Type;
+
+
+/* ================================================================================ */
+/* ================                      POWER                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Power control (POWER)
+  */
+
+typedef struct {                                    /*!< POWER Structure                                                       */
+  __I  uint32_t  RESERVED0[30];
+  __O  uint32_t  TASKS_CONSTLAT;                    /*!< Enable constant latency mode                                          */
+  __O  uint32_t  TASKS_LOWPWR;                      /*!< Enable low power mode (variable latency)                              */
+  __I  uint32_t  RESERVED1[34];
+  __IO uint32_t  EVENTS_POFWARN;                    /*!< Power failure warning                                                 */
+  __I  uint32_t  RESERVED2[2];
+  __IO uint32_t  EVENTS_SLEEPENTER;                 /*!< CPU entered WFI/WFE sleep                                             */
+  __IO uint32_t  EVENTS_SLEEPEXIT;                  /*!< CPU exited WFI/WFE sleep                                              */
+  __I  uint32_t  RESERVED3[122];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED4[61];
+  __IO uint32_t  RESETREAS;                         /*!< Reset reason                                                          */
+  __I  uint32_t  RESERVED5[9];
+  __I  uint32_t  RAMSTATUS;                         /*!< Deprecated register - RAM status register                             */
+  __I  uint32_t  RESERVED6[53];
+  __O  uint32_t  SYSTEMOFF;                         /*!< System OFF register                                                   */
+  __I  uint32_t  RESERVED7[3];
+  __IO uint32_t  POFCON;                            /*!< Power failure comparator configuration                                */
+  __I  uint32_t  RESERVED8[2];
+  __IO uint32_t  GPREGRET;                          /*!< General purpose retention register                                    */
+  __IO uint32_t  GPREGRET2;                         /*!< General purpose retention register                                    */
+  __IO uint32_t  RAMON;                             /*!< Deprecated register - RAM on/off register (this register is
+                                                         retained)                                                             */
+  __I  uint32_t  RESERVED9[11];
+  __IO uint32_t  RAMONB;                            /*!< Deprecated register - RAM on/off register (this register is
+                                                         retained)                                                             */
+  __I  uint32_t  RESERVED10[8];
+  __IO uint32_t  DCDCEN;                            /*!< DC/DC enable register                                                 */
+  __I  uint32_t  RESERVED11[225];
+  POWER_RAM_Type RAM[8];                            /*!< Unspecified                                                           */
+} NRF_POWER_Type;
+
+
+/* ================================================================================ */
+/* ================                      CLOCK                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Clock control (CLOCK)
+  */
+
+typedef struct {                                    /*!< CLOCK Structure                                                       */
+  __O  uint32_t  TASKS_HFCLKSTART;                  /*!< Start HFCLK crystal oscillator                                        */
+  __O  uint32_t  TASKS_HFCLKSTOP;                   /*!< Stop HFCLK crystal oscillator                                         */
+  __O  uint32_t  TASKS_LFCLKSTART;                  /*!< Start LFCLK source                                                    */
+  __O  uint32_t  TASKS_LFCLKSTOP;                   /*!< Stop LFCLK source                                                     */
+  __O  uint32_t  TASKS_CAL;                         /*!< Start calibration of LFRC oscillator                                  */
+  __O  uint32_t  TASKS_CTSTART;                     /*!< Start calibration timer                                               */
+  __O  uint32_t  TASKS_CTSTOP;                      /*!< Stop calibration timer                                                */
+  __I  uint32_t  RESERVED0[57];
+  __IO uint32_t  EVENTS_HFCLKSTARTED;               /*!< HFCLK oscillator started                                              */
+  __IO uint32_t  EVENTS_LFCLKSTARTED;               /*!< LFCLK started                                                         */
+  __I  uint32_t  RESERVED1;
+  __IO uint32_t  EVENTS_DONE;                       /*!< Calibration of LFCLK RC oscillator complete event                     */
+  __IO uint32_t  EVENTS_CTTO;                       /*!< Calibration timer timeout                                             */
+  __I  uint32_t  RESERVED2[124];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[63];
+  __I  uint32_t  HFCLKRUN;                          /*!< Status indicating that HFCLKSTART task has been triggered             */
+  __I  uint32_t  HFCLKSTAT;                         /*!< HFCLK status                                                          */
+  __I  uint32_t  RESERVED4;
+  __I  uint32_t  LFCLKRUN;                          /*!< Status indicating that LFCLKSTART task has been triggered             */
+  __I  uint32_t  LFCLKSTAT;                         /*!< LFCLK status                                                          */
+  __I  uint32_t  LFCLKSRCCOPY;                      /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered     */
+  __I  uint32_t  RESERVED5[62];
+  __IO uint32_t  LFCLKSRC;                          /*!< Clock source for the LFCLK                                            */
+  __I  uint32_t  RESERVED6[7];
+  __IO uint32_t  CTIV;                              /*!< Calibration timer interval                                            */
+  __I  uint32_t  RESERVED7[8];
+  __IO uint32_t  TRACECONFIG;                       /*!< Clocking options for the Trace Port debug interface                   */
+} NRF_CLOCK_Type;
+
+
+/* ================================================================================ */
+/* ================                      RADIO                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief 2.4 GHz Radio (RADIO)
+  */
+
+typedef struct {                                    /*!< RADIO Structure                                                       */
+  __O  uint32_t  TASKS_TXEN;                        /*!< Enable RADIO in TX mode                                               */
+  __O  uint32_t  TASKS_RXEN;                        /*!< Enable RADIO in RX mode                                               */
+  __O  uint32_t  TASKS_START;                       /*!< Start RADIO                                                           */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop RADIO                                                            */
+  __O  uint32_t  TASKS_DISABLE;                     /*!< Disable RADIO                                                         */
+  __O  uint32_t  TASKS_RSSISTART;                   /*!< Start the RSSI and take one single sample of the receive signal
+                                                         strength.                                                             */
+  __O  uint32_t  TASKS_RSSISTOP;                    /*!< Stop the RSSI measurement                                             */
+  __O  uint32_t  TASKS_BCSTART;                     /*!< Start the bit counter                                                 */
+  __O  uint32_t  TASKS_BCSTOP;                      /*!< Stop the bit counter                                                  */
+  __I  uint32_t  RESERVED0[55];
+  __IO uint32_t  EVENTS_READY;                      /*!< RADIO has ramped up and is ready to be started                        */
+  __IO uint32_t  EVENTS_ADDRESS;                    /*!< Address sent or received                                              */
+  __IO uint32_t  EVENTS_PAYLOAD;                    /*!< Packet payload sent or received                                       */
+  __IO uint32_t  EVENTS_END;                        /*!< Packet sent or received                                               */
+  __IO uint32_t  EVENTS_DISABLED;                   /*!< RADIO has been disabled                                               */
+  __IO uint32_t  EVENTS_DEVMATCH;                   /*!< A device address match occurred on the last received packet           */
+  __IO uint32_t  EVENTS_DEVMISS;                    /*!< No device address match occurred on the last received packet          */
+  __IO uint32_t  EVENTS_RSSIEND;                    /*!< Sampling of receive signal strength complete.                         */
+  __I  uint32_t  RESERVED1[2];
+  __IO uint32_t  EVENTS_BCMATCH;                    /*!< Bit counter reached bit count value.                                  */
+  __I  uint32_t  RESERVED2;
+  __IO uint32_t  EVENTS_CRCOK;                      /*!< Packet received with CRC ok                                           */
+  __IO uint32_t  EVENTS_CRCERROR;                   /*!< Packet received with CRC error                                        */
+  __I  uint32_t  RESERVED3[50];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED4[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED5[61];
+  __I  uint32_t  CRCSTATUS;                         /*!< CRC status                                                            */
+  __I  uint32_t  RESERVED6;
+  __I  uint32_t  RXMATCH;                           /*!< Received address                                                      */
+  __I  uint32_t  RXCRC;                             /*!< CRC field of previously received packet                               */
+  __I  uint32_t  DAI;                               /*!< Device address match index                                            */
+  __I  uint32_t  RESERVED7[60];
+  __IO uint32_t  PACKETPTR;                         /*!< Packet pointer                                                        */
+  __IO uint32_t  FREQUENCY;                         /*!< Frequency                                                             */
+  __IO uint32_t  TXPOWER;                           /*!< Output power                                                          */
+  __IO uint32_t  MODE;                              /*!< Data rate and modulation                                              */
+  __IO uint32_t  PCNF0;                             /*!< Packet configuration register 0                                       */
+  __IO uint32_t  PCNF1;                             /*!< Packet configuration register 1                                       */
+  __IO uint32_t  BASE0;                             /*!< Base address 0                                                        */
+  __IO uint32_t  BASE1;                             /*!< Base address 1                                                        */
+  __IO uint32_t  PREFIX0;                           /*!< Prefixes bytes for logical addresses 0-3                              */
+  __IO uint32_t  PREFIX1;                           /*!< Prefixes bytes for logical addresses 4-7                              */
+  __IO uint32_t  TXADDRESS;                         /*!< Transmit address select                                               */
+  __IO uint32_t  RXADDRESSES;                       /*!< Receive address select                                                */
+  __IO uint32_t  CRCCNF;                            /*!< CRC configuration                                                     */
+  __IO uint32_t  CRCPOLY;                           /*!< CRC polynomial                                                        */
+  __IO uint32_t  CRCINIT;                           /*!< CRC initial value                                                     */
+  __IO uint32_t  UNUSED0;                           /*!< Unspecified                                                           */
+  __IO uint32_t  TIFS;                              /*!< Inter Frame Spacing in us                                             */
+  __I  uint32_t  RSSISAMPLE;                        /*!< RSSI sample                                                           */
+  __I  uint32_t  RESERVED8;
+  __I  uint32_t  STATE;                             /*!< Current radio state                                                   */
+  __IO uint32_t  DATAWHITEIV;                       /*!< Data whitening initial value                                          */
+  __I  uint32_t  RESERVED9[2];
+  __IO uint32_t  BCC;                               /*!< Bit counter compare                                                   */
+  __I  uint32_t  RESERVED10[39];
+  __IO uint32_t  DAB[8];                            /*!< Description collection[0]: Device address base segment 0              */
+  __IO uint32_t  DAP[8];                            /*!< Description collection[0]: Device address prefix 0                    */
+  __IO uint32_t  DACNF;                             /*!< Device address match configuration                                    */
+  __I  uint32_t  RESERVED11[3];
+  __IO uint32_t  MODECNF0;                          /*!< Radio mode configuration register 0                                   */
+  __I  uint32_t  RESERVED12[618];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control                                              */
+} NRF_RADIO_Type;
+
+
+/* ================================================================================ */
+/* ================                      UARTE                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief UART with EasyDMA (UARTE)
+  */
+
+typedef struct {                                    /*!< UARTE Structure                                                       */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start UART receiver                                                   */
+  __O  uint32_t  TASKS_STOPRX;                      /*!< Stop UART receiver                                                    */
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start UART transmitter                                                */
+  __O  uint32_t  TASKS_STOPTX;                      /*!< Stop UART transmitter                                                 */
+  __I  uint32_t  RESERVED0[7];
+  __O  uint32_t  TASKS_FLUSHRX;                     /*!< Flush RX FIFO into RX buffer                                          */
+  __I  uint32_t  RESERVED1[52];
+  __IO uint32_t  EVENTS_CTS;                        /*!< CTS is activated (set low). Clear To Send.                            */
+  __IO uint32_t  EVENTS_NCTS;                       /*!< CTS is deactivated (set high). Not Clear To Send.                     */
+  __IO uint32_t  EVENTS_RXDRDY;                     /*!< Data received in RXD (but potentially not yet transferred to
+                                                         Data RAM)                                                             */
+  __I  uint32_t  RESERVED2;
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< Receive buffer is filled up                                           */
+  __I  uint32_t  RESERVED3[2];
+  __IO uint32_t  EVENTS_TXDRDY;                     /*!< Data sent from TXD                                                    */
+  __IO uint32_t  EVENTS_ENDTX;                      /*!< Last TX byte transmitted                                              */
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Error detected                                                        */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_RXTO;                       /*!< Receiver timeout                                                      */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  EVENTS_RXSTARTED;                  /*!< UART receiver has started                                             */
+  __IO uint32_t  EVENTS_TXSTARTED;                  /*!< UART transmitter has started                                          */
+  __I  uint32_t  RESERVED6;
+  __IO uint32_t  EVENTS_TXSTOPPED;                  /*!< Transmitter stopped                                                   */
+  __I  uint32_t  RESERVED7[41];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[93];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  RESERVED10[31];
+  __IO uint32_t  ENABLE;                            /*!< Enable UART                                                           */
+  __I  uint32_t  RESERVED11;
+  UARTE_PSEL_Type PSEL;                             /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[3];
+  __IO uint32_t  BAUDRATE;                          /*!< Baud rate. Accuracy depends on the HFCLK source selected.             */
+  __I  uint32_t  RESERVED13[3];
+  UARTE_RXD_Type RXD;                               /*!< RXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED14;
+  UARTE_TXD_Type TXD;                               /*!< TXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED15[7];
+  __IO uint32_t  CONFIG;                            /*!< Configuration of parity and hardware flow control                     */
+} NRF_UARTE_Type;
+
+
+/* ================================================================================ */
+/* ================                      UART                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Universal Asynchronous Receiver/Transmitter (UART)
+  */
+
+typedef struct {                                    /*!< UART Structure                                                        */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start UART receiver                                                   */
+  __O  uint32_t  TASKS_STOPRX;                      /*!< Stop UART receiver                                                    */
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start UART transmitter                                                */
+  __O  uint32_t  TASKS_STOPTX;                      /*!< Stop UART transmitter                                                 */
+  __I  uint32_t  RESERVED0[3];
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend UART                                                          */
+  __I  uint32_t  RESERVED1[56];
+  __IO uint32_t  EVENTS_CTS;                        /*!< CTS is activated (set low). Clear To Send.                            */
+  __IO uint32_t  EVENTS_NCTS;                       /*!< CTS is deactivated (set high). Not Clear To Send.                     */
+  __IO uint32_t  EVENTS_RXDRDY;                     /*!< Data received in RXD                                                  */
+  __I  uint32_t  RESERVED2[4];
+  __IO uint32_t  EVENTS_TXDRDY;                     /*!< Data sent from TXD                                                    */
+  __I  uint32_t  RESERVED3;
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Error detected                                                        */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_RXTO;                       /*!< Receiver timeout                                                      */
+  __I  uint32_t  RESERVED5[46];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED6[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED7[93];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  RESERVED8[31];
+  __IO uint32_t  ENABLE;                            /*!< Enable UART                                                           */
+  __I  uint32_t  RESERVED9;
+  __IO uint32_t  PSELRTS;                           /*!< Pin select for RTS                                                    */
+  __IO uint32_t  PSELTXD;                           /*!< Pin select for TXD                                                    */
+  __IO uint32_t  PSELCTS;                           /*!< Pin select for CTS                                                    */
+  __IO uint32_t  PSELRXD;                           /*!< Pin select for RXD                                                    */
+  __I  uint32_t  RXD;                               /*!< RXD register                                                          */
+  __O  uint32_t  TXD;                               /*!< TXD register                                                          */
+  __I  uint32_t  RESERVED10;
+  __IO uint32_t  BAUDRATE;                          /*!< Baud rate                                                             */
+  __I  uint32_t  RESERVED11[17];
+  __IO uint32_t  CONFIG;                            /*!< Configuration of parity and hardware flow control                     */
+} NRF_UART_Type;
+
+
+/* ================================================================================ */
+/* ================                      SPIM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM)
+  */
+
+typedef struct {                                    /*!< SPIM Structure                                                        */
+  __I  uint32_t  RESERVED0[4];
+  __O  uint32_t  TASKS_START;                       /*!< Start SPI transaction                                                 */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop SPI transaction                                                  */
+  __I  uint32_t  RESERVED1;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend SPI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume SPI transaction                                                */
+  __I  uint32_t  RESERVED2[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< SPI transaction has stopped                                           */
+  __I  uint32_t  RESERVED3[2];
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached                                             */
+  __I  uint32_t  RESERVED4;
+  __IO uint32_t  EVENTS_END;                        /*!< End of RXD buffer and TXD buffer reached                              */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  EVENTS_ENDTX;                      /*!< End of TXD buffer reached                                             */
+  __I  uint32_t  RESERVED6[10];
+  __IO uint32_t  EVENTS_STARTED;                    /*!< Transaction started                                                   */
+  __I  uint32_t  RESERVED7[44];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPIM                                                           */
+  __I  uint32_t  RESERVED10;
+  SPIM_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED11[4];
+  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency                                                         */
+  __I  uint32_t  RESERVED12[3];
+  SPIM_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */
+  SPIM_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  RESERVED13[26];
+  __IO uint32_t  ORC;                               /*!< Over-read character. Character clocked out in case and over-read
+                                                         of the TXD buffer.                                                    */
+} NRF_SPIM_Type;
+
+
+/* ================================================================================ */
+/* ================                      SPIS                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief SPI Slave 0 (SPIS)
+  */
+
+typedef struct {                                    /*!< SPIS Structure                                                        */
+  __I  uint32_t  RESERVED0[9];
+  __O  uint32_t  TASKS_ACQUIRE;                     /*!< Acquire SPI semaphore                                                 */
+  __O  uint32_t  TASKS_RELEASE;                     /*!< Release SPI semaphore, enabling the SPI slave to acquire it           */
+  __I  uint32_t  RESERVED1[54];
+  __IO uint32_t  EVENTS_END;                        /*!< Granted transaction completed                                         */
+  __I  uint32_t  RESERVED2[2];
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached                                             */
+  __I  uint32_t  RESERVED3[5];
+  __IO uint32_t  EVENTS_ACQUIRED;                   /*!< Semaphore acquired                                                    */
+  __I  uint32_t  RESERVED4[53];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED5[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED6[61];
+  __I  uint32_t  SEMSTAT;                           /*!< Semaphore status register                                             */
+  __I  uint32_t  RESERVED7[15];
+  __IO uint32_t  STATUS;                            /*!< Status from last transaction                                          */
+  __I  uint32_t  RESERVED8[47];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPI slave                                                      */
+  __I  uint32_t  RESERVED9;
+  SPIS_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED10[7];
+  SPIS_RXD_Type RXD;                                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED11;
+  SPIS_TXD_Type TXD;                                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12;
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  RESERVED13;
+  __IO uint32_t  DEF;                               /*!< Default character. Character clocked out in case of an ignored
+                                                         transaction.                                                          */
+  __I  uint32_t  RESERVED14[24];
+  __IO uint32_t  ORC;                               /*!< Over-read character                                                   */
+} NRF_SPIS_Type;
+
+
+/* ================================================================================ */
+/* ================                      TWIM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM)
+  */
+
+typedef struct {                                    /*!< TWIM Structure                                                        */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start TWI receive sequence                                            */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start TWI transmit sequence                                           */
+  __I  uint32_t  RESERVED1[2];
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction. Must be issued while the TWI master is
+                                                         not suspended.                                                        */
+  __I  uint32_t  RESERVED2;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */
+  __I  uint32_t  RESERVED3[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */
+  __I  uint32_t  RESERVED5[8];
+  __IO uint32_t  EVENTS_SUSPENDED;                  /*!< Last byte has been sent out after the SUSPEND task has been
+                                                         issued, TWI traffic is now suspended.                                 */
+  __IO uint32_t  EVENTS_RXSTARTED;                  /*!< Receive sequence started                                              */
+  __IO uint32_t  EVENTS_TXSTARTED;                  /*!< Transmit sequence started                                             */
+  __I  uint32_t  RESERVED6[2];
+  __IO uint32_t  EVENTS_LASTRX;                     /*!< Byte boundary, starting to receive the last byte                      */
+  __IO uint32_t  EVENTS_LASTTX;                     /*!< Byte boundary, starting to transmit the last byte                     */
+  __I  uint32_t  RESERVED7[39];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[110];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  RESERVED10[14];
+  __IO uint32_t  ENABLE;                            /*!< Enable TWIM                                                           */
+  __I  uint32_t  RESERVED11;
+  TWIM_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[5];
+  __IO uint32_t  FREQUENCY;                         /*!< TWI frequency                                                         */
+  __I  uint32_t  RESERVED13[3];
+  TWIM_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */
+  TWIM_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED14[13];
+  __IO uint32_t  ADDRESS;                           /*!< Address used in the TWI transfer                                      */
+} NRF_TWIM_Type;
+
+
+/* ================================================================================ */
+/* ================                      TWIS                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS)
+  */
+
+typedef struct {                                    /*!< TWIS Structure                                                        */
+  __I  uint32_t  RESERVED0[5];
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction                                                  */
+  __I  uint32_t  RESERVED1;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */
+  __I  uint32_t  RESERVED2[3];
+  __O  uint32_t  TASKS_PREPARERX;                   /*!< Prepare the TWI slave to respond to a write command                   */
+  __O  uint32_t  TASKS_PREPARETX;                   /*!< Prepare the TWI slave to respond to a read command                    */
+  __I  uint32_t  RESERVED3[51];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */
+  __I  uint32_t  RESERVED5[9];
+  __IO uint32_t  EVENTS_RXSTARTED;                  /*!< Receive sequence started                                              */
+  __IO uint32_t  EVENTS_TXSTARTED;                  /*!< Transmit sequence started                                             */
+  __I  uint32_t  RESERVED6[4];
+  __IO uint32_t  EVENTS_WRITE;                      /*!< Write command received                                                */
+  __IO uint32_t  EVENTS_READ;                       /*!< Read command received                                                 */
+  __I  uint32_t  RESERVED7[37];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[113];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  MATCH;                             /*!< Status register indicating which address had a match                  */
+  __I  uint32_t  RESERVED10[10];
+  __IO uint32_t  ENABLE;                            /*!< Enable TWIS                                                           */
+  __I  uint32_t  RESERVED11;
+  TWIS_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[9];
+  TWIS_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED13;
+  TWIS_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED14[14];
+  __IO uint32_t  ADDRESS[2];                        /*!< Description collection[0]: TWI slave address 0                        */
+  __I  uint32_t  RESERVED15;
+  __IO uint32_t  CONFIG;                            /*!< Configuration register for the address match mechanism                */
+  __I  uint32_t  RESERVED16[10];
+  __IO uint32_t  ORC;                               /*!< Over-read character. Character sent out in case of an over-read
+                                                         of the transmit buffer.                                               */
+} NRF_TWIS_Type;
+
+
+/* ================================================================================ */
+/* ================                       SPI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Serial Peripheral Interface 0 (SPI)
+  */
+
+typedef struct {                                    /*!< SPI Structure                                                         */
+  __I  uint32_t  RESERVED0[66];
+  __IO uint32_t  EVENTS_READY;                      /*!< TXD byte sent and RXD byte received                                   */
+  __I  uint32_t  RESERVED1[126];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPI                                                            */
+  __I  uint32_t  RESERVED3;
+  SPI_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED4;
+  __I  uint32_t  RXD;                               /*!< RXD register                                                          */
+  __IO uint32_t  TXD;                               /*!< TXD register                                                          */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency                                                         */
+  __I  uint32_t  RESERVED6[11];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+} NRF_SPI_Type;
+
+
+/* ================================================================================ */
+/* ================                       TWI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief I2C compatible Two-Wire Interface 0 (TWI)
+  */
+
+typedef struct {                                    /*!< TWI Structure                                                         */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start TWI receive sequence                                            */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start TWI transmit sequence                                           */
+  __I  uint32_t  RESERVED1[2];
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction                                                  */
+  __I  uint32_t  RESERVED2;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */
+  __I  uint32_t  RESERVED3[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */
+  __IO uint32_t  EVENTS_RXDREADY;                   /*!< TWI RXD byte received                                                 */
+  __I  uint32_t  RESERVED4[4];
+  __IO uint32_t  EVENTS_TXDSENT;                    /*!< TWI TXD byte sent                                                     */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */
+  __I  uint32_t  RESERVED6[4];
+  __IO uint32_t  EVENTS_BB;                         /*!< TWI byte boundary, generated before each byte that is sent or
+                                                         received                                                              */
+  __I  uint32_t  RESERVED7[3];
+  __IO uint32_t  EVENTS_SUSPENDED;                  /*!< TWI entered the suspended state                                       */
+  __I  uint32_t  RESERVED8[45];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED9[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED10[110];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  RESERVED11[14];
+  __IO uint32_t  ENABLE;                            /*!< Enable TWI                                                            */
+  __I  uint32_t  RESERVED12;
+  __IO uint32_t  PSELSCL;                           /*!< Pin select for SCL                                                    */
+  __IO uint32_t  PSELSDA;                           /*!< Pin select for SDA                                                    */
+  __I  uint32_t  RESERVED13[2];
+  __I  uint32_t  RXD;                               /*!< RXD register                                                          */
+  __IO uint32_t  TXD;                               /*!< TXD register                                                          */
+  __I  uint32_t  RESERVED14;
+  __IO uint32_t  FREQUENCY;                         /*!< TWI frequency                                                         */
+  __I  uint32_t  RESERVED15[24];
+  __IO uint32_t  ADDRESS;                           /*!< Address used in the TWI transfer                                      */
+} NRF_TWI_Type;
+
+
+/* ================================================================================ */
+/* ================                      NFCT                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief NFC-A compatible radio (NFCT)
+  */
+
+typedef struct {                                    /*!< NFCT Structure                                                        */
+  __O  uint32_t  TASKS_ACTIVATE;                    /*!< Activate NFC peripheral for incoming and outgoing frames, change
+                                                         state to activated                                                    */
+  __O  uint32_t  TASKS_DISABLE;                     /*!< Disable NFC peripheral                                                */
+  __O  uint32_t  TASKS_SENSE;                       /*!< Enable NFC sense field mode, change state to sense mode               */
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start transmission of a outgoing frame, change state to transmit      */
+  __I  uint32_t  RESERVED0[3];
+  __O  uint32_t  TASKS_ENABLERXDATA;                /*!< Initializes the EasyDMA for receive.                                  */
+  __I  uint32_t  RESERVED1;
+  __O  uint32_t  TASKS_GOIDLE;                      /*!< Force state machine to IDLE state                                     */
+  __O  uint32_t  TASKS_GOSLEEP;                     /*!< Force state machine to SLEEP_A state                                  */
+  __I  uint32_t  RESERVED2[53];
+  __IO uint32_t  EVENTS_READY;                      /*!< The NFC peripheral is ready to receive and send frames                */
+  __IO uint32_t  EVENTS_FIELDDETECTED;              /*!< Remote NFC field detected                                             */
+  __IO uint32_t  EVENTS_FIELDLOST;                  /*!< Remote NFC field lost                                                 */
+  __IO uint32_t  EVENTS_TXFRAMESTART;               /*!< Marks the start of the first symbol of a transmitted frame            */
+  __IO uint32_t  EVENTS_TXFRAMEEND;                 /*!< Marks the end of the last transmitted on-air symbol of a frame        */
+  __IO uint32_t  EVENTS_RXFRAMESTART;               /*!< Marks the end of the first symbol of a received frame                 */
+  __IO uint32_t  EVENTS_RXFRAMEEND;                 /*!< Received data have been checked (CRC, parity) and transferred
+                                                         to RAM, and EasyDMA has ended accessing the RX buffer                 */
+  __IO uint32_t  EVENTS_ERROR;                      /*!< NFC error reported. The ERRORSTATUS register contains details
+                                                         on the source of the error.                                           */
+  __I  uint32_t  RESERVED3[2];
+  __IO uint32_t  EVENTS_RXERROR;                    /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains
+                                                         details on the source of the error.                                   */
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.      */
+  __IO uint32_t  EVENTS_ENDTX;                      /*!< Transmission of data in RAM has ended, and EasyDMA has ended
+                                                         accessing the TX buffer                                               */
+  __I  uint32_t  RESERVED4;
+  __IO uint32_t  EVENTS_AUTOCOLRESSTARTED;          /*!< Auto collision resolution process has started                         */
+  __I  uint32_t  RESERVED5[3];
+  __IO uint32_t  EVENTS_COLLISION;                  /*!< NFC Auto collision resolution error reported.                         */
+  __IO uint32_t  EVENTS_SELECTED;                   /*!< NFC Auto collision resolution successfully completed                  */
+  __IO uint32_t  EVENTS_STARTED;                    /*!< EasyDMA is ready to receive or send frames.                           */
+  __I  uint32_t  RESERVED6[43];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED7[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED8[62];
+  __IO uint32_t  ERRORSTATUS;                       /*!< NFC Error Status register                                             */
+  __I  uint32_t  RESERVED9;
+  NFCT_FRAMESTATUS_Type FRAMESTATUS;                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED10[8];
+  __I  uint32_t  CURRENTLOADCTRL;                   /*!< Current value driven to the NFC Load Control                          */
+  __I  uint32_t  RESERVED11[2];
+  __I  uint32_t  FIELDPRESENT;                      /*!< Indicates the presence or not of a valid field                        */
+  __I  uint32_t  RESERVED12[49];
+  __IO uint32_t  FRAMEDELAYMIN;                     /*!< Minimum frame delay                                                   */
+  __IO uint32_t  FRAMEDELAYMAX;                     /*!< Maximum frame delay                                                   */
+  __IO uint32_t  FRAMEDELAYMODE;                    /*!< Configuration register for the Frame Delay Timer                      */
+  __IO uint32_t  PACKETPTR;                         /*!< Packet pointer for TXD and RXD data storage in Data RAM               */
+  __IO uint32_t  MAXLEN;                            /*!< Size of allocated for TXD and RXD data storage buffer in Data
+                                                         RAM                                                                   */
+  NFCT_TXD_Type TXD;                                /*!< Unspecified                                                           */
+  NFCT_RXD_Type RXD;                                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED13[26];
+  __IO uint32_t  NFCID1_LAST;                       /*!< Last NFCID1 part (4, 7 or 10 bytes ID)                                */
+  __IO uint32_t  NFCID1_2ND_LAST;                   /*!< Second last NFCID1 part (7 or 10 bytes ID)                            */
+  __IO uint32_t  NFCID1_3RD_LAST;                   /*!< Third last NFCID1 part (10 bytes ID)                                  */
+  __I  uint32_t  RESERVED14;
+  __IO uint32_t  SENSRES;                           /*!< NFC-A SENS_RES auto-response settings                                 */
+  __IO uint32_t  SELRES;                            /*!< NFC-A SEL_RES auto-response settings                                  */
+} NRF_NFCT_Type;
+
+
+/* ================================================================================ */
+/* ================                     GPIOTE                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief GPIO Tasks and Events (GPIOTE)
+  */
+
+typedef struct {                                    /*!< GPIOTE Structure                                                      */
+  __O  uint32_t  TASKS_OUT[8];                      /*!< Description collection[0]: Task for writing to pin specified
+                                                         in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */
+  __I  uint32_t  RESERVED0[4];
+  __O  uint32_t  TASKS_SET[8];                      /*!< Description collection[0]: Task for writing to pin specified
+                                                         in CONFIG[0].PSEL. Action on pin is to set it high.                   */
+  __I  uint32_t  RESERVED1[4];
+  __O  uint32_t  TASKS_CLR[8];                      /*!< Description collection[0]: Task for writing to pin specified
+                                                         in CONFIG[0].PSEL. Action on pin is to set it low.                    */
+  __I  uint32_t  RESERVED2[32];
+  __IO uint32_t  EVENTS_IN[8];                      /*!< Description collection[0]: Event generated from pin specified
+                                                         in CONFIG[0].PSEL                                                     */
+  __I  uint32_t  RESERVED3[23];
+  __IO uint32_t  EVENTS_PORT;                       /*!< Event generated from multiple input GPIO pins with SENSE mechanism
+                                                         enabled                                                               */
+  __I  uint32_t  RESERVED4[97];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED5[129];
+  __IO uint32_t  CONFIG[8];                         /*!< Description collection[0]: Configuration for OUT[n], SET[n]
+                                                         and CLR[n] tasks and IN[n] event                                      */
+} NRF_GPIOTE_Type;
+
+
+/* ================================================================================ */
+/* ================                      SAADC                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Analog to Digital Converter (SAADC)
+  */
+
+typedef struct {                                    /*!< SAADC Structure                                                       */
+  __O  uint32_t  TASKS_START;                       /*!< Start the ADC and prepare the result buffer in RAM                    */
+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Take one ADC sample, if scan is enabled all channels are sampled      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop the ADC and terminate any on-going conversion                    */
+  __O  uint32_t  TASKS_CALIBRATEOFFSET;             /*!< Starts offset auto-calibration                                        */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_STARTED;                    /*!< The ADC has started                                                   */
+  __IO uint32_t  EVENTS_END;                        /*!< The ADC has filled up the Result buffer                               */
+  __IO uint32_t  EVENTS_DONE;                       /*!< A conversion task has been completed. Depending on the mode,
+                                                         multiple conversions might be needed for a result to be transferred
+                                                          to RAM.                                                              */
+  __IO uint32_t  EVENTS_RESULTDONE;                 /*!< A result is ready to get transferred to RAM.                          */
+  __IO uint32_t  EVENTS_CALIBRATEDONE;              /*!< Calibration is complete                                               */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< The ADC has stopped                                                   */
+  SAADC_EVENTS_CH_Type EVENTS_CH[8];                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED1[106];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[61];
+  __I  uint32_t  STATUS;                            /*!< Status                                                                */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable or disable ADC                                                 */
+  __I  uint32_t  RESERVED4[3];
+  SAADC_CH_Type CH[8];                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5[24];
+  __IO uint32_t  RESOLUTION;                        /*!< Resolution configuration                                              */
+  __IO uint32_t  OVERSAMPLE;                        /*!< Oversampling configuration. OVERSAMPLE should not be combined
+                                                         with SCAN. The RESOLUTION is applied before averaging, thus
+                                                          for high OVERSAMPLE a higher RESOLUTION should be used.              */
+  __IO uint32_t  SAMPLERATE;                        /*!< Controls normal or continuous sample rate                             */
+  __I  uint32_t  RESERVED6[12];
+  SAADC_RESULT_Type RESULT;                         /*!< RESULT EasyDMA channel                                                */
+} NRF_SAADC_Type;
+
+
+/* ================================================================================ */
+/* ================                      TIMER                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Timer/Counter 0 (TIMER)
+  */
+
+typedef struct {                                    /*!< TIMER Structure                                                       */
+  __O  uint32_t  TASKS_START;                       /*!< Start Timer                                                           */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop Timer                                                            */
+  __O  uint32_t  TASKS_COUNT;                       /*!< Increment Timer (Counter mode only)                                   */
+  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear time                                                            */
+  __O  uint32_t  TASKS_SHUTDOWN;                    /*!< Deprecated register - Shut down timer                                 */
+  __I  uint32_t  RESERVED0[11];
+  __O  uint32_t  TASKS_CAPTURE[6];                  /*!< Description collection[0]: Capture Timer value to CC[0] register      */
+  __I  uint32_t  RESERVED1[58];
+  __IO uint32_t  EVENTS_COMPARE[6];                 /*!< Description collection[0]: Compare event on CC[0] match               */
+  __I  uint32_t  RESERVED2[42];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED3[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED4[126];
+  __IO uint32_t  MODE;                              /*!< Timer mode selection                                                  */
+  __IO uint32_t  BITMODE;                           /*!< Configure the number of bits used by the TIMER                        */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  PRESCALER;                         /*!< Timer prescaler register                                              */
+  __I  uint32_t  RESERVED6[11];
+  __IO uint32_t  CC[6];                             /*!< Description collection[0]: Capture/Compare register 0                 */
+} NRF_TIMER_Type;
+
+
+/* ================================================================================ */
+/* ================                       RTC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Real time counter 0 (RTC)
+  */
+
+typedef struct {                                    /*!< RTC Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start RTC COUNTER                                                     */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop RTC COUNTER                                                      */
+  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear RTC COUNTER                                                     */
+  __O  uint32_t  TASKS_TRIGOVRFLW;                  /*!< Set COUNTER to 0xFFFFF0                                               */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_TICK;                       /*!< Event on COUNTER increment                                            */
+  __IO uint32_t  EVENTS_OVRFLW;                     /*!< Event on COUNTER overflow                                             */
+  __I  uint32_t  RESERVED1[14];
+  __IO uint32_t  EVENTS_COMPARE[4];                 /*!< Description collection[0]: Compare event on CC[0] match               */
+  __I  uint32_t  RESERVED2[109];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[13];
+  __IO uint32_t  EVTEN;                             /*!< Enable or disable event routing                                       */
+  __IO uint32_t  EVTENSET;                          /*!< Enable event routing                                                  */
+  __IO uint32_t  EVTENCLR;                          /*!< Disable event routing                                                 */
+  __I  uint32_t  RESERVED4[110];
+  __I  uint32_t  COUNTER;                           /*!< Current COUNTER value                                                 */
+  __IO uint32_t  PRESCALER;                         /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must
+                                                         be written when RTC is stopped                                        */
+  __I  uint32_t  RESERVED5[13];
+  __IO uint32_t  CC[4];                             /*!< Description collection[0]: Compare register 0                         */
+} NRF_RTC_Type;
+
+
+/* ================================================================================ */
+/* ================                      TEMP                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Temperature Sensor (TEMP)
+  */
+
+typedef struct {                                    /*!< TEMP Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Start temperature measurement                                         */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop temperature measurement                                          */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_DATARDY;                    /*!< Temperature measurement complete, data ready                          */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[127];
+  __I  int32_t   TEMP;                              /*!< Temperature in degC (0.25deg steps)                                   */
+  __I  uint32_t  RESERVED3[5];
+  __IO uint32_t  A0;                                /*!< Slope of 1st piece wise linear function                               */
+  __IO uint32_t  A1;                                /*!< Slope of 2nd piece wise linear function                               */
+  __IO uint32_t  A2;                                /*!< Slope of 3rd piece wise linear function                               */
+  __IO uint32_t  A3;                                /*!< Slope of 4th piece wise linear function                               */
+  __IO uint32_t  A4;                                /*!< Slope of 5th piece wise linear function                               */
+  __IO uint32_t  A5;                                /*!< Slope of 6th piece wise linear function                               */
+  __I  uint32_t  RESERVED4[2];
+  __IO uint32_t  B0;                                /*!< y-intercept of 1st piece wise linear function                         */
+  __IO uint32_t  B1;                                /*!< y-intercept of 2nd piece wise linear function                         */
+  __IO uint32_t  B2;                                /*!< y-intercept of 3rd piece wise linear function                         */
+  __IO uint32_t  B3;                                /*!< y-intercept of 4th piece wise linear function                         */
+  __IO uint32_t  B4;                                /*!< y-intercept of 5th piece wise linear function                         */
+  __IO uint32_t  B5;                                /*!< y-intercept of 6th piece wise linear function                         */
+  __I  uint32_t  RESERVED5[2];
+  __IO uint32_t  T0;                                /*!< End point of 1st piece wise linear function                           */
+  __IO uint32_t  T1;                                /*!< End point of 2nd piece wise linear function                           */
+  __IO uint32_t  T2;                                /*!< End point of 3rd piece wise linear function                           */
+  __IO uint32_t  T3;                                /*!< End point of 4th piece wise linear function                           */
+  __IO uint32_t  T4;                                /*!< End point of 5th piece wise linear function                           */
+} NRF_TEMP_Type;
+
+
+/* ================================================================================ */
+/* ================                       RNG                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Random Number Generator (RNG)
+  */
+
+typedef struct {                                    /*!< RNG Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Task starting the random number generator                             */
+  __O  uint32_t  TASKS_STOP;                        /*!< Task stopping the random number generator                             */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_VALRDY;                     /*!< Event being generated for every new random number written to
+                                                         the VALUE register                                                    */
+  __I  uint32_t  RESERVED1[63];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[126];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  VALUE;                             /*!< Output random number                                                  */
+} NRF_RNG_Type;
+
+
+/* ================================================================================ */
+/* ================                       ECB                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief AES ECB Mode Encryption (ECB)
+  */
+
+typedef struct {                                    /*!< ECB Structure                                                         */
+  __O  uint32_t  TASKS_STARTECB;                    /*!< Start ECB block encrypt                                               */
+  __O  uint32_t  TASKS_STOPECB;                     /*!< Abort a possible executing ECB operation                              */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_ENDECB;                     /*!< ECB block encrypt complete                                            */
+  __IO uint32_t  EVENTS_ERRORECB;                   /*!< ECB block encrypt aborted because of a STOPECB task or due to
+                                                         an error                                                              */
+  __I  uint32_t  RESERVED1[127];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  ECBDATAPTR;                        /*!< ECB block encrypt memory pointers                                     */
+} NRF_ECB_Type;
+
+
+/* ================================================================================ */
+/* ================                       CCM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief AES CCM Mode Encryption (CCM)
+  */
+
+typedef struct {                                    /*!< CCM Structure                                                         */
+  __O  uint32_t  TASKS_KSGEN;                       /*!< Start generation of key-stream. This operation will stop by
+                                                         itself when completed.                                                */
+  __O  uint32_t  TASKS_CRYPT;                       /*!< Start encryption/decryption. This operation will stop by itself
+                                                         when completed.                                                       */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop encryption/decryption                                            */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_ENDKSGEN;                   /*!< Key-stream generation complete                                        */
+  __IO uint32_t  EVENTS_ENDCRYPT;                   /*!< Encrypt/decrypt complete                                              */
+  __IO uint32_t  EVENTS_ERROR;                      /*!< CCM error event                                                       */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  MICSTATUS;                         /*!< MIC check result                                                      */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable                                                                */
+  __IO uint32_t  MODE;                              /*!< Operation mode                                                        */
+  __IO uint32_t  CNFPTR;                            /*!< Pointer to data structure holding AES key and NONCE vector            */
+  __IO uint32_t  INPTR;                             /*!< Input pointer                                                         */
+  __IO uint32_t  OUTPTR;                            /*!< Output pointer                                                        */
+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to data area used for temporary storage                       */
+} NRF_CCM_Type;
+
+
+/* ================================================================================ */
+/* ================                       AAR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Accelerated Address Resolver (AAR)
+  */
+
+typedef struct {                                    /*!< AAR Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start resolving addresses based on IRKs specified in the IRK
+                                                         data structure                                                        */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop resolving addresses                                              */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  EVENTS_END;                        /*!< Address resolution procedure complete                                 */
+  __IO uint32_t  EVENTS_RESOLVED;                   /*!< Address resolved                                                      */
+  __IO uint32_t  EVENTS_NOTRESOLVED;                /*!< Address not resolved                                                  */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  STATUS;                            /*!< Resolution status                                                     */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable AAR                                                            */
+  __IO uint32_t  NIRK;                              /*!< Number of IRKs                                                        */
+  __IO uint32_t  IRKPTR;                            /*!< Pointer to IRK data structure                                         */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  ADDRPTR;                           /*!< Pointer to the resolvable address                                     */
+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to data area used for temporary storage                       */
+} NRF_AAR_Type;
+
+
+/* ================================================================================ */
+/* ================                       WDT                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Watchdog Timer (WDT)
+  */
+
+typedef struct {                                    /*!< WDT Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start the watchdog                                                    */
+  __I  uint32_t  RESERVED0[63];
+  __IO uint32_t  EVENTS_TIMEOUT;                    /*!< Watchdog timeout                                                      */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[61];
+  __I  uint32_t  RUNSTATUS;                         /*!< Run status                                                            */
+  __I  uint32_t  REQSTATUS;                         /*!< Request status                                                        */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  CRV;                               /*!< Counter reload value                                                  */
+  __IO uint32_t  RREN;                              /*!< Enable register for reload request registers                          */
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  RESERVED4[60];
+  __O  uint32_t  RR[8];                             /*!< Description collection[0]: Reload request 0                           */
+} NRF_WDT_Type;
+
+
+/* ================================================================================ */
+/* ================                      QDEC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Quadrature Decoder (QDEC)
+  */
+
+typedef struct {                                    /*!< QDEC Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Task starting the quadrature decoder                                  */
+  __O  uint32_t  TASKS_STOP;                        /*!< Task stopping the quadrature decoder                                  */
+  __O  uint32_t  TASKS_READCLRACC;                  /*!< Read and clear ACC and ACCDBL                                         */
+  __O  uint32_t  TASKS_RDCLRACC;                    /*!< Read and clear ACC                                                    */
+  __O  uint32_t  TASKS_RDCLRDBL;                    /*!< Read and clear ACCDBL                                                 */
+  __I  uint32_t  RESERVED0[59];
+  __IO uint32_t  EVENTS_SAMPLERDY;                  /*!< Event being generated for every new sample value written to
+                                                         the SAMPLE register                                                   */
+  __IO uint32_t  EVENTS_REPORTRDY;                  /*!< Non-null report ready                                                 */
+  __IO uint32_t  EVENTS_ACCOF;                      /*!< ACC or ACCDBL register overflow                                       */
+  __IO uint32_t  EVENTS_DBLRDY;                     /*!< Double displacement(s) detected                                       */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< QDEC has been stopped                                                 */
+  __I  uint32_t  RESERVED1[59];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable the quadrature decoder                                         */
+  __IO uint32_t  LEDPOL;                            /*!< LED output pin polarity                                               */
+  __IO uint32_t  SAMPLEPER;                         /*!< Sample period                                                         */
+  __I  int32_t   SAMPLE;                            /*!< Motion sample value                                                   */
+  __IO uint32_t  REPORTPER;                         /*!< Number of samples to be taken before REPORTRDY and DBLRDY events
+                                                         can be generated                                                      */
+  __I  int32_t   ACC;                               /*!< Register accumulating the valid transitions                           */
+  __I  int32_t   ACCREAD;                           /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC
+                                                         task                                                                  */
+  QDEC_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __IO uint32_t  DBFEN;                             /*!< Enable input debounce filters                                         */
+  __I  uint32_t  RESERVED4[5];
+  __IO uint32_t  LEDPRE;                            /*!< Time period the LED is switched ON prior to sampling                  */
+  __I  uint32_t  ACCDBL;                            /*!< Register accumulating the number of detected double transitions       */
+  __I  uint32_t  ACCDBLREAD;                        /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL
+                                                         task                                                                  */
+} NRF_QDEC_Type;
+
+
+/* ================================================================================ */
+/* ================                      COMP                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Comparator (COMP)
+  */
+
+typedef struct {                                    /*!< COMP Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Start comparator                                                      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop comparator                                                       */
+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Sample comparator value                                               */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_READY;                      /*!< COMP is ready and output is valid                                     */
+  __IO uint32_t  EVENTS_DOWN;                       /*!< Downward crossing                                                     */
+  __IO uint32_t  EVENTS_UP;                         /*!< Upward crossing                                                       */
+  __IO uint32_t  EVENTS_CROSS;                      /*!< Downward or upward crossing                                           */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  RESULT;                            /*!< Compare result                                                        */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< COMP enable                                                           */
+  __IO uint32_t  PSEL;                              /*!< Pin select                                                            */
+  __IO uint32_t  REFSEL;                            /*!< Reference source select                                               */
+  __IO uint32_t  EXTREFSEL;                         /*!< External reference select                                             */
+  __I  uint32_t  RESERVED5[8];
+  __IO uint32_t  TH;                                /*!< Threshold configuration for hysteresis unit                           */
+  __IO uint32_t  MODE;                              /*!< Mode configuration                                                    */
+  __IO uint32_t  HYST;                              /*!< Comparator hysteresis enable                                          */
+  __IO uint32_t  ISOURCE;                           /*!< Current source select on analog input                                 */
+} NRF_COMP_Type;
+
+
+/* ================================================================================ */
+/* ================                     LPCOMP                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Low Power Comparator (LPCOMP)
+  */
+
+typedef struct {                                    /*!< LPCOMP Structure                                                      */
+  __O  uint32_t  TASKS_START;                       /*!< Start comparator                                                      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop comparator                                                       */
+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Sample comparator value                                               */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_READY;                      /*!< LPCOMP is ready and output is valid                                   */
+  __IO uint32_t  EVENTS_DOWN;                       /*!< Downward crossing                                                     */
+  __IO uint32_t  EVENTS_UP;                         /*!< Upward crossing                                                       */
+  __IO uint32_t  EVENTS_CROSS;                      /*!< Downward or upward crossing                                           */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  RESULT;                            /*!< Compare result                                                        */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable LPCOMP                                                         */
+  __IO uint32_t  PSEL;                              /*!< Input pin select                                                      */
+  __IO uint32_t  REFSEL;                            /*!< Reference select                                                      */
+  __IO uint32_t  EXTREFSEL;                         /*!< External reference select                                             */
+  __I  uint32_t  RESERVED5[4];
+  __IO uint32_t  ANADETECT;                         /*!< Analog detect configuration                                           */
+  __I  uint32_t  RESERVED6[5];
+  __IO uint32_t  HYST;                              /*!< Comparator hysteresis enable                                          */
+} NRF_LPCOMP_Type;
+
+
+/* ================================================================================ */
+/* ================                       SWI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Software interrupt 0 (SWI)
+  */
+
+typedef struct {                                    /*!< SWI Structure                                                         */
+  __I  uint32_t  UNUSED;                            /*!< Unused.                                                               */
+} NRF_SWI_Type;
+
+
+/* ================================================================================ */
+/* ================                       EGU                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Event Generator Unit 0 (EGU)
+  */
+
+typedef struct {                                    /*!< EGU Structure                                                         */
+  __O  uint32_t  TASKS_TRIGGER[16];                 /*!< Description collection[0]: Trigger 0 for triggering the corresponding
+                                                         TRIGGERED[0] event                                                    */
+  __I  uint32_t  RESERVED0[48];
+  __IO uint32_t  EVENTS_TRIGGERED[16];              /*!< Description collection[0]: Event number 0 generated by triggering
+                                                         the corresponding TRIGGER[0] task                                     */
+  __I  uint32_t  RESERVED1[112];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+} NRF_EGU_Type;
+
+
+/* ================================================================================ */
+/* ================                       PWM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Pulse Width Modulation Unit 0 (PWM)
+  */
+
+typedef struct {                                    /*!< PWM Structure                                                         */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STOP;                        /*!< Stops PWM pulse generation on all channels at the end of current
+                                                         PWM period, and stops sequence playback                               */
+  __O  uint32_t  TASKS_SEQSTART[2];                 /*!< Description collection[0]: Loads the first PWM value on all
+                                                         enabled channels from sequence 0, and starts playing that sequence
+                                                          at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes
+                                                          PWM generation to start it was not running.                          */
+  __O  uint32_t  TASKS_NEXTSTEP;                    /*!< Steps by one value in the current sequence on all enabled channels
+                                                         if DECODER.MODE=NextStep. Does not cause PWM generation to start
+                                                          it was not running.                                                  */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< Response to STOP task, emitted when PWM pulses are no longer
+                                                         generated                                                             */
+  __IO uint32_t  EVENTS_SEQSTARTED[2];              /*!< Description collection[0]: First PWM period started on sequence
+                                                         0                                                                     */
+  __IO uint32_t  EVENTS_SEQEND[2];                  /*!< Description collection[0]: Emitted at end of every sequence
+                                                         0, when last value from RAM has been applied to wave counter          */
+  __IO uint32_t  EVENTS_PWMPERIODEND;               /*!< Emitted at the end of each PWM period                                 */
+  __IO uint32_t  EVENTS_LOOPSDONE;                  /*!< Concatenated sequences have been played the amount of times
+                                                         defined in LOOP.CNT                                                   */
+  __I  uint32_t  RESERVED2[56];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED4[125];
+  __IO uint32_t  ENABLE;                            /*!< PWM module enable register                                            */
+  __IO uint32_t  MODE;                              /*!< Selects operating mode of the wave counter                            */
+  __IO uint32_t  COUNTERTOP;                        /*!< Value up to which the pulse generator counter counts                  */
+  __IO uint32_t  PRESCALER;                         /*!< Configuration for PWM_CLK                                             */
+  __IO uint32_t  DECODER;                           /*!< Configuration of the decoder                                          */
+  __IO uint32_t  LOOP;                              /*!< Amount of playback of a loop                                          */
+  __I  uint32_t  RESERVED5[2];
+  PWM_SEQ_Type SEQ[2];                              /*!< Unspecified                                                           */
+  PWM_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+} NRF_PWM_Type;
+
+
+/* ================================================================================ */
+/* ================                       PDM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM)
+  */
+
+typedef struct {                                    /*!< PDM Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Starts continuous PDM transfer                                        */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stops PDM transfer                                                    */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_STARTED;                    /*!< PDM transfer has started                                              */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< PDM transfer has finished                                             */
+  __IO uint32_t  EVENTS_END;                        /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT
+                                                         (or the last sample after a STOP task has been received) to
+                                                          Data RAM                                                             */
+  __I  uint32_t  RESERVED1[125];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[125];
+  __IO uint32_t  ENABLE;                            /*!< PDM module enable register                                            */
+  __IO uint32_t  PDMCLKCTRL;                        /*!< PDM clock generator control                                           */
+  __IO uint32_t  MODE;                              /*!< Defines the routing of the connected PDM microphones' signals         */
+  __I  uint32_t  RESERVED3[3];
+  __IO uint32_t  GAINL;                             /*!< Left output gain adjustment                                           */
+  __IO uint32_t  GAINR;                             /*!< Right output gain adjustment                                          */
+  __I  uint32_t  RESERVED4[8];
+  PDM_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5[6];
+  PDM_SAMPLE_Type SAMPLE;                           /*!< Unspecified                                                           */
+} NRF_PDM_Type;
+
+
+/* ================================================================================ */
+/* ================                      NVMC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Non Volatile Memory Controller (NVMC)
+  */
+
+typedef struct {                                    /*!< NVMC Structure                                                        */
+  __I  uint32_t  RESERVED0[256];
+  __I  uint32_t  READY;                             /*!< Ready flag                                                            */
+  __I  uint32_t  RESERVED1[64];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  
+  union {
+    __IO uint32_t  ERASEPCR1;                       /*!< Deprecated register - Register for erasing a page in Code area.
+                                                         Equivalent to ERASEPAGE.                                              */
+    __IO uint32_t  ERASEPAGE;                       /*!< Register for erasing a page in Code area                              */
+  };
+  __IO uint32_t  ERASEALL;                          /*!< Register for erasing all non-volatile user memory                     */
+  __IO uint32_t  ERASEPCR0;                         /*!< Deprecated register - Register for erasing a page in Code area.
+                                                         Equivalent to ERASEPAGE.                                              */
+  __IO uint32_t  ERASEUICR;                         /*!< Register for erasing User Information Configuration Registers         */
+  __I  uint32_t  RESERVED2[10];
+  __IO uint32_t  ICACHECNF;                         /*!< I-Code cache configuration register.                                  */
+  __I  uint32_t  RESERVED3;
+  __IO uint32_t  IHIT;                              /*!< I-Code cache hit counter.                                             */
+  __IO uint32_t  IMISS;                             /*!< I-Code cache miss counter.                                            */
+} NRF_NVMC_Type;
+
+
+/* ================================================================================ */
+/* ================                       PPI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Programmable Peripheral Interconnect (PPI)
+  */
+
+typedef struct {                                    /*!< PPI Structure                                                         */
+  PPI_TASKS_CHG_Type TASKS_CHG[6];                  /*!< Channel group tasks                                                   */
+  __I  uint32_t  RESERVED0[308];
+  __IO uint32_t  CHEN;                              /*!< Channel enable register                                               */
+  __IO uint32_t  CHENSET;                           /*!< Channel enable set register                                           */
+  __IO uint32_t  CHENCLR;                           /*!< Channel enable clear register                                         */
+  __I  uint32_t  RESERVED1;
+  PPI_CH_Type CH[20];                               /*!< PPI Channel                                                           */
+  __I  uint32_t  RESERVED2[148];
+  __IO uint32_t  CHG[6];                            /*!< Description collection[0]: Channel group 0                            */
+  __I  uint32_t  RESERVED3[62];
+  PPI_FORK_Type FORK[32];                           /*!< Fork                                                                  */
+} NRF_PPI_Type;
+
+
+/* ================================================================================ */
+/* ================                       MWU                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Memory Watch Unit (MWU)
+  */
+
+typedef struct {                                    /*!< MWU Structure                                                         */
+  __I  uint32_t  RESERVED0[64];
+  MWU_EVENTS_REGION_Type EVENTS_REGION[4];          /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED1[16];
+  MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];        /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED2[100];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[5];
+  __IO uint32_t  NMIEN;                             /*!< Enable or disable non-maskable interrupt                              */
+  __IO uint32_t  NMIENSET;                          /*!< Enable non-maskable interrupt                                         */
+  __IO uint32_t  NMIENCLR;                          /*!< Disable non-maskable interrupt                                        */
+  __I  uint32_t  RESERVED4[53];
+  MWU_PERREGION_Type PERREGION[2];                  /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5[64];
+  __IO uint32_t  REGIONEN;                          /*!< Enable/disable regions watch                                          */
+  __IO uint32_t  REGIONENSET;                       /*!< Enable regions watch                                                  */
+  __IO uint32_t  REGIONENCLR;                       /*!< Disable regions watch                                                 */
+  __I  uint32_t  RESERVED6[57];
+  MWU_REGION_Type REGION[4];                        /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED7[32];
+  MWU_PREGION_Type PREGION[2];                      /*!< Unspecified                                                           */
+} NRF_MWU_Type;
+
+
+/* ================================================================================ */
+/* ================                       I2S                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Inter-IC Sound (I2S)
+  */
+
+typedef struct {                                    /*!< I2S Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Starts continuous I2S transfer. Also starts MCK generator when
+                                                         this is enabled.                                                      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stops I2S transfer. Also stops MCK generator. Triggering this
+                                                         task will cause the {event:STOPPED} event to be generated.            */
+  __I  uint32_t  RESERVED0[63];
+  __IO uint32_t  EVENTS_RXPTRUPD;                   /*!< The RXD.PTR register has been copied to internal double-buffers.
+                                                         When the I2S module is started and RX is enabled, this event
+                                                          will be generated for every RXTXD.MAXCNT words that are received
+                                                          on the SDIN pin.                                                     */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< I2S transfer stopped.                                                 */
+  __I  uint32_t  RESERVED1[2];
+  __IO uint32_t  EVENTS_TXPTRUPD;                   /*!< The TDX.PTR register has been copied to internal double-buffers.
+                                                         When the I2S module is started and TX is enabled, this event
+                                                          will be generated for every RXTXD.MAXCNT words that are sent
+                                                          on the SDOUT pin.                                                    */
+  __I  uint32_t  RESERVED2[122];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable I2S module.                                                    */
+  I2S_CONFIG_Type CONFIG;                           /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED4[3];
+  I2S_RXD_Type RXD;                                 /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5;
+  I2S_TXD_Type TXD;                                 /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED6[3];
+  I2S_RXTXD_Type RXTXD;                             /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED7[3];
+  I2S_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+} NRF_I2S_Type;
+
+
+/* ================================================================================ */
+/* ================                       FPU                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief FPU (FPU)
+  */
+
+typedef struct {                                    /*!< FPU Structure                                                         */
+  __I  uint32_t  UNUSED;                            /*!< Unused.                                                               */
+} NRF_FPU_Type;
+
+
+/* ================================================================================ */
+/* ================                      GPIO                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief GPIO Port 1 (GPIO)
+  */
+
+typedef struct {                                    /*!< GPIO Structure                                                        */
+  __I  uint32_t  RESERVED0[321];
+  __IO uint32_t  OUT;                               /*!< Write GPIO port                                                       */
+  __IO uint32_t  OUTSET;                            /*!< Set individual bits in GPIO port                                      */
+  __IO uint32_t  OUTCLR;                            /*!< Clear individual bits in GPIO port                                    */
+  __I  uint32_t  IN;                                /*!< Read GPIO port                                                        */
+  __IO uint32_t  DIR;                               /*!< Direction of GPIO pins                                                */
+  __IO uint32_t  DIRSET;                            /*!< DIR set register                                                      */
+  __IO uint32_t  DIRCLR;                            /*!< DIR clear register                                                    */
+  __IO uint32_t  LATCH;                             /*!< Latch register indicating what GPIO pins that have met the criteria
+                                                         set in the PIN_CNF[n].SENSE registers                                 */
+  __IO uint32_t  DETECTMODE;                        /*!< Select between default DETECT signal behaviour and LDETECT mode       */
+  __I  uint32_t  RESERVED1[118];
+  __IO uint32_t  PIN_CNF[32];                       /*!< Description collection[0]: Configuration of GPIO pins                 */
+} NRF_GPIO_Type;
+
+
+/* --------------------  End of section using anonymous unions  ------------------- */
+#if defined(__CC_ARM)
+  #pragma pop
+#elif defined(__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+  #pragma warning restore
+#else
+  #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================              Peripheral memory map             ================ */
+/* ================================================================================ */
+
+#define NRF_FICR_BASE                   0x10000000UL
+#define NRF_UICR_BASE                   0x10001000UL
+#define NRF_BPROT_BASE                  0x40000000UL
+#define NRF_POWER_BASE                  0x40000000UL
+#define NRF_CLOCK_BASE                  0x40000000UL
+#define NRF_RADIO_BASE                  0x40001000UL
+#define NRF_UARTE0_BASE                 0x40002000UL
+#define NRF_UART0_BASE                  0x40002000UL
+#define NRF_SPIM0_BASE                  0x40003000UL
+#define NRF_SPIS0_BASE                  0x40003000UL
+#define NRF_TWIM0_BASE                  0x40003000UL
+#define NRF_TWIS0_BASE                  0x40003000UL
+#define NRF_SPI0_BASE                   0x40003000UL
+#define NRF_TWI0_BASE                   0x40003000UL
+#define NRF_SPIM1_BASE                  0x40004000UL
+#define NRF_SPIS1_BASE                  0x40004000UL
+#define NRF_TWIM1_BASE                  0x40004000UL
+#define NRF_TWIS1_BASE                  0x40004000UL
+#define NRF_SPI1_BASE                   0x40004000UL
+#define NRF_TWI1_BASE                   0x40004000UL
+#define NRF_NFCT_BASE                   0x40005000UL
+#define NRF_GPIOTE_BASE                 0x40006000UL
+#define NRF_SAADC_BASE                  0x40007000UL
+#define NRF_TIMER0_BASE                 0x40008000UL
+#define NRF_TIMER1_BASE                 0x40009000UL
+#define NRF_TIMER2_BASE                 0x4000A000UL
+#define NRF_RTC0_BASE                   0x4000B000UL
+#define NRF_TEMP_BASE                   0x4000C000UL
+#define NRF_RNG_BASE                    0x4000D000UL
+#define NRF_ECB_BASE                    0x4000E000UL
+#define NRF_CCM_BASE                    0x4000F000UL
+#define NRF_AAR_BASE                    0x4000F000UL
+#define NRF_WDT_BASE                    0x40010000UL
+#define NRF_RTC1_BASE                   0x40011000UL
+#define NRF_QDEC_BASE                   0x40012000UL
+#define NRF_COMP_BASE                   0x40013000UL
+#define NRF_LPCOMP_BASE                 0x40013000UL
+#define NRF_SWI0_BASE                   0x40014000UL
+#define NRF_EGU0_BASE                   0x40014000UL
+#define NRF_SWI1_BASE                   0x40015000UL
+#define NRF_EGU1_BASE                   0x40015000UL
+#define NRF_SWI2_BASE                   0x40016000UL
+#define NRF_EGU2_BASE                   0x40016000UL
+#define NRF_SWI3_BASE                   0x40017000UL
+#define NRF_EGU3_BASE                   0x40017000UL
+#define NRF_SWI4_BASE                   0x40018000UL
+#define NRF_EGU4_BASE                   0x40018000UL
+#define NRF_SWI5_BASE                   0x40019000UL
+#define NRF_EGU5_BASE                   0x40019000UL
+#define NRF_TIMER3_BASE                 0x4001A000UL
+#define NRF_TIMER4_BASE                 0x4001B000UL
+#define NRF_PWM0_BASE                   0x4001C000UL
+#define NRF_PDM_BASE                    0x4001D000UL
+#define NRF_NVMC_BASE                   0x4001E000UL
+#define NRF_PPI_BASE                    0x4001F000UL
+#define NRF_MWU_BASE                    0x40020000UL
+#define NRF_PWM1_BASE                   0x40021000UL
+#define NRF_PWM2_BASE                   0x40022000UL
+#define NRF_SPIM2_BASE                  0x40023000UL
+#define NRF_SPIS2_BASE                  0x40023000UL
+#define NRF_SPI2_BASE                   0x40023000UL
+#define NRF_RTC2_BASE                   0x40024000UL
+#define NRF_I2S_BASE                    0x40025000UL
+#define NRF_FPU_BASE                    0x40026000UL
+#define NRF_P0_BASE                     0x50000000UL
+
+
+/* ================================================================================ */
+/* ================             Peripheral declaration             ================ */
+/* ================================================================================ */
+
+#define NRF_FICR                        ((NRF_FICR_Type           *) NRF_FICR_BASE)
+#define NRF_UICR                        ((NRF_UICR_Type           *) NRF_UICR_BASE)
+#define NRF_BPROT                       ((NRF_BPROT_Type          *) NRF_BPROT_BASE)
+#define NRF_POWER                       ((NRF_POWER_Type          *) NRF_POWER_BASE)
+#define NRF_CLOCK                       ((NRF_CLOCK_Type          *) NRF_CLOCK_BASE)
+#define NRF_RADIO                       ((NRF_RADIO_Type          *) NRF_RADIO_BASE)
+#define NRF_UARTE0                      ((NRF_UARTE_Type          *) NRF_UARTE0_BASE)
+#define NRF_UART0                       ((NRF_UART_Type           *) NRF_UART0_BASE)
+#define NRF_SPIM0                       ((NRF_SPIM_Type           *) NRF_SPIM0_BASE)
+#define NRF_SPIS0                       ((NRF_SPIS_Type           *) NRF_SPIS0_BASE)
+#define NRF_TWIM0                       ((NRF_TWIM_Type           *) NRF_TWIM0_BASE)
+#define NRF_TWIS0                       ((NRF_TWIS_Type           *) NRF_TWIS0_BASE)
+#define NRF_SPI0                        ((NRF_SPI_Type            *) NRF_SPI0_BASE)
+#define NRF_TWI0                        ((NRF_TWI_Type            *) NRF_TWI0_BASE)
+#define NRF_SPIM1                       ((NRF_SPIM_Type           *) NRF_SPIM1_BASE)
+#define NRF_SPIS1                       ((NRF_SPIS_Type           *) NRF_SPIS1_BASE)
+#define NRF_TWIM1                       ((NRF_TWIM_Type           *) NRF_TWIM1_BASE)
+#define NRF_TWIS1                       ((NRF_TWIS_Type           *) NRF_TWIS1_BASE)
+#define NRF_SPI1                        ((NRF_SPI_Type            *) NRF_SPI1_BASE)
+#define NRF_TWI1                        ((NRF_TWI_Type            *) NRF_TWI1_BASE)
+#define NRF_NFCT                        ((NRF_NFCT_Type           *) NRF_NFCT_BASE)
+#define NRF_GPIOTE                      ((NRF_GPIOTE_Type         *) NRF_GPIOTE_BASE)
+#define NRF_SAADC                       ((NRF_SAADC_Type          *) NRF_SAADC_BASE)
+#define NRF_TIMER0                      ((NRF_TIMER_Type          *) NRF_TIMER0_BASE)
+#define NRF_TIMER1                      ((NRF_TIMER_Type          *) NRF_TIMER1_BASE)
+#define NRF_TIMER2                      ((NRF_TIMER_Type          *) NRF_TIMER2_BASE)
+#define NRF_RTC0                        ((NRF_RTC_Type            *) NRF_RTC0_BASE)
+#define NRF_TEMP                        ((NRF_TEMP_Type           *) NRF_TEMP_BASE)
+#define NRF_RNG                         ((NRF_RNG_Type            *) NRF_RNG_BASE)
+#define NRF_ECB                         ((NRF_ECB_Type            *) NRF_ECB_BASE)
+#define NRF_CCM                         ((NRF_CCM_Type            *) NRF_CCM_BASE)
+#define NRF_AAR                         ((NRF_AAR_Type            *) NRF_AAR_BASE)
+#define NRF_WDT                         ((NRF_WDT_Type            *) NRF_WDT_BASE)
+#define NRF_RTC1                        ((NRF_RTC_Type            *) NRF_RTC1_BASE)
+#define NRF_QDEC                        ((NRF_QDEC_Type           *) NRF_QDEC_BASE)
+#define NRF_COMP                        ((NRF_COMP_Type           *) NRF_COMP_BASE)
+#define NRF_LPCOMP                      ((NRF_LPCOMP_Type         *) NRF_LPCOMP_BASE)
+#define NRF_SWI0                        ((NRF_SWI_Type            *) NRF_SWI0_BASE)
+#define NRF_EGU0                        ((NRF_EGU_Type            *) NRF_EGU0_BASE)
+#define NRF_SWI1                        ((NRF_SWI_Type            *) NRF_SWI1_BASE)
+#define NRF_EGU1                        ((NRF_EGU_Type            *) NRF_EGU1_BASE)
+#define NRF_SWI2                        ((NRF_SWI_Type            *) NRF_SWI2_BASE)
+#define NRF_EGU2                        ((NRF_EGU_Type            *) NRF_EGU2_BASE)
+#define NRF_SWI3                        ((NRF_SWI_Type            *) NRF_SWI3_BASE)
+#define NRF_EGU3                        ((NRF_EGU_Type            *) NRF_EGU3_BASE)
+#define NRF_SWI4                        ((NRF_SWI_Type            *) NRF_SWI4_BASE)
+#define NRF_EGU4                        ((NRF_EGU_Type            *) NRF_EGU4_BASE)
+#define NRF_SWI5                        ((NRF_SWI_Type            *) NRF_SWI5_BASE)
+#define NRF_EGU5                        ((NRF_EGU_Type            *) NRF_EGU5_BASE)
+#define NRF_TIMER3                      ((NRF_TIMER_Type          *) NRF_TIMER3_BASE)
+#define NRF_TIMER4                      ((NRF_TIMER_Type          *) NRF_TIMER4_BASE)
+#define NRF_PWM0                        ((NRF_PWM_Type            *) NRF_PWM0_BASE)
+#define NRF_PDM                         ((NRF_PDM_Type            *) NRF_PDM_BASE)
+#define NRF_NVMC                        ((NRF_NVMC_Type           *) NRF_NVMC_BASE)
+#define NRF_PPI                         ((NRF_PPI_Type            *) NRF_PPI_BASE)
+#define NRF_MWU                         ((NRF_MWU_Type            *) NRF_MWU_BASE)
+#define NRF_PWM1                        ((NRF_PWM_Type            *) NRF_PWM1_BASE)
+#define NRF_PWM2                        ((NRF_PWM_Type            *) NRF_PWM2_BASE)
+#define NRF_SPIM2                       ((NRF_SPIM_Type           *) NRF_SPIM2_BASE)
+#define NRF_SPIS2                       ((NRF_SPIS_Type           *) NRF_SPIS2_BASE)
+#define NRF_SPI2                        ((NRF_SPI_Type            *) NRF_SPI2_BASE)
+#define NRF_RTC2                        ((NRF_RTC_Type            *) NRF_RTC2_BASE)
+#define NRF_I2S                         ((NRF_I2S_Type            *) NRF_I2S_BASE)
+#define NRF_FPU                         ((NRF_FPU_Type            *) NRF_FPU_BASE)
+#define NRF_P0                          ((NRF_GPIO_Type           *) NRF_P0_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group nrf52 */
+/** @} */ /* End of group Nordic Semiconductor */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif  /* nrf52_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52832_peripherals.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,226 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+#ifndef _NRF52832_PERIPHERALS_H
+#define _NRF52832_PERIPHERALS_H
+
+
+/* Floating Point Unit */
+#define FPU_PRESENT
+#define FPU_COUNT 1
+
+/* Systick timer */
+#define SYSTICK_PRESENT
+#define SYSTICK_COUNT 1
+
+/* Software Interrupts */
+#define SWI_PRESENT
+#define SWI_COUNT 6
+
+/* Memory Watch Unit */
+#define MWU_PRESENT
+#define MWU_COUNT 1
+
+/* GPIO */
+#define GPIO_PRESENT
+#define GPIO_COUNT 1
+
+#define P0_PIN_NUM 32
+
+/* MPU and BPROT */
+#define BPROT_PRESENT
+
+#define BPROT_REGIONS_SIZE 4096
+#define BPROT_REGIONS_NUM 128
+
+/* Radio */
+#define RADIO_PRESENT
+#define RADIO_COUNT 1
+
+/* Accelerated Address Resolver */
+#define AAR_PRESENT
+#define AAR_COUNT 1
+
+#define AAR_MAX_IRK_NUM 16
+
+/* AES Electronic CodeBook mode encryption */
+#define ECB_PRESENT
+#define ECB_COUNT 1
+
+/* AES CCM mode encryption */
+#define CCM_PRESENT
+#define CCM_COUNT 1
+
+/* NFC Tag */
+#define NFCT_PRESENT
+#define NFCT_COUNT 1
+
+/* Peripheral to Peripheral Interconnect */
+#define PPI_PRESENT
+#define PPI_COUNT 1
+
+#define PPI_CH_NUM 20
+#define PPI_GROUP_NUM 6
+#define PPI_FEATURE_FORKS_PRESENT
+
+/* Event Generator Unit */
+#define EGU_PRESENT
+#define EGU_COUNT 6
+
+#define EGU0_CH_NUM 16
+#define EGU1_CH_NUM 16
+#define EGU2_CH_NUM 16
+#define EGU3_CH_NUM 16
+#define EGU4_CH_NUM 16
+#define EGU5_CH_NUM 16
+
+/* Timer/Counter */
+#define TIMER_PRESENT
+#define TIMER_COUNT 5
+
+#define TIMER0_MAX_SIZE 32
+#define TIMER1_MAX_SIZE 32
+#define TIMER2_MAX_SIZE 32
+#define TIMER3_MAX_SIZE 32
+#define TIMER4_MAX_SIZE 32
+
+#define TIMER0_CC_NUM 4
+#define TIMER1_CC_NUM 4
+#define TIMER2_CC_NUM 4
+#define TIMER3_CC_NUM 6
+#define TIMER4_CC_NUM 6
+
+/* Real Time Counter */
+#define RTC_PRESENT
+#define RTC_COUNT 3
+
+#define RTC0_CC_NUM 3
+#define RTC1_CC_NUM 4
+#define RTC2_CC_NUM 4
+
+/* RNG */
+#define RNG_PRESENT
+#define RNG_COUNT 1
+
+/* Watchdog Timer */
+#define WDT_PRESENT
+#define WDT_COUNT 1
+
+/* Temperature Sensor */
+#define TEMP_PRESENT
+#define TEMP_COUNT 1
+
+/* Serial Peripheral Interface Master */
+#define SPI_PRESENT
+#define SPI_COUNT 3
+
+/* Serial Peripheral Interface Master with DMA */
+#define SPIM_PRESENT
+#define SPIM_COUNT 3
+
+/* Serial Peripheral Interface Slave with DMA*/
+#define SPIS_PRESENT
+#define SPIS_COUNT 3
+
+/* Two Wire Interface Master */
+#define TWI_PRESENT
+#define TWI_COUNT 2
+
+/* Two Wire Interface Master with DMA */
+#define TWIM_PRESENT
+#define TWIM_COUNT 2
+
+/* Two Wire Interface Slave with DMA */
+#define TWIS_PRESENT
+#define TWIS_COUNT 2
+
+/* Universal Asynchronous Receiver-Transmitter */
+#define UART_PRESENT
+#define UART_COUNT 1
+
+/* Universal Asynchronous Receiver-Transmitter with DMA */
+#define UARTE_PRESENT
+#define UARTE_COUNT 1
+
+/* Quadrature Decoder */
+#define QDEC_PRESENT
+#define QDEC_COUNT 1
+
+/* Successive Approximation Analog to Digital Converter */
+#define SAADC_PRESENT
+#define SAADC_COUNT 1
+
+/* GPIO Tasks and Events */
+#define GPIOTE_PRESENT
+#define GPIOTE_COUNT 1
+
+#define GPIOTE_CH_NUM 8
+
+#define GPIOTE_FEATURE_SET_PRESENT
+#define GPIOTE_FEATURE_CLR_PRESENT
+
+/* Low Power Comparator */
+#define LPCOMP_PRESENT
+#define LPCOMP_COUNT 1
+
+#define LPCOMP_REFSEL_RESOLUTION 16
+
+#define LPCOMP_FEATURE_HYST_PRESENT
+
+/* Comparator */
+#define COMP_PRESENT
+#define COMP_COUNT 1
+
+/* Pulse Width Modulator */
+#define PWM_PRESENT
+#define PWM_COUNT 3
+
+#define PWM0_CH_NUM 4
+#define PWM1_CH_NUM 4
+#define PWM2_CH_NUM 4
+
+/* Pulse Density Modulator */
+#define PDM_PRESENT
+#define PDM_COUNT 1
+
+/* Inter-IC Sound Interface */
+#define I2S_PRESENT
+#define I2S_COUNT 1
+
+
+#endif      // _NRF52832_PERIPHERALS_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52840.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,2417 @@
+
+/****************************************************************************************************//**
+ * @file     nrf52840.h
+ *
+ * @brief    CMSIS Cortex-M4 Peripheral Access Layer Header File for
+ *           nrf52840 from Nordic Semiconductor.
+ *
+ * @version  V1
+ * @date     18. November 2016
+ *
+ * @note     Generated with SVDConv V2.81d 
+ *           from CMSIS SVD File 'nrf52840.svd' Version 1,
+ *
+ * @par      Copyright (c) 2016, Nordic Semiconductor ASA
+ *           All rights reserved.
+ *           
+ *           Redistribution and use in source and binary forms, with or without
+ *           modification, are permitted provided that the following conditions are met:
+ *           
+ *           * Redistributions of source code must retain the above copyright notice, this
+ *           list of conditions and the following disclaimer.
+ *           
+ *           * Redistributions in binary form must reproduce the above copyright notice,
+ *           this list of conditions and the following disclaimer in the documentation
+ *           and/or other materials provided with the distribution.
+ *           
+ *           * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *           contributors may be used to endorse or promote products derived from
+ *           this software without specific prior written permission.
+ *           
+ *           THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *           AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *           IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *           DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ *           FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *           DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ *           SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ *           CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ *           OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *           OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *           
+ *
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup Nordic Semiconductor
+  * @{
+  */
+
+/** @addtogroup nrf52840
+  * @{
+  */
+
+#ifndef NRF52840_H
+#define NRF52840_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum {
+/* -------------------  Cortex-M4 Processor Exceptions Numbers  ------------------- */
+  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */
+  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */
+  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
+  MemoryManagement_IRQn         = -12,              /*!<   4  Memory Management, MPU mismatch, including Access Violation
+                                                         and No Match                                                          */
+  BusFault_IRQn                 = -11,              /*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+                                                         related Fault                                                         */
+  UsageFault_IRQn               = -10,              /*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition    */
+  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */
+  DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */
+  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */
+  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */
+/* ---------------------  nrf52840 Specific Interrupt Numbers  -------------------- */
+  POWER_CLOCK_IRQn              =   0,              /*!<   0  POWER_CLOCK                                                      */
+  RADIO_IRQn                    =   1,              /*!<   1  RADIO                                                            */
+  UARTE0_UART0_IRQn             =   2,              /*!<   2  UARTE0_UART0                                                     */
+  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn=   3,      /*!<   3  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0                                */
+  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn=   4,      /*!<   4  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1                                */
+  NFCT_IRQn                     =   5,              /*!<   5  NFCT                                                             */
+  GPIOTE_IRQn                   =   6,              /*!<   6  GPIOTE                                                           */
+  SAADC_IRQn                    =   7,              /*!<   7  SAADC                                                            */
+  TIMER0_IRQn                   =   8,              /*!<   8  TIMER0                                                           */
+  TIMER1_IRQn                   =   9,              /*!<   9  TIMER1                                                           */
+  TIMER2_IRQn                   =  10,              /*!<  10  TIMER2                                                           */
+  RTC0_IRQn                     =  11,              /*!<  11  RTC0                                                             */
+  TEMP_IRQn                     =  12,              /*!<  12  TEMP                                                             */
+  RNG_IRQn                      =  13,              /*!<  13  RNG                                                              */
+  ECB_IRQn                      =  14,              /*!<  14  ECB                                                              */
+  CCM_AAR_IRQn                  =  15,              /*!<  15  CCM_AAR                                                          */
+  WDT_IRQn                      =  16,              /*!<  16  WDT                                                              */
+  RTC1_IRQn                     =  17,              /*!<  17  RTC1                                                             */
+  QDEC_IRQn                     =  18,              /*!<  18  QDEC                                                             */
+  COMP_LPCOMP_IRQn              =  19,              /*!<  19  COMP_LPCOMP                                                      */
+  SWI0_EGU0_IRQn                =  20,              /*!<  20  SWI0_EGU0                                                        */
+  SWI1_EGU1_IRQn                =  21,              /*!<  21  SWI1_EGU1                                                        */
+  SWI2_EGU2_IRQn                =  22,              /*!<  22  SWI2_EGU2                                                        */
+  SWI3_EGU3_IRQn                =  23,              /*!<  23  SWI3_EGU3                                                        */
+  SWI4_EGU4_IRQn                =  24,              /*!<  24  SWI4_EGU4                                                        */
+  SWI5_EGU5_IRQn                =  25,              /*!<  25  SWI5_EGU5                                                        */
+  TIMER3_IRQn                   =  26,              /*!<  26  TIMER3                                                           */
+  TIMER4_IRQn                   =  27,              /*!<  27  TIMER4                                                           */
+  PWM0_IRQn                     =  28,              /*!<  28  PWM0                                                             */
+  PDM_IRQn                      =  29,              /*!<  29  PDM                                                              */
+  MWU_IRQn                      =  32,              /*!<  32  MWU                                                              */
+  PWM1_IRQn                     =  33,              /*!<  33  PWM1                                                             */
+  PWM2_IRQn                     =  34,              /*!<  34  PWM2                                                             */
+  SPIM2_SPIS2_SPI2_IRQn         =  35,              /*!<  35  SPIM2_SPIS2_SPI2                                                 */
+  RTC2_IRQn                     =  36,              /*!<  36  RTC2                                                             */
+  I2S_IRQn                      =  37,              /*!<  37  I2S                                                              */
+  FPU_IRQn                      =  38,              /*!<  38  FPU                                                              */
+  USBD_IRQn                     =  39,              /*!<  39  USBD                                                             */
+  UARTE1_IRQn                   =  40,              /*!<  40  UARTE1                                                           */
+  QSPI_IRQn                     =  41,              /*!<  41  QSPI                                                             */
+  CRYPTOCELL_IRQn               =  42,              /*!<  42  CRYPTOCELL                                                       */
+  SPIM3_IRQn                    =  43,              /*!<  43  SPIM3                                                            */
+  PWM3_IRQn                     =  45               /*!<  45  PWM3                                                             */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
+#define __CM4_REV                 0x0001            /*!< Cortex-M4 Core Revision                                               */
+#define __MPU_PRESENT                  1            /*!< MPU present or not                                                    */
+#define __NVIC_PRIO_BITS               3            /*!< Number of Bits used for Priority Levels                               */
+#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
+#define __FPU_PRESENT                  1            /*!< FPU present or not                                                    */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm4.h"                               /*!< Cortex-M4 processor and core peripherals                              */
+#include "system_nrf52840.h"                        /*!< nrf52840 System                                                       */
+
+
+/* ================================================================================ */
+/* ================       Device Specific Peripheral Section       ================ */
+/* ================================================================================ */
+
+
+/** @addtogroup Device_Peripheral_Registers
+  * @{
+  */
+
+
+/* -------------------  Start of section using anonymous unions  ------------------ */
+#if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__ICCARM__)
+  #pragma language=extended
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+  #pragma warning 586
+#else
+  #warning Not supported compiler type
+#endif
+
+
+typedef struct {
+  __I  uint32_t  PART;                              /*!< Part code                                                             */
+  __I  uint32_t  VARIANT;                           /*!< Part variant (hardware version and production configuration).         */
+  __I  uint32_t  PACKAGE;                           /*!< Package option                                                        */
+  __I  uint32_t  RAM;                               /*!< RAM variant                                                           */
+  __I  uint32_t  FLASH;                             /*!< Flash variant                                                         */
+  __IO uint32_t  UNUSED0[3];                        /*!< Description collection[0]: Unspecified                                */
+} FICR_INFO_Type;
+
+typedef struct {
+  __I  uint32_t  A0;                                /*!< Slope definition A0.                                                  */
+  __I  uint32_t  A1;                                /*!< Slope definition A1.                                                  */
+  __I  uint32_t  A2;                                /*!< Slope definition A2.                                                  */
+  __I  uint32_t  A3;                                /*!< Slope definition A3.                                                  */
+  __I  uint32_t  A4;                                /*!< Slope definition A4.                                                  */
+  __I  uint32_t  A5;                                /*!< Slope definition A5.                                                  */
+  __I  uint32_t  B0;                                /*!< y-intercept B0.                                                       */
+  __I  uint32_t  B1;                                /*!< y-intercept B1.                                                       */
+  __I  uint32_t  B2;                                /*!< y-intercept B2.                                                       */
+  __I  uint32_t  B3;                                /*!< y-intercept B3.                                                       */
+  __I  uint32_t  B4;                                /*!< y-intercept B4.                                                       */
+  __I  uint32_t  B5;                                /*!< y-intercept B5.                                                       */
+  __I  uint32_t  T0;                                /*!< Segment end T0.                                                       */
+  __I  uint32_t  T1;                                /*!< Segment end T1.                                                       */
+  __I  uint32_t  T2;                                /*!< Segment end T2.                                                       */
+  __I  uint32_t  T3;                                /*!< Segment end T3.                                                       */
+  __I  uint32_t  T4;                                /*!< Segment end T4.                                                       */
+} FICR_TEMP_Type;
+
+typedef struct {
+  __I  uint32_t  TAGHEADER0;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+  __I  uint32_t  TAGHEADER1;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+  __I  uint32_t  TAGHEADER2;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+  __I  uint32_t  TAGHEADER3;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+} FICR_NFC_Type;
+
+typedef struct {
+  __IO uint32_t  POWER;                             /*!< Description cluster[0]: RAM0 power control register                   */
+  __O  uint32_t  POWERSET;                          /*!< Description cluster[0]: RAM0 power control set register               */
+  __O  uint32_t  POWERCLR;                          /*!< Description cluster[0]: RAM0 power control clear register             */
+  __I  uint32_t  RESERVED0;
+} POWER_RAM_Type;
+
+typedef struct {
+  __IO uint32_t  RTS;                               /*!< Pin select for RTS signal                                             */
+  __IO uint32_t  TXD;                               /*!< Pin select for TXD signal                                             */
+  __IO uint32_t  CTS;                               /*!< Pin select for CTS signal                                             */
+  __IO uint32_t  RXD;                               /*!< Pin select for RXD signal                                             */
+} UARTE_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+} UARTE_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+} UARTE_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  RTS;                               /*!< Pin select for RTS                                                    */
+  __IO uint32_t  TXD;                               /*!< Pin select for TXD                                                    */
+  __IO uint32_t  CTS;                               /*!< Pin select for CTS                                                    */
+  __IO uint32_t  RXD;                               /*!< Pin select for RXD                                                    */
+} UART_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */
+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI signal                                            */
+  __IO uint32_t  MISO;                              /*!< Pin select for MISO signal                                            */
+  __IO uint32_t  CSN;                               /*!< Pin select for CSN                                                    */
+} SPIM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} SPIM_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Number of bytes in transmit buffer                                    */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} SPIM_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  RXDELAY;                           /*!< Sample delay for input serial data on MISO                            */
+  __IO uint32_t  CSNDUR;                            /*!< Minimum duration between edge of CSN and edge of SCK and minimum
+                                                         duration CSN must stay high between transactions                      */
+} SPIM_IFTIMING_Type;
+
+typedef struct {
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */
+  __IO uint32_t  MISO;                              /*!< Pin select for MISO signal                                            */
+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI signal                                            */
+  __IO uint32_t  CSN;                               /*!< Pin select for CSN signal                                             */
+} SPIS_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< RXD data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes received in last granted transaction                  */
+} SPIS_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< TXD data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transmitted in last granted transaction               */
+} SPIS_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCL;                               /*!< Pin select for SCL signal                                             */
+  __IO uint32_t  SDA;                               /*!< Pin select for SDA signal                                             */
+} TWIM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} TWIM_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} TWIM_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCL;                               /*!< Pin select for SCL signal                                             */
+  __IO uint32_t  SDA;                               /*!< Pin select for SDA signal                                             */
+} TWIS_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< RXD Data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in RXD buffer                                 */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last RXD transaction               */
+} TWIS_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< TXD Data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in TXD buffer                                 */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last TXD transaction               */
+} TWIS_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */
+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI signal                                            */
+  __IO uint32_t  MISO;                              /*!< Pin select for MISO signal                                            */
+} SPI_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  SCL;                               /*!< Pin select for SCL                                                    */
+  __IO uint32_t  SDA;                               /*!< Pin select for SDA                                                    */
+} TWI_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  RX;                                /*!< Result of last incoming frame                                         */
+} NFCT_FRAMESTATUS_Type;
+
+typedef struct {
+  __IO uint32_t  FRAMECONFIG;                       /*!< Configuration of outgoing frames                                      */
+  __IO uint32_t  AMOUNT;                            /*!< Size of outgoing frame                                                */
+} NFCT_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  FRAMECONFIG;                       /*!< Configuration of incoming frames                                      */
+  __I  uint32_t  AMOUNT;                            /*!< Size of last incoming frame                                           */
+} NFCT_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  LIMITH;                            /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */
+  __IO uint32_t  LIMITL;                            /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */
+} SAADC_EVENTS_CH_Type;
+
+typedef struct {
+  __IO uint32_t  PSELP;                             /*!< Description cluster[0]: Input positive pin selection for CH[0]        */
+  __IO uint32_t  PSELN;                             /*!< Description cluster[0]: Input negative pin selection for CH[0]        */
+  __IO uint32_t  CONFIG;                            /*!< Description cluster[0]: Input configuration for CH[0]                 */
+  __IO uint32_t  LIMIT;                             /*!< Description cluster[0]: High/low limits for event monitoring
+                                                         a channel                                                             */
+} SAADC_CH_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of buffer words to transfer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of buffer words transferred since last START                   */
+} SAADC_RESULT_Type;
+
+typedef struct {
+  __IO uint32_t  LED;                               /*!< Pin select for LED signal                                             */
+  __IO uint32_t  A;                                 /*!< Pin select for A signal                                               */
+  __IO uint32_t  B;                                 /*!< Pin select for B signal                                               */
+} QDEC_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Description cluster[0]: Beginning address in Data RAM of sequence
+                                                         A                                                                     */
+  __IO uint32_t  CNT;                               /*!< Description cluster[0]: Amount of values (duty cycles) in sequence
+                                                         A                                                                     */
+  __IO uint32_t  REFRESH;                           /*!< Description cluster[0]: Amount of additional PWM periods between
+                                                         samples loaded to compare register (load every CNT+1 PWM periods)     */
+  __IO uint32_t  ENDDELAY;                          /*!< Description cluster[0]: Time added after the sequence                 */
+  __I  uint32_t  RESERVED1[4];
+} PWM_SEQ_Type;
+
+typedef struct {
+  __IO uint32_t  OUT[4];                            /*!< Description collection[0]: Output pin select for PWM channel
+                                                         0                                                                     */
+} PWM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  CLK;                               /*!< Pin number configuration for PDM CLK signal                           */
+  __IO uint32_t  DIN;                               /*!< Pin number configuration for PDM DIN signal                           */
+} PDM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< RAM address pointer to write samples to with EasyDMA                  */
+  __IO uint32_t  MAXCNT;                            /*!< Number of samples to allocate memory for in EasyDMA mode              */
+} PDM_SAMPLE_Type;
+
+typedef struct {
+  __IO uint32_t  ADDR;                              /*!< Description cluster[0]: Configure the word-aligned start address
+                                                         of region 0 to protect                                                */
+  __IO uint32_t  SIZE;                              /*!< Description cluster[0]: Size of region to protect counting from
+                                                         address ACL[0].ADDR. Write '0' as no effect.                          */
+  __IO uint32_t  PERM;                              /*!< Description cluster[0]: Access permissions for region 0 as defined
+                                                         by start address ACL[0].ADDR and size ACL[0].SIZE                     */
+  __IO uint32_t  UNUSED0;                           /*!< Unspecified                                                           */
+} ACL_ACL_Type;
+
+typedef struct {
+  __O  uint32_t  EN;                                /*!< Description cluster[0]: Enable channel group 0                        */
+  __O  uint32_t  DIS;                               /*!< Description cluster[0]: Disable channel group 0                       */
+} PPI_TASKS_CHG_Type;
+
+typedef struct {
+  __IO uint32_t  EEP;                               /*!< Description cluster[0]: Channel 0 event end-point                     */
+  __IO uint32_t  TEP;                               /*!< Description cluster[0]: Channel 0 task end-point                      */
+} PPI_CH_Type;
+
+typedef struct {
+  __IO uint32_t  TEP;                               /*!< Description cluster[0]: Channel 0 task end-point                      */
+} PPI_FORK_Type;
+
+typedef struct {
+  __IO uint32_t  WA;                                /*!< Description cluster[0]: Write access to region 0 detected             */
+  __IO uint32_t  RA;                                /*!< Description cluster[0]: Read access to region 0 detected              */
+} MWU_EVENTS_REGION_Type;
+
+typedef struct {
+  __IO uint32_t  WA;                                /*!< Description cluster[0]: Write access to peripheral region 0
+                                                         detected                                                              */
+  __IO uint32_t  RA;                                /*!< Description cluster[0]: Read access to peripheral region 0 detected   */
+} MWU_EVENTS_PREGION_Type;
+
+typedef struct {
+  __IO uint32_t  SUBSTATWA;                         /*!< Description cluster[0]: Source of event/interrupt in region
+                                                         0, write access detected while corresponding subregion was enabled
+                                                          for watching                                                         */
+  __IO uint32_t  SUBSTATRA;                         /*!< Description cluster[0]: Source of event/interrupt in region
+                                                         0, read access detected while corresponding subregion was enabled
+                                                          for watching                                                         */
+} MWU_PERREGION_Type;
+
+typedef struct {
+  __IO uint32_t  START;                             /*!< Description cluster[0]: Start address for region 0                    */
+  __IO uint32_t  END;                               /*!< Description cluster[0]: End address of region 0                       */
+  __I  uint32_t  RESERVED2[2];
+} MWU_REGION_Type;
+
+typedef struct {
+  __I  uint32_t  START;                             /*!< Description cluster[0]: Reserved for future use                       */
+  __I  uint32_t  END;                               /*!< Description cluster[0]: Reserved for future use                       */
+  __IO uint32_t  SUBS;                              /*!< Description cluster[0]: Subregions of region 0                        */
+  __I  uint32_t  RESERVED3;
+} MWU_PREGION_Type;
+
+typedef struct {
+  __IO uint32_t  MODE;                              /*!< I2S mode.                                                             */
+  __IO uint32_t  RXEN;                              /*!< Reception (RX) enable.                                                */
+  __IO uint32_t  TXEN;                              /*!< Transmission (TX) enable.                                             */
+  __IO uint32_t  MCKEN;                             /*!< Master clock generator enable.                                        */
+  __IO uint32_t  MCKFREQ;                           /*!< Master clock generator frequency.                                     */
+  __IO uint32_t  RATIO;                             /*!< MCK / LRCK ratio.                                                     */
+  __IO uint32_t  SWIDTH;                            /*!< Sample width.                                                         */
+  __IO uint32_t  ALIGN;                             /*!< Alignment of sample within a frame.                                   */
+  __IO uint32_t  FORMAT;                            /*!< Frame format.                                                         */
+  __IO uint32_t  CHANNELS;                          /*!< Enable channels.                                                      */
+} I2S_CONFIG_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Receive buffer RAM start address.                                     */
+} I2S_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Transmit buffer RAM start address.                                    */
+} I2S_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  MAXCNT;                            /*!< Size of RXD and TXD buffers.                                          */
+} I2S_RXTXD_Type;
+
+typedef struct {
+  __IO uint32_t  MCK;                               /*!< Pin select for MCK signal.                                            */
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK signal.                                            */
+  __IO uint32_t  LRCK;                              /*!< Pin select for LRCK signal.                                           */
+  __IO uint32_t  SDIN;                              /*!< Pin select for SDIN signal.                                           */
+  __IO uint32_t  SDOUT;                             /*!< Pin select for SDOUT signal.                                          */
+} I2S_PSEL_Type;
+
+typedef struct {
+  __I  uint32_t  EPIN[8];                           /*!< Description collection[0]: IN endpoint halted status. Can be
+                                                         used as is as response to a GetStatus() request to endpoint.          */
+  __I  uint32_t  RESERVED4;
+  __I  uint32_t  EPOUT[8];                          /*!< Description collection[0]: OUT endpoint halted status. Can be
+                                                         used as is as response to a GetStatus() request to endpoint.          */
+} USBD_HALTED_Type;
+
+typedef struct {
+  __IO uint32_t  EPOUT[8];                          /*!< Description collection[0]: Amount of bytes received last in
+                                                         the data stage of this OUT endpoint                                   */
+  __IO uint32_t  ISOOUT;                            /*!< Amount of bytes received last on this iso OUT data endpoint           */
+} USBD_SIZE_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Description cluster[0]: Data pointer                                  */
+  __IO uint32_t  MAXCNT;                            /*!< Description cluster[0]: Maximum number of bytes to transfer           */
+  __I  uint32_t  AMOUNT;                            /*!< Description cluster[0]: Number of bytes transferred in the last
+                                                         transaction                                                           */
+  __I  uint32_t  RESERVED5[2];
+} USBD_EPIN_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes to transfer                                   */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+} USBD_ISOIN_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Description cluster[0]: Data pointer                                  */
+  __IO uint32_t  MAXCNT;                            /*!< Description cluster[0]: Maximum number of bytes to transfer           */
+  __I  uint32_t  AMOUNT;                            /*!< Description cluster[0]: Number of bytes transferred in the last
+                                                         transaction                                                           */
+  __I  uint32_t  RESERVED6[2];
+} USBD_EPOUT_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes to transfer                                   */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+} USBD_ISOOUT_Type;
+
+typedef struct {
+  __IO uint32_t  SRC;                               /*!< Flash memory source address                                           */
+  __IO uint32_t  DST;                               /*!< RAM destination address                                               */
+  __IO uint32_t  CNT;                               /*!< Read transfer length                                                  */
+} QSPI_READ_Type;
+
+typedef struct {
+  __IO uint32_t  DST;                               /*!< Flash destination address                                             */
+  __IO uint32_t  SRC;                               /*!< RAM source address                                                    */
+  __IO uint32_t  CNT;                               /*!< Write transfer length                                                 */
+} QSPI_WRITE_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Start address of flash block to be erased                             */
+  __IO uint32_t  LEN;                               /*!< Size of block to be erased.                                           */
+} QSPI_ERASE_Type;
+
+typedef struct {
+  __IO uint32_t  SCK;                               /*!< Pin select for serial clock SCK                                       */
+  __IO uint32_t  CSN;                               /*!< Pin select for chip select signal CSN.                                */
+  __I  uint32_t  RESERVED7;
+  __IO uint32_t  IO0;                               /*!< Pin select for serial data MOSI/IO0.                                  */
+  __IO uint32_t  IO1;                               /*!< Pin select for serial data MISO/IO1.                                  */
+  __IO uint32_t  IO2;                               /*!< Pin select for serial data IO2.                                       */
+  __IO uint32_t  IO3;                               /*!< Pin select for serial data IO3.                                       */
+} QSPI_PSEL_Type;
+
+
+/* ================================================================================ */
+/* ================                      FICR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Factory Information Configuration Registers (FICR)
+  */
+
+typedef struct {                                    /*!< FICR Structure                                                        */
+  __I  uint32_t  RESERVED0[4];
+  __I  uint32_t  CODEPAGESIZE;                      /*!< Code memory page size                                                 */
+  __I  uint32_t  CODESIZE;                          /*!< Code memory size                                                      */
+  __I  uint32_t  RESERVED1[18];
+  __I  uint32_t  DEVICEID[2];                       /*!< Description collection[0]: Device identifier                          */
+  __I  uint32_t  RESERVED2[6];
+  __I  uint32_t  ER[4];                             /*!< Description collection[0]: Encryption root, word 0                    */
+  __I  uint32_t  IR[4];                             /*!< Description collection[0]: Identity Root, word 0                      */
+  __I  uint32_t  DEVICEADDRTYPE;                    /*!< Device address type                                                   */
+  __I  uint32_t  DEVICEADDR[2];                     /*!< Description collection[0]: Device address 0                           */
+  __I  uint32_t  RESERVED3[21];
+  FICR_INFO_Type INFO;                              /*!< Device info                                                           */
+  __I  uint32_t  RESERVED4[185];
+  FICR_TEMP_Type TEMP;                              /*!< Registers storing factory TEMP module linearization coefficients      */
+  __I  uint32_t  RESERVED5[2];
+  FICR_NFC_Type NFC;                                /*!< Unspecified                                                           */
+} NRF_FICR_Type;
+
+
+/* ================================================================================ */
+/* ================                      UICR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief User Information Configuration Registers (UICR)
+  */
+
+typedef struct {                                    /*!< UICR Structure                                                        */
+  __IO uint32_t  UNUSED0;                           /*!< Unspecified                                                           */
+  __IO uint32_t  UNUSED1;                           /*!< Unspecified                                                           */
+  __IO uint32_t  UNUSED2;                           /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t  UNUSED3;                           /*!< Unspecified                                                           */
+  __IO uint32_t  NRFFW[15];                         /*!< Description collection[0]: Reserved for Nordic firmware design        */
+  __IO uint32_t  NRFHW[12];                         /*!< Description collection[0]: Reserved for Nordic hardware design        */
+  __IO uint32_t  CUSTOMER[32];                      /*!< Description collection[0]: Reserved for customer                      */
+  __I  uint32_t  RESERVED1[64];
+  __IO uint32_t  PSELRESET[2];                      /*!< Description collection[0]: Mapping of the nRESET function             */
+  __IO uint32_t  APPROTECT;                         /*!< Access port protection                                                */
+  __IO uint32_t  NFCPINS;                           /*!< Setting of pins dedicated to NFC functionality: NFC antenna
+                                                         or GPIO                                                               */
+  __I  uint32_t  RESERVED2[60];
+  __IO uint32_t  EXTSUPPLY;                         /*!< Enable external circuitry to be supplied from VDD pin. Applicable
+                                                         in 'High voltage mode' only.                                          */
+  __IO uint32_t  REGOUT0;                           /*!< GPIO reference voltage / external output supply voltage in 'High
+                                                         voltage mode'.                                                        */
+} NRF_UICR_Type;
+
+
+/* ================================================================================ */
+/* ================                      POWER                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Power control (POWER)
+  */
+
+typedef struct {                                    /*!< POWER Structure                                                       */
+  __I  uint32_t  RESERVED0[30];
+  __O  uint32_t  TASKS_CONSTLAT;                    /*!< Enable constant latency mode                                          */
+  __O  uint32_t  TASKS_LOWPWR;                      /*!< Enable low power mode (variable latency)                              */
+  __I  uint32_t  RESERVED1[34];
+  __IO uint32_t  EVENTS_POFWARN;                    /*!< Power failure warning                                                 */
+  __I  uint32_t  RESERVED2[2];
+  __IO uint32_t  EVENTS_SLEEPENTER;                 /*!< CPU entered WFI/WFE sleep                                             */
+  __IO uint32_t  EVENTS_SLEEPEXIT;                  /*!< CPU exited WFI/WFE sleep                                              */
+  __IO uint32_t  EVENTS_USBDETECTED;                /*!< Voltage supply detected on VBUS                                       */
+  __IO uint32_t  EVENTS_USBREMOVED;                 /*!< Voltage supply removed from VBUS                                      */
+  __IO uint32_t  EVENTS_USBPWRRDY;                  /*!< USB 3.3 V supply ready                                                */
+  __I  uint32_t  RESERVED3[119];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED4[61];
+  __IO uint32_t  RESETREAS;                         /*!< Reset reason                                                          */
+  __I  uint32_t  RESERVED5[9];
+  __I  uint32_t  RAMSTATUS;                         /*!< Deprecated register - RAM status register                             */
+  __I  uint32_t  RESERVED6[3];
+  __I  uint32_t  USBREGSTATUS;                      /*!< USB supply status                                                     */
+  __I  uint32_t  RESERVED7[49];
+  __O  uint32_t  SYSTEMOFF;                         /*!< System OFF register                                                   */
+  __I  uint32_t  RESERVED8[3];
+  __IO uint32_t  POFCON;                            /*!< Power failure comparator configuration                                */
+  __I  uint32_t  RESERVED9[2];
+  __IO uint32_t  GPREGRET;                          /*!< General purpose retention register                                    */
+  __IO uint32_t  GPREGRET2;                         /*!< General purpose retention register                                    */
+  __I  uint32_t  RESERVED10[21];
+  __IO uint32_t  DCDCEN;                            /*!< Enable DC/DC converter for REG1 stage.                                */
+  __I  uint32_t  RESERVED11;
+  __IO uint32_t  DCDCEN0;                           /*!< Enable DC/DC converter for REG0 stage.                                */
+  __I  uint32_t  RESERVED12[47];
+  __I  uint32_t  MAINREGSTATUS;                     /*!< Main supply status                                                    */
+  __I  uint32_t  RESERVED13[175];
+  POWER_RAM_Type RAM[9];                            /*!< Unspecified                                                           */
+} NRF_POWER_Type;
+
+
+/* ================================================================================ */
+/* ================                      CLOCK                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Clock control (CLOCK)
+  */
+
+typedef struct {                                    /*!< CLOCK Structure                                                       */
+  __O  uint32_t  TASKS_HFCLKSTART;                  /*!< Start HFCLK crystal oscillator                                        */
+  __O  uint32_t  TASKS_HFCLKSTOP;                   /*!< Stop HFCLK crystal oscillator                                         */
+  __O  uint32_t  TASKS_LFCLKSTART;                  /*!< Start LFCLK source                                                    */
+  __O  uint32_t  TASKS_LFCLKSTOP;                   /*!< Stop LFCLK source                                                     */
+  __O  uint32_t  TASKS_CAL;                         /*!< Start calibration of LFRC or LFULP oscillator                         */
+  __O  uint32_t  TASKS_CTSTART;                     /*!< Start calibration timer                                               */
+  __O  uint32_t  TASKS_CTSTOP;                      /*!< Stop calibration timer                                                */
+  __I  uint32_t  RESERVED0[57];
+  __IO uint32_t  EVENTS_HFCLKSTARTED;               /*!< HFCLK oscillator started                                              */
+  __IO uint32_t  EVENTS_LFCLKSTARTED;               /*!< LFCLK started                                                         */
+  __I  uint32_t  RESERVED1;
+  __IO uint32_t  EVENTS_DONE;                       /*!< Calibration of LFCLK RC oscillator complete event                     */
+  __IO uint32_t  EVENTS_CTTO;                       /*!< Calibration timer timeout                                             */
+  __I  uint32_t  RESERVED2[124];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[63];
+  __I  uint32_t  HFCLKRUN;                          /*!< Status indicating that HFCLKSTART task has been triggered             */
+  __I  uint32_t  HFCLKSTAT;                         /*!< HFCLK status                                                          */
+  __I  uint32_t  RESERVED4;
+  __I  uint32_t  LFCLKRUN;                          /*!< Status indicating that LFCLKSTART task has been triggered             */
+  __I  uint32_t  LFCLKSTAT;                         /*!< LFCLK status                                                          */
+  __I  uint32_t  LFCLKSRCCOPY;                      /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered     */
+  __I  uint32_t  RESERVED5[62];
+  __IO uint32_t  LFCLKSRC;                          /*!< Clock source for the LFCLK                                            */
+  __I  uint32_t  RESERVED6[7];
+  __IO uint32_t  CTIV;                              /*!< Calibration timer interval                                            */
+  __I  uint32_t  RESERVED7[8];
+  __IO uint32_t  TRACECONFIG;                       /*!< Clocking options for the Trace Port debug interface                   */
+} NRF_CLOCK_Type;
+
+
+/* ================================================================================ */
+/* ================                      RADIO                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief 2.4 GHz Radio (RADIO)
+  */
+
+typedef struct {                                    /*!< RADIO Structure                                                       */
+  __O  uint32_t  TASKS_TXEN;                        /*!< Enable RADIO in TX mode                                               */
+  __O  uint32_t  TASKS_RXEN;                        /*!< Enable RADIO in RX mode                                               */
+  __O  uint32_t  TASKS_START;                       /*!< Start RADIO                                                           */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop RADIO                                                            */
+  __O  uint32_t  TASKS_DISABLE;                     /*!< Disable RADIO                                                         */
+  __O  uint32_t  TASKS_RSSISTART;                   /*!< Start the RSSI and take one single sample of the receive signal
+                                                         strength.                                                             */
+  __O  uint32_t  TASKS_RSSISTOP;                    /*!< Stop the RSSI measurement                                             */
+  __O  uint32_t  TASKS_BCSTART;                     /*!< Start the bit counter                                                 */
+  __O  uint32_t  TASKS_BCSTOP;                      /*!< Stop the bit counter                                                  */
+  __O  uint32_t  TASKS_EDSTART;                     /*!< Start the Energy Detect measurement used in IEEE 802.15.4 mode        */
+  __O  uint32_t  TASKS_EDSTOP;                      /*!< Stop the Energy Detect measurement                                    */
+  __O  uint32_t  TASKS_CCASTART;                    /*!< Start the Clear Channel Assessment used in IEEE 802.15.4 mode         */
+  __O  uint32_t  TASKS_CCASTOP;                     /*!< Stop the Clear Channel Assessment                                     */
+  __I  uint32_t  RESERVED0[51];
+  __IO uint32_t  EVENTS_READY;                      /*!< RADIO has ramped up and is ready to be started                        */
+  __IO uint32_t  EVENTS_ADDRESS;                    /*!< Address sent or received                                              */
+  __IO uint32_t  EVENTS_PAYLOAD;                    /*!< Packet payload sent or received                                       */
+  __IO uint32_t  EVENTS_END;                        /*!< Packet sent or received                                               */
+  __IO uint32_t  EVENTS_DISABLED;                   /*!< RADIO has been disabled                                               */
+  __IO uint32_t  EVENTS_DEVMATCH;                   /*!< A device address match occurred on the last received packet           */
+  __IO uint32_t  EVENTS_DEVMISS;                    /*!< No device address match occurred on the last received packet          */
+  __IO uint32_t  EVENTS_RSSIEND;                    /*!< Sampling of receive signal strength complete.                         */
+  __I  uint32_t  RESERVED1[2];
+  __IO uint32_t  EVENTS_BCMATCH;                    /*!< Bit counter reached bit count value.                                  */
+  __I  uint32_t  RESERVED2;
+  __IO uint32_t  EVENTS_CRCOK;                      /*!< Packet received with CRC ok                                           */
+  __IO uint32_t  EVENTS_CRCERROR;                   /*!< Packet received with CRC error                                        */
+  __IO uint32_t  EVENTS_FRAMESTART;                 /*!< IEEE 802.15.4 length field received                                   */
+  __IO uint32_t  EVENTS_EDEND;                      /*!< Sampling of Energy Detection complete. A new ED sample is ready
+                                                         for readout from the RADIO.EDSAMPLE register                          */
+  __IO uint32_t  EVENTS_EDSTOPPED;                  /*!< The sampling of Energy Detection has stopped                          */
+  __IO uint32_t  EVENTS_CCAIDLE;                    /*!< Wireless medium in idle - clear to send                               */
+  __IO uint32_t  EVENTS_CCABUSY;                    /*!< Wireless medium busy - do not send                                    */
+  __IO uint32_t  EVENTS_CCASTOPPED;                 /*!< The CCA has stopped                                                   */
+  __IO uint32_t  EVENTS_RATEBOOST;                  /*!< Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit
+                                                         to Ble_LR500Kbit.                                                     */
+  __IO uint32_t  EVENTS_TXREADY;                    /*!< RADIO has ramped up and is ready to be started TX path                */
+  __IO uint32_t  EVENTS_RXREADY;                    /*!< RADIO has ramped up and is ready to be started RX path                */
+  __IO uint32_t  EVENTS_MHRMATCH;                   /*!< MAC Header match found.                                               */
+  __I  uint32_t  RESERVED3[40];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED4[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED5[61];
+  __I  uint32_t  CRCSTATUS;                         /*!< CRC status                                                            */
+  __I  uint32_t  RESERVED6;
+  __I  uint32_t  RXMATCH;                           /*!< Received address                                                      */
+  __I  uint32_t  RXCRC;                             /*!< CRC field of previously received packet                               */
+  __I  uint32_t  DAI;                               /*!< Device address match index                                            */
+  __I  uint32_t  RESERVED7[60];
+  __IO uint32_t  PACKETPTR;                         /*!< Packet pointer                                                        */
+  __IO uint32_t  FREQUENCY;                         /*!< Frequency                                                             */
+  __IO uint32_t  TXPOWER;                           /*!< Output power                                                          */
+  __IO uint32_t  MODE;                              /*!< Data rate and modulation                                              */
+  __IO uint32_t  PCNF0;                             /*!< Packet configuration register 0                                       */
+  __IO uint32_t  PCNF1;                             /*!< Packet configuration register 1                                       */
+  __IO uint32_t  BASE0;                             /*!< Base address 0                                                        */
+  __IO uint32_t  BASE1;                             /*!< Base address 1                                                        */
+  __IO uint32_t  PREFIX0;                           /*!< Prefixes bytes for logical addresses 0-3                              */
+  __IO uint32_t  PREFIX1;                           /*!< Prefixes bytes for logical addresses 4-7                              */
+  __IO uint32_t  TXADDRESS;                         /*!< Transmit address select                                               */
+  __IO uint32_t  RXADDRESSES;                       /*!< Receive address select                                                */
+  __IO uint32_t  CRCCNF;                            /*!< CRC configuration                                                     */
+  __IO uint32_t  CRCPOLY;                           /*!< CRC polynomial                                                        */
+  __IO uint32_t  CRCINIT;                           /*!< CRC initial value                                                     */
+  __I  uint32_t  RESERVED8;
+  __IO uint32_t  TIFS;                              /*!< Inter Frame Spacing in us                                             */
+  __I  uint32_t  RSSISAMPLE;                        /*!< RSSI sample                                                           */
+  __I  uint32_t  RESERVED9;
+  __I  uint32_t  STATE;                             /*!< Current radio state                                                   */
+  __IO uint32_t  DATAWHITEIV;                       /*!< Data whitening initial value                                          */
+  __I  uint32_t  RESERVED10[2];
+  __IO uint32_t  BCC;                               /*!< Bit counter compare                                                   */
+  __I  uint32_t  RESERVED11[39];
+  __IO uint32_t  DAB[8];                            /*!< Description collection[0]: Device address base segment 0              */
+  __IO uint32_t  DAP[8];                            /*!< Description collection[0]: Device address prefix 0                    */
+  __IO uint32_t  DACNF;                             /*!< Device address match configuration                                    */
+  __IO uint32_t  MHRMATCHCONF;                      /*!< Search Pattern Configuration                                          */
+  __IO uint32_t  MHRMATCHMAS;                       /*!< Pattern mask                                                          */
+  __I  uint32_t  RESERVED12;
+  __IO uint32_t  MODECNF0;                          /*!< Radio mode configuration register 0                                   */
+  __I  uint32_t  RESERVED13[3];
+  __IO uint32_t  SFD;                               /*!< IEEE 802.15.4 Start of Frame Delimiter                                */
+  __IO uint32_t  EDCNT;                             /*!< IEEE 802.15.4 Energy Detect Loop Count                                */
+  __IO uint32_t  EDSAMPLE;                          /*!< IEEE 802.15.4 Energy Detect Level                                     */
+  __IO uint32_t  CCACTRL;                           /*!< IEEE 802.15.4 Clear Channel Assessment Control                        */
+  __I  uint32_t  RESERVED14[611];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control                                              */
+} NRF_RADIO_Type;
+
+
+/* ================================================================================ */
+/* ================                      UARTE                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief UART with EasyDMA 0 (UARTE)
+  */
+
+typedef struct {                                    /*!< UARTE Structure                                                       */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start UART receiver                                                   */
+  __O  uint32_t  TASKS_STOPRX;                      /*!< Stop UART receiver                                                    */
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start UART transmitter                                                */
+  __O  uint32_t  TASKS_STOPTX;                      /*!< Stop UART transmitter                                                 */
+  __I  uint32_t  RESERVED0[7];
+  __O  uint32_t  TASKS_FLUSHRX;                     /*!< Flush RX FIFO into RX buffer                                          */
+  __I  uint32_t  RESERVED1[52];
+  __IO uint32_t  EVENTS_CTS;                        /*!< CTS is activated (set low). Clear To Send.                            */
+  __IO uint32_t  EVENTS_NCTS;                       /*!< CTS is deactivated (set high). Not Clear To Send.                     */
+  __IO uint32_t  EVENTS_RXDRDY;                     /*!< Data received in RXD (but potentially not yet transferred to
+                                                         Data RAM)                                                             */
+  __I  uint32_t  RESERVED2;
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< Receive buffer is filled up                                           */
+  __I  uint32_t  RESERVED3[2];
+  __IO uint32_t  EVENTS_TXDRDY;                     /*!< Data sent from TXD                                                    */
+  __IO uint32_t  EVENTS_ENDTX;                      /*!< Last TX byte transmitted                                              */
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Error detected                                                        */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_RXTO;                       /*!< Receiver timeout                                                      */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  EVENTS_RXSTARTED;                  /*!< UART receiver has started                                             */
+  __IO uint32_t  EVENTS_TXSTARTED;                  /*!< UART transmitter has started                                          */
+  __I  uint32_t  RESERVED6;
+  __IO uint32_t  EVENTS_TXSTOPPED;                  /*!< Transmitter stopped                                                   */
+  __I  uint32_t  RESERVED7[41];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[93];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source Note : this register is read / write one to clear.       */
+  __I  uint32_t  RESERVED10[31];
+  __IO uint32_t  ENABLE;                            /*!< Enable UART                                                           */
+  __I  uint32_t  RESERVED11;
+  UARTE_PSEL_Type PSEL;                             /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[3];
+  __IO uint32_t  BAUDRATE;                          /*!< Baud rate. Accuracy depends on the HFCLK source selected.             */
+  __I  uint32_t  RESERVED13[3];
+  UARTE_RXD_Type RXD;                               /*!< RXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED14;
+  UARTE_TXD_Type TXD;                               /*!< TXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED15[7];
+  __IO uint32_t  CONFIG;                            /*!< Configuration of parity and hardware flow control                     */
+} NRF_UARTE_Type;
+
+
+/* ================================================================================ */
+/* ================                      UART                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Universal Asynchronous Receiver/Transmitter (UART)
+  */
+
+typedef struct {                                    /*!< UART Structure                                                        */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start UART receiver                                                   */
+  __O  uint32_t  TASKS_STOPRX;                      /*!< Stop UART receiver                                                    */
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start UART transmitter                                                */
+  __O  uint32_t  TASKS_STOPTX;                      /*!< Stop UART transmitter                                                 */
+  __I  uint32_t  RESERVED0[3];
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend UART                                                          */
+  __I  uint32_t  RESERVED1[56];
+  __IO uint32_t  EVENTS_CTS;                        /*!< CTS is activated (set low). Clear To Send.                            */
+  __IO uint32_t  EVENTS_NCTS;                       /*!< CTS is deactivated (set high). Not Clear To Send.                     */
+  __IO uint32_t  EVENTS_RXDRDY;                     /*!< Data received in RXD                                                  */
+  __I  uint32_t  RESERVED2[4];
+  __IO uint32_t  EVENTS_TXDRDY;                     /*!< Data sent from TXD                                                    */
+  __I  uint32_t  RESERVED3;
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Error detected                                                        */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_RXTO;                       /*!< Receiver timeout                                                      */
+  __I  uint32_t  RESERVED5[46];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED6[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED7[93];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  RESERVED8[31];
+  __IO uint32_t  ENABLE;                            /*!< Enable UART                                                           */
+  __I  uint32_t  RESERVED9;
+  UART_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RXD;                               /*!< RXD register                                                          */
+  __O  uint32_t  TXD;                               /*!< TXD register                                                          */
+  __I  uint32_t  RESERVED10;
+  __IO uint32_t  BAUDRATE;                          /*!< Baud rate. Accuracy depends on the HFCLK source selected.             */
+  __I  uint32_t  RESERVED11[17];
+  __IO uint32_t  CONFIG;                            /*!< Configuration of parity and hardware flow control                     */
+} NRF_UART_Type;
+
+
+/* ================================================================================ */
+/* ================                      SPIM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM)
+  */
+
+typedef struct {                                    /*!< SPIM Structure                                                        */
+  __I  uint32_t  RESERVED0[4];
+  __O  uint32_t  TASKS_START;                       /*!< Start SPI transaction                                                 */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop SPI transaction                                                  */
+  __I  uint32_t  RESERVED1;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend SPI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume SPI transaction                                                */
+  __I  uint32_t  RESERVED2[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< SPI transaction has stopped                                           */
+  __I  uint32_t  RESERVED3[2];
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached                                             */
+  __I  uint32_t  RESERVED4;
+  __IO uint32_t  EVENTS_END;                        /*!< End of RXD buffer and TXD buffer reached                              */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  EVENTS_ENDTX;                      /*!< End of TXD buffer reached                                             */
+  __I  uint32_t  RESERVED6[10];
+  __IO uint32_t  EVENTS_STARTED;                    /*!< Transaction started                                                   */
+  __I  uint32_t  RESERVED7[44];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[61];
+  __IO uint32_t  STALLSTAT;                         /*!< Stall status for EasyDMA RAM accesses. The fields in this register
+                                                         is set to STALL by hardware whenever a stall occurres and can
+                                                          be cleared (set to NOSTALL) by the CPU.                              */
+  __I  uint32_t  RESERVED10[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPIM                                                           */
+  __I  uint32_t  RESERVED11;
+  SPIM_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[3];
+  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency. Accuracy depends on the HFCLK source selected.         */
+  __I  uint32_t  RESERVED13[3];
+  SPIM_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */
+  SPIM_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  RESERVED14[2];
+  SPIM_IFTIMING_Type IFTIMING;                      /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED15[22];
+  __IO uint32_t  ORC;                               /*!< Byte transmitted after TXD.MAXCNT bytes have been transmitted
+                                                         in the case when RXD.MAXCNT is greater than TXD.MAXCNT                */
+} NRF_SPIM_Type;
+
+
+/* ================================================================================ */
+/* ================                      SPIS                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief SPI Slave 0 (SPIS)
+  */
+
+typedef struct {                                    /*!< SPIS Structure                                                        */
+  __I  uint32_t  RESERVED0[9];
+  __O  uint32_t  TASKS_ACQUIRE;                     /*!< Acquire SPI semaphore                                                 */
+  __O  uint32_t  TASKS_RELEASE;                     /*!< Release SPI semaphore, enabling the SPI slave to acquire it           */
+  __I  uint32_t  RESERVED1[54];
+  __IO uint32_t  EVENTS_END;                        /*!< Granted transaction completed                                         */
+  __I  uint32_t  RESERVED2[2];
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached                                             */
+  __I  uint32_t  RESERVED3[5];
+  __IO uint32_t  EVENTS_ACQUIRED;                   /*!< Semaphore acquired                                                    */
+  __I  uint32_t  RESERVED4[53];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED5[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED6[61];
+  __I  uint32_t  SEMSTAT;                           /*!< Semaphore status register                                             */
+  __I  uint32_t  RESERVED7[15];
+  __IO uint32_t  STATUS;                            /*!< Status from last transaction                                          */
+  __I  uint32_t  RESERVED8[47];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPI slave                                                      */
+  __I  uint32_t  RESERVED9;
+  SPIS_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED10[7];
+  SPIS_RXD_Type RXD;                                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED11;
+  SPIS_TXD_Type TXD;                                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12;
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  RESERVED13;
+  __IO uint32_t  DEF;                               /*!< Default character. Character clocked out in case of an ignored
+                                                         transaction.                                                          */
+  __I  uint32_t  RESERVED14[24];
+  __IO uint32_t  ORC;                               /*!< Over-read character                                                   */
+} NRF_SPIS_Type;
+
+
+/* ================================================================================ */
+/* ================                      TWIM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM)
+  */
+
+typedef struct {                                    /*!< TWIM Structure                                                        */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start TWI receive sequence                                            */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start TWI transmit sequence                                           */
+  __I  uint32_t  RESERVED1[2];
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction. Must be issued while the TWI master is
+                                                         not suspended.                                                        */
+  __I  uint32_t  RESERVED2;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */
+  __I  uint32_t  RESERVED3[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */
+  __I  uint32_t  RESERVED5[8];
+  __IO uint32_t  EVENTS_SUSPENDED;                  /*!< Last byte has been sent out after the SUSPEND task has been
+                                                         issued, TWI traffic is now suspended.                                 */
+  __IO uint32_t  EVENTS_RXSTARTED;                  /*!< Receive sequence started                                              */
+  __IO uint32_t  EVENTS_TXSTARTED;                  /*!< Transmit sequence started                                             */
+  __I  uint32_t  RESERVED6[2];
+  __IO uint32_t  EVENTS_LASTRX;                     /*!< Byte boundary, starting to receive the last byte                      */
+  __IO uint32_t  EVENTS_LASTTX;                     /*!< Byte boundary, starting to transmit the last byte                     */
+  __I  uint32_t  RESERVED7[39];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[110];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  RESERVED10[14];
+  __IO uint32_t  ENABLE;                            /*!< Enable TWIM                                                           */
+  __I  uint32_t  RESERVED11;
+  TWIM_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[5];
+  __IO uint32_t  FREQUENCY;                         /*!< TWI frequency. Accuracy depends on the HFCLK source selected.         */
+  __I  uint32_t  RESERVED13[3];
+  TWIM_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */
+  TWIM_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED14[13];
+  __IO uint32_t  ADDRESS;                           /*!< Address used in the TWI transfer                                      */
+} NRF_TWIM_Type;
+
+
+/* ================================================================================ */
+/* ================                      TWIS                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS)
+  */
+
+typedef struct {                                    /*!< TWIS Structure                                                        */
+  __I  uint32_t  RESERVED0[5];
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction                                                  */
+  __I  uint32_t  RESERVED1;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */
+  __I  uint32_t  RESERVED2[3];
+  __O  uint32_t  TASKS_PREPARERX;                   /*!< Prepare the TWI slave to respond to a write command                   */
+  __O  uint32_t  TASKS_PREPARETX;                   /*!< Prepare the TWI slave to respond to a read command                    */
+  __I  uint32_t  RESERVED3[51];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */
+  __I  uint32_t  RESERVED5[9];
+  __IO uint32_t  EVENTS_RXSTARTED;                  /*!< Receive sequence started                                              */
+  __IO uint32_t  EVENTS_TXSTARTED;                  /*!< Transmit sequence started                                             */
+  __I  uint32_t  RESERVED6[4];
+  __IO uint32_t  EVENTS_WRITE;                      /*!< Write command received                                                */
+  __IO uint32_t  EVENTS_READ;                       /*!< Read command received                                                 */
+  __I  uint32_t  RESERVED7[37];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[113];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  MATCH;                             /*!< Status register indicating which address had a match                  */
+  __I  uint32_t  RESERVED10[10];
+  __IO uint32_t  ENABLE;                            /*!< Enable TWIS                                                           */
+  __I  uint32_t  RESERVED11;
+  TWIS_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[9];
+  TWIS_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED13;
+  TWIS_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED14[14];
+  __IO uint32_t  ADDRESS[2];                        /*!< Description collection[0]: TWI slave address 0                        */
+  __I  uint32_t  RESERVED15;
+  __IO uint32_t  CONFIG;                            /*!< Configuration register for the address match mechanism                */
+  __I  uint32_t  RESERVED16[10];
+  __IO uint32_t  ORC;                               /*!< Over-read character. Character sent out in case of an over-read
+                                                         of the transmit buffer.                                               */
+} NRF_TWIS_Type;
+
+
+/* ================================================================================ */
+/* ================                       SPI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Serial Peripheral Interface 0 (SPI)
+  */
+
+typedef struct {                                    /*!< SPI Structure                                                         */
+  __I  uint32_t  RESERVED0[66];
+  __IO uint32_t  EVENTS_READY;                      /*!< TXD byte sent and RXD byte received                                   */
+  __I  uint32_t  RESERVED1[126];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPI                                                            */
+  __I  uint32_t  RESERVED3;
+  SPI_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED4;
+  __I  uint32_t  RXD;                               /*!< RXD register                                                          */
+  __IO uint32_t  TXD;                               /*!< TXD register                                                          */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency. Accuracy depends on the HFCLK source selected.         */
+  __I  uint32_t  RESERVED6[11];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+} NRF_SPI_Type;
+
+
+/* ================================================================================ */
+/* ================                       TWI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief I2C compatible Two-Wire Interface 0 (TWI)
+  */
+
+typedef struct {                                    /*!< TWI Structure                                                         */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start TWI receive sequence                                            */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start TWI transmit sequence                                           */
+  __I  uint32_t  RESERVED1[2];
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction                                                  */
+  __I  uint32_t  RESERVED2;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */
+  __I  uint32_t  RESERVED3[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */
+  __IO uint32_t  EVENTS_RXDREADY;                   /*!< TWI RXD byte received                                                 */
+  __I  uint32_t  RESERVED4[4];
+  __IO uint32_t  EVENTS_TXDSENT;                    /*!< TWI TXD byte sent                                                     */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */
+  __I  uint32_t  RESERVED6[4];
+  __IO uint32_t  EVENTS_BB;                         /*!< TWI byte boundary, generated before each byte that is sent or
+                                                         received                                                              */
+  __I  uint32_t  RESERVED7[3];
+  __IO uint32_t  EVENTS_SUSPENDED;                  /*!< TWI entered the suspended state                                       */
+  __I  uint32_t  RESERVED8[45];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED9[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED10[110];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  RESERVED11[14];
+  __IO uint32_t  ENABLE;                            /*!< Enable TWI                                                            */
+  __I  uint32_t  RESERVED12;
+  TWI_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED13[2];
+  __I  uint32_t  RXD;                               /*!< RXD register                                                          */
+  __IO uint32_t  TXD;                               /*!< TXD register                                                          */
+  __I  uint32_t  RESERVED14;
+  __IO uint32_t  FREQUENCY;                         /*!< TWI frequency. Accuracy depends on the HFCLK source selected.         */
+  __I  uint32_t  RESERVED15[24];
+  __IO uint32_t  ADDRESS;                           /*!< Address used in the TWI transfer                                      */
+} NRF_TWI_Type;
+
+
+/* ================================================================================ */
+/* ================                      NFCT                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief NFC-A compatible radio (NFCT)
+  */
+
+typedef struct {                                    /*!< NFCT Structure                                                        */
+  __O  uint32_t  TASKS_ACTIVATE;                    /*!< Activate NFCT peripheral for incoming and outgoing frames, change
+                                                         state to activated                                                    */
+  __O  uint32_t  TASKS_DISABLE;                     /*!< Disable NFCT peripheral                                               */
+  __O  uint32_t  TASKS_SENSE;                       /*!< Enable NFC sense field mode, change state to sense mode               */
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start transmission of an outgoing frame, change state to transmit     */
+  __I  uint32_t  RESERVED0[3];
+  __O  uint32_t  TASKS_ENABLERXDATA;                /*!< Initializes the EasyDMA for receive.                                  */
+  __I  uint32_t  RESERVED1;
+  __O  uint32_t  TASKS_GOIDLE;                      /*!< Force state machine to IDLE state                                     */
+  __O  uint32_t  TASKS_GOSLEEP;                     /*!< Force state machine to SLEEP_A state                                  */
+  __I  uint32_t  RESERVED2[53];
+  __IO uint32_t  EVENTS_READY;                      /*!< The NFCT peripheral is ready to receive and send frames               */
+  __IO uint32_t  EVENTS_FIELDDETECTED;              /*!< Remote NFC field detected                                             */
+  __IO uint32_t  EVENTS_FIELDLOST;                  /*!< Remote NFC field lost                                                 */
+  __IO uint32_t  EVENTS_TXFRAMESTART;               /*!< Marks the start of the first symbol of a transmitted frame            */
+  __IO uint32_t  EVENTS_TXFRAMEEND;                 /*!< Marks the end of the last transmitted on-air symbol of a frame        */
+  __IO uint32_t  EVENTS_RXFRAMESTART;               /*!< Marks the end of the first symbol of a received frame                 */
+  __IO uint32_t  EVENTS_RXFRAMEEND;                 /*!< Received data has been checked (CRC, parity) and transferred
+                                                         to RAM, and EasyDMA has ended accessing the RX buffer                 */
+  __IO uint32_t  EVENTS_ERROR;                      /*!< NFC error reported. The ERRORSTATUS register contains details
+                                                         on the source of the error.                                           */
+  __I  uint32_t  RESERVED3[2];
+  __IO uint32_t  EVENTS_RXERROR;                    /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains
+                                                         details on the source of the error.                                   */
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.      */
+  __IO uint32_t  EVENTS_ENDTX;                      /*!< Transmission of data in RAM has ended, and EasyDMA has ended
+                                                         accessing the TX buffer                                               */
+  __I  uint32_t  RESERVED4;
+  __IO uint32_t  EVENTS_AUTOCOLRESSTARTED;          /*!< Auto collision resolution process has started                         */
+  __I  uint32_t  RESERVED5[3];
+  __IO uint32_t  EVENTS_COLLISION;                  /*!< NFC auto collision resolution error reported.                         */
+  __IO uint32_t  EVENTS_SELECTED;                   /*!< NFC auto collision resolution successfully completed                  */
+  __IO uint32_t  EVENTS_STARTED;                    /*!< EasyDMA is ready to receive or send frames.                           */
+  __I  uint32_t  RESERVED6[43];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED7[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED8[62];
+  __IO uint32_t  ERRORSTATUS;                       /*!< NFC Error Status register                                             */
+  __I  uint32_t  RESERVED9;
+  NFCT_FRAMESTATUS_Type FRAMESTATUS;                /*!< Unspecified                                                           */
+  __I  uint32_t  NFCTAGSTATE;                       /*!< NfcTag state register                                                 */
+  __I  uint32_t  RESERVED10[10];
+  __I  uint32_t  FIELDPRESENT;                      /*!< Indicates the presence or not of a valid field                        */
+  __I  uint32_t  RESERVED11[49];
+  __IO uint32_t  FRAMEDELAYMIN;                     /*!< Minimum frame delay                                                   */
+  __IO uint32_t  FRAMEDELAYMAX;                     /*!< Maximum frame delay                                                   */
+  __IO uint32_t  FRAMEDELAYMODE;                    /*!< Configuration register for the Frame Delay Timer                      */
+  __IO uint32_t  PACKETPTR;                         /*!< Packet pointer for TXD and RXD data storage in Data RAM               */
+  __IO uint32_t  MAXLEN;                            /*!< Size of the RAM buffer allocated to TXD and RXD data storage
+                                                         each                                                                  */
+  NFCT_TXD_Type TXD;                                /*!< Unspecified                                                           */
+  NFCT_RXD_Type RXD;                                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[26];
+  __IO uint32_t  NFCID1_LAST;                       /*!< Last NFCID1 part (4, 7 or 10 bytes ID)                                */
+  __IO uint32_t  NFCID1_2ND_LAST;                   /*!< Second last NFCID1 part (7 or 10 bytes ID)                            */
+  __IO uint32_t  NFCID1_3RD_LAST;                   /*!< Third last NFCID1 part (10 bytes ID)                                  */
+  __IO uint32_t  AUTOCOLRESCONFIG;                  /*!< Controls the auto collision resolution function. This setting
+                                                         must be done before the NFCT peripheral is enabled.                   */
+  __IO uint32_t  SENSRES;                           /*!< NFC-A SENS_RES auto-response settings                                 */
+  __IO uint32_t  SELRES;                            /*!< NFC-A SEL_RES auto-response settings                                  */
+} NRF_NFCT_Type;
+
+
+/* ================================================================================ */
+/* ================                     GPIOTE                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief GPIO Tasks and Events (GPIOTE)
+  */
+
+typedef struct {                                    /*!< GPIOTE Structure                                                      */
+  __O  uint32_t  TASKS_OUT[8];                      /*!< Description collection[0]: Task for writing to pin specified
+                                                         in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */
+  __I  uint32_t  RESERVED0[4];
+  __O  uint32_t  TASKS_SET[8];                      /*!< Description collection[0]: Task for writing to pin specified
+                                                         in CONFIG[0].PSEL. Action on pin is to set it high.                   */
+  __I  uint32_t  RESERVED1[4];
+  __O  uint32_t  TASKS_CLR[8];                      /*!< Description collection[0]: Task for writing to pin specified
+                                                         in CONFIG[0].PSEL. Action on pin is to set it low.                    */
+  __I  uint32_t  RESERVED2[32];
+  __IO uint32_t  EVENTS_IN[8];                      /*!< Description collection[0]: Event generated from pin specified
+                                                         in CONFIG[0].PSEL                                                     */
+  __I  uint32_t  RESERVED3[23];
+  __IO uint32_t  EVENTS_PORT;                       /*!< Event generated from multiple input GPIO pins with SENSE mechanism
+                                                         enabled                                                               */
+  __I  uint32_t  RESERVED4[97];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED5[129];
+  __IO uint32_t  CONFIG[8];                         /*!< Description collection[0]: Configuration for OUT[n], SET[n]
+                                                         and CLR[n] tasks and IN[n] event                                      */
+} NRF_GPIOTE_Type;
+
+
+/* ================================================================================ */
+/* ================                      SAADC                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Analog to Digital Converter (SAADC)
+  */
+
+typedef struct {                                    /*!< SAADC Structure                                                       */
+  __O  uint32_t  TASKS_START;                       /*!< Start the ADC and prepare the result buffer in RAM                    */
+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Take one ADC sample, if scan is enabled all channels are sampled      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop the ADC and terminate any on-going conversion                    */
+  __O  uint32_t  TASKS_CALIBRATEOFFSET;             /*!< Starts offset auto-calibration                                        */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_STARTED;                    /*!< The ADC has started                                                   */
+  __IO uint32_t  EVENTS_END;                        /*!< The ADC has filled up the Result buffer                               */
+  __IO uint32_t  EVENTS_DONE;                       /*!< A conversion task has been completed. Depending on the mode,
+                                                         multiple conversions might be needed for a result to be transferred
+                                                          to RAM.                                                              */
+  __IO uint32_t  EVENTS_RESULTDONE;                 /*!< A result is ready to get transferred to RAM.                          */
+  __IO uint32_t  EVENTS_CALIBRATEDONE;              /*!< Calibration is complete                                               */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< The ADC has stopped                                                   */
+  SAADC_EVENTS_CH_Type EVENTS_CH[8];                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED1[106];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[61];
+  __I  uint32_t  STATUS;                            /*!< Status                                                                */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable or disable ADC                                                 */
+  __I  uint32_t  RESERVED4[3];
+  SAADC_CH_Type CH[8];                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5[24];
+  __IO uint32_t  RESOLUTION;                        /*!< Resolution configuration                                              */
+  __IO uint32_t  OVERSAMPLE;                        /*!< Oversampling configuration. OVERSAMPLE should not be combined
+                                                         with SCAN. The RESOLUTION is applied before averaging, thus
+                                                          for high OVERSAMPLE a higher RESOLUTION should be used.              */
+  __IO uint32_t  SAMPLERATE;                        /*!< Controls normal or continuous sample rate                             */
+  __I  uint32_t  RESERVED6[12];
+  SAADC_RESULT_Type RESULT;                         /*!< RESULT EasyDMA channel                                                */
+} NRF_SAADC_Type;
+
+
+/* ================================================================================ */
+/* ================                      TIMER                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Timer/Counter 0 (TIMER)
+  */
+
+typedef struct {                                    /*!< TIMER Structure                                                       */
+  __O  uint32_t  TASKS_START;                       /*!< Start Timer                                                           */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop Timer                                                            */
+  __O  uint32_t  TASKS_COUNT;                       /*!< Increment Timer (Counter mode only)                                   */
+  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear time                                                            */
+  __O  uint32_t  TASKS_SHUTDOWN;                    /*!< Deprecated register - Shut down timer                                 */
+  __I  uint32_t  RESERVED0[11];
+  __O  uint32_t  TASKS_CAPTURE[6];                  /*!< Description collection[0]: Capture Timer value to CC[0] register      */
+  __I  uint32_t  RESERVED1[58];
+  __IO uint32_t  EVENTS_COMPARE[6];                 /*!< Description collection[0]: Compare event on CC[0] match               */
+  __I  uint32_t  RESERVED2[42];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED3[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED4[61];
+  __I  uint32_t  STATUS;                            /*!< Timer status                                                          */
+  __I  uint32_t  RESERVED5[64];
+  __IO uint32_t  MODE;                              /*!< Timer mode selection                                                  */
+  __IO uint32_t  BITMODE;                           /*!< Configure the number of bits used by the TIMER                        */
+  __I  uint32_t  RESERVED6;
+  __IO uint32_t  PRESCALER;                         /*!< Timer prescaler register                                              */
+  __I  uint32_t  RESERVED7[11];
+  __IO uint32_t  CC[6];                             /*!< Description collection[0]: Capture/Compare register 0                 */
+} NRF_TIMER_Type;
+
+
+/* ================================================================================ */
+/* ================                       RTC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Real time counter 0 (RTC)
+  */
+
+typedef struct {                                    /*!< RTC Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start RTC COUNTER                                                     */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop RTC COUNTER                                                      */
+  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear RTC COUNTER                                                     */
+  __O  uint32_t  TASKS_TRIGOVRFLW;                  /*!< Set COUNTER to 0xFFFFF0                                               */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_TICK;                       /*!< Event on COUNTER increment                                            */
+  __IO uint32_t  EVENTS_OVRFLW;                     /*!< Event on COUNTER overflow                                             */
+  __I  uint32_t  RESERVED1[14];
+  __IO uint32_t  EVENTS_COMPARE[4];                 /*!< Description collection[0]: Compare event on CC[0] match               */
+  __I  uint32_t  RESERVED2[109];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[13];
+  __IO uint32_t  EVTEN;                             /*!< Enable or disable event routing                                       */
+  __IO uint32_t  EVTENSET;                          /*!< Enable event routing                                                  */
+  __IO uint32_t  EVTENCLR;                          /*!< Disable event routing                                                 */
+  __I  uint32_t  RESERVED4[110];
+  __I  uint32_t  COUNTER;                           /*!< Current COUNTER value                                                 */
+  __IO uint32_t  PRESCALER;                         /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must
+                                                         be written when RTC is stopped                                        */
+  __I  uint32_t  RESERVED5[13];
+  __IO uint32_t  CC[4];                             /*!< Description collection[0]: Compare register 0                         */
+} NRF_RTC_Type;
+
+
+/* ================================================================================ */
+/* ================                      TEMP                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Temperature Sensor (TEMP)
+  */
+
+typedef struct {                                    /*!< TEMP Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Start temperature measurement                                         */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop temperature measurement                                          */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_DATARDY;                    /*!< Temperature measurement complete, data ready                          */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[127];
+  __I  int32_t   TEMP;                              /*!< Temperature in degC (0.25deg steps)                                   */
+  __I  uint32_t  RESERVED3[5];
+  __IO uint32_t  A0;                                /*!< Slope of 1st piece wise linear function                               */
+  __IO uint32_t  A1;                                /*!< Slope of 2nd piece wise linear function                               */
+  __IO uint32_t  A2;                                /*!< Slope of 3rd piece wise linear function                               */
+  __IO uint32_t  A3;                                /*!< Slope of 4th piece wise linear function                               */
+  __IO uint32_t  A4;                                /*!< Slope of 5th piece wise linear function                               */
+  __IO uint32_t  A5;                                /*!< Slope of 6th piece wise linear function                               */
+  __I  uint32_t  RESERVED4[2];
+  __IO uint32_t  B0;                                /*!< y-intercept of 1st piece wise linear function                         */
+  __IO uint32_t  B1;                                /*!< y-intercept of 2nd piece wise linear function                         */
+  __IO uint32_t  B2;                                /*!< y-intercept of 3rd piece wise linear function                         */
+  __IO uint32_t  B3;                                /*!< y-intercept of 4th piece wise linear function                         */
+  __IO uint32_t  B4;                                /*!< y-intercept of 5th piece wise linear function                         */
+  __IO uint32_t  B5;                                /*!< y-intercept of 6th piece wise linear function                         */
+  __I  uint32_t  RESERVED5[2];
+  __IO uint32_t  T0;                                /*!< End point of 1st piece wise linear function                           */
+  __IO uint32_t  T1;                                /*!< End point of 2nd piece wise linear function                           */
+  __IO uint32_t  T2;                                /*!< End point of 3rd piece wise linear function                           */
+  __IO uint32_t  T3;                                /*!< End point of 4th piece wise linear function                           */
+  __IO uint32_t  T4;                                /*!< End point of 5th piece wise linear function                           */
+} NRF_TEMP_Type;
+
+
+/* ================================================================================ */
+/* ================                       RNG                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Random Number Generator (RNG)
+  */
+
+typedef struct {                                    /*!< RNG Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Task starting the random number generator                             */
+  __O  uint32_t  TASKS_STOP;                        /*!< Task stopping the random number generator                             */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_VALRDY;                     /*!< Event being generated for every new random number written to
+                                                         the VALUE register                                                    */
+  __I  uint32_t  RESERVED1[63];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[126];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  VALUE;                             /*!< Output random number                                                  */
+} NRF_RNG_Type;
+
+
+/* ================================================================================ */
+/* ================                       ECB                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief AES ECB Mode Encryption (ECB)
+  */
+
+typedef struct {                                    /*!< ECB Structure                                                         */
+  __O  uint32_t  TASKS_STARTECB;                    /*!< Start ECB block encrypt                                               */
+  __O  uint32_t  TASKS_STOPECB;                     /*!< Abort a possible executing ECB operation                              */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_ENDECB;                     /*!< ECB block encrypt complete                                            */
+  __IO uint32_t  EVENTS_ERRORECB;                   /*!< ECB block encrypt aborted because of a STOPECB task or due to
+                                                         an error                                                              */
+  __I  uint32_t  RESERVED1[127];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  ECBDATAPTR;                        /*!< ECB block encrypt memory pointers                                     */
+} NRF_ECB_Type;
+
+
+/* ================================================================================ */
+/* ================                       CCM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief AES CCM Mode Encryption (CCM)
+  */
+
+typedef struct {                                    /*!< CCM Structure                                                         */
+  __O  uint32_t  TASKS_KSGEN;                       /*!< Start generation of key-stream. This operation will stop by
+                                                         itself when completed.                                                */
+  __O  uint32_t  TASKS_CRYPT;                       /*!< Start encryption/decryption. This operation will stop by itself
+                                                         when completed.                                                       */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop encryption/decryption                                            */
+  __O  uint32_t  TASKS_RATEOVERRIDE;                /*!< Override DATARATE setting in MODE register with the contents
+                                                         of the RATEOVERRIDE register for any ongoing encryption/decryption    */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_ENDKSGEN;                   /*!< Key-stream generation complete                                        */
+  __IO uint32_t  EVENTS_ENDCRYPT;                   /*!< Encrypt/decrypt complete                                              */
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Deprecated register - CCM error event                                 */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  MICSTATUS;                         /*!< MIC check result                                                      */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable                                                                */
+  __IO uint32_t  MODE;                              /*!< Operation mode                                                        */
+  __IO uint32_t  CNFPTR;                            /*!< Pointer to data structure holding AES key and NONCE vector            */
+  __IO uint32_t  INPTR;                             /*!< Input pointer                                                         */
+  __IO uint32_t  OUTPTR;                            /*!< Output pointer                                                        */
+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to data area used for temporary storage                       */
+  __IO uint32_t  MAXPACKETSIZE;                     /*!< Length of key-stream generated when MODE.LENGTH = Extended.           */
+  __IO uint32_t  RATEOVERRIDE;                      /*!< Data rate override setting.                                           */
+} NRF_CCM_Type;
+
+
+/* ================================================================================ */
+/* ================                       AAR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Accelerated Address Resolver (AAR)
+  */
+
+typedef struct {                                    /*!< AAR Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start resolving addresses based on IRKs specified in the IRK
+                                                         data structure                                                        */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop resolving addresses                                              */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  EVENTS_END;                        /*!< Address resolution procedure complete                                 */
+  __IO uint32_t  EVENTS_RESOLVED;                   /*!< Address resolved                                                      */
+  __IO uint32_t  EVENTS_NOTRESOLVED;                /*!< Address not resolved                                                  */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  STATUS;                            /*!< Resolution status                                                     */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable AAR                                                            */
+  __IO uint32_t  NIRK;                              /*!< Number of IRKs                                                        */
+  __IO uint32_t  IRKPTR;                            /*!< Pointer to IRK data structure                                         */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  ADDRPTR;                           /*!< Pointer to the resolvable address                                     */
+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to data area used for temporary storage                       */
+} NRF_AAR_Type;
+
+
+/* ================================================================================ */
+/* ================                       WDT                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Watchdog Timer (WDT)
+  */
+
+typedef struct {                                    /*!< WDT Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start the watchdog                                                    */
+  __I  uint32_t  RESERVED0[63];
+  __IO uint32_t  EVENTS_TIMEOUT;                    /*!< Watchdog timeout                                                      */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[61];
+  __I  uint32_t  RUNSTATUS;                         /*!< Run status                                                            */
+  __I  uint32_t  REQSTATUS;                         /*!< Request status                                                        */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  CRV;                               /*!< Counter reload value                                                  */
+  __IO uint32_t  RREN;                              /*!< Enable register for reload request registers                          */
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  RESERVED4[60];
+  __O  uint32_t  RR[8];                             /*!< Description collection[0]: Reload request 0                           */
+} NRF_WDT_Type;
+
+
+/* ================================================================================ */
+/* ================                      QDEC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Quadrature Decoder (QDEC)
+  */
+
+typedef struct {                                    /*!< QDEC Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Task starting the quadrature decoder                                  */
+  __O  uint32_t  TASKS_STOP;                        /*!< Task stopping the quadrature decoder                                  */
+  __O  uint32_t  TASKS_READCLRACC;                  /*!< Read and clear ACC and ACCDBL                                         */
+  __O  uint32_t  TASKS_RDCLRACC;                    /*!< Read and clear ACC                                                    */
+  __O  uint32_t  TASKS_RDCLRDBL;                    /*!< Read and clear ACCDBL                                                 */
+  __I  uint32_t  RESERVED0[59];
+  __IO uint32_t  EVENTS_SAMPLERDY;                  /*!< Event being generated for every new sample value written to
+                                                         the SAMPLE register                                                   */
+  __IO uint32_t  EVENTS_REPORTRDY;                  /*!< Non-null report ready                                                 */
+  __IO uint32_t  EVENTS_ACCOF;                      /*!< ACC or ACCDBL register overflow                                       */
+  __IO uint32_t  EVENTS_DBLRDY;                     /*!< Double displacement(s) detected                                       */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< QDEC has been stopped                                                 */
+  __I  uint32_t  RESERVED1[59];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable the quadrature decoder                                         */
+  __IO uint32_t  LEDPOL;                            /*!< LED output pin polarity                                               */
+  __IO uint32_t  SAMPLEPER;                         /*!< Sample period                                                         */
+  __I  int32_t   SAMPLE;                            /*!< Motion sample value                                                   */
+  __IO uint32_t  REPORTPER;                         /*!< Number of samples to be taken before REPORTRDY and DBLRDY events
+                                                         can be generated                                                      */
+  __I  int32_t   ACC;                               /*!< Register accumulating the valid transitions                           */
+  __I  int32_t   ACCREAD;                           /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC
+                                                         task                                                                  */
+  QDEC_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __IO uint32_t  DBFEN;                             /*!< Enable input debounce filters                                         */
+  __I  uint32_t  RESERVED4[5];
+  __IO uint32_t  LEDPRE;                            /*!< Time period the LED is switched ON prior to sampling                  */
+  __I  uint32_t  ACCDBL;                            /*!< Register accumulating the number of detected double transitions       */
+  __I  uint32_t  ACCDBLREAD;                        /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL
+                                                         task                                                                  */
+} NRF_QDEC_Type;
+
+
+/* ================================================================================ */
+/* ================                      COMP                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Comparator (COMP)
+  */
+
+typedef struct {                                    /*!< COMP Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Start comparator                                                      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop comparator                                                       */
+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Sample comparator value                                               */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_READY;                      /*!< COMP is ready and output is valid                                     */
+  __IO uint32_t  EVENTS_DOWN;                       /*!< Downward crossing                                                     */
+  __IO uint32_t  EVENTS_UP;                         /*!< Upward crossing                                                       */
+  __IO uint32_t  EVENTS_CROSS;                      /*!< Downward or upward crossing                                           */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  RESULT;                            /*!< Compare result                                                        */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< COMP enable                                                           */
+  __IO uint32_t  PSEL;                              /*!< Pin select                                                            */
+  __IO uint32_t  REFSEL;                            /*!< Reference source select                                               */
+  __IO uint32_t  EXTREFSEL;                         /*!< External reference select                                             */
+  __I  uint32_t  RESERVED5[8];
+  __IO uint32_t  TH;                                /*!< Threshold configuration for hysteresis unit                           */
+  __IO uint32_t  MODE;                              /*!< Mode configuration                                                    */
+  __IO uint32_t  HYST;                              /*!< Comparator hysteresis enable                                          */
+  __IO uint32_t  ISOURCE;                           /*!< Current source select on analog input                                 */
+} NRF_COMP_Type;
+
+
+/* ================================================================================ */
+/* ================                     LPCOMP                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Low Power Comparator (LPCOMP)
+  */
+
+typedef struct {                                    /*!< LPCOMP Structure                                                      */
+  __O  uint32_t  TASKS_START;                       /*!< Start comparator                                                      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop comparator                                                       */
+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Sample comparator value                                               */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_READY;                      /*!< LPCOMP is ready and output is valid                                   */
+  __IO uint32_t  EVENTS_DOWN;                       /*!< Downward crossing                                                     */
+  __IO uint32_t  EVENTS_UP;                         /*!< Upward crossing                                                       */
+  __IO uint32_t  EVENTS_CROSS;                      /*!< Downward or upward crossing                                           */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  RESULT;                            /*!< Compare result                                                        */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable LPCOMP                                                         */
+  __IO uint32_t  PSEL;                              /*!< Input pin select                                                      */
+  __IO uint32_t  REFSEL;                            /*!< Reference select                                                      */
+  __IO uint32_t  EXTREFSEL;                         /*!< External reference select                                             */
+  __I  uint32_t  RESERVED5[4];
+  __IO uint32_t  ANADETECT;                         /*!< Analog detect configuration                                           */
+  __I  uint32_t  RESERVED6[5];
+  __IO uint32_t  HYST;                              /*!< Comparator hysteresis enable                                          */
+} NRF_LPCOMP_Type;
+
+
+/* ================================================================================ */
+/* ================                       SWI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Software interrupt 0 (SWI)
+  */
+
+typedef struct {                                    /*!< SWI Structure                                                         */
+  __I  uint32_t  UNUSED;                            /*!< Unused.                                                               */
+} NRF_SWI_Type;
+
+
+/* ================================================================================ */
+/* ================                       EGU                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Event Generator Unit 0 (EGU)
+  */
+
+typedef struct {                                    /*!< EGU Structure                                                         */
+  __O  uint32_t  TASKS_TRIGGER[16];                 /*!< Description collection[0]: Trigger 0 for triggering the corresponding
+                                                         TRIGGERED[0] event                                                    */
+  __I  uint32_t  RESERVED0[48];
+  __IO uint32_t  EVENTS_TRIGGERED[16];              /*!< Description collection[0]: Event number 0 generated by triggering
+                                                         the corresponding TRIGGER[0] task                                     */
+  __I  uint32_t  RESERVED1[112];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+} NRF_EGU_Type;
+
+
+/* ================================================================================ */
+/* ================                       PWM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Pulse Width Modulation Unit 0 (PWM)
+  */
+
+typedef struct {                                    /*!< PWM Structure                                                         */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STOP;                        /*!< Stops PWM pulse generation on all channels at the end of current
+                                                         PWM period, and stops sequence playback                               */
+  __O  uint32_t  TASKS_SEQSTART[2];                 /*!< Description collection[0]: Loads the first PWM value on all
+                                                         enabled channels from sequence 0, and starts playing that sequence
+                                                          at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes
+                                                          PWM generation to start it was not running.                          */
+  __O  uint32_t  TASKS_NEXTSTEP;                    /*!< Steps by one value in the current sequence on all enabled channels
+                                                         if DECODER.MODE=NextStep. Does not cause PWM generation to start
+                                                          it was not running.                                                  */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< Response to STOP task, emitted when PWM pulses are no longer
+                                                         generated                                                             */
+  __IO uint32_t  EVENTS_SEQSTARTED[2];              /*!< Description collection[0]: First PWM period started on sequence
+                                                         0                                                                     */
+  __IO uint32_t  EVENTS_SEQEND[2];                  /*!< Description collection[0]: Emitted at end of every sequence
+                                                         0, when last value from RAM has been applied to wave counter          */
+  __IO uint32_t  EVENTS_PWMPERIODEND;               /*!< Emitted at the end of each PWM period                                 */
+  __IO uint32_t  EVENTS_LOOPSDONE;                  /*!< Concatenated sequences have been played the amount of times
+                                                         defined in LOOP.CNT                                                   */
+  __I  uint32_t  RESERVED2[56];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED4[125];
+  __IO uint32_t  ENABLE;                            /*!< PWM module enable register                                            */
+  __IO uint32_t  MODE;                              /*!< Selects operating mode of the wave counter                            */
+  __IO uint32_t  COUNTERTOP;                        /*!< Value up to which the pulse generator counter counts                  */
+  __IO uint32_t  PRESCALER;                         /*!< Configuration for PWM_CLK                                             */
+  __IO uint32_t  DECODER;                           /*!< Configuration of the decoder                                          */
+  __IO uint32_t  LOOP;                              /*!< Amount of playback of a loop                                          */
+  __I  uint32_t  RESERVED5[2];
+  PWM_SEQ_Type SEQ[2];                              /*!< Unspecified                                                           */
+  PWM_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+} NRF_PWM_Type;
+
+
+/* ================================================================================ */
+/* ================                       PDM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM)
+  */
+
+typedef struct {                                    /*!< PDM Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Starts continuous PDM transfer                                        */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stops PDM transfer                                                    */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_STARTED;                    /*!< PDM transfer has started                                              */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< PDM transfer has finished                                             */
+  __IO uint32_t  EVENTS_END;                        /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT
+                                                         (or the last sample after a STOP task has been received) to
+                                                          Data RAM                                                             */
+  __I  uint32_t  RESERVED1[125];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[125];
+  __IO uint32_t  ENABLE;                            /*!< PDM module enable register                                            */
+  __IO uint32_t  PDMCLKCTRL;                        /*!< PDM clock generator control                                           */
+  __IO uint32_t  MODE;                              /*!< Defines the routing of the connected PDM microphones' signals         */
+  __I  uint32_t  RESERVED3[3];
+  __IO uint32_t  GAINL;                             /*!< Left output gain adjustment                                           */
+  __IO uint32_t  GAINR;                             /*!< Right output gain adjustment                                          */
+  __IO uint32_t  RATIO;                             /*!< Selects the ratio between PDM_CLK and output sample rate. Change
+                                                         PDMCLKCTRL accordingly.                                               */
+  __I  uint32_t  RESERVED4[7];
+  PDM_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5[6];
+  PDM_SAMPLE_Type SAMPLE;                           /*!< Unspecified                                                           */
+} NRF_PDM_Type;
+
+
+/* ================================================================================ */
+/* ================                      NVMC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Non Volatile Memory Controller (NVMC)
+  */
+
+typedef struct {                                    /*!< NVMC Structure                                                        */
+  __I  uint32_t  RESERVED0[256];
+  __I  uint32_t  READY;                             /*!< Ready flag                                                            */
+  __I  uint32_t  RESERVED1[64];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  
+  union {
+    __IO uint32_t  ERASEPCR1;                       /*!< Deprecated register - Register for erasing a page in Code area.
+                                                         Equivalent to ERASEPAGE.                                              */
+    __IO uint32_t  ERASEPAGE;                       /*!< Register for erasing a page in Code area                              */
+  };
+  __IO uint32_t  ERASEALL;                          /*!< Register for erasing all non-volatile user memory                     */
+  __IO uint32_t  ERASEPCR0;                         /*!< Deprecated register - Register for erasing a page in Code area.
+                                                         Equivalent to ERASEPAGE.                                              */
+  __IO uint32_t  ERASEUICR;                         /*!< Register for erasing User Information Configuration Registers         */
+  __I  uint32_t  RESERVED2[10];
+  __IO uint32_t  ICACHECNF;                         /*!< I-Code cache configuration register.                                  */
+  __I  uint32_t  RESERVED3;
+  __IO uint32_t  IHIT;                              /*!< I-Code cache hit counter.                                             */
+  __IO uint32_t  IMISS;                             /*!< I-Code cache miss counter.                                            */
+} NRF_NVMC_Type;
+
+
+/* ================================================================================ */
+/* ================                       ACL                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Access control lists (ACL)
+  */
+
+typedef struct {                                    /*!< ACL Structure                                                         */
+  __I  uint32_t  RESERVED0[449];
+  __IO uint32_t  DISABLEINDEBUG;                    /*!< Disable all ACL protection mechanisms for regions while in debug
+                                                         mode                                                                  */
+  __I  uint32_t  RESERVED1[62];
+  ACL_ACL_Type ACL[8];                              /*!< Unspecified                                                           */
+} NRF_ACL_Type;
+
+
+/* ================================================================================ */
+/* ================                       PPI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Programmable Peripheral Interconnect (PPI)
+  */
+
+typedef struct {                                    /*!< PPI Structure                                                         */
+  PPI_TASKS_CHG_Type TASKS_CHG[6];                  /*!< Channel group tasks                                                   */
+  __I  uint32_t  RESERVED0[308];
+  __IO uint32_t  CHEN;                              /*!< Channel enable register                                               */
+  __IO uint32_t  CHENSET;                           /*!< Channel enable set register                                           */
+  __IO uint32_t  CHENCLR;                           /*!< Channel enable clear register                                         */
+  __I  uint32_t  RESERVED1;
+  PPI_CH_Type CH[20];                               /*!< PPI Channel                                                           */
+  __I  uint32_t  RESERVED2[148];
+  __IO uint32_t  CHG[6];                            /*!< Description collection[0]: Channel group 0                            */
+  __I  uint32_t  RESERVED3[62];
+  PPI_FORK_Type FORK[32];                           /*!< Fork                                                                  */
+} NRF_PPI_Type;
+
+
+/* ================================================================================ */
+/* ================                       MWU                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Memory Watch Unit (MWU)
+  */
+
+typedef struct {                                    /*!< MWU Structure                                                         */
+  __I  uint32_t  RESERVED0[64];
+  MWU_EVENTS_REGION_Type EVENTS_REGION[4];          /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED1[16];
+  MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];        /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED2[100];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[5];
+  __IO uint32_t  NMIEN;                             /*!< Enable or disable non-maskable interrupt                              */
+  __IO uint32_t  NMIENSET;                          /*!< Enable non-maskable interrupt                                         */
+  __IO uint32_t  NMIENCLR;                          /*!< Disable non-maskable interrupt                                        */
+  __I  uint32_t  RESERVED4[53];
+  MWU_PERREGION_Type PERREGION[2];                  /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5[64];
+  __IO uint32_t  REGIONEN;                          /*!< Enable/disable regions watch                                          */
+  __IO uint32_t  REGIONENSET;                       /*!< Enable regions watch                                                  */
+  __IO uint32_t  REGIONENCLR;                       /*!< Disable regions watch                                                 */
+  __I  uint32_t  RESERVED6[57];
+  MWU_REGION_Type REGION[4];                        /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED7[32];
+  MWU_PREGION_Type PREGION[2];                      /*!< Unspecified                                                           */
+} NRF_MWU_Type;
+
+
+/* ================================================================================ */
+/* ================                       I2S                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Inter-IC Sound (I2S)
+  */
+
+typedef struct {                                    /*!< I2S Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Starts continuous I2S transfer. Also starts MCK generator when
+                                                         this is enabled.                                                      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stops I2S transfer. Also stops MCK generator. Triggering this
+                                                         task will cause the {event:STOPPED} event to be generated.            */
+  __I  uint32_t  RESERVED0[63];
+  __IO uint32_t  EVENTS_RXPTRUPD;                   /*!< The RXD.PTR register has been copied to internal double-buffers.
+                                                         When the I2S module is started and RX is enabled, this event
+                                                          will be generated for every RXTXD.MAXCNT words that are received
+                                                          on the SDIN pin.                                                     */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< I2S transfer stopped.                                                 */
+  __I  uint32_t  RESERVED1[2];
+  __IO uint32_t  EVENTS_TXPTRUPD;                   /*!< The TDX.PTR register has been copied to internal double-buffers.
+                                                         When the I2S module is started and TX is enabled, this event
+                                                          will be generated for every RXTXD.MAXCNT words that are sent
+                                                          on the SDOUT pin.                                                    */
+  __I  uint32_t  RESERVED2[122];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable I2S module.                                                    */
+  I2S_CONFIG_Type CONFIG;                           /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED4[3];
+  I2S_RXD_Type RXD;                                 /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5;
+  I2S_TXD_Type TXD;                                 /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED6[3];
+  I2S_RXTXD_Type RXTXD;                             /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED7[3];
+  I2S_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+} NRF_I2S_Type;
+
+
+/* ================================================================================ */
+/* ================                       FPU                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief FPU (FPU)
+  */
+
+typedef struct {                                    /*!< FPU Structure                                                         */
+  __I  uint32_t  UNUSED;                            /*!< Unused.                                                               */
+} NRF_FPU_Type;
+
+
+/* ================================================================================ */
+/* ================                      USBD                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Universal Serial Bus device (USBD)
+  */
+
+typedef struct {                                    /*!< USBD Structure                                                        */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STARTEPIN[8];                /*!< Description collection[0]: Captures the EPIN[0].PTR, EPIN[0].MAXCNT
+                                                         and EPIN[0].CONFIG registers values, and enables endpoint IN
+                                                          0 to respond to traffic from host                                    */
+  __O  uint32_t  TASKS_STARTISOIN;                  /*!< Captures the ISOIN.PTR, ISOIN.MAXCNT and ISOIN.CONFIG registers
+                                                         values, and enables sending data on iso endpoint                      */
+  __O  uint32_t  TASKS_STARTEPOUT[8];               /*!< Description collection[0]: Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT
+                                                         and EPOUT[0].CONFIG registers values, and enables endpoint 0
+                                                          to respond to traffic from host                                      */
+  __O  uint32_t  TASKS_STARTISOOUT;                 /*!< Captures the ISOOUT.PTR, ISOOUT.MAXCNT and ISOOUT.CONFIG registers
+                                                         values, and enables receiving of data on iso endpoint                 */
+  __O  uint32_t  TASKS_EP0RCVOUT;                   /*!< Allows OUT data stage on control endpoint 0                           */
+  __O  uint32_t  TASKS_EP0STATUS;                   /*!< Allows status stage on control endpoint 0                             */
+  __O  uint32_t  TASKS_EP0STALL;                    /*!< STALLs data and status stage on control endpoint 0                    */
+  __O  uint32_t  TASKS_DPDMDRIVE;                   /*!< Forces D+ and D-lines to the state defined in the DPDMVALUE
+                                                         register                                                              */
+  __O  uint32_t  TASKS_DPDMNODRIVE;                 /*!< Stops forcing D+ and D- lines to any state (USB engine takes
+                                                         control)                                                              */
+  __I  uint32_t  RESERVED1[40];
+  __IO uint32_t  EVENTS_USBRESET;                   /*!< Signals that a USB reset condition has been detected on the
+                                                         USB lines                                                             */
+  __IO uint32_t  EVENTS_STARTED;                    /*!< Confirms that the EPIN[n].PTR, EPIN[n].MAXCNT, EPIN[n].CONFIG,
+                                                         or EPOUT[n].PTR, EPOUT[n].MAXCNT and EPOUT[n].CONFIG registers
+                                                          have been captured on all endpoints reported in the EPSTATUS
+                                                          register                                                             */
+  __IO uint32_t  EVENTS_ENDEPIN[8];                 /*!< Description collection[0]: The whole EPIN[0] buffer has been
+                                                         consumed. The RAM buffer can be accessed safely by software.          */
+  __IO uint32_t  EVENTS_EP0DATADONE;                /*!< An acknowledged data transfer has taken place on the control
+                                                         endpoint                                                              */
+  __IO uint32_t  EVENTS_ENDISOIN;                   /*!< The whole ISOIN buffer has been consumed. The RAM buffer can
+                                                         be accessed safely by software.                                       */
+  __IO uint32_t  EVENTS_ENDEPOUT[8];                /*!< Description collection[0]: The whole EPOUT[0] buffer has been
+                                                         consumed. The RAM buffer can be accessed safely by software.          */
+  __IO uint32_t  EVENTS_ENDISOOUT;                  /*!< The whole ISOOUT buffer has been consumed. The RAM buffer can
+                                                         be accessed safely by software.                                       */
+  __IO uint32_t  EVENTS_SOF;                        /*!< Signals that a SOF (start of frame) condition has been detected
+                                                         on the USB lines                                                      */
+  __IO uint32_t  EVENTS_USBEVENT;                   /*!< An event or an error not covered by specific events has occurred,
+                                                         check EVENTCAUSE register to find the cause                           */
+  __IO uint32_t  EVENTS_EP0SETUP;                   /*!< A valid SETUP token has been received (and acknowledged) on
+                                                         the control endpoint                                                  */
+  __IO uint32_t  EVENTS_EPDATA;                     /*!< A data transfer has occurred on a data endpoint, indicated by
+                                                         the EPDATASTATUS register                                             */
+  __IO uint32_t  EVENTS_ACCESSFAULT;                /*!< Access to an unavailable USB register has been attempted (software
+                                                         or EasyDMA). This event can get fired even when USBD is not
+                                                          ENABLEd.                                                             */
+  __I  uint32_t  RESERVED2[38];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED4[61];
+  __IO uint32_t  EVENTCAUSE;                        /*!< Details on event that caused the USBEVENT event                       */
+  __I  uint32_t  BUSSTATE;                          /*!< Provides the logic state of the D+ and D- lines                       */
+  __I  uint32_t  RESERVED5[6];
+  USBD_HALTED_Type HALTED;                          /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED6;
+  __IO uint32_t  EPSTATUS;                          /*!< Provides information on which endpoint's EasyDMA registers have
+                                                         been captured                                                         */
+  __IO uint32_t  EPDATASTATUS;                      /*!< Provides information on which endpoint(s) an acknowledged data
+                                                         transfer has occurred (EPDATA event)                                  */
+  __I  uint32_t  USBADDR;                           /*!< Device USB address                                                    */
+  __I  uint32_t  RESERVED7[3];
+  __I  uint32_t  BMREQUESTTYPE;                     /*!< SETUP data, byte 0, bmRequestType                                     */
+  __I  uint32_t  BREQUEST;                          /*!< SETUP data, byte 1, bRequest                                          */
+  __I  uint32_t  WVALUEL;                           /*!< SETUP data, byte 2, LSB of wValue                                     */
+  __I  uint32_t  WVALUEH;                           /*!< SETUP data, byte 3, MSB of wValue                                     */
+  __I  uint32_t  WINDEXL;                           /*!< SETUP data, byte 4, LSB of wIndex                                     */
+  __I  uint32_t  WINDEXH;                           /*!< SETUP data, byte 5, MSB of wIndex                                     */
+  __I  uint32_t  WLENGTHL;                          /*!< SETUP data, byte 6, LSB of wLength                                    */
+  __I  uint32_t  WLENGTHH;                          /*!< SETUP data, byte 7, MSB of wLength                                    */
+  USBD_SIZE_Type SIZE;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED8[15];
+  __IO uint32_t  ENABLE;                            /*!< Enable USB                                                            */
+  __IO uint32_t  USBPULLUP;                         /*!< Control of the USB pull-up                                            */
+  __IO uint32_t  DPDMVALUE;                         /*!< State at which the DPDMDRIVE task will force D+ and D-. The
+                                                         DPDMNODRIVE task reverts the control of the lines to MAC IP
+                                                          (no forcing).                                                        */
+  __IO uint32_t  DTOGGLE;                           /*!< Data toggle control and status.                                       */
+  __IO uint32_t  EPINEN;                            /*!< Endpoint IN enable                                                    */
+  __IO uint32_t  EPOUTEN;                           /*!< Endpoint OUT enable                                                   */
+  __O  uint32_t  EPSTALL;                           /*!< STALL endpoints                                                       */
+  __IO uint32_t  ISOSPLIT;                          /*!< Controls the split of ISO buffers                                     */
+  __I  uint32_t  FRAMECNTR;                         /*!< Returns the current value of the start of frame counter               */
+  __I  uint32_t  RESERVED9[3];
+  __IO uint32_t  ISOINCONFIG;                       /*!< Controls the response of the ISO IN endpoint to an IN token
+                                                         when no data is ready to be sent                                      */
+  __I  uint32_t  RESERVED10[51];
+  USBD_EPIN_Type EPIN[8];                           /*!< Unspecified                                                           */
+  USBD_ISOIN_Type ISOIN;                            /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED11[21];
+  USBD_EPOUT_Type EPOUT[8];                         /*!< Unspecified                                                           */
+  USBD_ISOOUT_Type ISOOUT;                          /*!< Unspecified                                                           */
+} NRF_USBD_Type;
+
+
+/* ================================================================================ */
+/* ================                      QSPI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief External flash interface (QSPI)
+  */
+
+typedef struct {                                    /*!< QSPI Structure                                                        */
+  __O  uint32_t  TASKS_ACTIVATE;                    /*!< Activate QSPI interface                                               */
+  __O  uint32_t  TASKS_READSTART;                   /*!< Start transfer from external flash memory to internal RAM             */
+  __O  uint32_t  TASKS_WRITESTART;                  /*!< Start transfer from internal RAM to external flash memory             */
+  __O  uint32_t  TASKS_ERASESTART;                  /*!< Start external flash memory erase operation                           */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_READY;                      /*!< QSPI peripheral is ready. This event will be generated as a
+                                                         response to any QSPI task.                                            */
+  __I  uint32_t  RESERVED1[127];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable QSPI peripheral and acquire the pins selected in PSELn
+                                                         registers                                                             */
+  QSPI_READ_Type READ;                              /*!< Unspecified                                                           */
+  QSPI_WRITE_Type WRITE;                            /*!< Unspecified                                                           */
+  QSPI_ERASE_Type ERASE;                            /*!< Unspecified                                                           */
+  QSPI_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __IO uint32_t  XIPOFFSET;                         /*!< Address offset into the external memory for Execute in Place
+                                                         operation.                                                            */
+  __IO uint32_t  IFCONFIG0;                         /*!< Interface configuration.                                              */
+  __I  uint32_t  RESERVED3[46];
+  __IO uint32_t  IFCONFIG1;                         /*!< Interface configuration.                                              */
+  __I  uint32_t  STATUS;                            /*!< Status register.                                                      */
+  __I  uint32_t  RESERVED4[3];
+  __IO uint32_t  DPMDUR;                            /*!< Set the duration required to enter/exit deep power-down mode
+                                                         (DPM).                                                                */
+  __I  uint32_t  RESERVED5[3];
+  __IO uint32_t  ADDRCONF;                          /*!< Extended address configuration.                                       */
+  __I  uint32_t  RESERVED6[3];
+  __IO uint32_t  CINSTRCONF;                        /*!< Custom instruction configuration register.                            */
+  __IO uint32_t  CINSTRDAT0;                        /*!< Custom instruction data register 0.                                   */
+  __IO uint32_t  CINSTRDAT1;                        /*!< Custom instruction data register 1.                                   */
+  __IO uint32_t  IFTIMING;                          /*!< SPI interface timing.                                                 */
+} NRF_QSPI_Type;
+
+
+/* ================================================================================ */
+/* ================                      GPIO                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief GPIO Port 1 (GPIO)
+  */
+
+typedef struct {                                    /*!< GPIO Structure                                                        */
+  __I  uint32_t  RESERVED0[321];
+  __IO uint32_t  OUT;                               /*!< Write GPIO port                                                       */
+  __IO uint32_t  OUTSET;                            /*!< Set individual bits in GPIO port                                      */
+  __IO uint32_t  OUTCLR;                            /*!< Clear individual bits in GPIO port                                    */
+  __I  uint32_t  IN;                                /*!< Read GPIO port                                                        */
+  __IO uint32_t  DIR;                               /*!< Direction of GPIO pins                                                */
+  __IO uint32_t  DIRSET;                            /*!< DIR set register                                                      */
+  __IO uint32_t  DIRCLR;                            /*!< DIR clear register                                                    */
+  __IO uint32_t  LATCH;                             /*!< Latch register indicating what GPIO pins that have met the criteria
+                                                         set in the PIN_CNF[n].SENSE registers                                 */
+  __IO uint32_t  DETECTMODE;                        /*!< Select between default DETECT signal behaviour and LDETECT mode       */
+  __I  uint32_t  RESERVED1[118];
+  __IO uint32_t  PIN_CNF[32];                       /*!< Description collection[0]: Configuration of GPIO pins                 */
+} NRF_GPIO_Type;
+
+
+/* ================================================================================ */
+/* ================                   CRYPTOCELL                   ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief ARM CryptoCell register interface (CRYPTOCELL)
+  */
+
+typedef struct {                                    /*!< CRYPTOCELL Structure                                                  */
+  __I  uint32_t  RESERVED0[320];
+  __IO uint32_t  ENABLE;                            /*!< Control power and clock for ARM CryptoCell subsystem                  */
+} NRF_CRYPTOCELL_Type;
+
+
+/* --------------------  End of section using anonymous unions  ------------------- */
+#if defined(__CC_ARM)
+  #pragma pop
+#elif defined(__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+  #pragma warning restore
+#else
+  #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================              Peripheral memory map             ================ */
+/* ================================================================================ */
+
+#define NRF_FICR_BASE                   0x10000000UL
+#define NRF_UICR_BASE                   0x10001000UL
+#define NRF_POWER_BASE                  0x40000000UL
+#define NRF_CLOCK_BASE                  0x40000000UL
+#define NRF_RADIO_BASE                  0x40001000UL
+#define NRF_UARTE0_BASE                 0x40002000UL
+#define NRF_UART0_BASE                  0x40002000UL
+#define NRF_SPIM0_BASE                  0x40003000UL
+#define NRF_SPIS0_BASE                  0x40003000UL
+#define NRF_TWIM0_BASE                  0x40003000UL
+#define NRF_TWIS0_BASE                  0x40003000UL
+#define NRF_SPI0_BASE                   0x40003000UL
+#define NRF_TWI0_BASE                   0x40003000UL
+#define NRF_SPIM1_BASE                  0x40004000UL
+#define NRF_SPIS1_BASE                  0x40004000UL
+#define NRF_TWIM1_BASE                  0x40004000UL
+#define NRF_TWIS1_BASE                  0x40004000UL
+#define NRF_SPI1_BASE                   0x40004000UL
+#define NRF_TWI1_BASE                   0x40004000UL
+#define NRF_NFCT_BASE                   0x40005000UL
+#define NRF_GPIOTE_BASE                 0x40006000UL
+#define NRF_SAADC_BASE                  0x40007000UL
+#define NRF_TIMER0_BASE                 0x40008000UL
+#define NRF_TIMER1_BASE                 0x40009000UL
+#define NRF_TIMER2_BASE                 0x4000A000UL
+#define NRF_RTC0_BASE                   0x4000B000UL
+#define NRF_TEMP_BASE                   0x4000C000UL
+#define NRF_RNG_BASE                    0x4000D000UL
+#define NRF_ECB_BASE                    0x4000E000UL
+#define NRF_CCM_BASE                    0x4000F000UL
+#define NRF_AAR_BASE                    0x4000F000UL
+#define NRF_WDT_BASE                    0x40010000UL
+#define NRF_RTC1_BASE                   0x40011000UL
+#define NRF_QDEC_BASE                   0x40012000UL
+#define NRF_COMP_BASE                   0x40013000UL
+#define NRF_LPCOMP_BASE                 0x40013000UL
+#define NRF_SWI0_BASE                   0x40014000UL
+#define NRF_EGU0_BASE                   0x40014000UL
+#define NRF_SWI1_BASE                   0x40015000UL
+#define NRF_EGU1_BASE                   0x40015000UL
+#define NRF_SWI2_BASE                   0x40016000UL
+#define NRF_EGU2_BASE                   0x40016000UL
+#define NRF_SWI3_BASE                   0x40017000UL
+#define NRF_EGU3_BASE                   0x40017000UL
+#define NRF_SWI4_BASE                   0x40018000UL
+#define NRF_EGU4_BASE                   0x40018000UL
+#define NRF_SWI5_BASE                   0x40019000UL
+#define NRF_EGU5_BASE                   0x40019000UL
+#define NRF_TIMER3_BASE                 0x4001A000UL
+#define NRF_TIMER4_BASE                 0x4001B000UL
+#define NRF_PWM0_BASE                   0x4001C000UL
+#define NRF_PDM_BASE                    0x4001D000UL
+#define NRF_NVMC_BASE                   0x4001E000UL
+#define NRF_ACL_BASE                    0x4001E000UL
+#define NRF_PPI_BASE                    0x4001F000UL
+#define NRF_MWU_BASE                    0x40020000UL
+#define NRF_PWM1_BASE                   0x40021000UL
+#define NRF_PWM2_BASE                   0x40022000UL
+#define NRF_SPIM2_BASE                  0x40023000UL
+#define NRF_SPIS2_BASE                  0x40023000UL
+#define NRF_SPI2_BASE                   0x40023000UL
+#define NRF_RTC2_BASE                   0x40024000UL
+#define NRF_I2S_BASE                    0x40025000UL
+#define NRF_FPU_BASE                    0x40026000UL
+#define NRF_USBD_BASE                   0x40027000UL
+#define NRF_UARTE1_BASE                 0x40028000UL
+#define NRF_QSPI_BASE                   0x40029000UL
+#define NRF_SPIM3_BASE                  0x4002B000UL
+#define NRF_PWM3_BASE                   0x4002D000UL
+#define NRF_P0_BASE                     0x50000000UL
+#define NRF_P1_BASE                     0x50000300UL
+#define NRF_CRYPTOCELL_BASE             0x5002A000UL
+
+
+/* ================================================================================ */
+/* ================             Peripheral declaration             ================ */
+/* ================================================================================ */
+
+#define NRF_FICR                        ((NRF_FICR_Type           *) NRF_FICR_BASE)
+#define NRF_UICR                        ((NRF_UICR_Type           *) NRF_UICR_BASE)
+#define NRF_POWER                       ((NRF_POWER_Type          *) NRF_POWER_BASE)
+#define NRF_CLOCK                       ((NRF_CLOCK_Type          *) NRF_CLOCK_BASE)
+#define NRF_RADIO                       ((NRF_RADIO_Type          *) NRF_RADIO_BASE)
+#define NRF_UARTE0                      ((NRF_UARTE_Type          *) NRF_UARTE0_BASE)
+#define NRF_UART0                       ((NRF_UART_Type           *) NRF_UART0_BASE)
+#define NRF_SPIM0                       ((NRF_SPIM_Type           *) NRF_SPIM0_BASE)
+#define NRF_SPIS0                       ((NRF_SPIS_Type           *) NRF_SPIS0_BASE)
+#define NRF_TWIM0                       ((NRF_TWIM_Type           *) NRF_TWIM0_BASE)
+#define NRF_TWIS0                       ((NRF_TWIS_Type           *) NRF_TWIS0_BASE)
+#define NRF_SPI0                        ((NRF_SPI_Type            *) NRF_SPI0_BASE)
+#define NRF_TWI0                        ((NRF_TWI_Type            *) NRF_TWI0_BASE)
+#define NRF_SPIM1                       ((NRF_SPIM_Type           *) NRF_SPIM1_BASE)
+#define NRF_SPIS1                       ((NRF_SPIS_Type           *) NRF_SPIS1_BASE)
+#define NRF_TWIM1                       ((NRF_TWIM_Type           *) NRF_TWIM1_BASE)
+#define NRF_TWIS1                       ((NRF_TWIS_Type           *) NRF_TWIS1_BASE)
+#define NRF_SPI1                        ((NRF_SPI_Type            *) NRF_SPI1_BASE)
+#define NRF_TWI1                        ((NRF_TWI_Type            *) NRF_TWI1_BASE)
+#define NRF_NFCT                        ((NRF_NFCT_Type           *) NRF_NFCT_BASE)
+#define NRF_GPIOTE                      ((NRF_GPIOTE_Type         *) NRF_GPIOTE_BASE)
+#define NRF_SAADC                       ((NRF_SAADC_Type          *) NRF_SAADC_BASE)
+#define NRF_TIMER0                      ((NRF_TIMER_Type          *) NRF_TIMER0_BASE)
+#define NRF_TIMER1                      ((NRF_TIMER_Type          *) NRF_TIMER1_BASE)
+#define NRF_TIMER2                      ((NRF_TIMER_Type          *) NRF_TIMER2_BASE)
+#define NRF_RTC0                        ((NRF_RTC_Type            *) NRF_RTC0_BASE)
+#define NRF_TEMP                        ((NRF_TEMP_Type           *) NRF_TEMP_BASE)
+#define NRF_RNG                         ((NRF_RNG_Type            *) NRF_RNG_BASE)
+#define NRF_ECB                         ((NRF_ECB_Type            *) NRF_ECB_BASE)
+#define NRF_CCM                         ((NRF_CCM_Type            *) NRF_CCM_BASE)
+#define NRF_AAR                         ((NRF_AAR_Type            *) NRF_AAR_BASE)
+#define NRF_WDT                         ((NRF_WDT_Type            *) NRF_WDT_BASE)
+#define NRF_RTC1                        ((NRF_RTC_Type            *) NRF_RTC1_BASE)
+#define NRF_QDEC                        ((NRF_QDEC_Type           *) NRF_QDEC_BASE)
+#define NRF_COMP                        ((NRF_COMP_Type           *) NRF_COMP_BASE)
+#define NRF_LPCOMP                      ((NRF_LPCOMP_Type         *) NRF_LPCOMP_BASE)
+#define NRF_SWI0                        ((NRF_SWI_Type            *) NRF_SWI0_BASE)
+#define NRF_EGU0                        ((NRF_EGU_Type            *) NRF_EGU0_BASE)
+#define NRF_SWI1                        ((NRF_SWI_Type            *) NRF_SWI1_BASE)
+#define NRF_EGU1                        ((NRF_EGU_Type            *) NRF_EGU1_BASE)
+#define NRF_SWI2                        ((NRF_SWI_Type            *) NRF_SWI2_BASE)
+#define NRF_EGU2                        ((NRF_EGU_Type            *) NRF_EGU2_BASE)
+#define NRF_SWI3                        ((NRF_SWI_Type            *) NRF_SWI3_BASE)
+#define NRF_EGU3                        ((NRF_EGU_Type            *) NRF_EGU3_BASE)
+#define NRF_SWI4                        ((NRF_SWI_Type            *) NRF_SWI4_BASE)
+#define NRF_EGU4                        ((NRF_EGU_Type            *) NRF_EGU4_BASE)
+#define NRF_SWI5                        ((NRF_SWI_Type            *) NRF_SWI5_BASE)
+#define NRF_EGU5                        ((NRF_EGU_Type            *) NRF_EGU5_BASE)
+#define NRF_TIMER3                      ((NRF_TIMER_Type          *) NRF_TIMER3_BASE)
+#define NRF_TIMER4                      ((NRF_TIMER_Type          *) NRF_TIMER4_BASE)
+#define NRF_PWM0                        ((NRF_PWM_Type            *) NRF_PWM0_BASE)
+#define NRF_PDM                         ((NRF_PDM_Type            *) NRF_PDM_BASE)
+#define NRF_NVMC                        ((NRF_NVMC_Type           *) NRF_NVMC_BASE)
+#define NRF_ACL                         ((NRF_ACL_Type            *) NRF_ACL_BASE)
+#define NRF_PPI                         ((NRF_PPI_Type            *) NRF_PPI_BASE)
+#define NRF_MWU                         ((NRF_MWU_Type            *) NRF_MWU_BASE)
+#define NRF_PWM1                        ((NRF_PWM_Type            *) NRF_PWM1_BASE)
+#define NRF_PWM2                        ((NRF_PWM_Type            *) NRF_PWM2_BASE)
+#define NRF_SPIM2                       ((NRF_SPIM_Type           *) NRF_SPIM2_BASE)
+#define NRF_SPIS2                       ((NRF_SPIS_Type           *) NRF_SPIS2_BASE)
+#define NRF_SPI2                        ((NRF_SPI_Type            *) NRF_SPI2_BASE)
+#define NRF_RTC2                        ((NRF_RTC_Type            *) NRF_RTC2_BASE)
+#define NRF_I2S                         ((NRF_I2S_Type            *) NRF_I2S_BASE)
+#define NRF_FPU                         ((NRF_FPU_Type            *) NRF_FPU_BASE)
+#define NRF_USBD                        ((NRF_USBD_Type           *) NRF_USBD_BASE)
+#define NRF_UARTE1                      ((NRF_UARTE_Type          *) NRF_UARTE1_BASE)
+#define NRF_QSPI                        ((NRF_QSPI_Type           *) NRF_QSPI_BASE)
+#define NRF_SPIM3                       ((NRF_SPIM_Type           *) NRF_SPIM3_BASE)
+#define NRF_PWM3                        ((NRF_PWM_Type            *) NRF_PWM3_BASE)
+#define NRF_P0                          ((NRF_GPIO_Type           *) NRF_P0_BASE)
+#define NRF_P1                          ((NRF_GPIO_Type           *) NRF_P1_BASE)
+#define NRF_CRYPTOCELL                  ((NRF_CRYPTOCELL_Type     *) NRF_CRYPTOCELL_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group nrf52840 */
+/** @} */ /* End of group Nordic Semiconductor */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif  /* nrf52840_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52840_bitfields.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,14641 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+#ifndef __NRF52840_BITS_H
+#define __NRF52840_BITS_H
+
+/*lint ++flb "Enter library region" */
+
+/* Peripheral: AAR */
+/* Description: Accelerated Address Resolver */
+
+/* Register: AAR_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
+#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */
+#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for END event */
+#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Register: AAR_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
+#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */
+#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for END event */
+#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Register: AAR_STATUS */
+/* Description: Resolution status */
+
+/* Bits 3..0 : The IRK that was used last time an address was resolved */
+#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+
+/* Register: AAR_ENABLE */
+/* Description: Enable AAR */
+
+/* Bits 1..0 : Enable or disable AAR */
+#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
+
+/* Register: AAR_NIRK */
+/* Description: Number of IRKs */
+
+/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
+#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
+#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
+
+/* Register: AAR_IRKPTR */
+/* Description: Pointer to IRK data structure */
+
+/* Bits 31..0 : Pointer to the IRK data structure */
+#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
+#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
+
+/* Register: AAR_ADDRPTR */
+/* Description: Pointer to the resolvable address */
+
+/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
+#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
+#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
+
+/* Register: AAR_SCRATCHPTR */
+/* Description: Pointer to data area used for temporary storage */
+
+/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */
+#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
+#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
+
+
+/* Peripheral: ACL */
+/* Description: Access control lists */
+
+/* Register: ACL_DISABLEINDEBUG */
+/* Description: Disable all ACL protection mechanisms for regions while in debug mode */
+
+/* Bit 0 : Disable the protection mechanism for regions while in debug mode. */
+#define ACL_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
+#define ACL_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << ACL_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
+#define ACL_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< ACL is enabled in debug mode */
+#define ACL_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< ACL is disabled in debug mode */
+
+/* Register: ACL_ACL_ADDR */
+/* Description: Description cluster[0]:  Configure the word-aligned start address of region 0 to protect */
+
+/* Bits 31..0 : Valid word-aligned start address of region 0 to protect. Address must point to a flash page boundary. */
+#define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
+#define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
+
+/* Register: ACL_ACL_SIZE */
+/* Description: Description cluster[0]:  Size of region to protect counting from address ACL[0].ADDR. Write '0' as no effect. */
+
+/* Bits 31..0 : Size of flash region 0 in bytes. Must be a multiple of the flash page size. */
+#define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */
+#define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */
+
+/* Register: ACL_ACL_PERM */
+/* Description: Description cluster[0]:  Access permissions for region 0 as defined by start address ACL[0].ADDR and size ACL[0].SIZE */
+
+/* Bit 2 : Configure read permissions for region 0. Write '0' has no effect. */
+#define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */
+#define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */
+#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region 0 */
+#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region 0 */
+
+/* Bit 1 : Configure write and erase permissions for region 0. Write '0' has no effect. */
+#define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */
+#define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region 0 */
+#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region 0 */
+
+
+/* Peripheral: CCM */
+/* Description: AES CCM Mode Encryption */
+
+/* Register: CCM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: CCM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for ERROR event */
+#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */
+#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */
+#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
+
+/* Register: CCM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for ERROR event */
+#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */
+#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */
+#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
+
+/* Register: CCM_MICSTATUS */
+/* Description: MIC check result */
+
+/* Bit 0 : The result of the MIC check performed during the previous decryption operation */
+#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
+#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
+
+/* Register: CCM_ENABLE */
+/* Description: Enable */
+
+/* Bits 1..0 : Enable or disable CCM */
+#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
+
+/* Register: CCM_MODE */
+/* Description: Operation mode */
+
+/* Bit 24 : Packet length configuration */
+#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
+#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
+#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packets up to 27 bytes will be generated. */
+#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packets up to MAXPACKETSIZE bytes will be generated. */
+
+/* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */
+#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
+#define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
+#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */
+#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */
+#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */
+#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */
+
+/* Bit 0 : The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. */
+#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
+#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
+
+/* Register: CCM_CNFPTR */
+/* Description: Pointer to data structure holding AES key and NONCE vector */
+
+/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
+#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
+#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
+
+/* Register: CCM_INPTR */
+/* Description: Input pointer */
+
+/* Bits 31..0 : Input pointer */
+#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
+#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
+
+/* Register: CCM_OUTPTR */
+/* Description: Output pointer */
+
+/* Bits 31..0 : Output pointer */
+#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
+#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
+
+/* Register: CCM_SCRATCHPTR */
+/* Description: Pointer to data area used for temporary storage */
+
+/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */
+#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
+#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
+
+/* Register: CCM_MAXPACKETSIZE */
+/* Description: Length of key-stream generated when MODE.LENGTH = Extended. */
+
+/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet to be encrypted/decrypted. */
+#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */
+#define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */
+
+/* Register: CCM_RATEOVERRIDE */
+/* Description: Data rate override setting. */
+
+/* Bits 1..0 : Data rate override setting. */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_Pos (0UL) /*!< Position of RATEOVERRIDE field. */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */
+#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */
+
+
+/* Peripheral: CLOCK */
+/* Description: Clock control */
+
+/* Register: CLOCK_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 4 : Write '1' to Enable interrupt for CTTO event */
+#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for DONE event */
+#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */
+#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */
+#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
+
+/* Register: CLOCK_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 4 : Write '1' to Disable interrupt for CTTO event */
+#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for DONE event */
+#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
+
+/* Register: CLOCK_HFCLKRUN */
+/* Description: Status indicating that HFCLKSTART task has been triggered */
+
+/* Bit 0 : HFCLKSTART task triggered or not */
+#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
+#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
+
+/* Register: CLOCK_HFCLKSTAT */
+/* Description: HFCLK status */
+
+/* Bit 16 : HFCLK state */
+#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
+#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
+
+/* Bit 0 : Source of HFCLK */
+#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
+#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
+
+/* Register: CLOCK_LFCLKRUN */
+/* Description: Status indicating that LFCLKSTART task has been triggered */
+
+/* Bit 0 : LFCLKSTART task triggered or not */
+#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
+#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
+
+/* Register: CLOCK_LFCLKSTAT */
+/* Description: LFCLK status */
+
+/* Bit 16 : LFCLK state */
+#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
+#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
+
+/* Bits 1..0 : Source of LFCLK */
+#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
+#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
+#define CLOCK_LFCLKSTAT_SRC_LFULP (3UL) /*!< 32.768 kHz ultra low power RC oscillator */
+
+/* Register: CLOCK_LFCLKSRCCOPY */
+/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
+
+/* Bits 1..0 : Clock source */
+#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
+#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
+#define CLOCK_LFCLKSRCCOPY_SRC_LFULP (3UL) /*!< 32.768 kHz ultra low power RC oscillator */
+
+/* Register: CLOCK_LFCLKSRC */
+/* Description: Clock source for the LFCLK */
+
+/* Bit 17 : Enable or disable external source for LFCLK */
+#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */
+#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */
+#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */
+#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */
+
+/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
+#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */
+#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
+#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */
+#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
+
+/* Bits 1..0 : Clock source */
+#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
+#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
+#define CLOCK_LFCLKSRC_SRC_LFULP (3UL) /*!< 32.768 kHz ultra low power RC oscillator */
+
+/* Register: CLOCK_CTIV */
+/* Description: Calibration timer interval */
+
+/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
+#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
+#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
+
+/* Register: CLOCK_TRACECONFIG */
+/* Description: Clocking options for the Trace Port debug interface */
+
+/* Bits 17..16 : Pin multiplexing of trace signals. */
+#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
+#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
+#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */
+#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */
+#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */
+
+/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */
+
+
+/* Peripheral: COMP */
+/* Description: Comparator */
+
+/* Register: COMP_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between CROSS event and STOP task */
+#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
+#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
+#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between UP event and STOP task */
+#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
+#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
+#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between DOWN event and STOP task */
+#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
+#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
+#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between READY event and STOP task */
+#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
+#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
+#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between READY event and SAMPLE task */
+#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
+#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
+#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: COMP_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 3 : Enable or disable interrupt for CROSS event */
+#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for UP event */
+#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
+#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
+#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for DOWN event */
+#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for READY event */
+#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
+#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
+#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
+
+/* Register: COMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 3 : Write '1' to Enable interrupt for CROSS event */
+#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for UP event */
+#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
+#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
+#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for DOWN event */
+#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: COMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 3 : Write '1' to Disable interrupt for CROSS event */
+#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for UP event */
+#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
+#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
+#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for DOWN event */
+#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: COMP_RESULT */
+/* Description: Compare result */
+
+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
+#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
+#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
+
+/* Register: COMP_ENABLE */
+/* Description: COMP enable */
+
+/* Bits 1..0 : Enable or disable COMP */
+#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
+
+/* Register: COMP_PSEL */
+/* Description: Pin select */
+
+/* Bits 2..0 : Analog pin select */
+#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
+#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
+
+/* Register: COMP_REFSEL */
+/* Description: Reference source select */
+
+/* Bits 2..0 : Reference select */
+#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
+#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
+#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
+#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
+#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
+#define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) */
+
+/* Register: COMP_EXTREFSEL */
+/* Description: External reference select */
+
+/* Bit 0 : External analog reference select */
+#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
+#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
+
+/* Register: COMP_TH */
+/* Description: Threshold configuration for hysteresis unit */
+
+/* Bits 13..8 : VUP = (THUP+1)/64*VREF */
+#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
+#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
+
+/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
+#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
+#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
+
+/* Register: COMP_MODE */
+/* Description: Mode configuration */
+
+/* Bit 8 : Main operation mode */
+#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
+#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
+#define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */
+#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
+
+/* Bits 1..0 : Speed and power mode */
+#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
+#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
+#define COMP_MODE_SP_Low (0UL) /*!< Low power mode */
+#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
+#define COMP_MODE_SP_High (2UL) /*!< High speed mode */
+
+/* Register: COMP_HYST */
+/* Description: Comparator hysteresis enable */
+
+/* Bit 0 : Comparator hysteresis */
+#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
+#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
+#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
+#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
+
+/* Register: COMP_ISOURCE */
+/* Description: Current source select on analog input */
+
+/* Bits 1..0 : Comparator hysteresis */
+#define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */
+#define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */
+#define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */
+#define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
+#define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
+#define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */
+
+
+/* Peripheral: CRYPTOCELL */
+/* Description: ARM CryptoCell register interface */
+
+/* Register: CRYPTOCELL_ENABLE */
+/* Description: Control power and clock for ARM CryptoCell subsystem */
+
+/* Bit 0 : Enable or disable the CryptoCell subsystem */
+#define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CryptoCell subsystem disabled */
+#define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CryptoCell subsystem enabled */
+
+
+/* Peripheral: ECB */
+/* Description: AES ECB Mode Encryption */
+
+/* Register: ECB_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */
+#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for ENDECB event */
+#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
+
+/* Register: ECB_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */
+#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for ENDECB event */
+#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
+
+/* Register: ECB_ECBDATAPTR */
+/* Description: ECB block encrypt memory pointers */
+
+/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
+#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
+#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
+
+
+/* Peripheral: EGU */
+/* Description: Event Generator Unit 0 */
+
+/* Register: EGU_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
+#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
+#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
+#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
+#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
+#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
+#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
+#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
+#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
+#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
+#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
+#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
+#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
+#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
+#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
+#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
+#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
+
+/* Register: EGU_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */
+#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */
+#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */
+#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */
+#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */
+#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */
+#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */
+#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */
+#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */
+#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */
+#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */
+#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */
+#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */
+#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */
+#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */
+#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */
+#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
+
+/* Register: EGU_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */
+#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */
+#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */
+#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */
+#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */
+#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */
+#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */
+#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */
+#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */
+#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */
+#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */
+#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */
+#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */
+#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */
+#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */
+#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */
+#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
+
+
+/* Peripheral: FICR */
+/* Description: Factory Information Configuration Registers */
+
+/* Register: FICR_CODEPAGESIZE */
+/* Description: Code memory page size */
+
+/* Bits 31..0 : Code memory page size */
+#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
+#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
+
+/* Register: FICR_CODESIZE */
+/* Description: Code memory size */
+
+/* Bits 31..0 : Code memory size in number of pages */
+#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
+#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
+
+/* Register: FICR_DEVICEID */
+/* Description: Description collection[0]:  Device identifier */
+
+/* Bits 31..0 : 64 bit unique device identifier */
+#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
+#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
+
+/* Register: FICR_ER */
+/* Description: Description collection[0]:  Encryption root, word 0 */
+
+/* Bits 31..0 : Encryption root, word 0 */
+#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
+#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
+
+/* Register: FICR_IR */
+/* Description: Description collection[0]:  Identity Root, word 0 */
+
+/* Bits 31..0 : Identity Root, word 0 */
+#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
+#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
+
+/* Register: FICR_DEVICEADDRTYPE */
+/* Description: Device address type */
+
+/* Bit 0 : Device address type */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
+
+/* Register: FICR_DEVICEADDR */
+/* Description: Description collection[0]:  Device address 0 */
+
+/* Bits 31..0 : 48 bit device address */
+#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
+#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
+
+/* Register: FICR_INFO_PART */
+/* Description: Part code */
+
+/* Bits 31..0 : Part code */
+#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
+#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
+#define FICR_INFO_PART_PART_N52840 (0x52840UL) /*!< nRF52840 */
+#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_VARIANT */
+/* Description: Part variant (hardware version and production configuration). */
+
+/* Bits 31..0 : Part variant (hardware version and production configuration). Encoded as ASCII. */
+#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
+#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
+#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
+#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */
+#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */
+#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
+#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
+#define FICR_INFO_VARIANT_VARIANT_ABBA (0x41424241UL) /*!< ABBA */
+#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_PACKAGE */
+/* Description: Package option */
+
+/* Bits 31..0 : Package option */
+#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 73-pin aQFN */
+#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_RAM */
+/* Description: RAM variant */
+
+/* Bits 31..0 : RAM variant */
+#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
+#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
+#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
+#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
+#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
+#define FICR_INFO_RAM_RAM_K128 (0x80UL) /*!< 128 kByte RAM */
+#define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kByte RAM */
+#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_FLASH */
+/* Description: Flash variant */
+
+/* Bits 31..0 : Flash variant */
+#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
+#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
+#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MByte FLASH */
+#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_TEMP_A0 */
+/* Description: Slope definition A0. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A1 */
+/* Description: Slope definition A1. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A2 */
+/* Description: Slope definition A2. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A3 */
+/* Description: Slope definition A3. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A4 */
+/* Description: Slope definition A4. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A5 */
+/* Description: Slope definition A5. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_B0 */
+/* Description: y-intercept B0. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B1 */
+/* Description: y-intercept B1. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B2 */
+/* Description: y-intercept B2. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B3 */
+/* Description: y-intercept B3. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B4 */
+/* Description: y-intercept B4. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B5 */
+/* Description: y-intercept B5. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_T0 */
+/* Description: Segment end T0. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T1 */
+/* Description: Segment end T1. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T2 */
+/* Description: Segment end T2. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T3 */
+/* Description: Segment end T3. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T4 */
+/* Description: Segment end T4. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_NFC_TAGHEADER0 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 3 */
+#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
+#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
+
+/* Bits 23..16 : Unique identifier byte 2 */
+#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
+#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
+
+/* Bits 15..8 : Unique identifier byte 1 */
+#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
+#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
+
+/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
+#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
+#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
+
+/* Register: FICR_NFC_TAGHEADER1 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 7 */
+#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
+#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
+
+/* Bits 23..16 : Unique identifier byte 6 */
+#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
+#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
+
+/* Bits 15..8 : Unique identifier byte 5 */
+#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
+#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
+
+/* Bits 7..0 : Unique identifier byte 4 */
+#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
+#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
+
+/* Register: FICR_NFC_TAGHEADER2 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 11 */
+#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
+#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
+
+/* Bits 23..16 : Unique identifier byte 10 */
+#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
+#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
+
+/* Bits 15..8 : Unique identifier byte 9 */
+#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
+#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
+
+/* Bits 7..0 : Unique identifier byte 8 */
+#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
+#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
+
+/* Register: FICR_NFC_TAGHEADER3 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 15 */
+#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
+#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
+
+/* Bits 23..16 : Unique identifier byte 14 */
+#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
+#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
+
+/* Bits 15..8 : Unique identifier byte 13 */
+#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
+#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
+
+/* Bits 7..0 : Unique identifier byte 12 */
+#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
+#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
+
+
+/* Peripheral: GPIOTE */
+/* Description: GPIO Tasks and Events */
+
+/* Register: GPIOTE_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 31 : Write '1' to Enable interrupt for PORT event */
+#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for IN[7] event */
+#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for IN[6] event */
+#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for IN[5] event */
+#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for IN[4] event */
+#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for IN[3] event */
+#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for IN[2] event */
+#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for IN[1] event */
+#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for IN[0] event */
+#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
+
+/* Register: GPIOTE_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 31 : Write '1' to Disable interrupt for PORT event */
+#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for IN[7] event */
+#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for IN[6] event */
+#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for IN[5] event */
+#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for IN[4] event */
+#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for IN[3] event */
+#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for IN[2] event */
+#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for IN[1] event */
+#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for IN[0] event */
+#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
+
+/* Register: GPIOTE_CONFIG */
+/* Description: Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
+
+/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
+#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
+#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
+
+/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
+#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
+#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
+#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
+#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
+
+/* Bits 14..13 : Port number */
+#define GPIOTE_CONFIG_PORT_Pos (13UL) /*!< Position of PORT field. */
+#define GPIOTE_CONFIG_PORT_Msk (0x3UL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
+#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
+#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
+
+/* Bits 1..0 : Mode */
+#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
+#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
+#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
+
+
+/* Peripheral: I2S */
+/* Description: Inter-IC Sound */
+
+/* Register: I2S_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */
+#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for STOPPED event */
+#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
+#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
+
+/* Register: I2S_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */
+#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for STOPPED event */
+#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */
+#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
+
+/* Register: I2S_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */
+#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for STOPPED event */
+#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */
+#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
+
+/* Register: I2S_ENABLE */
+/* Description: Enable I2S module. */
+
+/* Bit 0 : Enable I2S module. */
+#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: I2S_CONFIG_MODE */
+/* Description: I2S mode. */
+
+/* Bit 0 : I2S mode. */
+#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
+#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
+
+/* Register: I2S_CONFIG_RXEN */
+/* Description: Reception (RX) enable. */
+
+/* Bit 0 : Reception (RX) enable. */
+#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
+#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
+#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
+#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
+
+/* Register: I2S_CONFIG_TXEN */
+/* Description: Transmission (TX) enable. */
+
+/* Bit 0 : Transmission (TX) enable. */
+#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
+#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
+#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
+#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
+
+/* Register: I2S_CONFIG_MCKEN */
+/* Description: Master clock generator enable. */
+
+/* Bit 0 : Master clock generator enable. */
+#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
+#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
+#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
+#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
+
+/* Register: I2S_CONFIG_MCKFREQ */
+/* Description: Master clock generator frequency. */
+
+/* Bits 31..0 : Master clock generator frequency. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */
+
+/* Register: I2S_CONFIG_RATIO */
+/* Description: MCK / LRCK ratio. */
+
+/* Bits 3..0 : MCK / LRCK ratio. */
+#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
+#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
+#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
+#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
+#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
+#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
+#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
+#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
+#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
+#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
+#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
+
+/* Register: I2S_CONFIG_SWIDTH */
+/* Description: Sample width. */
+
+/* Bits 1..0 : Sample width. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
+
+/* Register: I2S_CONFIG_ALIGN */
+/* Description: Alignment of sample within a frame. */
+
+/* Bit 0 : Alignment of sample within a frame. */
+#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
+#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
+#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
+#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
+
+/* Register: I2S_CONFIG_FORMAT */
+/* Description: Frame format. */
+
+/* Bit 0 : Frame format. */
+#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
+#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
+#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
+#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
+
+/* Register: I2S_CONFIG_CHANNELS */
+/* Description: Enable channels. */
+
+/* Bits 1..0 : Enable channels. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
+
+/* Register: I2S_RXD_PTR */
+/* Description: Receive buffer RAM start address. */
+
+/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
+#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: I2S_TXD_PTR */
+/* Description: Transmit buffer RAM start address. */
+
+/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
+#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: I2S_RXTXD_MAXCNT */
+/* Description: Size of RXD and TXD buffers. */
+
+/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
+#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: I2S_PSEL_MCK */
+/* Description: Pin select for MCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 9..8 : Port number */
+#define I2S_PSEL_MCK_PORT_Pos (8UL) /*!< Position of PORT field. */
+#define I2S_PSEL_MCK_PORT_Msk (0x3UL << I2S_PSEL_MCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SCK */
+/* Description: Pin select for SCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 9..8 : Port number */
+#define I2S_PSEL_SCK_PORT_Pos (8UL) /*!< Position of PORT field. */
+#define I2S_PSEL_SCK_PORT_Msk (0x3UL << I2S_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_LRCK */
+/* Description: Pin select for LRCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 9..8 : Port number */
+#define I2S_PSEL_LRCK_PORT_Pos (8UL) /*!< Position of PORT field. */
+#define I2S_PSEL_LRCK_PORT_Msk (0x3UL << I2S_PSEL_LRCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SDIN */
+/* Description: Pin select for SDIN signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 9..8 : Port number */
+#define I2S_PSEL_SDIN_PORT_Pos (8UL) /*!< Position of PORT field. */
+#define I2S_PSEL_SDIN_PORT_Msk (0x3UL << I2S_PSEL_SDIN_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SDOUT */
+/* Description: Pin select for SDOUT signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 9..8 : Port number */
+#define I2S_PSEL_SDOUT_PORT_Pos (8UL) /*!< Position of PORT field. */
+#define I2S_PSEL_SDOUT_PORT_Msk (0x3UL << I2S_PSEL_SDOUT_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
+
+
+/* Peripheral: LPCOMP */
+/* Description: Low Power Comparator */
+
+/* Register: LPCOMP_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between CROSS event and STOP task */
+#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between UP event and STOP task */
+#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between DOWN event and STOP task */
+#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between READY event and STOP task */
+#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between READY event and SAMPLE task */
+#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: LPCOMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 3 : Write '1' to Enable interrupt for CROSS event */
+#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for UP event */
+#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for DOWN event */
+#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: LPCOMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 3 : Write '1' to Disable interrupt for CROSS event */
+#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for UP event */
+#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for DOWN event */
+#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: LPCOMP_RESULT */
+/* Description: Compare result */
+
+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
+#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-). */
+#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-). */
+
+/* Register: LPCOMP_ENABLE */
+/* Description: Enable LPCOMP */
+
+/* Bits 1..0 : Enable or disable LPCOMP */
+#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: LPCOMP_PSEL */
+/* Description: Input pin select */
+
+/* Bits 2..0 : Analog pin select */
+#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
+#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
+
+/* Register: LPCOMP_REFSEL */
+/* Description: Reference select */
+
+/* Bits 3..0 : Reference select */
+#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
+#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
+
+/* Register: LPCOMP_EXTREFSEL */
+/* Description: External reference select */
+
+/* Bit 0 : External analog reference select */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
+
+/* Register: LPCOMP_ANADETECT */
+/* Description: Analog detect configuration */
+
+/* Bits 1..0 : Analog detect configuration */
+#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
+#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
+#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
+
+/* Register: LPCOMP_HYST */
+/* Description: Comparator hysteresis enable */
+
+/* Bit 0 : Comparator hysteresis enable */
+#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
+#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
+#define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
+#define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */
+
+
+/* Peripheral: MWU */
+/* Description: Memory Watch Unit */
+
+/* Register: MWU_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
+#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
+#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */
+#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */
+#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */
+#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */
+#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
+#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
+#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
+#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
+#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
+#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */
+#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Register: MWU_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */
+#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */
+#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */
+#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */
+#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */
+#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */
+#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */
+#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */
+#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */
+#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */
+#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */
+#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */
+#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
+
+/* Register: MWU_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */
+#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */
+#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */
+#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */
+#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */
+#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */
+#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */
+#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */
+#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */
+#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */
+#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */
+#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */
+#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
+
+/* Register: MWU_NMIEN */
+/* Description: Enable or disable non-maskable interrupt */
+
+/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
+#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
+#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
+#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
+#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
+#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
+#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
+#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
+#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
+#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
+#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
+#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
+#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Register: MWU_NMIENSET */
+/* Description: Enable non-maskable interrupt */
+
+/* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */
+#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */
+#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */
+#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */
+#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */
+#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */
+#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */
+#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */
+#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */
+#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */
+#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */
+#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */
+#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
+
+/* Register: MWU_NMIENCLR */
+/* Description: Disable non-maskable interrupt */
+
+/* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */
+#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */
+#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */
+#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */
+#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */
+#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */
+#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */
+#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */
+#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */
+#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */
+#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */
+#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */
+#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
+
+/* Register: MWU_PERREGION_SUBSTATWA */
+/* Description: Description cluster[0]:  Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */
+
+/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
+#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
+#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
+#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
+#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
+#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
+#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
+#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
+#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
+#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
+#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
+#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
+#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
+#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
+#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
+#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
+#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
+#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
+#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
+#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
+#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
+#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
+#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
+#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
+#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
+#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
+#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
+#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
+#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
+#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
+#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
+#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
+#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
+#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
+#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
+#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
+#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
+#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
+#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
+#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
+#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
+#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
+#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
+#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
+#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
+#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
+#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
+#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
+#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
+#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
+#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
+#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
+#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
+#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
+#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
+#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
+#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
+#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
+#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
+#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
+#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
+#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
+#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
+#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
+#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Register: MWU_PERREGION_SUBSTATRA */
+/* Description: Description cluster[0]:  Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */
+
+/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
+#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
+#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
+#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
+#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
+#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
+#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
+#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
+#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
+#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
+#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
+#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
+#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
+#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
+#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
+#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
+#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
+#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
+#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
+#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
+#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
+#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
+#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
+#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
+#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
+#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
+#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
+#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
+#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
+#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
+#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
+#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
+#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
+#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
+#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
+#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
+#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
+#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
+#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
+#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
+#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
+#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
+#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
+#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
+#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
+#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
+#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
+#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
+#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
+#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
+#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
+#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
+#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
+#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
+#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
+#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
+#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
+#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
+#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
+#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
+#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
+#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
+#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
+#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
+#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Register: MWU_REGIONEN */
+/* Description: Enable/disable regions watch */
+
+/* Bit 27 : Enable/disable read access watch in PREGION[1] */
+#define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
+#define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
+#define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
+#define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 26 : Enable/disable write access watch in PREGION[1] */
+#define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
+#define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
+#define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
+#define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 25 : Enable/disable read access watch in PREGION[0] */
+#define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
+#define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
+#define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
+#define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 24 : Enable/disable write access watch in PREGION[0] */
+#define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
+#define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
+#define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
+#define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 7 : Enable/disable read access watch in region[3] */
+#define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
+#define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
+#define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 6 : Enable/disable write access watch in region[3] */
+#define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
+#define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
+#define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 5 : Enable/disable read access watch in region[2] */
+#define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
+#define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
+#define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 4 : Enable/disable write access watch in region[2] */
+#define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
+#define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
+#define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 3 : Enable/disable read access watch in region[1] */
+#define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
+#define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
+#define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 2 : Enable/disable write access watch in region[1] */
+#define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
+#define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
+#define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 1 : Enable/disable read access watch in region[0] */
+#define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
+#define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
+#define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 0 : Enable/disable write access watch in region[0] */
+#define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
+#define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
+#define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Register: MWU_REGIONENSET */
+/* Description: Enable regions watch */
+
+/* Bit 27 : Enable read access watch in PREGION[1] */
+#define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
+#define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
+#define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 26 : Enable write access watch in PREGION[1] */
+#define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
+#define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
+#define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 25 : Enable read access watch in PREGION[0] */
+#define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
+#define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
+#define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 24 : Enable write access watch in PREGION[0] */
+#define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
+#define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
+#define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 7 : Enable read access watch in region[3] */
+#define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
+#define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
+#define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 6 : Enable write access watch in region[3] */
+#define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
+#define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
+#define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 5 : Enable read access watch in region[2] */
+#define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
+#define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
+#define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 4 : Enable write access watch in region[2] */
+#define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
+#define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
+#define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 3 : Enable read access watch in region[1] */
+#define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
+#define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
+#define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 2 : Enable write access watch in region[1] */
+#define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
+#define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
+#define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 1 : Enable read access watch in region[0] */
+#define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
+#define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
+#define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 0 : Enable write access watch in region[0] */
+#define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
+#define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
+#define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Register: MWU_REGIONENCLR */
+/* Description: Disable regions watch */
+
+/* Bit 27 : Disable read access watch in PREGION[1] */
+#define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
+#define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
+#define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
+
+/* Bit 26 : Disable write access watch in PREGION[1] */
+#define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
+#define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
+#define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
+
+/* Bit 25 : Disable read access watch in PREGION[0] */
+#define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
+#define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
+#define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
+
+/* Bit 24 : Disable write access watch in PREGION[0] */
+#define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
+#define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
+#define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
+
+/* Bit 7 : Disable read access watch in region[3] */
+#define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
+#define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
+#define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 6 : Disable write access watch in region[3] */
+#define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
+#define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
+#define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Bit 5 : Disable read access watch in region[2] */
+#define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
+#define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
+#define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 4 : Disable write access watch in region[2] */
+#define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
+#define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
+#define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Bit 3 : Disable read access watch in region[1] */
+#define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
+#define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
+#define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 2 : Disable write access watch in region[1] */
+#define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
+#define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
+#define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Bit 1 : Disable read access watch in region[0] */
+#define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
+#define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
+#define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 0 : Disable write access watch in region[0] */
+#define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
+#define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
+#define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Register: MWU_REGION_START */
+/* Description: Description cluster[0]:  Start address for region 0 */
+
+/* Bits 31..0 : Start address for region */
+#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
+#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
+
+/* Register: MWU_REGION_END */
+/* Description: Description cluster[0]:  End address of region 0 */
+
+/* Bits 31..0 : End address of region. */
+#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
+#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
+
+/* Register: MWU_PREGION_START */
+/* Description: Description cluster[0]:  Reserved for future use */
+
+/* Bits 31..0 : Reserved for future use */
+#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
+#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
+
+/* Register: MWU_PREGION_END */
+/* Description: Description cluster[0]:  Reserved for future use */
+
+/* Bits 31..0 : Reserved for future use */
+#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
+#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
+
+/* Register: MWU_PREGION_SUBS */
+/* Description: Description cluster[0]:  Subregions of region 0 */
+
+/* Bit 31 : Include or exclude subregion 31 in region */
+#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
+#define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
+#define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
+
+/* Bit 30 : Include or exclude subregion 30 in region */
+#define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
+#define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
+#define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
+
+/* Bit 29 : Include or exclude subregion 29 in region */
+#define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
+#define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
+#define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
+
+/* Bit 28 : Include or exclude subregion 28 in region */
+#define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
+#define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
+#define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
+
+/* Bit 27 : Include or exclude subregion 27 in region */
+#define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
+#define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
+#define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
+
+/* Bit 26 : Include or exclude subregion 26 in region */
+#define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
+#define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
+#define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
+
+/* Bit 25 : Include or exclude subregion 25 in region */
+#define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
+#define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
+#define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
+
+/* Bit 24 : Include or exclude subregion 24 in region */
+#define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
+#define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
+#define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
+
+/* Bit 23 : Include or exclude subregion 23 in region */
+#define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
+#define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
+#define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
+
+/* Bit 22 : Include or exclude subregion 22 in region */
+#define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
+#define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
+#define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
+
+/* Bit 21 : Include or exclude subregion 21 in region */
+#define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
+#define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
+#define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
+
+/* Bit 20 : Include or exclude subregion 20 in region */
+#define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
+#define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
+#define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
+
+/* Bit 19 : Include or exclude subregion 19 in region */
+#define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
+#define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
+#define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
+
+/* Bit 18 : Include or exclude subregion 18 in region */
+#define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
+#define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
+#define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
+
+/* Bit 17 : Include or exclude subregion 17 in region */
+#define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
+#define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
+#define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
+
+/* Bit 16 : Include or exclude subregion 16 in region */
+#define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
+#define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
+#define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
+
+/* Bit 15 : Include or exclude subregion 15 in region */
+#define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
+#define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
+#define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
+
+/* Bit 14 : Include or exclude subregion 14 in region */
+#define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
+#define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
+#define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
+
+/* Bit 13 : Include or exclude subregion 13 in region */
+#define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
+#define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
+#define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
+
+/* Bit 12 : Include or exclude subregion 12 in region */
+#define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
+#define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
+#define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
+
+/* Bit 11 : Include or exclude subregion 11 in region */
+#define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
+#define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
+#define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
+
+/* Bit 10 : Include or exclude subregion 10 in region */
+#define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
+#define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
+#define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
+
+/* Bit 9 : Include or exclude subregion 9 in region */
+#define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
+#define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
+#define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
+
+/* Bit 8 : Include or exclude subregion 8 in region */
+#define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
+#define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
+#define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
+
+/* Bit 7 : Include or exclude subregion 7 in region */
+#define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
+#define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
+#define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
+
+/* Bit 6 : Include or exclude subregion 6 in region */
+#define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
+#define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
+#define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
+
+/* Bit 5 : Include or exclude subregion 5 in region */
+#define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
+#define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
+#define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
+
+/* Bit 4 : Include or exclude subregion 4 in region */
+#define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
+#define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
+#define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
+
+/* Bit 3 : Include or exclude subregion 3 in region */
+#define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
+#define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
+#define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
+
+/* Bit 2 : Include or exclude subregion 2 in region */
+#define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
+#define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
+#define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
+
+/* Bit 1 : Include or exclude subregion 1 in region */
+#define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
+#define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
+#define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
+
+/* Bit 0 : Include or exclude subregion 0 in region */
+#define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
+#define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
+#define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
+
+
+/* Peripheral: NFCT */
+/* Description: NFC-A compatible radio */
+
+/* Register: NFCT_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 5 : Shortcut between TXFRAMEEND event and ENABLERXDATA task */
+#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL) /*!< Position of TXFRAMEEND_ENABLERXDATA field. */
+#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos) /*!< Bit mask of TXFRAMEEND_ENABLERXDATA field. */
+#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0UL) /*!< Disable shortcut */
+#define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: NFCT_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 20 : Enable or disable interrupt for STARTED event */
+#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
+#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for SELECTED event */
+#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
+#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for COLLISION event */
+#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
+#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
+#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for ENDTX event */
+#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
+#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for ENDRX event */
+#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
+#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for RXERROR event */
+#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
+#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
+#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for ERROR event */
+#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
+#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */
+#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
+#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
+#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */
+#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
+#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
+#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */
+#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
+#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
+#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */
+#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
+#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
+#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for FIELDLOST event */
+#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
+#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
+#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
+#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
+#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
+#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for READY event */
+#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
+#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
+#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
+
+/* Register: NFCT_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 20 : Write '1' to Enable interrupt for STARTED event */
+#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
+#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for SELECTED event */
+#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
+#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for COLLISION event */
+#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
+#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
+#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for ENDTX event */
+#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
+#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to Enable interrupt for ENDRX event */
+#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
+#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for RXERROR event */
+#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
+#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
+#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for ERROR event */
+#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
+#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */
+#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
+#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
+#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */
+#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
+#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
+#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */
+#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
+#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
+#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */
+#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
+#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
+#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */
+#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
+#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
+#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */
+#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
+#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
+#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: NFCT_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 20 : Write '1' to Disable interrupt for STARTED event */
+#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
+#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for SELECTED event */
+#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
+#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for COLLISION event */
+#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
+#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
+#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for ENDTX event */
+#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
+#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to Disable interrupt for ENDRX event */
+#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
+#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for RXERROR event */
+#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
+#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
+#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for ERROR event */
+#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
+#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */
+#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
+#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
+#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */
+#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
+#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
+#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */
+#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
+#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
+#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */
+#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
+#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
+#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */
+#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
+#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
+#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */
+#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
+#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
+#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: NFCT_ERRORSTATUS */
+/* Description: NFC Error Status register */
+
+/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
+#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
+#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
+
+/* Register: NFCT_FRAMESTATUS_RX */
+/* Description: Result of last incoming frame */
+
+/* Bit 3 : Overrun detected */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
+
+/* Bit 2 : Parity status of received frame */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
+
+/* Bit 0 : No valid end of frame (EoF) detected */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
+
+/* Register: NFCT_NFCTAGSTATE */
+/* Description: NfcTag state register */
+
+/* Bits 2..0 : NfcTag state */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos (0UL) /*!< Position of NFCTAGSTATE field. */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk (0x7UL << NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos) /*!< Bit mask of NFCTAGSTATE field. */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Disabled (0UL) /*!< Disabled or sense */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_RampUp (2UL) /*!< RampUp */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Idle (3UL) /*!< Idle */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Receive (4UL) /*!< Receive */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_FrameDelay (5UL) /*!< FrameDelay */
+#define NFCT_NFCTAGSTATE_NFCTAGSTATE_Transmit (6UL) /*!< Transmit */
+
+/* Register: NFCT_FIELDPRESENT */
+/* Description: Indicates the presence or not of a valid field */
+
+/* Bit 1 : Indicates if the low level has locked to the field */
+#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
+#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
+#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
+#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
+
+/* Bit 0 : Indicates if a valid field is present. Available only in the activated state. */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
+
+/* Register: NFCT_FRAMEDELAYMIN */
+/* Description: Minimum frame delay */
+
+/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
+#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
+#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
+
+/* Register: NFCT_FRAMEDELAYMAX */
+/* Description: Maximum frame delay */
+
+/* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */
+#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
+#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
+
+/* Register: NFCT_FRAMEDELAYMODE */
+/* Description: Configuration register for the Frame Delay Timer */
+
+/* Bits 1..0 : Configuration register for the Frame Delay Timer */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
+
+/* Register: NFCT_PACKETPTR */
+/* Description: Packet pointer for TXD and RXD data storage in Data RAM */
+
+/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. */
+#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: NFCT_MAXLEN */
+/* Description: Size of the RAM buffer allocated to TXD and RXD data storage each */
+
+/* Bits 8..0 : Size of the RAM buffer allocated to TXD and RXD data storage each */
+#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
+#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
+
+/* Register: NFCT_TXD_FRAMECONFIG */
+/* Description: Configuration of outgoing frames */
+
+/* Bit 4 : CRC mode for outgoing frames */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
+
+/* Bit 2 : Adding SoF or not in TX frames */
+#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
+#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
+#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< SoF symbol not added */
+#define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< SoF symbol added */
+
+/* Bit 1 : Discarding unused bits at start or end of a frame */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits are discarded at end of frame (EoF) */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits are discarded at start of frame (SoF) */
+
+/* Bit 0 : Indicates if parity is added to the frame */
+#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
+#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added to TX frames */
+#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added to TX frames */
+
+/* Register: NFCT_TXD_AMOUNT */
+/* Description: Size of outgoing frame */
+
+/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
+#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
+#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
+
+/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
+#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
+#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
+
+/* Register: NFCT_RXD_FRAMECONFIG */
+/* Description: Configuration of incoming frames */
+
+/* Bit 4 : CRC mode for incoming frames */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
+
+/* Bit 2 : SoF expected or not in RX frames */
+#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
+#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
+#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< SoF symbol is not expected in RX frames */
+#define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< SoF symbol is expected in RX frames */
+
+/* Bit 0 : Indicates if parity expected in RX frame */
+#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
+#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
+#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
+
+/* Register: NFCT_RXD_AMOUNT */
+/* Description: Size of last incoming frame */
+
+/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
+#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
+#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
+
+/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
+#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
+#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
+
+/* Register: NFCT_NFCID1_LAST */
+/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
+
+/* Bits 31..24 : NFCID1 byte W */
+#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
+#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
+
+/* Bits 23..16 : NFCID1 byte X */
+#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
+#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
+
+/* Bits 15..8 : NFCID1 byte Y */
+#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
+#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
+
+/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
+#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
+#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
+
+/* Register: NFCT_NFCID1_2ND_LAST */
+/* Description: Second last NFCID1 part (7 or 10 bytes ID) */
+
+/* Bits 23..16 : NFCID1 byte T */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
+
+/* Bits 15..8 : NFCID1 byte U */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
+
+/* Bits 7..0 : NFCID1 byte V */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
+
+/* Register: NFCT_NFCID1_3RD_LAST */
+/* Description: Third last NFCID1 part (10 bytes ID) */
+
+/* Bits 23..16 : NFCID1 byte Q */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
+
+/* Bits 15..8 : NFCID1 byte R */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
+
+/* Bits 7..0 : NFCID1 byte S */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
+
+/* Register: NFCT_AUTOCOLRESCONFIG */
+/* Description: Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled. */
+
+/* Bit 0 : Enables/disables auto collision resolution */
+#define NFCT_AUTOCOLRESCONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define NFCT_AUTOCOLRESCONFIG_MODE_Msk (0x1UL << NFCT_AUTOCOLRESCONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define NFCT_AUTOCOLRESCONFIG_MODE_Enabled (0UL) /*!< Auto collision resolution enabled */
+#define NFCT_AUTOCOLRESCONFIG_MODE_Disabled (1UL) /*!< Auto collision resolution disabled */
+
+/* Register: NFCT_SENSRES */
+/* Description: NFC-A SENS_RES auto-response settings */
+
+/* Bits 15..12 : Reserved for future use. Shall be 0. */
+#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
+#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
+
+/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
+#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
+#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
+
+/* Bits 7..6 : NFCID1 size. This value is used by the auto collision resolution engine. */
+#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
+#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
+
+/* Bit 5 : Reserved for future use. Shall be 0. */
+#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
+#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
+
+/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the <i>NFC Forum, NFC Digital Protocol Technical Specification</i> */
+#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
+#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
+
+/* Register: NFCT_SELRES */
+/* Description: NFC-A SEL_RES auto-response settings */
+
+/* Bit 7 : Reserved for future use. Shall be 0. */
+#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
+#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
+
+/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
+#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
+#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
+
+/* Bits 4..3 : Reserved for future use. Shall be 0. */
+#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
+#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
+
+/* Bit 2 : Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) */
+#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
+#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
+
+/* Bits 1..0 : Reserved for future use. Shall be 0. */
+#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
+#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
+
+
+/* Peripheral: NVMC */
+/* Description: Non Volatile Memory Controller */
+
+/* Register: NVMC_READY */
+/* Description: Ready flag */
+
+/* Bit 0 : NVMC is ready or busy */
+#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
+#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
+#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
+#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
+
+/* Register: NVMC_CONFIG */
+/* Description: Configuration register */
+
+/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
+#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
+#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
+#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
+#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
+#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
+
+/* Register: NVMC_ERASEPAGE */
+/* Description: Register for erasing a page in Code area */
+
+/* Bits 31..0 : Register for starting erase of a page in Code area */
+#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
+#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
+
+/* Register: NVMC_ERASEPCR1 */
+/* Description: Deprecated register -  Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
+
+/* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
+#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
+#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
+
+/* Register: NVMC_ERASEALL */
+/* Description: Register for erasing all non-volatile user memory */
+
+/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */
+#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
+#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
+
+/* Register: NVMC_ERASEPCR0 */
+/* Description: Deprecated register -  Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
+
+/* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */
+#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
+#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
+
+/* Register: NVMC_ERASEUICR */
+/* Description: Register for erasing User Information Configuration Registers */
+
+/* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. */
+#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
+#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
+
+/* Register: NVMC_ICACHECNF */
+/* Description: I-Code cache configuration register. */
+
+/* Bit 8 : Cache profiling enable */
+#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
+#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
+#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
+#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
+
+/* Bit 0 : Cache enable */
+#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
+#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
+#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
+#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
+
+/* Register: NVMC_IHIT */
+/* Description: I-Code cache hit counter. */
+
+/* Bits 31..0 : Number of cache hits */
+#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
+#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
+
+/* Register: NVMC_IMISS */
+/* Description: I-Code cache miss counter. */
+
+/* Bits 31..0 : Number of cache misses */
+#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
+#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
+
+
+/* Peripheral: GPIO */
+/* Description: GPIO Port 1 */
+
+/* Register: GPIO_OUT */
+/* Description: Write GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
+
+/* Register: GPIO_OUTSET */
+/* Description: Set individual bits in GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Register: GPIO_OUTCLR */
+/* Description: Clear individual bits in GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Register: GPIO_IN */
+/* Description: Read GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
+
+/* Register: GPIO_DIR */
+/* Description: Direction of GPIO pins */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
+
+/* Register: GPIO_DIRSET */
+/* Description: DIR set register */
+
+/* Bit 31 : Set as output pin 31 */
+#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 30 : Set as output pin 30 */
+#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 29 : Set as output pin 29 */
+#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 28 : Set as output pin 28 */
+#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 27 : Set as output pin 27 */
+#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 26 : Set as output pin 26 */
+#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 25 : Set as output pin 25 */
+#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 24 : Set as output pin 24 */
+#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 23 : Set as output pin 23 */
+#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 22 : Set as output pin 22 */
+#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 21 : Set as output pin 21 */
+#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 20 : Set as output pin 20 */
+#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 19 : Set as output pin 19 */
+#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 18 : Set as output pin 18 */
+#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 17 : Set as output pin 17 */
+#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 16 : Set as output pin 16 */
+#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 15 : Set as output pin 15 */
+#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 14 : Set as output pin 14 */
+#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 13 : Set as output pin 13 */
+#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 12 : Set as output pin 12 */
+#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 11 : Set as output pin 11 */
+#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 10 : Set as output pin 10 */
+#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 9 : Set as output pin 9 */
+#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 8 : Set as output pin 8 */
+#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 7 : Set as output pin 7 */
+#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 6 : Set as output pin 6 */
+#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 5 : Set as output pin 5 */
+#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 4 : Set as output pin 4 */
+#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 3 : Set as output pin 3 */
+#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 2 : Set as output pin 2 */
+#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 1 : Set as output pin 1 */
+#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 0 : Set as output pin 0 */
+#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Register: GPIO_DIRCLR */
+/* Description: DIR clear register */
+
+/* Bit 31 : Set as input pin 31 */
+#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 30 : Set as input pin 30 */
+#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 29 : Set as input pin 29 */
+#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 28 : Set as input pin 28 */
+#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 27 : Set as input pin 27 */
+#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 26 : Set as input pin 26 */
+#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 25 : Set as input pin 25 */
+#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 24 : Set as input pin 24 */
+#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 23 : Set as input pin 23 */
+#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 22 : Set as input pin 22 */
+#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 21 : Set as input pin 21 */
+#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 20 : Set as input pin 20 */
+#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 19 : Set as input pin 19 */
+#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 18 : Set as input pin 18 */
+#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 17 : Set as input pin 17 */
+#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 16 : Set as input pin 16 */
+#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 15 : Set as input pin 15 */
+#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 14 : Set as input pin 14 */
+#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 13 : Set as input pin 13 */
+#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 12 : Set as input pin 12 */
+#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 11 : Set as input pin 11 */
+#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 10 : Set as input pin 10 */
+#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 9 : Set as input pin 9 */
+#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 8 : Set as input pin 8 */
+#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 7 : Set as input pin 7 */
+#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 6 : Set as input pin 6 */
+#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 5 : Set as input pin 5 */
+#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 4 : Set as input pin 4 */
+#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 3 : Set as input pin 3 */
+#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 2 : Set as input pin 2 */
+#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 1 : Set as input pin 1 */
+#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 0 : Set as input pin 0 */
+#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Register: GPIO_LATCH */
+/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
+
+/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
+
+/* Register: GPIO_DETECTMODE */
+/* Description: Select between default DETECT signal behaviour and LDETECT mode */
+
+/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
+#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
+#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
+#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
+#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
+
+/* Register: GPIO_PIN_CNF */
+/* Description: Description collection[0]:  Configuration of GPIO pins */
+
+/* Bits 17..16 : Pin sensing mechanism */
+#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
+#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
+#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
+
+/* Bits 10..8 : Drive configuration */
+#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
+#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
+#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
+#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
+#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
+#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
+#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
+#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
+
+/* Bits 3..2 : Pull configuration */
+#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
+#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
+#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
+#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
+#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
+
+/* Bit 1 : Connect or disconnect input buffer */
+#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
+#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
+
+/* Bit 0 : Pin direction. Same physical register as DIR register */
+#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
+#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
+#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
+#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
+
+
+/* Peripheral: PDM */
+/* Description: Pulse Density Modulation (Digital Microphone) Interface */
+
+/* Register: PDM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 2 : Enable or disable interrupt for END event */
+#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for STARTED event */
+#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Register: PDM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for END event */
+#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for STARTED event */
+#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Register: PDM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for END event */
+#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for STARTED event */
+#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Register: PDM_ENABLE */
+/* Description: PDM module enable register */
+
+/* Bit 0 : Enable or disable PDM module */
+#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: PDM_PDMCLKCTRL */
+/* Description: PDM clock generator control */
+
+/* Bits 31..0 : PDM_CLK frequency */
+#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
+#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
+#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
+#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. */
+#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
+#define PDM_PDMCLKCTRL_FREQ_1231K (0x09800000UL) /*!< PDM_CLK = 32 MHz / 26 = 1.231 MHz */
+#define PDM_PDMCLKCTRL_FREQ_1280K (0x0A000000UL) /*!< PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. */
+#define PDM_PDMCLKCTRL_FREQ_1333K (0x0A800000UL) /*!< PDM_CLK = 32 MHz / 24 = 1.333 MHz */
+
+/* Register: PDM_MODE */
+/* Description: Defines the routing of the connected PDM microphones' signals */
+
+/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
+#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
+#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
+#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
+#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
+
+/* Bit 0 : Mono or stereo operation */
+#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
+#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
+#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
+#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
+
+/* Register: PDM_GAINL */
+/* Description: Left output gain adjustment */
+
+/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust */
+#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
+#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
+#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
+#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
+#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
+
+/* Register: PDM_GAINR */
+/* Description: Right output gain adjustment */
+
+/* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
+#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
+#define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
+#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
+#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
+#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
+
+/* Register: PDM_RATIO */
+/* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */
+
+/* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */
+#define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
+#define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
+#define PDM_RATIO_RATIO_Ratio64 (0UL) /*!< Ratio of 64 */
+#define PDM_RATIO_RATIO_Ratio80 (1UL) /*!< Ratio of 80 */
+
+/* Register: PDM_PSEL_CLK */
+/* Description: Pin number configuration for PDM CLK signal */
+
+/* Bit 31 : Connection */
+#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
+#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define PDM_PSEL_CLK_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define PDM_PSEL_CLK_PORT_Msk (0x3UL << PDM_PSEL_CLK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: PDM_PSEL_DIN */
+/* Description: Pin number configuration for PDM DIN signal */
+
+/* Bit 31 : Connection */
+#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
+#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define PDM_PSEL_DIN_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define PDM_PSEL_DIN_PORT_Msk (0x3UL << PDM_PSEL_DIN_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: PDM_SAMPLE_PTR */
+/* Description: RAM address pointer to write samples to with EasyDMA */
+
+/* Bits 31..0 : Address to write PDM samples to over DMA */
+#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
+#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
+
+/* Register: PDM_SAMPLE_MAXCNT */
+/* Description: Number of samples to allocate memory for in EasyDMA mode */
+
+/* Bits 14..0 : Length of DMA RAM allocation in number of samples */
+#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
+#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
+
+
+/* Peripheral: POWER */
+/* Description: Power control */
+
+/* Register: POWER_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 9 : Write '1' to Enable interrupt for USBPWRRDY event */
+#define POWER_INTENSET_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */
+#define POWER_INTENSET_USBPWRRDY_Msk (0x1UL << POWER_INTENSET_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
+#define POWER_INTENSET_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_USBPWRRDY_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for USBREMOVED event */
+#define POWER_INTENSET_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */
+#define POWER_INTENSET_USBREMOVED_Msk (0x1UL << POWER_INTENSET_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
+#define POWER_INTENSET_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_USBREMOVED_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for USBDETECTED event */
+#define POWER_INTENSET_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */
+#define POWER_INTENSET_USBDETECTED_Msk (0x1UL << POWER_INTENSET_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
+#define POWER_INTENSET_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_USBDETECTED_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */
+#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
+#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
+#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */
+#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
+#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
+#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for POFWARN event */
+#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
+
+/* Register: POWER_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 9 : Write '1' to Disable interrupt for USBPWRRDY event */
+#define POWER_INTENCLR_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */
+#define POWER_INTENCLR_USBPWRRDY_Msk (0x1UL << POWER_INTENCLR_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */
+#define POWER_INTENCLR_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_USBPWRRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for USBREMOVED event */
+#define POWER_INTENCLR_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */
+#define POWER_INTENCLR_USBREMOVED_Msk (0x1UL << POWER_INTENCLR_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */
+#define POWER_INTENCLR_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_USBREMOVED_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for USBDETECTED event */
+#define POWER_INTENCLR_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */
+#define POWER_INTENCLR_USBDETECTED_Msk (0x1UL << POWER_INTENCLR_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */
+#define POWER_INTENCLR_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_USBDETECTED_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */
+#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
+#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
+#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */
+#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
+#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
+#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for POFWARN event */
+#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
+
+/* Register: POWER_RESETREAS */
+/* Description: Reset reason */
+
+/* Bit 20 : Reset due to wake up from System OFF mode by Vbus rising into valid range */
+#define POWER_RESETREAS_VBUS_Pos (20UL) /*!< Position of VBUS field. */
+#define POWER_RESETREAS_VBUS_Msk (0x1UL << POWER_RESETREAS_VBUS_Pos) /*!< Bit mask of VBUS field. */
+#define POWER_RESETREAS_VBUS_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_VBUS_Detected (1UL) /*!< Detected */
+
+/* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
+#define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
+#define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
+#define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
+
+/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
+#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
+#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
+#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
+
+/* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
+#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
+
+/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
+#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
+#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
+#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
+
+/* Bit 3 : Reset from CPU lock-up detected */
+#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
+
+/* Bit 2 : Reset from soft reset detected */
+#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
+#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
+#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
+
+/* Bit 1 : Reset from watchdog detected */
+#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
+#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
+#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
+
+/* Bit 0 : Reset from pin-reset detected */
+#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
+
+/* Register: POWER_RAMSTATUS */
+/* Description: Deprecated register -  RAM status register */
+
+/* Bit 3 : RAM block 3 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
+
+/* Bit 2 : RAM block 2 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
+
+/* Bit 1 : RAM block 1 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
+
+/* Bit 0 : RAM block 0 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
+
+/* Register: POWER_USBREGSTATUS */
+/* Description: USB supply status */
+
+/* Bit 1 : USB supply output settling time elapsed */
+#define POWER_USBREGSTATUS_OUTPUTRDY_Pos (1UL) /*!< Position of OUTPUTRDY field. */
+#define POWER_USBREGSTATUS_OUTPUTRDY_Msk (0x1UL << POWER_USBREGSTATUS_OUTPUTRDY_Pos) /*!< Bit mask of OUTPUTRDY field. */
+#define POWER_USBREGSTATUS_OUTPUTRDY_NotReady (0UL) /*!< USBREG output settling time not elapsed */
+#define POWER_USBREGSTATUS_OUTPUTRDY_Ready (1UL) /*!< USBREG output settling time elapsed (same information as USBPWRRDY event) */
+
+/* Bit 0 : VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) */
+#define POWER_USBREGSTATUS_VBUSDETECT_Pos (0UL) /*!< Position of VBUSDETECT field. */
+#define POWER_USBREGSTATUS_VBUSDETECT_Msk (0x1UL << POWER_USBREGSTATUS_VBUSDETECT_Pos) /*!< Bit mask of VBUSDETECT field. */
+#define POWER_USBREGSTATUS_VBUSDETECT_NoVbus (0UL) /*!< VBUS voltage below valid threshold */
+#define POWER_USBREGSTATUS_VBUSDETECT_VbusPresent (1UL) /*!< VBUS voltage above valid threshold */
+
+/* Register: POWER_SYSTEMOFF */
+/* Description: System OFF register */
+
+/* Bit 0 : Enable System OFF mode */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
+
+/* Register: POWER_POFCON */
+/* Description: Power failure comparator configuration */
+
+/* Bits 11..8 : Power failure comparator threshold setting for voltage supply on VDDH */
+#define POWER_POFCON_THRESHOLDVDDH_Pos (8UL) /*!< Position of THRESHOLDVDDH field. */
+#define POWER_POFCON_THRESHOLDVDDH_Msk (0xFUL << POWER_POFCON_THRESHOLDVDDH_Pos) /*!< Bit mask of THRESHOLDVDDH field. */
+#define POWER_POFCON_THRESHOLDVDDH_V27 (0UL) /*!< Set threshold to 2.7 V */
+#define POWER_POFCON_THRESHOLDVDDH_V28 (1UL) /*!< Set threshold to 2.8 V */
+#define POWER_POFCON_THRESHOLDVDDH_V29 (2UL) /*!< Set threshold to 2.9 V */
+#define POWER_POFCON_THRESHOLDVDDH_V30 (3UL) /*!< Set threshold to 3.0 V */
+#define POWER_POFCON_THRESHOLDVDDH_V31 (4UL) /*!< Set threshold to 3.1 V */
+#define POWER_POFCON_THRESHOLDVDDH_V32 (5UL) /*!< Set threshold to 3.2 V */
+#define POWER_POFCON_THRESHOLDVDDH_V33 (6UL) /*!< Set threshold to 3.3 V */
+#define POWER_POFCON_THRESHOLDVDDH_V34 (7UL) /*!< Set threshold to 3.4 V */
+#define POWER_POFCON_THRESHOLDVDDH_V35 (8UL) /*!< Set threshold to 3.5 V */
+#define POWER_POFCON_THRESHOLDVDDH_V36 (9UL) /*!< Set threshold to 3.6 V */
+#define POWER_POFCON_THRESHOLDVDDH_V37 (10UL) /*!< Set threshold to 3.7 V */
+#define POWER_POFCON_THRESHOLDVDDH_V38 (11UL) /*!< Set threshold to 3.8 V */
+#define POWER_POFCON_THRESHOLDVDDH_V39 (12UL) /*!< Set threshold to 3.9 V */
+#define POWER_POFCON_THRESHOLDVDDH_V40 (13UL) /*!< Set threshold to 4.0 V */
+#define POWER_POFCON_THRESHOLDVDDH_V41 (14UL) /*!< Set threshold to 4.1 V */
+#define POWER_POFCON_THRESHOLDVDDH_V42 (15UL) /*!< Set threshold to 4.2 V */
+
+/* Bits 4..1 : Power failure comparator threshold setting */
+#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
+#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
+#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
+#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
+#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
+#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
+#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
+#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
+#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
+#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
+#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
+#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
+
+/* Bit 0 : Enable or disable power failure comparator */
+#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
+#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
+#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
+#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
+
+/* Register: POWER_GPREGRET */
+/* Description: General purpose retention register */
+
+/* Bits 7..0 : General purpose retention register */
+#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_GPREGRET2 */
+/* Description: General purpose retention register */
+
+/* Bits 7..0 : General purpose retention register */
+#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_DCDCEN */
+/* Description: Enable DC/DC converter for REG1 stage. */
+
+/* Bit 0 : Enable DC/DC converter for REG1 stage. */
+#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
+#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
+
+/* Register: POWER_DCDCEN0 */
+/* Description: Enable DC/DC converter for REG0 stage. */
+
+/* Bit 0 : Enable DC/DC converter for REG0 stage. */
+#define POWER_DCDCEN0_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
+#define POWER_DCDCEN0_DCDCEN_Msk (0x1UL << POWER_DCDCEN0_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
+#define POWER_DCDCEN0_DCDCEN_Disabled (0UL) /*!< Disable */
+#define POWER_DCDCEN0_DCDCEN_Enabled (1UL) /*!< Enable */
+
+/* Register: POWER_MAINREGSTATUS */
+/* Description: Main supply status */
+
+/* Bit 0 : Main supply status */
+#define POWER_MAINREGSTATUS_MAINREGSTATUS_Pos (0UL) /*!< Position of MAINREGSTATUS field. */
+#define POWER_MAINREGSTATUS_MAINREGSTATUS_Msk (0x1UL << POWER_MAINREGSTATUS_MAINREGSTATUS_Pos) /*!< Bit mask of MAINREGSTATUS field. */
+#define POWER_MAINREGSTATUS_MAINREGSTATUS_Normal (0UL) /*!< Normal voltage mode. Voltage supplied on VDD. */
+#define POWER_MAINREGSTATUS_MAINREGSTATUS_High (1UL) /*!< High voltage mode. Voltage supplied on VDDH. */
+
+/* Register: POWER_RAM_POWER */
+/* Description: Description cluster[0]:  RAM0 power control register */
+
+/* Bit 31 : Keep retention on RAM section S15 when RAM section is in OFF */
+#define POWER_RAM_POWER_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
+#define POWER_RAM_POWER_S15RETENTION_Msk (0x1UL << POWER_RAM_POWER_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
+#define POWER_RAM_POWER_S15RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S15RETENTION_On (1UL) /*!< On */
+
+/* Bit 30 : Keep retention on RAM section S14 when RAM section is in OFF */
+#define POWER_RAM_POWER_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
+#define POWER_RAM_POWER_S14RETENTION_Msk (0x1UL << POWER_RAM_POWER_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
+#define POWER_RAM_POWER_S14RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S14RETENTION_On (1UL) /*!< On */
+
+/* Bit 29 : Keep retention on RAM section S13 when RAM section is in OFF */
+#define POWER_RAM_POWER_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
+#define POWER_RAM_POWER_S13RETENTION_Msk (0x1UL << POWER_RAM_POWER_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
+#define POWER_RAM_POWER_S13RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S13RETENTION_On (1UL) /*!< On */
+
+/* Bit 28 : Keep retention on RAM section S12 when RAM section is in OFF */
+#define POWER_RAM_POWER_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
+#define POWER_RAM_POWER_S12RETENTION_Msk (0x1UL << POWER_RAM_POWER_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
+#define POWER_RAM_POWER_S12RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S12RETENTION_On (1UL) /*!< On */
+
+/* Bit 27 : Keep retention on RAM section S11 when RAM section is in OFF */
+#define POWER_RAM_POWER_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
+#define POWER_RAM_POWER_S11RETENTION_Msk (0x1UL << POWER_RAM_POWER_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
+#define POWER_RAM_POWER_S11RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S11RETENTION_On (1UL) /*!< On */
+
+/* Bit 26 : Keep retention on RAM section S10 when RAM section is in OFF */
+#define POWER_RAM_POWER_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
+#define POWER_RAM_POWER_S10RETENTION_Msk (0x1UL << POWER_RAM_POWER_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
+#define POWER_RAM_POWER_S10RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S10RETENTION_On (1UL) /*!< On */
+
+/* Bit 25 : Keep retention on RAM section S9 when RAM section is in OFF */
+#define POWER_RAM_POWER_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
+#define POWER_RAM_POWER_S9RETENTION_Msk (0x1UL << POWER_RAM_POWER_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
+#define POWER_RAM_POWER_S9RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S9RETENTION_On (1UL) /*!< On */
+
+/* Bit 24 : Keep retention on RAM section S8 when RAM section is in OFF */
+#define POWER_RAM_POWER_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
+#define POWER_RAM_POWER_S8RETENTION_Msk (0x1UL << POWER_RAM_POWER_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
+#define POWER_RAM_POWER_S8RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S8RETENTION_On (1UL) /*!< On */
+
+/* Bit 23 : Keep retention on RAM section S7 when RAM section is in OFF */
+#define POWER_RAM_POWER_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
+#define POWER_RAM_POWER_S7RETENTION_Msk (0x1UL << POWER_RAM_POWER_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
+#define POWER_RAM_POWER_S7RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S7RETENTION_On (1UL) /*!< On */
+
+/* Bit 22 : Keep retention on RAM section S6 when RAM section is in OFF */
+#define POWER_RAM_POWER_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
+#define POWER_RAM_POWER_S6RETENTION_Msk (0x1UL << POWER_RAM_POWER_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
+#define POWER_RAM_POWER_S6RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S6RETENTION_On (1UL) /*!< On */
+
+/* Bit 21 : Keep retention on RAM section S5 when RAM section is in OFF */
+#define POWER_RAM_POWER_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
+#define POWER_RAM_POWER_S5RETENTION_Msk (0x1UL << POWER_RAM_POWER_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
+#define POWER_RAM_POWER_S5RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S5RETENTION_On (1UL) /*!< On */
+
+/* Bit 20 : Keep retention on RAM section S4 when RAM section is in OFF */
+#define POWER_RAM_POWER_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
+#define POWER_RAM_POWER_S4RETENTION_Msk (0x1UL << POWER_RAM_POWER_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
+#define POWER_RAM_POWER_S4RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S4RETENTION_On (1UL) /*!< On */
+
+/* Bit 19 : Keep retention on RAM section S3 when RAM section is in OFF */
+#define POWER_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
+#define POWER_RAM_POWER_S3RETENTION_Msk (0x1UL << POWER_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
+#define POWER_RAM_POWER_S3RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S3RETENTION_On (1UL) /*!< On */
+
+/* Bit 18 : Keep retention on RAM section S2 when RAM section is in OFF */
+#define POWER_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
+#define POWER_RAM_POWER_S2RETENTION_Msk (0x1UL << POWER_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
+#define POWER_RAM_POWER_S2RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S2RETENTION_On (1UL) /*!< On */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */
+#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */
+#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
+
+/* Bit 15 : Keep RAM section S15 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
+#define POWER_RAM_POWER_S15POWER_Msk (0x1UL << POWER_RAM_POWER_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
+#define POWER_RAM_POWER_S15POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S15POWER_On (1UL) /*!< On */
+
+/* Bit 14 : Keep RAM section S14 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
+#define POWER_RAM_POWER_S14POWER_Msk (0x1UL << POWER_RAM_POWER_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
+#define POWER_RAM_POWER_S14POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S14POWER_On (1UL) /*!< On */
+
+/* Bit 13 : Keep RAM section S13 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
+#define POWER_RAM_POWER_S13POWER_Msk (0x1UL << POWER_RAM_POWER_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
+#define POWER_RAM_POWER_S13POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S13POWER_On (1UL) /*!< On */
+
+/* Bit 12 : Keep RAM section S12 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
+#define POWER_RAM_POWER_S12POWER_Msk (0x1UL << POWER_RAM_POWER_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
+#define POWER_RAM_POWER_S12POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S12POWER_On (1UL) /*!< On */
+
+/* Bit 11 : Keep RAM section S11 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
+#define POWER_RAM_POWER_S11POWER_Msk (0x1UL << POWER_RAM_POWER_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
+#define POWER_RAM_POWER_S11POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S11POWER_On (1UL) /*!< On */
+
+/* Bit 10 : Keep RAM section S10 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
+#define POWER_RAM_POWER_S10POWER_Msk (0x1UL << POWER_RAM_POWER_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
+#define POWER_RAM_POWER_S10POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S10POWER_On (1UL) /*!< On */
+
+/* Bit 9 : Keep RAM section S9 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
+#define POWER_RAM_POWER_S9POWER_Msk (0x1UL << POWER_RAM_POWER_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
+#define POWER_RAM_POWER_S9POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S9POWER_On (1UL) /*!< On */
+
+/* Bit 8 : Keep RAM section S8 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
+#define POWER_RAM_POWER_S8POWER_Msk (0x1UL << POWER_RAM_POWER_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
+#define POWER_RAM_POWER_S8POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S8POWER_On (1UL) /*!< On */
+
+/* Bit 7 : Keep RAM section S7 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
+#define POWER_RAM_POWER_S7POWER_Msk (0x1UL << POWER_RAM_POWER_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
+#define POWER_RAM_POWER_S7POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S7POWER_On (1UL) /*!< On */
+
+/* Bit 6 : Keep RAM section S6 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
+#define POWER_RAM_POWER_S6POWER_Msk (0x1UL << POWER_RAM_POWER_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
+#define POWER_RAM_POWER_S6POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S6POWER_On (1UL) /*!< On */
+
+/* Bit 5 : Keep RAM section S5 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
+#define POWER_RAM_POWER_S5POWER_Msk (0x1UL << POWER_RAM_POWER_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
+#define POWER_RAM_POWER_S5POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S5POWER_On (1UL) /*!< On */
+
+/* Bit 4 : Keep RAM section S4 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
+#define POWER_RAM_POWER_S4POWER_Msk (0x1UL << POWER_RAM_POWER_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
+#define POWER_RAM_POWER_S4POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S4POWER_On (1UL) /*!< On */
+
+/* Bit 3 : Keep RAM section S3 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
+#define POWER_RAM_POWER_S3POWER_Msk (0x1UL << POWER_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
+#define POWER_RAM_POWER_S3POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S3POWER_On (1UL) /*!< On */
+
+/* Bit 2 : Keep RAM section S2 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
+#define POWER_RAM_POWER_S2POWER_Msk (0x1UL << POWER_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
+#define POWER_RAM_POWER_S2POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S2POWER_On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
+
+/* Register: POWER_RAM_POWERSET */
+/* Description: Description cluster[0]:  RAM0 power control set register */
+
+/* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
+#define POWER_RAM_POWERSET_S15RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
+#define POWER_RAM_POWERSET_S15RETENTION_On (1UL) /*!< On */
+
+/* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
+#define POWER_RAM_POWERSET_S14RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
+#define POWER_RAM_POWERSET_S14RETENTION_On (1UL) /*!< On */
+
+/* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
+#define POWER_RAM_POWERSET_S13RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
+#define POWER_RAM_POWERSET_S13RETENTION_On (1UL) /*!< On */
+
+/* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
+#define POWER_RAM_POWERSET_S12RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
+#define POWER_RAM_POWERSET_S12RETENTION_On (1UL) /*!< On */
+
+/* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
+#define POWER_RAM_POWERSET_S11RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
+#define POWER_RAM_POWERSET_S11RETENTION_On (1UL) /*!< On */
+
+/* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
+#define POWER_RAM_POWERSET_S10RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
+#define POWER_RAM_POWERSET_S10RETENTION_On (1UL) /*!< On */
+
+/* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
+#define POWER_RAM_POWERSET_S9RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
+#define POWER_RAM_POWERSET_S9RETENTION_On (1UL) /*!< On */
+
+/* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
+#define POWER_RAM_POWERSET_S8RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
+#define POWER_RAM_POWERSET_S8RETENTION_On (1UL) /*!< On */
+
+/* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
+#define POWER_RAM_POWERSET_S7RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
+#define POWER_RAM_POWERSET_S7RETENTION_On (1UL) /*!< On */
+
+/* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
+#define POWER_RAM_POWERSET_S6RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
+#define POWER_RAM_POWERSET_S6RETENTION_On (1UL) /*!< On */
+
+/* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
+#define POWER_RAM_POWERSET_S5RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
+#define POWER_RAM_POWERSET_S5RETENTION_On (1UL) /*!< On */
+
+/* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
+#define POWER_RAM_POWERSET_S4RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
+#define POWER_RAM_POWERSET_S4RETENTION_On (1UL) /*!< On */
+
+/* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
+#define POWER_RAM_POWERSET_S3RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
+#define POWER_RAM_POWERSET_S3RETENTION_On (1UL) /*!< On */
+
+/* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
+#define POWER_RAM_POWERSET_S2RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
+#define POWER_RAM_POWERSET_S2RETENTION_On (1UL) /*!< On */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
+
+/* Bit 15 : Keep RAM section S15 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
+#define POWER_RAM_POWERSET_S15POWER_Msk (0x1UL << POWER_RAM_POWERSET_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
+#define POWER_RAM_POWERSET_S15POWER_On (1UL) /*!< On */
+
+/* Bit 14 : Keep RAM section S14 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
+#define POWER_RAM_POWERSET_S14POWER_Msk (0x1UL << POWER_RAM_POWERSET_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
+#define POWER_RAM_POWERSET_S14POWER_On (1UL) /*!< On */
+
+/* Bit 13 : Keep RAM section S13 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
+#define POWER_RAM_POWERSET_S13POWER_Msk (0x1UL << POWER_RAM_POWERSET_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
+#define POWER_RAM_POWERSET_S13POWER_On (1UL) /*!< On */
+
+/* Bit 12 : Keep RAM section S12 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
+#define POWER_RAM_POWERSET_S12POWER_Msk (0x1UL << POWER_RAM_POWERSET_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
+#define POWER_RAM_POWERSET_S12POWER_On (1UL) /*!< On */
+
+/* Bit 11 : Keep RAM section S11 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
+#define POWER_RAM_POWERSET_S11POWER_Msk (0x1UL << POWER_RAM_POWERSET_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
+#define POWER_RAM_POWERSET_S11POWER_On (1UL) /*!< On */
+
+/* Bit 10 : Keep RAM section S10 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
+#define POWER_RAM_POWERSET_S10POWER_Msk (0x1UL << POWER_RAM_POWERSET_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
+#define POWER_RAM_POWERSET_S10POWER_On (1UL) /*!< On */
+
+/* Bit 9 : Keep RAM section S9 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
+#define POWER_RAM_POWERSET_S9POWER_Msk (0x1UL << POWER_RAM_POWERSET_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
+#define POWER_RAM_POWERSET_S9POWER_On (1UL) /*!< On */
+
+/* Bit 8 : Keep RAM section S8 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
+#define POWER_RAM_POWERSET_S8POWER_Msk (0x1UL << POWER_RAM_POWERSET_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
+#define POWER_RAM_POWERSET_S8POWER_On (1UL) /*!< On */
+
+/* Bit 7 : Keep RAM section S7 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
+#define POWER_RAM_POWERSET_S7POWER_Msk (0x1UL << POWER_RAM_POWERSET_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
+#define POWER_RAM_POWERSET_S7POWER_On (1UL) /*!< On */
+
+/* Bit 6 : Keep RAM section S6 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
+#define POWER_RAM_POWERSET_S6POWER_Msk (0x1UL << POWER_RAM_POWERSET_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
+#define POWER_RAM_POWERSET_S6POWER_On (1UL) /*!< On */
+
+/* Bit 5 : Keep RAM section S5 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
+#define POWER_RAM_POWERSET_S5POWER_Msk (0x1UL << POWER_RAM_POWERSET_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
+#define POWER_RAM_POWERSET_S5POWER_On (1UL) /*!< On */
+
+/* Bit 4 : Keep RAM section S4 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
+#define POWER_RAM_POWERSET_S4POWER_Msk (0x1UL << POWER_RAM_POWERSET_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
+#define POWER_RAM_POWERSET_S4POWER_On (1UL) /*!< On */
+
+/* Bit 3 : Keep RAM section S3 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
+#define POWER_RAM_POWERSET_S3POWER_Msk (0x1UL << POWER_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
+#define POWER_RAM_POWERSET_S3POWER_On (1UL) /*!< On */
+
+/* Bit 2 : Keep RAM section S2 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
+#define POWER_RAM_POWERSET_S2POWER_Msk (0x1UL << POWER_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
+#define POWER_RAM_POWERSET_S2POWER_On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
+
+/* Register: POWER_RAM_POWERCLR */
+/* Description: Description cluster[0]:  RAM0 power control clear register */
+
+/* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */
+#define POWER_RAM_POWERCLR_S15RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */
+#define POWER_RAM_POWERCLR_S15RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 30 : Keep retention on RAM section S14 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */
+#define POWER_RAM_POWERCLR_S14RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */
+#define POWER_RAM_POWERCLR_S14RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 29 : Keep retention on RAM section S13 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */
+#define POWER_RAM_POWERCLR_S13RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */
+#define POWER_RAM_POWERCLR_S13RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 28 : Keep retention on RAM section S12 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */
+#define POWER_RAM_POWERCLR_S12RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */
+#define POWER_RAM_POWERCLR_S12RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 27 : Keep retention on RAM section S11 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */
+#define POWER_RAM_POWERCLR_S11RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */
+#define POWER_RAM_POWERCLR_S11RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 26 : Keep retention on RAM section S10 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */
+#define POWER_RAM_POWERCLR_S10RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */
+#define POWER_RAM_POWERCLR_S10RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 25 : Keep retention on RAM section S9 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */
+#define POWER_RAM_POWERCLR_S9RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */
+#define POWER_RAM_POWERCLR_S9RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 24 : Keep retention on RAM section S8 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */
+#define POWER_RAM_POWERCLR_S8RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */
+#define POWER_RAM_POWERCLR_S8RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 23 : Keep retention on RAM section S7 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */
+#define POWER_RAM_POWERCLR_S7RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */
+#define POWER_RAM_POWERCLR_S7RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 22 : Keep retention on RAM section S6 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */
+#define POWER_RAM_POWERCLR_S6RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */
+#define POWER_RAM_POWERCLR_S6RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 21 : Keep retention on RAM section S5 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */
+#define POWER_RAM_POWERCLR_S5RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */
+#define POWER_RAM_POWERCLR_S5RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 20 : Keep retention on RAM section S4 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */
+#define POWER_RAM_POWERCLR_S4RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */
+#define POWER_RAM_POWERCLR_S4RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 19 : Keep retention on RAM section S3 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */
+#define POWER_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */
+#define POWER_RAM_POWERCLR_S3RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 18 : Keep retention on RAM section S2 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */
+#define POWER_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */
+#define POWER_RAM_POWERCLR_S2RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 15 : Keep RAM section S15 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */
+#define POWER_RAM_POWERCLR_S15POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S15POWER_Pos) /*!< Bit mask of S15POWER field. */
+#define POWER_RAM_POWERCLR_S15POWER_Off (1UL) /*!< Off */
+
+/* Bit 14 : Keep RAM section S14 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */
+#define POWER_RAM_POWERCLR_S14POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S14POWER_Pos) /*!< Bit mask of S14POWER field. */
+#define POWER_RAM_POWERCLR_S14POWER_Off (1UL) /*!< Off */
+
+/* Bit 13 : Keep RAM section S13 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */
+#define POWER_RAM_POWERCLR_S13POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S13POWER_Pos) /*!< Bit mask of S13POWER field. */
+#define POWER_RAM_POWERCLR_S13POWER_Off (1UL) /*!< Off */
+
+/* Bit 12 : Keep RAM section S12 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */
+#define POWER_RAM_POWERCLR_S12POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S12POWER_Pos) /*!< Bit mask of S12POWER field. */
+#define POWER_RAM_POWERCLR_S12POWER_Off (1UL) /*!< Off */
+
+/* Bit 11 : Keep RAM section S11 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */
+#define POWER_RAM_POWERCLR_S11POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S11POWER_Pos) /*!< Bit mask of S11POWER field. */
+#define POWER_RAM_POWERCLR_S11POWER_Off (1UL) /*!< Off */
+
+/* Bit 10 : Keep RAM section S10 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */
+#define POWER_RAM_POWERCLR_S10POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S10POWER_Pos) /*!< Bit mask of S10POWER field. */
+#define POWER_RAM_POWERCLR_S10POWER_Off (1UL) /*!< Off */
+
+/* Bit 9 : Keep RAM section S9 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */
+#define POWER_RAM_POWERCLR_S9POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S9POWER_Pos) /*!< Bit mask of S9POWER field. */
+#define POWER_RAM_POWERCLR_S9POWER_Off (1UL) /*!< Off */
+
+/* Bit 8 : Keep RAM section S8 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */
+#define POWER_RAM_POWERCLR_S8POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S8POWER_Pos) /*!< Bit mask of S8POWER field. */
+#define POWER_RAM_POWERCLR_S8POWER_Off (1UL) /*!< Off */
+
+/* Bit 7 : Keep RAM section S7 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */
+#define POWER_RAM_POWERCLR_S7POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S7POWER_Pos) /*!< Bit mask of S7POWER field. */
+#define POWER_RAM_POWERCLR_S7POWER_Off (1UL) /*!< Off */
+
+/* Bit 6 : Keep RAM section S6 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */
+#define POWER_RAM_POWERCLR_S6POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S6POWER_Pos) /*!< Bit mask of S6POWER field. */
+#define POWER_RAM_POWERCLR_S6POWER_Off (1UL) /*!< Off */
+
+/* Bit 5 : Keep RAM section S5 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */
+#define POWER_RAM_POWERCLR_S5POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S5POWER_Pos) /*!< Bit mask of S5POWER field. */
+#define POWER_RAM_POWERCLR_S5POWER_Off (1UL) /*!< Off */
+
+/* Bit 4 : Keep RAM section S4 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */
+#define POWER_RAM_POWERCLR_S4POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S4POWER_Pos) /*!< Bit mask of S4POWER field. */
+#define POWER_RAM_POWERCLR_S4POWER_Off (1UL) /*!< Off */
+
+/* Bit 3 : Keep RAM section S3 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */
+#define POWER_RAM_POWERCLR_S3POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */
+#define POWER_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */
+
+/* Bit 2 : Keep RAM section S2 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */
+#define POWER_RAM_POWERCLR_S2POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */
+#define POWER_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */
+
+/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
+
+/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
+
+
+/* Peripheral: PPI */
+/* Description: Programmable Peripheral Interconnect */
+
+/* Register: PPI_CHEN */
+/* Description: Channel enable register */
+
+/* Bit 31 : Enable or disable channel 31 */
+#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 30 : Enable or disable channel 30 */
+#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 29 : Enable or disable channel 29 */
+#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 28 : Enable or disable channel 28 */
+#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 27 : Enable or disable channel 27 */
+#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 26 : Enable or disable channel 26 */
+#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 25 : Enable or disable channel 25 */
+#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 24 : Enable or disable channel 24 */
+#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 23 : Enable or disable channel 23 */
+#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 22 : Enable or disable channel 22 */
+#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 21 : Enable or disable channel 21 */
+#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 20 : Enable or disable channel 20 */
+#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 19 : Enable or disable channel 19 */
+#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 18 : Enable or disable channel 18 */
+#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 17 : Enable or disable channel 17 */
+#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 16 : Enable or disable channel 16 */
+#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 15 : Enable or disable channel 15 */
+#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 14 : Enable or disable channel 14 */
+#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 13 : Enable or disable channel 13 */
+#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 12 : Enable or disable channel 12 */
+#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 11 : Enable or disable channel 11 */
+#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 10 : Enable or disable channel 10 */
+#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 9 : Enable or disable channel 9 */
+#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 8 : Enable or disable channel 8 */
+#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 7 : Enable or disable channel 7 */
+#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 6 : Enable or disable channel 6 */
+#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 5 : Enable or disable channel 5 */
+#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 4 : Enable or disable channel 4 */
+#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 3 : Enable or disable channel 3 */
+#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 2 : Enable or disable channel 2 */
+#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 1 : Enable or disable channel 1 */
+#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 0 : Enable or disable channel 0 */
+#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
+
+/* Register: PPI_CHENSET */
+/* Description: Channel enable set register */
+
+/* Bit 31 : Channel 31 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 30 : Channel 30 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 29 : Channel 29 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 28 : Channel 28 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 27 : Channel 27 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 26 : Channel 26 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 25 : Channel 25 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 24 : Channel 24 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 23 : Channel 23 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 22 : Channel 22 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 21 : Channel 21 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 20 : Channel 20 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 19 : Channel 19 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 18 : Channel 18 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 17 : Channel 17 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 16 : Channel 16 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
+
+/* Register: PPI_CHENCLR */
+/* Description: Channel enable clear register */
+
+/* Bit 31 : Channel 31 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 30 : Channel 30 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 29 : Channel 29 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 28 : Channel 28 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 27 : Channel 27 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 26 : Channel 26 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 25 : Channel 25 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 24 : Channel 24 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 23 : Channel 23 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 22 : Channel 22 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 21 : Channel 21 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 20 : Channel 20 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 19 : Channel 19 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 18 : Channel 18 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 17 : Channel 17 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 16 : Channel 16 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
+
+/* Register: PPI_CH_EEP */
+/* Description: Description cluster[0]:  Channel 0 event end-point */
+
+/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
+#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
+#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
+
+/* Register: PPI_CH_TEP */
+/* Description: Description cluster[0]:  Channel 0 task end-point */
+
+/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
+#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
+#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
+
+/* Register: PPI_CHG */
+/* Description: Description collection[0]:  Channel group 0 */
+
+/* Bit 31 : Include or exclude channel 31 */
+#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH31_Included (1UL) /*!< Include */
+
+/* Bit 30 : Include or exclude channel 30 */
+#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH30_Included (1UL) /*!< Include */
+
+/* Bit 29 : Include or exclude channel 29 */
+#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH29_Included (1UL) /*!< Include */
+
+/* Bit 28 : Include or exclude channel 28 */
+#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH28_Included (1UL) /*!< Include */
+
+/* Bit 27 : Include or exclude channel 27 */
+#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH27_Included (1UL) /*!< Include */
+
+/* Bit 26 : Include or exclude channel 26 */
+#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH26_Included (1UL) /*!< Include */
+
+/* Bit 25 : Include or exclude channel 25 */
+#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH25_Included (1UL) /*!< Include */
+
+/* Bit 24 : Include or exclude channel 24 */
+#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH24_Included (1UL) /*!< Include */
+
+/* Bit 23 : Include or exclude channel 23 */
+#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH23_Included (1UL) /*!< Include */
+
+/* Bit 22 : Include or exclude channel 22 */
+#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH22_Included (1UL) /*!< Include */
+
+/* Bit 21 : Include or exclude channel 21 */
+#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH21_Included (1UL) /*!< Include */
+
+/* Bit 20 : Include or exclude channel 20 */
+#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH20_Included (1UL) /*!< Include */
+
+/* Bit 19 : Include or exclude channel 19 */
+#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH19_Included (1UL) /*!< Include */
+
+/* Bit 18 : Include or exclude channel 18 */
+#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH18_Included (1UL) /*!< Include */
+
+/* Bit 17 : Include or exclude channel 17 */
+#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH17_Included (1UL) /*!< Include */
+
+/* Bit 16 : Include or exclude channel 16 */
+#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH16_Included (1UL) /*!< Include */
+
+/* Bit 15 : Include or exclude channel 15 */
+#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH15_Included (1UL) /*!< Include */
+
+/* Bit 14 : Include or exclude channel 14 */
+#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH14_Included (1UL) /*!< Include */
+
+/* Bit 13 : Include or exclude channel 13 */
+#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH13_Included (1UL) /*!< Include */
+
+/* Bit 12 : Include or exclude channel 12 */
+#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH12_Included (1UL) /*!< Include */
+
+/* Bit 11 : Include or exclude channel 11 */
+#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH11_Included (1UL) /*!< Include */
+
+/* Bit 10 : Include or exclude channel 10 */
+#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH10_Included (1UL) /*!< Include */
+
+/* Bit 9 : Include or exclude channel 9 */
+#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH9_Included (1UL) /*!< Include */
+
+/* Bit 8 : Include or exclude channel 8 */
+#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH8_Included (1UL) /*!< Include */
+
+/* Bit 7 : Include or exclude channel 7 */
+#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH7_Included (1UL) /*!< Include */
+
+/* Bit 6 : Include or exclude channel 6 */
+#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH6_Included (1UL) /*!< Include */
+
+/* Bit 5 : Include or exclude channel 5 */
+#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH5_Included (1UL) /*!< Include */
+
+/* Bit 4 : Include or exclude channel 4 */
+#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH4_Included (1UL) /*!< Include */
+
+/* Bit 3 : Include or exclude channel 3 */
+#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH3_Included (1UL) /*!< Include */
+
+/* Bit 2 : Include or exclude channel 2 */
+#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH2_Included (1UL) /*!< Include */
+
+/* Bit 1 : Include or exclude channel 1 */
+#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH1_Included (1UL) /*!< Include */
+
+/* Bit 0 : Include or exclude channel 0 */
+#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH0_Included (1UL) /*!< Include */
+
+/* Register: PPI_FORK_TEP */
+/* Description: Description cluster[0]:  Channel 0 task end-point */
+
+/* Bits 31..0 : Pointer to task register */
+#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
+#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
+
+
+/* Peripheral: PWM */
+/* Description: Pulse Width Modulation Unit 0 */
+
+/* Register: PWM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */
+#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
+#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
+#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */
+#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
+#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
+#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */
+#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
+#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
+#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: PWM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
+#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
+#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
+#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
+#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
+#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
+#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: PWM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */
+#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */
+#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */
+#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */
+#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */
+#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */
+#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: PWM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */
+#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */
+#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */
+#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */
+#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */
+#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */
+#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: PWM_ENABLE */
+/* Description: PWM module enable register */
+
+/* Bit 0 : Enable or disable PWM module */
+#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
+#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: PWM_MODE */
+/* Description: Selects operating mode of the wave counter */
+
+/* Bit 0 : Selects up or up and down as wave counter mode */
+#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
+#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
+#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */
+#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */
+
+/* Register: PWM_COUNTERTOP */
+/* Description: Value up to which the pulse generator counter counts */
+
+/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */
+#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
+#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
+
+/* Register: PWM_PRESCALER */
+/* Description: Configuration for PWM_CLK */
+
+/* Bits 2..0 : Pre-scaler of PWM_CLK */
+#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by   1 (16MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by   2 ( 8MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by   4 ( 4MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by   8 ( 2MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by  16 ( 1MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by  32 ( 500kHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by  64 ( 250kHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */
+
+/* Register: PWM_DECODER */
+/* Description: Configuration of the decoder */
+
+/* Bit 8 : Selects source for advancing the active sequence */
+#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
+#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
+#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
+#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
+
+/* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */
+#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
+#define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
+#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
+#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
+#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
+#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
+
+/* Register: PWM_LOOP */
+/* Description: Amount of playback of a loop */
+
+/* Bits 15..0 : Amount of playback of pattern cycles */
+#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
+
+/* Register: PWM_SEQ_PTR */
+/* Description: Description cluster[0]:  Beginning address in Data RAM of sequence A */
+
+/* Bits 31..0 : Beginning address in Data RAM of sequence A */
+#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: PWM_SEQ_CNT */
+/* Description: Description cluster[0]:  Amount of values (duty cycles) in sequence A */
+
+/* Bits 14..0 : Amount of values (duty cycles) in sequence A */
+#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
+
+/* Register: PWM_SEQ_REFRESH */
+/* Description: Description cluster[0]:  Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */
+
+/* Bits 23..0 : Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */
+#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
+
+/* Register: PWM_SEQ_ENDDELAY */
+/* Description: Description cluster[0]:  Time added after the sequence */
+
+/* Bits 23..0 : Time added after the sequence in PWM periods */
+#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
+
+/* Register: PWM_PSEL_OUT */
+/* Description: Description collection[0]:  Output pin select for PWM channel 0 */
+
+/* Bit 31 : Connection */
+#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
+#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 9..8 : Port number */
+#define PWM_PSEL_OUT_PORT_Pos (8UL) /*!< Position of PORT field. */
+#define PWM_PSEL_OUT_PORT_Msk (0x3UL << PWM_PSEL_OUT_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
+
+
+/* Peripheral: QDEC */
+/* Description: Quadrature Decoder */
+
+/* Register: QDEC_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between DBLRDY event and STOP task */
+#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
+#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
+#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between REPORTRDY event and STOP task */
+#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
+#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
+#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: QDEC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 4 : Write '1' to Enable interrupt for STOPPED event */
+#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
+#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */
+#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
+#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
+#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for ACCOF event */
+#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */
+#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */
+#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
+
+/* Register: QDEC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 4 : Write '1' to Disable interrupt for STOPPED event */
+#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
+#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */
+#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
+#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
+#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for ACCOF event */
+#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */
+#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */
+#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
+
+/* Register: QDEC_ENABLE */
+/* Description: Enable the quadrature decoder */
+
+/* Bit 0 : Enable or disable the quadrature decoder */
+#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: QDEC_LEDPOL */
+/* Description: LED output pin polarity */
+
+/* Bit 0 : LED output pin polarity */
+#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
+#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
+
+/* Register: QDEC_SAMPLEPER */
+/* Description: Sample period */
+
+/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
+#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
+
+/* Register: QDEC_SAMPLE */
+/* Description: Motion sample value */
+
+/* Bits 31..0 : Last motion sample */
+#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
+#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
+
+/* Register: QDEC_REPORTPER */
+/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
+
+/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */
+#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */
+#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */
+#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
+#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */
+#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */
+#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */
+#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */
+#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */
+#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */
+
+/* Register: QDEC_ACC */
+/* Description: Register accumulating the valid transitions */
+
+/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */
+#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
+#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
+
+/* Register: QDEC_ACCREAD */
+/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
+
+/* Bits 31..0 : Snapshot of the ACC register. */
+#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
+#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
+
+/* Register: QDEC_PSEL_LED */
+/* Description: Pin select for LED signal */
+
+/* Bit 31 : Connection */
+#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
+#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define QDEC_PSEL_LED_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QDEC_PSEL_LED_PORT_Msk (0x3UL << QDEC_PSEL_LED_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QDEC_PSEL_A */
+/* Description: Pin select for A signal */
+
+/* Bit 31 : Connection */
+#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
+#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define QDEC_PSEL_A_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QDEC_PSEL_A_PORT_Msk (0x3UL << QDEC_PSEL_A_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QDEC_PSEL_B */
+/* Description: Pin select for B signal */
+
+/* Bit 31 : Connection */
+#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
+#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define QDEC_PSEL_B_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QDEC_PSEL_B_PORT_Msk (0x3UL << QDEC_PSEL_B_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QDEC_DBFEN */
+/* Description: Enable input debounce filters */
+
+/* Bit 0 : Enable input debounce filters */
+#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
+#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
+
+/* Register: QDEC_LEDPRE */
+/* Description: Time period the LED is switched ON prior to sampling */
+
+/* Bits 8..0 : Period in us the LED is switched on prior to sampling */
+#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
+#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
+
+/* Register: QDEC_ACCDBL */
+/* Description: Register accumulating the number of detected double transitions */
+
+/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
+#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
+#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
+
+/* Register: QDEC_ACCDBLREAD */
+/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
+
+/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
+
+
+/* Peripheral: QSPI */
+/* Description: External flash interface */
+
+/* Register: QSPI_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 0 : Enable or disable interrupt for READY event */
+#define QSPI_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
+#define QSPI_INTEN_READY_Msk (0x1UL << QSPI_INTEN_READY_Pos) /*!< Bit mask of READY field. */
+#define QSPI_INTEN_READY_Disabled (0UL) /*!< Disable */
+#define QSPI_INTEN_READY_Enabled (1UL) /*!< Enable */
+
+/* Register: QSPI_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define QSPI_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define QSPI_INTENSET_READY_Msk (0x1UL << QSPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define QSPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define QSPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define QSPI_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: QSPI_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define QSPI_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define QSPI_INTENCLR_READY_Msk (0x1UL << QSPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define QSPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define QSPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define QSPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: QSPI_ENABLE */
+/* Description: Enable QSPI peripheral and acquire the pins selected in PSELn registers */
+
+/* Bit 0 : Enable or disable QSPI */
+#define QSPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define QSPI_ENABLE_ENABLE_Msk (0x1UL << QSPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define QSPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable QSPI */
+#define QSPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QSPI */
+
+/* Register: QSPI_READ_SRC */
+/* Description: Flash memory source address */
+
+/* Bits 31..0 : Word-aligned flash memory source address. */
+#define QSPI_READ_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define QSPI_READ_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_READ_SRC_SRC_Pos) /*!< Bit mask of SRC field. */
+
+/* Register: QSPI_READ_DST */
+/* Description: RAM destination address */
+
+/* Bits 31..0 : Word-aligned RAM destination address. */
+#define QSPI_READ_DST_DST_Pos (0UL) /*!< Position of DST field. */
+#define QSPI_READ_DST_DST_Msk (0xFFFFFFFFUL << QSPI_READ_DST_DST_Pos) /*!< Bit mask of DST field. */
+
+/* Register: QSPI_READ_CNT */
+/* Description: Read transfer length */
+
+/* Bits 20..0 : Read transfer length in number of bytes. The length must be a multiple of 4 bytes. */
+#define QSPI_READ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define QSPI_READ_CNT_CNT_Msk (0x1FFFFFUL << QSPI_READ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
+
+/* Register: QSPI_WRITE_DST */
+/* Description: Flash destination address */
+
+/* Bits 31..0 : Word-aligned flash destination address. */
+#define QSPI_WRITE_DST_DST_Pos (0UL) /*!< Position of DST field. */
+#define QSPI_WRITE_DST_DST_Msk (0xFFFFFFFFUL << QSPI_WRITE_DST_DST_Pos) /*!< Bit mask of DST field. */
+
+/* Register: QSPI_WRITE_SRC */
+/* Description: RAM source address */
+
+/* Bits 31..0 : Word-aligned RAM source address. */
+#define QSPI_WRITE_SRC_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define QSPI_WRITE_SRC_SRC_Msk (0xFFFFFFFFUL << QSPI_WRITE_SRC_SRC_Pos) /*!< Bit mask of SRC field. */
+
+/* Register: QSPI_WRITE_CNT */
+/* Description: Write transfer length */
+
+/* Bits 20..0 : Write transfer length in number of bytes. The length must be a multiple of 4 bytes. */
+#define QSPI_WRITE_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define QSPI_WRITE_CNT_CNT_Msk (0x1FFFFFUL << QSPI_WRITE_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
+
+/* Register: QSPI_ERASE_PTR */
+/* Description: Start address of flash block to be erased */
+
+/* Bits 31..0 : Word-aligned start address of block to be erased. */
+#define QSPI_ERASE_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define QSPI_ERASE_PTR_PTR_Msk (0xFFFFFFFFUL << QSPI_ERASE_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: QSPI_ERASE_LEN */
+/* Description: Size of block to be erased. */
+
+/* Bits 1..0 : LEN */
+#define QSPI_ERASE_LEN_LEN_Pos (0UL) /*!< Position of LEN field. */
+#define QSPI_ERASE_LEN_LEN_Msk (0x3UL << QSPI_ERASE_LEN_LEN_Pos) /*!< Bit mask of LEN field. */
+#define QSPI_ERASE_LEN_LEN_4KB (0UL) /*!< Erase 4 kB block (flash command 0x20) */
+#define QSPI_ERASE_LEN_LEN_64KB (1UL) /*!< Erase 64 kB block (flash command 0xD8) */
+#define QSPI_ERASE_LEN_LEN_All (2UL) /*!< Erase all (flash command 0xC7) */
+
+/* Register: QSPI_PSEL_SCK */
+/* Description: Pin select for serial clock SCK */
+
+/* Bit 31 : Connection */
+#define QSPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QSPI_PSEL_SCK_CONNECT_Msk (0x1UL << QSPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QSPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define QSPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define QSPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QSPI_PSEL_SCK_PORT_Msk (0x3UL << QSPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QSPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QSPI_PSEL_SCK_PIN_Msk (0x1FUL << QSPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QSPI_PSEL_CSN */
+/* Description: Pin select for chip select signal CSN. */
+
+/* Bit 31 : Connection */
+#define QSPI_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QSPI_PSEL_CSN_CONNECT_Msk (0x1UL << QSPI_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QSPI_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
+#define QSPI_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define QSPI_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QSPI_PSEL_CSN_PORT_Msk (0x3UL << QSPI_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QSPI_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QSPI_PSEL_CSN_PIN_Msk (0x1FUL << QSPI_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QSPI_PSEL_IO0 */
+/* Description: Pin select for serial data MOSI/IO0. */
+
+/* Bit 31 : Connection */
+#define QSPI_PSEL_IO0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QSPI_PSEL_IO0_CONNECT_Msk (0x1UL << QSPI_PSEL_IO0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QSPI_PSEL_IO0_CONNECT_Connected (0UL) /*!< Connect */
+#define QSPI_PSEL_IO0_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define QSPI_PSEL_IO0_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QSPI_PSEL_IO0_PORT_Msk (0x3UL << QSPI_PSEL_IO0_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QSPI_PSEL_IO0_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QSPI_PSEL_IO0_PIN_Msk (0x1FUL << QSPI_PSEL_IO0_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QSPI_PSEL_IO1 */
+/* Description: Pin select for serial data MISO/IO1. */
+
+/* Bit 31 : Connection */
+#define QSPI_PSEL_IO1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QSPI_PSEL_IO1_CONNECT_Msk (0x1UL << QSPI_PSEL_IO1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QSPI_PSEL_IO1_CONNECT_Connected (0UL) /*!< Connect */
+#define QSPI_PSEL_IO1_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define QSPI_PSEL_IO1_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QSPI_PSEL_IO1_PORT_Msk (0x3UL << QSPI_PSEL_IO1_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QSPI_PSEL_IO1_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QSPI_PSEL_IO1_PIN_Msk (0x1FUL << QSPI_PSEL_IO1_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QSPI_PSEL_IO2 */
+/* Description: Pin select for serial data IO2. */
+
+/* Bit 31 : Connection */
+#define QSPI_PSEL_IO2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QSPI_PSEL_IO2_CONNECT_Msk (0x1UL << QSPI_PSEL_IO2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QSPI_PSEL_IO2_CONNECT_Connected (0UL) /*!< Connect */
+#define QSPI_PSEL_IO2_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define QSPI_PSEL_IO2_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QSPI_PSEL_IO2_PORT_Msk (0x3UL << QSPI_PSEL_IO2_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QSPI_PSEL_IO2_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QSPI_PSEL_IO2_PIN_Msk (0x1FUL << QSPI_PSEL_IO2_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QSPI_PSEL_IO3 */
+/* Description: Pin select for serial data IO3. */
+
+/* Bit 31 : Connection */
+#define QSPI_PSEL_IO3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QSPI_PSEL_IO3_CONNECT_Msk (0x1UL << QSPI_PSEL_IO3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QSPI_PSEL_IO3_CONNECT_Connected (0UL) /*!< Connect */
+#define QSPI_PSEL_IO3_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define QSPI_PSEL_IO3_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define QSPI_PSEL_IO3_PORT_Msk (0x3UL << QSPI_PSEL_IO3_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define QSPI_PSEL_IO3_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QSPI_PSEL_IO3_PIN_Msk (0x1FUL << QSPI_PSEL_IO3_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QSPI_XIPOFFSET */
+/* Description: Address offset into the external memory for Execute in Place operation. */
+
+/* Bits 31..0 : Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. */
+#define QSPI_XIPOFFSET_XIPOFFSET_Pos (0UL) /*!< Position of XIPOFFSET field. */
+#define QSPI_XIPOFFSET_XIPOFFSET_Msk (0xFFFFFFFFUL << QSPI_XIPOFFSET_XIPOFFSET_Pos) /*!< Bit mask of XIPOFFSET field. */
+
+/* Register: QSPI_IFCONFIG0 */
+/* Description: Interface configuration. */
+
+/* Bit 7 : Enable deep power-down mode (DPM) feature. */
+#define QSPI_IFCONFIG0_DPMENABLE_Pos (7UL) /*!< Position of DPMENABLE field. */
+#define QSPI_IFCONFIG0_DPMENABLE_Msk (0x1UL << QSPI_IFCONFIG0_DPMENABLE_Pos) /*!< Bit mask of DPMENABLE field. */
+#define QSPI_IFCONFIG0_DPMENABLE_Disable (0UL) /*!< Disable DPM feature. */
+#define QSPI_IFCONFIG0_DPMENABLE_Enable (1UL) /*!< Enable DPM feature. */
+
+/* Bit 6 : Addressing mode. */
+#define QSPI_IFCONFIG0_ADDRMODE_Pos (6UL) /*!< Position of ADDRMODE field. */
+#define QSPI_IFCONFIG0_ADDRMODE_Msk (0x1UL << QSPI_IFCONFIG0_ADDRMODE_Pos) /*!< Bit mask of ADDRMODE field. */
+#define QSPI_IFCONFIG0_ADDRMODE_24BIT (0UL) /*!< 24-bit addressing. */
+#define QSPI_IFCONFIG0_ADDRMODE_32BIT (1UL) /*!< 32-bit addressing. */
+
+/* Bits 5..3 : Configure number of data lines and opcode used for writing. */
+#define QSPI_IFCONFIG0_WRITEOC_Pos (3UL) /*!< Position of WRITEOC field. */
+#define QSPI_IFCONFIG0_WRITEOC_Msk (0x7UL << QSPI_IFCONFIG0_WRITEOC_Pos) /*!< Bit mask of WRITEOC field. */
+#define QSPI_IFCONFIG0_WRITEOC_PP (0UL) /*!< Single data line SPI. PP (opcode 0x02). */
+#define QSPI_IFCONFIG0_WRITEOC_PP2O (1UL) /*!< Dual data line SPI. PP2O (opcode 0xA2). */
+#define QSPI_IFCONFIG0_WRITEOC_PP4O (2UL) /*!< Quad data line SPI. PP4O (opcode 0x32). */
+#define QSPI_IFCONFIG0_WRITEOC_PP4IO (3UL) /*!< Quad data line SPI. PP4IO (opcode 0x38). */
+
+/* Bits 2..0 : Configure number of data lines and opcode used for reading. */
+#define QSPI_IFCONFIG0_READOC_Pos (0UL) /*!< Position of READOC field. */
+#define QSPI_IFCONFIG0_READOC_Msk (0x7UL << QSPI_IFCONFIG0_READOC_Pos) /*!< Bit mask of READOC field. */
+#define QSPI_IFCONFIG0_READOC_FASTREAD (0UL) /*!< Single data line SPI. FAST_READ (opcode 0x0B). */
+#define QSPI_IFCONFIG0_READOC_READ2O (1UL) /*!< Dual data line SPI. READ2O (opcode 0x3B). */
+#define QSPI_IFCONFIG0_READOC_READ2IO (2UL) /*!< Dual data line SPI. READ2IO (opcode 0xBB). */
+#define QSPI_IFCONFIG0_READOC_READ4O (3UL) /*!< Quad data line SPI. READ4O (opcode 0x6B). */
+#define QSPI_IFCONFIG0_READOC_READ4IO (4UL) /*!< Quad data line SPI. READ4IO (opcode 0xEB). */
+
+/* Register: QSPI_IFCONFIG1 */
+/* Description: Interface configuration. */
+
+/* Bits 31..28 : SCK frequency is given as 32 MHz / (SCKFREQ + 1). */
+#define QSPI_IFCONFIG1_SCKFREQ_Pos (28UL) /*!< Position of SCKFREQ field. */
+#define QSPI_IFCONFIG1_SCKFREQ_Msk (0xFUL << QSPI_IFCONFIG1_SCKFREQ_Pos) /*!< Bit mask of SCKFREQ field. */
+
+/* Bit 25 : Select SPI mode. */
+#define QSPI_IFCONFIG1_SPIMODE_Pos (25UL) /*!< Position of SPIMODE field. */
+#define QSPI_IFCONFIG1_SPIMODE_Msk (0x1UL << QSPI_IFCONFIG1_SPIMODE_Pos) /*!< Bit mask of SPIMODE field. */
+#define QSPI_IFCONFIG1_SPIMODE_MODE0 (0UL) /*!< Mode 0: Data are captured on the clock's rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). */
+#define QSPI_IFCONFIG1_SPIMODE_MODE3 (1UL) /*!< Mode 3: Data are captured on the clock's falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). */
+
+/* Bit 24 : Enter/exit deep power-down mode (DPM) for external flash memory. */
+#define QSPI_IFCONFIG1_DPMEN_Pos (24UL) /*!< Position of DPMEN field. */
+#define QSPI_IFCONFIG1_DPMEN_Msk (0x1UL << QSPI_IFCONFIG1_DPMEN_Pos) /*!< Bit mask of DPMEN field. */
+#define QSPI_IFCONFIG1_DPMEN_Exit (0UL) /*!< Exit DPM. */
+#define QSPI_IFCONFIG1_DPMEN_Enter (1UL) /*!< Enter DPM. */
+
+/* Bits 7..0 : Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). */
+#define QSPI_IFCONFIG1_SCKDELAY_Pos (0UL) /*!< Position of SCKDELAY field. */
+#define QSPI_IFCONFIG1_SCKDELAY_Msk (0xFFUL << QSPI_IFCONFIG1_SCKDELAY_Pos) /*!< Bit mask of SCKDELAY field. */
+
+/* Register: QSPI_STATUS */
+/* Description: Status register. */
+
+/* Bits 31..24 : Value of external flash devices Status Register. When the external flash has two bytes status register this field includes the value of the low byte. */
+#define QSPI_STATUS_SREG_Pos (24UL) /*!< Position of SREG field. */
+#define QSPI_STATUS_SREG_Msk (0xFFUL << QSPI_STATUS_SREG_Pos) /*!< Bit mask of SREG field. */
+
+/* Bit 3 : Ready status. */
+#define QSPI_STATUS_READY_Pos (3UL) /*!< Position of READY field. */
+#define QSPI_STATUS_READY_Msk (0x1UL << QSPI_STATUS_READY_Pos) /*!< Bit mask of READY field. */
+#define QSPI_STATUS_READY_BUSY (0UL) /*!< QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. */
+#define QSPI_STATUS_READY_READY (1UL) /*!< QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. */
+
+/* Bit 2 : Deep power-down mode (DPM) status of external flash. */
+#define QSPI_STATUS_DPM_Pos (2UL) /*!< Position of DPM field. */
+#define QSPI_STATUS_DPM_Msk (0x1UL << QSPI_STATUS_DPM_Pos) /*!< Bit mask of DPM field. */
+#define QSPI_STATUS_DPM_Disabled (0UL) /*!< External flash is not in DPM. */
+#define QSPI_STATUS_DPM_Enabled (1UL) /*!< External flash is in DPM. */
+
+/* Register: QSPI_DPMDUR */
+/* Description: Set the duration required to enter/exit deep power-down mode (DPM). */
+
+/* Bits 31..16 : Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. */
+#define QSPI_DPMDUR_EXIT_Pos (16UL) /*!< Position of EXIT field. */
+#define QSPI_DPMDUR_EXIT_Msk (0xFFFFUL << QSPI_DPMDUR_EXIT_Pos) /*!< Bit mask of EXIT field. */
+
+/* Bits 15..0 : Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. */
+#define QSPI_DPMDUR_ENTER_Pos (0UL) /*!< Position of ENTER field. */
+#define QSPI_DPMDUR_ENTER_Msk (0xFFFFUL << QSPI_DPMDUR_ENTER_Pos) /*!< Bit mask of ENTER field. */
+
+/* Register: QSPI_ADDRCONF */
+/* Description: Extended address configuration. */
+
+/* Bit 27 : Send WREN (write enable opcode 0x06) before instruction. */
+#define QSPI_ADDRCONF_WREN_Pos (27UL) /*!< Position of WREN field. */
+#define QSPI_ADDRCONF_WREN_Msk (0x1UL << QSPI_ADDRCONF_WREN_Pos) /*!< Bit mask of WREN field. */
+#define QSPI_ADDRCONF_WREN_Disable (0UL) /*!< Do not send WREN. */
+#define QSPI_ADDRCONF_WREN_Enable (1UL) /*!< Send WREN. */
+
+/* Bit 26 : Wait for write complete before sending command. */
+#define QSPI_ADDRCONF_WIPWAIT_Pos (26UL) /*!< Position of WIPWAIT field. */
+#define QSPI_ADDRCONF_WIPWAIT_Msk (0x1UL << QSPI_ADDRCONF_WIPWAIT_Pos) /*!< Bit mask of WIPWAIT field. */
+#define QSPI_ADDRCONF_WIPWAIT_Disable (0UL) /*!< No wait. */
+#define QSPI_ADDRCONF_WIPWAIT_Enable (1UL) /*!< Wait. */
+
+/* Bits 25..24 : Extended addressing mode. */
+#define QSPI_ADDRCONF_MODE_Pos (24UL) /*!< Position of MODE field. */
+#define QSPI_ADDRCONF_MODE_Msk (0x3UL << QSPI_ADDRCONF_MODE_Pos) /*!< Bit mask of MODE field. */
+#define QSPI_ADDRCONF_MODE_NoInstr (0UL) /*!< Do not send any instruction. */
+#define QSPI_ADDRCONF_MODE_Opcode (1UL) /*!< Send opcode. */
+#define QSPI_ADDRCONF_MODE_OpByte0 (2UL) /*!< Send opcode, byte0. */
+#define QSPI_ADDRCONF_MODE_All (3UL) /*!< Send opcode, byte0, byte1. */
+
+/* Bits 23..16 : Byte 1 following byte 0. */
+#define QSPI_ADDRCONF_BYTE1_Pos (16UL) /*!< Position of BYTE1 field. */
+#define QSPI_ADDRCONF_BYTE1_Msk (0xFFUL << QSPI_ADDRCONF_BYTE1_Pos) /*!< Bit mask of BYTE1 field. */
+
+/* Bits 15..8 : Byte 0 following opcode. */
+#define QSPI_ADDRCONF_BYTE0_Pos (8UL) /*!< Position of BYTE0 field. */
+#define QSPI_ADDRCONF_BYTE0_Msk (0xFFUL << QSPI_ADDRCONF_BYTE0_Pos) /*!< Bit mask of BYTE0 field. */
+
+/* Bits 7..0 : Opcode that enters the 32-bit addressing mode. */
+#define QSPI_ADDRCONF_OPCODE_Pos (0UL) /*!< Position of OPCODE field. */
+#define QSPI_ADDRCONF_OPCODE_Msk (0xFFUL << QSPI_ADDRCONF_OPCODE_Pos) /*!< Bit mask of OPCODE field. */
+
+/* Register: QSPI_CINSTRCONF */
+/* Description: Custom instruction configuration register. */
+
+/* Bit 15 : Send WREN (write enable opcode 0x06) before instruction. */
+#define QSPI_CINSTRCONF_WREN_Pos (15UL) /*!< Position of WREN field. */
+#define QSPI_CINSTRCONF_WREN_Msk (0x1UL << QSPI_CINSTRCONF_WREN_Pos) /*!< Bit mask of WREN field. */
+#define QSPI_CINSTRCONF_WREN_Disable (0UL) /*!< Do not send WREN. */
+#define QSPI_CINSTRCONF_WREN_Enable (1UL) /*!< Send WREN. */
+
+/* Bit 14 : Wait for write complete before sending command. */
+#define QSPI_CINSTRCONF_WIPWAIT_Pos (14UL) /*!< Position of WIPWAIT field. */
+#define QSPI_CINSTRCONF_WIPWAIT_Msk (0x1UL << QSPI_CINSTRCONF_WIPWAIT_Pos) /*!< Bit mask of WIPWAIT field. */
+#define QSPI_CINSTRCONF_WIPWAIT_Disable (0UL) /*!< No wait. */
+#define QSPI_CINSTRCONF_WIPWAIT_Enable (1UL) /*!< Wait. */
+
+/* Bit 13 : Level of the IO3 pin (if connected) during transmission of custom instruction. */
+#define QSPI_CINSTRCONF_LIO3_Pos (13UL) /*!< Position of LIO3 field. */
+#define QSPI_CINSTRCONF_LIO3_Msk (0x1UL << QSPI_CINSTRCONF_LIO3_Pos) /*!< Bit mask of LIO3 field. */
+
+/* Bit 12 : Level of the IO2 pin (if connected) during transmission of custom instruction. */
+#define QSPI_CINSTRCONF_LIO2_Pos (12UL) /*!< Position of LIO2 field. */
+#define QSPI_CINSTRCONF_LIO2_Msk (0x1UL << QSPI_CINSTRCONF_LIO2_Pos) /*!< Bit mask of LIO2 field. */
+
+/* Bits 11..8 : Length of custom instruction in number of bytes. */
+#define QSPI_CINSTRCONF_LENGTH_Pos (8UL) /*!< Position of LENGTH field. */
+#define QSPI_CINSTRCONF_LENGTH_Msk (0xFUL << QSPI_CINSTRCONF_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
+#define QSPI_CINSTRCONF_LENGTH_1B (1UL) /*!< Send opcode only. */
+#define QSPI_CINSTRCONF_LENGTH_2B (2UL) /*!< Send opcode, CINSTRDAT0.BYTE0. */
+#define QSPI_CINSTRCONF_LENGTH_3B (3UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE1. */
+#define QSPI_CINSTRCONF_LENGTH_4B (4UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE2. */
+#define QSPI_CINSTRCONF_LENGTH_5B (5UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE3. */
+#define QSPI_CINSTRCONF_LENGTH_6B (6UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE4. */
+#define QSPI_CINSTRCONF_LENGTH_7B (7UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE5. */
+#define QSPI_CINSTRCONF_LENGTH_8B (8UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE6. */
+#define QSPI_CINSTRCONF_LENGTH_9B (9UL) /*!< Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE7. */
+
+/* Bits 7..0 : Opcode of Custom instruction. */
+#define QSPI_CINSTRCONF_OPCODE_Pos (0UL) /*!< Position of OPCODE field. */
+#define QSPI_CINSTRCONF_OPCODE_Msk (0xFFUL << QSPI_CINSTRCONF_OPCODE_Pos) /*!< Bit mask of OPCODE field. */
+
+/* Register: QSPI_CINSTRDAT0 */
+/* Description: Custom instruction data register 0. */
+
+/* Bits 31..24 : Data byte 3 */
+#define QSPI_CINSTRDAT0_BYTE3_Pos (24UL) /*!< Position of BYTE3 field. */
+#define QSPI_CINSTRDAT0_BYTE3_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE3_Pos) /*!< Bit mask of BYTE3 field. */
+
+/* Bits 23..16 : Data byte 2 */
+#define QSPI_CINSTRDAT0_BYTE2_Pos (16UL) /*!< Position of BYTE2 field. */
+#define QSPI_CINSTRDAT0_BYTE2_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE2_Pos) /*!< Bit mask of BYTE2 field. */
+
+/* Bits 15..8 : Data byte 1 */
+#define QSPI_CINSTRDAT0_BYTE1_Pos (8UL) /*!< Position of BYTE1 field. */
+#define QSPI_CINSTRDAT0_BYTE1_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE1_Pos) /*!< Bit mask of BYTE1 field. */
+
+/* Bits 7..0 : Data byte 0 */
+#define QSPI_CINSTRDAT0_BYTE0_Pos (0UL) /*!< Position of BYTE0 field. */
+#define QSPI_CINSTRDAT0_BYTE0_Msk (0xFFUL << QSPI_CINSTRDAT0_BYTE0_Pos) /*!< Bit mask of BYTE0 field. */
+
+/* Register: QSPI_CINSTRDAT1 */
+/* Description: Custom instruction data register 1. */
+
+/* Bits 31..24 : Data byte 7 */
+#define QSPI_CINSTRDAT1_BYTE7_Pos (24UL) /*!< Position of BYTE7 field. */
+#define QSPI_CINSTRDAT1_BYTE7_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE7_Pos) /*!< Bit mask of BYTE7 field. */
+
+/* Bits 23..16 : Data byte 6 */
+#define QSPI_CINSTRDAT1_BYTE6_Pos (16UL) /*!< Position of BYTE6 field. */
+#define QSPI_CINSTRDAT1_BYTE6_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE6_Pos) /*!< Bit mask of BYTE6 field. */
+
+/* Bits 15..8 : Data byte 5 */
+#define QSPI_CINSTRDAT1_BYTE5_Pos (8UL) /*!< Position of BYTE5 field. */
+#define QSPI_CINSTRDAT1_BYTE5_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE5_Pos) /*!< Bit mask of BYTE5 field. */
+
+/* Bits 7..0 : Data byte 4 */
+#define QSPI_CINSTRDAT1_BYTE4_Pos (0UL) /*!< Position of BYTE4 field. */
+#define QSPI_CINSTRDAT1_BYTE4_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE4_Pos) /*!< Bit mask of BYTE4 field. */
+
+/* Register: QSPI_IFTIMING */
+/* Description: SPI interface timing. */
+
+/* Bits 10..8 : Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. */
+#define QSPI_IFTIMING_RXDELAY_Pos (8UL) /*!< Position of RXDELAY field. */
+#define QSPI_IFTIMING_RXDELAY_Msk (0x7UL << QSPI_IFTIMING_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */
+
+
+/* Peripheral: RADIO */
+/* Description: 2.4 GHz Radio */
+
+/* Register: RADIO_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 19 : Shortcut between RXREADY event and START task */
+#define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */
+#define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */
+#define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 18 : Shortcut between TXREADY event and START task */
+#define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */
+#define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */
+#define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 17 : Shortcut between CCAIDLE event and STOP task */
+#define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */
+#define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */
+#define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 16 : Shortcut between EDEND event and DISABLE task */
+#define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */
+#define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */
+#define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 15 : Shortcut between READY event and EDSTART task */
+#define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */
+#define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */
+#define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 14 : Shortcut between FRAMESTART event and BCSTART task */
+#define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */
+#define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */
+#define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 13 : Shortcut between CCABUSY event and DISABLE task */
+#define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */
+#define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */
+#define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 12 : Shortcut between CCAIDLE event and TXEN task */
+#define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */
+#define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */
+#define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 11 : Shortcut between RXREADY event and CCASTART task */
+#define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */
+#define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */
+#define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between END event and START task */
+#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
+#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between DISABLED event and RXEN task */
+#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between DISABLED event and TXEN task */
+#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between END event and DISABLE task */
+#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between READY event and START task */
+#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
+#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
+#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: RADIO_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 23 : Write '1' to Enable interrupt for MHRMATCH event */
+#define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
+#define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
+#define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */
+
+/* Bit 22 : Write '1' to Enable interrupt for RXREADY event */
+#define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
+#define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
+#define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */
+
+/* Bit 21 : Write '1' to Enable interrupt for TXREADY event */
+#define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
+#define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
+#define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for RATEBOOST event */
+#define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */
+#define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */
+#define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for CCASTOPPED event */
+#define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */
+#define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */
+#define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for CCABUSY event */
+#define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */
+#define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */
+#define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for CCAIDLE event */
+#define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */
+#define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */
+#define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for EDSTOPPED event */
+#define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */
+#define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */
+#define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 15 : Write '1' to Enable interrupt for EDEND event */
+#define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */
+#define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */
+#define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for FRAMESTART event */
+#define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */
+#define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
+#define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */
+#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
+#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for CRCOK event */
+#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
+#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
+#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */
+#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */
+#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */
+#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */
+#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for DISABLED event */
+#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for END event */
+#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */
+#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */
+#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: RADIO_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 23 : Write '1' to Disable interrupt for MHRMATCH event */
+#define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */
+#define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */
+#define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */
+
+/* Bit 22 : Write '1' to Disable interrupt for RXREADY event */
+#define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */
+#define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */
+#define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */
+
+/* Bit 21 : Write '1' to Disable interrupt for TXREADY event */
+#define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */
+#define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */
+#define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for RATEBOOST event */
+#define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */
+#define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */
+#define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for CCASTOPPED event */
+#define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */
+#define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */
+#define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for CCABUSY event */
+#define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */
+#define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */
+#define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for CCAIDLE event */
+#define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */
+#define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */
+#define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for EDSTOPPED event */
+#define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */
+#define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */
+#define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 15 : Write '1' to Disable interrupt for EDEND event */
+#define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */
+#define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */
+#define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for FRAMESTART event */
+#define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */
+#define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */
+#define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */
+#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
+#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for CRCOK event */
+#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
+#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
+#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */
+#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */
+#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */
+#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */
+#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for DISABLED event */
+#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for END event */
+#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */
+#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */
+#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: RADIO_CRCSTATUS */
+/* Description: CRC status */
+
+/* Bit 0 : CRC status of packet received */
+#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
+
+/* Register: RADIO_RXMATCH */
+/* Description: Received address */
+
+/* Bits 2..0 : Received address */
+#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
+#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
+
+/* Register: RADIO_RXCRC */
+/* Description: CRC field of previously received packet */
+
+/* Bits 23..0 : CRC field of previously received packet */
+#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
+#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
+
+/* Register: RADIO_DAI */
+/* Description: Device address match index */
+
+/* Bits 2..0 : Device address match index */
+#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
+#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
+
+/* Register: RADIO_PACKETPTR */
+/* Description: Packet pointer */
+
+/* Bits 31..0 : Packet pointer */
+#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
+#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
+
+/* Register: RADIO_FREQUENCY */
+/* Description: Frequency */
+
+/* Bit 8 : Channel map selection. */
+#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
+#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
+#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
+#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
+
+/* Bits 6..0 : Radio channel frequency */
+#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+
+/* Register: RADIO_TXPOWER */
+/* Description: Output power */
+
+/* Bits 7..0 : RADIO output power. */
+#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos2dBm (0x2UL) /*!< +2 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x3UL) /*!< +3 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x4UL) /*!< +4 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos5dBm (0x5UL) /*!< +5 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos6dBm (0x6UL) /*!< +6 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x7UL) /*!< +7 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x8UL) /*!< +8 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos9dBm (0x9UL) /*!< +9 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator -  -40 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
+
+/* Register: RADIO_MODE */
+/* Description: Data rate and modulation */
+
+/* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */
+#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator -  250 kbit/s Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */
+#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */
+#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbit/s (TX Only - RX supports both) */
+#define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long range 500 kbit/s (TX Only - RX supports both) */
+#define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbit/s */
+
+/* Register: RADIO_PCNF0 */
+/* Description: Packet configuration register 0 */
+
+/* Bits 30..29 : Length of TERM field in Long Range operation */
+#define RADIO_PCNF0_TERMLEN_Pos (29UL) /*!< Position of TERMLEN field. */
+#define RADIO_PCNF0_TERMLEN_Msk (0x3UL << RADIO_PCNF0_TERMLEN_Pos) /*!< Bit mask of TERMLEN field. */
+
+/* Bit 26 : Indicates if LENGTH field contains CRC or not */
+#define RADIO_PCNF0_CRCINC_Pos (26UL) /*!< Position of CRCINC field. */
+#define RADIO_PCNF0_CRCINC_Msk (0x1UL << RADIO_PCNF0_CRCINC_Pos) /*!< Bit mask of CRCINC field. */
+#define RADIO_PCNF0_CRCINC_Exclude (0UL) /*!< LENGTH does not contain CRC */
+#define RADIO_PCNF0_CRCINC_Include (1UL) /*!< LENGTH includes CRC */
+
+/* Bits 25..24 : Length of preamble on air. Decision point: TASKS_START task */
+#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
+#define RADIO_PCNF0_PLEN_Msk (0x3UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
+#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
+#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
+#define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */
+#define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for BTLE Long Range */
+
+/* Bits 23..22 : Length of Code Indicator - Long Range */
+#define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */
+#define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */
+
+/* Bit 20 : Include or exclude S1 field in RAM */
+#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
+#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
+#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
+#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
+
+/* Bits 19..16 : Length on air of S1 field in number of bits. */
+#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
+#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
+
+/* Bit 8 : Length on air of S0 field in number of bytes. */
+#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
+#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
+
+/* Bits 3..0 : Length on air of LENGTH field in number of bits. */
+#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
+#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
+
+/* Register: RADIO_PCNF1 */
+/* Description: Packet configuration register 1 */
+
+/* Bit 25 : Enable or disable packet whitening */
+#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
+#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
+#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */
+#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
+
+/* Bits 18..16 : Base address length in number of bytes */
+#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
+#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
+
+/* Bits 15..8 : Static length in number of bytes */
+#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
+#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
+
+/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
+#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
+#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
+
+/* Register: RADIO_BASE0 */
+/* Description: Base address 0 */
+
+/* Bits 31..0 : Base address 0 */
+#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
+#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
+
+/* Register: RADIO_BASE1 */
+/* Description: Base address 1 */
+
+/* Bits 31..0 : Base address 1 */
+#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
+#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
+
+/* Register: RADIO_PREFIX0 */
+/* Description: Prefixes bytes for logical addresses 0-3 */
+
+/* Bits 31..24 : Address prefix 3. */
+#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
+#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
+
+/* Bits 23..16 : Address prefix 2. */
+#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
+#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
+
+/* Bits 15..8 : Address prefix 1. */
+#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
+#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
+
+/* Bits 7..0 : Address prefix 0. */
+#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
+#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
+
+/* Register: RADIO_PREFIX1 */
+/* Description: Prefixes bytes for logical addresses 4-7 */
+
+/* Bits 31..24 : Address prefix 7. */
+#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
+#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
+
+/* Bits 23..16 : Address prefix 6. */
+#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
+#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
+
+/* Bits 15..8 : Address prefix 5. */
+#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
+#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
+
+/* Bits 7..0 : Address prefix 4. */
+#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
+#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
+
+/* Register: RADIO_TXADDRESS */
+/* Description: Transmit address select */
+
+/* Bits 2..0 : Transmit address select */
+#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
+#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
+
+/* Register: RADIO_RXADDRESSES */
+/* Description: Receive address select */
+
+/* Bit 7 : Enable or disable reception on logical address 7. */
+#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable reception on logical address 6. */
+#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable reception on logical address 5. */
+#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable reception on logical address 4. */
+#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable reception on logical address 3. */
+#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable reception on logical address 2. */
+#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable reception on logical address 1. */
+#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable reception on logical address 0. */
+#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
+
+/* Register: RADIO_CRCCNF */
+/* Description: CRC configuration */
+
+/* Bits 9..8 : Include or exclude packet address field out of CRC calculation. */
+#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Msk (0x3UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
+#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
+#define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */
+
+/* Bits 1..0 : CRC length in number of bytes. */
+#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
+#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
+#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
+#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
+#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
+#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
+
+/* Register: RADIO_CRCPOLY */
+/* Description: CRC polynomial */
+
+/* Bits 23..0 : CRC polynomial */
+#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
+#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
+
+/* Register: RADIO_CRCINIT */
+/* Description: CRC initial value */
+
+/* Bits 23..0 : CRC initial value */
+#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
+#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
+
+/* Register: RADIO_TIFS */
+/* Description: Inter Frame Spacing in us */
+
+/* Bits 9..0 : Inter Frame Spacing in us */
+#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
+#define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
+
+/* Register: RADIO_RSSISAMPLE */
+/* Description: RSSI sample */
+
+/* Bits 6..0 : RSSI sample */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
+
+/* Register: RADIO_STATE */
+/* Description: Current radio state */
+
+/* Bits 3..0 : Current radio state */
+#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
+#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
+#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
+#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
+#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
+#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
+#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
+#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
+#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
+#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
+#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
+
+/* Register: RADIO_DATAWHITEIV */
+/* Description: Data whitening initial value */
+
+/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
+
+/* Register: RADIO_BCC */
+/* Description: Bit counter compare */
+
+/* Bits 31..0 : Bit counter compare */
+#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
+#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
+
+/* Register: RADIO_DAB */
+/* Description: Description collection[0]:  Device address base segment 0 */
+
+/* Bits 31..0 : Device address base segment 0 */
+#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
+#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
+
+/* Register: RADIO_DAP */
+/* Description: Description collection[0]:  Device address prefix 0 */
+
+/* Bits 15..0 : Device address prefix 0 */
+#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
+#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
+
+/* Register: RADIO_DACNF */
+/* Description: Device address match configuration */
+
+/* Bit 15 : TxAdd for device address 7 */
+#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
+#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
+
+/* Bit 14 : TxAdd for device address 6 */
+#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
+#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
+
+/* Bit 13 : TxAdd for device address 5 */
+#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
+#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
+
+/* Bit 12 : TxAdd for device address 4 */
+#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
+#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
+
+/* Bit 11 : TxAdd for device address 3 */
+#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
+#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
+
+/* Bit 10 : TxAdd for device address 2 */
+#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
+#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
+
+/* Bit 9 : TxAdd for device address 1 */
+#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
+#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
+
+/* Bit 8 : TxAdd for device address 0 */
+#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
+#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
+
+/* Bit 7 : Enable or disable device address matching using device address 7 */
+#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
+#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
+#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
+
+/* Bit 6 : Enable or disable device address matching using device address 6 */
+#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
+#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
+#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
+
+/* Bit 5 : Enable or disable device address matching using device address 5 */
+#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
+#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
+#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
+
+/* Bit 4 : Enable or disable device address matching using device address 4 */
+#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
+#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
+#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
+
+/* Bit 3 : Enable or disable device address matching using device address 3 */
+#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
+#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
+#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
+
+/* Bit 2 : Enable or disable device address matching using device address 2 */
+#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
+#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
+#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
+
+/* Bit 1 : Enable or disable device address matching using device address 1 */
+#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
+#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
+#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
+
+/* Bit 0 : Enable or disable device address matching using device address 0 */
+#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
+#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
+#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
+
+/* Register: RADIO_MODECNF0 */
+/* Description: Radio mode configuration register 0 */
+
+/* Bits 9..8 : Default TX value */
+#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
+#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
+#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
+#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
+#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
+
+/* Bit 0 : Radio ramp-up time */
+#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
+#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
+#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */
+#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */
+
+/* Register: RADIO_SFD */
+/* Description: IEEE 802.15.4 Start of Frame Delimiter */
+
+/* Bits 7..0 : IEEE 802.15.4 Start of Frame Delimiter */
+#define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */
+#define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */
+
+/* Register: RADIO_EDCNT */
+/* Description: IEEE 802.15.4 Energy Detect Loop Count */
+
+/* Bits 20..0 : IEEE 802.15.4 Energy Detect Loop Count */
+#define RADIO_EDCNT_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */
+#define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos) /*!< Bit mask of EDCNT field. */
+
+/* Register: RADIO_EDSAMPLE */
+/* Description: IEEE 802.15.4 Energy Detect Level */
+
+/* Bits 7..0 : IEEE 802.15.4 Energy Detect Level */
+#define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */
+#define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */
+
+/* Register: RADIO_CCACTRL */
+/* Description: IEEE 802.15.4 Clear Channel Assessment Control */
+
+/* Bits 31..24 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */
+#define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */
+#define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */
+
+/* Bits 23..16 : CCA Correlator Busy Threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. */
+#define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */
+#define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */
+
+/* Bits 15..8 : CCA Energy Busy Threshold. Used in all the CCA modes except CarrierMode. */
+#define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */
+#define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */
+
+/* Bits 2..0 : CCA Mode Of Operation */
+#define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */
+#define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */
+#define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy Above Threshold */
+#define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier Seen */
+#define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy Above Threshold AND Carrier Seen */
+#define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy Above Threshold OR Carrier Seen */
+#define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy Above Threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */
+
+/* Register: RADIO_POWER */
+/* Description: Peripheral power control */
+
+/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
+#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
+#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
+
+
+/* Peripheral: RNG */
+/* Description: Random Number Generator */
+
+/* Register: RNG_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 0 : Shortcut between VALRDY event and STOP task */
+#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: RNG_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to Enable interrupt for VALRDY event */
+#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
+#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
+#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
+
+/* Register: RNG_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to Disable interrupt for VALRDY event */
+#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
+#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
+#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
+
+/* Register: RNG_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 0 : Bias correction */
+#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
+#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
+
+/* Register: RNG_VALUE */
+/* Description: Output random number */
+
+/* Bits 7..0 : Generated random number */
+#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
+#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
+
+
+/* Peripheral: RTC */
+/* Description: Real time counter 0 */
+
+/* Register: RTC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
+#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
+#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
+#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
+#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */
+#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for TICK event */
+#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
+
+/* Register: RTC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
+#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
+#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
+#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
+#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */
+#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for TICK event */
+#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
+
+/* Register: RTC_EVTEN */
+/* Description: Enable or disable event routing */
+
+/* Bit 19 : Enable or disable event routing for COMPARE[3] event */
+#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable event routing for COMPARE[2] event */
+#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable event routing for COMPARE[1] event */
+#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
+
+/* Bit 16 : Enable or disable event routing for COMPARE[0] event */
+#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable event routing for OVRFLW event */
+#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable event routing for TICK event */
+#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
+
+/* Register: RTC_EVTENSET */
+/* Description: Enable event routing */
+
+/* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */
+#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */
+#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */
+#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */
+#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable event routing for OVRFLW event */
+#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable event routing for TICK event */
+#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
+
+/* Register: RTC_EVTENCLR */
+/* Description: Disable event routing */
+
+/* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */
+#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */
+#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */
+#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */
+#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable event routing for OVRFLW event */
+#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable event routing for TICK event */
+#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
+
+/* Register: RTC_COUNTER */
+/* Description: Current COUNTER value */
+
+/* Bits 23..0 : Counter value */
+#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
+#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
+
+/* Register: RTC_PRESCALER */
+/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */
+
+/* Bits 11..0 : Prescaler value */
+#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: RTC_CC */
+/* Description: Description collection[0]:  Compare register 0 */
+
+/* Bits 23..0 : Compare value */
+#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
+#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
+
+
+/* Peripheral: SAADC */
+/* Description: Analog to Digital Converter */
+
+/* Register: SAADC_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
+#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
+#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
+#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
+#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
+#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
+#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
+#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
+#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
+#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
+#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
+#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
+#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
+#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
+#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
+#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
+#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for STOPPED event */
+#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
+#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for RESULTDONE event */
+#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for DONE event */
+#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for END event */
+#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for STARTED event */
+#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Register: SAADC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */
+#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */
+#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */
+#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */
+#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */
+#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */
+#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */
+#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */
+#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */
+#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */
+#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */
+#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */
+#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */
+#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */
+#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */
+#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */
+#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for STOPPED event */
+#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */
+#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */
+#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for DONE event */
+#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for END event */
+#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for STARTED event */
+#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Register: SAADC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */
+#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */
+#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */
+#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */
+#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */
+#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */
+#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */
+#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */
+#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */
+#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */
+#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */
+#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */
+#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */
+#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */
+#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */
+#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */
+#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for STOPPED event */
+#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */
+#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */
+#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for DONE event */
+#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for END event */
+#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for STARTED event */
+#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Register: SAADC_STATUS */
+/* Description: Status */
+
+/* Bit 0 : Status */
+#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
+#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
+
+/* Register: SAADC_ENABLE */
+/* Description: Enable or disable ADC */
+
+/* Bit 0 : Enable or disable ADC */
+#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
+#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
+
+/* Register: SAADC_CH_PSELP */
+/* Description: Description cluster[0]:  Input positive pin selection for CH[0] */
+
+/* Bits 4..0 : Analog positive input channel */
+#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
+#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
+#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
+#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
+#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
+#define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0x11UL) /*!< VDDH/5 */
+
+/* Register: SAADC_CH_PSELN */
+/* Description: Description cluster[0]:  Input negative pin selection for CH[0] */
+
+/* Bits 4..0 : Analog negative input, enables differential channel */
+#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
+#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
+#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
+#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
+#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
+#define SAADC_CH_PSELN_PSELN_VDDHDIV5 (0x11UL) /*!< VDDH/5 */
+
+/* Register: SAADC_CH_CONFIG */
+/* Description: Description cluster[0]:  Input configuration for CH[0] */
+
+/* Bit 24 : Enable burst mode */
+#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
+#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
+#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
+#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
+
+/* Bit 20 : Enable differential mode */
+#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
+#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
+#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
+
+/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
+#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
+#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
+#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
+#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
+#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
+#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
+#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
+#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
+
+/* Bit 12 : Reference control */
+#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
+#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
+#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
+
+/* Bits 10..8 : Gain control */
+#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
+#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
+#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
+#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
+#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
+#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
+
+/* Bits 5..4 : Negative channel resistor control */
+#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
+#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
+#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
+#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
+#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
+#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
+
+/* Bits 1..0 : Positive channel resistor control */
+#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
+#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
+#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
+#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
+#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
+#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
+
+/* Register: SAADC_CH_LIMIT */
+/* Description: Description cluster[0]:  High/low limits for event monitoring a channel */
+
+/* Bits 31..16 : High level limit */
+#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
+#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
+
+/* Bits 15..0 : Low level limit */
+#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
+#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
+
+/* Register: SAADC_RESOLUTION */
+/* Description: Resolution configuration */
+
+/* Bits 2..0 : Set the resolution */
+#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
+#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
+#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
+#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
+#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
+#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
+
+/* Register: SAADC_OVERSAMPLE */
+/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
+
+/* Bits 3..0 : Oversample control */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
+
+/* Register: SAADC_SAMPLERATE */
+/* Description: Controls normal or continuous sample rate */
+
+/* Bit 12 : Select mode for sample rate control */
+#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
+#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
+#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
+
+/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
+#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
+#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
+
+/* Register: SAADC_RESULT_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SAADC_RESULT_MAXCNT */
+/* Description: Maximum number of buffer words to transfer */
+
+/* Bits 14..0 : Maximum number of buffer words to transfer */
+#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SAADC_RESULT_AMOUNT */
+/* Description: Number of buffer words transferred since last START */
+
+/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
+#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+
+/* Peripheral: SPI */
+/* Description: Serial Peripheral Interface 0 */
+
+/* Register: SPI_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for READY event */
+#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: SPI_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for READY event */
+#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: SPI_ENABLE */
+/* Description: Enable SPI */
+
+/* Bits 3..0 : Enable or disable SPI */
+#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
+#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
+
+/* Register: SPI_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPI_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPI_PSEL_SCK_CONNECT_Msk (0x1UL << SPI_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPI_PSEL_SCK_PORT_Msk (0x3UL << SPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPI_PSEL_SCK_PIN_Msk (0x1FUL << SPI_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPI_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPI_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPI_PSEL_MOSI_CONNECT_Msk (0x1UL << SPI_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPI_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPI_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPI_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPI_PSEL_MOSI_PORT_Msk (0x3UL << SPI_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPI_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPI_PSEL_MOSI_PIN_Msk (0x1FUL << SPI_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPI_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPI_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPI_PSEL_MISO_CONNECT_Msk (0x1UL << SPI_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPI_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPI_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPI_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPI_PSEL_MISO_PORT_Msk (0x3UL << SPI_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPI_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPI_PSEL_MISO_PIN_Msk (0x1FUL << SPI_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPI_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RX data received. Double buffered */
+#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: SPI_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TX data to send. Double buffered */
+#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: SPI_FREQUENCY */
+/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : SPI master data rate */
+#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
+#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
+#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
+
+/* Register: SPI_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+
+/* Peripheral: SPIM */
+/* Description: Serial Peripheral Interface Master with EasyDMA 0 */
+
+/* Register: SPIM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 17 : Shortcut between END event and START task */
+#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
+#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
+#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: SPIM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 19 : Write '1' to Enable interrupt for STARTED event */
+#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
+#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for END event */
+#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
+#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
+#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: SPIM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 19 : Write '1' to Disable interrupt for STARTED event */
+#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
+#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for END event */
+#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
+#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
+#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: SPIM_STALLSTAT */
+/* Description: Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. */
+
+/* Bit 1 : Stall status for EasyDMA RAM writes */
+#define SPIM_STALLSTAT_RX_Pos (1UL) /*!< Position of RX field. */
+#define SPIM_STALLSTAT_RX_Msk (0x1UL << SPIM_STALLSTAT_RX_Pos) /*!< Bit mask of RX field. */
+#define SPIM_STALLSTAT_RX_NOSTALL (0UL) /*!< No stall */
+#define SPIM_STALLSTAT_RX_STALL (1UL) /*!< A stall has occurred */
+
+/* Bit 0 : Stall status for EasyDMA RAM reads */
+#define SPIM_STALLSTAT_TX_Pos (0UL) /*!< Position of TX field. */
+#define SPIM_STALLSTAT_TX_Msk (0x1UL << SPIM_STALLSTAT_TX_Pos) /*!< Bit mask of TX field. */
+#define SPIM_STALLSTAT_TX_NOSTALL (0UL) /*!< No stall */
+#define SPIM_STALLSTAT_TX_STALL (1UL) /*!< A stall has occurred */
+
+/* Register: SPIM_ENABLE */
+/* Description: Enable SPIM */
+
+/* Bits 3..0 : Enable or disable SPIM */
+#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
+#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
+
+/* Register: SPIM_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPIM_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIM_PSEL_SCK_PORT_Msk (0x3UL << SPIM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPIM_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIM_PSEL_MOSI_PORT_Msk (0x3UL << SPIM_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPIM_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIM_PSEL_MISO_PORT_Msk (0x3UL << SPIM_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_CSN */
+/* Description: Pin select for CSN */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_CSN_CONNECT_Msk (0x1UL << SPIM_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPIM_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIM_PSEL_CSN_PORT_Msk (0x3UL << SPIM_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_CSN_PIN_Msk (0x1FUL << SPIM_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_FREQUENCY */
+/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : SPI master data rate */
+#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_M16 (0x0A000000UL) /*!< 16 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M32 (0x14000000UL) /*!< 32 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
+
+/* Register: SPIM_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 15..0 : Maximum number of bytes in receive buffer */
+#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 15..0 : Number of bytes transferred in the last transaction */
+#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIM_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_TXD_MAXCNT */
+/* Description: Number of bytes in transmit buffer */
+
+/* Bits 15..0 : Maximum number of bytes in transmit buffer */
+#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 15..0 : Number of bytes transferred in the last transaction */
+#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 1..0 : List type */
+#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIM_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+/* Register: SPIM_IFTIMING_RXDELAY */
+/* Description: Sample delay for input serial data on MISO */
+
+/* Bits 2..0 : Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. */
+#define SPIM_IFTIMING_RXDELAY_RXDELAY_Pos (0UL) /*!< Position of RXDELAY field. */
+#define SPIM_IFTIMING_RXDELAY_RXDELAY_Msk (0x7UL << SPIM_IFTIMING_RXDELAY_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */
+
+/* Register: SPIM_IFTIMING_CSNDUR */
+/* Description: Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions */
+
+/* Bits 7..0 : Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). */
+#define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL) /*!< Position of CSNDUR field. */
+#define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field. */
+
+/* Register: SPIM_ORC */
+/* Description: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT */
+
+/* Bits 7..0 : Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. */
+#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: SPIS */
+/* Description: SPI Slave 0 */
+
+/* Register: SPIS_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 2 : Shortcut between END event and ACQUIRE task */
+#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
+#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: SPIS_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */
+#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
+#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for END event */
+#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Register: SPIS_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */
+#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
+#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for END event */
+#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Register: SPIS_SEMSTAT */
+/* Description: Semaphore status register */
+
+/* Bits 1..0 : Semaphore status */
+#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
+#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
+#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
+#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
+
+/* Register: SPIS_STATUS */
+/* Description: Status from last transaction */
+
+/* Bit 1 : RX buffer overflow detected, and prevented */
+#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
+#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
+#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Bit 0 : TX buffer over-read detected, and prevented */
+#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
+#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
+#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Register: SPIS_ENABLE */
+/* Description: Enable SPI slave */
+
+/* Bits 3..0 : Enable or disable SPI slave */
+#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
+#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
+
+/* Register: SPIS_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPIS_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIS_PSEL_SCK_PORT_Msk (0x3UL << SPIS_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPIS_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIS_PSEL_MISO_PORT_Msk (0x3UL << SPIS_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPIS_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIS_PSEL_MOSI_PORT_Msk (0x3UL << SPIS_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_CSN */
+/* Description: Pin select for CSN signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define SPIS_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define SPIS_PSEL_CSN_PORT_Msk (0x3UL << SPIS_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_RXD_PTR */
+/* Description: RXD data pointer */
+
+/* Bits 31..0 : RXD data pointer */
+#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIS_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 7..0 : Maximum number of bytes in receive buffer */
+#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIS_RXD_AMOUNT */
+/* Description: Number of bytes received in last granted transaction */
+
+/* Bits 7..0 : Number of bytes received in the last granted transaction */
+#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIS_TXD_PTR */
+/* Description: TXD data pointer */
+
+/* Bits 31..0 : TXD data pointer */
+#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIS_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 7..0 : Maximum number of bytes in transmit buffer */
+#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIS_TXD_AMOUNT */
+/* Description: Number of bytes transmitted in last granted transaction */
+
+/* Bits 7..0 : Number of bytes transmitted in last granted transaction */
+#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIS_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+/* Register: SPIS_DEF */
+/* Description: Default character. Character clocked out in case of an ignored transaction. */
+
+/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
+#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
+#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
+
+/* Register: SPIS_ORC */
+/* Description: Over-read character */
+
+/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
+#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: TEMP */
+/* Description: Temperature Sensor */
+
+/* Register: TEMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to Enable interrupt for DATARDY event */
+#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
+#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
+#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
+
+/* Register: TEMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to Disable interrupt for DATARDY event */
+#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
+#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
+#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
+
+/* Register: TEMP_TEMP */
+/* Description: Temperature in degC (0.25deg steps) */
+
+/* Bits 31..0 : Temperature in degC (0.25deg steps) */
+#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
+#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
+
+/* Register: TEMP_A0 */
+/* Description: Slope of 1st piece wise linear function */
+
+/* Bits 11..0 : Slope of 1st piece wise linear function */
+#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
+#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
+
+/* Register: TEMP_A1 */
+/* Description: Slope of 2nd piece wise linear function */
+
+/* Bits 11..0 : Slope of 2nd piece wise linear function */
+#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
+#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
+
+/* Register: TEMP_A2 */
+/* Description: Slope of 3rd piece wise linear function */
+
+/* Bits 11..0 : Slope of 3rd piece wise linear function */
+#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
+#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
+
+/* Register: TEMP_A3 */
+/* Description: Slope of 4th piece wise linear function */
+
+/* Bits 11..0 : Slope of 4th piece wise linear function */
+#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
+#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
+
+/* Register: TEMP_A4 */
+/* Description: Slope of 5th piece wise linear function */
+
+/* Bits 11..0 : Slope of 5th piece wise linear function */
+#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
+#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
+
+/* Register: TEMP_A5 */
+/* Description: Slope of 6th piece wise linear function */
+
+/* Bits 11..0 : Slope of 6th piece wise linear function */
+#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
+#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
+
+/* Register: TEMP_B0 */
+/* Description: y-intercept of 1st piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 1st piece wise linear function */
+#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
+#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
+
+/* Register: TEMP_B1 */
+/* Description: y-intercept of 2nd piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 2nd piece wise linear function */
+#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
+#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
+
+/* Register: TEMP_B2 */
+/* Description: y-intercept of 3rd piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 3rd piece wise linear function */
+#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
+#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
+
+/* Register: TEMP_B3 */
+/* Description: y-intercept of 4th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 4th piece wise linear function */
+#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
+#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
+
+/* Register: TEMP_B4 */
+/* Description: y-intercept of 5th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 5th piece wise linear function */
+#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
+#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
+
+/* Register: TEMP_B5 */
+/* Description: y-intercept of 6th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 6th piece wise linear function */
+#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
+#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
+
+/* Register: TEMP_T0 */
+/* Description: End point of 1st piece wise linear function */
+
+/* Bits 7..0 : End point of 1st piece wise linear function */
+#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
+#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
+
+/* Register: TEMP_T1 */
+/* Description: End point of 2nd piece wise linear function */
+
+/* Bits 7..0 : End point of 2nd piece wise linear function */
+#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
+#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
+
+/* Register: TEMP_T2 */
+/* Description: End point of 3rd piece wise linear function */
+
+/* Bits 7..0 : End point of 3rd piece wise linear function */
+#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
+#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
+
+/* Register: TEMP_T3 */
+/* Description: End point of 4th piece wise linear function */
+
+/* Bits 7..0 : End point of 4th piece wise linear function */
+#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
+#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
+
+/* Register: TEMP_T4 */
+/* Description: End point of 5th piece wise linear function */
+
+/* Bits 7..0 : End point of 5th piece wise linear function */
+#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
+#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
+
+
+/* Peripheral: TIMER */
+/* Description: Timer/Counter 0 */
+
+/* Register: TIMER_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */
+#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
+#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
+#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */
+#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
+#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
+#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */
+#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */
+#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */
+#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */
+#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TIMER_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */
+#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
+#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
+#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */
+#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
+#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
+#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
+#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
+#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
+#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
+#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Register: TIMER_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */
+#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
+#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
+#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */
+#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
+#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
+#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
+#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
+#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
+#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
+#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Register: TIMER_STATUS */
+/* Description: Timer status */
+
+/* Bit 0 : Timer status */
+#define TIMER_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define TIMER_STATUS_STATUS_Msk (0x1UL << TIMER_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define TIMER_STATUS_STATUS_Stopped (0UL) /*!< Timer is stopped */
+#define TIMER_STATUS_STATUS_Started (1UL) /*!< Timer is started */
+
+/* Register: TIMER_MODE */
+/* Description: Timer mode selection */
+
+/* Bits 1..0 : Timer mode */
+#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
+#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
+#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
+
+/* Register: TIMER_BITMODE */
+/* Description: Configure the number of bits used by the TIMER */
+
+/* Bits 1..0 : Timer bit width */
+#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
+
+/* Register: TIMER_PRESCALER */
+/* Description: Timer prescaler register */
+
+/* Bits 3..0 : Prescaler value */
+#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: TIMER_CC */
+/* Description: Description collection[0]:  Capture/Compare register 0 */
+
+/* Bits 31..0 : Capture/Compare value */
+#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
+#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
+
+
+/* Peripheral: TWI */
+/* Description: I2C compatible Two-Wire Interface 0 */
+
+/* Register: TWI_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 1 : Shortcut between BB event and STOP task */
+#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between BB event and SUSPEND task */
+#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWI_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
+#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for BB event */
+#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */
+#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */
+#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWI_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
+#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for BB event */
+#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */
+#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */
+#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWI_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
+#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
+#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : NACK received after sending the address (write '1' to clear) */
+#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
+#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
+#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
+
+/* Register: TWI_ENABLE */
+/* Description: Enable TWI */
+
+/* Bits 3..0 : Enable or disable TWI */
+#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
+#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
+
+/* Register: TWI_PSEL_SCL */
+/* Description: Pin select for SCL */
+
+/* Bit 31 : Connection */
+#define TWI_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWI_PSEL_SCL_CONNECT_Msk (0x1UL << TWI_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWI_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWI_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define TWI_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define TWI_PSEL_SCL_PORT_Msk (0x3UL << TWI_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define TWI_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWI_PSEL_SCL_PIN_Msk (0x1FUL << TWI_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWI_PSEL_SDA */
+/* Description: Pin select for SDA */
+
+/* Bit 31 : Connection */
+#define TWI_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWI_PSEL_SDA_CONNECT_Msk (0x1UL << TWI_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWI_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWI_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define TWI_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define TWI_PSEL_SDA_PORT_Msk (0x3UL << TWI_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define TWI_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWI_PSEL_SDA_PIN_Msk (0x1FUL << TWI_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWI_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RXD register */
+#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: TWI_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TXD register */
+#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: TWI_FREQUENCY */
+/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : TWI master clock frequency */
+#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
+#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
+
+/* Register: TWI_ADDRESS */
+/* Description: Address used in the TWI transfer */
+
+/* Bits 6..0 : Address used in the TWI transfer */
+#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+
+/* Peripheral: TWIM */
+/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
+
+/* Register: TWIM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 12 : Shortcut between LASTRX event and STOP task */
+#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
+#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
+#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 10 : Shortcut between LASTRX event and STARTTX task */
+#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
+#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
+#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 9 : Shortcut between LASTTX event and STOP task */
+#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
+#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
+#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 7 : Shortcut between LASTTX event and STARTRX task */
+#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
+#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
+#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWIM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 24 : Enable or disable interrupt for LASTTX event */
+#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 23 : Enable or disable interrupt for LASTRX event */
+#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
+#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
+#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for SUSPENDED event */
+#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for ERROR event */
+#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: TWIM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 24 : Write '1' to Enable interrupt for LASTTX event */
+#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
+
+/* Bit 23 : Write '1' to Enable interrupt for LASTRX event */
+#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
+#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
+#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
+#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWIM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 24 : Write '1' to Disable interrupt for LASTTX event */
+#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
+
+/* Bit 23 : Write '1' to Disable interrupt for LASTRX event */
+#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
+#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
+#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
+#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWIM_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
+#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 1 : NACK received after sending the address (write '1' to clear) */
+#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 0 : Overrun error */
+#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
+
+/* Register: TWIM_ENABLE */
+/* Description: Enable TWIM */
+
+/* Bits 3..0 : Enable or disable TWIM */
+#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
+#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
+
+/* Register: TWIM_PSEL_SCL */
+/* Description: Pin select for SCL signal */
+
+/* Bit 31 : Connection */
+#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define TWIM_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define TWIM_PSEL_SCL_PORT_Msk (0x3UL << TWIM_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIM_PSEL_SDA */
+/* Description: Pin select for SDA signal */
+
+/* Bit 31 : Connection */
+#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define TWIM_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define TWIM_PSEL_SDA_PORT_Msk (0x3UL << TWIM_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIM_FREQUENCY */
+/* Description: TWI frequency. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : TWI master clock frequency */
+#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
+#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
+
+/* Register: TWIM_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIM_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 7..0 : Maximum number of bytes in receive buffer */
+#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIM_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
+#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIM_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIM_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIM_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 7..0 : Maximum number of bytes in transmit buffer */
+#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIM_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
+#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIM_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIM_ADDRESS */
+/* Description: Address used in the TWI transfer */
+
+/* Bits 6..0 : Address used in the TWI transfer */
+#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+
+/* Peripheral: TWIS */
+/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
+
+/* Register: TWIS_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 14 : Shortcut between READ event and SUSPEND task */
+#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
+#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
+#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 13 : Shortcut between WRITE event and SUSPEND task */
+#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
+#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
+#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWIS_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 26 : Enable or disable interrupt for READ event */
+#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable interrupt for WRITE event */
+#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
+#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
+#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for ERROR event */
+#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: TWIS_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 26 : Write '1' to Enable interrupt for READ event */
+#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to Enable interrupt for WRITE event */
+#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
+#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
+#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWIS_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 26 : Write '1' to Disable interrupt for READ event */
+#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to Disable interrupt for WRITE event */
+#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
+#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
+#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWIS_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 3 : TX buffer over-read detected, and prevented */
+#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
+#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
+
+/* Bit 2 : NACK sent after receiving a data byte */
+#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 0 : RX buffer overflow detected, and prevented */
+#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
+#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
+
+/* Register: TWIS_MATCH */
+/* Description: Status register indicating which address had a match */
+
+/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
+#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
+#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
+
+/* Register: TWIS_ENABLE */
+/* Description: Enable TWIS */
+
+/* Bits 3..0 : Enable or disable TWIS */
+#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
+#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
+
+/* Register: TWIS_PSEL_SCL */
+/* Description: Pin select for SCL signal */
+
+/* Bit 31 : Connection */
+#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define TWIS_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define TWIS_PSEL_SCL_PORT_Msk (0x3UL << TWIS_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIS_PSEL_SDA */
+/* Description: Pin select for SDA signal */
+
+/* Bit 31 : Connection */
+#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define TWIS_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define TWIS_PSEL_SDA_PORT_Msk (0x3UL << TWIS_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIS_RXD_PTR */
+/* Description: RXD Data pointer */
+
+/* Bits 31..0 : RXD Data pointer */
+#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIS_RXD_MAXCNT */
+/* Description: Maximum number of bytes in RXD buffer */
+
+/* Bits 7..0 : Maximum number of bytes in RXD buffer */
+#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIS_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last RXD transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last RXD transaction */
+#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIS_TXD_PTR */
+/* Description: TXD Data pointer */
+
+/* Bits 31..0 : TXD Data pointer */
+#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIS_TXD_MAXCNT */
+/* Description: Maximum number of bytes in TXD buffer */
+
+/* Bits 7..0 : Maximum number of bytes in TXD buffer */
+#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIS_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last TXD transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last TXD transaction */
+#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIS_ADDRESS */
+/* Description: Description collection[0]:  TWI slave address 0 */
+
+/* Bits 6..0 : TWI slave address */
+#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+/* Register: TWIS_CONFIG */
+/* Description: Configuration register for the address match mechanism */
+
+/* Bit 1 : Enable or disable address matching on ADDRESS[1] */
+#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
+#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
+#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
+#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
+
+/* Bit 0 : Enable or disable address matching on ADDRESS[0] */
+#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
+#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
+#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
+#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
+
+/* Register: TWIS_ORC */
+/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
+
+/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
+#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: UART */
+/* Description: Universal Asynchronous Receiver/Transmitter */
+
+/* Register: UART_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between NCTS event and STOPRX task */
+#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
+#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between CTS event and STARTRX task */
+#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: UART_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 17 : Write '1' to Enable interrupt for RXTO event */
+#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
+#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
+#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for NCTS event */
+#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for CTS event */
+#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
+
+/* Register: UART_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 17 : Write '1' to Disable interrupt for RXTO event */
+#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
+#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
+#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for NCTS event */
+#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for CTS event */
+#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
+
+/* Register: UART_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 3 : Break condition */
+#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
+
+/* Bit 2 : Framing error occurred */
+#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : Parity error */
+#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
+
+/* Register: UART_ENABLE */
+/* Description: Enable UART */
+
+/* Bits 3..0 : Enable or disable UART */
+#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
+#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
+
+/* Register: UART_PSEL_RTS */
+/* Description: Pin select for RTS */
+
+/* Bit 31 : Connection */
+#define UART_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UART_PSEL_RTS_CONNECT_Msk (0x1UL << UART_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UART_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UART_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define UART_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UART_PSEL_RTS_PORT_Msk (0x3UL << UART_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UART_PSEL_RTS_PIN_Msk (0x1FUL << UART_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UART_PSEL_TXD */
+/* Description: Pin select for TXD */
+
+/* Bit 31 : Connection */
+#define UART_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UART_PSEL_TXD_CONNECT_Msk (0x1UL << UART_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UART_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UART_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define UART_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UART_PSEL_TXD_PORT_Msk (0x3UL << UART_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UART_PSEL_TXD_PIN_Msk (0x1FUL << UART_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UART_PSEL_CTS */
+/* Description: Pin select for CTS */
+
+/* Bit 31 : Connection */
+#define UART_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UART_PSEL_CTS_CONNECT_Msk (0x1UL << UART_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UART_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UART_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define UART_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UART_PSEL_CTS_PORT_Msk (0x3UL << UART_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UART_PSEL_CTS_PIN_Msk (0x1FUL << UART_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UART_PSEL_RXD */
+/* Description: Pin select for RXD */
+
+/* Bit 31 : Connection */
+#define UART_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UART_PSEL_RXD_CONNECT_Msk (0x1UL << UART_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UART_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UART_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define UART_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UART_PSEL_RXD_PORT_Msk (0x3UL << UART_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UART_PSEL_RXD_PIN_Msk (0x1FUL << UART_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UART_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RX data received in previous transfers, double buffered */
+#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: UART_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TX data to be transferred */
+#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: UART_BAUDRATE */
+/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : Baud rate */
+#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
+#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
+#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
+#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
+#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
+#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
+#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
+#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
+#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
+#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
+#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
+#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
+#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
+#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
+#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
+#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
+#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
+#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
+
+/* Register: UART_CONFIG */
+/* Description: Configuration of parity and hardware flow control */
+
+/* Bits 3..1 : Parity */
+#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
+#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
+
+/* Bit 0 : Hardware flow control */
+#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
+#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
+
+
+/* Peripheral: UARTE */
+/* Description: UART with EasyDMA 0 */
+
+/* Register: UARTE_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 6 : Shortcut between ENDRX event and STOPRX task */
+#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
+#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
+#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
+#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between ENDRX event and STARTRX task */
+#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
+#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
+#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: UARTE_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
+#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
+#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
+#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for RXTO event */
+#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for ERROR event */
+#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for ENDTX event */
+#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for TXDRDY event */
+#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for ENDRX event */
+#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for RXDRDY event */
+#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for NCTS event */
+#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for CTS event */
+#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
+
+/* Register: UARTE_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */
+#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
+#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
+#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for RXTO event */
+#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
+#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
+#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
+#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
+#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for NCTS event */
+#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for CTS event */
+#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
+
+/* Register: UARTE_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */
+#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
+#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
+#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for RXTO event */
+#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
+#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
+#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
+#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
+#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for NCTS event */
+#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for CTS event */
+#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
+
+/* Register: UARTE_ERRORSRC */
+/* Description: Error source Note : this register is read / write one to clear. */
+
+/* Bit 3 : Break condition */
+#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
+
+/* Bit 2 : Framing error occurred */
+#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : Parity error */
+#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
+
+/* Register: UARTE_ENABLE */
+/* Description: Enable UART */
+
+/* Bits 3..0 : Enable or disable UARTE */
+#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
+#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
+
+/* Register: UARTE_PSEL_RTS */
+/* Description: Pin select for RTS signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define UARTE_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UARTE_PSEL_RTS_PORT_Msk (0x3UL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_TXD */
+/* Description: Pin select for TXD signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define UARTE_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UARTE_PSEL_TXD_PORT_Msk (0x3UL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_CTS */
+/* Description: Pin select for CTS signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define UARTE_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UARTE_PSEL_CTS_PORT_Msk (0x3UL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_RXD */
+/* Description: Pin select for RXD signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number */
+#define UARTE_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UARTE_PSEL_RXD_PORT_Msk (0x3UL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_BAUDRATE */
+/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : Baud rate */
+#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
+#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
+#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
+
+/* Register: UARTE_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: UARTE_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 9..0 : Maximum number of bytes in receive buffer */
+#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: UARTE_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 9..0 : Number of bytes transferred in the last transaction */
+#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: UARTE_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: UARTE_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 9..0 : Maximum number of bytes in transmit buffer */
+#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: UARTE_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 9..0 : Number of bytes transferred in the last transaction */
+#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: UARTE_CONFIG */
+/* Description: Configuration of parity and hardware flow control */
+
+/* Bit 4 : Stop bits */
+#define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */
+#define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */
+#define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */
+#define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */
+
+/* Bits 3..1 : Parity */
+#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
+#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include even parity bit */
+
+/* Bit 0 : Hardware flow control */
+#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
+#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
+
+
+/* Peripheral: UICR */
+/* Description: User Information Configuration Registers */
+
+/* Register: UICR_NRFFW */
+/* Description: Description collection[0]:  Reserved for Nordic firmware design */
+
+/* Bits 31..0 : Reserved for Nordic firmware design */
+#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
+#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
+
+/* Register: UICR_NRFHW */
+/* Description: Description collection[0]:  Reserved for Nordic hardware design */
+
+/* Bits 31..0 : Reserved for Nordic hardware design */
+#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
+#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
+
+/* Register: UICR_CUSTOMER */
+/* Description: Description collection[0]:  Reserved for customer */
+
+/* Bits 31..0 : Reserved for customer */
+#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
+#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
+
+/* Register: UICR_PSELRESET */
+/* Description: Description collection[0]:  Mapping of the nRESET function */
+
+/* Bit 31 : Connection */
+#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
+#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 6..5 : Port number onto which nRESET is exposed */
+#define UICR_PSELRESET_PORT_Pos (5UL) /*!< Position of PORT field. */
+#define UICR_PSELRESET_PORT_Msk (0x3UL << UICR_PSELRESET_PORT_Pos) /*!< Bit mask of PORT field. */
+
+/* Bits 4..0 : Pin number of PORT onto which nRESET is exposed */
+#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UICR_APPROTECT */
+/* Description: Access port protection */
+
+/* Bits 7..0 : Enable or disable Access Port protection. */
+#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
+#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
+#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
+#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */
+
+/* Register: UICR_NFCPINS */
+/* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
+
+/* Bit 0 : Setting of pins dedicated to NFC functionality */
+#define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
+#define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
+#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */
+#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */
+
+/* Register: UICR_EXTSUPPLY */
+/* Description: Enable external circuitry to be supplied from VDD pin. Applicable in 'High voltage mode' only. */
+
+/* Bit 0 : Enable external circuitry to be supplied from VDD pin (output of REG0 stage). */
+#define UICR_EXTSUPPLY_EXTSUPPLY_Pos (0UL) /*!< Position of EXTSUPPLY field. */
+#define UICR_EXTSUPPLY_EXTSUPPLY_Msk (0x1UL << UICR_EXTSUPPLY_EXTSUPPLY_Pos) /*!< Bit mask of EXTSUPPLY field. */
+#define UICR_EXTSUPPLY_EXTSUPPLY_Disabled (0UL) /*!< No current can be drawn from the VDD pin. */
+#define UICR_EXTSUPPLY_EXTSUPPLY_Enabled (1UL) /*!< It is allowed to supply external circuitry from the VDD pin. */
+
+/* Register: UICR_REGOUT0 */
+/* Description: GPIO reference voltage / external output supply voltage in 'High voltage mode'. */
+
+/* Bits 2..0 : Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. */
+#define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */
+#define UICR_REGOUT0_VOUT_Msk (0x7UL << UICR_REGOUT0_VOUT_Pos) /*!< Bit mask of VOUT field. */
+#define UICR_REGOUT0_VOUT_1V8 (0UL) /*!< 1.8 V */
+#define UICR_REGOUT0_VOUT_2V1 (1UL) /*!< 2.1 V */
+#define UICR_REGOUT0_VOUT_2V4 (2UL) /*!< 2.4 V */
+#define UICR_REGOUT0_VOUT_2V7 (3UL) /*!< 2.7 V */
+#define UICR_REGOUT0_VOUT_3V0 (4UL) /*!< 3.0 V */
+#define UICR_REGOUT0_VOUT_3V3 (5UL) /*!< 3.3 V */
+#define UICR_REGOUT0_VOUT_DEFAULT (7UL) /*!< Default voltage: 1.8 V */
+
+
+/* Peripheral: USBD */
+/* Description: Universal Serial Bus device */
+
+/* Register: USBD_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between ENDEPOUT[0] event and EP0RCVOUT task */
+#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos (4UL) /*!< Position of ENDEPOUT0_EP0RCVOUT field. */
+#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos) /*!< Bit mask of ENDEPOUT0_EP0RCVOUT field. */
+#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0UL) /*!< Disable shortcut */
+#define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between ENDEPOUT[0] event and EP0STATUS task */
+#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos (3UL) /*!< Position of ENDEPOUT0_EP0STATUS field. */
+#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos) /*!< Bit mask of ENDEPOUT0_EP0STATUS field. */
+#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */
+#define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between EP0DATADONE event and EP0STATUS task */
+#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL) /*!< Position of EP0DATADONE_EP0STATUS field. */
+#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos) /*!< Bit mask of EP0DATADONE_EP0STATUS field. */
+#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */
+#define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between EP0DATADONE event and STARTEPOUT[0] task */
+#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos (1UL) /*!< Position of EP0DATADONE_STARTEPOUT0 field. */
+#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPOUT0 field. */
+#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0UL) /*!< Disable shortcut */
+#define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between EP0DATADONE event and STARTEPIN[0] task */
+#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos (0UL) /*!< Position of EP0DATADONE_STARTEPIN0 field. */
+#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPIN0 field. */
+#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0UL) /*!< Disable shortcut */
+#define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: USBD_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 25 : Enable or disable interrupt for ACCESSFAULT event */
+#define USBD_INTEN_ACCESSFAULT_Pos (25UL) /*!< Position of ACCESSFAULT field. */
+#define USBD_INTEN_ACCESSFAULT_Msk (0x1UL << USBD_INTEN_ACCESSFAULT_Pos) /*!< Bit mask of ACCESSFAULT field. */
+#define USBD_INTEN_ACCESSFAULT_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ACCESSFAULT_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : Enable or disable interrupt for EPDATA event */
+#define USBD_INTEN_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
+#define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
+#define USBD_INTEN_EPDATA_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_EPDATA_Enabled (1UL) /*!< Enable */
+
+/* Bit 23 : Enable or disable interrupt for EP0SETUP event */
+#define USBD_INTEN_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
+#define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
+#define USBD_INTEN_EP0SETUP_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_EP0SETUP_Enabled (1UL) /*!< Enable */
+
+/* Bit 22 : Enable or disable interrupt for USBEVENT event */
+#define USBD_INTEN_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
+#define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
+#define USBD_INTEN_USBEVENT_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_USBEVENT_Enabled (1UL) /*!< Enable */
+
+/* Bit 21 : Enable or disable interrupt for SOF event */
+#define USBD_INTEN_SOF_Pos (21UL) /*!< Position of SOF field. */
+#define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos) /*!< Bit mask of SOF field. */
+#define USBD_INTEN_SOF_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_SOF_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for ENDISOOUT event */
+#define USBD_INTEN_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
+#define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
+#define USBD_INTEN_ENDISOOUT_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDISOOUT_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for ENDEPOUT[7] event */
+#define USBD_INTEN_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
+#define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
+#define USBD_INTEN_ENDEPOUT7_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT7_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for ENDEPOUT[6] event */
+#define USBD_INTEN_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
+#define USBD_INTEN_ENDEPOUT6_Msk (0x1UL << USBD_INTEN_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
+#define USBD_INTEN_ENDEPOUT6_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT6_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for ENDEPOUT[5] event */
+#define USBD_INTEN_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
+#define USBD_INTEN_ENDEPOUT5_Msk (0x1UL << USBD_INTEN_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
+#define USBD_INTEN_ENDEPOUT5_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT5_Enabled (1UL) /*!< Enable */
+
+/* Bit 16 : Enable or disable interrupt for ENDEPOUT[4] event */
+#define USBD_INTEN_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
+#define USBD_INTEN_ENDEPOUT4_Msk (0x1UL << USBD_INTEN_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
+#define USBD_INTEN_ENDEPOUT4_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT4_Enabled (1UL) /*!< Enable */
+
+/* Bit 15 : Enable or disable interrupt for ENDEPOUT[3] event */
+#define USBD_INTEN_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
+#define USBD_INTEN_ENDEPOUT3_Msk (0x1UL << USBD_INTEN_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
+#define USBD_INTEN_ENDEPOUT3_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT3_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for ENDEPOUT[2] event */
+#define USBD_INTEN_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
+#define USBD_INTEN_ENDEPOUT2_Msk (0x1UL << USBD_INTEN_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
+#define USBD_INTEN_ENDEPOUT2_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT2_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for ENDEPOUT[1] event */
+#define USBD_INTEN_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
+#define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
+#define USBD_INTEN_ENDEPOUT1_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT1_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for ENDEPOUT[0] event */
+#define USBD_INTEN_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
+#define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
+#define USBD_INTEN_ENDEPOUT0_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPOUT0_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for ENDISOIN event */
+#define USBD_INTEN_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
+#define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
+#define USBD_INTEN_ENDISOIN_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDISOIN_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for EP0DATADONE event */
+#define USBD_INTEN_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
+#define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
+#define USBD_INTEN_EP0DATADONE_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_EP0DATADONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for ENDEPIN[7] event */
+#define USBD_INTEN_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
+#define USBD_INTEN_ENDEPIN7_Msk (0x1UL << USBD_INTEN_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
+#define USBD_INTEN_ENDEPIN7_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN7_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for ENDEPIN[6] event */
+#define USBD_INTEN_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
+#define USBD_INTEN_ENDEPIN6_Msk (0x1UL << USBD_INTEN_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
+#define USBD_INTEN_ENDEPIN6_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN6_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for ENDEPIN[5] event */
+#define USBD_INTEN_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
+#define USBD_INTEN_ENDEPIN5_Msk (0x1UL << USBD_INTEN_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
+#define USBD_INTEN_ENDEPIN5_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN5_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for ENDEPIN[4] event */
+#define USBD_INTEN_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
+#define USBD_INTEN_ENDEPIN4_Msk (0x1UL << USBD_INTEN_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
+#define USBD_INTEN_ENDEPIN4_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN4_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for ENDEPIN[3] event */
+#define USBD_INTEN_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
+#define USBD_INTEN_ENDEPIN3_Msk (0x1UL << USBD_INTEN_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
+#define USBD_INTEN_ENDEPIN3_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN3_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for ENDEPIN[2] event */
+#define USBD_INTEN_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
+#define USBD_INTEN_ENDEPIN2_Msk (0x1UL << USBD_INTEN_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
+#define USBD_INTEN_ENDEPIN2_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN2_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for ENDEPIN[1] event */
+#define USBD_INTEN_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
+#define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
+#define USBD_INTEN_ENDEPIN1_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN1_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for ENDEPIN[0] event */
+#define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
+#define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
+#define USBD_INTEN_ENDEPIN0_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_ENDEPIN0_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STARTED event */
+#define USBD_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */
+#define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define USBD_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for USBRESET event */
+#define USBD_INTEN_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
+#define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
+#define USBD_INTEN_USBRESET_Disabled (0UL) /*!< Disable */
+#define USBD_INTEN_USBRESET_Enabled (1UL) /*!< Enable */
+
+/* Register: USBD_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 25 : Write '1' to Enable interrupt for ACCESSFAULT event */
+#define USBD_INTENSET_ACCESSFAULT_Pos (25UL) /*!< Position of ACCESSFAULT field. */
+#define USBD_INTENSET_ACCESSFAULT_Msk (0x1UL << USBD_INTENSET_ACCESSFAULT_Pos) /*!< Bit mask of ACCESSFAULT field. */
+#define USBD_INTENSET_ACCESSFAULT_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ACCESSFAULT_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ACCESSFAULT_Set (1UL) /*!< Enable */
+
+/* Bit 24 : Write '1' to Enable interrupt for EPDATA event */
+#define USBD_INTENSET_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
+#define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
+#define USBD_INTENSET_EPDATA_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_EPDATA_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_EPDATA_Set (1UL) /*!< Enable */
+
+/* Bit 23 : Write '1' to Enable interrupt for EP0SETUP event */
+#define USBD_INTENSET_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
+#define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
+#define USBD_INTENSET_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_EP0SETUP_Set (1UL) /*!< Enable */
+
+/* Bit 22 : Write '1' to Enable interrupt for USBEVENT event */
+#define USBD_INTENSET_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
+#define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
+#define USBD_INTENSET_USBEVENT_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_USBEVENT_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_USBEVENT_Set (1UL) /*!< Enable */
+
+/* Bit 21 : Write '1' to Enable interrupt for SOF event */
+#define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */
+#define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */
+#define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_SOF_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for ENDISOOUT event */
+#define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
+#define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
+#define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDISOOUT_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for ENDEPOUT[7] event */
+#define USBD_INTENSET_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
+#define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
+#define USBD_INTENSET_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT7_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for ENDEPOUT[6] event */
+#define USBD_INTENSET_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
+#define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
+#define USBD_INTENSET_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT6_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for ENDEPOUT[5] event */
+#define USBD_INTENSET_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
+#define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
+#define USBD_INTENSET_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT5_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for ENDEPOUT[4] event */
+#define USBD_INTENSET_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
+#define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
+#define USBD_INTENSET_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT4_Set (1UL) /*!< Enable */
+
+/* Bit 15 : Write '1' to Enable interrupt for ENDEPOUT[3] event */
+#define USBD_INTENSET_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
+#define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
+#define USBD_INTENSET_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT3_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for ENDEPOUT[2] event */
+#define USBD_INTENSET_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
+#define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
+#define USBD_INTENSET_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT2_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to Enable interrupt for ENDEPOUT[1] event */
+#define USBD_INTENSET_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
+#define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
+#define USBD_INTENSET_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT1_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for ENDEPOUT[0] event */
+#define USBD_INTENSET_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
+#define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
+#define USBD_INTENSET_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPOUT0_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to Enable interrupt for ENDISOIN event */
+#define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
+#define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
+#define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDISOIN_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for EP0DATADONE event */
+#define USBD_INTENSET_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
+#define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
+#define USBD_INTENSET_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_EP0DATADONE_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ENDEPIN[7] event */
+#define USBD_INTENSET_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
+#define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
+#define USBD_INTENSET_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN7_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for ENDEPIN[6] event */
+#define USBD_INTENSET_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
+#define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
+#define USBD_INTENSET_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN6_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for ENDEPIN[5] event */
+#define USBD_INTENSET_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
+#define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
+#define USBD_INTENSET_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN5_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for ENDEPIN[4] event */
+#define USBD_INTENSET_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
+#define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
+#define USBD_INTENSET_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN4_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for ENDEPIN[3] event */
+#define USBD_INTENSET_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
+#define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
+#define USBD_INTENSET_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN3_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for ENDEPIN[2] event */
+#define USBD_INTENSET_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
+#define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
+#define USBD_INTENSET_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN2_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for ENDEPIN[1] event */
+#define USBD_INTENSET_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
+#define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
+#define USBD_INTENSET_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN1_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for ENDEPIN[0] event */
+#define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
+#define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
+#define USBD_INTENSET_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_ENDEPIN0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STARTED event */
+#define USBD_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */
+#define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define USBD_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for USBRESET event */
+#define USBD_INTENSET_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
+#define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
+#define USBD_INTENSET_USBRESET_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENSET_USBRESET_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENSET_USBRESET_Set (1UL) /*!< Enable */
+
+/* Register: USBD_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 25 : Write '1' to Disable interrupt for ACCESSFAULT event */
+#define USBD_INTENCLR_ACCESSFAULT_Pos (25UL) /*!< Position of ACCESSFAULT field. */
+#define USBD_INTENCLR_ACCESSFAULT_Msk (0x1UL << USBD_INTENCLR_ACCESSFAULT_Pos) /*!< Bit mask of ACCESSFAULT field. */
+#define USBD_INTENCLR_ACCESSFAULT_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ACCESSFAULT_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ACCESSFAULT_Clear (1UL) /*!< Disable */
+
+/* Bit 24 : Write '1' to Disable interrupt for EPDATA event */
+#define USBD_INTENCLR_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */
+#define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos) /*!< Bit mask of EPDATA field. */
+#define USBD_INTENCLR_EPDATA_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_EPDATA_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_EPDATA_Clear (1UL) /*!< Disable */
+
+/* Bit 23 : Write '1' to Disable interrupt for EP0SETUP event */
+#define USBD_INTENCLR_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */
+#define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */
+#define USBD_INTENCLR_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_EP0SETUP_Clear (1UL) /*!< Disable */
+
+/* Bit 22 : Write '1' to Disable interrupt for USBEVENT event */
+#define USBD_INTENCLR_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */
+#define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */
+#define USBD_INTENCLR_USBEVENT_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_USBEVENT_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_USBEVENT_Clear (1UL) /*!< Disable */
+
+/* Bit 21 : Write '1' to Disable interrupt for SOF event */
+#define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */
+#define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */
+#define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_SOF_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for ENDISOOUT event */
+#define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */
+#define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */
+#define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDISOOUT_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for ENDEPOUT[7] event */
+#define USBD_INTENCLR_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */
+#define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */
+#define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT7_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for ENDEPOUT[6] event */
+#define USBD_INTENCLR_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */
+#define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */
+#define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT6_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for ENDEPOUT[5] event */
+#define USBD_INTENCLR_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */
+#define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */
+#define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT5_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for ENDEPOUT[4] event */
+#define USBD_INTENCLR_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */
+#define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */
+#define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT4_Clear (1UL) /*!< Disable */
+
+/* Bit 15 : Write '1' to Disable interrupt for ENDEPOUT[3] event */
+#define USBD_INTENCLR_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */
+#define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */
+#define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT3_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for ENDEPOUT[2] event */
+#define USBD_INTENCLR_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */
+#define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */
+#define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT2_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to Disable interrupt for ENDEPOUT[1] event */
+#define USBD_INTENCLR_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */
+#define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */
+#define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT1_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for ENDEPOUT[0] event */
+#define USBD_INTENCLR_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */
+#define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */
+#define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPOUT0_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to Disable interrupt for ENDISOIN event */
+#define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */
+#define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */
+#define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDISOIN_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for EP0DATADONE event */
+#define USBD_INTENCLR_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */
+#define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */
+#define USBD_INTENCLR_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_EP0DATADONE_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ENDEPIN[7] event */
+#define USBD_INTENCLR_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */
+#define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */
+#define USBD_INTENCLR_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN7_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for ENDEPIN[6] event */
+#define USBD_INTENCLR_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */
+#define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */
+#define USBD_INTENCLR_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN6_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for ENDEPIN[5] event */
+#define USBD_INTENCLR_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */
+#define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */
+#define USBD_INTENCLR_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN5_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for ENDEPIN[4] event */
+#define USBD_INTENCLR_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */
+#define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */
+#define USBD_INTENCLR_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN4_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for ENDEPIN[3] event */
+#define USBD_INTENCLR_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */
+#define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */
+#define USBD_INTENCLR_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN3_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for ENDEPIN[2] event */
+#define USBD_INTENCLR_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */
+#define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */
+#define USBD_INTENCLR_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN2_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for ENDEPIN[1] event */
+#define USBD_INTENCLR_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */
+#define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */
+#define USBD_INTENCLR_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN1_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for ENDEPIN[0] event */
+#define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */
+#define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */
+#define USBD_INTENCLR_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_ENDEPIN0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STARTED event */
+#define USBD_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */
+#define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define USBD_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for USBRESET event */
+#define USBD_INTENCLR_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */
+#define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos) /*!< Bit mask of USBRESET field. */
+#define USBD_INTENCLR_USBRESET_Disabled (0UL) /*!< Read: Disabled */
+#define USBD_INTENCLR_USBRESET_Enabled (1UL) /*!< Read: Enabled */
+#define USBD_INTENCLR_USBRESET_Clear (1UL) /*!< Disable */
+
+/* Register: USBD_EVENTCAUSE */
+/* Description: Details on event that caused the USBEVENT event */
+
+/* Bit 11 : Wrapper has re-initialized SFRs to the proper values. MAC is ready for normal operation. Write '1' to clear. */
+#define USBD_EVENTCAUSE_READY_Pos (11UL) /*!< Position of READY field. */
+#define USBD_EVENTCAUSE_READY_Msk (0x1UL << USBD_EVENTCAUSE_READY_Pos) /*!< Bit mask of READY field. */
+#define USBD_EVENTCAUSE_READY_NotDetected (0UL) /*!< USBEVENT was not issued due to USBD peripheral ready */
+#define USBD_EVENTCAUSE_READY_Ready (1UL) /*!< USBD peripheral is ready */
+
+/* Bit 9 : Signals that a RESUME condition (K state or activity restart) has been detected on the USB lines. Write '1' to clear. */
+#define USBD_EVENTCAUSE_RESUME_Pos (9UL) /*!< Position of RESUME field. */
+#define USBD_EVENTCAUSE_RESUME_Msk (0x1UL << USBD_EVENTCAUSE_RESUME_Pos) /*!< Bit mask of RESUME field. */
+#define USBD_EVENTCAUSE_RESUME_NotDetected (0UL) /*!< Resume not detected */
+#define USBD_EVENTCAUSE_RESUME_Detected (1UL) /*!< Resume detected */
+
+/* Bit 8 : Signals that the USB lines have been seen idle long enough for the device to enter suspend. Write '1' to clear. */
+#define USBD_EVENTCAUSE_SUSPEND_Pos (8UL) /*!< Position of SUSPEND field. */
+#define USBD_EVENTCAUSE_SUSPEND_Msk (0x1UL << USBD_EVENTCAUSE_SUSPEND_Pos) /*!< Bit mask of SUSPEND field. */
+#define USBD_EVENTCAUSE_SUSPEND_NotDetected (0UL) /*!< Suspend not detected */
+#define USBD_EVENTCAUSE_SUSPEND_Detected (1UL) /*!< Suspend detected */
+
+/* Bit 0 : CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. */
+#define USBD_EVENTCAUSE_ISOOUTCRC_Pos (0UL) /*!< Position of ISOOUTCRC field. */
+#define USBD_EVENTCAUSE_ISOOUTCRC_Msk (0x1UL << USBD_EVENTCAUSE_ISOOUTCRC_Pos) /*!< Bit mask of ISOOUTCRC field. */
+#define USBD_EVENTCAUSE_ISOOUTCRC_NotDetected (0UL) /*!< No error detected */
+#define USBD_EVENTCAUSE_ISOOUTCRC_Detected (1UL) /*!< Error detected */
+
+/* Register: USBD_BUSSTATE */
+/* Description: Provides the logic state of the D+ and D- lines */
+
+/* Bit 1 : State of the D+ line */
+#define USBD_BUSSTATE_DP_Pos (1UL) /*!< Position of DP field. */
+#define USBD_BUSSTATE_DP_Msk (0x1UL << USBD_BUSSTATE_DP_Pos) /*!< Bit mask of DP field. */
+#define USBD_BUSSTATE_DP_Low (0UL) /*!< Low */
+#define USBD_BUSSTATE_DP_High (1UL) /*!< High */
+
+/* Bit 0 : State of the D- line */
+#define USBD_BUSSTATE_DM_Pos (0UL) /*!< Position of DM field. */
+#define USBD_BUSSTATE_DM_Msk (0x1UL << USBD_BUSSTATE_DM_Pos) /*!< Bit mask of DM field. */
+#define USBD_BUSSTATE_DM_Low (0UL) /*!< Low */
+#define USBD_BUSSTATE_DM_High (1UL) /*!< High */
+
+/* Register: USBD_HALTED_EPIN */
+/* Description: Description collection[0]:  IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
+
+/* Bits 15..0 : IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
+#define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */
+#define USBD_HALTED_EPIN_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPIN_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */
+#define USBD_HALTED_EPIN_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */
+#define USBD_HALTED_EPIN_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */
+
+/* Register: USBD_HALTED_EPOUT */
+/* Description: Description collection[0]:  OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
+
+/* Bits 15..0 : OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */
+#define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */
+#define USBD_HALTED_EPOUT_GETSTATUS_Msk (0xFFFFUL << USBD_HALTED_EPOUT_GETSTATUS_Pos) /*!< Bit mask of GETSTATUS field. */
+#define USBD_HALTED_EPOUT_GETSTATUS_NotHalted (0UL) /*!< Endpoint is not halted */
+#define USBD_HALTED_EPOUT_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */
+
+/* Register: USBD_EPSTATUS */
+/* Description: Provides information on which endpoint's EasyDMA registers have been captured */
+
+/* Bit 24 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT8_Pos (24UL) /*!< Position of EPOUT8 field. */
+#define USBD_EPSTATUS_EPOUT8_Msk (0x1UL << USBD_EPSTATUS_EPOUT8_Pos) /*!< Bit mask of EPOUT8 field. */
+#define USBD_EPSTATUS_EPOUT8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 23 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */
+#define USBD_EPSTATUS_EPOUT7_Msk (0x1UL << USBD_EPSTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */
+#define USBD_EPSTATUS_EPOUT7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 22 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */
+#define USBD_EPSTATUS_EPOUT6_Msk (0x1UL << USBD_EPSTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */
+#define USBD_EPSTATUS_EPOUT6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 21 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */
+#define USBD_EPSTATUS_EPOUT5_Msk (0x1UL << USBD_EPSTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */
+#define USBD_EPSTATUS_EPOUT5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 20 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */
+#define USBD_EPSTATUS_EPOUT4_Msk (0x1UL << USBD_EPSTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */
+#define USBD_EPSTATUS_EPOUT4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 19 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */
+#define USBD_EPSTATUS_EPOUT3_Msk (0x1UL << USBD_EPSTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */
+#define USBD_EPSTATUS_EPOUT3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 18 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */
+#define USBD_EPSTATUS_EPOUT2_Msk (0x1UL << USBD_EPSTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */
+#define USBD_EPSTATUS_EPOUT2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 17 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */
+#define USBD_EPSTATUS_EPOUT1_Msk (0x1UL << USBD_EPSTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */
+#define USBD_EPSTATUS_EPOUT1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 16 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPOUT0_Pos (16UL) /*!< Position of EPOUT0 field. */
+#define USBD_EPSTATUS_EPOUT0_Msk (0x1UL << USBD_EPSTATUS_EPOUT0_Pos) /*!< Bit mask of EPOUT0 field. */
+#define USBD_EPSTATUS_EPOUT0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPOUT0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 8 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN8_Pos (8UL) /*!< Position of EPIN8 field. */
+#define USBD_EPSTATUS_EPIN8_Msk (0x1UL << USBD_EPSTATUS_EPIN8_Pos) /*!< Bit mask of EPIN8 field. */
+#define USBD_EPSTATUS_EPIN8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 7 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */
+#define USBD_EPSTATUS_EPIN7_Msk (0x1UL << USBD_EPSTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */
+#define USBD_EPSTATUS_EPIN7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 6 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */
+#define USBD_EPSTATUS_EPIN6_Msk (0x1UL << USBD_EPSTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */
+#define USBD_EPSTATUS_EPIN6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 5 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */
+#define USBD_EPSTATUS_EPIN5_Msk (0x1UL << USBD_EPSTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */
+#define USBD_EPSTATUS_EPIN5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 4 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */
+#define USBD_EPSTATUS_EPIN4_Msk (0x1UL << USBD_EPSTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */
+#define USBD_EPSTATUS_EPIN4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 3 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */
+#define USBD_EPSTATUS_EPIN3_Msk (0x1UL << USBD_EPSTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */
+#define USBD_EPSTATUS_EPIN3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 2 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
+#define USBD_EPSTATUS_EPIN2_Msk (0x1UL << USBD_EPSTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */
+#define USBD_EPSTATUS_EPIN2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 1 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */
+#define USBD_EPSTATUS_EPIN1_Msk (0x1UL << USBD_EPSTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */
+#define USBD_EPSTATUS_EPIN1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Bit 0 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */
+#define USBD_EPSTATUS_EPIN0_Pos (0UL) /*!< Position of EPIN0 field. */
+#define USBD_EPSTATUS_EPIN0_Msk (0x1UL << USBD_EPSTATUS_EPIN0_Pos) /*!< Bit mask of EPIN0 field. */
+#define USBD_EPSTATUS_EPIN0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */
+#define USBD_EPSTATUS_EPIN0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */
+
+/* Register: USBD_EPDATASTATUS */
+/* Description: Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) */
+
+/* Bit 23 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */
+#define USBD_EPDATASTATUS_EPOUT7_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */
+#define USBD_EPDATASTATUS_EPOUT7_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT7_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 22 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */
+#define USBD_EPDATASTATUS_EPOUT6_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */
+#define USBD_EPDATASTATUS_EPOUT6_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT6_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 21 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */
+#define USBD_EPDATASTATUS_EPOUT5_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */
+#define USBD_EPDATASTATUS_EPOUT5_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT5_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 20 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */
+#define USBD_EPDATASTATUS_EPOUT4_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */
+#define USBD_EPDATASTATUS_EPOUT4_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT4_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 19 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */
+#define USBD_EPDATASTATUS_EPOUT3_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */
+#define USBD_EPDATASTATUS_EPOUT3_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT3_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 18 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */
+#define USBD_EPDATASTATUS_EPOUT2_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */
+#define USBD_EPDATASTATUS_EPOUT2_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT2_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 17 : Acknowledged data transfer on this OUT endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */
+#define USBD_EPDATASTATUS_EPOUT1_Msk (0x1UL << USBD_EPDATASTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */
+#define USBD_EPDATASTATUS_EPOUT1_NotStarted (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPOUT1_Started (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 7 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */
+#define USBD_EPDATASTATUS_EPIN7_Msk (0x1UL << USBD_EPDATASTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */
+#define USBD_EPDATASTATUS_EPIN7_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN7_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 6 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */
+#define USBD_EPDATASTATUS_EPIN6_Msk (0x1UL << USBD_EPDATASTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */
+#define USBD_EPDATASTATUS_EPIN6_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN6_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 5 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */
+#define USBD_EPDATASTATUS_EPIN5_Msk (0x1UL << USBD_EPDATASTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */
+#define USBD_EPDATASTATUS_EPIN5_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN5_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 4 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */
+#define USBD_EPDATASTATUS_EPIN4_Msk (0x1UL << USBD_EPDATASTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */
+#define USBD_EPDATASTATUS_EPIN4_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN4_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 3 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */
+#define USBD_EPDATASTATUS_EPIN3_Msk (0x1UL << USBD_EPDATASTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */
+#define USBD_EPDATASTATUS_EPIN3_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN3_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 2 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */
+#define USBD_EPDATASTATUS_EPIN2_Msk (0x1UL << USBD_EPDATASTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */
+#define USBD_EPDATASTATUS_EPIN2_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN2_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Bit 1 : Acknowledged data transfer on this IN endpoint. Write '1' to clear. */
+#define USBD_EPDATASTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */
+#define USBD_EPDATASTATUS_EPIN1_Msk (0x1UL << USBD_EPDATASTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */
+#define USBD_EPDATASTATUS_EPIN1_NotDone (0UL) /*!< No acknowledged data transfer on this endpoint */
+#define USBD_EPDATASTATUS_EPIN1_DataDone (1UL) /*!< Acknowledged data transfer on this endpoint has occurred */
+
+/* Register: USBD_USBADDR */
+/* Description: Device USB address */
+
+/* Bits 6..0 : Device USB address */
+#define USBD_USBADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */
+#define USBD_USBADDR_ADDR_Msk (0x7FUL << USBD_USBADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */
+
+/* Register: USBD_BMREQUESTTYPE */
+/* Description: SETUP data, byte 0, bmRequestType */
+
+/* Bit 7 : Data transfer direction */
+#define USBD_BMREQUESTTYPE_DIRECTION_Pos (7UL) /*!< Position of DIRECTION field. */
+#define USBD_BMREQUESTTYPE_DIRECTION_Msk (0x1UL << USBD_BMREQUESTTYPE_DIRECTION_Pos) /*!< Bit mask of DIRECTION field. */
+#define USBD_BMREQUESTTYPE_DIRECTION_HostToDevice (0UL) /*!< Host-to-device */
+#define USBD_BMREQUESTTYPE_DIRECTION_DeviceToHost (1UL) /*!< Device-to-host */
+
+/* Bits 6..5 : Data transfer type */
+#define USBD_BMREQUESTTYPE_TYPE_Pos (5UL) /*!< Position of TYPE field. */
+#define USBD_BMREQUESTTYPE_TYPE_Msk (0x3UL << USBD_BMREQUESTTYPE_TYPE_Pos) /*!< Bit mask of TYPE field. */
+#define USBD_BMREQUESTTYPE_TYPE_Standard (0UL) /*!< Standard */
+#define USBD_BMREQUESTTYPE_TYPE_Class (1UL) /*!< Class */
+#define USBD_BMREQUESTTYPE_TYPE_Vendor (2UL) /*!< Vendor */
+
+/* Bits 4..0 : Data transfer type */
+#define USBD_BMREQUESTTYPE_RECIPIENT_Pos (0UL) /*!< Position of RECIPIENT field. */
+#define USBD_BMREQUESTTYPE_RECIPIENT_Msk (0x1FUL << USBD_BMREQUESTTYPE_RECIPIENT_Pos) /*!< Bit mask of RECIPIENT field. */
+#define USBD_BMREQUESTTYPE_RECIPIENT_Device (0UL) /*!< Device */
+#define USBD_BMREQUESTTYPE_RECIPIENT_Interface (1UL) /*!< Interface */
+#define USBD_BMREQUESTTYPE_RECIPIENT_Endpoint (2UL) /*!< Endpoint */
+#define USBD_BMREQUESTTYPE_RECIPIENT_Other (3UL) /*!< Other */
+
+/* Register: USBD_BREQUEST */
+/* Description: SETUP data, byte 1, bRequest */
+
+/* Bits 7..0 : SETUP data, byte 1, bRequest. Values provides for standard requests only, user must implement Class and Vendor values. */
+#define USBD_BREQUEST_BREQUEST_Pos (0UL) /*!< Position of BREQUEST field. */
+#define USBD_BREQUEST_BREQUEST_Msk (0xFFUL << USBD_BREQUEST_BREQUEST_Pos) /*!< Bit mask of BREQUEST field. */
+#define USBD_BREQUEST_BREQUEST_STD_GET_STATUS (0UL) /*!< Standard request GET_STATUS */
+#define USBD_BREQUEST_BREQUEST_STD_CLEAR_FEATURE (1UL) /*!< Standard request CLEAR_FEATURE */
+#define USBD_BREQUEST_BREQUEST_STD_SET_FEATURE (3UL) /*!< Standard request SET_FEATURE */
+#define USBD_BREQUEST_BREQUEST_STD_SET_ADDRESS (5UL) /*!< Standard request SET_ADDRESS */
+#define USBD_BREQUEST_BREQUEST_STD_GET_DESCRIPTOR (6UL) /*!< Standard request GET_DESCRIPTOR */
+#define USBD_BREQUEST_BREQUEST_STD_SET_DESCRIPTOR (7UL) /*!< Standard request SET_DESCRIPTOR */
+#define USBD_BREQUEST_BREQUEST_STD_GET_CONFIGURATION (8UL) /*!< Standard request GET_CONFIGURATION */
+#define USBD_BREQUEST_BREQUEST_STD_SET_CONFIGURATION (9UL) /*!< Standard request SET_CONFIGURATION */
+#define USBD_BREQUEST_BREQUEST_STD_GET_INTERFACE (10UL) /*!< Standard request GET_INTERFACE */
+#define USBD_BREQUEST_BREQUEST_STD_SET_INTERFACE (11UL) /*!< Standard request SET_INTERFACE */
+#define USBD_BREQUEST_BREQUEST_STD_SYNCH_FRAME (12UL) /*!< Standard request SYNCH_FRAME */
+
+/* Register: USBD_WVALUEL */
+/* Description: SETUP data, byte 2, LSB of wValue */
+
+/* Bits 7..0 : SETUP data, byte 2, LSB of wValue */
+#define USBD_WVALUEL_WVALUEL_Pos (0UL) /*!< Position of WVALUEL field. */
+#define USBD_WVALUEL_WVALUEL_Msk (0xFFUL << USBD_WVALUEL_WVALUEL_Pos) /*!< Bit mask of WVALUEL field. */
+
+/* Register: USBD_WVALUEH */
+/* Description: SETUP data, byte 3, MSB of wValue */
+
+/* Bits 7..0 : SETUP data, byte 3, MSB of wValue */
+#define USBD_WVALUEH_WVALUEH_Pos (0UL) /*!< Position of WVALUEH field. */
+#define USBD_WVALUEH_WVALUEH_Msk (0xFFUL << USBD_WVALUEH_WVALUEH_Pos) /*!< Bit mask of WVALUEH field. */
+
+/* Register: USBD_WINDEXL */
+/* Description: SETUP data, byte 4, LSB of wIndex */
+
+/* Bits 7..0 : SETUP data, byte 4, LSB of wIndex */
+#define USBD_WINDEXL_WINDEXL_Pos (0UL) /*!< Position of WINDEXL field. */
+#define USBD_WINDEXL_WINDEXL_Msk (0xFFUL << USBD_WINDEXL_WINDEXL_Pos) /*!< Bit mask of WINDEXL field. */
+
+/* Register: USBD_WINDEXH */
+/* Description: SETUP data, byte 5, MSB of wIndex */
+
+/* Bits 7..0 : SETUP data, byte 5, MSB of wIndex */
+#define USBD_WINDEXH_WINDEXH_Pos (0UL) /*!< Position of WINDEXH field. */
+#define USBD_WINDEXH_WINDEXH_Msk (0xFFUL << USBD_WINDEXH_WINDEXH_Pos) /*!< Bit mask of WINDEXH field. */
+
+/* Register: USBD_WLENGTHL */
+/* Description: SETUP data, byte 6, LSB of wLength */
+
+/* Bits 7..0 : SETUP data, byte 6, LSB of wLength */
+#define USBD_WLENGTHL_WLENGTHL_Pos (0UL) /*!< Position of WLENGTHL field. */
+#define USBD_WLENGTHL_WLENGTHL_Msk (0xFFUL << USBD_WLENGTHL_WLENGTHL_Pos) /*!< Bit mask of WLENGTHL field. */
+
+/* Register: USBD_WLENGTHH */
+/* Description: SETUP data, byte 7, MSB of wLength */
+
+/* Bits 7..0 : SETUP data, byte 7, MSB of wLength */
+#define USBD_WLENGTHH_WLENGTHH_Pos (0UL) /*!< Position of WLENGTHH field. */
+#define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos) /*!< Bit mask of WLENGTHH field. */
+
+/* Register: USBD_SIZE_EPOUT */
+/* Description: Description collection[0]:  Amount of bytes received last in the data stage of this OUT endpoint */
+
+/* Bits 6..0 : Amount of bytes received last in the data stage of this OUT endpoint */
+#define USBD_SIZE_EPOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */
+#define USBD_SIZE_EPOUT_SIZE_Msk (0x7FUL << USBD_SIZE_EPOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */
+
+/* Register: USBD_SIZE_ISOOUT */
+/* Description: Amount of bytes received last on this iso OUT data endpoint */
+
+/* Bit 16 : Zero-length data packet received */
+#define USBD_SIZE_ISOOUT_ZERO_Pos (16UL) /*!< Position of ZERO field. */
+#define USBD_SIZE_ISOOUT_ZERO_Msk (0x1UL << USBD_SIZE_ISOOUT_ZERO_Pos) /*!< Bit mask of ZERO field. */
+#define USBD_SIZE_ISOOUT_ZERO_Normal (0UL) /*!< No zero-length data received, use value in SIZE */
+#define USBD_SIZE_ISOOUT_ZERO_ZeroData (1UL) /*!< Zero-length data received, ignore value in SIZE */
+
+/* Bits 9..0 : Amount of bytes received last on this iso OUT data endpoint */
+#define USBD_SIZE_ISOOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */
+#define USBD_SIZE_ISOOUT_SIZE_Msk (0x3FFUL << USBD_SIZE_ISOOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */
+
+/* Register: USBD_ENABLE */
+/* Description: Enable USB */
+
+/* Bit 0 : Enable USB */
+#define USBD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define USBD_ENABLE_ENABLE_Msk (0x1UL << USBD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define USBD_ENABLE_ENABLE_Disabled (0UL) /*!< USB peripheral is disabled */
+#define USBD_ENABLE_ENABLE_Enabled (1UL) /*!< USB peripheral is enabled */
+
+/* Register: USBD_USBPULLUP */
+/* Description: Control of the USB pull-up */
+
+/* Bit 0 : Control of the USB pull-up on the D+ line */
+#define USBD_USBPULLUP_CONNECT_Pos (0UL) /*!< Position of CONNECT field. */
+#define USBD_USBPULLUP_CONNECT_Msk (0x1UL << USBD_USBPULLUP_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define USBD_USBPULLUP_CONNECT_Disabled (0UL) /*!< Pull-up is disconnected */
+#define USBD_USBPULLUP_CONNECT_Enabled (1UL) /*!< Pull-up is connected to D+ */
+
+/* Register: USBD_DPDMVALUE */
+/* Description: State at which the DPDMDRIVE task will force D+ and D-. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). */
+
+/* Bits 4..0 : State at which the DPDMDRIVE task will force D+ and D- */
+#define USBD_DPDMVALUE_STATE_Pos (0UL) /*!< Position of STATE field. */
+#define USBD_DPDMVALUE_STATE_Msk (0x1FUL << USBD_DPDMVALUE_STATE_Pos) /*!< Bit mask of STATE field. */
+#define USBD_DPDMVALUE_STATE_Resume (1UL) /*!< D+ forced low, D- forced high (K state) for a timing pre-set in hardware (50 us or 5 ms, depending on bus state) */
+#define USBD_DPDMVALUE_STATE_J (2UL) /*!< D+ forced high, D- forced low (J state) */
+#define USBD_DPDMVALUE_STATE_K (4UL) /*!< D+ forced low, D- forced high (K state) */
+
+/* Register: USBD_DTOGGLE */
+/* Description: Data toggle control and status. */
+
+/* Bits 9..8 : Data toggle value */
+#define USBD_DTOGGLE_VALUE_Pos (8UL) /*!< Position of VALUE field. */
+#define USBD_DTOGGLE_VALUE_Msk (0x3UL << USBD_DTOGGLE_VALUE_Pos) /*!< Bit mask of VALUE field. */
+#define USBD_DTOGGLE_VALUE_Nop (0UL) /*!< No action on data toggle when writing the register with this value */
+#define USBD_DTOGGLE_VALUE_Data0 (1UL) /*!< Data toggle is DATA0 on endpoint set by EP and IO */
+#define USBD_DTOGGLE_VALUE_Data1 (2UL) /*!< Data toggle is DATA1 on endpoint set by EP and IO */
+
+/* Bit 7 : Selects IN or OUT endpoint */
+#define USBD_DTOGGLE_IO_Pos (7UL) /*!< Position of IO field. */
+#define USBD_DTOGGLE_IO_Msk (0x1UL << USBD_DTOGGLE_IO_Pos) /*!< Bit mask of IO field. */
+#define USBD_DTOGGLE_IO_Out (0UL) /*!< Selects OUT endpoint */
+#define USBD_DTOGGLE_IO_In (1UL) /*!< Selects IN endpoint */
+
+/* Bits 2..0 : Select bulk endpoint number */
+#define USBD_DTOGGLE_EP_Pos (0UL) /*!< Position of EP field. */
+#define USBD_DTOGGLE_EP_Msk (0x7UL << USBD_DTOGGLE_EP_Pos) /*!< Bit mask of EP field. */
+
+/* Register: USBD_EPINEN */
+/* Description: Endpoint IN enable */
+
+/* Bit 8 : Enable iso IN endpoint */
+#define USBD_EPINEN_ISOIN_Pos (8UL) /*!< Position of ISOIN field. */
+#define USBD_EPINEN_ISOIN_Msk (0x1UL << USBD_EPINEN_ISOIN_Pos) /*!< Bit mask of ISOIN field. */
+#define USBD_EPINEN_ISOIN_Disable (0UL) /*!< Disable iso IN endpoint 8 */
+#define USBD_EPINEN_ISOIN_Enable (1UL) /*!< Enable iso IN endpoint 8 */
+
+/* Bit 7 : Enable IN endpoint 7 */
+#define USBD_EPINEN_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define USBD_EPINEN_IN7_Msk (0x1UL << USBD_EPINEN_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define USBD_EPINEN_IN7_Disable (0UL) /*!< Disable endpoint IN 7 (no response to IN tokens) */
+#define USBD_EPINEN_IN7_Enable (1UL) /*!< Enable endpoint IN 7 (response to IN tokens) */
+
+/* Bit 6 : Enable IN endpoint 6 */
+#define USBD_EPINEN_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define USBD_EPINEN_IN6_Msk (0x1UL << USBD_EPINEN_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define USBD_EPINEN_IN6_Disable (0UL) /*!< Disable endpoint IN 6 (no response to IN tokens) */
+#define USBD_EPINEN_IN6_Enable (1UL) /*!< Enable endpoint IN 6 (response to IN tokens) */
+
+/* Bit 5 : Enable IN endpoint 5 */
+#define USBD_EPINEN_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define USBD_EPINEN_IN5_Msk (0x1UL << USBD_EPINEN_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define USBD_EPINEN_IN5_Disable (0UL) /*!< Disable endpoint IN 5 (no response to IN tokens) */
+#define USBD_EPINEN_IN5_Enable (1UL) /*!< Enable endpoint IN 5 (response to IN tokens) */
+
+/* Bit 4 : Enable IN endpoint 4 */
+#define USBD_EPINEN_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define USBD_EPINEN_IN4_Msk (0x1UL << USBD_EPINEN_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define USBD_EPINEN_IN4_Disable (0UL) /*!< Disable endpoint IN 4 (no response to IN tokens) */
+#define USBD_EPINEN_IN4_Enable (1UL) /*!< Enable endpoint IN 4 (response to IN tokens) */
+
+/* Bit 3 : Enable IN endpoint 3 */
+#define USBD_EPINEN_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define USBD_EPINEN_IN3_Msk (0x1UL << USBD_EPINEN_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define USBD_EPINEN_IN3_Disable (0UL) /*!< Disable endpoint IN 3 (no response to IN tokens) */
+#define USBD_EPINEN_IN3_Enable (1UL) /*!< Enable endpoint IN 3 (response to IN tokens) */
+
+/* Bit 2 : Enable IN endpoint 2 */
+#define USBD_EPINEN_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define USBD_EPINEN_IN2_Msk (0x1UL << USBD_EPINEN_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define USBD_EPINEN_IN2_Disable (0UL) /*!< Disable endpoint IN 2 (no response to IN tokens) */
+#define USBD_EPINEN_IN2_Enable (1UL) /*!< Enable endpoint IN 2 (response to IN tokens) */
+
+/* Bit 1 : Enable IN endpoint 1 */
+#define USBD_EPINEN_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define USBD_EPINEN_IN1_Msk (0x1UL << USBD_EPINEN_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define USBD_EPINEN_IN1_Disable (0UL) /*!< Disable endpoint IN 1 (no response to IN tokens) */
+#define USBD_EPINEN_IN1_Enable (1UL) /*!< Enable endpoint IN 1 (response to IN tokens) */
+
+/* Bit 0 : Enable IN endpoint 0 */
+#define USBD_EPINEN_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define USBD_EPINEN_IN0_Msk (0x1UL << USBD_EPINEN_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define USBD_EPINEN_IN0_Disable (0UL) /*!< Disable endpoint IN 0 (no response to IN tokens) */
+#define USBD_EPINEN_IN0_Enable (1UL) /*!< Enable endpoint IN 0 (response to IN tokens) */
+
+/* Register: USBD_EPOUTEN */
+/* Description: Endpoint OUT enable */
+
+/* Bit 8 : Enable iso OUT endpoint 8 */
+#define USBD_EPOUTEN_ISOOUT_Pos (8UL) /*!< Position of ISOOUT field. */
+#define USBD_EPOUTEN_ISOOUT_Msk (0x1UL << USBD_EPOUTEN_ISOOUT_Pos) /*!< Bit mask of ISOOUT field. */
+#define USBD_EPOUTEN_ISOOUT_Disable (0UL) /*!< Disable iso OUT endpoint 8 */
+#define USBD_EPOUTEN_ISOOUT_Enable (1UL) /*!< Enable iso OUT endpoint 8 */
+
+/* Bit 7 : Enable OUT endpoint 7 */
+#define USBD_EPOUTEN_OUT7_Pos (7UL) /*!< Position of OUT7 field. */
+#define USBD_EPOUTEN_OUT7_Msk (0x1UL << USBD_EPOUTEN_OUT7_Pos) /*!< Bit mask of OUT7 field. */
+#define USBD_EPOUTEN_OUT7_Disable (0UL) /*!< Disable endpoint OUT 7 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT7_Enable (1UL) /*!< Enable endpoint OUT 7 (response to OUT tokens) */
+
+/* Bit 6 : Enable OUT endpoint 6 */
+#define USBD_EPOUTEN_OUT6_Pos (6UL) /*!< Position of OUT6 field. */
+#define USBD_EPOUTEN_OUT6_Msk (0x1UL << USBD_EPOUTEN_OUT6_Pos) /*!< Bit mask of OUT6 field. */
+#define USBD_EPOUTEN_OUT6_Disable (0UL) /*!< Disable endpoint OUT 6 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT6_Enable (1UL) /*!< Enable endpoint OUT 6 (response to OUT tokens) */
+
+/* Bit 5 : Enable OUT endpoint 5 */
+#define USBD_EPOUTEN_OUT5_Pos (5UL) /*!< Position of OUT5 field. */
+#define USBD_EPOUTEN_OUT5_Msk (0x1UL << USBD_EPOUTEN_OUT5_Pos) /*!< Bit mask of OUT5 field. */
+#define USBD_EPOUTEN_OUT5_Disable (0UL) /*!< Disable endpoint OUT 5 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT5_Enable (1UL) /*!< Enable endpoint OUT 5 (response to OUT tokens) */
+
+/* Bit 4 : Enable OUT endpoint 4 */
+#define USBD_EPOUTEN_OUT4_Pos (4UL) /*!< Position of OUT4 field. */
+#define USBD_EPOUTEN_OUT4_Msk (0x1UL << USBD_EPOUTEN_OUT4_Pos) /*!< Bit mask of OUT4 field. */
+#define USBD_EPOUTEN_OUT4_Disable (0UL) /*!< Disable endpoint OUT 4 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT4_Enable (1UL) /*!< Enable endpoint OUT 4 (response to OUT tokens) */
+
+/* Bit 3 : Enable OUT endpoint 3 */
+#define USBD_EPOUTEN_OUT3_Pos (3UL) /*!< Position of OUT3 field. */
+#define USBD_EPOUTEN_OUT3_Msk (0x1UL << USBD_EPOUTEN_OUT3_Pos) /*!< Bit mask of OUT3 field. */
+#define USBD_EPOUTEN_OUT3_Disable (0UL) /*!< Disable endpoint OUT 3 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT3_Enable (1UL) /*!< Enable endpoint OUT 3 (response to OUT tokens) */
+
+/* Bit 2 : Enable OUT endpoint 2 */
+#define USBD_EPOUTEN_OUT2_Pos (2UL) /*!< Position of OUT2 field. */
+#define USBD_EPOUTEN_OUT2_Msk (0x1UL << USBD_EPOUTEN_OUT2_Pos) /*!< Bit mask of OUT2 field. */
+#define USBD_EPOUTEN_OUT2_Disable (0UL) /*!< Disable endpoint OUT 2 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT2_Enable (1UL) /*!< Enable endpoint OUT 2 (response to OUT tokens) */
+
+/* Bit 1 : Enable OUT endpoint 1 */
+#define USBD_EPOUTEN_OUT1_Pos (1UL) /*!< Position of OUT1 field. */
+#define USBD_EPOUTEN_OUT1_Msk (0x1UL << USBD_EPOUTEN_OUT1_Pos) /*!< Bit mask of OUT1 field. */
+#define USBD_EPOUTEN_OUT1_Disable (0UL) /*!< Disable endpoint OUT 1 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT1_Enable (1UL) /*!< Enable endpoint OUT 1 (response to OUT tokens) */
+
+/* Bit 0 : Enable OUT endpoint 0 */
+#define USBD_EPOUTEN_OUT0_Pos (0UL) /*!< Position of OUT0 field. */
+#define USBD_EPOUTEN_OUT0_Msk (0x1UL << USBD_EPOUTEN_OUT0_Pos) /*!< Bit mask of OUT0 field. */
+#define USBD_EPOUTEN_OUT0_Disable (0UL) /*!< Disable endpoint OUT 0 (no response to OUT tokens) */
+#define USBD_EPOUTEN_OUT0_Enable (1UL) /*!< Enable endpoint OUT 0 (response to OUT tokens) */
+
+/* Register: USBD_EPSTALL */
+/* Description: STALL endpoints */
+
+/* Bit 8 : Stall selected endpoint */
+#define USBD_EPSTALL_STALL_Pos (8UL) /*!< Position of STALL field. */
+#define USBD_EPSTALL_STALL_Msk (0x1UL << USBD_EPSTALL_STALL_Pos) /*!< Bit mask of STALL field. */
+#define USBD_EPSTALL_STALL_UnStall (0UL) /*!< Don't stall selected endpoint */
+#define USBD_EPSTALL_STALL_Stall (1UL) /*!< Stall selected endpoint */
+
+/* Bit 7 : Selects IN or OUT endpoint */
+#define USBD_EPSTALL_IO_Pos (7UL) /*!< Position of IO field. */
+#define USBD_EPSTALL_IO_Msk (0x1UL << USBD_EPSTALL_IO_Pos) /*!< Bit mask of IO field. */
+#define USBD_EPSTALL_IO_Out (0UL) /*!< Selects OUT endpoint */
+#define USBD_EPSTALL_IO_In (1UL) /*!< Selects IN endpoint */
+
+/* Bits 2..0 : Select endpoint number */
+#define USBD_EPSTALL_EP_Pos (0UL) /*!< Position of EP field. */
+#define USBD_EPSTALL_EP_Msk (0x7UL << USBD_EPSTALL_EP_Pos) /*!< Bit mask of EP field. */
+
+/* Register: USBD_ISOSPLIT */
+/* Description: Controls the split of ISO buffers */
+
+/* Bits 15..0 : Controls the split of ISO buffers */
+#define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */
+#define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */
+#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either iso IN or OUT */
+#define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */
+
+/* Register: USBD_FRAMECNTR */
+/* Description: Returns the current value of the start of frame counter */
+
+/* Bits 10..0 : Returns the current value of the start of frame counter */
+#define USBD_FRAMECNTR_FRAMECNTR_Pos (0UL) /*!< Position of FRAMECNTR field. */
+#define USBD_FRAMECNTR_FRAMECNTR_Msk (0x7FFUL << USBD_FRAMECNTR_FRAMECNTR_Pos) /*!< Bit mask of FRAMECNTR field. */
+
+/* Register: USBD_ISOINCONFIG */
+/* Description: Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
+
+/* Bit 0 : Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */
+#define USBD_ISOINCONFIG_RESPONSE_Pos (0UL) /*!< Position of RESPONSE field. */
+#define USBD_ISOINCONFIG_RESPONSE_Msk (0x1UL << USBD_ISOINCONFIG_RESPONSE_Pos) /*!< Bit mask of RESPONSE field. */
+#define USBD_ISOINCONFIG_RESPONSE_NoResp (0UL) /*!< Endpoint does not respond in that case */
+#define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data packet in that case */
+
+/* Register: USBD_EPIN_PTR */
+/* Description: Description cluster[0]:  Data pointer */
+
+/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */
+#define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: USBD_EPIN_MAXCNT */
+/* Description: Description cluster[0]:  Maximum number of bytes to transfer */
+
+/* Bits 6..0 : Maximum number of bytes to transfer */
+#define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: USBD_EPIN_AMOUNT */
+/* Description: Description cluster[0]:  Number of bytes transferred in the last transaction */
+
+/* Bits 6..0 : Number of bytes transferred in the last transaction */
+#define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define USBD_EPIN_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: USBD_ISOIN_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */
+#define USBD_ISOIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: USBD_ISOIN_MAXCNT */
+/* Description: Maximum number of bytes to transfer */
+
+/* Bits 9..0 : Maximum number of bytes to transfer */
+#define USBD_ISOIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define USBD_ISOIN_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: USBD_ISOIN_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 9..0 : Number of bytes transferred in the last transaction */
+#define USBD_ISOIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: USBD_EPOUT_PTR */
+/* Description: Description cluster[0]:  Data pointer */
+
+/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */
+#define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: USBD_EPOUT_MAXCNT */
+/* Description: Description cluster[0]:  Maximum number of bytes to transfer */
+
+/* Bits 6..0 : Maximum number of bytes to transfer */
+#define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: USBD_EPOUT_AMOUNT */
+/* Description: Description cluster[0]:  Number of bytes transferred in the last transaction */
+
+/* Bits 6..0 : Number of bytes transferred in the last transaction */
+#define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define USBD_EPOUT_AMOUNT_AMOUNT_Msk (0x7FUL << USBD_EPOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: USBD_ISOOUT_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */
+#define USBD_ISOOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: USBD_ISOOUT_MAXCNT */
+/* Description: Maximum number of bytes to transfer */
+
+/* Bits 9..0 : Maximum number of bytes to transfer */
+#define USBD_ISOOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define USBD_ISOOUT_MAXCNT_MAXCNT_Msk (0x3FFUL << USBD_ISOOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: USBD_ISOOUT_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 9..0 : Number of bytes transferred in the last transaction */
+#define USBD_ISOOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define USBD_ISOOUT_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOOUT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+
+/* Peripheral: WDT */
+/* Description: Watchdog Timer */
+
+/* Register: WDT_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */
+#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
+#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
+#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
+
+/* Register: WDT_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */
+#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
+#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
+#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
+
+/* Register: WDT_RUNSTATUS */
+/* Description: Run status */
+
+/* Bit 0 : Indicates whether or not the watchdog is running */
+#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
+#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
+
+/* Register: WDT_REQSTATUS */
+/* Description: Request status */
+
+/* Bit 7 : Request status for RR[7] register */
+#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
+
+/* Bit 6 : Request status for RR[6] register */
+#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
+
+/* Bit 5 : Request status for RR[5] register */
+#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
+
+/* Bit 4 : Request status for RR[4] register */
+#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
+
+/* Bit 3 : Request status for RR[3] register */
+#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
+
+/* Bit 2 : Request status for RR[2] register */
+#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
+
+/* Bit 1 : Request status for RR[1] register */
+#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
+
+/* Bit 0 : Request status for RR[0] register */
+#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
+
+/* Register: WDT_CRV */
+/* Description: Counter reload value */
+
+/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
+#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
+#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
+
+/* Register: WDT_RREN */
+/* Description: Enable register for reload request registers */
+
+/* Bit 7 : Enable or disable RR[7] register */
+#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
+#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
+
+/* Bit 6 : Enable or disable RR[6] register */
+#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
+#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
+
+/* Bit 5 : Enable or disable RR[5] register */
+#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
+#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
+
+/* Bit 4 : Enable or disable RR[4] register */
+#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
+#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
+
+/* Bit 3 : Enable or disable RR[3] register */
+#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
+#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
+
+/* Bit 2 : Enable or disable RR[2] register */
+#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
+#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
+
+/* Bit 1 : Enable or disable RR[1] register */
+#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
+#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
+
+/* Bit 0 : Enable or disable RR[0] register */
+#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
+#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
+
+/* Register: WDT_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
+#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
+#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
+#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
+#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
+
+/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
+#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
+#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
+
+/* Register: WDT_RR */
+/* Description: Description collection[0]:  Reload request 0 */
+
+/* Bits 31..0 : Reload request register */
+#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
+#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
+#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
+
+
+/*lint --flb "Leave library region" */
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52840_peripherals.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,248 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+#ifndef _NRF52840_PERIPHERALS_H
+#define _NRF52840_PERIPHERALS_H
+
+
+/* Floating Point Unit */
+#define FPU_PRESENT
+#define FPU_COUNT 1
+
+/* Systick timer */
+#define SYSTICK_PRESENT
+#define SYSTICK_COUNT 1
+
+/* Software Interrupts */
+#define SWI_PRESENT
+#define SWI_COUNT 6
+
+/* Memory Watch Unit */
+#define MWU_PRESENT
+#define MWU_COUNT 1
+
+/* GPIO */
+#define GPIO_PRESENT
+#define GPIO_COUNT 2
+
+#define P0_PIN_NUM 32
+#define P1_PIN_NUM 16
+
+/* ACL */
+#define ACL_PRESENT
+
+#define ACL_REGIONS_COUNT 8
+
+/* Radio */
+#define RADIO_PRESENT
+#define RADIO_COUNT 1
+
+/* Accelerated Address Resolver */
+#define AAR_PRESENT
+#define AAR_COUNT 1
+
+#define AAR_MAX_IRK_NUM 16
+
+/* AES Electronic CodeBook mode encryption */
+#define ECB_PRESENT
+#define ECB_COUNT 1
+
+/* AES CCM mode encryption */
+#define CCM_PRESENT
+#define CCM_COUNT 1
+
+/* NFC Tag */
+#define NFCT_PRESENT
+#define NFCT_COUNT 1
+
+/* Peripheral to Peripheral Interconnect */
+#define PPI_PRESENT
+#define PPI_COUNT 1
+
+#define PPI_CH_NUM 20
+#define PPI_GROUP_NUM 6
+#define PPI_FEATURE_FORKS_PRESENT
+
+/* Event Generator Unit */
+#define EGU_PRESENT
+#define EGU_COUNT 6
+
+#define EGU0_CH_NUM 16
+#define EGU1_CH_NUM 16
+#define EGU2_CH_NUM 16
+#define EGU3_CH_NUM 16
+#define EGU4_CH_NUM 16
+#define EGU5_CH_NUM 16
+
+/* Timer/Counter */
+#define TIMER_PRESENT
+#define TIMER_COUNT 5
+
+#define TIMER0_MAX_SIZE 32
+#define TIMER1_MAX_SIZE 32
+#define TIMER2_MAX_SIZE 32
+#define TIMER3_MAX_SIZE 32
+#define TIMER4_MAX_SIZE 32
+
+#define TIMER0_CC_NUM 4
+#define TIMER1_CC_NUM 4
+#define TIMER2_CC_NUM 4
+#define TIMER3_CC_NUM 6
+#define TIMER4_CC_NUM 6
+
+/* Real Time Counter */
+#define RTC_PRESENT
+#define RTC_COUNT 3
+
+#define RTC0_CC_NUM 3
+#define RTC1_CC_NUM 4
+#define RTC2_CC_NUM 4
+
+/* RNG */
+#define RNG_PRESENT
+#define RNG_COUNT 1
+
+/* Watchdog Timer */
+#define WDT_PRESENT
+#define WDT_COUNT 1
+
+/* Temperature Sensor */
+#define TEMP_PRESENT
+#define TEMP_COUNT 1
+
+/* Serial Peripheral Interface Master */
+#define SPI_PRESENT
+#define SPI_COUNT 3
+
+/* Serial Peripheral Interface Master with DMA */
+#define SPIM_PRESENT
+#define SPIM_COUNT 4
+
+#define SPIM0_MAX_DATARATE  8
+#define SPIM1_MAX_DATARATE  8
+#define SPIM2_MAX_DATARATE  8
+#define SPIM3_MAX_DATARATE  32
+
+#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT  0
+#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT  0
+#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT  0
+#define SPIM3_FEATURE_HARDWARE_CSN_PRESENT  1
+
+/* Serial Peripheral Interface Slave with DMA*/
+#define SPIS_PRESENT
+#define SPIS_COUNT 3
+
+/* Two Wire Interface Master */
+#define TWI_PRESENT
+#define TWI_COUNT 2
+
+/* Two Wire Interface Master with DMA */
+#define TWIM_PRESENT
+#define TWIM_COUNT 2
+
+/* Two Wire Interface Slave with DMA */
+#define TWIS_PRESENT
+#define TWIS_COUNT 2
+
+/* Universal Asynchronous Receiver-Transmitter */
+#define UART_PRESENT
+#define UART_COUNT 1
+
+/* Universal Asynchronous Receiver-Transmitter with DMA */
+#define UARTE_PRESENT
+#define UARTE_COUNT 2
+
+/* Quadrature Decoder */
+#define QDEC_PRESENT
+#define QDEC_COUNT 1
+
+/* Successive Approximation Analog to Digital Converter */
+#define SAADC_PRESENT
+#define SAADC_COUNT 1
+
+/* GPIO Tasks and Events */
+#define GPIOTE_PRESENT
+#define GPIOTE_COUNT 1
+
+#define GPIOTE_CH_NUM 8
+
+#define GPIOTE_FEATURE_SET_PRESENT
+#define GPIOTE_FEATURE_CLR_PRESENT
+
+/* Low Power Comparator */
+#define LPCOMP_PRESENT
+#define LPCOMP_COUNT 1
+
+#define LPCOMP_REFSEL_RESOLUTION 16
+
+#define LPCOMP_FEATURE_HYST_PRESENT
+
+/* Comparator */
+#define COMP_PRESENT
+#define COMP_COUNT 1
+
+/* Pulse Width Modulator */
+#define PWM_PRESENT
+#define PWM_COUNT 4
+
+#define PWM0_CH_NUM 4
+#define PWM1_CH_NUM 4
+#define PWM2_CH_NUM 4
+#define PWM3_CH_NUM 4
+
+/* Pulse Density Modulator */
+#define PDM_PRESENT
+#define PDM_COUNT 1
+
+/* Inter-IC Sound Interface */
+#define I2S_PRESENT
+#define I2S_COUNT 1
+
+/* Universal Serial Bus Device */
+#define USBD_PRESENT
+#define USBD_COUNT 1
+
+/* ARM TrustZone Cryptocell 310 */
+#define CRYPTOCELL_PRESENT
+#define CRYPTOCELL_COUNT 1
+
+/* Quad SPI */
+#define QSPI_PRESENT
+#define QSPI_COUNT 1
+
+#endif      // _NRF52840_PERIPHERALS_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52_bitfields.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,12650 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+#ifndef __NRF52_BITS_H
+#define __NRF52_BITS_H
+
+/*lint ++flb "Enter library region" */
+
+/* Peripheral: AAR */
+/* Description: Accelerated Address Resolver */
+
+/* Register: AAR_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
+#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */
+#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for END event */
+#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Register: AAR_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
+#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */
+#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for END event */
+#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Register: AAR_STATUS */
+/* Description: Resolution status */
+
+/* Bits 3..0 : The IRK that was used last time an address was resolved */
+#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+
+/* Register: AAR_ENABLE */
+/* Description: Enable AAR */
+
+/* Bits 1..0 : Enable or disable AAR */
+#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
+
+/* Register: AAR_NIRK */
+/* Description: Number of IRKs */
+
+/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
+#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
+#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
+
+/* Register: AAR_IRKPTR */
+/* Description: Pointer to IRK data structure */
+
+/* Bits 31..0 : Pointer to the IRK data structure */
+#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
+#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
+
+/* Register: AAR_ADDRPTR */
+/* Description: Pointer to the resolvable address */
+
+/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
+#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
+#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
+
+/* Register: AAR_SCRATCHPTR */
+/* Description: Pointer to data area used for temporary storage */
+
+/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */
+#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
+#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
+
+
+/* Peripheral: BPROT */
+/* Description: Block Protect */
+
+/* Register: BPROT_CONFIG0 */
+/* Description: Block protect configuration register 0 */
+
+/* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */
+#define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */
+#define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */
+#define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */
+#define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */
+#define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */
+#define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */
+#define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */
+#define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */
+#define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */
+#define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */
+#define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */
+#define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */
+#define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */
+#define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */
+#define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */
+#define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */
+#define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */
+#define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */
+#define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */
+#define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */
+#define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */
+#define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */
+#define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */
+#define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */
+#define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */
+#define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */
+#define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */
+#define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */
+#define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */
+#define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */
+#define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */
+#define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */
+#define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */
+#define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */
+#define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */
+#define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */
+#define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */
+#define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */
+#define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */
+#define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */
+#define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */
+#define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */
+#define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */
+#define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */
+#define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */
+#define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */
+#define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */
+#define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */
+#define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */
+#define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */
+#define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */
+#define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */
+#define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */
+#define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */
+#define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */
+#define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */
+#define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */
+#define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
+#define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */
+#define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */
+#define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */
+#define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */
+#define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */
+#define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */
+
+/* Register: BPROT_CONFIG1 */
+/* Description: Block protect configuration register 1 */
+
+/* Bit 31 : Enable protection for region 63. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */
+#define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */
+#define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 30 : Enable protection for region 62. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */
+#define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */
+#define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 29 : Enable protection for region 61. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */
+#define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */
+#define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 28 : Enable protection for region 60. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */
+#define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */
+#define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 27 : Enable protection for region 59. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */
+#define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */
+#define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 26 : Enable protection for region 58. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */
+#define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */
+#define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 25 : Enable protection for region 57. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */
+#define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */
+#define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 24 : Enable protection for region 56. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */
+#define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */
+#define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 23 : Enable protection for region 55. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */
+#define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */
+#define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 22 : Enable protection for region 54. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */
+#define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */
+#define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 21 : Enable protection for region 53. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */
+#define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */
+#define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 20 : Enable protection for region 52. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */
+#define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */
+#define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 19 : Enable protection for region 51. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */
+#define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */
+#define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 18 : Enable protection for region 50. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */
+#define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */
+#define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 17 : Enable protection for region 49. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */
+#define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */
+#define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 16 : Enable protection for region 48. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */
+#define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */
+#define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */
+#define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */
+#define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */
+#define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */
+#define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */
+#define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */
+#define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */
+#define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */
+#define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */
+#define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */
+#define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */
+#define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */
+#define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */
+#define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */
+#define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */
+#define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */
+#define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */
+#define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */
+#define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */
+#define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */
+#define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */
+#define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */
+#define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */
+#define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */
+#define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */
+#define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */
+#define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
+#define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */
+#define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */
+#define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */
+#define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */
+#define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */
+#define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
+
+/* Register: BPROT_DISABLEINDEBUG */
+/* Description: Disable protection mechanism in debug interface mode */
+
+/* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */
+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */
+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */
+
+/* Register: BPROT_CONFIG2 */
+/* Description: Block protect configuration register 2 */
+
+/* Bit 31 : Enable protection for region 95. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */
+#define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */
+#define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 30 : Enable protection for region 94. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */
+#define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */
+#define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 29 : Enable protection for region 93. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */
+#define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */
+#define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 28 : Enable protection for region 92. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */
+#define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */
+#define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 27 : Enable protection for region 91. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */
+#define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */
+#define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 26 : Enable protection for region 90. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */
+#define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */
+#define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 25 : Enable protection for region 89. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */
+#define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */
+#define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 24 : Enable protection for region 88. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */
+#define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */
+#define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 23 : Enable protection for region 87. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */
+#define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */
+#define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 22 : Enable protection for region 86. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */
+#define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */
+#define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 21 : Enable protection for region 85. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */
+#define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */
+#define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 20 : Enable protection for region 84. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */
+#define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */
+#define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 19 : Enable protection for region 83. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */
+#define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */
+#define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 18 : Enable protection for region 82. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */
+#define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */
+#define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 17 : Enable protection for region 81. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */
+#define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */
+#define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 16 : Enable protection for region 80. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */
+#define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */
+#define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 15 : Enable protection for region 79. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */
+#define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */
+#define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 14 : Enable protection for region 78. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */
+#define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */
+#define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 13 : Enable protection for region 77. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */
+#define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */
+#define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 12 : Enable protection for region 76. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */
+#define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */
+#define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 11 : Enable protection for region 75. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */
+#define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */
+#define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 10 : Enable protection for region 74. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */
+#define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */
+#define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 9 : Enable protection for region 73. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */
+#define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */
+#define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 8 : Enable protection for region 72. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */
+#define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */
+#define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 7 : Enable protection for region 71. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */
+#define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */
+#define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 6 : Enable protection for region 70. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */
+#define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */
+#define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 5 : Enable protection for region 69. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */
+#define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */
+#define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 4 : Enable protection for region 68. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */
+#define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */
+#define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 3 : Enable protection for region 67. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */
+#define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */
+#define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 2 : Enable protection for region 66. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */
+#define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */
+#define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 1 : Enable protection for region 65. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */
+#define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */
+#define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 0 : Enable protection for region 64. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */
+#define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */
+#define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */
+
+/* Register: BPROT_CONFIG3 */
+/* Description: Block protect configuration register 3 */
+
+/* Bit 31 : Enable protection for region 127. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */
+#define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */
+#define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 30 : Enable protection for region 126. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */
+#define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */
+#define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 29 : Enable protection for region 125. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */
+#define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */
+#define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 28 : Enable protection for region 124. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */
+#define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */
+#define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 27 : Enable protection for region 123. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */
+#define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */
+#define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 26 : Enable protection for region 122. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */
+#define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */
+#define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 25 : Enable protection for region 121. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */
+#define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */
+#define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 24 : Enable protection for region 120. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */
+#define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */
+#define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 23 : Enable protection for region 119. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */
+#define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */
+#define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 22 : Enable protection for region 118. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */
+#define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */
+#define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 21 : Enable protection for region 117. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */
+#define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */
+#define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 20 : Enable protection for region 116. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */
+#define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */
+#define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 19 : Enable protection for region 115. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */
+#define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */
+#define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 18 : Enable protection for region 114. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */
+#define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */
+#define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 17 : Enable protection for region 113. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */
+#define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */
+#define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 16 : Enable protection for region 112. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */
+#define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */
+#define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 15 : Enable protection for region 111. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */
+#define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */
+#define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 14 : Enable protection for region 110. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */
+#define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */
+#define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 13 : Enable protection for region 109. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */
+#define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */
+#define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 12 : Enable protection for region 108. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */
+#define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */
+#define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 11 : Enable protection for region 107. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */
+#define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */
+#define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 10 : Enable protection for region 106. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */
+#define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */
+#define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 9 : Enable protection for region 105. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */
+#define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */
+#define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 8 : Enable protection for region 104. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */
+#define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */
+#define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 7 : Enable protection for region 103. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */
+#define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */
+#define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 6 : Enable protection for region 102. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */
+#define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */
+#define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 5 : Enable protection for region 101. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */
+#define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */
+#define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 4 : Enable protection for region 100. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */
+#define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */
+#define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 3 : Enable protection for region 99. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */
+#define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */
+#define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 2 : Enable protection for region 98. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */
+#define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */
+#define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 1 : Enable protection for region 97. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */
+#define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */
+#define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 0 : Enable protection for region 96. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */
+#define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */
+#define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */
+
+
+/* Peripheral: CCM */
+/* Description: AES CCM Mode Encryption */
+
+/* Register: CCM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: CCM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for ERROR event */
+#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */
+#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */
+#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
+
+/* Register: CCM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for ERROR event */
+#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */
+#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */
+#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
+
+/* Register: CCM_MICSTATUS */
+/* Description: MIC check result */
+
+/* Bit 0 : The result of the MIC check performed during the previous decryption operation */
+#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
+#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
+
+/* Register: CCM_ENABLE */
+/* Description: Enable */
+
+/* Bits 1..0 : Enable or disable CCM */
+#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
+
+/* Register: CCM_MODE */
+/* Description: Operation mode */
+
+/* Bit 24 : Packet length configuration */
+#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
+#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
+#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */
+#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */
+
+/* Bit 16 : Data rate that the CCM shall run in synch with */
+#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
+#define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
+#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */
+#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */
+
+/* Bit 0 : The mode of operation to be used */
+#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
+#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
+
+/* Register: CCM_CNFPTR */
+/* Description: Pointer to data structure holding AES key and NONCE vector */
+
+/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
+#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
+#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
+
+/* Register: CCM_INPTR */
+/* Description: Input pointer */
+
+/* Bits 31..0 : Input pointer */
+#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
+#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
+
+/* Register: CCM_OUTPTR */
+/* Description: Output pointer */
+
+/* Bits 31..0 : Output pointer */
+#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
+#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
+
+/* Register: CCM_SCRATCHPTR */
+/* Description: Pointer to data area used for temporary storage */
+
+/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */
+#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
+#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
+
+
+/* Peripheral: CLOCK */
+/* Description: Clock control */
+
+/* Register: CLOCK_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 4 : Write '1' to Enable interrupt for CTTO event */
+#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for DONE event */
+#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */
+#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */
+#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
+
+/* Register: CLOCK_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 4 : Write '1' to Disable interrupt for CTTO event */
+#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for DONE event */
+#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
+
+/* Register: CLOCK_HFCLKRUN */
+/* Description: Status indicating that HFCLKSTART task has been triggered */
+
+/* Bit 0 : HFCLKSTART task triggered or not */
+#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
+#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
+
+/* Register: CLOCK_HFCLKSTAT */
+/* Description: HFCLK status */
+
+/* Bit 16 : HFCLK state */
+#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
+#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
+
+/* Bit 0 : Source of HFCLK */
+#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
+#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
+
+/* Register: CLOCK_LFCLKRUN */
+/* Description: Status indicating that LFCLKSTART task has been triggered */
+
+/* Bit 0 : LFCLKSTART task triggered or not */
+#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
+#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
+
+/* Register: CLOCK_LFCLKSTAT */
+/* Description: LFCLK status */
+
+/* Bit 16 : LFCLK state */
+#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
+#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
+
+/* Bits 1..0 : Source of LFCLK */
+#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
+#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
+
+/* Register: CLOCK_LFCLKSRCCOPY */
+/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
+
+/* Bits 1..0 : Clock source */
+#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
+#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
+
+/* Register: CLOCK_LFCLKSRC */
+/* Description: Clock source for the LFCLK */
+
+/* Bit 17 : Enable or disable external source for LFCLK */
+#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */
+#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */
+#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */
+#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */
+
+/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
+#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */
+#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
+#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */
+#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
+
+/* Bits 1..0 : Clock source */
+#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
+#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
+
+/* Register: CLOCK_CTIV */
+/* Description: Calibration timer interval */
+
+/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
+#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
+#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
+
+/* Register: CLOCK_TRACECONFIG */
+/* Description: Clocking options for the Trace Port debug interface */
+
+/* Bits 17..16 : Pin multiplexing of trace signals. */
+#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
+#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
+#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */
+#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */
+#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */
+
+/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */
+
+
+/* Peripheral: COMP */
+/* Description: Comparator */
+
+/* Register: COMP_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between CROSS event and STOP task */
+#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
+#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
+#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between UP event and STOP task */
+#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
+#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
+#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between DOWN event and STOP task */
+#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
+#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
+#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between READY event and STOP task */
+#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
+#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
+#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between READY event and SAMPLE task */
+#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
+#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
+#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: COMP_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 3 : Enable or disable interrupt for CROSS event */
+#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for UP event */
+#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
+#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
+#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for DOWN event */
+#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for READY event */
+#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
+#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
+#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
+
+/* Register: COMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 3 : Write '1' to Enable interrupt for CROSS event */
+#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for UP event */
+#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
+#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
+#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for DOWN event */
+#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: COMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 3 : Write '1' to Disable interrupt for CROSS event */
+#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for UP event */
+#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
+#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
+#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for DOWN event */
+#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: COMP_RESULT */
+/* Description: Compare result */
+
+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
+#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
+#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
+
+/* Register: COMP_ENABLE */
+/* Description: COMP enable */
+
+/* Bits 1..0 : Enable or disable COMP */
+#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
+
+/* Register: COMP_PSEL */
+/* Description: Pin select */
+
+/* Bits 2..0 : Analog pin select */
+#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
+#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
+
+/* Register: COMP_REFSEL */
+/* Description: Reference source select */
+
+/* Bits 2..0 : Reference select */
+#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
+#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
+#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
+#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
+#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
+#define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) */
+
+/* Register: COMP_EXTREFSEL */
+/* Description: External reference select */
+
+/* Bit 0 : External analog reference select */
+#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
+#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
+
+/* Register: COMP_TH */
+/* Description: Threshold configuration for hysteresis unit */
+
+/* Bits 13..8 : VUP = (THUP+1)/64*VREF */
+#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
+#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
+
+/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
+#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
+#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
+
+/* Register: COMP_MODE */
+/* Description: Mode configuration */
+
+/* Bit 8 : Main operation mode */
+#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
+#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
+#define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */
+#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
+
+/* Bits 1..0 : Speed and power mode */
+#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
+#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
+#define COMP_MODE_SP_Low (0UL) /*!< Low power mode */
+#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
+#define COMP_MODE_SP_High (2UL) /*!< High speed mode */
+
+/* Register: COMP_HYST */
+/* Description: Comparator hysteresis enable */
+
+/* Bit 0 : Comparator hysteresis */
+#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
+#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
+#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
+#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
+
+/* Register: COMP_ISOURCE */
+/* Description: Current source select on analog input */
+
+/* Bits 1..0 : Comparator hysteresis */
+#define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */
+#define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */
+#define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */
+#define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
+#define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
+#define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */
+
+
+/* Peripheral: ECB */
+/* Description: AES ECB Mode Encryption */
+
+/* Register: ECB_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */
+#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for ENDECB event */
+#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
+
+/* Register: ECB_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */
+#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for ENDECB event */
+#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
+
+/* Register: ECB_ECBDATAPTR */
+/* Description: ECB block encrypt memory pointers */
+
+/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
+#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
+#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
+
+
+/* Peripheral: EGU */
+/* Description: Event Generator Unit 0 */
+
+/* Register: EGU_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
+#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
+#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
+#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
+#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
+#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
+#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
+#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
+#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
+#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
+#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
+#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
+#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
+#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
+#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
+#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
+#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
+
+/* Register: EGU_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */
+#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */
+#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */
+#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */
+#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */
+#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */
+#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */
+#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */
+#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */
+#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */
+#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */
+#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */
+#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */
+#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */
+#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */
+#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */
+#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
+
+/* Register: EGU_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */
+#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */
+#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */
+#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */
+#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */
+#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */
+#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */
+#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */
+#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */
+#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */
+#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */
+#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */
+#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */
+#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */
+#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */
+#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */
+#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
+
+
+/* Peripheral: FICR */
+/* Description: Factory Information Configuration Registers */
+
+/* Register: FICR_CODEPAGESIZE */
+/* Description: Code memory page size */
+
+/* Bits 31..0 : Code memory page size */
+#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
+#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
+
+/* Register: FICR_CODESIZE */
+/* Description: Code memory size */
+
+/* Bits 31..0 : Code memory size in number of pages */
+#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
+#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
+
+/* Register: FICR_DEVICEID */
+/* Description: Description collection[0]:  Device identifier */
+
+/* Bits 31..0 : 64 bit unique device identifier */
+#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
+#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
+
+/* Register: FICR_ER */
+/* Description: Description collection[0]:  Encryption Root, word 0 */
+
+/* Bits 31..0 : Encryption Root, word n */
+#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
+#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
+
+/* Register: FICR_IR */
+/* Description: Description collection[0]:  Identity Root, word 0 */
+
+/* Bits 31..0 : Identity Root, word n */
+#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
+#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
+
+/* Register: FICR_DEVICEADDRTYPE */
+/* Description: Device address type */
+
+/* Bit 0 : Device address type */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
+
+/* Register: FICR_DEVICEADDR */
+/* Description: Description collection[0]:  Device address 0 */
+
+/* Bits 31..0 : 48 bit device address */
+#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
+#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
+
+/* Register: FICR_INFO_PART */
+/* Description: Part code */
+
+/* Bits 31..0 : Part code */
+#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
+#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
+#define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */
+#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_VARIANT */
+/* Description: Part Variant, Hardware version and Production configuration */
+
+/* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
+#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
+#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
+#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
+#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */
+#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
+#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
+#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_PACKAGE */
+/* Description: Package option */
+
+/* Bits 31..0 : Package option */
+#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */
+#define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */
+#define FICR_INFO_PACKAGE_PACKAGE_CI (0x2002UL) /*!< CIxx - 7x8 WLCSP 56 balls */
+#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_RAM */
+/* Description: RAM variant */
+
+/* Bits 31..0 : RAM variant */
+#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
+#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
+#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
+#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
+#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
+#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_FLASH */
+/* Description: Flash variant */
+
+/* Bits 31..0 : Flash variant */
+#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
+#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
+#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
+#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_TEMP_A0 */
+/* Description: Slope definition A0. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A1 */
+/* Description: Slope definition A1. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A2 */
+/* Description: Slope definition A2. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A3 */
+/* Description: Slope definition A3. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A4 */
+/* Description: Slope definition A4. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A5 */
+/* Description: Slope definition A5. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_B0 */
+/* Description: y-intercept B0. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B1 */
+/* Description: y-intercept B1. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B2 */
+/* Description: y-intercept B2. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B3 */
+/* Description: y-intercept B3. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B4 */
+/* Description: y-intercept B4. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B5 */
+/* Description: y-intercept B5. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_T0 */
+/* Description: Segment end T0. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T1 */
+/* Description: Segment end T1. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T2 */
+/* Description: Segment end T2. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T3 */
+/* Description: Segment end T3. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T4 */
+/* Description: Segment end T4. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_NFC_TAGHEADER0 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 3 */
+#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
+#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
+
+/* Bits 23..16 : Unique identifier byte 2 */
+#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
+#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
+
+/* Bits 15..8 : Unique identifier byte 1 */
+#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
+#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
+
+/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
+#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
+#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
+
+/* Register: FICR_NFC_TAGHEADER1 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 7 */
+#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
+#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
+
+/* Bits 23..16 : Unique identifier byte 6 */
+#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
+#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
+
+/* Bits 15..8 : Unique identifier byte 5 */
+#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
+#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
+
+/* Bits 7..0 : Unique identifier byte 4 */
+#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
+#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
+
+/* Register: FICR_NFC_TAGHEADER2 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 11 */
+#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
+#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
+
+/* Bits 23..16 : Unique identifier byte 10 */
+#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
+#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
+
+/* Bits 15..8 : Unique identifier byte 9 */
+#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
+#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
+
+/* Bits 7..0 : Unique identifier byte 8 */
+#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
+#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
+
+/* Register: FICR_NFC_TAGHEADER3 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 15 */
+#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
+#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
+
+/* Bits 23..16 : Unique identifier byte 14 */
+#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
+#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
+
+/* Bits 15..8 : Unique identifier byte 13 */
+#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
+#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
+
+/* Bits 7..0 : Unique identifier byte 12 */
+#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
+#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
+
+
+/* Peripheral: GPIOTE */
+/* Description: GPIO Tasks and Events */
+
+/* Register: GPIOTE_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 31 : Write '1' to Enable interrupt for PORT event */
+#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for IN[7] event */
+#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for IN[6] event */
+#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for IN[5] event */
+#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for IN[4] event */
+#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for IN[3] event */
+#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for IN[2] event */
+#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for IN[1] event */
+#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for IN[0] event */
+#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
+
+/* Register: GPIOTE_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 31 : Write '1' to Disable interrupt for PORT event */
+#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for IN[7] event */
+#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for IN[6] event */
+#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for IN[5] event */
+#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for IN[4] event */
+#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for IN[3] event */
+#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for IN[2] event */
+#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for IN[1] event */
+#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for IN[0] event */
+#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
+
+/* Register: GPIOTE_CONFIG */
+/* Description: Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
+
+/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
+#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
+#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
+
+/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
+#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
+#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
+#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
+#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
+
+/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
+#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
+#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
+
+/* Bits 1..0 : Mode */
+#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
+#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
+#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
+
+
+/* Peripheral: I2S */
+/* Description: Inter-IC Sound */
+
+/* Register: I2S_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */
+#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for STOPPED event */
+#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
+#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
+
+/* Register: I2S_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */
+#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for STOPPED event */
+#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */
+#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
+
+/* Register: I2S_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */
+#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for STOPPED event */
+#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */
+#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
+
+/* Register: I2S_ENABLE */
+/* Description: Enable I2S module. */
+
+/* Bit 0 : Enable I2S module. */
+#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: I2S_CONFIG_MODE */
+/* Description: I2S mode. */
+
+/* Bit 0 : I2S mode. */
+#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
+#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
+
+/* Register: I2S_CONFIG_RXEN */
+/* Description: Reception (RX) enable. */
+
+/* Bit 0 : Reception (RX) enable. */
+#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
+#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
+#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
+#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
+
+/* Register: I2S_CONFIG_TXEN */
+/* Description: Transmission (TX) enable. */
+
+/* Bit 0 : Transmission (TX) enable. */
+#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
+#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
+#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
+#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
+
+/* Register: I2S_CONFIG_MCKEN */
+/* Description: Master clock generator enable. */
+
+/* Bit 0 : Master clock generator enable. */
+#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
+#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
+#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
+#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
+
+/* Register: I2S_CONFIG_MCKFREQ */
+/* Description: Master clock generator frequency. */
+
+/* Bits 31..0 : Master clock generator frequency. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */
+
+/* Register: I2S_CONFIG_RATIO */
+/* Description: MCK / LRCK ratio. */
+
+/* Bits 3..0 : MCK / LRCK ratio. */
+#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
+#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
+#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
+#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
+#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
+#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
+#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
+#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
+#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
+#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
+#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
+
+/* Register: I2S_CONFIG_SWIDTH */
+/* Description: Sample width. */
+
+/* Bits 1..0 : Sample width. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
+
+/* Register: I2S_CONFIG_ALIGN */
+/* Description: Alignment of sample within a frame. */
+
+/* Bit 0 : Alignment of sample within a frame. */
+#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
+#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
+#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
+#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
+
+/* Register: I2S_CONFIG_FORMAT */
+/* Description: Frame format. */
+
+/* Bit 0 : Frame format. */
+#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
+#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
+#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
+#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
+
+/* Register: I2S_CONFIG_CHANNELS */
+/* Description: Enable channels. */
+
+/* Bits 1..0 : Enable channels. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
+
+/* Register: I2S_RXD_PTR */
+/* Description: Receive buffer RAM start address. */
+
+/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
+#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: I2S_TXD_PTR */
+/* Description: Transmit buffer RAM start address. */
+
+/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
+#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: I2S_RXTXD_MAXCNT */
+/* Description: Size of RXD and TXD buffers. */
+
+/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
+#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: I2S_PSEL_MCK */
+/* Description: Pin select for MCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SCK */
+/* Description: Pin select for SCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_LRCK */
+/* Description: Pin select for LRCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SDIN */
+/* Description: Pin select for SDIN signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SDOUT */
+/* Description: Pin select for SDOUT signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
+
+
+/* Peripheral: LPCOMP */
+/* Description: Low Power Comparator */
+
+/* Register: LPCOMP_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between CROSS event and STOP task */
+#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between UP event and STOP task */
+#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between DOWN event and STOP task */
+#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between READY event and STOP task */
+#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between READY event and SAMPLE task */
+#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: LPCOMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 3 : Write '1' to Enable interrupt for CROSS event */
+#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for UP event */
+#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for DOWN event */
+#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: LPCOMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 3 : Write '1' to Disable interrupt for CROSS event */
+#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for UP event */
+#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for DOWN event */
+#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: LPCOMP_RESULT */
+/* Description: Compare result */
+
+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
+#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-). */
+#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-). */
+
+/* Register: LPCOMP_ENABLE */
+/* Description: Enable LPCOMP */
+
+/* Bits 1..0 : Enable or disable LPCOMP */
+#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: LPCOMP_PSEL */
+/* Description: Input pin select */
+
+/* Bits 2..0 : Analog pin select */
+#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
+#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
+
+/* Register: LPCOMP_REFSEL */
+/* Description: Reference select */
+
+/* Bits 3..0 : Reference select */
+#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
+#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
+
+/* Register: LPCOMP_EXTREFSEL */
+/* Description: External reference select */
+
+/* Bit 0 : External analog reference select */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
+
+/* Register: LPCOMP_ANADETECT */
+/* Description: Analog detect configuration */
+
+/* Bits 1..0 : Analog detect configuration */
+#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
+#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
+#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
+
+/* Register: LPCOMP_HYST */
+/* Description: Comparator hysteresis enable */
+
+/* Bit 0 : Comparator hysteresis enable */
+#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
+#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
+#define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
+#define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */
+
+
+/* Peripheral: MWU */
+/* Description: Memory Watch Unit */
+
+/* Register: MWU_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
+#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
+#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */
+#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */
+#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */
+#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */
+#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
+#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
+#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
+#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
+#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
+#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */
+#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Register: MWU_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */
+#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */
+#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */
+#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */
+#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */
+#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */
+#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */
+#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */
+#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */
+#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */
+#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */
+#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */
+#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
+
+/* Register: MWU_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */
+#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */
+#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */
+#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */
+#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */
+#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */
+#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */
+#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */
+#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */
+#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */
+#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */
+#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */
+#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
+
+/* Register: MWU_NMIEN */
+/* Description: Enable or disable non-maskable interrupt */
+
+/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
+#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
+#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
+#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
+#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
+#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
+#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
+#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
+#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
+#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
+#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
+#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
+#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Register: MWU_NMIENSET */
+/* Description: Enable non-maskable interrupt */
+
+/* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */
+#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */
+#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */
+#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */
+#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */
+#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */
+#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */
+#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */
+#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */
+#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */
+#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */
+#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */
+#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
+
+/* Register: MWU_NMIENCLR */
+/* Description: Disable non-maskable interrupt */
+
+/* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */
+#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */
+#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */
+#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */
+#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */
+#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */
+#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */
+#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */
+#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */
+#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */
+#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */
+#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */
+#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
+
+/* Register: MWU_PERREGION_SUBSTATWA */
+/* Description: Description cluster[0]:  Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */
+
+/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
+#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
+#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
+#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
+#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
+#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
+#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
+#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
+#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
+#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
+#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
+#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
+#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
+#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
+#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
+#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
+#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
+#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
+#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
+#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
+#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
+#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
+#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
+#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
+#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
+#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
+#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
+#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
+#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
+#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
+#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
+#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
+#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
+#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
+#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
+#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
+#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
+#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
+#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
+#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
+#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
+#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
+#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
+#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
+#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
+#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
+#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
+#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
+#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
+#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
+#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
+#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
+#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
+#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
+#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
+#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
+#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
+#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
+#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
+#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
+#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
+#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
+#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
+#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
+#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Register: MWU_PERREGION_SUBSTATRA */
+/* Description: Description cluster[0]:  Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */
+
+/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
+#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
+#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
+#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
+#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
+#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
+#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
+#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
+#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
+#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
+#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
+#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
+#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
+#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
+#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
+#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
+#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
+#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
+#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
+#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
+#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
+#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
+#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
+#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
+#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
+#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
+#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
+#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
+#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
+#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
+#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
+#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
+#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
+#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
+#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
+#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
+#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
+#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
+#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
+#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
+#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
+#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
+#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
+#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
+#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
+#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
+#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
+#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
+#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
+#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
+#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
+#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
+#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
+#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
+#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
+#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
+#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
+#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
+#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
+#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
+#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
+#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
+#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
+#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
+#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Register: MWU_REGIONEN */
+/* Description: Enable/disable regions watch */
+
+/* Bit 27 : Enable/disable read access watch in PREGION[1] */
+#define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
+#define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
+#define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
+#define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 26 : Enable/disable write access watch in PREGION[1] */
+#define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
+#define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
+#define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
+#define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 25 : Enable/disable read access watch in PREGION[0] */
+#define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
+#define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
+#define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
+#define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 24 : Enable/disable write access watch in PREGION[0] */
+#define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
+#define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
+#define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
+#define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 7 : Enable/disable read access watch in region[3] */
+#define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
+#define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
+#define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 6 : Enable/disable write access watch in region[3] */
+#define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
+#define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
+#define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 5 : Enable/disable read access watch in region[2] */
+#define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
+#define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
+#define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 4 : Enable/disable write access watch in region[2] */
+#define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
+#define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
+#define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 3 : Enable/disable read access watch in region[1] */
+#define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
+#define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
+#define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 2 : Enable/disable write access watch in region[1] */
+#define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
+#define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
+#define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 1 : Enable/disable read access watch in region[0] */
+#define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
+#define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
+#define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 0 : Enable/disable write access watch in region[0] */
+#define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
+#define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
+#define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Register: MWU_REGIONENSET */
+/* Description: Enable regions watch */
+
+/* Bit 27 : Enable read access watch in PREGION[1] */
+#define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
+#define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
+#define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 26 : Enable write access watch in PREGION[1] */
+#define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
+#define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
+#define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 25 : Enable read access watch in PREGION[0] */
+#define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
+#define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
+#define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 24 : Enable write access watch in PREGION[0] */
+#define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
+#define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
+#define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 7 : Enable read access watch in region[3] */
+#define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
+#define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
+#define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 6 : Enable write access watch in region[3] */
+#define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
+#define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
+#define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 5 : Enable read access watch in region[2] */
+#define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
+#define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
+#define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 4 : Enable write access watch in region[2] */
+#define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
+#define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
+#define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 3 : Enable read access watch in region[1] */
+#define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
+#define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
+#define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 2 : Enable write access watch in region[1] */
+#define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
+#define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
+#define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 1 : Enable read access watch in region[0] */
+#define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
+#define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
+#define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 0 : Enable write access watch in region[0] */
+#define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
+#define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
+#define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Register: MWU_REGIONENCLR */
+/* Description: Disable regions watch */
+
+/* Bit 27 : Disable read access watch in PREGION[1] */
+#define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
+#define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
+#define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
+
+/* Bit 26 : Disable write access watch in PREGION[1] */
+#define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
+#define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
+#define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
+
+/* Bit 25 : Disable read access watch in PREGION[0] */
+#define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
+#define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
+#define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
+
+/* Bit 24 : Disable write access watch in PREGION[0] */
+#define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
+#define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
+#define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
+
+/* Bit 7 : Disable read access watch in region[3] */
+#define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
+#define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
+#define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 6 : Disable write access watch in region[3] */
+#define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
+#define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
+#define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Bit 5 : Disable read access watch in region[2] */
+#define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
+#define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
+#define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 4 : Disable write access watch in region[2] */
+#define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
+#define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
+#define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Bit 3 : Disable read access watch in region[1] */
+#define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
+#define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
+#define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 2 : Disable write access watch in region[1] */
+#define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
+#define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
+#define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Bit 1 : Disable read access watch in region[0] */
+#define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
+#define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
+#define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 0 : Disable write access watch in region[0] */
+#define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
+#define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
+#define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Register: MWU_REGION_START */
+/* Description: Description cluster[0]:  Start address for region 0 */
+
+/* Bits 31..0 : Start address for region */
+#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
+#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
+
+/* Register: MWU_REGION_END */
+/* Description: Description cluster[0]:  End address of region 0 */
+
+/* Bits 31..0 : End address of region. */
+#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
+#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
+
+/* Register: MWU_PREGION_START */
+/* Description: Description cluster[0]:  Reserved for future use */
+
+/* Bits 31..0 : Reserved for future use */
+#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
+#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
+
+/* Register: MWU_PREGION_END */
+/* Description: Description cluster[0]:  Reserved for future use */
+
+/* Bits 31..0 : Reserved for future use */
+#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
+#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
+
+/* Register: MWU_PREGION_SUBS */
+/* Description: Description cluster[0]:  Subregions of region 0 */
+
+/* Bit 31 : Include or exclude subregion 31 in region */
+#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
+#define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
+#define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
+
+/* Bit 30 : Include or exclude subregion 30 in region */
+#define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
+#define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
+#define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
+
+/* Bit 29 : Include or exclude subregion 29 in region */
+#define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
+#define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
+#define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
+
+/* Bit 28 : Include or exclude subregion 28 in region */
+#define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
+#define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
+#define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
+
+/* Bit 27 : Include or exclude subregion 27 in region */
+#define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
+#define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
+#define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
+
+/* Bit 26 : Include or exclude subregion 26 in region */
+#define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
+#define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
+#define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
+
+/* Bit 25 : Include or exclude subregion 25 in region */
+#define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
+#define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
+#define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
+
+/* Bit 24 : Include or exclude subregion 24 in region */
+#define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
+#define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
+#define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
+
+/* Bit 23 : Include or exclude subregion 23 in region */
+#define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
+#define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
+#define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
+
+/* Bit 22 : Include or exclude subregion 22 in region */
+#define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
+#define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
+#define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
+
+/* Bit 21 : Include or exclude subregion 21 in region */
+#define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
+#define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
+#define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
+
+/* Bit 20 : Include or exclude subregion 20 in region */
+#define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
+#define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
+#define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
+
+/* Bit 19 : Include or exclude subregion 19 in region */
+#define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
+#define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
+#define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
+
+/* Bit 18 : Include or exclude subregion 18 in region */
+#define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
+#define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
+#define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
+
+/* Bit 17 : Include or exclude subregion 17 in region */
+#define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
+#define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
+#define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
+
+/* Bit 16 : Include or exclude subregion 16 in region */
+#define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
+#define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
+#define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
+
+/* Bit 15 : Include or exclude subregion 15 in region */
+#define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
+#define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
+#define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
+
+/* Bit 14 : Include or exclude subregion 14 in region */
+#define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
+#define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
+#define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
+
+/* Bit 13 : Include or exclude subregion 13 in region */
+#define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
+#define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
+#define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
+
+/* Bit 12 : Include or exclude subregion 12 in region */
+#define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
+#define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
+#define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
+
+/* Bit 11 : Include or exclude subregion 11 in region */
+#define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
+#define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
+#define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
+
+/* Bit 10 : Include or exclude subregion 10 in region */
+#define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
+#define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
+#define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
+
+/* Bit 9 : Include or exclude subregion 9 in region */
+#define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
+#define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
+#define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
+
+/* Bit 8 : Include or exclude subregion 8 in region */
+#define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
+#define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
+#define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
+
+/* Bit 7 : Include or exclude subregion 7 in region */
+#define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
+#define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
+#define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
+
+/* Bit 6 : Include or exclude subregion 6 in region */
+#define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
+#define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
+#define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
+
+/* Bit 5 : Include or exclude subregion 5 in region */
+#define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
+#define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
+#define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
+
+/* Bit 4 : Include or exclude subregion 4 in region */
+#define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
+#define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
+#define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
+
+/* Bit 3 : Include or exclude subregion 3 in region */
+#define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
+#define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
+#define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
+
+/* Bit 2 : Include or exclude subregion 2 in region */
+#define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
+#define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
+#define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
+
+/* Bit 1 : Include or exclude subregion 1 in region */
+#define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
+#define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
+#define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
+
+/* Bit 0 : Include or exclude subregion 0 in region */
+#define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
+#define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
+#define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
+
+
+/* Peripheral: NFCT */
+/* Description: NFC-A compatible radio */
+
+/* Register: NFCT_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: NFCT_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 20 : Enable or disable interrupt for STARTED event */
+#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
+#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for SELECTED event */
+#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
+#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for COLLISION event */
+#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
+#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
+#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for ENDTX event */
+#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
+#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for ENDRX event */
+#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
+#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for RXERROR event */
+#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
+#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
+#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for ERROR event */
+#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
+#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */
+#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
+#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
+#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */
+#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
+#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
+#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */
+#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
+#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
+#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */
+#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
+#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
+#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for FIELDLOST event */
+#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
+#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
+#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
+#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
+#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
+#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for READY event */
+#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
+#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
+#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
+
+/* Register: NFCT_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 20 : Write '1' to Enable interrupt for STARTED event */
+#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
+#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for SELECTED event */
+#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
+#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for COLLISION event */
+#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
+#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
+#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for ENDTX event */
+#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
+#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to Enable interrupt for ENDRX event */
+#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
+#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for RXERROR event */
+#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
+#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
+#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for ERROR event */
+#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
+#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */
+#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
+#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
+#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */
+#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
+#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
+#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */
+#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
+#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
+#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */
+#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
+#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
+#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */
+#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
+#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
+#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */
+#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
+#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
+#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: NFCT_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 20 : Write '1' to Disable interrupt for STARTED event */
+#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
+#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for SELECTED event */
+#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
+#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for COLLISION event */
+#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
+#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
+#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for ENDTX event */
+#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
+#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to Disable interrupt for ENDRX event */
+#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
+#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for RXERROR event */
+#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
+#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
+#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for ERROR event */
+#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
+#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */
+#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
+#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
+#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */
+#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
+#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
+#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */
+#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
+#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
+#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */
+#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
+#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
+#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */
+#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
+#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
+#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */
+#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
+#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
+#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: NFCT_ERRORSTATUS */
+/* Description: NFC Error Status register */
+
+/* Bit 3 : Field level is too low at min load resistance */
+#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */
+#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */
+
+/* Bit 2 : Field level is too high at max load resistance */
+#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */
+#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */
+
+/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
+#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
+#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
+
+/* Register: NFCT_FRAMESTATUS_RX */
+/* Description: Result of last incoming frames */
+
+/* Bit 3 : Overrun detected */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
+
+/* Bit 2 : Parity status of received frame */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
+
+/* Bit 0 : No valid End of Frame detected */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
+
+/* Register: NFCT_CURRENTLOADCTRL */
+/* Description: Current value driven to the NFC Load Control */
+
+/* Bits 5..0 : Current value driven to the NFC Load Control */
+#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */
+#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */
+
+/* Register: NFCT_FIELDPRESENT */
+/* Description: Indicates the presence or not of a valid field */
+
+/* Bit 1 : Indicates if the low level has locked to the field */
+#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
+#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
+#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
+#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
+
+/* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
+
+/* Register: NFCT_FRAMEDELAYMIN */
+/* Description: Minimum frame delay */
+
+/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
+#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
+#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
+
+/* Register: NFCT_FRAMEDELAYMAX */
+/* Description: Maximum frame delay */
+
+/* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */
+#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
+#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
+
+/* Register: NFCT_FRAMEDELAYMODE */
+/* Description: Configuration register for the Frame Delay Timer */
+
+/* Bits 1..0 : Configuration register for the Frame Delay Timer */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
+
+/* Register: NFCT_PACKETPTR */
+/* Description: Packet pointer for TXD and RXD data storage in Data RAM */
+
+/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */
+#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: NFCT_MAXLEN */
+/* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */
+
+/* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */
+#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
+#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
+
+/* Register: NFCT_TXD_FRAMECONFIG */
+/* Description: Configuration of outgoing frames */
+
+/* Bit 4 : CRC mode for outgoing frames */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
+
+/* Bit 2 : Adding SoF or not in TX frames */
+#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
+#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
+#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */
+#define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */
+
+/* Bit 1 : Discarding unused bits in start or at end of a Frame */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */
+
+/* Bit 0 : Adding parity or not in the frame */
+#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
+#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */
+#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */
+
+/* Register: NFCT_TXD_AMOUNT */
+/* Description: Size of outgoing frame */
+
+/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
+#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
+#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
+
+/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
+#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
+#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
+
+/* Register: NFCT_RXD_FRAMECONFIG */
+/* Description: Configuration of incoming frames */
+
+/* Bit 4 : CRC mode for incoming frames */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
+
+/* Bit 2 : SoF expected or not in RX frames */
+#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
+#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
+#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */
+#define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */
+
+/* Bit 0 : Parity expected or not in RX frame */
+#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
+#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
+#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
+
+/* Register: NFCT_RXD_AMOUNT */
+/* Description: Size of last incoming frame */
+
+/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
+#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
+#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
+
+/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
+#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
+#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
+
+/* Register: NFCT_NFCID1_LAST */
+/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
+
+/* Bits 31..24 : NFCID1 byte W */
+#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
+#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
+
+/* Bits 23..16 : NFCID1 byte X */
+#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
+#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
+
+/* Bits 15..8 : NFCID1 byte Y */
+#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
+#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
+
+/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
+#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
+#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
+
+/* Register: NFCT_NFCID1_2ND_LAST */
+/* Description: Second last NFCID1 part (7 or 10 bytes ID) */
+
+/* Bits 23..16 : NFCID1 byte T */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
+
+/* Bits 15..8 : NFCID1 byte U */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
+
+/* Bits 7..0 : NFCID1 byte V */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
+
+/* Register: NFCT_NFCID1_3RD_LAST */
+/* Description: Third last NFCID1 part (10 bytes ID) */
+
+/* Bits 23..16 : NFCID1 byte Q */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
+
+/* Bits 15..8 : NFCID1 byte R */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
+
+/* Bits 7..0 : NFCID1 byte S */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
+
+/* Register: NFCT_SENSRES */
+/* Description: NFC-A SENS_RES auto-response settings */
+
+/* Bits 15..12 : Reserved for future use. Shall be 0. */
+#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
+#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
+
+/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
+#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
+#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
+
+/* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */
+#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
+#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
+
+/* Bit 5 : Reserved for future use. Shall be 0. */
+#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
+#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
+
+/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
+#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
+#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
+
+/* Register: NFCT_SELRES */
+/* Description: NFC-A SEL_RES auto-response settings */
+
+/* Bit 7 : Reserved for future use. Shall be 0. */
+#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
+#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
+
+/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
+#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
+#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
+
+/* Bits 4..3 : Reserved for future use. Shall be 0. */
+#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
+#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
+
+/* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */
+#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
+#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
+#define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */
+#define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */
+
+/* Bits 1..0 : Reserved for future use. Shall be 0. */
+#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
+#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
+
+
+/* Peripheral: NVMC */
+/* Description: Non Volatile Memory Controller */
+
+/* Register: NVMC_READY */
+/* Description: Ready flag */
+
+/* Bit 0 : NVMC is ready or busy */
+#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
+#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
+#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
+#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
+
+/* Register: NVMC_CONFIG */
+/* Description: Configuration register */
+
+/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
+#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
+#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
+#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
+#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
+#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
+
+/* Register: NVMC_ERASEPAGE */
+/* Description: Register for erasing a page in Code area */
+
+/* Bits 31..0 : Register for starting erase of a page in Code area */
+#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
+#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
+
+/* Register: NVMC_ERASEPCR1 */
+/* Description: Deprecated register -  Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
+
+/* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
+#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
+#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
+
+/* Register: NVMC_ERASEALL */
+/* Description: Register for erasing all non-volatile user memory */
+
+/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
+#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
+#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
+
+/* Register: NVMC_ERASEPCR0 */
+/* Description: Deprecated register -  Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
+
+/* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */
+#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
+#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
+
+/* Register: NVMC_ERASEUICR */
+/* Description: Register for erasing User Information Configuration Registers */
+
+/* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
+#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
+#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
+
+/* Register: NVMC_ICACHECNF */
+/* Description: I-Code cache configuration register. */
+
+/* Bit 8 : Cache profiling enable */
+#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
+#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
+#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
+#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
+
+/* Bit 0 : Cache enable */
+#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
+#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
+#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
+#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
+
+/* Register: NVMC_IHIT */
+/* Description: I-Code cache hit counter. */
+
+/* Bits 31..0 : Number of cache hits */
+#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
+#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
+
+/* Register: NVMC_IMISS */
+/* Description: I-Code cache miss counter. */
+
+/* Bits 31..0 : Number of cache misses */
+#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
+#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
+
+
+/* Peripheral: GPIO */
+/* Description: GPIO Port 1 */
+
+/* Register: GPIO_OUT */
+/* Description: Write GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
+
+/* Register: GPIO_OUTSET */
+/* Description: Set individual bits in GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Register: GPIO_OUTCLR */
+/* Description: Clear individual bits in GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Register: GPIO_IN */
+/* Description: Read GPIO port */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
+
+/* Register: GPIO_DIR */
+/* Description: Direction of GPIO pins */
+
+/* Bit 31 : Pin 31 */
+#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
+
+/* Bit 30 : Pin 30 */
+#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
+
+/* Bit 29 : Pin 29 */
+#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
+
+/* Bit 28 : Pin 28 */
+#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
+
+/* Bit 27 : Pin 27 */
+#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
+
+/* Bit 26 : Pin 26 */
+#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
+
+/* Bit 25 : Pin 25 */
+#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
+
+/* Bit 24 : Pin 24 */
+#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
+
+/* Bit 23 : Pin 23 */
+#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
+
+/* Bit 22 : Pin 22 */
+#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
+
+/* Bit 21 : Pin 21 */
+#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
+
+/* Bit 20 : Pin 20 */
+#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
+
+/* Bit 19 : Pin 19 */
+#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
+
+/* Bit 18 : Pin 18 */
+#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
+
+/* Bit 17 : Pin 17 */
+#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
+
+/* Bit 16 : Pin 16 */
+#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
+
+/* Bit 15 : Pin 15 */
+#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
+
+/* Bit 14 : Pin 14 */
+#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
+
+/* Bit 13 : Pin 13 */
+#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
+
+/* Bit 12 : Pin 12 */
+#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
+
+/* Bit 11 : Pin 11 */
+#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
+
+/* Bit 10 : Pin 10 */
+#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
+
+/* Bit 9 : Pin 9 */
+#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
+
+/* Bit 8 : Pin 8 */
+#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
+
+/* Bit 7 : Pin 7 */
+#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
+
+/* Bit 6 : Pin 6 */
+#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
+
+/* Bit 5 : Pin 5 */
+#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
+
+/* Bit 4 : Pin 4 */
+#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
+
+/* Bit 3 : Pin 3 */
+#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
+
+/* Bit 2 : Pin 2 */
+#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
+
+/* Bit 1 : Pin 1 */
+#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
+
+/* Bit 0 : Pin 0 */
+#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
+
+/* Register: GPIO_DIRSET */
+/* Description: DIR set register */
+
+/* Bit 31 : Set as output pin 31 */
+#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 30 : Set as output pin 30 */
+#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 29 : Set as output pin 29 */
+#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 28 : Set as output pin 28 */
+#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 27 : Set as output pin 27 */
+#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 26 : Set as output pin 26 */
+#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 25 : Set as output pin 25 */
+#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 24 : Set as output pin 24 */
+#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 23 : Set as output pin 23 */
+#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 22 : Set as output pin 22 */
+#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 21 : Set as output pin 21 */
+#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 20 : Set as output pin 20 */
+#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 19 : Set as output pin 19 */
+#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 18 : Set as output pin 18 */
+#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 17 : Set as output pin 17 */
+#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 16 : Set as output pin 16 */
+#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 15 : Set as output pin 15 */
+#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 14 : Set as output pin 14 */
+#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 13 : Set as output pin 13 */
+#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 12 : Set as output pin 12 */
+#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 11 : Set as output pin 11 */
+#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 10 : Set as output pin 10 */
+#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 9 : Set as output pin 9 */
+#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 8 : Set as output pin 8 */
+#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 7 : Set as output pin 7 */
+#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 6 : Set as output pin 6 */
+#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 5 : Set as output pin 5 */
+#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 4 : Set as output pin 4 */
+#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 3 : Set as output pin 3 */
+#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 2 : Set as output pin 2 */
+#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 1 : Set as output pin 1 */
+#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 0 : Set as output pin 0 */
+#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Register: GPIO_DIRCLR */
+/* Description: DIR clear register */
+
+/* Bit 31 : Set as input pin 31 */
+#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 30 : Set as input pin 30 */
+#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 29 : Set as input pin 29 */
+#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 28 : Set as input pin 28 */
+#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 27 : Set as input pin 27 */
+#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 26 : Set as input pin 26 */
+#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 25 : Set as input pin 25 */
+#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 24 : Set as input pin 24 */
+#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 23 : Set as input pin 23 */
+#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 22 : Set as input pin 22 */
+#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 21 : Set as input pin 21 */
+#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 20 : Set as input pin 20 */
+#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 19 : Set as input pin 19 */
+#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 18 : Set as input pin 18 */
+#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 17 : Set as input pin 17 */
+#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 16 : Set as input pin 16 */
+#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 15 : Set as input pin 15 */
+#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 14 : Set as input pin 14 */
+#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 13 : Set as input pin 13 */
+#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 12 : Set as input pin 12 */
+#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 11 : Set as input pin 11 */
+#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 10 : Set as input pin 10 */
+#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 9 : Set as input pin 9 */
+#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 8 : Set as input pin 8 */
+#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 7 : Set as input pin 7 */
+#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 6 : Set as input pin 6 */
+#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 5 : Set as input pin 5 */
+#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 4 : Set as input pin 4 */
+#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 3 : Set as input pin 3 */
+#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 2 : Set as input pin 2 */
+#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 1 : Set as input pin 1 */
+#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 0 : Set as input pin 0 */
+#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Register: GPIO_LATCH */
+/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
+
+/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
+
+/* Register: GPIO_DETECTMODE */
+/* Description: Select between default DETECT signal behaviour and LDETECT mode */
+
+/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
+#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
+#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
+#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
+#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
+
+/* Register: GPIO_PIN_CNF */
+/* Description: Description collection[0]:  Configuration of GPIO pins */
+
+/* Bits 17..16 : Pin sensing mechanism */
+#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
+#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
+#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
+
+/* Bits 10..8 : Drive configuration */
+#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
+#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
+#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
+#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
+#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
+#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
+#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
+#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
+
+/* Bits 3..2 : Pull configuration */
+#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
+#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
+#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
+#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
+#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
+
+/* Bit 1 : Connect or disconnect input buffer */
+#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
+#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
+
+/* Bit 0 : Pin direction. Same physical register as DIR register */
+#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
+#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
+#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
+#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
+
+
+/* Peripheral: PDM */
+/* Description: Pulse Density Modulation (Digital Microphone) Interface */
+
+/* Register: PDM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 2 : Enable or disable interrupt for END event */
+#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for STARTED event */
+#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Register: PDM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for END event */
+#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for STARTED event */
+#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Register: PDM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for END event */
+#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for STARTED event */
+#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Register: PDM_ENABLE */
+/* Description: PDM module enable register */
+
+/* Bit 0 : Enable or disable PDM module */
+#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: PDM_PDMCLKCTRL */
+/* Description: PDM clock generator control */
+
+/* Bits 31..0 : PDM_CLK frequency */
+#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
+#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
+#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
+#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */
+#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
+
+/* Register: PDM_MODE */
+/* Description: Defines the routing of the connected PDM microphones' signals */
+
+/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
+#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
+#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
+#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
+#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
+
+/* Bit 0 : Mono or stereo operation */
+#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
+#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
+#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
+#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
+
+/* Register: PDM_GAINL */
+/* Description: Left output gain adjustment */
+
+/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust */
+#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
+#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
+#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
+#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
+#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
+
+/* Register: PDM_GAINR */
+/* Description: Right output gain adjustment */
+
+/* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
+#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
+#define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
+#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
+#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
+#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
+
+/* Register: PDM_PSEL_CLK */
+/* Description: Pin number configuration for PDM CLK signal */
+
+/* Bit 31 : Connection */
+#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
+#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: PDM_PSEL_DIN */
+/* Description: Pin number configuration for PDM DIN signal */
+
+/* Bit 31 : Connection */
+#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
+#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: PDM_SAMPLE_PTR */
+/* Description: RAM address pointer to write samples to with EasyDMA */
+
+/* Bits 31..0 : Address to write PDM samples to over DMA */
+#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
+#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
+
+/* Register: PDM_SAMPLE_MAXCNT */
+/* Description: Number of samples to allocate memory for in EasyDMA mode */
+
+/* Bits 14..0 : Length of DMA RAM allocation in number of samples */
+#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
+#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
+
+
+/* Peripheral: POWER */
+/* Description: Power control */
+
+/* Register: POWER_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */
+#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
+#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
+#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */
+#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
+#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
+#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for POFWARN event */
+#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
+
+/* Register: POWER_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */
+#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
+#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
+#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */
+#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
+#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
+#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for POFWARN event */
+#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
+
+/* Register: POWER_RESETREAS */
+/* Description: Reset reason */
+
+/* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
+#define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
+#define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
+#define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
+
+/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
+#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
+#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
+#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
+
+/* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
+#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
+
+/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
+#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
+#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
+#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
+
+/* Bit 3 : Reset from CPU lock-up detected */
+#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
+
+/* Bit 2 : Reset from soft reset detected */
+#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
+#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
+#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
+
+/* Bit 1 : Reset from watchdog detected */
+#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
+#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
+#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
+
+/* Bit 0 : Reset from pin-reset detected */
+#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
+
+/* Register: POWER_RAMSTATUS */
+/* Description: Deprecated register -  RAM status register */
+
+/* Bit 3 : RAM block 3 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
+
+/* Bit 2 : RAM block 2 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
+
+/* Bit 1 : RAM block 1 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
+
+/* Bit 0 : RAM block 0 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
+
+/* Register: POWER_SYSTEMOFF */
+/* Description: System OFF register */
+
+/* Bit 0 : Enable System OFF mode */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
+
+/* Register: POWER_POFCON */
+/* Description: Power failure comparator configuration */
+
+/* Bits 4..1 : Power failure comparator threshold setting */
+#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
+#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
+#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
+#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
+#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
+#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
+#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
+#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
+#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
+#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
+#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
+#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
+
+/* Bit 0 : Enable or disable power failure comparator */
+#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
+#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
+#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
+#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
+
+/* Register: POWER_GPREGRET */
+/* Description: General purpose retention register */
+
+/* Bits 7..0 : General purpose retention register */
+#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_GPREGRET2 */
+/* Description: General purpose retention register */
+
+/* Bits 7..0 : General purpose retention register */
+#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_RAMON */
+/* Description: Deprecated register -  RAM on/off register (this register is retained) */
+
+/* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */
+#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
+#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
+#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */
+#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */
+#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
+#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
+#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */
+#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM block 1 on or off in system ON Mode */
+#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
+#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
+#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */
+#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM block 0 on or off in system ON Mode */
+#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
+#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
+#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */
+#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */
+
+/* Register: POWER_RAMONB */
+/* Description: Deprecated register -  RAM on/off register (this register is retained) */
+
+/* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */
+#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
+#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
+#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */
+#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */
+#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
+#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
+#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */
+#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM block 3 on or off in system ON Mode */
+#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
+#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
+#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */
+#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM block 2 on or off in system ON Mode */
+#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
+#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
+#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */
+#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */
+
+/* Register: POWER_DCDCEN */
+/* Description: DC/DC enable register */
+
+/* Bit 0 : Enable or disable DC/DC converter */
+#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
+#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
+
+/* Register: POWER_RAM_POWER */
+/* Description: Description cluster[0]:  RAM0 power control register */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */
+#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */
+#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
+
+/* Register: POWER_RAM_POWERSET */
+/* Description: Description cluster[0]:  RAM0 power control set register */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
+
+/* Register: POWER_RAM_POWERCLR */
+/* Description: Description cluster[0]:  RAM0 power control clear register */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
+
+/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
+
+
+/* Peripheral: PPI */
+/* Description: Programmable Peripheral Interconnect */
+
+/* Register: PPI_CHEN */
+/* Description: Channel enable register */
+
+/* Bit 31 : Enable or disable channel 31 */
+#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 30 : Enable or disable channel 30 */
+#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 29 : Enable or disable channel 29 */
+#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 28 : Enable or disable channel 28 */
+#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 27 : Enable or disable channel 27 */
+#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 26 : Enable or disable channel 26 */
+#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 25 : Enable or disable channel 25 */
+#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 24 : Enable or disable channel 24 */
+#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 23 : Enable or disable channel 23 */
+#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 22 : Enable or disable channel 22 */
+#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 21 : Enable or disable channel 21 */
+#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 20 : Enable or disable channel 20 */
+#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 19 : Enable or disable channel 19 */
+#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 18 : Enable or disable channel 18 */
+#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 17 : Enable or disable channel 17 */
+#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 16 : Enable or disable channel 16 */
+#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 15 : Enable or disable channel 15 */
+#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 14 : Enable or disable channel 14 */
+#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 13 : Enable or disable channel 13 */
+#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 12 : Enable or disable channel 12 */
+#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 11 : Enable or disable channel 11 */
+#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 10 : Enable or disable channel 10 */
+#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 9 : Enable or disable channel 9 */
+#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 8 : Enable or disable channel 8 */
+#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 7 : Enable or disable channel 7 */
+#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 6 : Enable or disable channel 6 */
+#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 5 : Enable or disable channel 5 */
+#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 4 : Enable or disable channel 4 */
+#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 3 : Enable or disable channel 3 */
+#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 2 : Enable or disable channel 2 */
+#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 1 : Enable or disable channel 1 */
+#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 0 : Enable or disable channel 0 */
+#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
+
+/* Register: PPI_CHENSET */
+/* Description: Channel enable set register */
+
+/* Bit 31 : Channel 31 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 30 : Channel 30 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 29 : Channel 29 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 28 : Channel 28 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 27 : Channel 27 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 26 : Channel 26 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 25 : Channel 25 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 24 : Channel 24 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 23 : Channel 23 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 22 : Channel 22 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 21 : Channel 21 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 20 : Channel 20 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 19 : Channel 19 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 18 : Channel 18 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 17 : Channel 17 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 16 : Channel 16 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
+
+/* Register: PPI_CHENCLR */
+/* Description: Channel enable clear register */
+
+/* Bit 31 : Channel 31 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 30 : Channel 30 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 29 : Channel 29 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 28 : Channel 28 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 27 : Channel 27 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 26 : Channel 26 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 25 : Channel 25 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 24 : Channel 24 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 23 : Channel 23 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 22 : Channel 22 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 21 : Channel 21 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 20 : Channel 20 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 19 : Channel 19 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 18 : Channel 18 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 17 : Channel 17 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 16 : Channel 16 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
+
+/* Register: PPI_CH_EEP */
+/* Description: Description cluster[0]:  Channel 0 event end-point */
+
+/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
+#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
+#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
+
+/* Register: PPI_CH_TEP */
+/* Description: Description cluster[0]:  Channel 0 task end-point */
+
+/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
+#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
+#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
+
+/* Register: PPI_CHG */
+/* Description: Description collection[0]:  Channel group 0 */
+
+/* Bit 31 : Include or exclude channel 31 */
+#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH31_Included (1UL) /*!< Include */
+
+/* Bit 30 : Include or exclude channel 30 */
+#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH30_Included (1UL) /*!< Include */
+
+/* Bit 29 : Include or exclude channel 29 */
+#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH29_Included (1UL) /*!< Include */
+
+/* Bit 28 : Include or exclude channel 28 */
+#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH28_Included (1UL) /*!< Include */
+
+/* Bit 27 : Include or exclude channel 27 */
+#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH27_Included (1UL) /*!< Include */
+
+/* Bit 26 : Include or exclude channel 26 */
+#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH26_Included (1UL) /*!< Include */
+
+/* Bit 25 : Include or exclude channel 25 */
+#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH25_Included (1UL) /*!< Include */
+
+/* Bit 24 : Include or exclude channel 24 */
+#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH24_Included (1UL) /*!< Include */
+
+/* Bit 23 : Include or exclude channel 23 */
+#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH23_Included (1UL) /*!< Include */
+
+/* Bit 22 : Include or exclude channel 22 */
+#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH22_Included (1UL) /*!< Include */
+
+/* Bit 21 : Include or exclude channel 21 */
+#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH21_Included (1UL) /*!< Include */
+
+/* Bit 20 : Include or exclude channel 20 */
+#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH20_Included (1UL) /*!< Include */
+
+/* Bit 19 : Include or exclude channel 19 */
+#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH19_Included (1UL) /*!< Include */
+
+/* Bit 18 : Include or exclude channel 18 */
+#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH18_Included (1UL) /*!< Include */
+
+/* Bit 17 : Include or exclude channel 17 */
+#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH17_Included (1UL) /*!< Include */
+
+/* Bit 16 : Include or exclude channel 16 */
+#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH16_Included (1UL) /*!< Include */
+
+/* Bit 15 : Include or exclude channel 15 */
+#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH15_Included (1UL) /*!< Include */
+
+/* Bit 14 : Include or exclude channel 14 */
+#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH14_Included (1UL) /*!< Include */
+
+/* Bit 13 : Include or exclude channel 13 */
+#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH13_Included (1UL) /*!< Include */
+
+/* Bit 12 : Include or exclude channel 12 */
+#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH12_Included (1UL) /*!< Include */
+
+/* Bit 11 : Include or exclude channel 11 */
+#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH11_Included (1UL) /*!< Include */
+
+/* Bit 10 : Include or exclude channel 10 */
+#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH10_Included (1UL) /*!< Include */
+
+/* Bit 9 : Include or exclude channel 9 */
+#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH9_Included (1UL) /*!< Include */
+
+/* Bit 8 : Include or exclude channel 8 */
+#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH8_Included (1UL) /*!< Include */
+
+/* Bit 7 : Include or exclude channel 7 */
+#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH7_Included (1UL) /*!< Include */
+
+/* Bit 6 : Include or exclude channel 6 */
+#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH6_Included (1UL) /*!< Include */
+
+/* Bit 5 : Include or exclude channel 5 */
+#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH5_Included (1UL) /*!< Include */
+
+/* Bit 4 : Include or exclude channel 4 */
+#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH4_Included (1UL) /*!< Include */
+
+/* Bit 3 : Include or exclude channel 3 */
+#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH3_Included (1UL) /*!< Include */
+
+/* Bit 2 : Include or exclude channel 2 */
+#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH2_Included (1UL) /*!< Include */
+
+/* Bit 1 : Include or exclude channel 1 */
+#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH1_Included (1UL) /*!< Include */
+
+/* Bit 0 : Include or exclude channel 0 */
+#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH0_Included (1UL) /*!< Include */
+
+/* Register: PPI_FORK_TEP */
+/* Description: Description cluster[0]:  Channel 0 task end-point */
+
+/* Bits 31..0 : Pointer to task register */
+#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
+#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
+
+
+/* Peripheral: PWM */
+/* Description: Pulse Width Modulation Unit 0 */
+
+/* Register: PWM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */
+#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
+#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
+#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */
+#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
+#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
+#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */
+#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
+#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
+#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: PWM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
+#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
+#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
+#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
+#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
+#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
+#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: PWM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */
+#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */
+#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */
+#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */
+#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */
+#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */
+#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: PWM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */
+#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */
+#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */
+#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */
+#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */
+#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */
+#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: PWM_ENABLE */
+/* Description: PWM module enable register */
+
+/* Bit 0 : Enable or disable PWM module */
+#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
+#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: PWM_MODE */
+/* Description: Selects operating mode of the wave counter */
+
+/* Bit 0 : Selects up or up and down as wave counter mode */
+#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
+#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
+#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */
+#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */
+
+/* Register: PWM_COUNTERTOP */
+/* Description: Value up to which the pulse generator counter counts */
+
+/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */
+#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
+#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
+
+/* Register: PWM_PRESCALER */
+/* Description: Configuration for PWM_CLK */
+
+/* Bits 2..0 : Pre-scaler of PWM_CLK */
+#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by   1 (16MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by   2 ( 8MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by   4 ( 4MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by   8 ( 2MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by  16 ( 1MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by  32 ( 500kHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by  64 ( 250kHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */
+
+/* Register: PWM_DECODER */
+/* Description: Configuration of the decoder */
+
+/* Bit 8 : Selects source for advancing the active sequence */
+#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
+#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
+#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
+#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
+
+/* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */
+#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
+#define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
+#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
+#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
+#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
+#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
+
+/* Register: PWM_LOOP */
+/* Description: Amount of playback of a loop */
+
+/* Bits 15..0 : Amount of playback of pattern cycles */
+#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
+
+/* Register: PWM_SEQ_PTR */
+/* Description: Description cluster[0]:  Beginning address in Data RAM of this sequence */
+
+/* Bits 31..0 : Beginning address in Data RAM of this sequence */
+#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: PWM_SEQ_CNT */
+/* Description: Description cluster[0]:  Amount of values (duty cycles) in this sequence */
+
+/* Bits 14..0 : Amount of values (duty cycles) in this sequence */
+#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
+
+/* Register: PWM_SEQ_REFRESH */
+/* Description: Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register */
+
+/* Bits 23..0 : Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
+#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
+
+/* Register: PWM_SEQ_ENDDELAY */
+/* Description: Description cluster[0]:  Time added after the sequence */
+
+/* Bits 23..0 : Time added after the sequence in PWM periods */
+#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
+
+/* Register: PWM_PSEL_OUT */
+/* Description: Description collection[0]:  Output pin select for PWM channel 0 */
+
+/* Bit 31 : Connection */
+#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
+#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
+
+
+/* Peripheral: QDEC */
+/* Description: Quadrature Decoder */
+
+/* Register: QDEC_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between DBLRDY event and STOP task */
+#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
+#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
+#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between REPORTRDY event and STOP task */
+#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
+#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
+#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: QDEC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 4 : Write '1' to Enable interrupt for STOPPED event */
+#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
+#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */
+#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
+#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
+#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for ACCOF event */
+#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */
+#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */
+#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
+
+/* Register: QDEC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 4 : Write '1' to Disable interrupt for STOPPED event */
+#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
+#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */
+#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
+#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
+#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for ACCOF event */
+#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */
+#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */
+#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
+
+/* Register: QDEC_ENABLE */
+/* Description: Enable the quadrature decoder */
+
+/* Bit 0 : Enable or disable the quadrature decoder */
+#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: QDEC_LEDPOL */
+/* Description: LED output pin polarity */
+
+/* Bit 0 : LED output pin polarity */
+#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
+#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
+
+/* Register: QDEC_SAMPLEPER */
+/* Description: Sample period */
+
+/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
+#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
+
+/* Register: QDEC_SAMPLE */
+/* Description: Motion sample value */
+
+/* Bits 31..0 : Last motion sample */
+#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
+#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
+
+/* Register: QDEC_REPORTPER */
+/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
+
+/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */
+#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */
+#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */
+#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
+#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */
+#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */
+#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */
+#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */
+#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */
+#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */
+
+/* Register: QDEC_ACC */
+/* Description: Register accumulating the valid transitions */
+
+/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */
+#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
+#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
+
+/* Register: QDEC_ACCREAD */
+/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
+
+/* Bits 31..0 : Snapshot of the ACC register. */
+#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
+#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
+
+/* Register: QDEC_PSEL_LED */
+/* Description: Pin select for LED signal */
+
+/* Bit 31 : Connection */
+#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
+#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QDEC_PSEL_A */
+/* Description: Pin select for A signal */
+
+/* Bit 31 : Connection */
+#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
+#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QDEC_PSEL_B */
+/* Description: Pin select for B signal */
+
+/* Bit 31 : Connection */
+#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
+#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QDEC_DBFEN */
+/* Description: Enable input debounce filters */
+
+/* Bit 0 : Enable input debounce filters */
+#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
+#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
+
+/* Register: QDEC_LEDPRE */
+/* Description: Time period the LED is switched ON prior to sampling */
+
+/* Bits 8..0 : Period in us the LED is switched on prior to sampling */
+#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
+#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
+
+/* Register: QDEC_ACCDBL */
+/* Description: Register accumulating the number of detected double transitions */
+
+/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
+#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
+#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
+
+/* Register: QDEC_ACCDBLREAD */
+/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
+
+/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
+
+
+/* Peripheral: RADIO */
+/* Description: 2.4 GHz Radio */
+
+/* Register: RADIO_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between END event and START task */
+#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
+#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between DISABLED event and RXEN task */
+#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between DISABLED event and TXEN task */
+#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between END event and DISABLE task */
+#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between READY event and START task */
+#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
+#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
+#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: RADIO_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */
+#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
+#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for CRCOK event */
+#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
+#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
+#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */
+#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */
+#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */
+#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */
+#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for DISABLED event */
+#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for END event */
+#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */
+#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */
+#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: RADIO_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */
+#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
+#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for CRCOK event */
+#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
+#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
+#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */
+#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */
+#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */
+#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */
+#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for DISABLED event */
+#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for END event */
+#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */
+#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */
+#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: RADIO_CRCSTATUS */
+/* Description: CRC status */
+
+/* Bit 0 : CRC status of packet received */
+#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
+
+/* Register: RADIO_RXMATCH */
+/* Description: Received address */
+
+/* Bits 2..0 : Received address */
+#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
+#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
+
+/* Register: RADIO_RXCRC */
+/* Description: CRC field of previously received packet */
+
+/* Bits 23..0 : CRC field of previously received packet */
+#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
+#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
+
+/* Register: RADIO_DAI */
+/* Description: Device address match index */
+
+/* Bits 2..0 : Device address match index */
+#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
+#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
+
+/* Register: RADIO_PACKETPTR */
+/* Description: Packet pointer */
+
+/* Bits 31..0 : Packet pointer */
+#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
+#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
+
+/* Register: RADIO_FREQUENCY */
+/* Description: Frequency */
+
+/* Bit 8 : Channel map selection. */
+#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
+#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
+#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
+#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
+
+/* Bits 6..0 : Radio channel frequency */
+#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+
+/* Register: RADIO_TXPOWER */
+/* Description: Output power */
+
+/* Bits 7..0 : RADIO output power. */
+#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator -  -40 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
+
+/* Register: RADIO_MODE */
+/* Description: Data rate and modulation */
+
+/* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */
+#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator -  250 kbit/s Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */
+
+/* Register: RADIO_PCNF0 */
+/* Description: Packet configuration register 0 */
+
+/* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */
+#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
+#define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
+#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
+#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
+
+/* Bit 20 : Include or exclude S1 field in RAM */
+#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
+#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
+#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
+#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
+
+/* Bits 19..16 : Length on air of S1 field in number of bits. */
+#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
+#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
+
+/* Bit 8 : Length on air of S0 field in number of bytes. */
+#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
+#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
+
+/* Bits 3..0 : Length on air of LENGTH field in number of bits. */
+#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
+#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
+
+/* Register: RADIO_PCNF1 */
+/* Description: Packet configuration register 1 */
+
+/* Bit 25 : Enable or disable packet whitening */
+#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
+#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
+#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */
+#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
+
+/* Bits 18..16 : Base address length in number of bytes */
+#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
+#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
+
+/* Bits 15..8 : Static length in number of bytes */
+#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
+#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
+
+/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
+#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
+#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
+
+/* Register: RADIO_BASE0 */
+/* Description: Base address 0 */
+
+/* Bits 31..0 : Base address 0 */
+#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
+#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
+
+/* Register: RADIO_BASE1 */
+/* Description: Base address 1 */
+
+/* Bits 31..0 : Base address 1 */
+#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
+#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
+
+/* Register: RADIO_PREFIX0 */
+/* Description: Prefixes bytes for logical addresses 0-3 */
+
+/* Bits 31..24 : Address prefix 3. */
+#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
+#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
+
+/* Bits 23..16 : Address prefix 2. */
+#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
+#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
+
+/* Bits 15..8 : Address prefix 1. */
+#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
+#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
+
+/* Bits 7..0 : Address prefix 0. */
+#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
+#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
+
+/* Register: RADIO_PREFIX1 */
+/* Description: Prefixes bytes for logical addresses 4-7 */
+
+/* Bits 31..24 : Address prefix 7. */
+#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
+#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
+
+/* Bits 23..16 : Address prefix 6. */
+#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
+#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
+
+/* Bits 15..8 : Address prefix 5. */
+#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
+#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
+
+/* Bits 7..0 : Address prefix 4. */
+#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
+#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
+
+/* Register: RADIO_TXADDRESS */
+/* Description: Transmit address select */
+
+/* Bits 2..0 : Transmit address select */
+#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
+#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
+
+/* Register: RADIO_RXADDRESSES */
+/* Description: Receive address select */
+
+/* Bit 7 : Enable or disable reception on logical address 7. */
+#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable reception on logical address 6. */
+#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable reception on logical address 5. */
+#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable reception on logical address 4. */
+#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable reception on logical address 3. */
+#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable reception on logical address 2. */
+#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable reception on logical address 1. */
+#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable reception on logical address 0. */
+#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
+
+/* Register: RADIO_CRCCNF */
+/* Description: CRC configuration */
+
+/* Bit 8 : Include or exclude packet address field out of CRC calculation. */
+#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
+#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
+
+/* Bits 1..0 : CRC length in number of bytes. */
+#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
+#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
+#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
+#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
+#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
+#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
+
+/* Register: RADIO_CRCPOLY */
+/* Description: CRC polynomial */
+
+/* Bits 23..0 : CRC polynomial */
+#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
+#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
+
+/* Register: RADIO_CRCINIT */
+/* Description: CRC initial value */
+
+/* Bits 23..0 : CRC initial value */
+#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
+#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
+
+/* Register: RADIO_TIFS */
+/* Description: Inter Frame Spacing in us */
+
+/* Bits 7..0 : Inter Frame Spacing in us */
+#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
+#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
+
+/* Register: RADIO_RSSISAMPLE */
+/* Description: RSSI sample */
+
+/* Bits 6..0 : RSSI sample */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
+
+/* Register: RADIO_STATE */
+/* Description: Current radio state */
+
+/* Bits 3..0 : Current radio state */
+#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
+#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
+#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
+#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
+#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
+#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
+#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
+#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
+#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
+#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
+#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
+
+/* Register: RADIO_DATAWHITEIV */
+/* Description: Data whitening initial value */
+
+/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
+
+/* Register: RADIO_BCC */
+/* Description: Bit counter compare */
+
+/* Bits 31..0 : Bit counter compare */
+#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
+#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
+
+/* Register: RADIO_DAB */
+/* Description: Description collection[0]:  Device address base segment 0 */
+
+/* Bits 31..0 : Device address base segment 0 */
+#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
+#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
+
+/* Register: RADIO_DAP */
+/* Description: Description collection[0]:  Device address prefix 0 */
+
+/* Bits 15..0 : Device address prefix 0 */
+#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
+#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
+
+/* Register: RADIO_DACNF */
+/* Description: Device address match configuration */
+
+/* Bit 15 : TxAdd for device address 7 */
+#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
+#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
+
+/* Bit 14 : TxAdd for device address 6 */
+#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
+#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
+
+/* Bit 13 : TxAdd for device address 5 */
+#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
+#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
+
+/* Bit 12 : TxAdd for device address 4 */
+#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
+#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
+
+/* Bit 11 : TxAdd for device address 3 */
+#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
+#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
+
+/* Bit 10 : TxAdd for device address 2 */
+#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
+#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
+
+/* Bit 9 : TxAdd for device address 1 */
+#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
+#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
+
+/* Bit 8 : TxAdd for device address 0 */
+#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
+#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
+
+/* Bit 7 : Enable or disable device address matching using device address 7 */
+#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
+#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
+#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
+
+/* Bit 6 : Enable or disable device address matching using device address 6 */
+#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
+#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
+#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
+
+/* Bit 5 : Enable or disable device address matching using device address 5 */
+#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
+#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
+#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
+
+/* Bit 4 : Enable or disable device address matching using device address 4 */
+#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
+#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
+#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
+
+/* Bit 3 : Enable or disable device address matching using device address 3 */
+#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
+#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
+#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
+
+/* Bit 2 : Enable or disable device address matching using device address 2 */
+#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
+#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
+#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
+
+/* Bit 1 : Enable or disable device address matching using device address 1 */
+#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
+#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
+#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
+
+/* Bit 0 : Enable or disable device address matching using device address 0 */
+#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
+#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
+#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
+
+/* Register: RADIO_MODECNF0 */
+/* Description: Radio mode configuration register 0 */
+
+/* Bits 9..8 : Default TX value */
+#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
+#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
+#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
+#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
+#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
+
+/* Bit 0 : Radio ramp-up time */
+#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
+#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
+#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */
+#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */
+
+/* Register: RADIO_POWER */
+/* Description: Peripheral power control */
+
+/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
+#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
+#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
+
+
+/* Peripheral: RNG */
+/* Description: Random Number Generator */
+
+/* Register: RNG_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 0 : Shortcut between VALRDY event and STOP task */
+#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: RNG_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to Enable interrupt for VALRDY event */
+#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
+#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
+#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
+
+/* Register: RNG_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to Disable interrupt for VALRDY event */
+#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
+#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
+#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
+
+/* Register: RNG_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 0 : Bias correction */
+#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
+#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
+
+/* Register: RNG_VALUE */
+/* Description: Output random number */
+
+/* Bits 7..0 : Generated random number */
+#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
+#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
+
+
+/* Peripheral: RTC */
+/* Description: Real time counter 0 */
+
+/* Register: RTC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
+#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
+#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
+#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
+#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */
+#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for TICK event */
+#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
+
+/* Register: RTC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
+#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
+#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
+#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
+#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */
+#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for TICK event */
+#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
+
+/* Register: RTC_EVTEN */
+/* Description: Enable or disable event routing */
+
+/* Bit 19 : Enable or disable event routing for COMPARE[3] event */
+#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable event routing for COMPARE[2] event */
+#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable event routing for COMPARE[1] event */
+#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
+
+/* Bit 16 : Enable or disable event routing for COMPARE[0] event */
+#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable event routing for OVRFLW event */
+#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable event routing for TICK event */
+#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
+
+/* Register: RTC_EVTENSET */
+/* Description: Enable event routing */
+
+/* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */
+#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */
+#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */
+#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */
+#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable event routing for OVRFLW event */
+#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable event routing for TICK event */
+#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
+
+/* Register: RTC_EVTENCLR */
+/* Description: Disable event routing */
+
+/* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */
+#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */
+#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */
+#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */
+#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable event routing for OVRFLW event */
+#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable event routing for TICK event */
+#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
+
+/* Register: RTC_COUNTER */
+/* Description: Current COUNTER value */
+
+/* Bits 23..0 : Counter value */
+#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
+#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
+
+/* Register: RTC_PRESCALER */
+/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */
+
+/* Bits 11..0 : Prescaler value */
+#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: RTC_CC */
+/* Description: Description collection[0]:  Compare register 0 */
+
+/* Bits 23..0 : Compare value */
+#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
+#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
+
+
+/* Peripheral: SAADC */
+/* Description: Analog to Digital Converter */
+
+/* Register: SAADC_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
+#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
+#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
+#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
+#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
+#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
+#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
+#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
+#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
+#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
+#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
+#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
+#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
+#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
+#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
+#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
+#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for STOPPED event */
+#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
+#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for RESULTDONE event */
+#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for DONE event */
+#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for END event */
+#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for STARTED event */
+#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Register: SAADC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */
+#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */
+#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */
+#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */
+#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */
+#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */
+#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */
+#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */
+#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */
+#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */
+#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */
+#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */
+#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */
+#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */
+#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */
+#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */
+#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for STOPPED event */
+#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */
+#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */
+#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for DONE event */
+#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for END event */
+#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for STARTED event */
+#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Register: SAADC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */
+#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */
+#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */
+#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */
+#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */
+#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */
+#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */
+#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */
+#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */
+#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */
+#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */
+#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */
+#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */
+#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */
+#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */
+#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */
+#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for STOPPED event */
+#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */
+#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */
+#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for DONE event */
+#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for END event */
+#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for STARTED event */
+#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Register: SAADC_STATUS */
+/* Description: Status */
+
+/* Bit 0 : Status */
+#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
+#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
+
+/* Register: SAADC_ENABLE */
+/* Description: Enable or disable ADC */
+
+/* Bit 0 : Enable or disable ADC */
+#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
+#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
+
+/* Register: SAADC_CH_PSELP */
+/* Description: Description cluster[0]:  Input positive pin selection for CH[0] */
+
+/* Bits 4..0 : Analog positive input channel */
+#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
+#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
+#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
+#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
+#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
+
+/* Register: SAADC_CH_PSELN */
+/* Description: Description cluster[0]:  Input negative pin selection for CH[0] */
+
+/* Bits 4..0 : Analog negative input, enables differential channel */
+#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
+#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
+#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
+#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
+#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
+
+/* Register: SAADC_CH_CONFIG */
+/* Description: Description cluster[0]:  Input configuration for CH[0] */
+
+/* Bit 24 : Enable burst mode */
+#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
+#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
+#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
+#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
+
+/* Bit 20 : Enable differential mode */
+#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
+#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
+#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
+
+/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
+#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
+#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
+#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
+#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
+#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
+#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
+#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
+#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
+
+/* Bit 12 : Reference control */
+#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
+#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
+#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
+
+/* Bits 10..8 : Gain control */
+#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
+#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
+#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
+#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
+#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
+#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
+
+/* Bits 5..4 : Negative channel resistor control */
+#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
+#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
+#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
+#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
+#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
+#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
+
+/* Bits 1..0 : Positive channel resistor control */
+#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
+#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
+#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
+#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
+#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
+#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
+
+/* Register: SAADC_CH_LIMIT */
+/* Description: Description cluster[0]:  High/low limits for event monitoring a channel */
+
+/* Bits 31..16 : High level limit */
+#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
+#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
+
+/* Bits 15..0 : Low level limit */
+#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
+#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
+
+/* Register: SAADC_RESOLUTION */
+/* Description: Resolution configuration */
+
+/* Bits 2..0 : Set the resolution */
+#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
+#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
+#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
+#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
+#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
+#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
+
+/* Register: SAADC_OVERSAMPLE */
+/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
+
+/* Bits 3..0 : Oversample control */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
+
+/* Register: SAADC_SAMPLERATE */
+/* Description: Controls normal or continuous sample rate */
+
+/* Bit 12 : Select mode for sample rate control */
+#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
+#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
+#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
+
+/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
+#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
+#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
+
+/* Register: SAADC_RESULT_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SAADC_RESULT_MAXCNT */
+/* Description: Maximum number of buffer words to transfer */
+
+/* Bits 14..0 : Maximum number of buffer words to transfer */
+#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SAADC_RESULT_AMOUNT */
+/* Description: Number of buffer words transferred since last START */
+
+/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
+#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+
+/* Peripheral: SPI */
+/* Description: Serial Peripheral Interface 0 */
+
+/* Register: SPI_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for READY event */
+#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: SPI_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for READY event */
+#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: SPI_ENABLE */
+/* Description: Enable SPI */
+
+/* Bits 3..0 : Enable or disable SPI */
+#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
+#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
+
+/* Register: SPI_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bits 31..0 : Pin number configuration for SPI SCK signal */
+#define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */
+#define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */
+#define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: SPI_PSEL_MOSI */
+/* Description: Pin select for MOSI */
+
+/* Bits 31..0 : Pin number configuration for SPI MOSI signal */
+#define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */
+#define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */
+#define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: SPI_PSEL_MISO */
+/* Description: Pin select for MISO */
+
+/* Bits 31..0 : Pin number configuration for SPI MISO signal */
+#define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */
+#define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */
+#define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: SPI_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RX data received. Double buffered */
+#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: SPI_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TX data to send. Double buffered */
+#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: SPI_FREQUENCY */
+/* Description: SPI frequency */
+
+/* Bits 31..0 : SPI master data rate */
+#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
+#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
+#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
+
+/* Register: SPI_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+
+/* Peripheral: SPIM */
+/* Description: Serial Peripheral Interface Master with EasyDMA 0 */
+
+/* Register: SPIM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 17 : Shortcut between END event and START task */
+#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
+#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
+#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: SPIM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 19 : Write '1' to Enable interrupt for STARTED event */
+#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
+#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for END event */
+#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
+#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
+#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: SPIM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 19 : Write '1' to Disable interrupt for STARTED event */
+#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
+#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for END event */
+#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
+#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
+#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: SPIM_ENABLE */
+/* Description: Enable SPIM */
+
+/* Bits 3..0 : Enable or disable SPIM */
+#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
+#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
+
+/* Register: SPIM_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_FREQUENCY */
+/* Description: SPI frequency */
+
+/* Bits 31..0 : SPI master data rate */
+#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
+
+/* Register: SPIM_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 7..0 : Maximum number of bytes in receive buffer */
+#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction */
+#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIM_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 7..0 : Maximum number of bytes in transmit buffer */
+#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction */
+#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIM_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+/* Register: SPIM_ORC */
+/* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */
+
+/* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */
+#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: SPIS */
+/* Description: SPI Slave 0 */
+
+/* Register: SPIS_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 2 : Shortcut between END event and ACQUIRE task */
+#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
+#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: SPIS_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */
+#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
+#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for END event */
+#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Register: SPIS_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */
+#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
+#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for END event */
+#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Register: SPIS_SEMSTAT */
+/* Description: Semaphore status register */
+
+/* Bits 1..0 : Semaphore status */
+#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
+#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
+#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
+#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
+
+/* Register: SPIS_STATUS */
+/* Description: Status from last transaction */
+
+/* Bit 1 : RX buffer overflow detected, and prevented */
+#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
+#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
+#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Bit 0 : TX buffer over-read detected, and prevented */
+#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
+#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
+#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Register: SPIS_ENABLE */
+/* Description: Enable SPI slave */
+
+/* Bits 3..0 : Enable or disable SPI slave */
+#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
+#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
+
+/* Register: SPIS_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_CSN */
+/* Description: Pin select for CSN signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_RXD_PTR */
+/* Description: RXD data pointer */
+
+/* Bits 31..0 : RXD data pointer */
+#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIS_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 7..0 : Maximum number of bytes in receive buffer */
+#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIS_RXD_AMOUNT */
+/* Description: Number of bytes received in last granted transaction */
+
+/* Bits 7..0 : Number of bytes received in the last granted transaction */
+#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIS_TXD_PTR */
+/* Description: TXD data pointer */
+
+/* Bits 31..0 : TXD data pointer */
+#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIS_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 7..0 : Maximum number of bytes in transmit buffer */
+#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIS_TXD_AMOUNT */
+/* Description: Number of bytes transmitted in last granted transaction */
+
+/* Bits 7..0 : Number of bytes transmitted in last granted transaction */
+#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIS_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+/* Register: SPIS_DEF */
+/* Description: Default character. Character clocked out in case of an ignored transaction. */
+
+/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
+#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
+#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
+
+/* Register: SPIS_ORC */
+/* Description: Over-read character */
+
+/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
+#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: TEMP */
+/* Description: Temperature Sensor */
+
+/* Register: TEMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to Enable interrupt for DATARDY event */
+#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
+#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
+#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
+
+/* Register: TEMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to Disable interrupt for DATARDY event */
+#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
+#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
+#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
+
+/* Register: TEMP_TEMP */
+/* Description: Temperature in degC (0.25deg steps) */
+
+/* Bits 31..0 : Temperature in degC (0.25deg steps) */
+#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
+#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
+
+/* Register: TEMP_A0 */
+/* Description: Slope of 1st piece wise linear function */
+
+/* Bits 11..0 : Slope of 1st piece wise linear function */
+#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
+#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
+
+/* Register: TEMP_A1 */
+/* Description: Slope of 2nd piece wise linear function */
+
+/* Bits 11..0 : Slope of 2nd piece wise linear function */
+#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
+#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
+
+/* Register: TEMP_A2 */
+/* Description: Slope of 3rd piece wise linear function */
+
+/* Bits 11..0 : Slope of 3rd piece wise linear function */
+#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
+#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
+
+/* Register: TEMP_A3 */
+/* Description: Slope of 4th piece wise linear function */
+
+/* Bits 11..0 : Slope of 4th piece wise linear function */
+#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
+#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
+
+/* Register: TEMP_A4 */
+/* Description: Slope of 5th piece wise linear function */
+
+/* Bits 11..0 : Slope of 5th piece wise linear function */
+#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
+#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
+
+/* Register: TEMP_A5 */
+/* Description: Slope of 6th piece wise linear function */
+
+/* Bits 11..0 : Slope of 6th piece wise linear function */
+#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
+#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
+
+/* Register: TEMP_B0 */
+/* Description: y-intercept of 1st piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 1st piece wise linear function */
+#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
+#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
+
+/* Register: TEMP_B1 */
+/* Description: y-intercept of 2nd piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 2nd piece wise linear function */
+#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
+#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
+
+/* Register: TEMP_B2 */
+/* Description: y-intercept of 3rd piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 3rd piece wise linear function */
+#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
+#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
+
+/* Register: TEMP_B3 */
+/* Description: y-intercept of 4th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 4th piece wise linear function */
+#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
+#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
+
+/* Register: TEMP_B4 */
+/* Description: y-intercept of 5th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 5th piece wise linear function */
+#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
+#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
+
+/* Register: TEMP_B5 */
+/* Description: y-intercept of 6th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 6th piece wise linear function */
+#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
+#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
+
+/* Register: TEMP_T0 */
+/* Description: End point of 1st piece wise linear function */
+
+/* Bits 7..0 : End point of 1st piece wise linear function */
+#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
+#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
+
+/* Register: TEMP_T1 */
+/* Description: End point of 2nd piece wise linear function */
+
+/* Bits 7..0 : End point of 2nd piece wise linear function */
+#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
+#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
+
+/* Register: TEMP_T2 */
+/* Description: End point of 3rd piece wise linear function */
+
+/* Bits 7..0 : End point of 3rd piece wise linear function */
+#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
+#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
+
+/* Register: TEMP_T3 */
+/* Description: End point of 4th piece wise linear function */
+
+/* Bits 7..0 : End point of 4th piece wise linear function */
+#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
+#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
+
+/* Register: TEMP_T4 */
+/* Description: End point of 5th piece wise linear function */
+
+/* Bits 7..0 : End point of 5th piece wise linear function */
+#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
+#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
+
+
+/* Peripheral: TIMER */
+/* Description: Timer/Counter 0 */
+
+/* Register: TIMER_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */
+#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
+#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
+#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */
+#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
+#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
+#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */
+#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */
+#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */
+#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */
+#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TIMER_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */
+#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
+#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
+#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */
+#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
+#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
+#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
+#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
+#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
+#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
+#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Register: TIMER_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */
+#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
+#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
+#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */
+#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
+#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
+#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
+#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
+#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
+#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
+#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Register: TIMER_MODE */
+/* Description: Timer mode selection */
+
+/* Bits 1..0 : Timer mode */
+#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
+#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
+#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
+
+/* Register: TIMER_BITMODE */
+/* Description: Configure the number of bits used by the TIMER */
+
+/* Bits 1..0 : Timer bit width */
+#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
+
+/* Register: TIMER_PRESCALER */
+/* Description: Timer prescaler register */
+
+/* Bits 3..0 : Prescaler value */
+#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: TIMER_CC */
+/* Description: Description collection[0]:  Capture/Compare register 0 */
+
+/* Bits 31..0 : Capture/Compare value */
+#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
+#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
+
+
+/* Peripheral: TWI */
+/* Description: I2C compatible Two-Wire Interface 0 */
+
+/* Register: TWI_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 1 : Shortcut between BB event and STOP task */
+#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between BB event and SUSPEND task */
+#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWI_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
+#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for BB event */
+#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */
+#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */
+#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWI_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
+#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for BB event */
+#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */
+#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */
+#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWI_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
+#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
+#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
+#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Bit 1 : NACK received after sending the address (write '1' to clear) */
+#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
+#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
+#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Bit 0 : Overrun error */
+#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
+#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
+#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Register: TWI_ENABLE */
+/* Description: Enable TWI */
+
+/* Bits 3..0 : Enable or disable TWI */
+#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
+#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
+
+/* Register: TWI_PSELSCL */
+/* Description: Pin select for SCL */
+
+/* Bits 31..0 : Pin number configuration for TWI SCL signal */
+#define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */
+#define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */
+#define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: TWI_PSELSDA */
+/* Description: Pin select for SDA */
+
+/* Bits 31..0 : Pin number configuration for TWI SDA signal */
+#define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */
+#define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */
+#define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: TWI_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RXD register */
+#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: TWI_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TXD register */
+#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: TWI_FREQUENCY */
+/* Description: TWI frequency */
+
+/* Bits 31..0 : TWI master clock frequency */
+#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
+#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
+
+/* Register: TWI_ADDRESS */
+/* Description: Address used in the TWI transfer */
+
+/* Bits 6..0 : Address used in the TWI transfer */
+#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+
+/* Peripheral: TWIM */
+/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
+
+/* Register: TWIM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 12 : Shortcut between LASTRX event and STOP task */
+#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
+#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
+#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 10 : Shortcut between LASTRX event and STARTTX task */
+#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
+#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
+#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 9 : Shortcut between LASTTX event and STOP task */
+#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
+#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
+#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 7 : Shortcut between LASTTX event and STARTRX task */
+#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
+#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
+#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWIM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 24 : Enable or disable interrupt for LASTTX event */
+#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 23 : Enable or disable interrupt for LASTRX event */
+#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
+#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
+#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for SUSPENDED event */
+#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for ERROR event */
+#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: TWIM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 24 : Write '1' to Enable interrupt for LASTTX event */
+#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
+
+/* Bit 23 : Write '1' to Enable interrupt for LASTRX event */
+#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
+#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
+#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
+#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWIM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 24 : Write '1' to Disable interrupt for LASTTX event */
+#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
+
+/* Bit 23 : Write '1' to Disable interrupt for LASTRX event */
+#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
+#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
+#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
+#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWIM_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
+#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 1 : NACK received after sending the address (write '1' to clear) */
+#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 0 : Overrun error */
+#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
+
+/* Register: TWIM_ENABLE */
+/* Description: Enable TWIM */
+
+/* Bits 3..0 : Enable or disable TWIM */
+#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
+#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
+
+/* Register: TWIM_PSEL_SCL */
+/* Description: Pin select for SCL signal */
+
+/* Bit 31 : Connection */
+#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIM_PSEL_SDA */
+/* Description: Pin select for SDA signal */
+
+/* Bit 31 : Connection */
+#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIM_FREQUENCY */
+/* Description: TWI frequency */
+
+/* Bits 31..0 : TWI master clock frequency */
+#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
+#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
+
+/* Register: TWIM_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIM_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 7..0 : Maximum number of bytes in receive buffer */
+#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIM_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
+#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIM_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIM_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIM_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 7..0 : Maximum number of bytes in transmit buffer */
+#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIM_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
+#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIM_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIM_ADDRESS */
+/* Description: Address used in the TWI transfer */
+
+/* Bits 6..0 : Address used in the TWI transfer */
+#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+
+/* Peripheral: TWIS */
+/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
+
+/* Register: TWIS_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 14 : Shortcut between READ event and SUSPEND task */
+#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
+#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
+#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 13 : Shortcut between WRITE event and SUSPEND task */
+#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
+#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
+#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWIS_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 26 : Enable or disable interrupt for READ event */
+#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable interrupt for WRITE event */
+#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
+#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
+#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for ERROR event */
+#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: TWIS_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 26 : Write '1' to Enable interrupt for READ event */
+#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to Enable interrupt for WRITE event */
+#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
+#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
+#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWIS_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 26 : Write '1' to Disable interrupt for READ event */
+#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to Disable interrupt for WRITE event */
+#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
+#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
+#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWIS_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 3 : TX buffer over-read detected, and prevented */
+#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
+#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
+
+/* Bit 2 : NACK sent after receiving a data byte */
+#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 0 : RX buffer overflow detected, and prevented */
+#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
+#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
+
+/* Register: TWIS_MATCH */
+/* Description: Status register indicating which address had a match */
+
+/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
+#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
+#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
+
+/* Register: TWIS_ENABLE */
+/* Description: Enable TWIS */
+
+/* Bits 3..0 : Enable or disable TWIS */
+#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
+#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
+
+/* Register: TWIS_PSEL_SCL */
+/* Description: Pin select for SCL signal */
+
+/* Bit 31 : Connection */
+#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIS_PSEL_SDA */
+/* Description: Pin select for SDA signal */
+
+/* Bit 31 : Connection */
+#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIS_RXD_PTR */
+/* Description: RXD Data pointer */
+
+/* Bits 31..0 : RXD Data pointer */
+#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIS_RXD_MAXCNT */
+/* Description: Maximum number of bytes in RXD buffer */
+
+/* Bits 7..0 : Maximum number of bytes in RXD buffer */
+#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIS_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last RXD transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last RXD transaction */
+#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIS_TXD_PTR */
+/* Description: TXD Data pointer */
+
+/* Bits 31..0 : TXD Data pointer */
+#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIS_TXD_MAXCNT */
+/* Description: Maximum number of bytes in TXD buffer */
+
+/* Bits 7..0 : Maximum number of bytes in TXD buffer */
+#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIS_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last TXD transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last TXD transaction */
+#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIS_ADDRESS */
+/* Description: Description collection[0]:  TWI slave address 0 */
+
+/* Bits 6..0 : TWI slave address */
+#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+/* Register: TWIS_CONFIG */
+/* Description: Configuration register for the address match mechanism */
+
+/* Bit 1 : Enable or disable address matching on ADDRESS[1] */
+#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
+#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
+#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
+#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
+
+/* Bit 0 : Enable or disable address matching on ADDRESS[0] */
+#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
+#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
+#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
+#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
+
+/* Register: TWIS_ORC */
+/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
+
+/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
+#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: UART */
+/* Description: Universal Asynchronous Receiver/Transmitter */
+
+/* Register: UART_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between NCTS event and STOPRX task */
+#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
+#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between CTS event and STARTRX task */
+#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: UART_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 17 : Write '1' to Enable interrupt for RXTO event */
+#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
+#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
+#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for NCTS event */
+#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for CTS event */
+#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
+
+/* Register: UART_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 17 : Write '1' to Disable interrupt for RXTO event */
+#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
+#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
+#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for NCTS event */
+#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for CTS event */
+#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
+
+/* Register: UART_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 3 : Break condition */
+#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
+
+/* Bit 2 : Framing error occurred */
+#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : Parity error */
+#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
+
+/* Register: UART_ENABLE */
+/* Description: Enable UART */
+
+/* Bits 3..0 : Enable or disable UART */
+#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
+#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
+
+/* Register: UART_PSELRTS */
+/* Description: Pin select for RTS */
+
+/* Bits 31..0 : Pin number configuration for UART RTS signal */
+#define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */
+#define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */
+#define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: UART_PSELTXD */
+/* Description: Pin select for TXD */
+
+/* Bits 31..0 : Pin number configuration for UART TXD signal */
+#define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */
+#define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */
+#define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: UART_PSELCTS */
+/* Description: Pin select for CTS */
+
+/* Bits 31..0 : Pin number configuration for UART CTS signal */
+#define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */
+#define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */
+#define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: UART_PSELRXD */
+/* Description: Pin select for RXD */
+
+/* Bits 31..0 : Pin number configuration for UART RXD signal */
+#define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */
+#define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */
+#define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: UART_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RX data received in previous transfers, double buffered */
+#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: UART_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TX data to be transferred */
+#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: UART_BAUDRATE */
+/* Description: Baud rate */
+
+/* Bits 31..0 : Baud rate */
+#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
+#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
+#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
+#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
+#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
+#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
+#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
+#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
+#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
+#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
+#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
+#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
+#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
+#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
+#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
+#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
+#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
+#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
+
+/* Register: UART_CONFIG */
+/* Description: Configuration of parity and hardware flow control */
+
+/* Bits 3..1 : Parity */
+#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
+#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
+
+/* Bit 0 : Hardware flow control */
+#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
+#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
+
+
+/* Peripheral: UARTE */
+/* Description: UART with EasyDMA */
+
+/* Register: UARTE_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 6 : Shortcut between ENDRX event and STOPRX task */
+#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
+#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
+#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
+#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between ENDRX event and STARTRX task */
+#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
+#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
+#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: UARTE_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
+#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
+#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
+#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for RXTO event */
+#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for ERROR event */
+#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for ENDTX event */
+#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for TXDRDY event */
+#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for ENDRX event */
+#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for RXDRDY event */
+#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for NCTS event */
+#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for CTS event */
+#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
+
+/* Register: UARTE_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */
+#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
+#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
+#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for RXTO event */
+#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
+#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
+#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
+#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
+#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for NCTS event */
+#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for CTS event */
+#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
+
+/* Register: UARTE_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */
+#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
+#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
+#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for RXTO event */
+#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
+#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
+#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
+#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
+#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for NCTS event */
+#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for CTS event */
+#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
+
+/* Register: UARTE_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 3 : Break condition */
+#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
+
+/* Bit 2 : Framing error occurred */
+#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : Parity error */
+#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
+
+/* Register: UARTE_ENABLE */
+/* Description: Enable UART */
+
+/* Bits 3..0 : Enable or disable UARTE */
+#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
+#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
+
+/* Register: UARTE_PSEL_RTS */
+/* Description: Pin select for RTS signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_TXD */
+/* Description: Pin select for TXD signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_CTS */
+/* Description: Pin select for CTS signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_RXD */
+/* Description: Pin select for RXD signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_BAUDRATE */
+/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
+
+/* Bits 31..0 : Baud rate */
+#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
+#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
+#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
+
+/* Register: UARTE_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: UARTE_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 7..0 : Maximum number of bytes in receive buffer */
+#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: UARTE_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction */
+#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: UARTE_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: UARTE_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 7..0 : Maximum number of bytes in transmit buffer */
+#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: UARTE_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction */
+#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: UARTE_CONFIG */
+/* Description: Configuration of parity and hardware flow control */
+
+/* Bits 3..1 : Parity */
+#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
+#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
+
+/* Bit 0 : Hardware flow control */
+#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
+#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
+
+
+/* Peripheral: UICR */
+/* Description: User Information Configuration Registers */
+
+/* Register: UICR_NRFFW */
+/* Description: Description collection[0]:  Reserved for Nordic firmware design */
+
+/* Bits 31..0 : Reserved for Nordic firmware design */
+#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
+#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
+
+/* Register: UICR_NRFHW */
+/* Description: Description collection[0]:  Reserved for Nordic hardware design */
+
+/* Bits 31..0 : Reserved for Nordic hardware design */
+#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
+#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
+
+/* Register: UICR_CUSTOMER */
+/* Description: Description collection[0]:  Reserved for customer */
+
+/* Bits 31..0 : Reserved for customer */
+#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
+#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
+
+/* Register: UICR_PSELRESET */
+/* Description: Description collection[0]:  Mapping of the nRESET function (see POWER chapter for details) */
+
+/* Bit 31 : Connection */
+#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
+#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : GPIO number P0.n onto which Reset is exposed */
+#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UICR_APPROTECT */
+/* Description: Access Port protection */
+
+/* Bits 7..0 : Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. */
+#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
+#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
+#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
+#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */
+
+/* Register: UICR_NFCPINS */
+/* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
+
+/* Bit 0 : Setting of pins dedicated to NFC functionality */
+#define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
+#define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
+#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */
+#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */
+
+
+/* Peripheral: WDT */
+/* Description: Watchdog Timer */
+
+/* Register: WDT_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */
+#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
+#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
+#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
+
+/* Register: WDT_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */
+#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
+#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
+#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
+
+/* Register: WDT_RUNSTATUS */
+/* Description: Run status */
+
+/* Bit 0 : Indicates whether or not the watchdog is running */
+#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
+#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
+
+/* Register: WDT_REQSTATUS */
+/* Description: Request status */
+
+/* Bit 7 : Request status for RR[7] register */
+#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
+
+/* Bit 6 : Request status for RR[6] register */
+#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
+
+/* Bit 5 : Request status for RR[5] register */
+#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
+
+/* Bit 4 : Request status for RR[4] register */
+#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
+
+/* Bit 3 : Request status for RR[3] register */
+#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
+
+/* Bit 2 : Request status for RR[2] register */
+#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
+
+/* Bit 1 : Request status for RR[1] register */
+#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
+
+/* Bit 0 : Request status for RR[0] register */
+#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
+
+/* Register: WDT_CRV */
+/* Description: Counter reload value */
+
+/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
+#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
+#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
+
+/* Register: WDT_RREN */
+/* Description: Enable register for reload request registers */
+
+/* Bit 7 : Enable or disable RR[7] register */
+#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
+#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
+
+/* Bit 6 : Enable or disable RR[6] register */
+#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
+#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
+
+/* Bit 5 : Enable or disable RR[5] register */
+#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
+#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
+
+/* Bit 4 : Enable or disable RR[4] register */
+#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
+#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
+
+/* Bit 3 : Enable or disable RR[3] register */
+#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
+#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
+
+/* Bit 2 : Enable or disable RR[2] register */
+#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
+#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
+
+/* Bit 1 : Enable or disable RR[1] register */
+#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
+#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
+
+/* Bit 0 : Enable or disable RR[0] register */
+#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
+#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
+
+/* Register: WDT_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
+#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
+#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
+#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
+#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
+
+/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
+#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
+#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
+
+/* Register: WDT_RR */
+/* Description: Description collection[0]:  Reload request 0 */
+
+/* Bits 31..0 : Reload request register */
+#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
+#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
+#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
+
+
+/*lint --flb "Leave library region" */
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52_name_change.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,78 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+#ifndef NRF52_NAME_CHANGE_H
+#define NRF52_NAME_CHANGE_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the updates made to nrf52.h and 
+ * nrf52_bitfields.h. The macros defined in this file were available previously. Do not use these
+ * macros on purpose. Use the ones defined in nrf52.h and nrf52_bitfields.h instead.
+ */
+
+/* I2S */
+/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
+#define I2S_ENABLE_ENABLE_DISABLE           I2S_ENABLE_ENABLE_Disabled
+#define I2S_ENABLE_ENABLE_ENABLE            I2S_ENABLE_ENABLE_Enabled
+#define I2S_CONFIG_MODE_MODE_MASTER         I2S_CONFIG_MODE_MODE_Master
+#define I2S_CONFIG_MODE_MODE_SLAVE          I2S_CONFIG_MODE_MODE_Slave
+#define I2S_CONFIG_RXEN_RXEN_DISABLE        I2S_CONFIG_RXEN_RXEN_Disabled
+#define I2S_CONFIG_RXEN_RXEN_ENABLE         I2S_CONFIG_RXEN_RXEN_Enabled
+#define I2S_CONFIG_TXEN_TXEN_DISABLE        I2S_CONFIG_TXEN_TXEN_Disabled
+#define I2S_CONFIG_TXEN_TXEN_ENABLE         I2S_CONFIG_TXEN_TXEN_Enabled
+#define I2S_CONFIG_MCKEN_MCKEN_DISABLE      I2S_CONFIG_MCKEN_MCKEN_Disabled
+#define I2S_CONFIG_MCKEN_MCKEN_ENABLE       I2S_CONFIG_MCKEN_MCKEN_Enabled
+#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT       I2S_CONFIG_SWIDTH_SWIDTH_8Bit
+#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT      I2S_CONFIG_SWIDTH_SWIDTH_16Bit
+#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT      I2S_CONFIG_SWIDTH_SWIDTH_24Bit
+#define I2S_CONFIG_ALIGN_ALIGN_LEFT         I2S_CONFIG_ALIGN_ALIGN_Left
+#define I2S_CONFIG_ALIGN_ALIGN_RIGHT        I2S_CONFIG_ALIGN_ALIGN_Right
+#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED    I2S_CONFIG_FORMAT_FORMAT_Aligned
+#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
+#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT   I2S_CONFIG_CHANNELS_CHANNELS_Left
+#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT  I2S_CONFIG_CHANNELS_CHANNELS_Right
+
+/* LPCOMP */
+/* Corrected typo in RESULT register. */
+#define LPCOMP_RESULT_RESULT_Bellow         LPCOMP_RESULT_RESULT_Below
+
+/*lint --flb "Leave library region" */
+
+#endif /* NRF52_NAME_CHANGE_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52_to_nrf52840.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,96 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+#ifndef NRF52_TO_NRF52840_H
+#define NRF52_TO_NRF52840_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the name changes between nRF51 or nRF52832 and nRF52840 devices.
+ * It redefines the old nRF51 or nRF52832 names into the new ones as long as the functionality is still supported. If the
+ * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros
+ * from the nrf52_namechange.h file. */
+ 
+/* Differences between latest nRF52 headers and nRF52840 headers. */
+
+/* UART */
+/* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */
+#define PSELRTS       PSEL.RTS
+#define PSELTXD       PSEL.TXD
+#define PSELCTS       PSEL.CTS
+#define PSELRXD       PSEL.RXD
+
+/* TWI */
+/* The registers PSELSCL, PSELSDA were restructured into a struct. */
+#define PSELSCL       PSEL.SCL
+#define PSELSDA       PSEL.SDA
+
+
+/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */
+
+/* I2S */
+/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
+#define I2S_ENABLE_ENABLE_DISABLE           I2S_ENABLE_ENABLE_Disabled
+#define I2S_ENABLE_ENABLE_ENABLE            I2S_ENABLE_ENABLE_Enabled
+#define I2S_CONFIG_MODE_MODE_MASTER         I2S_CONFIG_MODE_MODE_Master
+#define I2S_CONFIG_MODE_MODE_SLAVE          I2S_CONFIG_MODE_MODE_Slave
+#define I2S_CONFIG_RXEN_RXEN_DISABLE        I2S_CONFIG_RXEN_RXEN_Disabled
+#define I2S_CONFIG_RXEN_RXEN_ENABLE         I2S_CONFIG_RXEN_RXEN_Enabled
+#define I2S_CONFIG_TXEN_TXEN_DISABLE        I2S_CONFIG_TXEN_TXEN_Disabled
+#define I2S_CONFIG_TXEN_TXEN_ENABLE         I2S_CONFIG_TXEN_TXEN_Enabled
+#define I2S_CONFIG_MCKEN_MCKEN_DISABLE      I2S_CONFIG_MCKEN_MCKEN_Disabled
+#define I2S_CONFIG_MCKEN_MCKEN_ENABLE       I2S_CONFIG_MCKEN_MCKEN_Enabled
+#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT       I2S_CONFIG_SWIDTH_SWIDTH_8Bit
+#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT      I2S_CONFIG_SWIDTH_SWIDTH_16Bit
+#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT      I2S_CONFIG_SWIDTH_SWIDTH_24Bit
+#define I2S_CONFIG_ALIGN_ALIGN_LEFT         I2S_CONFIG_ALIGN_ALIGN_Left
+#define I2S_CONFIG_ALIGN_ALIGN_RIGHT        I2S_CONFIG_ALIGN_ALIGN_Right
+#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED    I2S_CONFIG_FORMAT_FORMAT_Aligned
+#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
+#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT   I2S_CONFIG_CHANNELS_CHANNELS_Left
+#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT  I2S_CONFIG_CHANNELS_CHANNELS_Right
+
+/* LPCOMP */
+/* Corrected typo in RESULT register. */
+#define LPCOMP_RESULT_RESULT_Bellow         LPCOMP_RESULT_RESULT_Below
+
+
+/*lint --flb "Leave library region" */
+
+#endif /* NRF51_TO_NRF52840_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/ble_flash/ble_flash.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,312 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "ble_flash.h"
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include "nrf_soc.h"
+#include "nordic_common.h"
+#include "nrf_error.h"
+#include "nrf.h"
+#include "app_util.h"
+
+
+static volatile bool m_radio_active = false;  /**< TRUE if radio is active (or about to become active), FALSE otherwise. */
+
+
+uint16_t ble_flash_crc16_compute(uint8_t * p_data, uint16_t size, uint16_t * p_crc)
+{
+    uint16_t i;
+    uint16_t crc = (p_crc == NULL) ? 0xffff : *p_crc;
+
+    for (i = 0; i < size; i++)
+    {
+        crc  = (unsigned char)(crc >> 8) | (crc << 8);
+        crc ^= p_data[i];
+        crc ^= (unsigned char)(crc & 0xff) >> 4;
+        crc ^= (crc << 8) << 4;
+        crc ^= ((crc & 0xff) << 4) << 1;
+    }
+    return crc;
+}
+
+
+/**@brief Function for erasing a page in flash.
+ *
+ * @param[in]  p_page  Pointer to first word in page to be erased.
+ */
+static void flash_page_erase(uint32_t * p_page)
+{
+    // Turn on flash erase enable and wait until the NVMC is ready.
+    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Een << NVMC_CONFIG_WEN_Pos);
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+        // Do nothing.
+    }
+
+    // Erase page.
+    NRF_NVMC->ERASEPAGE = (uint32_t)p_page;
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+        // Do nothing.
+    }
+
+    // Turn off flash erase enable and wait until the NVMC is ready.
+    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos);
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+        // Do nothing
+    }
+}
+
+
+/**@brief Function for writing one word to flash. Unprotected write, which can interfere with radio communication.
+ *
+ * @details This function DOES NOT use the m_radio_active variable, but will force the write even
+ *          when the radio is active. To be used only from @ref ble_flash_page_write.
+ *
+ * @note Flash location to be written must have been erased previously.
+ *
+ * @param[in]  p_address   Pointer to flash location to be written.
+ * @param[in]  value       Value to write to flash.
+ */
+static void flash_word_unprotected_write(uint32_t * p_address, uint32_t value)
+{
+    // Turn on flash write enable and wait until the NVMC is ready.
+    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos);
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+        // Do nothing.
+    }
+    *p_address = value;
+
+    // Wait flash write to finish
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+        // Do nothing.
+    }
+
+    // Turn off flash write enable and wait until the NVMC is ready.
+    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos);
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+        // Do nothing.
+    }
+}
+
+
+/**@brief Function for writing one word to flash.
+ *
+ * @note Flash location to be written must have been erased previously.
+ *
+ * @param[in]  p_address   Pointer to flash location to be written.
+ * @param[in]  value       Value to write to flash.
+ */
+static void flash_word_write(uint32_t * p_address, uint32_t value)
+{
+    // If radio is active, wait for it to become inactive.
+    while (m_radio_active)
+    {
+        // Do nothing (just wait for radio to become inactive).
+        (void) sd_app_evt_wait();
+    }
+
+    // Turn on flash write enable and wait until the NVMC is ready.
+    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos);
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+        // Do nothing.
+    }
+
+    *p_address = value;
+    // Wait flash write to finish
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+        // Do nothing.
+    }
+    // Turn off flash write enable and wait until the NVMC is ready.
+    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos);
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+        // Do nothing
+    }
+}
+
+
+uint32_t ble_flash_word_write(uint32_t * p_address, uint32_t value)
+{
+    flash_word_write(p_address, value);
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_flash_block_write(uint32_t * p_address, uint32_t * p_in_array, uint16_t word_count)
+{
+    uint16_t i;
+
+    for (i = 0; i < word_count; i++)
+    {
+        flash_word_write(p_address, p_in_array[i]);
+        p_address++;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_flash_page_erase(uint8_t page_num)
+{
+    uint32_t * p_page = (uint32_t *)(BLE_FLASH_PAGE_SIZE * page_num);
+    flash_page_erase(p_page);
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_flash_page_write(uint8_t page_num, uint32_t * p_in_array, uint8_t word_count)
+{
+    int        i;
+    uint32_t * p_page;
+    uint32_t * p_curr_addr;
+    uint16_t   in_data_crc;
+    uint16_t   flash_crc;
+    uint32_t   flash_header;
+
+    p_page      = (uint32_t *)(BLE_FLASH_PAGE_SIZE * page_num);
+    p_curr_addr = p_page;
+
+    // Calculate CRC of the data to write.
+    in_data_crc = ble_flash_crc16_compute((uint8_t *)p_in_array,
+                                          word_count * sizeof(uint32_t),
+                                          NULL);
+
+    // Compare the calculated to the one in flash.
+    flash_header = *p_curr_addr;
+    flash_crc    = (uint16_t)flash_header;
+
+    if (flash_crc == in_data_crc)
+    {
+        // Data is the same as the data already stored in flash, return without modifying flash.
+        return NRF_SUCCESS;
+    }
+
+    // Erase flash page
+    flash_page_erase(p_page);
+
+    // Reserve space for magic number (for detecting if flash content is valid).
+    p_curr_addr++;
+
+    // Reserve space for saving word_count.
+    p_curr_addr++;
+
+    // Write data
+    for (i = 0; i < word_count; i++)
+    {
+        flash_word_unprotected_write(p_curr_addr, p_in_array[i]);
+        p_curr_addr++;
+    }
+
+    // Write number of elements.
+    flash_word_write(p_page + 1, (uint32_t)(word_count));
+
+    // Write magic number and CRC to indicate that flash content is valid.
+    flash_header = BLE_FLASH_MAGIC_NUMBER | (uint32_t)in_data_crc;
+    flash_word_write(p_page, flash_header);
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_flash_page_read(uint8_t page_num, uint32_t * p_out_array, uint8_t * p_word_count)
+{
+    int        byte_count;
+    uint32_t * p_page;
+    uint32_t * p_curr_addr;
+    uint32_t   flash_header;
+    uint32_t   calc_header;
+    uint16_t   calc_crc;
+    uint32_t   tmp;
+
+    p_page      = (uint32_t *)(BLE_FLASH_PAGE_SIZE * page_num);
+    p_curr_addr = p_page;
+
+    // Check if block is valid
+    flash_header = *p_curr_addr;
+    tmp = flash_header & 0xFFFF0000;
+    if (tmp != BLE_FLASH_MAGIC_NUMBER)
+    {
+        *p_word_count = 0;
+        return NRF_ERROR_NOT_FOUND;
+    }
+    p_curr_addr++;
+
+    // Read number of elements
+    *p_word_count = (uint8_t)(*(p_curr_addr));
+    p_curr_addr++;
+
+    // Read data
+    byte_count = (*p_word_count) * sizeof(uint32_t);
+    memcpy(p_out_array, p_curr_addr, byte_count);
+
+    // Check CRC
+    calc_crc = ble_flash_crc16_compute((uint8_t *)p_out_array,
+                                       (*p_word_count) * sizeof(uint32_t),
+                                       NULL);
+    calc_header = BLE_FLASH_MAGIC_NUMBER | (uint32_t)calc_crc;
+
+    if (calc_header != flash_header)
+    {
+        return NRF_ERROR_NOT_FOUND;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_flash_page_addr(uint8_t page_num, uint32_t ** pp_page_addr)
+{
+    *pp_page_addr = (uint32_t *)(BLE_FLASH_PAGE_SIZE * page_num);
+    return NRF_SUCCESS;
+}
+
+
+void ble_flash_on_radio_active_evt(bool radio_active)
+{
+    m_radio_active = radio_active;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/ble_flash/ble_flash.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,177 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup ble_flash_module Flash Manager
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Module for accessing flash memory.
+ *
+ * @details It contains functions for reading, writing and erasing one page in flash.
+ *
+ *          The module uses the first 32 bits of the flash page to write a magic number in order to
+ *          determine if the page has been written or not.
+ *
+ * @note Be careful not to use a page number in the SoftDevice area (which currently occupies the
+ *       range 0 to 127), or in your application space! In both cases, this would end up
+ *       with a hard fault.
+ */
+
+#ifndef BLE_FLASH_H__
+#define BLE_FLASH_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BLE_FLASH_PAGE_SIZE     ((uint16_t)NRF_FICR->CODEPAGESIZE)  /**< Size of one flash page. */
+#define BLE_FLASH_MAGIC_NUMBER  0x45DE0000                          /**< Magic value to identify if flash contains valid data. */
+#define BLE_FLASH_EMPTY_MASK    0xFFFFFFFF                          /**< Bit mask that defines an empty address in flash. */
+
+
+/**@brief Macro for getting the end of the flash available for application.
+ *
+ * @details    The result flash page number indicates the end boundary of the flash available
+ *             to the application. If a bootloader is used, the end will be the start of the
+ *             bootloader region. Otherwise, the end will be the size of the flash.
+ */
+#define BLE_FLASH_PAGE_END \
+    ((NRF_UICR->NRFFW[0] != BLE_FLASH_EMPTY_MASK) \
+        ? (NRF_UICR->NRFFW[0] / BLE_FLASH_PAGE_SIZE) \
+        : NRF_FICR->CODESIZE)
+
+/**@brief Function for erasing the specified flash page, and then writes the given data to this page.
+ *
+ * @warning This operation blocks the CPU. DO NOT use while in a connection!
+ *
+ * @param[in]  page_num     Page number to update.
+ * @param[in]  p_in_array   Pointer to a RAM area containing the elements to write in flash.
+ *                          This area has to be 32 bits aligned.
+ * @param[in]  word_count   Number of 32 bits words to write in flash.
+ *
+ * @return     NRF_SUCCESS on successful flash write, otherwise an error code.
+ */
+uint32_t ble_flash_page_write(uint8_t page_num, uint32_t * p_in_array, uint8_t word_count);
+
+/**@brief Function for reading data from flash to RAM.
+ *
+ * @param[in]  page_num       Page number to read.
+ * @param[out] p_out_array    Pointer to a RAM area where the found data will be written.
+ *                            This area has to be 32 bits aligned.
+ * @param[out] p_word_count   Number of 32 bits words read.
+ *
+ * @return     NRF_SUCCESS on successful upload, NRF_ERROR_NOT_FOUND if no valid data has been found
+ *             in flash (first 32 bits not equal to the MAGIC_NUMBER + CRC).
+ */
+uint32_t ble_flash_page_read(uint8_t page_num, uint32_t * p_out_array, uint8_t * p_word_count);
+
+/**@brief Function for erasing a flash page.
+ *
+ * @note This operation blocks the CPU, so it should not be done while the radio is running!
+ *
+ * @param[in]  page_num   Page number to erase.
+ *
+ * @return     NRF_SUCCESS on success, an error_code otherwise.
+ */
+uint32_t ble_flash_page_erase(uint8_t page_num);
+
+/**@brief Function for writing one word to flash.
+ *
+ * @note Flash location to be written must have been erased previously.
+ *
+ * @param[in]  p_address   Pointer to flash location to be written.
+ * @param[in]  value       Value to write to flash.
+ *
+ * @return     NRF_SUCCESS.
+ */
+uint32_t ble_flash_word_write(uint32_t * p_address, uint32_t value);
+
+/**@brief Function for writing a data block to flash.
+ *
+ * @note Flash locations to be written must have been erased previously.
+ *
+ * @param[in]  p_address    Pointer to start of flash location to be written.
+ * @param[in]  p_in_array   Pointer to start of flash block to be written.
+ * @param[in]  word_count   Number of words to be written.
+ *
+ * @return     NRF_SUCCESS.
+ */
+uint32_t ble_flash_block_write(uint32_t * p_address, uint32_t * p_in_array, uint16_t word_count);
+
+/**@brief Function for computing pointer to start of specified flash page.
+ *
+ * @param[in]  page_num       Page number.
+ * @param[out] pp_page_addr   Pointer to start of flash page.
+ *
+ * @return     NRF_SUCCESS.
+ */
+uint32_t ble_flash_page_addr(uint8_t page_num, uint32_t ** pp_page_addr);
+
+/**@brief Function for calculating a 16 bit CRC using the CRC-16-CCITT scheme.
+ *
+ * @param[in]  p_data   Pointer to data on which the CRC is to be calulated.
+ * @param[in]  size     Number of bytes on which the CRC is to be calulated.
+ * @param[in]  p_crc    Initial CRC value (if NULL, a preset value is used as the initial value).
+ *
+ * @return     Calculated CRC.
+ */
+uint16_t ble_flash_crc16_compute(uint8_t * p_data, uint16_t size, uint16_t * p_crc);
+
+/**@brief Function for handling flashing module Radio Notification event.
+ *
+ * @note For flash writing to work safely while in a connection or while advertising, this function
+ *       MUST be called from the Radio Notification module's event handler (see
+ *       @ref ble_radio_notification for details).
+ *
+ * @param[in]  radio_active   TRUE if radio is active (or about to become active), FALSE otherwise.
+ */
+void ble_flash_on_radio_active_evt(bool radio_active);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // BLE_FLASH_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/clock/nrf_drv_clock.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,597 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(CLOCK)
+
+#include "nrf_drv_clock.h"
+#include "nrf_error.h"
+#include "app_util_platform.h"
+#ifdef SOFTDEVICE_PRESENT
+#include "softdevice_handler.h"
+#include "nrf_sdm.h"
+#include "nrf_soc.h"
+#endif
+
+#define NRF_LOG_MODULE_NAME "CLOCK"
+
+#if CLOCK_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       CLOCK_CONFIG_LOG_LEVEL
+#define NRF_LOG_INFO_COLOR  CLOCK_CONFIG_INFO_COLOR
+#define NRF_LOG_DEBUG_COLOR CLOCK_CONFIG_DEBUG_COLOR
+#define EVT_TO_STR(event)   (event == NRF_CLOCK_EVENT_HFCLKSTARTED ? "NRF_CLOCK_EVENT_HFCLKSTARTED" :        \
+                            (event == NRF_CLOCK_EVENT_LFCLKSTARTED ? "NRF_CLOCK_EVENT_LFCLKSTARTED" :        \
+                            (event == NRF_CLOCK_EVENT_DONE ? "NRF_CLOCK_EVENT_DONE" :                        \
+                            (event == NRF_CLOCK_EVENT_CTTO ? "NRF_CLOCK_EVENT_CTTO" : "UNKNOWN EVENT"))))
+#else //CLOCK_CONFIG_LOG_ENABLED
+#define EVT_TO_STR(event)   ""
+#define NRF_LOG_LEVEL       0
+#endif //CLOCK_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+
+
+/* Validate configuration */
+INTERRUPT_PRIORITY_VALIDATION(CLOCK_CONFIG_IRQ_PRIORITY);
+
+/*lint -save -e652 */
+#define NRF_CLOCK_LFCLK_RC    CLOCK_LFCLKSRC_SRC_RC
+#define NRF_CLOCK_LFCLK_Xtal  CLOCK_LFCLKSRC_SRC_Xtal
+#define NRF_CLOCK_LFCLK_Synth CLOCK_LFCLKSRC_SRC_Synth
+/*lint -restore */
+
+#if (CLOCK_CONFIG_LF_SRC == NRF_CLOCK_LFCLK_RC) && !defined(SOFTDEVICE_PRESENT)
+#define CALIBRATION_SUPPORT 1
+#else
+#define CALIBRATION_SUPPORT 0
+#endif
+typedef enum
+{
+    CAL_STATE_IDLE,
+    CAL_STATE_CT,
+    CAL_STATE_HFCLK_REQ,
+    CAL_STATE_CAL,
+    CAL_STATE_ABORT,
+} nrf_drv_clock_cal_state_t;
+
+/**@brief CLOCK control block. */
+typedef struct
+{
+    bool                                    module_initialized; /*< Indicate the state of module */
+    volatile bool                           hfclk_on;           /*< High-frequency clock state. */
+    volatile bool                           lfclk_on;           /*< Low-frequency clock state. */
+    volatile uint32_t                       hfclk_requests;     /*< High-frequency clock request counter. */
+    volatile nrf_drv_clock_handler_item_t * p_hf_head;
+    volatile uint32_t                       lfclk_requests;     /*< Low-frequency clock request counter. */
+    volatile nrf_drv_clock_handler_item_t * p_lf_head;
+#if CALIBRATION_SUPPORT
+    nrf_drv_clock_handler_item_t            cal_hfclk_started_handler_item;
+    nrf_drv_clock_event_handler_t           cal_done_handler;
+    volatile nrf_drv_clock_cal_state_t      cal_state;
+#endif // CALIBRATION_SUPPORT
+} nrf_drv_clock_cb_t;
+
+static nrf_drv_clock_cb_t m_clock_cb;
+
+
+/**@brief Function for starting LFCLK. This function will return immediately without waiting for start.
+ */
+static void lfclk_start(void)
+{
+    nrf_clock_event_clear(NRF_CLOCK_EVENT_LFCLKSTARTED);
+    nrf_clock_int_enable(NRF_CLOCK_INT_LF_STARTED_MASK);
+    nrf_clock_task_trigger(NRF_CLOCK_TASK_LFCLKSTART);
+}
+
+/**@brief Function for stopping LFCLK and calibration (if it was set up).
+ */
+static void lfclk_stop(void)
+{
+#if CALIBRATION_SUPPORT
+    (void)nrf_drv_clock_calibration_abort();
+#endif
+
+#ifdef SOFTDEVICE_PRESENT
+    // If LFCLK is requested to stop while SD is still enabled,
+    // it indicates an error in the application.
+    // Enabling SD should increment the LFCLK request.
+    ASSERT(!softdevice_handler_is_enabled());
+#endif // SOFTDEVICE_PRESENT
+
+    nrf_clock_task_trigger(NRF_CLOCK_TASK_LFCLKSTOP);
+    while (nrf_clock_lf_is_running())
+    {}
+    m_clock_cb.lfclk_on = false;
+}
+
+static void hfclk_start(void)
+{
+#ifdef SOFTDEVICE_PRESENT
+    if (softdevice_handler_is_enabled())
+    {
+        (void)sd_clock_hfclk_request();
+        return;
+    }
+#endif // SOFTDEVICE_PRESENT
+
+    nrf_clock_event_clear(NRF_CLOCK_EVENT_HFCLKSTARTED);
+    nrf_clock_int_enable(NRF_CLOCK_INT_HF_STARTED_MASK);
+    nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTART);
+}
+
+static void hfclk_stop(void)
+{
+#ifdef SOFTDEVICE_PRESENT
+    if (softdevice_handler_is_enabled())
+    {
+        (void)sd_clock_hfclk_release();
+        return;
+    }
+#endif // SOFTDEVICE_PRESENT
+
+    nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTOP);
+    while (nrf_clock_hf_is_running(NRF_CLOCK_HFCLK_HIGH_ACCURACY))
+    {}
+    m_clock_cb.hfclk_on = false;
+}
+
+bool nrf_drv_clock_init_check(void)
+{
+    return m_clock_cb.module_initialized;
+}
+
+ret_code_t nrf_drv_clock_init(void)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+    if (m_clock_cb.module_initialized)
+    {
+        err_code = NRF_ERROR_MODULE_ALREADY_INITIALIZED;
+    }
+    else
+    {
+        m_clock_cb.p_hf_head      = NULL;
+        m_clock_cb.hfclk_requests = 0;
+        m_clock_cb.p_lf_head      = NULL;
+        m_clock_cb.lfclk_requests = 0;
+        nrf_drv_common_power_clock_irq_init();
+#ifdef SOFTDEVICE_PRESENT
+        if (!softdevice_handler_is_enabled())
+#endif
+        {
+            nrf_clock_lf_src_set((nrf_clock_lfclk_t)CLOCK_CONFIG_LF_SRC);
+        }
+
+#if CALIBRATION_SUPPORT
+        m_clock_cb.cal_state = CAL_STATE_IDLE;
+#endif
+
+        m_clock_cb.module_initialized = true;
+    }
+
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n",
+        (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+void nrf_drv_clock_uninit(void)
+{
+    ASSERT(m_clock_cb.module_initialized);
+    nrf_drv_common_clock_irq_disable();
+    nrf_clock_int_disable(0xFFFFFFFF);
+
+    lfclk_stop();
+    hfclk_stop();
+    m_clock_cb.module_initialized = false;
+    NRF_LOG_INFO("Uninitialized.\r\n");
+}
+
+static void item_enqueue(nrf_drv_clock_handler_item_t ** p_head,
+                         nrf_drv_clock_handler_item_t * p_item)
+{
+    nrf_drv_clock_handler_item_t * p_next = *p_head;
+    while(p_next)
+    {
+        if(p_next == p_item)
+        {
+            return;
+        }
+        p_next = p_next->p_next;
+    }
+
+    p_item->p_next = (*p_head ? *p_head : NULL);
+    *p_head = p_item;
+}
+
+static nrf_drv_clock_handler_item_t * item_dequeue(nrf_drv_clock_handler_item_t ** p_head)
+{
+    nrf_drv_clock_handler_item_t * p_item = *p_head;
+    if (p_item)
+    {
+        *p_head = p_item->p_next;
+    }
+    return p_item;
+}
+
+void nrf_drv_clock_lfclk_request(nrf_drv_clock_handler_item_t * p_handler_item)
+{
+    ASSERT(m_clock_cb.module_initialized);
+
+    if (m_clock_cb.lfclk_on)
+    {
+        if (p_handler_item)
+        {
+            p_handler_item->event_handler(NRF_DRV_CLOCK_EVT_LFCLK_STARTED);
+        }
+        CRITICAL_REGION_ENTER();
+        ++(m_clock_cb.lfclk_requests);
+        CRITICAL_REGION_EXIT();
+    }
+    else
+    {
+        CRITICAL_REGION_ENTER();
+        if (p_handler_item)
+        {
+            item_enqueue((nrf_drv_clock_handler_item_t **)&m_clock_cb.p_lf_head,
+                p_handler_item);
+        }
+        if (m_clock_cb.lfclk_requests == 0)
+        {
+            lfclk_start();
+        }
+        ++(m_clock_cb.lfclk_requests);
+        CRITICAL_REGION_EXIT();
+    }
+
+    ASSERT(m_clock_cb.lfclk_requests > 0);
+}
+
+void nrf_drv_clock_lfclk_release(void)
+{
+    ASSERT(m_clock_cb.module_initialized);
+    ASSERT(m_clock_cb.lfclk_requests > 0);
+
+    CRITICAL_REGION_ENTER();
+    --(m_clock_cb.lfclk_requests);
+    if (m_clock_cb.lfclk_requests == 0)
+    {
+        lfclk_stop();
+    }
+    CRITICAL_REGION_EXIT();
+}
+
+bool nrf_drv_clock_lfclk_is_running(void)
+{
+    ASSERT(m_clock_cb.module_initialized);
+
+#ifdef SOFTDEVICE_PRESENT
+    if (softdevice_handler_is_enabled())
+    {
+        return true;
+    }
+#endif // SOFTDEVICE_PRESENT
+
+    return nrf_clock_lf_is_running();
+}
+
+void nrf_drv_clock_hfclk_request(nrf_drv_clock_handler_item_t * p_handler_item)
+{
+    ASSERT(m_clock_cb.module_initialized);
+
+    if (m_clock_cb.hfclk_on)
+    {
+        if (p_handler_item)
+        {
+            p_handler_item->event_handler(NRF_DRV_CLOCK_EVT_HFCLK_STARTED);
+        }
+        CRITICAL_REGION_ENTER();
+        ++(m_clock_cb.hfclk_requests);
+        CRITICAL_REGION_EXIT();
+    }
+    else
+    {
+        CRITICAL_REGION_ENTER();
+        if (p_handler_item)
+        {
+            item_enqueue((nrf_drv_clock_handler_item_t **)&m_clock_cb.p_hf_head,
+                p_handler_item);
+        }
+        if (m_clock_cb.hfclk_requests == 0)
+        {
+            hfclk_start();
+        }
+        ++(m_clock_cb.hfclk_requests);
+        CRITICAL_REGION_EXIT();
+    }
+
+    ASSERT(m_clock_cb.hfclk_requests > 0);
+}
+
+void nrf_drv_clock_hfclk_release(void)
+{
+    ASSERT(m_clock_cb.module_initialized);
+    ASSERT(m_clock_cb.hfclk_requests > 0);
+
+    CRITICAL_REGION_ENTER();
+    --(m_clock_cb.hfclk_requests);
+    if (m_clock_cb.hfclk_requests == 0)
+    {
+        hfclk_stop();
+    }
+    CRITICAL_REGION_EXIT();
+}
+
+bool nrf_drv_clock_hfclk_is_running(void)
+{
+    ASSERT(m_clock_cb.module_initialized);
+
+#ifdef SOFTDEVICE_PRESENT
+    if (softdevice_handler_is_enabled())
+    {
+        uint32_t is_running;
+        UNUSED_VARIABLE(sd_clock_hfclk_is_running(&is_running));
+        return (is_running ? true : false);
+    }
+#endif // SOFTDEVICE_PRESENT
+
+    return nrf_clock_hf_is_running(NRF_CLOCK_HFCLK_HIGH_ACCURACY);
+}
+
+#if CALIBRATION_SUPPORT
+static void clock_calibration_hf_started(nrf_drv_clock_evt_type_t event)
+{
+    if (m_clock_cb.cal_state == CAL_STATE_ABORT)
+    {
+        nrf_drv_clock_hfclk_release();
+        m_clock_cb.cal_state = CAL_STATE_IDLE;
+        if (m_clock_cb.cal_done_handler)
+        {
+            m_clock_cb.cal_done_handler(NRF_DRV_CLOCK_EVT_CAL_ABORTED);
+        }
+    }
+    else
+    {
+        nrf_clock_event_clear(NRF_CLOCK_EVENT_DONE);
+        nrf_clock_int_enable(NRF_CLOCK_INT_DONE_MASK);
+        m_clock_cb.cal_state = CAL_STATE_CAL;
+        nrf_clock_task_trigger(NRF_CLOCK_TASK_CAL);
+    }
+}
+#endif // CALIBRATION_SUPPORT
+
+ret_code_t nrf_drv_clock_calibration_start(uint8_t interval, nrf_drv_clock_event_handler_t handler)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+#if CALIBRATION_SUPPORT
+    ASSERT(m_clock_cb.cal_state == CAL_STATE_IDLE);
+    if (m_clock_cb.lfclk_on == false)
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+    }
+    else if (m_clock_cb.cal_state == CAL_STATE_IDLE)
+    {
+        m_clock_cb.cal_done_handler = handler;
+        m_clock_cb.cal_hfclk_started_handler_item.event_handler = clock_calibration_hf_started;
+        if (interval == 0)
+        {
+            m_clock_cb.cal_state = CAL_STATE_HFCLK_REQ;
+            nrf_drv_clock_hfclk_request(&m_clock_cb.cal_hfclk_started_handler_item);
+        }
+        else
+        {
+            m_clock_cb.cal_state = CAL_STATE_CT;
+            nrf_clock_cal_timer_timeout_set(interval);
+            nrf_clock_event_clear(NRF_CLOCK_EVENT_CTTO);
+            nrf_clock_int_enable(NRF_CLOCK_INT_CTTO_MASK);
+            nrf_clock_task_trigger(NRF_CLOCK_TASK_CTSTART);
+        }
+    }
+    else
+    {
+        err_code = NRF_ERROR_BUSY;
+    }
+    NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+#else
+    err_code = NRF_ERROR_FORBIDDEN;
+    NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+#endif // CALIBRATION_SUPPORT
+}
+
+ret_code_t nrf_drv_clock_calibration_abort(void)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+#if CALIBRATION_SUPPORT
+    CRITICAL_REGION_ENTER();
+    switch (m_clock_cb.cal_state)
+    {
+    case CAL_STATE_CT:
+        nrf_clock_int_disable(NRF_CLOCK_INT_CTTO_MASK);
+        nrf_clock_task_trigger(NRF_CLOCK_TASK_CTSTOP);
+        m_clock_cb.cal_state = CAL_STATE_IDLE;
+        if (m_clock_cb.cal_done_handler)
+        {
+            m_clock_cb.cal_done_handler(NRF_DRV_CLOCK_EVT_CAL_ABORTED);
+        }
+        break;
+    case CAL_STATE_HFCLK_REQ:
+        /* fall through. */
+    case CAL_STATE_CAL:
+        m_clock_cb.cal_state = CAL_STATE_ABORT;
+        break;
+    default:
+        break;
+    }
+    CRITICAL_REGION_EXIT();
+    
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+#else
+    err_code = NRF_ERROR_FORBIDDEN;
+    NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+#endif // CALIBRATION_SUPPORT
+}
+
+ret_code_t nrf_drv_clock_is_calibrating(bool * p_is_calibrating)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+#if CALIBRATION_SUPPORT
+    ASSERT(m_clock_cb.module_initialized);
+    *p_is_calibrating = (m_clock_cb.cal_state != CAL_STATE_IDLE);
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+#else
+    err_code = NRF_ERROR_FORBIDDEN;
+    NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+#endif // CALIBRATION_SUPPORT
+}
+
+__STATIC_INLINE void clock_clk_started_notify(nrf_drv_clock_evt_type_t evt_type)
+{
+    nrf_drv_clock_handler_item_t **p_head;
+    if (evt_type == NRF_DRV_CLOCK_EVT_HFCLK_STARTED)
+    {
+        p_head = (nrf_drv_clock_handler_item_t **)&m_clock_cb.p_hf_head;
+    }
+    else
+    {
+        p_head = (nrf_drv_clock_handler_item_t **)&m_clock_cb.p_lf_head;
+    }
+
+    while (1)
+    {
+        nrf_drv_clock_handler_item_t * p_item = item_dequeue(p_head);
+        if (!p_item)
+        {
+            break;
+        }
+
+        p_item->event_handler(evt_type);
+    }
+}
+
+#if NRF_DRV_COMMON_POWER_CLOCK_ISR
+void nrf_drv_clock_onIRQ(void)
+#else
+void POWER_CLOCK_IRQHandler(void)
+#endif
+{
+    if (nrf_clock_event_check(NRF_CLOCK_EVENT_HFCLKSTARTED))
+    {
+        nrf_clock_event_clear(NRF_CLOCK_EVENT_HFCLKSTARTED);
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_CLOCK_EVENT_HFCLKSTARTED));
+        nrf_clock_int_disable(NRF_CLOCK_INT_HF_STARTED_MASK);
+        m_clock_cb.hfclk_on = true;
+        clock_clk_started_notify(NRF_DRV_CLOCK_EVT_HFCLK_STARTED);
+    }
+    if (nrf_clock_event_check(NRF_CLOCK_EVENT_LFCLKSTARTED))
+    {
+        nrf_clock_event_clear(NRF_CLOCK_EVENT_LFCLKSTARTED);
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_CLOCK_EVENT_LFCLKSTARTED));
+        nrf_clock_int_disable(NRF_CLOCK_INT_LF_STARTED_MASK);
+        m_clock_cb.lfclk_on = true;
+        clock_clk_started_notify(NRF_DRV_CLOCK_EVT_LFCLK_STARTED);
+    }
+#if CALIBRATION_SUPPORT
+    if (nrf_clock_event_check(NRF_CLOCK_EVENT_CTTO))
+    {
+        nrf_clock_event_clear(NRF_CLOCK_EVENT_CTTO);
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_CLOCK_EVENT_CTTO));
+        nrf_clock_int_disable(NRF_CLOCK_INT_CTTO_MASK);
+        nrf_drv_clock_hfclk_request(&m_clock_cb.cal_hfclk_started_handler_item);
+    }
+
+    if (nrf_clock_event_check(NRF_CLOCK_EVENT_DONE))
+    {
+        nrf_clock_event_clear(NRF_CLOCK_EVENT_DONE);
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_CLOCK_EVENT_DONE));
+        nrf_clock_int_disable(NRF_CLOCK_INT_DONE_MASK);
+        nrf_drv_clock_hfclk_release();
+        bool aborted = (m_clock_cb.cal_state == CAL_STATE_ABORT);
+        m_clock_cb.cal_state = CAL_STATE_IDLE;
+        if (m_clock_cb.cal_done_handler)
+        {
+            m_clock_cb.cal_done_handler(aborted ?
+                NRF_DRV_CLOCK_EVT_CAL_ABORTED : NRF_DRV_CLOCK_EVT_CAL_DONE);
+        }
+    }
+#endif // CALIBRATION_SUPPORT
+}
+
+#ifdef SOFTDEVICE_PRESENT
+
+void nrf_drv_clock_on_soc_event(uint32_t evt_id)
+{
+    if (evt_id == NRF_EVT_HFCLKSTARTED)
+    {
+        clock_clk_started_notify(NRF_DRV_CLOCK_EVT_HFCLK_STARTED);
+    }
+}
+
+void nrf_drv_clock_on_sd_enable(void)
+{
+    CRITICAL_REGION_ENTER();
+    /* Make sure that nrf_drv_clock module is initialized */
+    if (!m_clock_cb.module_initialized)
+    {
+        (void)nrf_drv_clock_init();
+    }
+    /* SD is one of the LFCLK requesters, but it will enable it by itself. */
+    ++(m_clock_cb.lfclk_requests);
+    m_clock_cb.lfclk_on = true;
+    CRITICAL_REGION_EXIT();
+}
+
+void nrf_drv_clock_on_sd_disable(void)
+{
+    /* Reinit interrupts */
+    ASSERT(m_clock_cb.module_initialized);
+    nrf_drv_common_irq_enable(POWER_CLOCK_IRQn, CLOCK_CONFIG_IRQ_PRIORITY);
+
+    /* SD leaves LFCLK enabled - disable it if it is no longer required. */
+    nrf_drv_clock_lfclk_release();
+}
+
+#endif // SOFTDEVICE_PRESENT
+
+#undef NRF_CLOCK_LFCLK_RC
+#undef NRF_CLOCK_LFCLK_Xtal
+#undef NRF_CLOCK_LFCLK_Synth
+
+#endif // NRF_MODULE_ENABLED(CLOCK)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/clock/nrf_drv_clock.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,313 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_DRV_CLOCK_H__
+#define NRF_DRV_CLOCK_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "nrf_assert.h"
+#include "nrf_clock.h"
+#include "sdk_config.h"
+#include "nrf_drv_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ *
+ * @addtogroup nrf_clock Clock HAL and driver
+ * @ingroup nrf_drivers
+ * @brief Clock APIs.
+ * @details The clock HAL provides basic APIs for accessing the registers of the clock.
+ * The clock driver provides APIs on a higher level.
+ *
+ * @defgroup nrf_drv_clock Clock driver
+ * @{
+ * @ingroup nrf_clock
+ * @brief Driver for managing the low-frequency clock (LFCLK) and the high-frequency clock (HFCLK).
+ */
+
+/**
+ * @brief Clock events.
+ */
+typedef enum
+{
+    NRF_DRV_CLOCK_EVT_HFCLK_STARTED, ///< HFCLK has been started.
+    NRF_DRV_CLOCK_EVT_LFCLK_STARTED, ///< LFCLK has been started.
+    NRF_DRV_CLOCK_EVT_CAL_DONE,      ///< Calibration is done.
+    NRF_DRV_CLOCK_EVT_CAL_ABORTED,   ///< Calibration has been aborted.
+} nrf_drv_clock_evt_type_t;
+
+/**
+ * @brief Clock event handler.
+ *
+ * @param[in] event  Event.
+ */
+typedef void (*nrf_drv_clock_event_handler_t)(nrf_drv_clock_evt_type_t event);
+
+// Forward declaration of the nrf_drv_clock_handler_item_t type.
+typedef struct nrf_drv_clock_handler_item_s nrf_drv_clock_handler_item_t;
+
+struct nrf_drv_clock_handler_item_s
+{
+    nrf_drv_clock_handler_item_t * p_next;        ///< A pointer to the next handler that should be called when the clock is started.
+    nrf_drv_clock_event_handler_t  event_handler; ///< Function to be called when the clock is started.
+};
+
+/**
+ * @brief Function for checking if driver is already initialized
+ *
+ * This function is used to check whatever common POWER_CLOCK common interrupt
+ * should be disabled or not if @ref nrf_drv_power tries to disable the interrupt.
+ *
+ * @retval true  Driver is initialized
+ * @retval false Driver is uninitialized
+ */
+bool nrf_drv_clock_init_check(void);
+
+/**
+ * @brief Function for initializing the nrf_drv_clock module.
+ *
+ * After initialization, the module is in power off state (clocks are not requested).
+ *
+ * @retval     NRF_SUCCESS                           If the procedure was successful.
+ * @retval     NRF_ERROR_MODULE_ALREADY_INITIALIZED  If the driver was already initialized.
+ */
+ret_code_t nrf_drv_clock_init(void);
+
+/**
+ * @brief Function for uninitializing the clock module.
+ *
+ */
+void nrf_drv_clock_uninit(void);
+
+/**
+ * @brief Function for requesting the LFCLK.
+ *
+ * The low-frequency clock can be requested by different modules
+ * or contexts. The driver ensures that the clock will be started only when it is requested
+ * the first time. If the clock is not ready but it was already started, the handler item that is
+ * provided as an input parameter is added to the list of handlers that will be notified
+ * when the clock is started. If the clock is already enabled, user callback is called from the
+ * current context.
+ *
+ * The first request will start the selected LFCLK source. If an event handler is
+ * provided, it will be called once the LFCLK is started. If the LFCLK was already started at this
+ * time, the event handler will be called from the context of this function. Additionally,
+ * the @ref nrf_drv_clock_lfclk_is_running function can be polled to check if the clock has started.
+ *
+ * @note When a SoftDevice is enabled, the LFCLK is always running and the driver cannot control it.
+ *
+ * @note The handler item provided by the user cannot be an automatic variable.
+ *
+ * @param[in] p_handler_item A pointer to the event handler structure.
+ */
+void nrf_drv_clock_lfclk_request(nrf_drv_clock_handler_item_t * p_handler_item);
+
+/**
+ * @brief Function for releasing the LFCLK.
+ *
+ * If there are no more requests, the LFCLK source will be stopped.
+ *
+ * @note When a SoftDevice is enabled, the LFCLK is always running.
+ */
+void nrf_drv_clock_lfclk_release(void);
+
+/**
+ * @brief Function for checking the LFCLK state.
+ *
+ * @retval true If the LFCLK is running.
+ * @retval false If the LFCLK is not running.
+ */
+bool nrf_drv_clock_lfclk_is_running(void);
+
+/**
+ * @brief Function for requesting the high-accuracy source HFCLK.
+ *
+ * The high-accuracy source
+ * can be requested by different modules or contexts. The driver ensures that the high-accuracy
+ * clock will be started only when it is requested the first time. If the clock is not ready
+ * but it was already started, the handler item that is provided as an input parameter is added
+ * to the list of handlers that will be notified when the clock is started.
+ *
+ * If an event handler is provided, it will be called once the clock is started. If the clock was already
+ * started at this time, the event handler will be called from the context of this function. Additionally,
+ * the @ref nrf_drv_clock_hfclk_is_running function can be polled to check if the clock has started.
+ *
+ * @note If a SoftDevice is running, the clock is managed by the SoftDevice and all requests are handled by
+ *       the SoftDevice. This function cannot be called from all interrupt priority levels in that case.
+ * @note The handler item provided by the user cannot be an automatic variable.
+ *
+ * @param[in] p_handler_item A pointer to the event handler structure.
+ */
+void nrf_drv_clock_hfclk_request(nrf_drv_clock_handler_item_t * p_handler_item);
+
+/**
+ * @brief Function for releasing the high-accuracy source HFCLK.
+ *
+ * If there are no more requests, the high-accuracy source will be released.
+ */
+void nrf_drv_clock_hfclk_release(void);
+
+/**
+ * @brief Function for checking the HFCLK state.
+ *
+ * @retval true If the HFCLK is running (for \nRFXX XTAL source).
+ * @retval false If the HFCLK is not running.
+ */
+bool nrf_drv_clock_hfclk_is_running(void);
+
+/**
+ * @brief Function for starting a single calibration process.
+ *
+ * This function can also delay the start of calibration by a user-specified value. The delay will use
+ * a low-power timer that is part of the CLOCK module. @ref nrf_drv_clock_is_calibrating can be called to
+ * check if calibration is still in progress. If a handler is provided, the user can be notified when
+ * calibration is completed. The ext calibration can be started from the handler context.
+ *
+ * The calibration process consists of three phases:
+ * - Delay (optional)
+ * - Requesting the high-accuracy HFCLK
+ * - Hardware-supported calibration
+ *
+ * @param[in]  delay   Time after which the calibration will be started (in 0.25 s units).
+ * @param[in]  handler NULL or user function to be called when calibration is completed or aborted.
+ *
+ * @retval     NRF_SUCCESS                        If the procedure was successful.
+ * @retval     NRF_ERROR_FORBIDDEN                If a SoftDevice is present or the selected LFCLK source is not an RC oscillator.
+ * @retval     NRF_ERROR_INVALID_STATE            If the low-frequency clock is off.
+ * @retval     NRF_ERROR_BUSY                     If calibration is in progress.
+ */
+ret_code_t nrf_drv_clock_calibration_start(uint8_t delay, nrf_drv_clock_event_handler_t handler);
+
+/**
+ * @brief Function for aborting calibration.
+ *
+ * This function aborts on-going calibration. If calibration was started, it cannot be stopped. If a handler
+ * was provided by @ref nrf_drv_clock_calibration_start, this handler will be called once
+ * aborted calibration is completed. @ref nrf_drv_clock_is_calibrating can also be used to check
+ * if the system is calibrating.
+ *
+ * @retval     NRF_SUCCESS                        If the procedure was successful.
+ * @retval     NRF_ERROR_FORBIDDEN                If a SoftDevice is present or the selected LFCLK source is not an RC oscillator.
+ */
+ret_code_t nrf_drv_clock_calibration_abort(void);
+
+/**
+ * @brief Function for checking if calibration is in progress.
+ *
+ * This function indicates that the system is
+ * in calibration if it is in any of the calibration process phases (see @ref nrf_drv_clock_calibration_start).
+ *
+ * @param[out] p_is_calibrating                   True if calibration is in progress, false if not.
+ *
+ * @retval     NRF_SUCCESS                        If the procedure was successful.
+ * @retval     NRF_ERROR_FORBIDDEN                If a SoftDevice is present or the selected LFCLK source is not an RC oscillator.
+ */
+ret_code_t nrf_drv_clock_is_calibrating(bool * p_is_calibrating);
+
+/**@brief Function for returning a requested task address for the clock driver module.
+ *
+ * @param[in]  task                               One of the peripheral tasks.
+ *
+ * @return     Task address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_clock_ppi_task_addr(nrf_clock_task_t task);
+
+/**@brief Function for returning a requested event address for the clock driver module.
+ *
+ * @param[in]  event                              One of the peripheral events.
+ *
+ * @return     Event address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_clock_ppi_event_addr(nrf_clock_event_t event);
+
+
+#ifdef SOFTDEVICE_PRESENT
+/**
+ * @brief Function called by the SoftDevice handler if an @ref nrf_soc event is received from the SoftDevice.
+ *
+ * @param[in] evt_id One of NRF_SOC_EVTS values.
+ */
+void nrf_drv_clock_on_soc_event(uint32_t evt_id);
+
+/**
+ * @brief Function called by the SoftDevice handler when the SoftDevice has been enabled.
+ *
+ * This function is called just after the SoftDevice has been properly enabled.
+ * Its main purpose is to mark that LFCLK has been requested by SD.
+ */
+void nrf_drv_clock_on_sd_enable(void);
+
+/**
+ * @brief Function called by the SoftDevice handler when the SoftDevice has been disabled.
+ *
+ * This function is called just after the SoftDevice has been properly disabled.
+ * It has two purposes:
+ * 1. Releases the LFCLK from the SD.
+ * 2. Reinitializes an interrupt after the SD releases POWER_CLOCK_IRQ.
+ */
+void nrf_drv_clock_on_sd_disable(void);
+
+#endif
+/**
+ *@}
+ **/
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+__STATIC_INLINE uint32_t nrf_drv_clock_ppi_task_addr(nrf_clock_task_t task)
+{
+    return nrf_clock_task_address_get(task);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_clock_ppi_event_addr(nrf_clock_event_t event)
+{
+    return nrf_clock_event_address_get(event);
+}
+#endif //SUPPRESS_INLINE_IMPLEMENTATION
+
+/*lint --flb "Leave library region" */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_CLOCK_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/common/nrf_drv_common.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,295 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include <stddef.h>
+#include "nrf_drv_common.h"
+#include "nrf_assert.h"
+#include "app_util_platform.h"
+#include "nrf_peripherals.h"
+
+#if NRF_DRV_COMMON_POWER_CLOCK_ISR
+#include "nrf_drv_power.h"
+#include "nrf_drv_clock.h"
+#endif
+#ifdef SOFTDEVICE_PRESENT
+#include "nrf_soc.h"
+#endif
+
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+
+#define NRF_LOG_MODULE_NAME "COMMON"
+
+#if COMMON_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       COMMON_CONFIG_LOG_LEVEL
+#define NRF_LOG_INFO_COLOR  COMMON_CONFIG_INFO_COLOR
+#define NRF_LOG_DEBUG_COLOR COMMON_CONFIG_DEBUG_COLOR
+#else //COMMON_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       0
+#endif //COMMON_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+
+typedef struct {
+    nrf_drv_irq_handler_t handler;
+    bool                  acquired;
+} shared_resource_t;
+
+// SPIM0, SPIS0, SPI0, TWIM0, TWIS0, TWI0
+#if (NRF_MODULE_ENABLED(SPI0) || NRF_MODULE_ENABLED(SPIS0) || NRF_MODULE_ENABLED(TWI0) || NRF_MODULE_ENABLED(TWIS0))
+    #define SERIAL_BOX_0_IN_USE
+    // [this checking may need a different form in unit tests, hence macro]
+    #ifndef IS_SERIAL_BOX_0
+        #define IS_SERIAL_BOX_0(p_per_base)  (p_per_base == NRF_SPI0)
+    #endif
+
+    static shared_resource_t m_serial_box_0 = { .acquired = false };
+    void SPI0_TWI0_IRQHandler(void)
+    {
+        ASSERT(m_serial_box_0.handler);
+        m_serial_box_0.handler();
+    }
+#endif // (NRF_MODULE_ENABLED(SPI0) || NRF_MODULE_ENABLED(SPIS0) || NRF_MODULE_ENABLED(TWI0) || NRF_MODULE_ENABLED(TWIS0))
+
+// SPIM1, SPIS1, SPI1, TWIM1, TWIS1, TWI1
+#if (NRF_MODULE_ENABLED(SPI1) || NRF_MODULE_ENABLED(SPIS1) || NRF_MODULE_ENABLED(TWI1) || NRF_MODULE_ENABLED(TWIS1))
+    #define SERIAL_BOX_1_IN_USE
+    // [this checking may need a different form in unit tests, hence macro]
+    #ifndef IS_SERIAL_BOX_1
+        #define IS_SERIAL_BOX_1(p_per_base)  (p_per_base == NRF_SPI1)
+    #endif
+
+    static shared_resource_t m_serial_box_1 = { .acquired = false };
+#ifdef TWIM_PRESENT
+    void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler(void)
+#else
+    void SPI1_TWI1_IRQHandler(void)
+#endif
+    {
+        ASSERT(m_serial_box_1.handler);
+        m_serial_box_1.handler();
+    }
+#endif // (NRF_MODULE_ENABLED(SPI1) || NRF_MODULE_ENABLED(SPIS1) || NRF_MODULE_ENABLED(TWI1) || NRF_MODULE_ENABLED(TWIS1))
+
+// SPIM2, SPIS2, SPI2
+#if (NRF_MODULE_ENABLED(SPI2) || NRF_MODULE_ENABLED(SPIS2))
+    #define SERIAL_BOX_2_IN_USE
+    // [this checking may need a different form in unit tests, hence macro]
+    #ifndef IS_SERIAL_BOX_2
+        #define IS_SERIAL_BOX_2(p_per_base)  (p_per_base == NRF_SPI2)
+    #endif
+
+    static shared_resource_t m_serial_box_2 = { .acquired = false };
+    void SPIM2_SPIS2_SPI2_IRQHandler(void)
+    {
+        ASSERT(m_serial_box_2.handler);
+        m_serial_box_2.handler();
+    }
+#endif // (NRF_MODULE_ENABLED(SPI2) || NRF_MODULE_ENABLED(SPIS2))
+
+// COMP, LPCOMP
+#if (NRF_MODULE_ENABLED(COMP) || NRF_MODULE_ENABLED(LPCOMP))
+    #define COMP_LPCOMP_IN_USE
+
+    #ifndef IS_COMP_LPCOMP
+        #define IS_COMP_LPCOMP(p_per_base)  ((p_per_base) == NRF_LPCOMP)
+    #endif
+
+    static shared_resource_t m_comp_lpcomp = { .acquired = false };
+    void LPCOMP_IRQHandler(void)
+    {
+        ASSERT(m_comp_lpcomp.handler);
+        m_comp_lpcomp.handler();
+    }
+#endif    // (NRF_MODULE_ENABLED(COMP) || NRF_MODULE_ENABLED(LPCOMP))
+
+#if defined(SERIAL_BOX_0_IN_USE) || \
+    defined(SERIAL_BOX_1_IN_USE) || \
+    defined(SERIAL_BOX_2_IN_USE) || \
+    defined(COMP_LPCOMP_IN_USE)
+static ret_code_t acquire_shared_resource(shared_resource_t * p_resource,
+                                          nrf_drv_irq_handler_t handler)
+{
+    ret_code_t err_code;
+    
+    bool busy = false;
+
+    CRITICAL_REGION_ENTER();
+    if (p_resource->acquired)
+    {
+        busy = true;
+    }
+    else
+    {
+        p_resource->acquired = true;
+    }
+    CRITICAL_REGION_EXIT();
+
+    if (busy)
+    {
+        err_code = NRF_ERROR_BUSY;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    p_resource->handler = handler;
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+#endif
+
+ret_code_t nrf_drv_common_per_res_acquire(void const * p_per_base,
+                                          nrf_drv_irq_handler_t handler)
+{
+#ifdef SERIAL_BOX_0_IN_USE
+    if (IS_SERIAL_BOX_0(p_per_base))
+    {
+        return acquire_shared_resource(&m_serial_box_0, handler);
+    }
+#endif
+
+#ifdef SERIAL_BOX_1_IN_USE
+    if (IS_SERIAL_BOX_1(p_per_base))
+    {
+        return acquire_shared_resource(&m_serial_box_1, handler);
+    }
+#endif
+
+#ifdef SERIAL_BOX_2_IN_USE
+    if (IS_SERIAL_BOX_2(p_per_base))
+    {
+        return acquire_shared_resource(&m_serial_box_2, handler);
+    }
+#endif
+
+#ifdef COMP_LPCOMP_IN_USE
+    if (IS_COMP_LPCOMP(p_per_base))
+    {
+        return acquire_shared_resource(&m_comp_lpcomp, handler);
+    }
+#endif
+    ret_code_t err_code;
+    
+    err_code = NRF_ERROR_INVALID_PARAM;
+    NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+void nrf_drv_common_per_res_release(void const * p_per_base)
+{
+#ifdef SERIAL_BOX_0_IN_USE
+    if (IS_SERIAL_BOX_0(p_per_base))
+    {
+        m_serial_box_0.acquired = false;
+    }
+    else
+#endif
+
+#ifdef SERIAL_BOX_1_IN_USE
+    if (IS_SERIAL_BOX_1(p_per_base))
+    {
+        m_serial_box_1.acquired = false;
+    }
+    else
+#endif
+
+#ifdef SERIAL_BOX_2_IN_USE
+    if (IS_SERIAL_BOX_2(p_per_base))
+    {
+        m_serial_box_2.acquired = false;
+    }
+    else
+#endif
+
+#ifdef COMP_LPCOMP_IN_USE
+    if (IS_COMP_LPCOMP(p_per_base))
+    {
+        m_comp_lpcomp.acquired = false;
+    }
+    else
+#endif
+
+    {}
+}
+
+#endif // NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+
+#if NRF_MODULE_ENABLED(POWER)
+void nrf_drv_common_power_irq_disable(void)
+{
+#if NRF_DRV_COMMON_POWER_CLOCK_ISR
+    if(!nrf_drv_clock_init_check())
+#endif
+    {
+        nrf_drv_common_irq_disable(POWER_CLOCK_IRQn);
+    }
+}
+#endif
+
+#if NRF_MODULE_ENABLED(CLOCK)
+void nrf_drv_common_clock_irq_disable(void)
+{
+#if NRF_DRV_COMMON_POWER_CLOCK_ISR
+    if(!nrf_drv_power_init_check())
+#endif
+    {
+        nrf_drv_common_irq_disable(POWER_CLOCK_IRQn);
+    }
+}
+#endif
+
+#if NRF_DRV_COMMON_POWER_CLOCK_ISR
+void POWER_CLOCK_IRQHandler(void)
+{
+    extern void nrf_drv_clock_onIRQ(void);
+    extern void nrf_drv_power_onIRQ(void);
+
+    nrf_drv_clock_onIRQ();
+    nrf_drv_power_onIRQ();
+}
+#endif // NRF_DRV_COMMON_POWER_CLOCK_ISR
+
+
+void nrf_drv_common_irq_enable(IRQn_Type IRQn, uint8_t priority)
+{
+    INTERRUPT_PRIORITY_ASSERT(priority);
+
+    NVIC_SetPriority(IRQn, priority);
+    NVIC_ClearPendingIRQ(IRQn);
+    NVIC_EnableIRQ(IRQn);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/common/nrf_drv_common.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,356 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_DRV_COMMON_H__
+#define NRF_DRV_COMMON_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf.h"
+#include "sdk_errors.h"
+#include "sdk_common.h"
+#include "nrf_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef NRF51
+#ifdef SOFTDEVICE_PRESENT
+#define INTERRUPT_PRIORITY_IS_VALID(pri) (((pri) == 1) || ((pri) == 3))
+#else
+#define INTERRUPT_PRIORITY_IS_VALID(pri) ((pri) < 4)
+#endif //SOFTDEVICE_PRESENT
+#else
+#ifdef SOFTDEVICE_PRESENT
+#define INTERRUPT_PRIORITY_IS_VALID(pri) ((((pri) > 1) && ((pri) < 4)) || (((pri) > 5) && ((pri) < 8)))
+#else
+#define INTERRUPT_PRIORITY_IS_VALID(pri) ((pri) < 8)
+#endif //SOFTDEVICE_PRESENT
+#endif //NRF52
+
+#define INTERRUPT_PRIORITY_VALIDATION(pri) STATIC_ASSERT(INTERRUPT_PRIORITY_IS_VALID((pri)))
+#define INTERRUPT_PRIORITY_ASSERT(pri)     ASSERT(INTERRUPT_PRIORITY_IS_VALID((pri)))
+
+/**
+ * @defgroup nrf_drv_common Peripheral drivers common module
+ * @{
+ * @ingroup nrf_drivers
+ */
+
+/**
+ * @brief Offset of event registers in every peripheral instance.
+ *
+ * This is the offset where event registers start in  every peripheral.
+ */
+#define NRF_DRV_COMMON_EVREGS_OFFSET 0x100U
+
+/**
+ * @brief The flag that is set when POWER_CLOCK ISR is implemented in common module
+ *
+ * This flag means that the function POWER_CLOCK_IRQHandler is implemented in
+ * nrf_drv_common.c file. In the @c clock and @c power modules functions
+ * nrf_drv_clock_onIRQ nrf_drv_power_onIRQ should be implemented
+ * and they would be called from common implementation.
+ *
+ * None of the checking is done here.
+ * The implementation functions in @c clock and @c power are required to handle
+ * correctly the case when they are called without any event bit set.
+ */
+#define NRF_DRV_COMMON_POWER_CLOCK_ISR (NRF_MODULE_ENABLED(CLOCK) && NRF_MODULE_ENABLED(POWER))
+
+/**
+ * @brief Driver state.
+ */
+typedef enum
+{
+    NRF_DRV_STATE_UNINITIALIZED, /**< Uninitialized. */
+    NRF_DRV_STATE_INITIALIZED, /**< Initialized but powered off. */
+    NRF_DRV_STATE_POWERED_ON
+} nrf_drv_state_t;
+
+/**
+ * @brief Driver power state selection.
+ */
+typedef enum
+{
+    NRF_DRV_PWR_CTRL_ON,   /**< Power on request. */
+    NRF_DRV_PWR_CTRL_OFF   /**< Power off request. */
+} nrf_drv_pwr_ctrl_t;
+
+/**
+ * @brief IRQ handler type.
+ */
+typedef void (*nrf_drv_irq_handler_t)(void);
+
+
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+
+/**
+ * @brief Function for acquiring shared peripheral resources associated with
+ *        the specified peripheral.
+ *
+ * Certain resources and registers are shared among peripherals that have
+ * the same ID (for example: SPI0, SPIM0, SPIS0, TWI0, TWIM0, and TWIS0).
+ * Only one of them can be utilized at a given time. This function reserves
+ * proper resources to be used by the specified peripheral.
+ * If PERIPHERAL_RESOURCE_SHARING_ENABLED is set to a non-zero value, IRQ
+ * handlers for peripherals that are sharing resources with others are
+ * implemented by the nrf_drv_common module instead of individual drivers.
+ * The drivers must then specify their interrupt handling routines and
+ * register them by using this function.
+ *
+ * @param[in] p_per_base Requested peripheral base pointer.
+ * @param[in] handler    Interrupt handler to register. May be NULL
+ *                       if interrupts are not used for the peripheral.
+ *
+ * @retval NRF_SUCCESS             If resources were acquired successfully.
+ * @retval NRF_ERROR_BUSY          If resources were already acquired.
+ * @retval NRF_ERROR_INVALID_PARAM If the specified peripheral is not enabled
+ *                                 or the peripheral does not share resources
+ *                                 with other peripherals.
+ */
+ret_code_t nrf_drv_common_per_res_acquire(void const * p_per_base,
+                                          nrf_drv_irq_handler_t handler);
+
+/**
+ * @brief Function for releasing shared resources reserved previously by
+ *        @ref nrf_drv_common_per_res_acquire() for the specified peripheral.
+ *
+ * @param[in] p_per_base Requested peripheral base pointer.
+ */
+void nrf_drv_common_per_res_release(void const * p_per_base);
+
+#endif // NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+
+
+/**
+ * @brief Function sets priority and enables NVIC interrupt
+ *
+ * @note Function checks if correct priority is used when softdevice is present
+ *
+ * @param[in] IRQn     Interrupt id
+ * @param[in] priority Interrupt priority
+ */
+void nrf_drv_common_irq_enable(IRQn_Type IRQn, uint8_t priority);
+
+#if NRF_MODULE_ENABLED(POWER)
+/**
+ * @brief Disable power IRQ
+ *
+ * Power and clock peripheral uses the same IRQ.
+ * This function disables POWER_CLOCK IRQ only if CLOCK driver
+ * is uninitialized.
+ *
+ * @sa nrf_drv_common_power_clock_irq_init
+ */
+void nrf_drv_common_power_irq_disable(void);
+#endif
+
+#if NRF_MODULE_ENABLED(CLOCK)
+/**
+ * @brief Disable clock IRQ
+ *
+ * Power and clock peripheral uses the same IRQ.
+ * This function disables POWER_CLOCK IRQ only if POWER driver
+ * is uninitialized.
+ *
+ * @sa nrf_drv_common_power_clock_irq_init
+ */
+void nrf_drv_common_clock_irq_disable(void);
+#endif
+
+/**
+ * @brief Check if interrupt is enabled
+ *
+ * Function that checks if selected interrupt is enabled.
+ *
+ * @param[in] IRQn     Interrupt id
+ *
+ * @retval true  Selected IRQ is enabled.
+ * @retval false Selected IRQ is disabled.
+ */
+__STATIC_INLINE bool nrf_drv_common_irq_enable_check(IRQn_Type IRQn);
+
+/**
+ * @brief Function disables NVIC interrupt
+ *
+ * @param[in] IRQn     Interrupt id
+ */
+__STATIC_INLINE void nrf_drv_common_irq_disable(IRQn_Type IRQn);
+
+/**
+ * @brief Convert bit position to event code
+ *
+ * Function for converting the bit position in INTEN register to event code
+ * that is equivalent to the offset of the event register from the beginning
+ * of peripheral instance.
+ *
+ * For example the result of this function can be casted directly to
+ * the types like @ref nrf_twis_event_t or @ref nrf_rng_event_t
+ *
+ * @param bit Bit position in INTEN register
+ * @return Event code to be casted to the right enum type or to be used in functions like
+ * @ref nrf_rng_event_get
+ *
+ * @sa nrf_drv_event_to_bitpos
+ */
+__STATIC_INLINE uint32_t nrf_drv_bitpos_to_event(uint32_t bit);
+
+/**
+ * @brief Convert event code to bit position
+ *
+ * This function can be used to get bit position in INTEN register from event code.
+ *
+ * @param event Event code that may be casted from enum values from types like
+ * @ref nrf_twis_event_t or @ref nrf_rng_event_t
+ * @return Bit position in INTEN register that corresponds to the given code.
+ *
+ * @sa nrf_drv_bitpos_to_event
+ */
+__STATIC_INLINE uint32_t nrf_drv_event_to_bitpos(uint32_t event);
+
+/**
+ * @brief Get interrupt number connected with given instance
+ *
+ * Function returns interrupt number for a given instance of any peripheral.
+ * @param[in] pinst Pointer to peripheral registry
+ * @return Interrupt number
+ */
+__STATIC_INLINE IRQn_Type nrf_drv_get_IRQn(void const * const pinst);
+
+#if NRF_MODULE_ENABLED(CLOCK) || NRF_MODULE_ENABLED(POWER)
+/**
+ * @brief Enable and setup power clock IRQ
+ *
+ * This function would be called from @ref nrf_drv_clock and @ref nrf_drv_power
+ * to enable related interrupt.
+ * This function avoids multiple interrupt configuration.
+ *
+ * @note
+ * This function is aviable only if @ref nrf_drv_clock or @ref nrf_drv_power
+ * module is enabled.
+ *
+ * @note
+ * If both @ref nrf_drv_clock and @ref nrf_drv_power modules are enabled,
+ * during the compilation the check is made that
+ * @ref CLOCK_CONFIG_IRQ_PRIORITY equals @ref POWER_CONFIG_IRQ_PRIORITY.
+ *
+ * @sa nrf_drv_common_power_irq_disable
+ * @sa nrf_drv_common_clock_irq_disable
+ */
+__STATIC_INLINE void nrf_drv_common_power_clock_irq_init(void);
+#endif
+
+/**
+ * @brief Check if given object is in RAM
+ *
+ * Function for analyzing if given location is placed in RAM.
+ * This function is used to determine if we have address that can be supported by EasyDMA.
+ * @param[in] ptr Pointer to the object
+ * @retval true  Object is located in RAM
+ * @retval false Object is not located in RAM
+ */
+__STATIC_INLINE bool nrf_drv_is_in_RAM(void const * const ptr);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE bool nrf_drv_common_irq_enable_check(IRQn_Type IRQn)
+{
+    return 0 != (NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] &
+        (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+}
+
+__STATIC_INLINE void nrf_drv_common_irq_disable(IRQn_Type IRQn)
+{
+    NVIC_DisableIRQ(IRQn);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_bitpos_to_event(uint32_t bit)
+{
+    return NRF_DRV_COMMON_EVREGS_OFFSET + bit * sizeof(uint32_t);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_event_to_bitpos(uint32_t event)
+{
+    return (event - NRF_DRV_COMMON_EVREGS_OFFSET) / sizeof(uint32_t);
+}
+
+__STATIC_INLINE IRQn_Type nrf_drv_get_IRQn(void const * const pinst)
+{
+    uint8_t ret = (uint8_t)((uint32_t)pinst>>12U);
+    return (IRQn_Type) ret;
+}
+
+#if NRF_MODULE_ENABLED(CLOCK) || NRF_MODULE_ENABLED(POWER)
+__STATIC_INLINE void nrf_drv_common_power_clock_irq_init(void)
+{
+    if(!nrf_drv_common_irq_enable_check(POWER_CLOCK_IRQn))
+    {
+        nrf_drv_common_irq_enable(
+            POWER_CLOCK_IRQn,
+#if NRF_DRV_COMMON_POWER_CLOCK_ISR
+    #if CLOCK_CONFIG_IRQ_PRIORITY != POWER_CONFIG_IRQ_PRIORITY
+    #error CLOCK_CONFIG_IRQ_PRIORITY and POWER_CONFIG_IRQ_PRIORITY have to be the same.
+    #endif
+            CLOCK_CONFIG_IRQ_PRIORITY
+#elif NRF_MODULE_ENABLED(CLOCK)
+            CLOCK_CONFIG_IRQ_PRIORITY
+#elif NRF_MODULE_ENABLED(POWER)
+            POWER_CONFIG_IRQ_PRIORITY
+#endif
+            );
+    }
+}
+#endif
+
+__STATIC_INLINE bool nrf_drv_is_in_RAM(void const * const ptr)
+{
+    return ((((uintptr_t)ptr) & 0xE0000000u) == 0x20000000u);
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_DRV_COMMON_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/comp/nrf_drv_comp.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,236 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(COMP)
+#include "nrf_drv_comp.h"
+
+#include "nrf_assert.h"
+#include "nrf_error.h"
+#include "nrf_soc.h"
+#include "nrf_drv_common.h"
+#include "app_util_platform.h"
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+ 
+#define NRF_LOG_MODULE_NAME "COMP"
+
+#if COMP_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       COMP_CONFIG_LOG_LEVEL
+#define NRF_LOG_INFO_COLOR  COMP_CONFIG_INFO_COLOR
+#define NRF_LOG_DEBUG_COLOR COMP_CONFIG_DEBUG_COLOR
+#define EVT_TO_STR(event)   (event == NRF_COMP_EVENT_READY ? "NRF_COMP_EVENT_READY" :                   \
+                            (event == NRF_COMP_EVENT_DOWN ? "NRF_COMP_EVENT_DOWN" :                     \
+                            (event == NRF_COMP_EVENT_UP ? "NRF_COMP_EVENT_UP" :                         \
+                            (event == NRF_COMP_EVENT_CROSS ? "NRF_COMP_EVENT_CROSS" : "UNKNOWN ERROR"))))
+#else //COMP_CONFIG_LOG_ENABLED
+#define EVT_TO_STR(event)   ""
+#define NRF_LOG_LEVEL       0
+#endif //COMP_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+
+
+
+static comp_events_handler_t     m_comp_events_handler = NULL;
+static nrf_drv_state_t           m_state = NRF_DRV_STATE_UNINITIALIZED;
+
+static const nrf_drv_comp_config_t m_default_config = NRF_DRV_COMP_DEFAULT_CONFIG(NRF_COMP_INPUT_0);
+
+static void comp_execute_handler(nrf_comp_event_t event, uint32_t event_mask)
+{
+    if ( nrf_comp_event_check(event) && nrf_comp_int_enable_check(event_mask) )
+    {
+        nrf_comp_event_clear(event);
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(event));
+
+        m_comp_events_handler(event);
+    }
+}
+
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+    #define IRQ_HANDLER_NAME   irq_handler_for_comp
+    #define IRQ_HANDLER        static void IRQ_HANDLER_NAME(void)
+
+    IRQ_HANDLER;
+#else
+    #define IRQ_HANDLER void COMP_LPCOMP_IRQHandler(void)
+#endif // NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+
+IRQ_HANDLER
+{
+    comp_execute_handler(NRF_COMP_EVENT_READY, COMP_INTENSET_READY_Msk);
+    comp_execute_handler(NRF_COMP_EVENT_DOWN, COMP_INTENSET_DOWN_Msk);
+    comp_execute_handler(NRF_COMP_EVENT_UP, COMP_INTENSET_UP_Msk);
+    comp_execute_handler(NRF_COMP_EVENT_CROSS, COMP_INTENSET_CROSS_Msk);
+}
+
+
+ret_code_t nrf_drv_comp_init(const nrf_drv_comp_config_t * p_config,
+                             comp_events_handler_t   event_handler)
+{
+    ret_code_t err_code;
+
+    if (m_state != NRF_DRV_STATE_UNINITIALIZED)
+    { // COMP driver is already initialized
+        err_code = NRF_ERROR_INVALID_STATE;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    if (p_config == NULL)
+    {
+        p_config = &m_default_config;
+    }
+
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+    if (nrf_drv_common_per_res_acquire(NRF_COMP, IRQ_HANDLER_NAME) != NRF_SUCCESS)
+    {
+        err_code = NRF_ERROR_BUSY;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+#endif
+
+    nrf_comp_task_trigger(NRF_COMP_TASK_STOP);
+    nrf_comp_enable();
+
+    // Clear events to be sure there are no leftovers.
+    nrf_comp_event_clear(NRF_COMP_EVENT_READY);
+    nrf_comp_event_clear(NRF_COMP_EVENT_DOWN);
+    nrf_comp_event_clear(NRF_COMP_EVENT_UP);
+    nrf_comp_event_clear(NRF_COMP_EVENT_CROSS);
+
+    nrf_comp_ref_set(p_config->reference);
+
+    //If external source is chosen, write to appropriate register.
+    if (p_config->reference == COMP_REFSEL_REFSEL_ARef)
+    {
+        nrf_comp_ext_ref_set(p_config->ext_ref);
+    }
+
+    nrf_comp_th_set(p_config->threshold);
+    nrf_comp_main_mode_set(p_config->main_mode);
+    nrf_comp_speed_mode_set(p_config->speed_mode);
+    nrf_comp_hysteresis_set(p_config->hyst);
+    nrf_comp_isource_set(p_config->isource);
+    nrf_comp_shorts_disable(NRF_DRV_COMP_SHORT_STOP_AFTER_CROSS_EVT | NRF_DRV_COMP_SHORT_STOP_AFTER_UP_EVT |
+                            NRF_DRV_COMP_SHORT_STOP_AFTER_DOWN_EVT);
+    nrf_comp_int_disable(COMP_INTENCLR_CROSS_Msk | COMP_INTENCLR_UP_Msk |
+                         COMP_INTENCLR_DOWN_Msk | COMP_INTENCLR_READY_Msk);
+
+    if (event_handler)
+    {
+        m_comp_events_handler = event_handler;
+    }
+    else
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    nrf_comp_input_select(p_config->input);
+
+    nrf_drv_common_irq_enable(COMP_LPCOMP_IRQn, p_config->interrupt_priority);
+
+    m_state = NRF_DRV_STATE_INITIALIZED;
+
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+void nrf_drv_comp_uninit(void)
+{
+    ASSERT(m_state != NRF_DRV_STATE_UNINITIALIZED);
+    nrf_drv_common_irq_disable(COMP_LPCOMP_IRQn);
+    nrf_comp_disable();
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+    nrf_drv_common_per_res_release(NRF_COMP);
+#endif
+    m_state = NRF_DRV_STATE_UNINITIALIZED;
+    m_comp_events_handler = NULL;
+    NRF_LOG_INFO("Uninitialized.\r\n");
+}
+
+void nrf_drv_comp_pin_select(nrf_comp_input_t psel)
+{
+    bool comp_enable_state = nrf_comp_enable_check();
+    nrf_comp_task_trigger(NRF_COMP_TASK_STOP);
+    if (m_state == NRF_DRV_STATE_POWERED_ON)
+    {
+        m_state = NRF_DRV_STATE_INITIALIZED;
+    }
+    nrf_comp_disable();
+    nrf_comp_input_select(psel);
+    if (comp_enable_state == true)
+    {
+        nrf_comp_enable();
+    }
+}
+
+void nrf_drv_comp_start(uint32_t comp_int_mask, uint32_t comp_shorts_mask)
+{
+    ASSERT(m_state == NRF_DRV_STATE_INITIALIZED);
+    nrf_comp_int_enable(comp_int_mask);
+    nrf_comp_shorts_enable(comp_shorts_mask);
+    nrf_comp_task_trigger(NRF_COMP_TASK_START);
+    m_state = NRF_DRV_STATE_POWERED_ON;
+    NRF_LOG_INFO("Enabled.\r\n");
+}
+
+void nrf_drv_comp_stop(void)
+{
+    ASSERT(m_state == NRF_DRV_STATE_POWERED_ON);
+    nrf_comp_shorts_disable(UINT32_MAX);
+    nrf_comp_int_disable(UINT32_MAX);
+    nrf_comp_task_trigger(NRF_COMP_TASK_STOP);
+    m_state = NRF_DRV_STATE_INITIALIZED;
+    NRF_LOG_INFO("Disabled.\r\n");
+}
+
+uint32_t nrf_drv_comp_sample()
+{
+    ASSERT(m_state == NRF_DRV_STATE_POWERED_ON);
+    nrf_comp_task_trigger(NRF_COMP_TASK_SAMPLE);
+    return nrf_comp_result_get();
+}
+#endif //NRF_MODULE_ENABLED(COMP)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/comp/nrf_drv_comp.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,242 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_DRV_COMP_H__
+#define NRF_DRV_COMP_H__
+
+#include "sdk_config.h"
+#include "nrf_comp.h"
+#include "sdk_errors.h"
+#include "nrf_drv_common.h"
+#include "app_util_platform.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @addtogroup nrf_comp COMP HAL and driver
+ * @ingroup nrf_drivers
+ * @brief @tagAPI52 Comparator (COMP) APIs.
+ * @details The COMP HAL provides basic APIs for accessing the registers of Comparator.
+ * The COMP driver provides APIs on a higher level.
+ *
+ * @defgroup nrf_drv_comp COMP driver
+ * @{
+ * @ingroup nrf_comp
+ * @brief @tagAPI52 Comparator (COMP) driver.
+ */
+
+/**
+ * @brief Macro to convert the threshold voltage to an integer value (needed by the COMP_TH register).
+ *
+ * @param[in] vol             Voltage to be changed to COMP_TH register value. This value must not be smaller than
+ *                            reference voltage divided by 64.
+ * @param[in] ref             Reference voltage.
+ */
+#define VOLTAGE_THRESHOLD_TO_INT(vol, ref) (uint8_t)(((vol) > ((ref) / 64)) ? (ROUNDED_DIV((vol) * 64,(ref)) - 1) : 0)
+
+/**@brief COMP event handler function type.
+ * @param[in] event  COMP event.
+ */
+typedef void (* comp_events_handler_t)(nrf_comp_event_t event);
+
+/**
+ * @enum nrf_drv_comp_short_mask_t
+ * @brief COMP shortcut masks.
+ */
+typedef enum
+{
+    NRF_DRV_COMP_SHORT_STOP_AFTER_CROSS_EVT = COMP_SHORTS_CROSS_STOP_Msk,        /*!< Shortcut between the CROSS event and the STOP task. */
+    NRF_DRV_COMP_SHORT_STOP_AFTER_UP_EVT = COMP_SHORTS_UP_STOP_Msk,              /*!< Shortcut between the UP event and the STOP task. */
+    NRF_DRV_COMP_SHORT_STOP_AFTER_DOWN_EVT = COMP_SHORTS_DOWN_STOP_Msk           /*!< Shortcut between the DOWN event and the STOP task. */
+}nrf_drv_comp_short_mask_t;
+
+/**
+ * @enum nrf_drv_comp_evt_en_mask_t
+ * @brief COMP events masks.
+ */
+typedef enum
+{
+    NRF_DRV_COMP_EVT_EN_CROSS_MASK = COMP_INTENSET_CROSS_Msk,                /*!< CROSS event (generated after VIN+ == VIN-). */
+    NRF_DRV_COMP_EVT_EN_UP_MASK = COMP_INTENSET_UP_Msk,                      /*!< UP event (generated when VIN+ crosses VIN- while increasing). */
+    NRF_DRV_COMP_EVT_EN_DOWN_MASK = COMP_INTENSET_DOWN_Msk,                  /*!< DOWN event (generated when VIN+ crosses VIN- while decreasing). */
+    NRF_DRV_COMP_EVT_EN_READY_MASK = COMP_INTENSET_READY_Msk                 /*!< READY event (generated when the module is ready). */
+}nrf_drv_comp_evt_en_mask_t;
+
+/**@brief COMP configuration.
+ */
+typedef struct
+{
+    nrf_comp_ref_t           reference;          /**< Reference selection. */
+    nrf_comp_ext_ref_t       ext_ref;            /**< External analog reference selection. */
+    nrf_comp_main_mode_t     main_mode;          /**< Main operation mode. */
+    nrf_comp_th_t            threshold;          /**< Structure holding THDOWN and THUP values needed by the COMP_TH register. */
+    nrf_comp_sp_mode_t       speed_mode;         /**< Speed and power mode. */
+    nrf_comp_hyst_t          hyst;               /**< Comparator hysteresis.*/
+    nrf_isource_t            isource;            /**< Current source selected on analog input. */
+    nrf_comp_input_t         input;              /**< Input to be monitored. */
+    uint8_t                  interrupt_priority; /**< Interrupt priority. */
+} nrf_drv_comp_config_t;
+
+/** @brief COMP threshold default configuration. */
+#define COMP_CONFIG_TH                                  \
+{                                                       \
+    .th_down = VOLTAGE_THRESHOLD_TO_INT(0.5, 1.8),      \
+    .th_up = VOLTAGE_THRESHOLD_TO_INT(1.5, 1.8)         \
+}
+
+/** @brief COMP driver default configuration including the COMP HAL configuration. */
+#define NRF_DRV_COMP_DEFAULT_CONFIG(INPUT)                                     \
+{                                                                                   \
+    .reference          = (nrf_comp_ref_t)COMP_CONFIG_REF,                          \
+    .main_mode          = (nrf_comp_main_mode_t)COMP_CONFIG_MAIN_MODE,              \
+    .threshold          = COMP_CONFIG_TH,                                           \
+    .speed_mode         = (nrf_comp_sp_mode_t)COMP_CONFIG_SPEED_MODE,               \
+    .hyst               = (nrf_comp_hyst_t)COMP_CONFIG_HYST,                        \
+    .isource            = (nrf_isource_t)COMP_CONFIG_ISOURCE,                       \
+    .input              = (nrf_comp_input_t)INPUT,                                  \
+    .interrupt_priority = COMP_CONFIG_IRQ_PRIORITY                                  \
+}
+
+/**
+ * @brief Function for initializing the COMP driver.
+ *
+ * This function initializes the COMP driver, but does not enable the peripheral or any interrupts.
+ * To start the driver, call the function @ref nrf_drv_comp_start() after initialization.
+ *
+ * If no configuration structure is provided, the driver is initialized with the default settings.
+ *
+ * @param[in] p_config              Initial configuration. If NULL, the default configuration is used.
+ * @param[in] event_handler         Handler function.
+ *
+ * @retval NRF_ERROR_INVALID_PARAM     If the configuration is invalid.
+ * @retval NRF_ERROR_INVALID_STATE     If the driver has already been initialized.
+ * @retval NRF_ERROR_BUSY              If the LPCOMP driver is initialized.
+ */
+ret_code_t nrf_drv_comp_init(const nrf_drv_comp_config_t * p_config,
+                             comp_events_handler_t   event_handler);
+
+
+/**
+ *  @brief Function for uninitializing the COMP driver.
+ *
+ *  This function uninitializes the COMP driver. The COMP peripheral and
+ *  its interrupts are disabled, and local variables are cleaned. After this call, you must
+ *  initialize the driver again by calling nrf_drv_comp_init() if you want to use it.
+ *
+ *  @sa nrf_drv_comp_stop()
+ */
+void     nrf_drv_comp_uninit(void);
+
+/**
+ * @brief Function for setting the analog input.
+ *
+ * @param[in] psel              COMP analog pin selection.
+ */
+void nrf_drv_comp_pin_select(nrf_comp_input_t psel);
+
+/**
+ * @brief Function for starting the COMP peripheral and interrupts.
+ *
+ * Before calling this function, the driver must be initialized. This function
+ * enables the COMP peripheral and its interrupts.
+ *
+ * @param[in] comp_evt_en_mask            Mask of events to be enabled. This parameter should be built as
+ *                                        'or' of elements from @ref nrf_drv_comp_evt_en_mask_t.
+ * @param[in] comp_shorts_mask            Mask of shorts to be enabled. This parameter should be built as
+ *                                        'or' of elements from @ref nrf_drv_comp_short_mask_t.
+ *
+ * @sa nrf_drv_comp_init()
+ *
+ */
+void nrf_drv_comp_start(uint32_t comp_evt_en_mask, uint32_t comp_shorts_mask);
+
+/**@brief Function for stopping the COMP peripheral.
+ *
+ * Before calling this function, the driver must be enabled. This function disables the COMP
+ * peripheral and its interrupts.
+ *
+ * @sa nrf_drv_comp_uninit()
+ *
+ */
+void nrf_drv_comp_stop(void);
+
+/**
+ * @brief Function for copying the current state of the comparator result to the RESULT register.
+ *
+ * @retval 0 If the input voltage is below the threshold (VIN+ < VIN-).
+ * @retval 1 If the input voltage is above the threshold (VIN+ > VIN-).
+ */
+uint32_t nrf_drv_comp_sample(void);
+
+/**
+ * @brief Function for getting the task address.
+ *
+ * Before calling this function, the driver must be enabled.
+ *
+ * @param[in] comp_task                    COMP task.
+ *
+ * @return Address of the given COMP task.
+ */
+__STATIC_INLINE uint32_t nrf_drv_comp_task_address_get(nrf_comp_task_t comp_task)
+{
+    return (uint32_t)nrf_comp_task_address_get(comp_task);
+}
+
+/**
+ * @brief Function for getting the event address.
+ *
+ * @param[in] comp_event                COMP event.
+ *
+ * @return Address of the given COMP event.
+ */
+__STATIC_INLINE uint32_t nrf_drv_comp_event_address_get(nrf_comp_event_t comp_event)
+{
+    return (uint32_t)nrf_comp_event_address_get(comp_event);
+}
+
+/**
+ *@}
+ **/
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* NRF_DRV_COMP_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/delay/nrf_delay.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,224 @@
+#ifndef _NRF_DELAY_H
+#define _NRF_DELAY_H
+
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CLOCK_FREQ_16MHz (16000000UL)
+
+/**
+ * @brief Function for delaying execution for number of microseconds.
+ *
+ * @note NRF52 has instruction cache and because of that delay is not precise.
+ *
+ * @param number_of_us
+ *
+ */
+/*lint --e{438, 522, 40, 10, 563} "Variable not used" "Function lacks side-effects" */
+__STATIC_INLINE void nrf_delay_us(uint32_t number_of_us);
+
+
+/**
+ * @brief Function for delaying execution for number of miliseconds.
+ *
+ * @note NRF52 has instruction cache and because of that delay is not precise.
+ *
+ * @note Function internally calls @ref nrf_delay_us so the maximum delay is the
+ * same as in case of @ref nrf_delay_us, approx. 71 minutes.
+ *
+ * @param number_of_ms
+ *
+ */
+
+/*lint --e{438, 522, 40, 10, 563} "Variable not used" "Function lacks side-effects" */
+__STATIC_INLINE void nrf_delay_ms(uint32_t number_of_ms);
+
+#if defined ( __CC_ARM   )
+__STATIC_INLINE void nrf_delay_us(uint32_t number_of_us)
+{
+    if(!number_of_us)
+        return;
+__asm
+    {
+loop:
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    CMP SystemCoreClock, CLOCK_FREQ_16MHz
+    BEQ cond
+    NOP
+#if defined(NRF52) || defined(NRF52840_XXAA) || defined(NRF52832)
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+    NOP
+#endif
+cond:
+    SUBS number_of_us,number_of_us, #1
+    BNE    loop
+    }
+}
+
+#elif defined ( _WIN32 ) || defined ( __unix ) || defined( __APPLE__ )
+
+
+#ifndef CUSTOM_NRF_DELAY_US
+__STATIC_INLINE void nrf_delay_us(uint32_t number_of_us)
+{}
+#endif
+
+#elif defined ( __GNUC__ ) || ( __ICCARM__ )
+
+__STATIC_INLINE void nrf_delay_us(uint32_t number_of_us)
+{
+    const uint32_t clock16MHz = CLOCK_FREQ_16MHz;
+    if (number_of_us)
+    {
+__ASM volatile (
+#if ( defined(__GNUC__) && (__CORTEX_M == (0x00U) ) )
+        ".syntax unified\n"
+#endif
+"1:\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " CMP %[SystemCoreClock],%[clock16MHz]\n"
+       " BEQ.n 2f\n"
+       " NOP\n"
+#if defined(NRF52) || defined(NRF52840_XXAA) || defined(NRF52832)
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+       " NOP\n"
+#endif
+"2:\n"
+       " SUBS %0, %0, #1\n"
+       " BNE.n 1b\n"
+#if __CORTEX_M == (0x00U)
+#ifdef __GNUC__
+    ".syntax divided\n"
+#endif
+    :"+l" (number_of_us) :
+#else
+    :"+r" (number_of_us) :
+#endif
+                [SystemCoreClock] "r" (SystemCoreClock),
+                [clock16MHz] "r" (clock16MHz)
+        );
+#ifdef __ICCARM__
+        __DMB();
+#endif
+    }
+}
+#endif
+
+__STATIC_INLINE void nrf_delay_ms(uint32_t number_of_ms)
+{
+    nrf_delay_us(1000*number_of_ms);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/gpiote/nrf_drv_gpiote.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,807 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(GPIOTE)
+#include "nrf_drv_gpiote.h"
+#include "nrf_drv_common.h"
+#include "app_util_platform.h"
+#include "nrf_assert.h"
+#include "nrf_bitmask.h"
+#include <string.h>
+
+#define NRF_LOG_MODULE_NAME "GPIOTE"
+
+#if GPIOTE_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       GPIOTE_CONFIG_LOG_LEVEL
+#define NRF_LOG_INFO_COLOR  GPIOTE_CONFIG_INFO_COLOR
+#define NRF_LOG_DEBUG_COLOR GPIOTE_CONFIG_DEBUG_COLOR
+#else // GPIOTE_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       0
+#endif  // GPIOTE_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+
+/* Validate configuration */
+INTERRUPT_PRIORITY_VALIDATION(GPIOTE_CONFIG_IRQ_PRIORITY);
+
+#define FORBIDDEN_HANDLER_ADDRESS ((nrf_drv_gpiote_evt_handler_t)UINT32_MAX)
+#define PIN_NOT_USED              (-1)
+#define PIN_USED                  (-2)
+#define NO_CHANNELS               (-1)
+#define SENSE_FIELD_POS           (6)
+#define SENSE_FIELD_MASK          (0xC0)
+
+/**
+ * @brief Macro for converting task-event index to an address of an event register.
+ *
+ * Macro utilizes the fact that registers are grouped together in ascending order.
+ */
+#define TE_IDX_TO_EVENT_ADDR(idx)    (nrf_gpiote_events_t)((uint32_t)NRF_GPIOTE_EVENTS_IN_0 + \
+                                                           (sizeof(uint32_t) * (idx)))
+
+/**
+ * @brief Macro for converting task-event index of OUT task to an address of a task register.
+ *
+ * Macro utilizes the fact that registers are grouped together in ascending order.
+ */
+#define TE_OUT_IDX_TO_TASK_ADDR(idx) (nrf_gpiote_tasks_t)((uint32_t)NRF_GPIOTE_TASKS_OUT_0 + \
+                                                          (sizeof(uint32_t) * (idx)))
+
+#if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__SDK_DOXYGEN__)
+/**
+ * @brief Macro for converting task-event index of SET task to an address of a task register.
+ *
+ * Macro utilizes the fact that registers are grouped together in ascending order.
+ */
+#define TE_SET_IDX_TO_TASK_ADDR(idx) (nrf_gpiote_tasks_t)((uint32_t)NRF_GPIOTE_TASKS_SET_0 + \
+                                                          (sizeof(uint32_t) * (idx)))
+
+#endif // defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__SDK_DOXYGEN__)
+
+#if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__SDK_DOXYGEN__)
+/**
+ * @brief Macro for converting task-event index of CLR task to an address of a task register.
+ *
+ * Macro utilizes the fact that registers are grouped together in ascending order.
+ */
+#define TE_CLR_IDX_TO_TASK_ADDR(idx) (nrf_gpiote_tasks_t)((uint32_t)NRF_GPIOTE_TASKS_CLR_0 + \
+                                                          (sizeof(uint32_t) * (idx)))
+
+#endif // defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__SDK_DOXYGEN__)
+
+/*lint -save -e661*/
+typedef struct
+{
+    nrf_drv_gpiote_evt_handler_t handlers[GPIOTE_CH_NUM + GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS];
+    int8_t                       pin_assignments[NUMBER_OF_PINS];
+    int8_t                       port_handlers_pins[GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS];
+    nrf_drv_state_t              state;
+} gpiote_control_block_t;
+
+static gpiote_control_block_t m_cb;
+
+__STATIC_INLINE bool pin_in_use(uint32_t pin)
+{
+    return (m_cb.pin_assignments[pin] != PIN_NOT_USED);
+}
+
+
+__STATIC_INLINE bool pin_in_use_as_non_task_out(uint32_t pin)
+{
+    return (m_cb.pin_assignments[pin] == PIN_USED);
+}
+
+
+__STATIC_INLINE bool pin_in_use_by_te(uint32_t pin)
+{
+    return (m_cb.pin_assignments[pin] >= 0 && m_cb.pin_assignments[pin] <
+            GPIOTE_CH_NUM) ? true : false;
+}
+
+
+__STATIC_INLINE bool pin_in_use_by_port(uint32_t pin)
+{
+    return (m_cb.pin_assignments[pin] >= GPIOTE_CH_NUM);
+}
+
+
+__STATIC_INLINE bool pin_in_use_by_gpiote(uint32_t pin)
+{
+    return (m_cb.pin_assignments[pin] >= 0);
+}
+
+
+__STATIC_INLINE void pin_in_use_by_te_set(uint32_t                     pin,
+                                          uint32_t                     channel_id,
+                                          nrf_drv_gpiote_evt_handler_t handler,
+                                          bool                         is_channel)
+{
+    m_cb.pin_assignments[pin] = channel_id;
+    m_cb.handlers[channel_id] = handler;
+    if (!is_channel)
+    {
+        m_cb.port_handlers_pins[channel_id - GPIOTE_CH_NUM] = (int8_t)pin;
+    }
+}
+
+
+__STATIC_INLINE void pin_in_use_set(uint32_t pin)
+{
+    m_cb.pin_assignments[pin] = PIN_USED;
+}
+
+
+__STATIC_INLINE void pin_in_use_clear(uint32_t pin)
+{
+    m_cb.pin_assignments[pin] = PIN_NOT_USED;
+}
+
+
+__STATIC_INLINE int8_t channel_port_get(uint32_t pin)
+{
+    return m_cb.pin_assignments[pin];
+}
+
+
+__STATIC_INLINE nrf_drv_gpiote_evt_handler_t channel_handler_get(uint32_t channel)
+{
+    return m_cb.handlers[channel];
+}
+
+
+static int8_t channel_port_alloc(uint32_t pin, nrf_drv_gpiote_evt_handler_t handler, bool channel)
+{
+    int8_t   channel_id = NO_CHANNELS;
+    uint32_t i;
+
+    uint32_t start_idx = channel ? 0 : GPIOTE_CH_NUM;
+    uint32_t end_idx   =
+        channel ? GPIOTE_CH_NUM : (GPIOTE_CH_NUM + GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS);
+
+    // critical section
+
+    for (i = start_idx; i < end_idx; i++)
+    {
+        if (m_cb.handlers[i] == FORBIDDEN_HANDLER_ADDRESS)
+        {
+            pin_in_use_by_te_set(pin, i, handler, channel);
+            channel_id = i;
+            break;
+        }
+    }
+    // critical section
+    return channel_id;
+}
+
+
+static void channel_free(uint8_t channel_id)
+{
+    m_cb.handlers[channel_id] = FORBIDDEN_HANDLER_ADDRESS;
+    if (channel_id >= GPIOTE_CH_NUM)
+    {
+        m_cb.port_handlers_pins[channel_id - GPIOTE_CH_NUM] = (int8_t)PIN_NOT_USED;
+    }
+}
+
+
+ret_code_t nrf_drv_gpiote_init(void)
+{
+    ret_code_t err_code;
+
+    if (m_cb.state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n",
+                        (uint32_t)__func__,
+                        (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    uint8_t i;
+
+    for (i = 0; i < NUMBER_OF_PINS; i++)
+    {
+        pin_in_use_clear(i);
+    }
+
+    for (i = 0; i < (GPIOTE_CH_NUM + GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS); i++)
+    {
+        channel_free(i);
+    }
+
+    nrf_drv_common_irq_enable(GPIOTE_IRQn, GPIOTE_CONFIG_IRQ_PRIORITY);
+    nrf_gpiote_event_clear(NRF_GPIOTE_EVENTS_PORT);
+    nrf_gpiote_int_enable(GPIOTE_INTENSET_PORT_Msk);
+    m_cb.state = NRF_DRV_STATE_INITIALIZED;
+
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__,
+                 (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+bool nrf_drv_gpiote_is_init(void)
+{
+    return (m_cb.state != NRF_DRV_STATE_UNINITIALIZED) ? true : false;
+}
+
+
+void nrf_drv_gpiote_uninit(void)
+{
+    ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
+
+    uint32_t i;
+
+    for (i = 0; i < NUMBER_OF_PINS; i++)
+    {
+        if (pin_in_use_as_non_task_out(i))
+        {
+            nrf_drv_gpiote_out_uninit(i);
+        }
+        else if ( pin_in_use_by_gpiote(i))
+        {
+            /* Disable gpiote_in is having the same effect on out pin as gpiote_out_uninit on
+             * so it can be called on all pins used by GPIOTE.
+             */
+            nrf_drv_gpiote_in_uninit(i);
+        }
+    }
+    m_cb.state = NRF_DRV_STATE_UNINITIALIZED;
+    NRF_LOG_INFO("Uninitialized.\r\n");
+}
+
+
+ret_code_t nrf_drv_gpiote_out_init(nrf_drv_gpiote_pin_t                pin,
+                                   nrf_drv_gpiote_out_config_t const * p_config)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(m_cb.state == NRF_DRV_STATE_INITIALIZED);
+    ASSERT(p_config);
+
+    ret_code_t err_code = NRF_SUCCESS;
+
+    if (pin_in_use(pin))
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+    }
+    else
+    {
+        if (p_config->task_pin)
+        {
+            int8_t channel = channel_port_alloc(pin, NULL, true);
+
+            if (channel != NO_CHANNELS)
+            {
+                nrf_gpiote_task_configure(channel, pin, p_config->action, p_config->init_state);
+            }
+            else
+            {
+                err_code = NRF_ERROR_NO_MEM;
+            }
+        }
+        else
+        {
+            pin_in_use_set(pin);
+        }
+
+        if (err_code == NRF_SUCCESS)
+        {
+            if (p_config->init_state == NRF_GPIOTE_INITIAL_VALUE_HIGH)
+            {
+                nrf_gpio_pin_set(pin);
+            }
+            else
+            {
+                nrf_gpio_pin_clear(pin);
+            }
+
+            nrf_gpio_cfg_output(pin);
+        }
+    }
+
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__,
+                 (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+void nrf_drv_gpiote_out_uninit(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use(pin));
+
+    if (pin_in_use_by_te(pin))
+    {
+        channel_free((uint8_t)channel_port_get(pin));
+        nrf_gpiote_te_default(channel_port_get(pin));
+    }
+    pin_in_use_clear(pin);
+
+    nrf_gpio_cfg_default(pin);
+}
+
+
+void nrf_drv_gpiote_out_set(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use(pin));
+    ASSERT(!pin_in_use_by_te(pin))
+
+    nrf_gpio_pin_set(pin);
+}
+
+
+void nrf_drv_gpiote_out_clear(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use(pin));
+    ASSERT(!pin_in_use_by_te(pin))
+
+    nrf_gpio_pin_clear(pin);
+}
+
+
+void nrf_drv_gpiote_out_toggle(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use(pin));
+    ASSERT(!pin_in_use_by_te(pin))
+
+    nrf_gpio_pin_toggle(pin);
+}
+
+
+void nrf_drv_gpiote_out_task_enable(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use(pin));
+    ASSERT(pin_in_use_by_te(pin))
+
+    nrf_gpiote_task_enable(m_cb.pin_assignments[pin]);
+}
+
+
+void nrf_drv_gpiote_out_task_disable(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use(pin));
+    ASSERT(pin_in_use_by_te(pin))
+
+    nrf_gpiote_task_disable(m_cb.pin_assignments[pin]);
+}
+
+
+uint32_t nrf_drv_gpiote_out_task_addr_get(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use_by_te(pin));
+
+    nrf_gpiote_tasks_t task = TE_OUT_IDX_TO_TASK_ADDR(channel_port_get(pin));
+    return nrf_gpiote_task_addr_get(task);
+}
+
+
+#if defined(GPIOTE_FEATURE_SET_PRESENT)
+uint32_t nrf_drv_gpiote_set_task_addr_get(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use_by_te(pin));
+
+    nrf_gpiote_tasks_t task = TE_SET_IDX_TO_TASK_ADDR(channel_port_get(pin));
+    return nrf_gpiote_task_addr_get(task);
+}
+
+
+#endif // defined(GPIOTE_FEATURE_SET_PRESENT)
+
+#if defined(GPIOTE_FEATURE_CLR_PRESENT)
+uint32_t nrf_drv_gpiote_clr_task_addr_get(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use_by_te(pin));
+
+    nrf_gpiote_tasks_t task = TE_CLR_IDX_TO_TASK_ADDR(channel_port_get(pin));
+    return nrf_gpiote_task_addr_get(task);
+}
+
+
+#endif // defined(GPIOTE_FEATURE_CLR_PRESENT)
+
+void nrf_drv_gpiote_out_task_force(nrf_drv_gpiote_pin_t pin, uint8_t state)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use(pin));
+    ASSERT(pin_in_use_by_te(pin));
+
+    nrf_gpiote_outinit_t init_val =
+        state ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW;
+    nrf_gpiote_task_force(m_cb.pin_assignments[pin], init_val);
+}
+
+
+void nrf_drv_gpiote_out_task_trigger(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use(pin));
+    ASSERT(pin_in_use_by_te(pin));
+
+    nrf_gpiote_tasks_t task = TE_OUT_IDX_TO_TASK_ADDR(channel_port_get(pin));
+    nrf_gpiote_task_set(task);
+}
+
+
+#if defined(GPIOTE_FEATURE_SET_PRESENT)
+void nrf_drv_gpiote_set_task_trigger(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use(pin));
+    ASSERT(pin_in_use_by_te(pin));
+
+    nrf_gpiote_tasks_t task = TE_SET_IDX_TO_TASK_ADDR(channel_port_get(pin));
+    nrf_gpiote_task_set(task);
+}
+
+
+#endif // defined(GPIOTE_FEATURE_SET_PRESENT)
+
+#if  defined(GPIOTE_FEATURE_CLR_PRESENT)
+void nrf_drv_gpiote_clr_task_trigger(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use(pin));
+    ASSERT(pin_in_use_by_te(pin));
+
+    nrf_gpiote_tasks_t task = TE_CLR_IDX_TO_TASK_ADDR(channel_port_get(pin));
+    nrf_gpiote_task_set(task);
+}
+
+
+#endif // defined(GPIOTE_FEATURE_CLR_PRESENT)
+
+ret_code_t nrf_drv_gpiote_in_init(nrf_drv_gpiote_pin_t               pin,
+                                  nrf_drv_gpiote_in_config_t const * p_config,
+                                  nrf_drv_gpiote_evt_handler_t       evt_handler)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ret_code_t err_code = NRF_SUCCESS;
+
+    /* Only one GPIOTE channel can be assigned to one physical pin. */
+    if (pin_in_use_by_gpiote(pin))
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+    }
+    else
+    {
+        int8_t channel = channel_port_alloc(pin, evt_handler, p_config->hi_accuracy);
+        if (channel != NO_CHANNELS)
+        {
+            if (p_config->is_watcher)
+            {
+                nrf_gpio_cfg_watcher(pin);
+            }
+            else
+            {
+                nrf_gpio_cfg_input(pin, p_config->pull);
+            }
+
+            if (p_config->hi_accuracy)
+            {
+                nrf_gpiote_event_configure(channel, pin, p_config->sense);
+            }
+            else
+            {
+                m_cb.port_handlers_pins[channel -
+                                        GPIOTE_CH_NUM] |= (p_config->sense) << SENSE_FIELD_POS;
+            }
+        }
+        else
+        {
+            err_code = NRF_ERROR_NO_MEM;
+        }
+    }
+
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__,
+                 (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+void nrf_drv_gpiote_in_event_enable(nrf_drv_gpiote_pin_t pin, bool int_enable)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use_by_gpiote(pin));
+    if (pin_in_use_by_port(pin))
+    {
+        uint8_t pin_and_sense =
+            m_cb.port_handlers_pins[channel_port_get(pin) - GPIOTE_CH_NUM];
+        nrf_gpiote_polarity_t polarity =
+            (nrf_gpiote_polarity_t)(pin_and_sense >> SENSE_FIELD_POS);
+        nrf_gpio_pin_sense_t sense;
+        if (polarity == NRF_GPIOTE_POLARITY_TOGGLE)
+        {
+            /* read current pin state and set for next sense to oposit */
+            sense = (nrf_gpio_pin_read(pin)) ?
+                    NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
+        }
+        else
+        {
+            sense = (polarity == NRF_GPIOTE_POLARITY_LOTOHI) ?
+                    NRF_GPIO_PIN_SENSE_HIGH : NRF_GPIO_PIN_SENSE_LOW;
+        }
+        nrf_gpio_cfg_sense_set(pin, sense);
+    }
+    else if (pin_in_use_by_te(pin))
+    {
+        int32_t             channel = (int32_t)channel_port_get(pin);
+        nrf_gpiote_events_t event   = TE_IDX_TO_EVENT_ADDR(channel);
+
+        nrf_gpiote_event_enable(channel);
+
+        nrf_gpiote_event_clear(event);
+        if (int_enable)
+        {
+            nrf_drv_gpiote_evt_handler_t handler = channel_handler_get(channel_port_get(pin));
+            // Enable the interrupt only if event handler was provided.
+            if (handler)
+            {
+                nrf_gpiote_int_enable(1 << channel);
+            }
+        }
+    }
+}
+
+
+void nrf_drv_gpiote_in_event_disable(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use_by_gpiote(pin));
+    if (pin_in_use_by_port(pin))
+    {
+        nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE);
+    }
+    else if (pin_in_use_by_te(pin))
+    {
+        int32_t channel = (int32_t)channel_port_get(pin);
+        nrf_gpiote_event_disable(channel);
+        nrf_gpiote_int_disable(1 << channel);
+    }
+}
+
+
+void nrf_drv_gpiote_in_uninit(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use_by_gpiote(pin));
+    nrf_drv_gpiote_in_event_disable(pin);
+    if (pin_in_use_by_te(pin))
+    {
+        nrf_gpiote_te_default(channel_port_get(pin));
+    }
+    nrf_gpio_cfg_default(pin);
+    channel_free((uint8_t)channel_port_get(pin));
+    pin_in_use_clear(pin);
+}
+
+
+bool nrf_drv_gpiote_in_is_set(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    return nrf_gpio_pin_read(pin) ? true : false;
+}
+
+
+uint32_t nrf_drv_gpiote_in_event_addr_get(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use_by_port(pin) || pin_in_use_by_te(pin));
+
+    nrf_gpiote_events_t event = NRF_GPIOTE_EVENTS_PORT;
+
+    if (pin_in_use_by_te(pin))
+    {
+        event = TE_IDX_TO_EVENT_ADDR(channel_port_get(pin));
+    }
+    return nrf_gpiote_event_addr_get(event);
+}
+
+
+void GPIOTE_IRQHandler(void)
+{
+    uint32_t status            = 0;
+    uint32_t input[GPIO_COUNT] = {0};
+
+    /* collect status of all GPIOTE pin events. Processing is done once all are collected and cleared.*/
+    uint32_t            i;
+    nrf_gpiote_events_t event = NRF_GPIOTE_EVENTS_IN_0;
+    uint32_t            mask  = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;
+
+    for (i = 0; i < GPIOTE_CH_NUM; i++)
+    {
+        if (nrf_gpiote_event_is_set(event) && nrf_gpiote_int_is_enabled(mask))
+        {
+            nrf_gpiote_event_clear(event);
+            status |= mask;
+        }
+        mask <<= 1;
+        /* Incrementing to next event, utilizing the fact that events are grouped together
+         * in ascending order. */
+        event = (nrf_gpiote_events_t)((uint32_t)event + sizeof(uint32_t));
+    }
+
+    /* collect PORT status event, if event is set read pins state. Processing is postponed to the
+     * end of interrupt. */
+    if (nrf_gpiote_event_is_set(NRF_GPIOTE_EVENTS_PORT))
+    {
+        nrf_gpiote_event_clear(NRF_GPIOTE_EVENTS_PORT);
+        status |= (uint32_t)NRF_GPIOTE_INT_PORT_MASK;
+        nrf_gpio_ports_read(0, GPIO_COUNT, input);
+    }
+
+    /* Process pin events. */
+    if (status & NRF_GPIOTE_INT_IN_MASK)
+    {
+        mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;
+
+        for (i = 0; i < GPIOTE_CH_NUM; i++)
+        {
+            if (mask & status)
+            {
+                nrf_drv_gpiote_pin_t pin = nrf_gpiote_event_pin_get(i);
+                NRF_LOG_DEBUG("Event in number: %d.\r\n", i);
+                nrf_gpiote_polarity_t        polarity = nrf_gpiote_event_polarity_get(i);
+                nrf_drv_gpiote_evt_handler_t handler  = channel_handler_get(i);
+                NRF_LOG_DEBUG("Pin: %d, polarity: %d.\r\n", pin, polarity);
+                if (handler)
+                {
+                    handler(pin, polarity);
+                }
+            }
+            mask <<= 1;
+        }
+    }
+
+    if (status & (uint32_t)NRF_GPIOTE_INT_PORT_MASK)
+    {
+        /* Process port event. */
+        uint32_t port_idx;
+        uint8_t  repeat                  = 0;
+        uint32_t toggle_mask[GPIO_COUNT] = {0};
+        uint32_t pins_to_check[GPIO_COUNT];
+
+        // Faster way of doing memset because in interrupt context.
+        for (port_idx = 0; port_idx < GPIO_COUNT; port_idx++)
+        {
+            pins_to_check[port_idx] = 0xFFFFFFFF;
+        }
+
+        do
+        {
+            repeat = 0;
+
+            for (i = 0; i < GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS; i++)
+            {
+                uint8_t              pin_and_sense = m_cb.port_handlers_pins[i];
+                nrf_drv_gpiote_pin_t pin           = (pin_and_sense & ~SENSE_FIELD_MASK);
+
+                if ((m_cb.port_handlers_pins[i] != PIN_NOT_USED)
+                    && nrf_bitmask_bit_is_set(pin, pins_to_check))
+                {
+                    nrf_gpiote_polarity_t polarity =
+                        (nrf_gpiote_polarity_t)((pin_and_sense &
+                                                 SENSE_FIELD_MASK) >> SENSE_FIELD_POS);
+                    nrf_drv_gpiote_evt_handler_t handler =
+                        channel_handler_get(channel_port_get(pin));
+                    if (handler || (polarity == NRF_GPIOTE_POLARITY_TOGGLE))
+                    {
+                        if (polarity == NRF_GPIOTE_POLARITY_TOGGLE)
+                        {
+                            nrf_bitmask_bit_set(pin, toggle_mask);
+                        }
+                        nrf_gpio_pin_sense_t sense     = nrf_gpio_pin_sense_get(pin);
+                        uint32_t             pin_state = nrf_bitmask_bit_is_set(pin, input);
+                        if ((pin_state && (sense == NRF_GPIO_PIN_SENSE_HIGH)) ||
+                            (!pin_state && (sense == NRF_GPIO_PIN_SENSE_LOW))  )
+                        {
+                            NRF_LOG_DEBUG("PORT event for pin: %d, polarity: %d.\r\n", pin,
+                                          polarity);
+                            if (polarity == NRF_GPIOTE_POLARITY_TOGGLE)
+                            {
+                                nrf_gpio_pin_sense_t next_sense =
+                                    (sense == NRF_GPIO_PIN_SENSE_HIGH) ?
+                                    NRF_GPIO_PIN_SENSE_LOW :
+                                    NRF_GPIO_PIN_SENSE_HIGH;
+                                nrf_gpio_cfg_sense_set(pin, next_sense);
+                                ++repeat;
+
+                            }
+                            if (handler)
+                            {
+                                handler(pin, polarity);
+                            }
+                        }
+                    }
+                }
+            }
+
+            if (repeat)
+            {
+                // When one of the pins in low-accuracy and toggle mode becomes active,
+                // it's sense mode is inverted to clear the internal SENSE signal.
+                // State of any other enabled low-accuracy input in toggle mode must be checked
+                // explicitly, because it does not trigger the interrput when SENSE signal is active.
+                // For more information about SENSE functionality, refer to Product Specification.
+
+                uint32_t new_input[GPIO_COUNT];
+                bool     input_unchanged = true;
+                nrf_gpio_ports_read(0, GPIO_COUNT, new_input);
+
+                // Faster way of doing memcmp because in interrupt context.
+                for (port_idx = 0; port_idx < GPIO_COUNT; port_idx++)
+                {
+                    if (new_input[port_idx] != input[port_idx])
+                    {
+                        input_unchanged = false;
+                        break;
+                    }
+                }
+
+                if (input_unchanged)
+                {
+                    // No change.
+                    repeat = 0;
+                }
+                else
+                {
+                    // Faster way of doing memcpy because in interrupt context.
+                    for (port_idx = 0; port_idx < GPIO_COUNT; port_idx++)
+                    {
+                        input[port_idx]         = new_input[port_idx];
+                        pins_to_check[port_idx] = toggle_mask[port_idx];
+                    }
+                }
+            }
+        }
+        while (repeat);
+    }
+}
+
+
+/*lint -restore*/
+#endif // NRF_MODULE_ENABLED(GPIOTE)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/gpiote/nrf_drv_gpiote.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,384 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_DRV_GPIOTE__
+#define NRF_DRV_GPIOTE__
+
+/**
+ * @addtogroup nrf_gpiote GPIOTE abstraction and driver
+ * @ingroup nrf_drivers
+ * @brief GPIOTE APIs.
+ * @defgroup nrf_drv_gpiote GPIOTE driver
+ * @{
+ * @ingroup nrf_gpiote
+ * @brief GPIOTE driver for managing input and output pins.
+ */
+
+#include "nrf_gpiote.h"
+#include "nrf_gpio.h"
+#include "sdk_errors.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include "sdk_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Input pin configuration. */
+typedef struct
+{
+    nrf_gpiote_polarity_t sense;      /**< Transition that triggers interrupt. */
+    nrf_gpio_pin_pull_t   pull;       /**< Pulling mode. */
+    bool                  is_watcher; /**< True when the input pin is tracking an output pin. */
+    bool                  hi_accuracy;/**< True when high accuracy (IN_EVENT) is used. */
+} nrf_drv_gpiote_in_config_t;
+
+/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect low-to-high transition.
+ * @details Set hi_accu to true to use IN_EVENT. */
+#define GPIOTE_CONFIG_IN_SENSE_LOTOHI(hi_accu)     \
+    {                                            \
+        .is_watcher = false,                     \
+        .hi_accuracy = hi_accu,                  \
+        .pull = NRF_GPIO_PIN_NOPULL,             \
+        .sense = NRF_GPIOTE_POLARITY_LOTOHI,     \
+    }
+
+/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect high-to-low transition.
+ * @details Set hi_accu to true to use IN_EVENT. */
+#define GPIOTE_CONFIG_IN_SENSE_HITOLO(hi_accu)      \
+    {                                            \
+        .is_watcher = false,                     \
+        .hi_accuracy = hi_accu,                  \
+        .pull = NRF_GPIO_PIN_NOPULL,             \
+        .sense = NRF_GPIOTE_POLARITY_HITOLO,     \
+    }
+
+/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect any change on the pin.
+ * @details Set hi_accu to true to use IN_EVENT.*/
+#define GPIOTE_CONFIG_IN_SENSE_TOGGLE(hi_accu)   \
+    {                                            \
+        .is_watcher = false,                     \
+        .hi_accuracy = hi_accu,                  \
+        .pull = NRF_GPIO_PIN_NOPULL,             \
+        .sense = NRF_GPIOTE_POLARITY_TOGGLE,     \
+    }
+
+/**@brief Output pin configuration. */
+typedef struct
+{
+    nrf_gpiote_polarity_t action;    /**< Configuration of the pin task. */
+    nrf_gpiote_outinit_t  init_state; /**< Initial state of the output pin. */
+    bool                  task_pin;  /**< True if the pin is controlled by a GPIOTE task. */
+} nrf_drv_gpiote_out_config_t;
+
+/**@brief Macro for configuring a pin to use as output. GPIOTE is not used for the pin. */
+#define GPIOTE_CONFIG_OUT_SIMPLE(init_high)                                                        \
+    {                                                                                              \
+        .init_state = init_high ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW,    \
+        .task_pin = false,                                                                         \
+    }
+
+/**@brief Macro for configuring a pin to use the GPIO OUT TASK to change the state from high to low.
+ * @details The task will clear the pin. Therefore, the pin is set initially.  */
+#define GPIOTE_CONFIG_OUT_TASK_LOW                                                                 \
+    {                                                                                              \
+        .init_state = NRF_GPIOTE_INITIAL_VALUE_HIGH,                                               \
+        .task_pin   = true,                                                                        \
+        .action     = NRF_GPIOTE_POLARITY_HITOLO,                                                  \
+    }
+
+/**@brief Macro for configuring a pin to use the GPIO OUT TASK to change the state from low to high.
+ * @details The task will set the pin. Therefore, the pin is cleared initially.  */
+#define GPIOTE_CONFIG_OUT_TASK_HIGH                                                                \
+    {                                                                                              \
+        .init_state = NRF_GPIOTE_INITIAL_VALUE_LOW,                                                \
+        .task_pin   = true,                                                                        \
+        .action     = NRF_GPIOTE_POLARITY_LOTOHI,                                                  \
+    }
+
+/**@brief Macro for configuring a pin to use the GPIO OUT TASK to toggle the pin state.
+ * @details The initial pin state must be provided.  */
+#define GPIOTE_CONFIG_OUT_TASK_TOGGLE(init_high)                                                   \
+    {                                                                                              \
+        .init_state = init_high ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW,    \
+        .task_pin   = true,                                                                        \
+        .action     = NRF_GPIOTE_POLARITY_TOGGLE,                                                  \
+    }
+
+/** @brief Pin. */
+typedef uint32_t nrf_drv_gpiote_pin_t;
+
+/**
+ * @brief Pin event handler prototype.
+ * @param pin    Pin that triggered this event.
+ * @param action Action that lead to triggering this event.
+ */
+typedef void (*nrf_drv_gpiote_evt_handler_t)(nrf_drv_gpiote_pin_t pin, nrf_gpiote_polarity_t action);
+
+/**
+ * @brief Function for initializing the GPIOTE module.
+ *
+ * @details Only static configuration is supported to prevent the shared
+ * resource being customized by the initiator.
+ *
+ * @retval    NRF_SUCCESS If initialization was successful.
+ * @retval    NRF_ERROR_INVALID_STATE If the driver was already initialized.
+ */
+ret_code_t nrf_drv_gpiote_init(void);
+
+/**
+ * @brief Function for checking if the GPIOTE module is initialized.
+ *
+ * @details The GPIOTE module is a shared module. Therefore, you should check if
+ * the module is already initialized and skip initialization if it is.
+ *
+ * @retval    true  If the module is already initialized.
+ * @retval    false If the module is not initialized.
+ */
+bool nrf_drv_gpiote_is_init(void);
+
+/**
+ * @brief Function for uninitializing the GPIOTE module.
+ */
+void nrf_drv_gpiote_uninit(void);
+
+/**
+ * @brief Function for initializing a GPIOTE output pin.
+ * @details The output pin can be controlled by the CPU or by PPI. The initial
+ * configuration specifies which mode is used. If PPI mode is used, the driver
+ * attempts to allocate one of the available GPIOTE channels. If no channel is
+ * available, an error is returned.
+ *
+ * @param[in] pin       Pin.
+ * @param[in] p_config  Initial configuration.
+ *
+ * @retval NRF_SUCCESS             If initialization was successful.
+ * @retval NRF_ERROR_INVALID_STATE If the driver is not initialized or the pin is already used.
+ * @retval NRF_ERROR_NO_MEM        If no GPIOTE channel is available.
+ */
+ret_code_t nrf_drv_gpiote_out_init(nrf_drv_gpiote_pin_t pin,
+                                   nrf_drv_gpiote_out_config_t const * p_config);
+
+/**
+ * @brief Function for uninitializing a GPIOTE output pin.
+ * @details The driver frees the GPIOTE channel if the output pin was using one.
+ *
+ * @param[in] pin       Pin.
+ */
+void nrf_drv_gpiote_out_uninit(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for setting a GPIOTE output pin.
+ *
+ * @param[in] pin       Pin.
+ */
+void nrf_drv_gpiote_out_set(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for clearing a GPIOTE output pin.
+ *
+ * @param[in] pin       Pin.
+ */
+void nrf_drv_gpiote_out_clear(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for toggling a GPIOTE output pin.
+ *
+ * @param[in] pin       Pin.
+ */
+void nrf_drv_gpiote_out_toggle(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for enabling a GPIOTE output pin task.
+ *
+ * @param[in] pin       Pin.
+ */
+void nrf_drv_gpiote_out_task_enable(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for disabling a GPIOTE output pin task.
+ *
+ * @param[in] pin       Pin.
+ */
+void nrf_drv_gpiote_out_task_disable(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for getting the address of a configurable GPIOTE task.
+ *
+ * @param[in] pin       Pin.
+ *
+ * @return Address of OUT task.
+ */
+uint32_t nrf_drv_gpiote_out_task_addr_get(nrf_drv_gpiote_pin_t pin);
+
+#if defined(GPIOTE_FEATURE_SET_PRESENT)
+/**
+ * @brief Function for getting the address of a configurable GPIOTE task.
+ *
+ * @param[in] pin       Pin.
+ *
+ * @return Address of SET task.
+ */
+uint32_t nrf_drv_gpiote_set_task_addr_get(nrf_drv_gpiote_pin_t pin);
+#endif // defined(GPIOTE_FEATURE_SET_PRESENT)
+
+#if defined(GPIOTE_FEATURE_CLR_PRESENT)
+/**
+ * @brief Function for getting the address of a configurable GPIOTE task.
+ *
+ * @param[in] pin       Pin.
+ *
+ * @return Address of CLR task.
+ */
+uint32_t nrf_drv_gpiote_clr_task_addr_get(nrf_drv_gpiote_pin_t pin);
+#endif // defined(GPIOTE_FEATURE_CLR_PRESENT)
+
+/**
+ * @brief Function for initializing a GPIOTE input pin.
+ * @details The input pin can act in two ways:
+ * - lower accuracy but low power (high frequency clock not needed)
+ * - higher accuracy (high frequency clock required)
+ *
+ * The initial configuration specifies which mode is used.
+ * If high-accuracy mode is used, the driver attempts to allocate one
+ * of the available GPIOTE channels. If no channel is
+ * available, an error is returned.
+ * In low accuracy mode SENSE feature is used. In this case only one active pin
+ * can be detected at a time. It can be worked around by setting all of the used
+ * low accuracy pins to toggle mode.
+ * For more information about SENSE functionality, refer to Product Specification.
+ *
+ * @param[in] pin       Pin.
+ * @param[in] p_config    Initial configuration.
+ * @param[in] evt_handler User function to be called when the configured transition occurs.
+ *
+ * @retval NRF_SUCCESS             If initialization was successful.
+ * @retval NRF_ERROR_INVALID_STATE If the driver is not initialized or the pin is already used.
+ * @retval NRF_ERROR_NO_MEM        If no GPIOTE channel is available.
+ */
+ret_code_t nrf_drv_gpiote_in_init(nrf_drv_gpiote_pin_t pin,
+                                  nrf_drv_gpiote_in_config_t const * p_config,
+                                  nrf_drv_gpiote_evt_handler_t evt_handler);
+
+/**
+ * @brief Function for uninitializing a GPIOTE input pin.
+ * @details The driver frees the GPIOTE channel if the input pin was using one.
+ *
+ * @param[in] pin       Pin.
+ */
+void nrf_drv_gpiote_in_uninit(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for enabling sensing of a GPIOTE input pin.
+ *
+ * @details If the input pin is configured as high-accuracy pin, the function
+ * enables an IN_EVENT. Otherwise, the function enables the GPIO sense mechanism.
+ * Note that a PORT event is shared between multiple pins, therefore the
+ * interrupt is always enabled.
+ *
+ * @param[in] pin       Pin.
+ * @param[in] int_enable  True to enable the interrupt. Always valid for a high-accuracy pin.
+ */
+void nrf_drv_gpiote_in_event_enable(nrf_drv_gpiote_pin_t pin, bool int_enable);
+
+/**
+ * @brief Function for disabling a GPIOTE input pin.
+ *
+ * @param[in] pin       Pin.
+ */
+void nrf_drv_gpiote_in_event_disable(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for checking if a GPIOTE input pin is set.
+ *
+ * @param[in] pin       Pin.
+ * @retval    true If the input pin is set.
+ * @retval    false If the input pin is not set.
+ */
+bool nrf_drv_gpiote_in_is_set(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for getting the address of a GPIOTE input pin event.
+ * @details If the pin is configured to use low-accuracy mode, the address of the PORT event is returned.
+ *
+ * @param[in] pin       Pin.
+ */
+uint32_t nrf_drv_gpiote_in_event_addr_get(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for forcing a specific state on the pin configured as task.
+ *
+ * @param[in] pin       Pin.
+ * @param[in] state     Pin state.
+ */
+void nrf_drv_gpiote_out_task_force(nrf_drv_gpiote_pin_t pin, uint8_t state);
+
+/**
+ * @brief Function for triggering the task OUT manually.
+ *
+ * @param[in] pin       Pin.
+ */
+void nrf_drv_gpiote_out_task_trigger(nrf_drv_gpiote_pin_t pin);
+
+#ifdef NRF52_SERIES
+/**
+ * @brief Function for triggering the task SET manually.
+ *
+ * @param[in] pin       Pin.
+ */
+void nrf_drv_gpiote_set_task_trigger(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for triggering the task CLR manually.
+ *
+ * @param[in] pin       Pin.
+ */
+void nrf_drv_gpiote_clr_task_trigger(nrf_drv_gpiote_pin_t pin);
+#endif
+
+/**
+ *@}
+ **/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //NRF_DRV_GPIOTE__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_clock.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,400 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_CLOCK_H__
+#define NRF_CLOCK_H__
+
+#include <stddef.h>
+#include <stdbool.h>
+
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrf_clock_hal Clock HAL
+ * @{
+ * @ingroup nrf_clock
+ * @brief Hardware access layer for managing the low-frequency clock (LFCLK) and the high-frequency clock (HFCLK).
+ */
+
+#define NRF_CLOCK_TASK_TRIGGER (1UL)
+#define NRF_CLOCK_EVENT_CLEAR  (0UL)
+
+/**
+ * @brief Low-frequency clock sources.
+ * @details Used by LFCLKSRC, LFCLKSTAT, and LFCLKSRCCOPY registers.
+ */
+typedef enum
+{
+    NRF_CLOCK_LFCLK_RC    = CLOCK_LFCLKSRC_SRC_RC,   /**< Internal 32 kHz RC oscillator. */
+    NRF_CLOCK_LFCLK_Xtal  = CLOCK_LFCLKSRC_SRC_Xtal, /**< External 32 kHz crystal. */
+    NRF_CLOCK_LFCLK_Synth = CLOCK_LFCLKSRC_SRC_Synth /**< Internal 32 kHz synthesizer from HFCLK system clock. */
+} nrf_clock_lfclk_t;
+
+/**
+ * @brief High-frequency clock sources.
+ */
+typedef enum
+{
+    NRF_CLOCK_HFCLK_LOW_ACCURACY  = CLOCK_HFCLKSTAT_SRC_RC,  /**< Internal 16 MHz RC oscillator. */
+    NRF_CLOCK_HFCLK_HIGH_ACCURACY = CLOCK_HFCLKSTAT_SRC_Xtal /**< External 16 MHz/32 MHz crystal oscillator. */
+} nrf_clock_hfclk_t;
+
+/**
+ * @brief Trigger status of task LFCLKSTART/HFCLKSTART.
+ * @details Used by LFCLKRUN and HFCLKRUN registers.
+ */
+typedef enum
+{
+    NRF_CLOCK_START_TASK_NOT_TRIGGERED = CLOCK_LFCLKRUN_STATUS_NotTriggered, /**< Task LFCLKSTART/HFCLKSTART has not been triggered. */
+    NRF_CLOCK_START_TASK_TRIGGERED     = CLOCK_LFCLKRUN_STATUS_Triggered     /**< Task LFCLKSTART/HFCLKSTART has been triggered. */
+} nrf_clock_start_task_status_t;
+
+/**
+ * @brief Interrupts.
+ */
+typedef enum
+{
+    NRF_CLOCK_INT_HF_STARTED_MASK = CLOCK_INTENSET_HFCLKSTARTED_Msk, /**< Interrupt on HFCLKSTARTED event. */
+    NRF_CLOCK_INT_LF_STARTED_MASK = CLOCK_INTENSET_LFCLKSTARTED_Msk, /**< Interrupt on LFCLKSTARTED event. */
+    NRF_CLOCK_INT_DONE_MASK       = CLOCK_INTENSET_DONE_Msk,         /**< Interrupt on DONE event. */
+    NRF_CLOCK_INT_CTTO_MASK       = CLOCK_INTENSET_CTTO_Msk          /**< Interrupt on CTTO event. */
+} nrf_clock_int_mask_t;
+
+/**
+ * @brief Tasks.
+ *
+ * @details The NRF_CLOCK_TASK_LFCLKSTOP task cannot be set when the low-frequency clock is not running.
+ * The NRF_CLOCK_TASK_HFCLKSTOP task cannot be set when the high-frequency clock is not running.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_CLOCK_TASK_HFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTART), /**< Start HFCLK clock source.*/
+    NRF_CLOCK_TASK_HFCLKSTOP  = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTOP),  /**< Stop HFCLK clock source.*/
+    NRF_CLOCK_TASK_LFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTART), /**< Start LFCLK clock source.*/
+    NRF_CLOCK_TASK_LFCLKSTOP  = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTOP),  /**< Stop LFCLK clock source.*/
+    NRF_CLOCK_TASK_CAL        = offsetof(NRF_CLOCK_Type, TASKS_CAL),        /**< Start calibration of LFCLK RC oscillator.*/
+    NRF_CLOCK_TASK_CTSTART    = offsetof(NRF_CLOCK_Type, TASKS_CTSTART),    /**< Start calibration timer.*/
+    NRF_CLOCK_TASK_CTSTOP     = offsetof(NRF_CLOCK_Type, TASKS_CTSTOP)      /**< Stop calibration timer.*/
+} nrf_clock_task_t;                                                         /*lint -restore */
+
+/**
+ * @brief Events.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_CLOCK_EVENT_HFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLKSTARTED), /**< HFCLK oscillator started.*/
+    NRF_CLOCK_EVENT_LFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_LFCLKSTARTED), /**< LFCLK oscillator started.*/
+    NRF_CLOCK_EVENT_DONE         = offsetof(NRF_CLOCK_Type, EVENTS_DONE),         /**< Calibration of LFCLK RC oscillator completed.*/
+    NRF_CLOCK_EVENT_CTTO         = offsetof(NRF_CLOCK_Type, EVENTS_CTTO)          /**< Calibration timer time-out.*/
+} nrf_clock_event_t;                                                               /*lint -restore */
+
+/**
+ * @brief Function for enabling a specific interrupt.
+ *
+ * @param[in]  int_mask         Interrupt.
+ */
+__STATIC_INLINE void nrf_clock_int_enable(uint32_t int_mask);
+
+/**
+ * @brief Function for disabling a specific interrupt.
+ *
+ * @param[in]  int_mask         Interrupt.
+ */
+__STATIC_INLINE void nrf_clock_int_disable(uint32_t int_mask);
+
+/**
+ * @brief Function for retrieving the state of a specific interrupt.
+ *
+ * @param[in]  int_mask         Interrupt.
+ *
+ * @retval     true                   If the interrupt is enabled.
+ * @retval     false                  If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_clock_int_enable_check(nrf_clock_int_mask_t int_mask);
+
+/**
+ * @brief Function for retrieving the address of a specific task.
+ * @details This function can be used by the PPI module.
+ *
+ * @param[in]  task             Task.
+ *
+ * @return     Address of the requested task register.
+ */
+__STATIC_INLINE uint32_t nrf_clock_task_address_get(nrf_clock_task_t task);
+
+/**
+ * @brief Function for setting a specific task.
+ *
+ * @param[in]  task             Task.
+ */
+__STATIC_INLINE void nrf_clock_task_trigger(nrf_clock_task_t task);
+
+/**
+ * @brief Function for retrieving the address of a specific event.
+ * @details This function can be used by the PPI module.
+ *
+ * @param[in]  event       Event.
+ *
+ * @return     Address of the requested event register.
+ */
+__STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event);
+
+/**
+ * @brief Function for clearing a specific event.
+ *
+ * @param[in]  event       Event.
+ */
+__STATIC_INLINE void nrf_clock_event_clear(nrf_clock_event_t event);
+
+/**
+ * @brief Function for retrieving the state of a specific event.
+ *
+ * @param[in]  event       Event.
+ *
+ * @retval     true              If the event is set.
+ * @retval     false             If the event is not set.
+ */
+__STATIC_INLINE bool nrf_clock_event_check(nrf_clock_event_t event);
+
+/**
+ * @brief Function for changing the low-frequency clock source.
+ * @details This function cannot be called when the low-frequency clock is running.
+ *
+ * @param[in]  source            New low-frequency clock source.
+ *
+ */
+__STATIC_INLINE void nrf_clock_lf_src_set(nrf_clock_lfclk_t source);
+
+/**
+ * @brief Function for retrieving the selected source for the low-frequency clock.
+ *
+ * @retval     NRF_CLOCK_LFCLK_RC     If the internal 32 kHz RC oscillator is the selected source for the low-frequency clock.
+ * @retval     NRF_CLOCK_LFCLK_Xtal   If an external 32 kHz crystal oscillator is the selected source for the low-frequency clock.
+ * @retval     NRF_CLOCK_LFCLK_Synth  If the internal 32 kHz synthesizer from the HFCLK is the selected source for the low-frequency clock.
+ */
+__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void);
+
+/**
+ * @brief Function for retrieving the active source of the low-frequency clock.
+ *
+ * @retval     NRF_CLOCK_LFCLK_RC     If the internal 32 kHz RC oscillator is the active source of the low-frequency clock.
+ * @retval     NRF_CLOCK_LFCLK_Xtal   If an external 32 kHz crystal oscillator is the active source of the low-frequency clock.
+ * @retval     NRF_CLOCK_LFCLK_Synth  If the internal 32 kHz synthesizer from the HFCLK is the active source of the low-frequency clock.
+ */
+__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void);
+
+/**
+ * @brief Function for retrieving the clock source for the LFCLK clock when the task LKCLKSTART is triggered.
+ *
+ * @retval     NRF_CLOCK_LFCLK_RC     If the internal 32 kHz RC oscillator is running and generating the LFCLK clock.
+ * @retval     NRF_CLOCK_LFCLK_Xtal   If an external 32 kHz crystal oscillator is running and generating the LFCLK clock.
+ * @retval     NRF_CLOCK_LFCLK_Synth  If the internal 32 kHz synthesizer from the HFCLK is running and generating the LFCLK clock.
+ */
+__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(void);
+
+/**
+ * @brief Function for retrieving the state of the LFCLK clock.
+ *
+ * @retval     false                     If the LFCLK clock is not running.
+ * @retval     true                      If the LFCLK clock is running.
+ */
+__STATIC_INLINE bool nrf_clock_lf_is_running(void);
+
+/**
+ * @brief Function for retrieving the trigger status of the task LFCLKSTART.
+ *
+ * @retval     NRF_CLOCK_START_TASK_NOT_TRIGGERED     If the task LFCLKSTART has not been triggered.
+ * @retval     NRF_CLOCK_START_TASK_TRIGGERED         If the task LFCLKSTART has been triggered.
+ */
+__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(void);
+
+/**
+ * @brief Function for retrieving the active source of the high-frequency clock.
+ *
+ * @retval     NRF_CLOCK_HFCLK_LOW_ACCURACY   If the internal 16 MHz RC oscillator is the active source of the high-frequency clock.
+ * @retval     NRF_CLOCK_HFCLK_HIGH_ACCURACY  If an external 16 MHz/32 MHz crystal oscillator is the active source of the high-frequency clock.
+ */
+__STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(void);
+
+/**
+ * @brief Function for retrieving the state of the HFCLK clock.
+ *
+ * @param[in]  clk_src                   Clock source to be checked.
+ *
+ * @retval     false                     If the HFCLK clock is not running.
+ * @retval     true                      If the HFCLK clock is running.
+ */
+__STATIC_INLINE bool nrf_clock_hf_is_running(nrf_clock_hfclk_t clk_src);
+
+/**
+ * @brief Function for retrieving the trigger status of the task HFCLKSTART.
+ *
+ * @retval     NRF_CLOCK_START_TASK_NOT_TRIGGERED     If the task HFCLKSTART has not been triggered.
+ * @retval     NRF_CLOCK_START_TASK_TRIGGERED         If the task HFCLKSTART has been triggered.
+ */
+__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(void);
+
+/**
+ * @brief Function for changing the calibration timer interval.
+ *
+ * @param[in]  interval             New calibration timer interval in 0.25 s resolution (range: 0.25 seconds to 31.75 seconds).
+ */
+__STATIC_INLINE void nrf_clock_cal_timer_timeout_set(uint32_t interval);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_clock_int_enable(uint32_t int_mask)
+{
+    NRF_CLOCK->INTENSET = int_mask;
+}
+
+__STATIC_INLINE void nrf_clock_int_disable(uint32_t int_mask)
+{
+    NRF_CLOCK->INTENCLR = int_mask;
+}
+
+__STATIC_INLINE bool nrf_clock_int_enable_check(nrf_clock_int_mask_t int_mask)
+{
+    return (bool)(NRF_CLOCK->INTENCLR & int_mask);
+}
+
+__STATIC_INLINE uint32_t nrf_clock_task_address_get(nrf_clock_task_t task)
+{
+    return ((uint32_t )NRF_CLOCK + task);
+}
+
+__STATIC_INLINE void nrf_clock_task_trigger(nrf_clock_task_t task)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + task)) = NRF_CLOCK_TASK_TRIGGER;
+}
+
+__STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event)
+{
+    return ((uint32_t)NRF_CLOCK + event);
+}
+
+__STATIC_INLINE void nrf_clock_event_clear(nrf_clock_event_t event)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event)) = NRF_CLOCK_EVENT_CLEAR;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event));
+    (void)dummy;
+#endif
+}
+
+__STATIC_INLINE bool nrf_clock_event_check(nrf_clock_event_t event)
+{
+    return (bool)*((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event));
+}
+
+__STATIC_INLINE void nrf_clock_lf_src_set(nrf_clock_lfclk_t source)
+{
+    NRF_CLOCK->LFCLKSRC =
+        (uint32_t)((source << CLOCK_LFCLKSRC_SRC_Pos) & CLOCK_LFCLKSRC_SRC_Msk);
+}
+
+__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void)
+{
+    return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSRC &
+                                CLOCK_LFCLKSRC_SRC_Msk) >> CLOCK_LFCLKSRC_SRC_Pos);
+}
+
+__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void)
+{
+    return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSTAT &
+                                CLOCK_LFCLKSTAT_SRC_Msk) >> CLOCK_LFCLKSTAT_SRC_Pos);
+}
+
+__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(void)
+{
+    return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSRCCOPY &
+                                CLOCK_LFCLKSRCCOPY_SRC_Msk) >> CLOCK_LFCLKSRCCOPY_SRC_Pos);
+}
+
+__STATIC_INLINE bool nrf_clock_lf_is_running(void)
+{
+    return ((NRF_CLOCK->LFCLKSTAT &
+             CLOCK_LFCLKSTAT_STATE_Msk) >> CLOCK_LFCLKSTAT_STATE_Pos);
+}
+
+__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(void)
+{
+    return (nrf_clock_start_task_status_t)((NRF_CLOCK->LFCLKRUN &
+                                            CLOCK_LFCLKRUN_STATUS_Msk) >>
+                                           CLOCK_LFCLKRUN_STATUS_Pos);
+}
+
+__STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(void)
+{
+    return (nrf_clock_hfclk_t)((NRF_CLOCK->HFCLKSTAT &
+                                CLOCK_HFCLKSTAT_SRC_Msk) >> CLOCK_HFCLKSTAT_SRC_Pos);
+}
+
+__STATIC_INLINE bool nrf_clock_hf_is_running(nrf_clock_hfclk_t clk_src)
+{
+    return (NRF_CLOCK->HFCLKSTAT & (CLOCK_HFCLKSTAT_STATE_Msk | CLOCK_HFCLKSTAT_SRC_Msk)) ==
+            (CLOCK_HFCLKSTAT_STATE_Msk | (clk_src << CLOCK_HFCLKSTAT_SRC_Pos));
+}
+
+__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(void)
+{
+    return (nrf_clock_start_task_status_t)((NRF_CLOCK->HFCLKRUN &
+                                            CLOCK_HFCLKRUN_STATUS_Msk) >>
+                                           CLOCK_HFCLKRUN_STATUS_Pos);
+}
+
+__STATIC_INLINE void nrf_clock_cal_timer_timeout_set(uint32_t interval)
+{
+    NRF_CLOCK->CTIV = ((interval << CLOCK_CTIV_CTIV_Pos) & CLOCK_CTIV_CTIV_Msk);
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+/**
+ *@}
+ **/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_CLOCK_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_comp.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,508 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @file
+ * @brief COMP HAL API.
+ */
+
+#ifndef NRF_COMP_H_
+#define NRF_COMP_H_
+
+/**
+ * @defgroup nrf_comp_hal COMP HAL
+ * @{
+ * @ingroup nrf_comp
+ * @brief @tagAPI52 Hardware access layer for managing the Comparator (COMP).
+ */
+
+#include "nrf.h"
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @enum nrf_comp_input_t
+ * @brief COMP analog pin selection.
+ */
+typedef enum
+{
+    NRF_COMP_INPUT_0 = COMP_PSEL_PSEL_AnalogInput0,        /*!< AIN0 selected as analog input. */
+    NRF_COMP_INPUT_1 = COMP_PSEL_PSEL_AnalogInput1,        /*!< AIN1 selected as analog input. */
+    NRF_COMP_INPUT_2 = COMP_PSEL_PSEL_AnalogInput2,        /*!< AIN2 selected as analog input. */
+    NRF_COMP_INPUT_3 = COMP_PSEL_PSEL_AnalogInput3,        /*!< AIN3 selected as analog input. */
+    NRF_COMP_INPUT_4 = COMP_PSEL_PSEL_AnalogInput4,        /*!< AIN4 selected as analog input. */
+    NRF_COMP_INPUT_5 = COMP_PSEL_PSEL_AnalogInput5,        /*!< AIN5 selected as analog input. */
+    NRF_COMP_INPUT_6 = COMP_PSEL_PSEL_AnalogInput6,        /*!< AIN6 selected as analog input. */
+    NRF_COMP_INPUT_7 = COMP_PSEL_PSEL_AnalogInput7         /*!< AIN7 selected as analog input. */
+}nrf_comp_input_t;
+
+/**
+ * @enum nrf_comp_ref_t
+ * @brief COMP reference selection.
+ */
+typedef enum
+{
+    NRF_COMP_REF_Int1V2 = COMP_REFSEL_REFSEL_Int1V2,     /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V). */
+    NRF_COMP_REF_Int1V8 = COMP_REFSEL_REFSEL_Int1V8,     /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V). */
+    NRF_COMP_REF_Int2V4 = COMP_REFSEL_REFSEL_Int2V4,     /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V). */
+    NRF_COMP_REF_VDD = COMP_REFSEL_REFSEL_VDD,           /*!< VREF = VDD. */
+    NRF_COMP_REF_ARef = COMP_REFSEL_REFSEL_ARef          /*!< VREF = AREF (VDD >= VREF >= AREFMIN). */
+}nrf_comp_ref_t;
+
+/**
+ * @enum nrf_comp_ext_ref_t
+ * @brief COMP external analog reference selection.
+ */
+typedef enum
+{
+    NRF_COMP_EXT_REF_0 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference0,        /*!< Use AIN0 as external analog reference. */
+    NRF_COMP_EXT_REF_1 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference1         /*!< Use AIN1 as external analog reference. */
+}nrf_comp_ext_ref_t;
+
+/**
+ * @brief COMP THDOWN and THUP values that are used to calculate the threshold voltages VDOWN and VUP.
+ */
+typedef struct
+{
+    uint8_t th_down; /*!< THDOWN value. */
+    uint8_t th_up;   /*!< THUP value. */
+}nrf_comp_th_t;
+
+/**
+ * @enum nrf_comp_main_mode_t
+ * @brief COMP main operation mode.
+ */
+typedef enum
+{
+    NRF_COMP_MAIN_MODE_SE = COMP_MODE_MAIN_SE,        /*!< Single ended mode. */
+    NRF_COMP_MAIN_MODE_Diff = COMP_MODE_MAIN_Diff     /*!< Differential mode. */
+}nrf_comp_main_mode_t;
+
+/**
+ * @enum nrf_comp_sp_mode_t
+ * @brief COMP speed and power mode.
+ */
+typedef enum
+{
+    NRF_COMP_SP_MODE_Low = COMP_MODE_SP_Low,          /*!< Low power mode. */
+    NRF_COMP_SP_MODE_Normal = COMP_MODE_SP_Normal,    /*!< Normal mode. */
+    NRF_COMP_SP_MODE_High = COMP_MODE_SP_High         /*!< High speed mode. */
+}nrf_comp_sp_mode_t;
+
+/**
+ * @enum nrf_comp_hyst_t
+ * @brief COMP comparator hysteresis.
+ */
+typedef enum
+{
+    NRF_COMP_HYST_NoHyst = COMP_HYST_HYST_NoHyst,    /*!< Comparator hysteresis disabled. */
+    NRF_COMP_HYST_50mV = COMP_HYST_HYST_Hyst50mV     /*!< Comparator hysteresis enabled. */
+}nrf_comp_hyst_t;
+
+/**
+ * @brief COMP current source selection on analog input.
+ */
+typedef enum
+{
+    NRF_COMP_ISOURCE_Off = COMP_ISOURCE_ISOURCE_Off,            /*!< Current source disabled. */
+    NRF_COMP_ISOURCE_Ien2uA5 = COMP_ISOURCE_ISOURCE_Ien2mA5,    /*!< Current source enabled (+/- 2.5 uA). */
+    NRF_COMP_ISOURCE_Ien5uA = COMP_ISOURCE_ISOURCE_Ien5mA,      /*!< Current source enabled (+/- 5 uA). */
+    NRF_COMP_ISOURCE_Ien10uA = COMP_ISOURCE_ISOURCE_Ien10mA     /*!< Current source enabled (+/- 10 uA). */
+}nrf_isource_t;
+
+/**
+ * @enum nrf_comp_task_t
+ * @brief COMP tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_COMP_TASK_START  = offsetof(NRF_COMP_Type, TASKS_START), /*!< COMP start sampling task. */
+    NRF_COMP_TASK_STOP   = offsetof(NRF_COMP_Type, TASKS_STOP),  /*!< COMP stop sampling task. */
+    NRF_COMP_TASK_SAMPLE = offsetof(NRF_COMP_Type, TASKS_SAMPLE) /*!< Sample comparator value. */
+    /*lint -restore*/
+}nrf_comp_task_t;
+
+/**
+ * @enum nrf_comp_event_t
+ * @brief COMP events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_COMP_EVENT_READY = offsetof(NRF_COMP_Type, EVENTS_READY), /*!< COMP is ready and output is valid. */
+    NRF_COMP_EVENT_DOWN  = offsetof(NRF_COMP_Type, EVENTS_DOWN),  /*!< Input voltage crossed the threshold going down. */
+    NRF_COMP_EVENT_UP    = offsetof(NRF_COMP_Type, EVENTS_UP),    /*!< Input voltage crossed the threshold going up. */
+    NRF_COMP_EVENT_CROSS = offsetof(NRF_COMP_Type, EVENTS_CROSS)  /*!< Input voltage crossed the threshold in any direction. */
+    /*lint -restore*/
+}nrf_comp_event_t;
+
+/**
+ * @brief COMP reference configuration.
+ */
+typedef struct
+{
+    nrf_comp_ref_t     reference;        /*!< COMP reference selection. */
+    nrf_comp_ext_ref_t external;         /*!< COMP external analog reference selection. */
+}nrf_comp_ref_conf_t;
+
+
+/**
+ * @brief Function for enabling the COMP peripheral.
+ */
+__STATIC_INLINE void nrf_comp_enable(void);
+
+
+/**
+ * @brief Function for disabling the COMP peripheral.
+ */
+
+__STATIC_INLINE void nrf_comp_disable(void);
+
+/**
+ * @brief Function for checking if the COMP peripheral is enabled.
+ *
+ * @retval true  If the COMP peripheral is enabled.
+ * @retval false If the COMP peripheral is not enabled.
+ */
+__STATIC_INLINE bool nrf_comp_enable_check(void);
+
+/**
+ * @brief Function for setting the reference source.
+ *
+ * @param[in] reference                 COMP reference selection.
+ */
+__STATIC_INLINE void nrf_comp_ref_set(nrf_comp_ref_t reference);
+
+
+/**
+ * @brief Function for setting the external analog reference source.
+ *
+ * @param[in] ext_ref                   COMP external analog reference selection.
+ */
+__STATIC_INLINE void nrf_comp_ext_ref_set(nrf_comp_ext_ref_t ext_ref);
+
+
+/**
+ * @brief Function for setting threshold voltages.
+ *
+ * @param[in] threshold                 COMP VDOWN and VUP thresholds.
+ */
+__STATIC_INLINE void nrf_comp_th_set(nrf_comp_th_t threshold);
+
+
+/**
+ * @brief Function for setting the main mode.
+ *
+ * @param[in] main_mode                 COMP main operation mode.
+ */
+__STATIC_INLINE void nrf_comp_main_mode_set(nrf_comp_main_mode_t main_mode);
+
+
+/**
+ * @brief Function for setting the speed mode.
+ *
+ * @param[in] speed_mode                COMP speed and power mode.
+ */
+__STATIC_INLINE void nrf_comp_speed_mode_set(nrf_comp_sp_mode_t speed_mode);
+
+
+/**
+ * @brief Function for setting the hysteresis.
+ *
+ * @param[in] hyst                      COMP comparator hysteresis.
+ */
+__STATIC_INLINE void nrf_comp_hysteresis_set(nrf_comp_hyst_t hyst);
+
+
+/**
+ * @brief Function for setting the current source on the analog input.
+ *
+ * @param[in] isource                   COMP current source selection on analog input.
+ */
+__STATIC_INLINE void nrf_comp_isource_set(nrf_isource_t isource);
+
+
+/**
+ * @brief Function for selecting the active input of the COMP.
+ *
+ * @param[in] input Input to be selected.
+ */
+__STATIC_INLINE void nrf_comp_input_select(nrf_comp_input_t input);
+
+
+/**
+ * @brief Function for getting the last COMP compare result.
+ *
+ * @return The last compare result. If 0, then VIN+ < VIN-. If 1, then VIN+ > VIN-.
+ *
+ * @note If VIN+ == VIN-, the return value depends on the previous result.
+ */
+__STATIC_INLINE uint32_t nrf_comp_result_get(void);
+
+
+/**
+ * @brief Function for enabling interrupts from COMP.
+ *
+ * @param[in] comp_int_mask Mask of interrupts to be enabled.
+ *
+ * @sa nrf_comp_int_enable_check()
+ */
+__STATIC_INLINE void nrf_comp_int_enable(uint32_t comp_int_mask);
+
+/**
+ * @brief Function for disabling interrupts from COMP.
+ *
+ * @param[in] comp_int_mask Mask of interrupts to be disabled.
+ *
+ * @sa nrf_comp_int_enable_check()
+ */
+__STATIC_INLINE void nrf_comp_int_disable(uint32_t comp_int_mask);
+
+
+/**
+ * @brief Function for getting the enabled interrupts of COMP.
+ *
+ * @param[in] comp_int_mask Mask of interrupts to be checked.
+ *
+ * @retval true If any interrupts of the specified mask are enabled.
+ */
+__STATIC_INLINE bool nrf_comp_int_enable_check(uint32_t comp_int_mask);
+
+
+
+/**
+ * @brief Function for getting the address of a specific COMP task register.
+ *
+ * @param[in] comp_task COMP task.
+ *
+ * @return Address of the specified COMP task.
+ */
+__STATIC_INLINE uint32_t * nrf_comp_task_address_get(nrf_comp_task_t comp_task);
+
+
+/**
+ * @brief Function for getting the address of a specific COMP event register.
+ *
+ * @param[in] comp_event COMP event.
+ *
+ * @return Address of the specified COMP event.
+ */
+__STATIC_INLINE uint32_t * nrf_comp_event_address_get(nrf_comp_event_t comp_event);
+
+
+/**
+ * @brief  Function for setting COMP shorts.
+ *
+ * @param[in] comp_short_mask COMP shorts by mask.
+ *
+ */
+__STATIC_INLINE void nrf_comp_shorts_enable(uint32_t comp_short_mask);
+
+
+/**
+ * @brief Function for clearing COMP shorts by mask.
+ *
+ * @param[in] comp_short_mask COMP shorts to be cleared.
+ *
+ */
+__STATIC_INLINE void nrf_comp_shorts_disable(uint32_t comp_short_mask);
+
+
+/**
+ * @brief Function for setting a specific COMP task.
+ *
+ * @param[in] comp_task COMP task to be set.
+ *
+ */
+__STATIC_INLINE void nrf_comp_task_trigger(nrf_comp_task_t comp_task);
+
+
+/**
+ * @brief Function for clearing a specific COMP event.
+ *
+ * @param[in] comp_event COMP event to be cleared.
+ *
+ */
+__STATIC_INLINE void nrf_comp_event_clear(nrf_comp_event_t comp_event);
+
+
+/**
+ * @brief Function for getting the state of a specific COMP event.
+ *
+ * @retval true If the specified COMP event is active.
+ *
+ */
+__STATIC_INLINE bool nrf_comp_event_check(nrf_comp_event_t comp_event);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_comp_enable(void)
+{
+    NRF_COMP->ENABLE = (COMP_ENABLE_ENABLE_Enabled << COMP_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_comp_disable(void)
+{
+    NRF_COMP->ENABLE = (COMP_ENABLE_ENABLE_Disabled << COMP_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE bool nrf_comp_enable_check(void)
+{
+    return ((NRF_COMP->ENABLE) & COMP_ENABLE_ENABLE_Enabled);
+}
+
+__STATIC_INLINE void nrf_comp_ref_set(nrf_comp_ref_t reference)
+{
+    NRF_COMP->REFSEL = (reference << COMP_REFSEL_REFSEL_Pos);
+}
+
+__STATIC_INLINE void nrf_comp_ext_ref_set(nrf_comp_ext_ref_t ext_ref)
+{
+    NRF_COMP->EXTREFSEL = (ext_ref << COMP_EXTREFSEL_EXTREFSEL_Pos);
+}
+
+__STATIC_INLINE void nrf_comp_th_set(nrf_comp_th_t threshold)
+{
+    NRF_COMP->TH =
+        ((threshold.th_down << COMP_TH_THDOWN_Pos) & COMP_TH_THDOWN_Msk) |
+        ((threshold.th_up << COMP_TH_THUP_Pos) & COMP_TH_THUP_Msk);
+}
+
+__STATIC_INLINE void nrf_comp_main_mode_set(nrf_comp_main_mode_t main_mode)
+{
+    NRF_COMP->MODE |= (main_mode << COMP_MODE_MAIN_Pos);
+}
+
+__STATIC_INLINE void nrf_comp_speed_mode_set(nrf_comp_sp_mode_t speed_mode)
+{
+    NRF_COMP->MODE |= (speed_mode << COMP_MODE_SP_Pos);
+}
+
+__STATIC_INLINE void nrf_comp_hysteresis_set(nrf_comp_hyst_t hyst)
+{
+    NRF_COMP->HYST = (hyst << COMP_HYST_HYST_Pos) & COMP_HYST_HYST_Msk;
+}
+
+__STATIC_INLINE void nrf_comp_isource_set(nrf_isource_t isource)
+{
+    NRF_COMP->ISOURCE = (isource << COMP_ISOURCE_ISOURCE_Pos) & COMP_ISOURCE_ISOURCE_Msk;
+}
+
+__STATIC_INLINE void nrf_comp_input_select(nrf_comp_input_t input)
+{
+    NRF_COMP->PSEL   = ((uint32_t)input << COMP_PSEL_PSEL_Pos);
+}
+
+__STATIC_INLINE uint32_t nrf_comp_result_get(void)
+{
+    return (uint32_t)NRF_COMP->RESULT;
+}
+
+__STATIC_INLINE void nrf_comp_int_enable(uint32_t comp_int_mask)
+{
+    NRF_COMP->INTENSET = comp_int_mask;
+}
+
+__STATIC_INLINE void nrf_comp_int_disable(uint32_t comp_int_mask)
+{
+    NRF_COMP->INTENCLR = comp_int_mask;
+}
+
+__STATIC_INLINE bool nrf_comp_int_enable_check(uint32_t comp_int_mask)
+{
+    return (NRF_COMP->INTENSET & comp_int_mask); // when read this register will return the value of INTEN.
+}
+
+__STATIC_INLINE uint32_t * nrf_comp_task_address_get(nrf_comp_task_t comp_task)
+{
+    return (uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_task);
+}
+
+__STATIC_INLINE uint32_t * nrf_comp_event_address_get(nrf_comp_event_t comp_event)
+{
+    return (uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_event);
+}
+
+__STATIC_INLINE void nrf_comp_shorts_enable(uint32_t comp_short_mask)
+{
+    NRF_COMP->SHORTS |= comp_short_mask;
+}
+
+__STATIC_INLINE void nrf_comp_shorts_disable(uint32_t comp_short_mask)
+{
+    NRF_COMP->SHORTS &= ~comp_short_mask;
+}
+
+__STATIC_INLINE void nrf_comp_task_trigger(nrf_comp_task_t comp_task)
+{
+    *( (volatile uint32_t *)( (uint8_t *)NRF_COMP + comp_task) ) = 1;
+}
+
+__STATIC_INLINE void nrf_comp_event_clear(nrf_comp_event_t comp_event)
+{
+    *( (volatile uint32_t *)( (uint8_t *)NRF_COMP + (uint32_t)comp_event) ) = 0;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)comp_event));
+    (void)dummy;
+#endif
+}
+
+__STATIC_INLINE bool nrf_comp_event_check(nrf_comp_event_t comp_event)
+{
+    return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_COMP + comp_event));
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+/**
+ *@}
+ **/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_COMP_H_

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_ecb.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,99 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @file
+ * @brief Implementation of AES ECB driver
+ */
+
+
+//lint -e438
+
+#include <stdlib.h>
+#include <stdbool.h>
+#include <string.h>
+#include "nrf.h"
+#include "nrf_ecb.h"
+
+static uint8_t  ecb_data[48];   ///< ECB data structure for RNG peripheral to access.
+static uint8_t* ecb_key;        ///< Key:        Starts at ecb_data
+static uint8_t* ecb_cleartext;  ///< Cleartext:  Starts at ecb_data + 16 bytes.
+static uint8_t* ecb_ciphertext; ///< Ciphertext: Starts at ecb_data + 32 bytes.
+
+bool nrf_ecb_init(void)
+{
+  ecb_key = ecb_data;
+  ecb_cleartext  = ecb_data + 16;
+  ecb_ciphertext = ecb_data + 32;
+
+  NRF_ECB->ECBDATAPTR = (uint32_t)ecb_data;
+  return true;
+}
+
+
+bool nrf_ecb_crypt(uint8_t * dest_buf, const uint8_t * src_buf)
+{
+   uint32_t counter = 0x1000000;
+   if (src_buf != ecb_cleartext)
+   {
+     memcpy(ecb_cleartext,src_buf,16);
+   }
+   NRF_ECB->EVENTS_ENDECB = 0;
+   NRF_ECB->TASKS_STARTECB = 1;
+   while (NRF_ECB->EVENTS_ENDECB == 0)
+   {
+    counter--;
+    if (counter == 0)
+    {
+      return false;
+    }
+   }
+   NRF_ECB->EVENTS_ENDECB = 0;
+   if (dest_buf != ecb_ciphertext)
+   {
+     memcpy(dest_buf,ecb_ciphertext,16);
+   }
+   return true;
+}
+
+void nrf_ecb_set_key(const uint8_t * key)
+{
+  memcpy(ecb_key,key,16);
+}
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_ecb.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,100 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @file
+ * @brief ECB driver API.
+ */
+
+#ifndef NRF_ECB_H__
+#define NRF_ECB_H__
+
+/**
+ * @defgroup nrf_ecb AES ECB encryption
+ * @{
+ * @ingroup nrf_drivers
+ * @brief Driver for the AES Electronic Code Book (ECB) peripheral.
+ *
+ * To encrypt data, the peripheral must first be powered on
+ * using @ref nrf_ecb_init. Next, the key must be set using @ref nrf_ecb_set_key.
+ */
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Function for initializing and powering on the ECB peripheral.
+ *
+ * This function allocates memory for the ECBDATAPTR.
+ * @retval true If initialization was successful.
+ * @retval false If powering on failed.
+ */
+bool nrf_ecb_init(void);
+
+/**
+ * @brief Function for encrypting 16-byte data using current key.
+ *
+ * This function avoids unnecessary copying of data if the parameters point to the
+ * correct locations in the ECB data structure.
+ *
+ * @param dst Result of encryption, 16 bytes will be written.
+ * @param src Source with 16-byte data to be encrypted.
+ *
+ * @retval true  If the encryption operation completed.
+ * @retval false If the encryption operation did not complete.
+ */
+bool nrf_ecb_crypt(uint8_t * dst, const uint8_t * src);
+
+/**
+ * @brief Function for setting the key to be used for encryption.
+ *
+ * @param key Pointer to the key. 16 bytes will be read.
+ */
+void nrf_ecb_set_key(const uint8_t * key);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // NRF_ECB_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_egu.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,350 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_EGU_H__
+#define NRF_EGU_H__
+
+/**
+* @defgroup nrf_egu EGU (Event Generator Unit) abstraction
+* @{
+* @ingroup nrf_drivers
+* @brief @tagAPI52 EGU (Event Generator Unit) module functions.
+*
+*/
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include "nrf_assert.h"
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @enum  nrf_egu_task_t
+ * @brief EGU tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30 -esym(628,__INTADDR__)*/
+    NRF_EGU_TASK_TRIGGER0  = offsetof(NRF_EGU_Type, TASKS_TRIGGER[0]),  /**< Trigger 0 for triggering the corresponding TRIGGERED[0] event. */
+    NRF_EGU_TASK_TRIGGER1  = offsetof(NRF_EGU_Type, TASKS_TRIGGER[1]),  /**< Trigger 1 for triggering the corresponding TRIGGERED[1] event. */
+    NRF_EGU_TASK_TRIGGER2  = offsetof(NRF_EGU_Type, TASKS_TRIGGER[2]),  /**< Trigger 2 for triggering the corresponding TRIGGERED[2] event. */
+    NRF_EGU_TASK_TRIGGER3  = offsetof(NRF_EGU_Type, TASKS_TRIGGER[3]),  /**< Trigger 3 for triggering the corresponding TRIGGERED[3] event. */
+    NRF_EGU_TASK_TRIGGER4  = offsetof(NRF_EGU_Type, TASKS_TRIGGER[4]),  /**< Trigger 4 for triggering the corresponding TRIGGERED[4] event. */
+    NRF_EGU_TASK_TRIGGER5  = offsetof(NRF_EGU_Type, TASKS_TRIGGER[5]),  /**< Trigger 5 for triggering the corresponding TRIGGERED[5] event. */
+    NRF_EGU_TASK_TRIGGER6  = offsetof(NRF_EGU_Type, TASKS_TRIGGER[6]),  /**< Trigger 6 for triggering the corresponding TRIGGERED[6] event. */
+    NRF_EGU_TASK_TRIGGER7  = offsetof(NRF_EGU_Type, TASKS_TRIGGER[7]),  /**< Trigger 7 for triggering the corresponding TRIGGERED[7] event. */
+    NRF_EGU_TASK_TRIGGER8  = offsetof(NRF_EGU_Type, TASKS_TRIGGER[8]),  /**< Trigger 8 for triggering the corresponding TRIGGERED[8] event. */
+    NRF_EGU_TASK_TRIGGER9  = offsetof(NRF_EGU_Type, TASKS_TRIGGER[9]),  /**< Trigger 9 for triggering the corresponding TRIGGERED[9] event. */
+    NRF_EGU_TASK_TRIGGER10 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[10]), /**< Trigger 10 for triggering the corresponding TRIGGERED[10] event. */
+    NRF_EGU_TASK_TRIGGER11 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[11]), /**< Trigger 11 for triggering the corresponding TRIGGERED[11] event. */
+    NRF_EGU_TASK_TRIGGER12 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[12]), /**< Trigger 12 for triggering the corresponding TRIGGERED[12] event. */
+    NRF_EGU_TASK_TRIGGER13 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[13]), /**< Trigger 13 for triggering the corresponding TRIGGERED[13] event. */
+    NRF_EGU_TASK_TRIGGER14 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[14]), /**< Trigger 14 for triggering the corresponding TRIGGERED[14] event. */
+    NRF_EGU_TASK_TRIGGER15 = offsetof(NRF_EGU_Type, TASKS_TRIGGER[15])  /**< Trigger 15 for triggering the corresponding TRIGGERED[15] event. */
+    /*lint -restore*/
+} nrf_egu_task_t;
+
+
+/**
+ * @enum  nrf_egu_event_t
+ * @brief EGU events.
+ */
+typedef enum
+{
+    /*lint -save -e30 -esym(628,__INTADDR__)*/
+    NRF_EGU_EVENT_TRIGGERED0  = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[0]),  /**< Event number 0 generated by triggering the corresponding TRIGGER[0] task. */
+    NRF_EGU_EVENT_TRIGGERED1  = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[1]),  /**< Event number 1 generated by triggering the corresponding TRIGGER[1] task. */
+    NRF_EGU_EVENT_TRIGGERED2  = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[2]),  /**< Event number 2 generated by triggering the corresponding TRIGGER[2] task. */
+    NRF_EGU_EVENT_TRIGGERED3  = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[3]),  /**< Event number 3 generated by triggering the corresponding TRIGGER[3] task. */
+    NRF_EGU_EVENT_TRIGGERED4  = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[4]),  /**< Event number 4 generated by triggering the corresponding TRIGGER[4] task. */
+    NRF_EGU_EVENT_TRIGGERED5  = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[5]),  /**< Event number 5 generated by triggering the corresponding TRIGGER[5] task. */
+    NRF_EGU_EVENT_TRIGGERED6  = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[6]),  /**< Event number 6 generated by triggering the corresponding TRIGGER[6] task. */
+    NRF_EGU_EVENT_TRIGGERED7  = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[7]),  /**< Event number 7 generated by triggering the corresponding TRIGGER[7] task. */
+    NRF_EGU_EVENT_TRIGGERED8  = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[8]),  /**< Event number 8 generated by triggering the corresponding TRIGGER[8] task. */
+    NRF_EGU_EVENT_TRIGGERED9  = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[9]),  /**< Event number 9 generated by triggering the corresponding TRIGGER[9] task. */
+    NRF_EGU_EVENT_TRIGGERED10 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[10]), /**< Event number 10 generated by triggering the corresponding TRIGGER[10] task. */
+    NRF_EGU_EVENT_TRIGGERED11 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[11]), /**< Event number 11 generated by triggering the corresponding TRIGGER[11] task. */
+    NRF_EGU_EVENT_TRIGGERED12 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[12]), /**< Event number 12 generated by triggering the corresponding TRIGGER[12] task. */
+    NRF_EGU_EVENT_TRIGGERED13 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[13]), /**< Event number 13 generated by triggering the corresponding TRIGGER[13] task. */
+    NRF_EGU_EVENT_TRIGGERED14 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[14]), /**< Event number 14 generated by triggering the corresponding TRIGGER[14] task. */
+    NRF_EGU_EVENT_TRIGGERED15 = offsetof(NRF_EGU_Type, EVENTS_TRIGGERED[15])  /**< Event number 15 generated by triggering the corresponding TRIGGER[15] task. */
+    /*lint -restore*/
+} nrf_egu_event_t;
+
+
+/**
+ * @enum  nrf_egu_int_mask_t
+ * @brief EGU interrupts.
+ */
+typedef enum
+{
+    NRF_EGU_INT_TRIGGERED0  = EGU_INTENSET_TRIGGERED0_Msk,  /**< Interrupt on EVENTS_TRIGGERED[0] event. */
+    NRF_EGU_INT_TRIGGERED1  = EGU_INTENSET_TRIGGERED1_Msk,  /**< Interrupt on EVENTS_TRIGGERED[1] event. */
+    NRF_EGU_INT_TRIGGERED2  = EGU_INTENSET_TRIGGERED2_Msk,  /**< Interrupt on EVENTS_TRIGGERED[2] event. */
+    NRF_EGU_INT_TRIGGERED3  = EGU_INTENSET_TRIGGERED3_Msk,  /**< Interrupt on EVENTS_TRIGGERED[3] event. */
+    NRF_EGU_INT_TRIGGERED4  = EGU_INTENSET_TRIGGERED4_Msk,  /**< Interrupt on EVENTS_TRIGGERED[4] event. */
+    NRF_EGU_INT_TRIGGERED5  = EGU_INTENSET_TRIGGERED5_Msk,  /**< Interrupt on EVENTS_TRIGGERED[5] event. */
+    NRF_EGU_INT_TRIGGERED6  = EGU_INTENSET_TRIGGERED6_Msk,  /**< Interrupt on EVENTS_TRIGGERED[6] event. */
+    NRF_EGU_INT_TRIGGERED7  = EGU_INTENSET_TRIGGERED7_Msk,  /**< Interrupt on EVENTS_TRIGGERED[7] event. */
+    NRF_EGU_INT_TRIGGERED8  = EGU_INTENSET_TRIGGERED8_Msk,  /**< Interrupt on EVENTS_TRIGGERED[8] event. */
+    NRF_EGU_INT_TRIGGERED9  = EGU_INTENSET_TRIGGERED9_Msk,  /**< Interrupt on EVENTS_TRIGGERED[9] event. */
+    NRF_EGU_INT_TRIGGERED10 = EGU_INTENSET_TRIGGERED10_Msk, /**< Interrupt on EVENTS_TRIGGERED[10] event. */
+    NRF_EGU_INT_TRIGGERED11 = EGU_INTENSET_TRIGGERED11_Msk, /**< Interrupt on EVENTS_TRIGGERED[11] event. */
+    NRF_EGU_INT_TRIGGERED12 = EGU_INTENSET_TRIGGERED12_Msk, /**< Interrupt on EVENTS_TRIGGERED[12] event. */
+    NRF_EGU_INT_TRIGGERED13 = EGU_INTENSET_TRIGGERED13_Msk, /**< Interrupt on EVENTS_TRIGGERED[13] event. */
+    NRF_EGU_INT_TRIGGERED14 = EGU_INTENSET_TRIGGERED14_Msk, /**< Interrupt on EVENTS_TRIGGERED[14] event. */
+    NRF_EGU_INT_TRIGGERED15 = EGU_INTENSET_TRIGGERED15_Msk, /**< Interrupt on EVENTS_TRIGGERED[15] event. */
+    NRF_EGU_INT_ALL         = 0xFFFFuL
+} nrf_egu_int_mask_t;
+
+/**@brief Function for getting max channel number of given EGU.
+ *
+ * @param NRF_EGUx EGU instance.
+ *
+ * @returns number of available channels.
+ */
+__STATIC_INLINE uint32_t nrf_egu_channel_count(NRF_EGU_Type * NRF_EGUx)
+{
+    if (NRF_EGUx == NRF_EGU0){
+        return EGU0_CH_NUM;
+    }
+    if (NRF_EGUx ==  NRF_EGU1){
+        return EGU1_CH_NUM;
+    }
+    if (NRF_EGUx ==  NRF_EGU2){
+        return EGU2_CH_NUM;
+    }
+    if (NRF_EGUx ==  NRF_EGU3){
+        return EGU3_CH_NUM;
+    }
+    if (NRF_EGUx ==  NRF_EGU4){
+        return EGU4_CH_NUM;
+    }
+    if (NRF_EGUx ==  NRF_EGU5){
+        return EGU5_CH_NUM;
+    }
+    return 0;
+}
+
+/**
+ * @brief Function for triggering a specific EGU task.
+ *
+ * @param NRF_EGUx EGU instance.
+ * @param egu_task EGU task.
+ */
+__STATIC_INLINE void nrf_egu_task_trigger(NRF_EGU_Type * NRF_EGUx, nrf_egu_task_t egu_task)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_task)) = 0x1UL;
+}
+
+
+/**
+ * @brief Function for returning the address of a specific EGU task register.
+ *
+ * @param NRF_EGUx EGU instance.
+ * @param egu_task EGU task.
+ */
+__STATIC_INLINE uint32_t * nrf_egu_task_address_get(NRF_EGU_Type * NRF_EGUx,
+                                                    nrf_egu_task_t egu_task)
+{
+    return (uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_task);
+}
+
+
+/**
+ * @brief Function for returning the address of a specific EGU TRIGGER task register.
+ *
+ * @param NRF_EGUx EGU instance.
+ * @param channel  Channel number.
+ */
+__STATIC_INLINE uint32_t * nrf_egu_task_trigger_addres_get(NRF_EGU_Type * NRF_EGUx,
+                                                           uint8_t channel)
+{
+    ASSERT(channel < nrf_egu_channel_count(NRF_EGUx));
+    return (uint32_t*)&NRF_EGUx->TASKS_TRIGGER[channel];
+}
+
+
+/**
+ * @brief Function for returning the specific EGU TRIGGER task.
+ *
+ * @param NRF_EGUx EGU instance.
+ * @param channel  Channel number.
+ */
+__STATIC_INLINE nrf_egu_task_t nrf_egu_task_trigger_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel)
+{
+    ASSERT(channel < nrf_egu_channel_count(NRF_EGUx));
+    return (nrf_egu_task_t)((uint32_t) NRF_EGU_TASK_TRIGGER0 + (channel * sizeof(uint32_t)));
+}
+
+
+/**
+ * @brief Function for returning the state of a specific EGU event.
+ *
+ * @param NRF_EGUx  EGU instance.
+ * @param egu_event EGU event to check.
+ */
+__STATIC_INLINE bool nrf_egu_event_check(NRF_EGU_Type * NRF_EGUx,
+                                         nrf_egu_event_t egu_event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event);
+}
+
+
+/**
+ * @brief Function for clearing a specific EGU event.
+ *
+ * @param NRF_EGUx  EGU instance.
+ * @param egu_event EGU event to clear.
+ */
+__STATIC_INLINE void nrf_egu_event_clear(NRF_EGU_Type * NRF_EGUx,
+                                         nrf_egu_event_t egu_event)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event)) = 0x0UL;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event));
+    (void)dummy;
+#endif
+}
+
+
+/**
+ * @brief Function for returning the address of a specific EGU event register.
+ *
+ * @param NRF_EGUx  EGU instance.
+ * @param egu_event EGU event.
+ */
+__STATIC_INLINE uint32_t * nrf_egu_event_address_get(NRF_EGU_Type * NRF_EGUx,
+                                                     nrf_egu_event_t egu_event)
+{
+    return (uint32_t *)((uint8_t *)NRF_EGUx + (uint32_t)egu_event);
+}
+
+
+/**
+ * @brief Function for returning the address of a specific EGU TRIGGERED event register.
+ *
+ * @param NRF_EGUx EGU instance.
+ * @param channel  Channel number.
+ */
+__STATIC_INLINE uint32_t * nrf_egu_event_triggered_addres_get(NRF_EGU_Type * NRF_EGUx,
+                                                              uint8_t channel)
+{
+    ASSERT(channel < nrf_egu_channel_count(NRF_EGUx));
+    return (uint32_t*)&NRF_EGUx->EVENTS_TRIGGERED[channel];
+}
+
+
+/**
+ * @brief Function for returning the specific EGU TRIGGERED event.
+ *
+ * @param NRF_EGUx EGU instance.
+ * @param channel  Channel number.
+ */
+__STATIC_INLINE nrf_egu_event_t nrf_egu_event_triggered_get(NRF_EGU_Type * NRF_EGUx,
+                                                            uint8_t channel)
+{
+    ASSERT(channel < nrf_egu_channel_count(NRF_EGUx));
+    return (nrf_egu_event_t)((uint32_t) NRF_EGU_EVENT_TRIGGERED0 + (channel * sizeof(uint32_t)));
+}
+
+
+/**
+ * @brief Function for enabling one or more specific EGU interrupts.
+ *
+ * @param NRF_EGUx     EGU instance.
+ * @param egu_int_mask Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_egu_int_enable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask)
+{
+    NRF_EGUx->INTENSET = egu_int_mask;
+}
+
+
+/**
+ * @brief Function for retrieving the state of one or more EGU interrupts.
+ *
+ * @param NRF_EGUx EGU instance.
+ * @param egu_int_mask Interrupts to check.
+ *
+ * @retval true  If all of the specified interrupts are enabled.
+ * @retval false If at least one of the specified interrupts is disabled.
+ */
+__STATIC_INLINE bool nrf_egu_int_enable_check(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask)
+{
+    return (bool)(NRF_EGUx->INTENSET & egu_int_mask);
+}
+
+
+/**
+ * @brief Function for disabling one or more specific EGU interrupts.
+ *
+ * @param NRF_EGUx     EGU instance.
+ * @param egu_int_mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_egu_int_disable(NRF_EGU_Type * NRF_EGUx, uint32_t egu_int_mask)
+{
+    NRF_EGUx->INTENCLR = egu_int_mask;
+}
+
+/**
+ * @brief Function for retrieving one or more specific EGU interrupts.
+ *
+ * @param NRF_EGUx EGU instance.
+ * @param channel Channel number.
+ *
+ * @returns EGU interrupt mask.
+ */
+__STATIC_INLINE nrf_egu_int_mask_t nrf_egu_int_get(NRF_EGU_Type * NRF_EGUx, uint8_t channel)
+{
+    ASSERT(channel < nrf_egu_channel_count(NRF_EGUx));
+    return (nrf_egu_int_mask_t)((uint32_t) (EGU_INTENSET_TRIGGERED0_Msk << channel));
+}
+
+/** @} */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_gpio.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,793 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef NRF_GPIO_H__
+#define NRF_GPIO_H__
+
+#include "nrf.h"
+#include "nrf_peripherals.h"
+#include "nrf_assert.h"
+#include <stdbool.h>
+#include <stdlib.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrf_gpio GPIO abstraction
+ * @{
+ * @ingroup nrf_drivers
+ * @brief GPIO pin abstraction and port abstraction for reading and writing byte-wise to GPIO ports.
+ */
+
+#if (GPIO_COUNT == 1)
+#define NUMBER_OF_PINS (P0_PIN_NUM)
+#define GPIO_REG_LIST  {NRF_GPIO}
+#elif (GPIO_COUNT == 2)
+#define NUMBER_OF_PINS (P0_PIN_NUM + P1_PIN_NUM)
+#define GPIO_REG_LIST  {NRF_P0, NRF_P1}
+#else
+#error "Not supported."
+#endif
+
+
+/**
+ * @brief Macro for mapping port and pin numbers to values understandable for nrf_gpio functions.
+ */
+#define NRF_GPIO_PIN_MAP(port, pin) ((port << 5) | (pin & 0x1F))
+
+/**
+ * @brief Pin direction definitions.
+ */
+typedef enum
+{
+    NRF_GPIO_PIN_DIR_INPUT  = GPIO_PIN_CNF_DIR_Input, ///< Input.
+    NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< Output.
+} nrf_gpio_pin_dir_t;
+
+/**
+ * @brief Connection of input buffer.
+ */
+typedef enum
+{
+    NRF_GPIO_PIN_INPUT_CONNECT    = GPIO_PIN_CNF_INPUT_Connect,   ///< Connect input buffer.
+    NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< Disconnect input buffer.
+} nrf_gpio_pin_input_t;
+
+/**
+ * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin configuration.
+ */
+typedef enum
+{
+    NRF_GPIO_PIN_NOPULL   = GPIO_PIN_CNF_PULL_Disabled, ///<  Pin pull-up resistor disabled.
+    NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown, ///<  Pin pull-down resistor enabled.
+    NRF_GPIO_PIN_PULLUP   = GPIO_PIN_CNF_PULL_Pullup,   ///<  Pin pull-up resistor enabled.
+} nrf_gpio_pin_pull_t;
+
+/**
+ * @brief Enumerator used for selecting output drive mode.
+ */
+typedef enum
+{
+    NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< !< Standard '0', standard '1'.
+    NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< !< High-drive '0', standard '1'.
+    NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< !< Standard '0', high-drive '1'.
+    NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< !< High drive '0', high-drive '1'.
+    NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< !< Disconnect '0' standard '1'.
+    NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< !< Disconnect '0', high-drive '1'.
+    NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< !< Standard '0', disconnect '1'.
+    NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< !< High-drive '0', disconnect '1'.
+} nrf_gpio_pin_drive_t;
+
+/**
+ * @brief Enumerator used for selecting the pin to sense high or low level on the pin input.
+ */
+typedef enum
+{
+    NRF_GPIO_PIN_NOSENSE    = GPIO_PIN_CNF_SENSE_Disabled, ///<  Pin sense level disabled.
+    NRF_GPIO_PIN_SENSE_LOW  = GPIO_PIN_CNF_SENSE_Low,      ///<  Pin sense low level.
+    NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High,     ///<  Pin sense high level.
+} nrf_gpio_pin_sense_t;
+
+
+#if (__LINT__ != 1)
+
+/**
+ * @brief Function for configuring the GPIO pin range as output pins with normal drive strength.
+ *        This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
+ *
+ * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
+ *
+ * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
+ *
+ * @note For configuring only one pin as output, use @ref nrf_gpio_cfg_output.
+ *       Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
+ */
+__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end);
+
+/**
+ * @brief Function for configuring the GPIO pin range as input pins with given initial value set, hiding inner details.
+ *        This function can be used to configure pin range as simple input.
+ *
+ * @param pin_range_start Specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
+ *
+ * @param pin_range_end Specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30).
+ *
+ * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
+ *
+ * @note  For configuring only one pin as input, use @ref nrf_gpio_cfg_input.
+ *        Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
+ */
+__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t            pin_range_start,
+                                              uint32_t            pin_range_end,
+                                              nrf_gpio_pin_pull_t pull_config);
+
+/**
+ * @brief Pin configuration function.
+ *
+ * The main pin configuration function.
+ * This function allows to set any aspect in PIN_CNF register.
+ * @param pin_number Specifies the pin number.
+ * @param dir        Pin direction.
+ * @param input      Connect or disconnect the input buffer.
+ * @param pull       Pull configuration.
+ * @param drive      Drive configuration.
+ * @param sense      Pin sensing mechanism.
+ */
+__STATIC_INLINE void nrf_gpio_cfg(
+    uint32_t             pin_number,
+    nrf_gpio_pin_dir_t   dir,
+    nrf_gpio_pin_input_t input,
+    nrf_gpio_pin_pull_t  pull,
+    nrf_gpio_pin_drive_t drive,
+    nrf_gpio_pin_sense_t sense);
+
+/**
+ * @brief Function for configuring the given GPIO pin number as output, hiding inner details.
+ *        This function can be used to configure a pin as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
+ *
+ * @param pin_number Specifies the pin number.
+ *
+ * @note  Sense capability on the pin is disabled and input is disconnected from the buffer as the pins are configured as output.
+ */
+__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number);
+
+/**
+ * @brief Function for configuring the given GPIO pin number as input, hiding inner details.
+ *        This function can be used to configure a pin as simple input.
+ *
+ * @param pin_number Specifies the pin number.
+ * @param pull_config State of the pin range pull resistor (no pull, pulled down, or pulled high).
+ *
+ * @note  Sense capability on the pin is disabled and input is connected to buffer so that the GPIO->IN register is readable.
+ */
+__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config);
+
+/**
+ * @brief Function for resetting pin configuration to its default state.
+ *
+ * @param pin_number Specifies the pin number.
+ */
+__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number);
+
+/**
+ * @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected.
+ *
+ * @param pin_number Specifies the pin number.
+ *
+ */
+__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number);
+
+/**
+ * @brief Function for disconnecting input for the given GPIO.
+ *
+ * @param pin_number Specifies the pin number.
+ *
+ */
+__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number);
+
+/**
+ * @brief Function for configuring the given GPIO pin number as input, hiding inner details.
+ *        This function can be used to configure pin range as simple input.
+ *        Sense capability on the pin is configurable and input is connected to buffer so that the GPIO->IN register is readable.
+ *
+ * @param pin_number   Specifies the pin number.
+ * @param pull_config  State of the pin pull resistor (no pull, pulled down, or pulled high).
+ * @param sense_config Sense level of the pin (no sense, sense low, or sense high).
+ */
+__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t             pin_number,
+                                              nrf_gpio_pin_pull_t  pull_config,
+                                              nrf_gpio_pin_sense_t sense_config);
+
+/**
+ * @brief Function for configuring sense level for the given GPIO.
+ *
+ * @param pin_number   Specifies the pin number.
+ * @param sense_config Sense configuration.
+ *
+ */
+__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config);
+
+/**
+ * @brief Function for setting the direction for a GPIO pin.
+ *
+ * @param pin_number Specifies the pin number for which to set the direction.
+ *
+ * @param direction Specifies the direction.
+ */
+__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction);
+
+/**
+ * @brief Function for setting a GPIO pin.
+ *
+ * Note that the pin must be configured as an output for this function to have any effect.
+ *
+ * @param pin_number Specifies the pin number to set.
+ */
+__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number);
+
+/**
+ * @brief Function for clearing a GPIO pin.
+ *
+ * Note that the pin must be configured as an output for this
+ * function to have any effect.
+ *
+ * @param pin_number Specifies the pin number to clear.
+ */
+__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number);
+
+/**
+ * @brief Function for toggling a GPIO pin.
+ *
+ * Note that the pin must be configured as an output for this
+ * function to have any effect.
+ *
+ * @param pin_number Specifies the pin number to toggle.
+ */
+__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number);
+
+/**
+ * @brief Function for writing a value to a GPIO pin.
+ *
+ * Note that the pin must be configured as an output for this
+ * function to have any effect.
+ *
+ * @param pin_number Specifies the pin number to write.
+ *
+ * @param value Specifies the value to be written to the pin.
+ * @arg 0 Clears the pin.
+ * @arg >=1 Sets the pin.
+ */
+__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value);
+
+/**
+ * @brief Function for reading the input level of a GPIO pin.
+ *
+ * Note that the pin must have input connected for the value
+ * returned from this function to be valid.
+ *
+ * @param pin_number Specifies the pin number to read.
+ *
+ * @return 0 if the pin input level is low. Positive value if the pin is high.
+ */
+__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number);
+
+/**
+ * @brief Function for reading the output level of a GPIO pin.
+ *
+ * @param pin_number Specifies the pin number to read.
+ *
+ * @return 0 if the pin output level is low. Positive value if pin output is high.
+ */
+__STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number);
+
+/**
+ * @brief Function for reading the sense configuration of a GPIO pin.
+ *
+ * @param pin_number Specifies the pin number to read.
+ *
+ * @retval Sense configuration.
+ */
+__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number);
+
+/**
+ * @brief Function for setting output direction on selected pins on a given port.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ * @param out_mask Mask specifying the pins to set as output.
+ *
+ */
+__STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask);
+
+/**
+ * @brief Function for setting input direction on selected pins on a given port.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ * @param in_mask  Mask specifying the pins to set as input.
+ *
+ */
+__STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask);
+
+/**
+ * @brief Function for writing the direction configuration of GPIO pins in a given port.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ * @param dir_mask Mask specifying the direction of pins. Bit set means that the given pin is configured as output.
+ *
+ */
+__STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t dir_mask);
+
+/**
+ * @brief Function for reading the direction configuration of a GPIO port.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ *
+ * @retval Pin configuration of the current direction settings. Bit set means that the given pin is configured as output.
+ */
+__STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg);
+
+/**
+ * @brief Function for reading the input signals of GPIO pins on a given port.
+ *
+ * @param p_reg Pointer to the peripheral registers structure.
+ *
+ * @retval Port input values.
+ */
+__STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg);
+
+/**
+ * @brief Function for reading the output signals of GPIO pins of a given port.
+ *
+ * @param p_reg Pointer to the peripheral registers structure.
+ *
+ * @retval Port output values.
+ */
+__STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg);
+
+/**
+ * @brief Function for writing the GPIO pins output on a given port.
+ *
+ * @param p_reg Pointer to the peripheral registers structure.
+ * @param value Output port mask.
+ *
+ */
+__STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value);
+
+/**
+ * @brief Function for setting high level on selected GPIO pins of a given port.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ * @param set_mask Mask with pins to set as logical high level.
+ *
+ */
+__STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask);
+
+/**
+ * @brief Function for setting low level on selected GPIO pins of a given port.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ * @param clr_mask Mask with pins to set as logical low level.
+ *
+ */
+__STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask);
+
+/**
+ * @brief Function for reading pins state of multiple consecutive ports.
+ *
+ * @param start_port Index of the first port to read.
+ * @param length     Number of ports to read.
+ * @param p_masks    Pointer to output array where port states will be stored.
+ */
+__STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks);
+
+#ifdef GPIO_DETECTMODE_DETECTMODE_LDETECT
+/**
+ * @brief Function for reading latch state of multiple consecutive ports.
+ *
+ * @param start_port Index of the first port to read.
+ * @param length     Number of ports to read.
+ * @param p_masks    Pointer to output array where latch states will be stored.
+ */
+__STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, uint32_t length,
+                                           uint32_t * p_masks);
+
+/**
+ * @brief Function for reading latch state of single pin.
+ *
+ * @param pin_number Pin number.
+ * @return 0 if latch is not set. Positive value otherwise.
+ *
+ */
+__STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number);
+
+/**
+ * @brief Function for clearing latch state of a single pin.
+ *
+ * @param pin_number Pin number.
+ *
+ */
+__STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number);
+#endif
+
+
+#endif // #ifndef (__LINT__ != 1)
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+/**
+ * @brief Function for extracting port and relative pin number from absolute pin number.
+ *
+ * @param[inout] Pointer to absolute pin number which is overriden by relative to port pin number.
+ *
+ * @return Pointer to port register set.
+ *
+ */
+__STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin)
+{
+    ASSERT(*p_pin < NUMBER_OF_PINS);
+#if (GPIO_COUNT == 1)
+    // The oldest definition case
+    return NRF_GPIO;
+#else
+    if (*p_pin < P0_PIN_NUM)
+    {
+        return NRF_P0;
+    }
+    else
+    {
+        *p_pin = *p_pin & (P0_PIN_NUM - 1);
+        return NRF_P1;
+    }
+#endif
+}
+
+
+__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end)
+{
+    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
+    for (; pin_range_start <= pin_range_end; pin_range_start++)
+    {
+        nrf_gpio_cfg_output(pin_range_start);
+    }
+}
+
+
+__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t            pin_range_start,
+                                              uint32_t            pin_range_end,
+                                              nrf_gpio_pin_pull_t pull_config)
+{
+    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
+    for (; pin_range_start <= pin_range_end; pin_range_start++)
+    {
+        nrf_gpio_cfg_input(pin_range_start, pull_config);
+    }
+}
+
+
+__STATIC_INLINE void nrf_gpio_cfg(
+    uint32_t             pin_number,
+    nrf_gpio_pin_dir_t   dir,
+    nrf_gpio_pin_input_t input,
+    nrf_gpio_pin_pull_t  pull,
+    nrf_gpio_pin_drive_t drive,
+    nrf_gpio_pin_sense_t sense)
+{
+    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+
+    reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos)
+                               | ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos)
+                               | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos)
+                               | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos)
+                               | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos);
+}
+
+
+__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number)
+{
+    nrf_gpio_cfg(
+        pin_number,
+        NRF_GPIO_PIN_DIR_OUTPUT,
+        NRF_GPIO_PIN_INPUT_DISCONNECT,
+        NRF_GPIO_PIN_NOPULL,
+        NRF_GPIO_PIN_S0S1,
+        NRF_GPIO_PIN_NOSENSE);
+}
+
+
+__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config)
+{
+    nrf_gpio_cfg(
+        pin_number,
+        NRF_GPIO_PIN_DIR_INPUT,
+        NRF_GPIO_PIN_INPUT_CONNECT,
+        pull_config,
+        NRF_GPIO_PIN_S0S1,
+        NRF_GPIO_PIN_NOSENSE);
+}
+
+
+__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number)
+{
+    nrf_gpio_cfg(
+        pin_number,
+        NRF_GPIO_PIN_DIR_INPUT,
+        NRF_GPIO_PIN_INPUT_DISCONNECT,
+        NRF_GPIO_PIN_NOPULL,
+        NRF_GPIO_PIN_S0S1,
+        NRF_GPIO_PIN_NOSENSE);
+}
+
+
+__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number)
+{
+    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
+    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk;
+
+    reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos);
+}
+
+
+__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number)
+{
+    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
+    uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk;
+
+    reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos);
+}
+
+
+__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t             pin_number,
+                                              nrf_gpio_pin_pull_t  pull_config,
+                                              nrf_gpio_pin_sense_t sense_config)
+{
+    nrf_gpio_cfg(
+        pin_number,
+        NRF_GPIO_PIN_DIR_INPUT,
+        NRF_GPIO_PIN_INPUT_CONNECT,
+        pull_config,
+        NRF_GPIO_PIN_S0S1,
+        sense_config);
+}
+
+
+__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config)
+{
+    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+
+    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
+    reg->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_SENSE_Msk;
+    reg->PIN_CNF[pin_number] |= (sense_config << GPIO_PIN_CNF_SENSE_Pos);
+}
+
+
+__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction)
+{
+    if (direction == NRF_GPIO_PIN_DIR_INPUT)
+    {
+        nrf_gpio_cfg(
+            pin_number,
+            NRF_GPIO_PIN_DIR_INPUT,
+            NRF_GPIO_PIN_INPUT_CONNECT,
+            NRF_GPIO_PIN_NOPULL,
+            NRF_GPIO_PIN_S0S1,
+            NRF_GPIO_PIN_NOSENSE);
+    }
+    else
+    {
+        NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+        reg->DIRSET = (1UL << pin_number);
+    }
+}
+
+
+__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number)
+{
+    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+
+    nrf_gpio_port_out_set(reg, 1UL << pin_number);
+}
+
+
+__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number)
+{
+    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+
+    nrf_gpio_port_out_clear(reg, 1UL << pin_number);
+}
+
+
+__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number)
+{
+    NRF_GPIO_Type * reg        = nrf_gpio_pin_port_decode(&pin_number);
+    uint32_t        pins_state = reg->OUT;
+
+    reg->OUTSET = (~pins_state & (1UL << pin_number));
+    reg->OUTCLR = (pins_state & (1UL << pin_number));
+}
+
+
+__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value)
+{
+    if (value == 0)
+    {
+        nrf_gpio_pin_clear(pin_number);
+    }
+    else
+    {
+        nrf_gpio_pin_set(pin_number);
+    }
+}
+
+
+__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number)
+{
+    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+
+    return ((nrf_gpio_port_in_read(reg) >> pin_number) & 1UL);
+}
+
+
+__STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin_number)
+{
+    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+
+    return ((nrf_gpio_port_out_read(reg) >> pin_number) & 1UL);
+}
+
+
+__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number)
+{
+    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+
+    return (nrf_gpio_pin_sense_t)((reg->PIN_CNF[pin_number] &
+                                   GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
+}
+
+
+__STATIC_INLINE void nrf_gpio_port_dir_output_set(NRF_GPIO_Type * p_reg, uint32_t out_mask)
+{
+    p_reg->DIRSET = out_mask;
+}
+
+
+__STATIC_INLINE void nrf_gpio_port_dir_input_set(NRF_GPIO_Type * p_reg, uint32_t in_mask)
+{
+    p_reg->DIRCLR = in_mask;
+}
+
+
+__STATIC_INLINE void nrf_gpio_port_dir_write(NRF_GPIO_Type * p_reg, uint32_t value)
+{
+    p_reg->DIR = value;
+}
+
+
+__STATIC_INLINE uint32_t nrf_gpio_port_dir_read(NRF_GPIO_Type const * p_reg)
+{
+    return p_reg->DIR;
+}
+
+
+__STATIC_INLINE uint32_t nrf_gpio_port_in_read(NRF_GPIO_Type const * p_reg)
+{
+    return p_reg->IN;
+}
+
+
+__STATIC_INLINE uint32_t nrf_gpio_port_out_read(NRF_GPIO_Type const * p_reg)
+{
+    return p_reg->OUT;
+}
+
+
+__STATIC_INLINE void nrf_gpio_port_out_write(NRF_GPIO_Type * p_reg, uint32_t value)
+{
+    p_reg->OUT = value;
+}
+
+
+__STATIC_INLINE void nrf_gpio_port_out_set(NRF_GPIO_Type * p_reg, uint32_t set_mask)
+{
+    p_reg->OUTSET = set_mask;
+}
+
+
+__STATIC_INLINE void nrf_gpio_port_out_clear(NRF_GPIO_Type * p_reg, uint32_t clr_mask)
+{
+    p_reg->OUTCLR = clr_mask;
+}
+
+
+__STATIC_INLINE void nrf_gpio_ports_read(uint32_t start_port, uint32_t length, uint32_t * p_masks)
+{
+    NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
+
+    ASSERT(start_port + length <= GPIO_COUNT);
+    uint32_t i;
+
+    for (i = start_port; i < (start_port + length); i++)
+    {
+        *p_masks = nrf_gpio_port_in_read(gpio_regs[i]);
+        p_masks++;
+    }
+}
+
+
+#ifdef GPIO_DETECTMODE_DETECTMODE_LDETECT
+__STATIC_INLINE void nrf_gpio_latches_read(uint32_t start_port, uint32_t length, uint32_t * p_masks)
+{
+    NRF_GPIO_Type * gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
+    uint32_t        i;
+
+    for (i = start_port; i < (start_port + length); i++)
+    {
+        *p_masks = gpio_regs[i]->LATCH;
+        p_masks++;
+    }
+}
+
+
+__STATIC_INLINE uint32_t nrf_gpio_pin_latch_get(uint32_t pin_number)
+{
+    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+
+    return (reg->LATCH & (1 << pin_number)) ? 1 : 0;
+}
+
+
+__STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number)
+{
+    NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
+
+    reg->LATCH = (1 << pin_number);
+}
+
+
+#endif
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+/** @} */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_gpiote.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,428 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef NRF_GPIOTE_H__
+#define NRF_GPIOTE_H__
+
+#include "nrf_peripherals.h"
+#include "nrf.h"
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef GPIOTE_CONFIG_PORT_Msk
+#define GPIOTE_CONFIG_PORT_PIN_Msk (GPIOTE_CONFIG_PORT_Msk | GPIOTE_CONFIG_PSEL_Msk)
+#else
+#define GPIOTE_CONFIG_PORT_PIN_Msk GPIOTE_CONFIG_PSEL_Msk
+#endif
+/**
+* @defgroup nrf_gpiote_abs GPIOTE abstraction
+* @{
+* @ingroup nrf_gpiote
+* @brief GPIOTE abstraction for configuration of channels.
+*/
+
+ /**
+ * @enum nrf_gpiote_polarity_t
+ * @brief Polarity for the GPIOTE channel.
+ */
+typedef enum
+{
+  NRF_GPIOTE_POLARITY_LOTOHI = GPIOTE_CONFIG_POLARITY_LoToHi,       ///<  Low to high.
+  NRF_GPIOTE_POLARITY_HITOLO = GPIOTE_CONFIG_POLARITY_HiToLo,       ///<  High to low.
+  NRF_GPIOTE_POLARITY_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle        ///<  Toggle.
+} nrf_gpiote_polarity_t;
+
+
+ /**
+ * @enum nrf_gpiote_outinit_t
+ * @brief Initial output value for the GPIOTE channel.
+ */
+typedef enum
+{
+  NRF_GPIOTE_INITIAL_VALUE_LOW  = GPIOTE_CONFIG_OUTINIT_Low,       ///<  Low to high.
+  NRF_GPIOTE_INITIAL_VALUE_HIGH = GPIOTE_CONFIG_OUTINIT_High       ///<  High to low.
+} nrf_gpiote_outinit_t;
+
+/**
+ * @brief Tasks.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_GPIOTE_TASKS_OUT_0     = offsetof(NRF_GPIOTE_Type, TASKS_OUT[0]), /**< Out task 0.*/
+    NRF_GPIOTE_TASKS_OUT_1     = offsetof(NRF_GPIOTE_Type, TASKS_OUT[1]), /**< Out task 1.*/
+    NRF_GPIOTE_TASKS_OUT_2     = offsetof(NRF_GPIOTE_Type, TASKS_OUT[2]), /**< Out task 2.*/
+    NRF_GPIOTE_TASKS_OUT_3     = offsetof(NRF_GPIOTE_Type, TASKS_OUT[3]), /**< Out task 3.*/
+#if (GPIOTE_CH_NUM > 4) || defined(__SDK_DOXYGEN__)
+    NRF_GPIOTE_TASKS_OUT_4     = offsetof(NRF_GPIOTE_Type, TASKS_OUT[4]), /**< Out task 4.*/
+    NRF_GPIOTE_TASKS_OUT_5     = offsetof(NRF_GPIOTE_Type, TASKS_OUT[5]), /**< Out task 5.*/
+    NRF_GPIOTE_TASKS_OUT_6     = offsetof(NRF_GPIOTE_Type, TASKS_OUT[6]), /**< Out task 6.*/
+    NRF_GPIOTE_TASKS_OUT_7     = offsetof(NRF_GPIOTE_Type, TASKS_OUT[7]), /**< Out task 7.*/
+#endif
+#if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__SDK_DOXYGEN__)
+    NRF_GPIOTE_TASKS_SET_0     = offsetof(NRF_GPIOTE_Type, TASKS_SET[0]), /**< Set task 0.*/
+    NRF_GPIOTE_TASKS_SET_1     = offsetof(NRF_GPIOTE_Type, TASKS_SET[1]), /**< Set task 1.*/
+    NRF_GPIOTE_TASKS_SET_2     = offsetof(NRF_GPIOTE_Type, TASKS_SET[2]), /**< Set task 2.*/
+    NRF_GPIOTE_TASKS_SET_3     = offsetof(NRF_GPIOTE_Type, TASKS_SET[3]), /**< Set task 3.*/
+    NRF_GPIOTE_TASKS_SET_4     = offsetof(NRF_GPIOTE_Type, TASKS_SET[4]), /**< Set task 4.*/
+    NRF_GPIOTE_TASKS_SET_5     = offsetof(NRF_GPIOTE_Type, TASKS_SET[5]), /**< Set task 5.*/
+    NRF_GPIOTE_TASKS_SET_6     = offsetof(NRF_GPIOTE_Type, TASKS_SET[6]), /**< Set task 6.*/
+    NRF_GPIOTE_TASKS_SET_7     = offsetof(NRF_GPIOTE_Type, TASKS_SET[7]), /**< Set task 7.*/
+#endif
+#if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__SDK_DOXYGEN__)
+    NRF_GPIOTE_TASKS_CLR_0     = offsetof(NRF_GPIOTE_Type, TASKS_CLR[0]), /**< Clear task 0.*/
+    NRF_GPIOTE_TASKS_CLR_1     = offsetof(NRF_GPIOTE_Type, TASKS_CLR[1]), /**< Clear task 1.*/
+    NRF_GPIOTE_TASKS_CLR_2     = offsetof(NRF_GPIOTE_Type, TASKS_CLR[2]), /**< Clear task 2.*/
+    NRF_GPIOTE_TASKS_CLR_3     = offsetof(NRF_GPIOTE_Type, TASKS_CLR[3]), /**< Clear task 3.*/
+    NRF_GPIOTE_TASKS_CLR_4     = offsetof(NRF_GPIOTE_Type, TASKS_CLR[4]), /**< Clear task 4.*/
+    NRF_GPIOTE_TASKS_CLR_5     = offsetof(NRF_GPIOTE_Type, TASKS_CLR[5]), /**< Clear task 5.*/
+    NRF_GPIOTE_TASKS_CLR_6     = offsetof(NRF_GPIOTE_Type, TASKS_CLR[6]), /**< Clear task 6.*/
+    NRF_GPIOTE_TASKS_CLR_7     = offsetof(NRF_GPIOTE_Type, TASKS_CLR[7]), /**< Clear task 7.*/
+#endif
+    /*lint -restore*/
+} nrf_gpiote_tasks_t;
+
+/**
+ * @brief Events.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_GPIOTE_EVENTS_IN_0     = offsetof(NRF_GPIOTE_Type, EVENTS_IN[0]), /**< In event 0.*/
+    NRF_GPIOTE_EVENTS_IN_1     = offsetof(NRF_GPIOTE_Type, EVENTS_IN[1]), /**< In event 1.*/
+    NRF_GPIOTE_EVENTS_IN_2     = offsetof(NRF_GPIOTE_Type, EVENTS_IN[2]), /**< In event 2.*/
+    NRF_GPIOTE_EVENTS_IN_3     = offsetof(NRF_GPIOTE_Type, EVENTS_IN[3]), /**< In event 3.*/
+#if (GPIOTE_CH_NUM > 4) || defined(__SDK_DOXYGEN__)
+    NRF_GPIOTE_EVENTS_IN_4     = offsetof(NRF_GPIOTE_Type, EVENTS_IN[4]), /**< In event 4.*/
+    NRF_GPIOTE_EVENTS_IN_5     = offsetof(NRF_GPIOTE_Type, EVENTS_IN[5]), /**< In event 5.*/
+    NRF_GPIOTE_EVENTS_IN_6     = offsetof(NRF_GPIOTE_Type, EVENTS_IN[6]), /**< In event 6.*/
+    NRF_GPIOTE_EVENTS_IN_7     = offsetof(NRF_GPIOTE_Type, EVENTS_IN[7]), /**< In event 7.*/
+#endif
+    NRF_GPIOTE_EVENTS_PORT     = offsetof(NRF_GPIOTE_Type, EVENTS_PORT), /**<  Port event.*/
+    /*lint -restore*/
+} nrf_gpiote_events_t;
+
+/**
+ * @enum nrf_gpiote_int_t
+ * @brief GPIOTE interrupts.
+ */
+typedef enum
+{
+    NRF_GPIOTE_INT_IN0_MASK  = GPIOTE_INTENSET_IN0_Msk,  /**< GPIOTE interrupt from IN0. */
+    NRF_GPIOTE_INT_IN1_MASK  = GPIOTE_INTENSET_IN1_Msk,  /**< GPIOTE interrupt from IN1. */
+    NRF_GPIOTE_INT_IN2_MASK  = GPIOTE_INTENSET_IN2_Msk,  /**< GPIOTE interrupt from IN2. */
+    NRF_GPIOTE_INT_IN3_MASK  = GPIOTE_INTENSET_IN3_Msk,  /**< GPIOTE interrupt from IN3. */
+#if (GPIOTE_CH_NUM > 4) || defined(__SDK_DOXYGEN__)
+    NRF_GPIOTE_INT_IN4_MASK  = GPIOTE_INTENSET_IN4_Msk,  /**< GPIOTE interrupt from IN4. */
+    NRF_GPIOTE_INT_IN5_MASK  = GPIOTE_INTENSET_IN5_Msk,  /**< GPIOTE interrupt from IN5. */
+    NRF_GPIOTE_INT_IN6_MASK  = GPIOTE_INTENSET_IN6_Msk,  /**< GPIOTE interrupt from IN6. */
+    NRF_GPIOTE_INT_IN7_MASK  = GPIOTE_INTENSET_IN7_Msk,  /**< GPIOTE interrupt from IN7. */
+#endif
+    NRF_GPIOTE_INT_PORT_MASK = (int)GPIOTE_INTENSET_PORT_Msk, /**< GPIOTE interrupt from PORT event. */
+} nrf_gpiote_int_t;
+
+#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\
+                                NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK)
+#if (GPIOTE_CH_NUM > 4)
+#undef NRF_GPIOTE_INT_IN_MASK
+#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\
+                                NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK |\
+                                NRF_GPIOTE_INT_IN4_MASK | NRF_GPIOTE_INT_IN5_MASK |\
+                                NRF_GPIOTE_INT_IN6_MASK | NRF_GPIOTE_INT_IN7_MASK)
+#endif
+
+/**
+ * @brief Function for activating a specific GPIOTE task.
+ *
+ * @param[in]  task Task.
+ */
+__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task);
+
+/**
+ * @brief Function for getting the address of a specific GPIOTE task.
+ *
+ * @param[in] task Task.
+ *
+ * @returns Address.
+ */
+__STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task);
+
+/**
+ * @brief Function for getting the state of a specific GPIOTE event.
+ *
+ * @param[in] event Event.
+ */
+__STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event);
+
+/**
+ * @brief Function for clearing a specific GPIOTE event.
+ *
+ * @param[in] event Event.
+ */
+__STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event);
+
+/**
+ * @brief Function for getting the address of a specific GPIOTE event.
+ *
+ * @param[in] event Event.
+ *
+ * @return Address
+ */
+__STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event);
+
+/**@brief Function for enabling interrupts.
+ *
+ * @param[in]  mask          Interrupt mask to be enabled.
+ */
+__STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask);
+
+/**@brief Function for disabling interrupts.
+ *
+ * @param[in]  mask          Interrupt mask to be disabled.
+ */
+__STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask);
+
+/**@brief Function for checking if interrupts are enabled.
+ *
+ * @param[in]  mask          Mask of interrupt flags to check.
+ *
+ * @return                   Mask with enabled interrupts.
+ */
+__STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask);
+
+/**@brief Function for enabling a GPIOTE event.
+ *
+ * @param[in]  idx        Task-Event index.
+ */
+__STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx);
+
+/**@brief Function for disabling a GPIOTE event.
+ *
+ * @param[in]  idx        Task-Event index.
+ */
+__STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx);
+
+/**@brief Function for configuring a GPIOTE event.
+ *
+ * @param[in]  idx        Task-Event index.
+ * @param[in]  pin        Pin associated with event.
+ * @param[in]  polarity   Transition that should generate an event.
+ */
+__STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin,
+                                                nrf_gpiote_polarity_t polarity);
+
+/**@brief Function for getting the pin associated with a GPIOTE event.
+ *
+ * @param[in]  idx        Task-Event index.
+ *
+ * @return Pin number.
+ */
+__STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx);
+
+/**@brief Function for getting the polarity associated with a GPIOTE event.
+ *
+ * @param[in]  idx        Task-Event index.
+ *
+ * @return Polarity.
+ */
+__STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx);
+
+/**@brief Function for enabling a GPIOTE task.
+ *
+ * @param[in]  idx        Task-Event index.
+ */
+__STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx);
+
+/**@brief Function for disabling a GPIOTE task.
+ *
+ * @param[in]  idx        Task-Event index.
+ */
+__STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx);
+
+/**@brief Function for configuring a GPIOTE task.
+ * @note  Function is not configuring mode field so task is disabled after this function is called.
+ *
+ * @param[in]  idx        Task-Event index.
+ * @param[in]  pin        Pin associated with event.
+ * @param[in]  polarity   Transition that should generate an event.
+ * @param[in]  init_val   Initial value of the pin.
+ */
+__STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin,
+                                               nrf_gpiote_polarity_t polarity,
+                                               nrf_gpiote_outinit_t  init_val);
+
+/**@brief Function for forcing a specific state on the pin connected to GPIOTE.
+ *
+ * @param[in]  idx        Task-Event index.
+ * @param[in]  init_val   Pin state.
+ */
+__STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val);
+
+/**@brief Function for resetting a GPIOTE task event configuration to the default state.
+ *
+ * @param[in]  idx        Task-Event index.
+ */
+__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task)
+{
+    *(__IO uint32_t *)((uint32_t)NRF_GPIOTE + task) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task)
+{
+    return ((uint32_t)NRF_GPIOTE + task);
+}
+
+__STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event)
+{
+    return (*(uint32_t *)nrf_gpiote_event_addr_get(event) == 0x1UL) ? true : false;
+}
+
+__STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event)
+{
+    *(uint32_t *)nrf_gpiote_event_addr_get(event) = 0;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)nrf_gpiote_event_addr_get(event));
+    (void)dummy;
+#endif
+}
+
+__STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event)
+{
+    return ((uint32_t)NRF_GPIOTE + event);
+}
+
+__STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask)
+{
+    NRF_GPIOTE->INTENSET = mask;
+}
+
+__STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask)
+{
+    NRF_GPIOTE->INTENCLR = mask;
+}
+
+__STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask)
+{
+    return (NRF_GPIOTE->INTENSET & mask);
+}
+
+__STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx)
+{
+   NRF_GPIOTE->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
+}
+
+__STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx)
+{
+   NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event;
+}
+
+__STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin, nrf_gpiote_polarity_t polarity)
+{
+  NRF_GPIOTE->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk | GPIOTE_CONFIG_POLARITY_Msk);
+  NRF_GPIOTE->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
+                              ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
+}
+
+__STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx)
+{
+    return ((NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_PORT_PIN_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
+}
+
+__STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx)
+{
+    return (nrf_gpiote_polarity_t)((NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >> GPIOTE_CONFIG_POLARITY_Pos);
+}
+
+__STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx)
+{
+    uint32_t final_config = NRF_GPIOTE->CONFIG[idx] | GPIOTE_CONFIG_MODE_Task;
+#ifdef NRF51
+    /* Workaround for the OUTINIT PAN. When nrf_gpiote_task_config() is called a glitch happens
+    on the GPIO if the GPIO in question is already assigned to GPIOTE and the pin is in the
+    correct state in GPIOTE but not in the OUT register. */
+    /* Configure channel to not existing, not connected to the pin, and configure as a tasks that will set it to proper level */
+    NRF_GPIOTE->CONFIG[idx] = final_config | (((31) << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk);
+    __NOP();
+    __NOP();
+    __NOP();
+#endif
+    NRF_GPIOTE->CONFIG[idx] = final_config;
+}
+
+__STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx)
+{
+    NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Task;
+}
+
+__STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin,
+                                                nrf_gpiote_polarity_t polarity,
+                                                nrf_gpiote_outinit_t  init_val)
+{
+  NRF_GPIOTE->CONFIG[idx] &= ~(GPIOTE_CONFIG_PORT_PIN_Msk |
+                               GPIOTE_CONFIG_POLARITY_Msk |
+                               GPIOTE_CONFIG_OUTINIT_Msk);
+
+  NRF_GPIOTE->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PORT_PIN_Msk) |
+                             ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
+                             ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
+}
+
+__STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val)
+{
+    NRF_GPIOTE->CONFIG[idx] = (NRF_GPIOTE->CONFIG[idx] & ~GPIOTE_CONFIG_OUTINIT_Msk)
+                              | ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
+}
+
+__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx)
+{
+    NRF_GPIOTE->CONFIG[idx] = 0;
+}
+#endif //SUPPRESS_INLINE_IMPLEMENTATION
+/** @} */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_i2s.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,562 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @defgroup nrf_i2s_hal I2S HAL
+ * @{
+ * @ingroup nrf_i2s
+ *
+ * @brief @tagAPI52 Hardware access layer for managing the Inter-IC Sound (I2S) peripheral.
+ */
+
+#ifndef NRF_I2S_H__
+#define NRF_I2S_H__
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @brief This value can be provided as a parameter for the @ref nrf_i2s_pins_set
+ *        function call to specify that a given I2S signal (SDOUT, SDIN, or MCK)
+ *        shall not be connected to a physical pin.
+ */
+#define NRF_I2S_PIN_NOT_CONNECTED  0xFFFFFFFF
+
+
+/**
+ * @brief I2S tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_I2S_TASK_START = offsetof(NRF_I2S_Type, TASKS_START), ///< Starts continuous I2S transfer. Also starts the MCK generator if this is enabled.
+    NRF_I2S_TASK_STOP  = offsetof(NRF_I2S_Type, TASKS_STOP)   ///< Stops I2S transfer. Also stops the MCK generator.
+    /*lint -restore*/
+} nrf_i2s_task_t;
+
+/**
+ * @brief I2S events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_I2S_EVENT_RXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_RXPTRUPD), ///< The RXD.PTR register has been copied to internal double-buffers.
+    NRF_I2S_EVENT_TXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_TXPTRUPD), ///< The TXD.PTR register has been copied to internal double-buffers.
+    NRF_I2S_EVENT_STOPPED  = offsetof(NRF_I2S_Type, EVENTS_STOPPED)   ///< I2S transfer stopped.
+    /*lint -restore*/
+} nrf_i2s_event_t;
+
+/**
+ * @brief I2S interrupts.
+ */
+typedef enum
+{
+    NRF_I2S_INT_RXPTRUPD_MASK = I2S_INTENSET_RXPTRUPD_Msk, ///< Interrupt on RXPTRUPD event.
+    NRF_I2S_INT_TXPTRUPD_MASK = I2S_INTENSET_TXPTRUPD_Msk, ///< Interrupt on TXPTRUPD event.
+    NRF_I2S_INT_STOPPED_MASK  = I2S_INTENSET_STOPPED_Msk   ///< Interrupt on STOPPED event.
+} nrf_i2s_int_mask_t;
+
+/**
+ * @brief I2S modes of operation.
+ */
+typedef enum
+{
+    NRF_I2S_MODE_MASTER = I2S_CONFIG_MODE_MODE_Master, ///< Master mode.
+    NRF_I2S_MODE_SLAVE  = I2S_CONFIG_MODE_MODE_Slave   ///< Slave mode.
+} nrf_i2s_mode_t;
+
+/**
+ * @brief I2S master clock generator settings.
+ */
+typedef enum
+{
+    NRF_I2S_MCK_DISABLED  = 0,                                       ///< MCK disabled.
+    // [conversion to 'int' needed to prevent compilers from complaining
+    //  that the provided value (0x80000000UL) is out of range of "int"]
+    NRF_I2S_MCK_32MDIV2   = (int)I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2, ///< 32 MHz / 2 = 16.0 MHz.
+    NRF_I2S_MCK_32MDIV3   = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3,      ///< 32 MHz / 3 = 10.6666667 MHz.
+    NRF_I2S_MCK_32MDIV4   = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4,      ///< 32 MHz / 4 = 8.0 MHz.
+    NRF_I2S_MCK_32MDIV5   = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5,      ///< 32 MHz / 5 = 6.4 MHz.
+    NRF_I2S_MCK_32MDIV6   = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6,      ///< 32 MHz / 6 = 5.3333333 MHz.
+    NRF_I2S_MCK_32MDIV8   = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8,      ///< 32 MHz / 8 = 4.0 MHz.
+    NRF_I2S_MCK_32MDIV10  = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10,     ///< 32 MHz / 10 = 3.2 MHz.
+    NRF_I2S_MCK_32MDIV11  = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11,     ///< 32 MHz / 11 = 2.9090909 MHz.
+    NRF_I2S_MCK_32MDIV15  = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15,     ///< 32 MHz / 15 = 2.1333333 MHz.
+    NRF_I2S_MCK_32MDIV16  = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16,     ///< 32 MHz / 16 = 2.0 MHz.
+    NRF_I2S_MCK_32MDIV21  = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21,     ///< 32 MHz / 21 = 1.5238095 MHz.
+    NRF_I2S_MCK_32MDIV23  = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23,     ///< 32 MHz / 23 = 1.3913043 MHz.
+    NRF_I2S_MCK_32MDIV31  = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31,     ///< 32 MHz / 31 = 1.0322581 MHz.
+    NRF_I2S_MCK_32MDIV42  = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42,     ///< 32 MHz / 42 = 0.7619048 MHz.
+    NRF_I2S_MCK_32MDIV63  = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63,     ///< 32 MHz / 63 = 0.5079365 MHz.
+    NRF_I2S_MCK_32MDIV125 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125     ///< 32 MHz / 125 = 0.256 MHz.
+} nrf_i2s_mck_t;
+
+/**
+ * @brief I2S MCK/LRCK ratios.
+ */
+typedef enum
+{
+    NRF_I2S_RATIO_32X  = I2S_CONFIG_RATIO_RATIO_32X,  ///< LRCK = MCK / 32.
+    NRF_I2S_RATIO_48X  = I2S_CONFIG_RATIO_RATIO_48X,  ///< LRCK = MCK / 48.
+    NRF_I2S_RATIO_64X  = I2S_CONFIG_RATIO_RATIO_64X,  ///< LRCK = MCK / 64.
+    NRF_I2S_RATIO_96X  = I2S_CONFIG_RATIO_RATIO_96X,  ///< LRCK = MCK / 96.
+    NRF_I2S_RATIO_128X = I2S_CONFIG_RATIO_RATIO_128X, ///< LRCK = MCK / 128.
+    NRF_I2S_RATIO_192X = I2S_CONFIG_RATIO_RATIO_192X, ///< LRCK = MCK / 192.
+    NRF_I2S_RATIO_256X = I2S_CONFIG_RATIO_RATIO_256X, ///< LRCK = MCK / 256.
+    NRF_I2S_RATIO_384X = I2S_CONFIG_RATIO_RATIO_384X, ///< LRCK = MCK / 384.
+    NRF_I2S_RATIO_512X = I2S_CONFIG_RATIO_RATIO_512X  ///< LRCK = MCK / 512.
+} nrf_i2s_ratio_t;
+
+/**
+ * @brief I2S sample widths.
+ */
+typedef enum
+{
+    NRF_I2S_SWIDTH_8BIT  = I2S_CONFIG_SWIDTH_SWIDTH_8Bit,  ///< 8 bit.
+    NRF_I2S_SWIDTH_16BIT = I2S_CONFIG_SWIDTH_SWIDTH_16Bit, ///< 16 bit.
+    NRF_I2S_SWIDTH_24BIT = I2S_CONFIG_SWIDTH_SWIDTH_24Bit  ///< 24 bit.
+} nrf_i2s_swidth_t;
+
+/**
+ * @brief I2S alignments of sample within a frame.
+ */
+typedef enum
+{
+    NRF_I2S_ALIGN_LEFT  = I2S_CONFIG_ALIGN_ALIGN_Left, ///< Left-aligned.
+    NRF_I2S_ALIGN_RIGHT = I2S_CONFIG_ALIGN_ALIGN_Right ///< Right-aligned.
+} nrf_i2s_align_t;
+
+/**
+ * @brief I2S frame formats.
+ */
+typedef enum
+{
+    NRF_I2S_FORMAT_I2S     = I2S_CONFIG_FORMAT_FORMAT_I2S,    ///< Original I2S format.
+    NRF_I2S_FORMAT_ALIGNED = I2S_CONFIG_FORMAT_FORMAT_Aligned ///< Alternate (left- or right-aligned) format.
+} nrf_i2s_format_t;
+
+/**
+ * @brief I2S enabled channels.
+ */
+typedef enum
+{
+    NRF_I2S_CHANNELS_STEREO = I2S_CONFIG_CHANNELS_CHANNELS_Stereo, ///< Stereo.
+    NRF_I2S_CHANNELS_LEFT   = I2S_CONFIG_CHANNELS_CHANNELS_Left,   ///< Left only.
+    NRF_I2S_CHANNELS_RIGHT  = I2S_CONFIG_CHANNELS_CHANNELS_Right   ///< Right only.
+} nrf_i2s_channels_t;
+
+
+/**
+ * @brief Function for activating a specific I2S task.
+ *
+ * @param[in] p_i2s I2S instance.
+ * @param[in] task  Task to activate.
+ */
+__STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_i2s,
+                                          nrf_i2s_task_t task);
+
+/**
+ * @brief Function for getting the address of a specific I2S task register.
+ *
+ * @param[in] p_i2s I2S instance.
+ * @param[in] task  Requested task.
+ *
+ * @return Address of the specified task register.
+ */
+__STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_i2s,
+                                                  nrf_i2s_task_t task);
+
+/**
+ * @brief Function for clearing a specific I2S event.
+ *
+ * @param[in] p_i2s I2S instance.
+ * @param[in] event Event to clear.
+ */
+__STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_i2s,
+                                         nrf_i2s_event_t event);
+
+/**
+ * @brief Function for checking the state of a specific I2S event.
+ *
+ * @param[in] p_i2s I2S instance.
+ * @param[in] event Event to check.
+ *
+ * @retval true  If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_i2s,
+                                         nrf_i2s_event_t event);
+
+/**
+ * @brief Function for getting the address of a specific I2S event register.
+ *
+ * @param[in] p_i2s I2S instance.
+ * @param[in] event Requested event.
+ *
+ * @return Address of the specified event register.
+ */
+__STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_i2s,
+                                                   nrf_i2s_event_t event);
+
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] p_i2s I2S instance.
+ * @param[in] mask  Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_i2s, uint32_t mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] p_i2s I2S instance.
+ * @param[in] mask  Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_i2s, uint32_t mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param[in] p_i2s   I2S instance.
+ * @param[in] i2s_int Interrupt to check.
+ *
+ * @retval true  If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_i2s_int_enable_check(NRF_I2S_Type const * p_i2s,
+                                              nrf_i2s_int_mask_t i2s_int);
+
+/**
+ * @brief Function for enabling the I2S peripheral.
+ *
+ * @param[in] p_i2s I2S instance.
+ */
+__STATIC_INLINE void nrf_i2s_enable(NRF_I2S_Type * p_i2s);
+
+/**
+ * @brief Function for disabling the I2S peripheral.
+ *
+ * @param[in] p_i2s I2S instance.
+ */
+__STATIC_INLINE void nrf_i2s_disable(NRF_I2S_Type * p_i2s);
+
+/**
+ * @brief Function for configuring I2S pins.
+ *
+ * Usage of the SDOUT, SDIN, and MCK signals is optional.
+ * If a given signal is not needed, pass the @ref NRF_I2S_PIN_NOT_CONNECTED
+ * value instead of its pin number.
+ *
+ * @param[in] p_i2s     I2S instance.
+ * @param[in] sck_pin   SCK pin number.
+ * @param[in] lrck_pin  LRCK pin number.
+ * @param[in] mck_pin   MCK pin number.
+ * @param[in] sdout_pin SDOUT pin number.
+ * @param[in] sdin_pin  SDIN pin number.
+ */
+__STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_i2s,
+                                      uint32_t sck_pin,
+                                      uint32_t lrck_pin,
+                                      uint32_t mck_pin,
+                                      uint32_t sdout_pin,
+                                      uint32_t sdin_pin);
+
+/**
+ * @brief Function for setting the I2S peripheral configuration.
+ *
+ * @param[in] p_i2s        I2S instance.
+ * @param[in] mode         Mode of operation (master or slave).
+ * @param[in] format       I2S frame format.
+ * @param[in] alignment    Alignment of sample within a frame.
+ * @param[in] sample_width Sample width.
+ * @param[in] channels     Enabled channels.
+ * @param[in] mck_setup    Master clock generator setup.
+ * @param[in] ratio        MCK/LRCK ratio.
+ *
+ * @retval true  If the configuration has been set successfully.
+ * @retval false If the requested configuration is not allowed.
+ */
+__STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_i2s,
+                                       nrf_i2s_mode_t     mode,
+                                       nrf_i2s_format_t   format,
+                                       nrf_i2s_align_t    alignment,
+                                       nrf_i2s_swidth_t   sample_width,
+                                       nrf_i2s_channels_t channels,
+                                       nrf_i2s_mck_t      mck_setup,
+                                       nrf_i2s_ratio_t    ratio);
+
+/**
+ * @brief Function for setting up the I2S transfer.
+ *
+ * This function sets up the RX and TX buffers and enables reception and/or
+ * transmission accordingly. If the transfer in a given direction is not
+ * required, pass NULL instead of the pointer to the corresponding buffer.
+ *
+ * @param[in] p_i2s       I2S instance.
+ * @param[in] size        Size of the buffers (in 32-bit words).
+ * @param[in] p_rx_buffer Pointer to the receive buffer.
+ *                        Pass NULL to disable reception.
+ * @param[in] p_tx_buffer Pointer to the transmit buffer.
+ *                        Pass NULL to disable transmission.
+ */
+__STATIC_INLINE void nrf_i2s_transfer_set(NRF_I2S_Type * p_i2s,
+                                          uint16_t         size,
+                                          uint32_t *       p_rx_buffer,
+                                          uint32_t const * p_tx_buffer);
+
+/**
+ * @brief Function for setting the pointer to the receive buffer.
+ *
+ * @note The size of the buffer can be set only by calling
+ *       @ref nrf_i2s_transfer_set.
+ *
+ * @param[in] p_i2s    I2S instance.
+ * @param[in] p_buffer Pointer to the receive buffer.
+ */
+__STATIC_INLINE void nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_i2s,
+                                           uint32_t * p_buffer);
+
+/**
+ * @brief Function for getting the pointer to the receive buffer.
+ *
+ * @param[in] p_i2s I2S instance.
+ *
+ * @return Pointer to the receive buffer.
+ */
+__STATIC_INLINE uint32_t * nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_i2s);
+
+/**
+ * @brief Function for setting the pointer to the transmit buffer.
+ *
+ * @note The size of the buffer can be set only by calling
+ *       @ref nrf_i2s_transfer_set.
+ *
+ * @param[in] p_i2s    I2S instance.
+ * @param[in] p_buffer Pointer to the transmit buffer.
+ */
+__STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_i2s,
+                                           uint32_t const * p_buffer);
+
+/**
+ * @brief Function for getting the pointer to the transmit buffer.
+ *
+ * @param[in] p_i2s I2S instance.
+ *
+ * @return Pointer to the transmit buffer.
+ */
+__STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_i2s);
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_i2s,
+                                          nrf_i2s_task_t task)
+{
+    *((volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)task)) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_i2s,
+                                                  nrf_i2s_task_t task)
+{
+    return ((uint32_t)p_i2s + (uint32_t)task);
+}
+
+__STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_i2s,
+                                         nrf_i2s_event_t event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)event)) = 0x0UL;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)event));
+    (void)dummy;
+#endif
+}
+
+__STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_i2s,
+                                         nrf_i2s_event_t event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)p_i2s + (uint32_t)event);
+}
+
+__STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_i2s,
+                                                   nrf_i2s_event_t event)
+{
+    return ((uint32_t)p_i2s + (uint32_t)event);
+}
+
+__STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_i2s, uint32_t mask)
+{
+    p_i2s->INTENSET = mask;
+}
+
+__STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_i2s, uint32_t mask)
+{
+    p_i2s->INTENCLR = mask;
+}
+
+__STATIC_INLINE bool nrf_i2s_int_enable_check(NRF_I2S_Type const * p_i2s,
+                                              nrf_i2s_int_mask_t i2s_int)
+{
+    return (bool)(p_i2s->INTENSET & i2s_int);
+}
+
+__STATIC_INLINE void nrf_i2s_enable(NRF_I2S_Type * p_i2s)
+{
+    p_i2s->ENABLE = (I2S_ENABLE_ENABLE_Enabled << I2S_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_i2s_disable(NRF_I2S_Type * p_i2s)
+{
+    p_i2s->ENABLE = (I2S_ENABLE_ENABLE_Disabled << I2S_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_i2s,
+                                      uint32_t sck_pin,
+                                      uint32_t lrck_pin,
+                                      uint32_t mck_pin,
+                                      uint32_t sdout_pin,
+                                      uint32_t sdin_pin)
+{
+    p_i2s->PSEL.SCK   = sck_pin;
+    p_i2s->PSEL.LRCK  = lrck_pin;
+    p_i2s->PSEL.MCK   = mck_pin;
+    p_i2s->PSEL.SDOUT = sdout_pin;
+    p_i2s->PSEL.SDIN  = sdin_pin;
+}
+
+__STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_i2s,
+                                       nrf_i2s_mode_t     mode,
+                                       nrf_i2s_format_t   format,
+                                       nrf_i2s_align_t    alignment,
+                                       nrf_i2s_swidth_t   sample_width,
+                                       nrf_i2s_channels_t channels,
+                                       nrf_i2s_mck_t      mck_setup,
+                                       nrf_i2s_ratio_t    ratio)
+{
+    if (mode == NRF_I2S_MODE_MASTER)
+    {
+        // The MCK/LRCK ratio shall be a multiple of 2 * sample width.
+        if (((sample_width == NRF_I2S_SWIDTH_16BIT) &&
+                 (ratio == NRF_I2S_RATIO_48X))
+            ||
+            ((sample_width == NRF_I2S_SWIDTH_24BIT) &&
+                ((ratio == NRF_I2S_RATIO_32X)  ||
+                 (ratio == NRF_I2S_RATIO_64X)  ||
+                 (ratio == NRF_I2S_RATIO_128X) ||
+                 (ratio == NRF_I2S_RATIO_256X) ||
+                 (ratio == NRF_I2S_RATIO_512X))))
+        {
+            return false;
+        }
+    }
+
+    p_i2s->CONFIG.MODE     = mode;
+    p_i2s->CONFIG.FORMAT   = format;
+    p_i2s->CONFIG.ALIGN    = alignment;
+    p_i2s->CONFIG.SWIDTH   = sample_width;
+    p_i2s->CONFIG.CHANNELS = channels;
+    p_i2s->CONFIG.RATIO    = ratio;
+
+    if (mck_setup == NRF_I2S_MCK_DISABLED)
+    {
+        p_i2s->CONFIG.MCKEN =
+            (I2S_CONFIG_MCKEN_MCKEN_Disabled << I2S_CONFIG_MCKEN_MCKEN_Pos);
+    }
+    else
+    {
+        p_i2s->CONFIG.MCKFREQ = mck_setup;
+        p_i2s->CONFIG.MCKEN =
+            (I2S_CONFIG_MCKEN_MCKEN_Enabled << I2S_CONFIG_MCKEN_MCKEN_Pos);
+    }
+
+    return true;
+}
+
+__STATIC_INLINE void nrf_i2s_transfer_set(NRF_I2S_Type * p_i2s,
+                                          uint16_t         size,
+                                          uint32_t *       p_buffer_rx,
+                                          uint32_t const * p_buffer_tx)
+{
+    p_i2s->RXTXD.MAXCNT = size;
+
+    nrf_i2s_rx_buffer_set(p_i2s, p_buffer_rx);
+    p_i2s->CONFIG.RXEN = (p_buffer_rx != NULL) ? 1 : 0;
+
+    nrf_i2s_tx_buffer_set(p_i2s, p_buffer_tx);
+    p_i2s->CONFIG.TXEN = (p_buffer_tx != NULL) ? 1 : 0;
+}
+
+__STATIC_INLINE void nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_i2s,
+                                           uint32_t * p_buffer)
+{
+    p_i2s->RXD.PTR = (uint32_t)p_buffer;
+}
+
+__STATIC_INLINE uint32_t * nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_i2s)
+{
+    return (uint32_t *)(p_i2s->RXD.PTR);
+}
+
+__STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_i2s,
+                                           uint32_t const * p_buffer)
+{
+    p_i2s->TXD.PTR = (uint32_t)p_buffer;
+}
+
+__STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_i2s)
+{
+    return (uint32_t *)(p_i2s->TXD.PTR);
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_I2S_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_lpcomp.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,424 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @file
+ * @brief LPCOMP HAL API.
+ */
+
+#ifndef NRF_LPCOMP_H_
+#define NRF_LPCOMP_H_
+
+/**
+ * @defgroup nrf_lpcomp_hal LPCOMP HAL
+ * @{
+ * @ingroup nrf_lpcomp
+ * @brief Hardware access layer for managing the Low Power Comparator (LPCOMP).
+ */
+
+#include "nrf.h"
+#include "nrf_peripherals.h"
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @enum nrf_lpcomp_ref_t
+ * @brief LPCOMP reference selection.
+ */
+typedef enum
+{
+#if (LPCOMP_REFSEL_RESOLUTION == 8) || defined(__SDK_DOXYGEN__)
+    NRF_LPCOMP_REF_SUPPLY_1_8   = LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling,    /**< Use supply with a 1/8 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_2_8   = LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling,   /**< Use supply with a 2/8 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_3_8   = LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling, /**< Use supply with a 3/8 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_4_8   = LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling,  /**< Use supply with a 4/8 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_5_8   = LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling,  /**< Use supply with a 5/8 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_6_8   = LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling,   /**< Use supply with a 6/8 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_7_8   = LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling, /**< Use supply with a 7/8 prescaler as reference. */
+#elif (LPCOMP_REFSEL_RESOLUTION == 16) || defined(__SDK_DOXYGEN__)
+    NRF_LPCOMP_REF_SUPPLY_1_8   = LPCOMP_REFSEL_REFSEL_Ref1_8Vdd, /**< Use supply with a 1/8 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_2_8   = LPCOMP_REFSEL_REFSEL_Ref2_8Vdd, /**< Use supply with a 2/8 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_3_8   = LPCOMP_REFSEL_REFSEL_Ref3_8Vdd, /**< Use supply with a 3/8 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_4_8   = LPCOMP_REFSEL_REFSEL_Ref4_8Vdd, /**< Use supply with a 4/8 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_5_8   = LPCOMP_REFSEL_REFSEL_Ref5_8Vdd, /**< Use supply with a 5/8 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_6_8   = LPCOMP_REFSEL_REFSEL_Ref6_8Vdd, /**< Use supply with a 6/8 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_7_8   = LPCOMP_REFSEL_REFSEL_Ref7_8Vdd, /**< Use supply with a 7/8 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_1_16  = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 1/16 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_3_16  = LPCOMP_REFSEL_REFSEL_Ref3_16Vdd, /**< Use supply with a 3/16 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_5_16  = LPCOMP_REFSEL_REFSEL_Ref5_16Vdd, /**< Use supply with a 5/16 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_7_16  = LPCOMP_REFSEL_REFSEL_Ref7_16Vdd, /**< Use supply with a 7/16 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_9_16  = LPCOMP_REFSEL_REFSEL_Ref9_16Vdd, /**< Use supply with a 9/16 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_11_16 = LPCOMP_REFSEL_REFSEL_Ref11_16Vdd, /**< Use supply with a 11/16 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_13_16 = LPCOMP_REFSEL_REFSEL_Ref13_16Vdd, /**< Use supply with a 13/16 prescaler as reference. */
+    NRF_LPCOMP_REF_SUPPLY_15_16 = LPCOMP_REFSEL_REFSEL_Ref15_16Vdd, /**< Use supply with a 15/16 prescaler as reference. */
+#endif
+    NRF_LPCOMP_REF_EXT_REF0        = LPCOMP_REFSEL_REFSEL_ARef |
+                       (LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 << 16), /**< External reference 0. */
+    NRF_LPCOMP_CONFIG_REF_EXT_REF1 = LPCOMP_REFSEL_REFSEL_ARef |
+                        (LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 << 16), /**< External reference 1. */
+} nrf_lpcomp_ref_t;
+
+/**
+ * @enum nrf_lpcomp_input_t
+ * @brief LPCOMP input selection.
+ */
+typedef enum
+{
+    NRF_LPCOMP_INPUT_0 = LPCOMP_PSEL_PSEL_AnalogInput0, /**< Input 0. */
+    NRF_LPCOMP_INPUT_1 = LPCOMP_PSEL_PSEL_AnalogInput1, /**< Input 1. */
+    NRF_LPCOMP_INPUT_2 = LPCOMP_PSEL_PSEL_AnalogInput2, /**< Input 2. */
+    NRF_LPCOMP_INPUT_3 = LPCOMP_PSEL_PSEL_AnalogInput3, /**< Input 3. */
+    NRF_LPCOMP_INPUT_4 = LPCOMP_PSEL_PSEL_AnalogInput4, /**< Input 4. */
+    NRF_LPCOMP_INPUT_5 = LPCOMP_PSEL_PSEL_AnalogInput5, /**< Input 5. */
+    NRF_LPCOMP_INPUT_6 = LPCOMP_PSEL_PSEL_AnalogInput6, /**< Input 6. */
+    NRF_LPCOMP_INPUT_7 = LPCOMP_PSEL_PSEL_AnalogInput7  /**< Input 7. */
+} nrf_lpcomp_input_t;
+
+/**
+ * @enum nrf_lpcomp_detect_t
+ * @brief LPCOMP detection type selection.
+ */
+typedef enum
+{
+    NRF_LPCOMP_DETECT_CROSS = LPCOMP_ANADETECT_ANADETECT_Cross, /**< Generate ANADETEC on crossing, both upwards and downwards crossing. */
+    NRF_LPCOMP_DETECT_UP    = LPCOMP_ANADETECT_ANADETECT_Up,    /**< Generate ANADETEC on upwards crossing only. */
+    NRF_LPCOMP_DETECT_DOWN  = LPCOMP_ANADETECT_ANADETECT_Down   /**< Generate ANADETEC on downwards crossing only. */
+} nrf_lpcomp_detect_t;
+
+/**
+ * @enum nrf_lpcomp_task_t
+ * @brief LPCOMP tasks.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_LPCOMP_TASK_START  = offsetof(NRF_LPCOMP_Type, TASKS_START), /**< LPCOMP start sampling task. */
+    NRF_LPCOMP_TASK_STOP   = offsetof(NRF_LPCOMP_Type, TASKS_STOP),  /**< LPCOMP stop sampling task. */
+    NRF_LPCOMP_TASK_SAMPLE = offsetof(NRF_LPCOMP_Type, TASKS_SAMPLE) /**< Sample comparator value. */
+} nrf_lpcomp_task_t;                                                 /*lint -restore*/
+
+
+/**
+ * @enum nrf_lpcomp_event_t
+ * @brief LPCOMP events.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_LPCOMP_EVENT_READY = offsetof(NRF_LPCOMP_Type, EVENTS_READY), /**< LPCOMP is ready and output is valid. */
+    NRF_LPCOMP_EVENT_DOWN  = offsetof(NRF_LPCOMP_Type, EVENTS_DOWN),  /**< Input voltage crossed the threshold going down. */
+    NRF_LPCOMP_EVENT_UP    = offsetof(NRF_LPCOMP_Type, EVENTS_UP),    /**< Input voltage crossed the threshold going up. */
+    NRF_LPCOMP_EVENT_CROSS = offsetof(NRF_LPCOMP_Type, EVENTS_CROSS)  /**< Input voltage crossed the threshold in any direction. */
+} nrf_lpcomp_event_t;                                                 /*lint -restore*/
+
+/**
+ * @enum nrf_lpcomp_short_mask_t
+ * @brief LPCOMP shorts masks.
+ */
+typedef enum
+{
+    NRF_LPCOMP_SHORT_CROSS_STOP_MASK   = LPCOMP_SHORTS_CROSS_STOP_Msk,  /*!< Short between CROSS event and STOP task. */
+    NRF_LPCOMP_SHORT_UP_STOP_MASK      = LPCOMP_SHORTS_UP_STOP_Msk,     /*!< Short between UP event and STOP task. */
+    NRF_LPCOMP_SHORT_DOWN_STOP_MASK    = LPCOMP_SHORTS_DOWN_STOP_Msk,   /*!< Short between DOWN event and STOP task. */
+    NRF_LPCOMP_SHORT_READY_STOP_MASK   = LPCOMP_SHORTS_READY_STOP_Msk,  /*!< Short between READY event and STOP task. */
+    NRF_LPCOMP_SHORT_READY_SAMPLE_MASK = LPCOMP_SHORTS_READY_SAMPLE_Msk /*!< Short between READY event and SAMPLE task. */
+} nrf_lpcomp_short_mask_t;
+
+#ifdef NRF52_SERIES
+/**
+ * @enum nrf_lpcomp_hysteresis_t
+ * @brief LPCOMP hysteresis.
+ */
+typedef enum
+{
+    NRF_LPCOMP_HYST_NOHYST              = LPCOMP_HYST_HYST_NoHyst,      /**< Comparator hysteresis disabled. */
+    NRF_LPCOMP_HYST_50mV                = LPCOMP_HYST_HYST_Hyst50mV     /**< Comparator hysteresis enabled (typ. 50 mV). */
+}nrf_lpcomp_hysteresis_t;
+#endif // NRF52
+
+/** @brief LPCOMP configuration. */
+typedef struct
+{
+    nrf_lpcomp_ref_t            reference; /**< LPCOMP reference. */
+    nrf_lpcomp_detect_t         detection; /**< LPCOMP detection type. */
+#ifdef NRF52_SERIES
+    nrf_lpcomp_hysteresis_t     hyst;      /**< LPCOMP hysteresis. */
+#endif // NRF52
+} nrf_lpcomp_config_t;
+
+/** Default LPCOMP configuration. */
+#define NRF_LPCOMP_CONFIG_DEFAULT { NRF_LPCOMP_REF_SUPPLY_FOUR_EIGHT, NRF_LPCOMP_DETECT_DOWN }
+
+/**
+ * @brief Function for configuring LPCOMP.
+ *
+ * This function powers on LPCOMP and configures it. LPCOMP is in DISABLE state after configuration,
+ * so it must be enabled before using it. All shorts are inactive, events are cleared, and LPCOMP is stopped.
+ *
+ * @param[in] p_config Configuration.
+ */
+__STATIC_INLINE void nrf_lpcomp_configure(const nrf_lpcomp_config_t * p_config)
+{
+    NRF_LPCOMP->TASKS_STOP = 1;
+    NRF_LPCOMP->ENABLE     = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos;
+    NRF_LPCOMP->REFSEL     =
+        (p_config->reference << LPCOMP_REFSEL_REFSEL_Pos) & LPCOMP_REFSEL_REFSEL_Msk;
+
+    //If external source is choosen extract analog reference index.
+    if ((p_config->reference & LPCOMP_REFSEL_REFSEL_ARef)==LPCOMP_REFSEL_REFSEL_ARef)
+    {
+        uint32_t extref       = p_config->reference >> 16;
+        NRF_LPCOMP->EXTREFSEL = (extref << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) & LPCOMP_EXTREFSEL_EXTREFSEL_Msk;
+    }
+
+    NRF_LPCOMP->ANADETECT   =
+        (p_config->detection << LPCOMP_ANADETECT_ANADETECT_Pos) & LPCOMP_ANADETECT_ANADETECT_Msk;
+#ifdef NRF52_SERIES
+    NRF_LPCOMP->HYST        = ((p_config->hyst) << LPCOMP_HYST_HYST_Pos) & LPCOMP_HYST_HYST_Msk;
+#endif
+    NRF_LPCOMP->SHORTS      = 0;
+    NRF_LPCOMP->INTENCLR    = LPCOMP_INTENCLR_CROSS_Msk | LPCOMP_INTENCLR_UP_Msk |
+                               LPCOMP_INTENCLR_DOWN_Msk | LPCOMP_INTENCLR_READY_Msk;
+}
+
+
+/**
+ * @brief Function for selecting the LPCOMP input.
+ *
+ * This function selects the active input of LPCOMP.
+ *
+ * @param[in] input Input to be selected.
+ */
+__STATIC_INLINE void nrf_lpcomp_input_select(nrf_lpcomp_input_t input)
+{
+    uint32_t lpcomp_enable_state = NRF_LPCOMP->ENABLE;
+
+    NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos;
+    NRF_LPCOMP->PSEL   =
+        ((uint32_t)input << LPCOMP_PSEL_PSEL_Pos) | (NRF_LPCOMP->PSEL & ~LPCOMP_PSEL_PSEL_Msk);
+    NRF_LPCOMP->ENABLE = lpcomp_enable_state;
+}
+
+
+/**
+ * @brief Function for enabling the Low Power Comparator.
+ *
+ * This function enables LPCOMP.
+ *
+ */
+__STATIC_INLINE void nrf_lpcomp_enable(void)
+{
+    NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Enabled << LPCOMP_ENABLE_ENABLE_Pos;
+    NRF_LPCOMP->EVENTS_READY = 0;
+    NRF_LPCOMP->EVENTS_DOWN  = 0;
+    NRF_LPCOMP->EVENTS_UP    = 0;
+    NRF_LPCOMP->EVENTS_CROSS = 0;
+}
+
+
+/**
+ * @brief Function for disabling the Low Power Comparator.
+ *
+ * This function disables LPCOMP.
+ *
+ */
+__STATIC_INLINE void nrf_lpcomp_disable(void)
+{
+    NRF_LPCOMP->ENABLE     = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos;
+}
+
+
+/**
+ * @brief Function for getting the last LPCOMP compare result.
+ *
+ * @return The last compare result. If 0 then VIN+ < VIN-, if 1 then the opposite.
+ */
+__STATIC_INLINE uint32_t nrf_lpcomp_result_get(void)
+{
+    return (uint32_t)NRF_LPCOMP->RESULT;
+}
+
+
+/**
+ * @brief Function for enabling interrupts from LPCOMP.
+ *
+ * @param[in] lpcomp_int_mask Mask of interrupts to be enabled.
+ *
+ * @sa nrf_lpcomp_int_disable()
+ * @sa nrf_lpcomp_int_enable_check()
+ */
+__STATIC_INLINE void nrf_lpcomp_int_enable(uint32_t lpcomp_int_mask)
+{
+    NRF_LPCOMP->INTENSET = lpcomp_int_mask;
+}
+
+
+/**
+ * @brief Function for disabling interrupts from LPCOMP.
+ *
+ * @param[in] lpcomp_int_mask Mask of interrupts to be disabled.
+ *
+ * @sa nrf_lpcomp_int_enable()
+ * @sa nrf_lpcomp_int_enable_check()
+ */
+__STATIC_INLINE void nrf_lpcomp_int_disable(uint32_t lpcomp_int_mask)
+{
+    NRF_LPCOMP->INTENCLR = lpcomp_int_mask;
+}
+
+
+/**
+ * @brief Function for getting the enabled interrupts of LPCOMP.
+ *
+ * @param[in] lpcomp_int_mask Mask of interrupts to be checked.
+ *
+ * @retval true If any of interrupts of the specified mask are enabled.
+ *
+ * @sa nrf_lpcomp_int_enable()
+ * @sa nrf_lpcomp_int_disable()
+ */
+__STATIC_INLINE bool nrf_lpcomp_int_enable_check(uint32_t lpcomp_int_mask)
+{
+    return (NRF_LPCOMP->INTENSET & lpcomp_int_mask); // when read this register will return the value of INTEN.
+}
+
+
+/**
+ * @brief Function for getting the address of a specific LPCOMP task register.
+ *
+ * @param[in] lpcomp_task LPCOMP task.
+ *
+ * @return The address of the specified LPCOMP task.
+ */
+__STATIC_INLINE uint32_t * nrf_lpcomp_task_address_get(nrf_lpcomp_task_t lpcomp_task)
+{
+    return (uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_task);
+}
+
+
+/**
+ * @brief Function for getting the address of a specific LPCOMP event register.
+ *
+ * @param[in] lpcomp_event LPCOMP event.
+ *
+ * @return The address of the specified LPCOMP event.
+ */
+__STATIC_INLINE uint32_t * nrf_lpcomp_event_address_get(nrf_lpcomp_event_t lpcomp_event)
+{
+    return (uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_event);
+}
+
+
+/**
+ * @brief  Function for setting LPCOMP shorts.
+ *
+ * @param[in] lpcomp_short_mask LPCOMP shorts by mask.
+ *
+ */
+__STATIC_INLINE void nrf_lpcomp_shorts_enable(uint32_t lpcomp_short_mask)
+{
+    NRF_LPCOMP->SHORTS |= lpcomp_short_mask;
+}
+
+
+/**
+ * @brief Function for clearing LPCOMP shorts by mask.
+ *
+ * @param[in] lpcomp_short_mask LPCOMP shorts to be cleared.
+ *
+ */
+__STATIC_INLINE void nrf_lpcomp_shorts_disable(uint32_t lpcomp_short_mask)
+{
+    NRF_LPCOMP->SHORTS &= ~lpcomp_short_mask;
+}
+
+
+/**
+ * @brief Function for setting a specific LPCOMP task.
+ *
+ * @param[in] lpcomp_task LPCOMP task to be set.
+ *
+ */
+__STATIC_INLINE void nrf_lpcomp_task_trigger(nrf_lpcomp_task_t lpcomp_task)
+{
+    *( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_task) ) = 1;
+}
+
+
+/**
+ * @brief Function for clearing a specific LPCOMP event.
+ *
+ * @param[in] lpcomp_event LPCOMP event to be cleared.
+ *
+ */
+__STATIC_INLINE void nrf_lpcomp_event_clear(nrf_lpcomp_event_t lpcomp_event)
+{
+    *( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_event) ) = 0;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_event));
+    (void)dummy;
+#endif
+}
+
+
+/**
+ * @brief Function for getting the state of a specific LPCOMP event.
+ *
+ * @retval true If the specified LPCOMP event is active.
+ *
+ */
+__STATIC_INLINE bool nrf_lpcomp_event_check(nrf_lpcomp_event_t lpcomp_event)
+{
+    return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_event));
+}
+
+
+/**
+ *@}
+ **/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF_LPCOMP_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_nvmc.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,142 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ *@file
+ *@brief NMVC driver implementation
+ */
+
+#include <stdbool.h>
+#include "nrf.h"
+#include "nrf_nvmc.h"
+
+
+void nrf_nvmc_page_erase(uint32_t address)
+{
+    // Enable erase.
+    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een;
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+    }
+
+    // Erase the page
+    NRF_NVMC->ERASEPAGE = address;
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+    }
+
+    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+    }
+}
+
+
+void nrf_nvmc_write_byte(uint32_t address, uint8_t value)
+{
+    uint32_t byte_shift = address & (uint32_t)0x03;
+    uint32_t address32 = address & ~byte_shift; // Address to the word this byte is in.
+    uint32_t value32 = (*(uint32_t*)address32 & ~((uint32_t)0xFF << (byte_shift << (uint32_t)3)));
+    value32 = value32 + ((uint32_t)value << (byte_shift << 3));
+
+    // Enable write.
+    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos);
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+    }
+
+    *(uint32_t*)address32 = value32;
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+    }
+
+    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos);
+    {
+    }
+}
+
+void nrf_nvmc_write_word(uint32_t address, uint32_t value)
+{
+    // Enable write.
+    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){
+    }
+
+    *(uint32_t*)address = value;
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){
+    }
+
+    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+    }
+}
+
+void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes)
+{
+    uint32_t i;
+    for (i=0;i<num_bytes;i++)
+    {
+       nrf_nvmc_write_byte(address + i,src[i]);
+    }
+}
+
+void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words)
+{
+    uint32_t i;
+
+    // Enable write.
+    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+    }
+
+    for (i=0;i<num_words;i++)
+    {
+        ((uint32_t*)address)[i] = src[i];
+        while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+        {
+        }
+    }
+
+    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+    }
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_nvmc.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,124 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @file
+ * @brief NMVC driver API.
+ */
+
+#ifndef NRF_NVMC_H__
+#define NRF_NVMC_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @defgroup nrf_nvmc Non-volatile memory controller
+ * @{
+ * @ingroup nrf_drivers
+ * @brief Driver for the NVMC peripheral.
+ *
+ * This driver allows writing to the non-volatile memory (NVM) regions
+ * of the chip. In order to write to NVM the controller must be powered
+ * on and the relevant page must be erased.
+ *
+ */
+
+
+/**
+ * @brief Erase a page in flash. This is required before writing to any
+ * address in the page.
+ *
+ * @param address Start address of the page.
+ */
+void nrf_nvmc_page_erase(uint32_t address);
+
+
+/**
+ * @brief Write a single byte to flash.
+ *
+ * The function reads the word containing the byte, and then
+ * rewrites the entire word.
+ *
+ * @param address Address to write to.
+ * @param value   Value to write.
+ */
+void nrf_nvmc_write_byte(uint32_t address , uint8_t value);
+
+
+/**
+ * @brief Write a 32-bit word to flash.
+ * @param address Address to write to.
+ * @param value   Value to write.
+ */
+void nrf_nvmc_write_word(uint32_t address, uint32_t value);
+
+
+/**
+ * @brief Write consecutive bytes to flash.
+ *
+ * @param address   Address to write to.
+ * @param src       Pointer to data to copy from.
+ * @param num_bytes Number of bytes in src to write.
+ */
+void nrf_nvmc_write_bytes(uint32_t  address, const uint8_t * src, uint32_t num_bytes);
+
+
+/**
+ * @brief Write consecutive words to flash.
+ *
+ * @param address   Address to write to.
+ * @param src       Pointer to data to copy from.
+ * @param num_words Number of bytes in src to write.
+ */
+void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_NVMC_H__
+/** @} */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_pdm.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,396 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_PDM_H_
+#define NRF_PDM_H_
+
+/**
+ * @defgroup nrf_pdm_hal PDM HAL
+ * @{
+ * @ingroup nrf_pdm
+ *
+ * @brief @tagAPI52 Hardware abstraction layer for accessing the pulse density modulation (PDM) peripheral.
+ */
+
+#include <stdbool.h>
+#include <stddef.h>
+#include "nrf.h"
+#include "nrf_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define NRF_PDM_GAIN_MINIMUM  0x00
+#define NRF_PDM_GAIN_DEFAULT  0x28
+#define NRF_PDM_GAIN_MAXIMUM  0x50
+
+typedef uint8_t nrf_pdm_gain_t;
+
+
+/**
+ * @brief PDM tasks.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_PDM_TASK_START           = offsetof(NRF_PDM_Type, TASKS_START),           ///< Starts continuous PDM transfer.
+    NRF_PDM_TASK_STOP            = offsetof(NRF_PDM_Type, TASKS_STOP)             ///< Stops PDM transfer.
+} nrf_pdm_task_t;
+
+
+/**
+ * @brief PDM events.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_PDM_EVENT_STARTED       = offsetof(NRF_PDM_Type, EVENTS_STARTED),       ///< PDM transfer has started.
+    NRF_PDM_EVENT_STOPPED       = offsetof(NRF_PDM_Type, EVENTS_STOPPED),       ///< PDM transfer has finished.
+    NRF_PDM_EVENT_END           = offsetof(NRF_PDM_Type, EVENTS_END)            ///< The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM.
+} nrf_pdm_event_t;
+
+
+/**
+ * @brief PDM interrupt masks.
+ */
+typedef enum
+{
+    NRF_PDM_INT_STARTED = PDM_INTENSET_STARTED_Msk,   ///< Interrupt on EVENTS_STARTED event.
+    NRF_PDM_INT_STOPPED = PDM_INTENSET_STOPPED_Msk,   ///< Interrupt on EVENTS_STOPPED event.
+    NRF_PDM_INT_END     = PDM_INTENSET_END_Msk        ///< Interrupt on EVENTS_END event.
+} nrf_pdm_int_mask_t;
+
+/**
+ * @brief PDM clock frequency.
+ */
+typedef enum
+{
+    NRF_PDM_FREQ_1000K = PDM_PDMCLKCTRL_FREQ_1000K,  ///< PDM_CLK = 1.000 MHz.
+    NRF_PDM_FREQ_1032K = PDM_PDMCLKCTRL_FREQ_Default,  ///< PDM_CLK = 1.032 MHz.
+    NRF_PDM_FREQ_1067K = PDM_PDMCLKCTRL_FREQ_1067K   ///< PDM_CLK = 1.067 MHz.
+} nrf_pdm_freq_t;
+
+
+/**
+ * @brief PDM operation mode.
+ */
+typedef enum
+{
+    NRF_PDM_MODE_STEREO = PDM_MODE_OPERATION_Stereo,  ///< Sample and store one pair (Left + Right) of 16-bit samples per RAM word.
+    NRF_PDM_MODE_MONO   = PDM_MODE_OPERATION_Mono     ///< Sample and store two successive Left samples (16 bit each) per RAM word.
+} nrf_pdm_mode_t;
+
+
+/**
+ * @brief PDM sampling mode.
+ */
+typedef enum
+{
+    NRF_PDM_EDGE_LEFTFALLING = PDM_MODE_EDGE_LeftFalling,  ///< Left (or mono) is sampled on falling edge of PDM_CLK.
+    NRF_PDM_EDGE_LEFTRISING  = PDM_MODE_EDGE_LeftRising    ///< Left (or mono) is sampled on rising edge of PDM_CLK.
+} nrf_pdm_edge_t;
+
+
+/**
+ * @brief Function for triggering a PDM task.
+ *
+ * @param[in] pdm_task PDM task.
+ */
+__STATIC_INLINE void nrf_pdm_task_trigger(nrf_pdm_task_t pdm_task)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_task)) = 0x1UL;
+}
+
+
+/**
+ * @brief Function for getting the address of a PDM task register.
+ *
+ * @param[in] pdm_task PDM task.
+ *
+ * @return Address of the specified PDM task.
+ */
+__STATIC_INLINE uint32_t nrf_pdm_task_address_get(nrf_pdm_task_t pdm_task)
+{
+    return (uint32_t)((uint8_t *)NRF_PDM + (uint32_t)pdm_task);
+}
+
+
+/**
+ * @brief Function for getting the state of a PDM event.
+ *
+ * @param[in] pdm_event PDM event.
+ *
+ * @return State of the specified PDM event.
+ */
+__STATIC_INLINE bool nrf_pdm_event_check(nrf_pdm_event_t pdm_event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event);
+}
+
+
+/**
+ * @brief Function for clearing a PDM event.
+ *
+ * @param[in] pdm_event PDM event.
+ */
+__STATIC_INLINE void nrf_pdm_event_clear(nrf_pdm_event_t pdm_event)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event)) = 0x0UL;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event));
+    (void)dummy;
+#endif
+}
+
+
+/**
+ * @brief Function for getting the address of a PDM event register.
+ *
+ * @param[in] pdm_event PDM event.
+ *
+ * @return Address of the specified PDM event.
+ */
+__STATIC_INLINE volatile uint32_t * nrf_pdm_event_address_get(nrf_pdm_event_t pdm_event)
+{
+    return (volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event);
+}
+
+
+/**
+ * @brief Function for enabling PDM interrupts.
+ *
+ * @param[in] pdm_int_mask Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_pdm_int_enable(uint32_t pdm_int_mask)
+{
+    NRF_PDM->INTENSET = pdm_int_mask;
+}
+
+
+/**
+ * @brief Function for retrieving the state of PDM interrupts.
+ *
+ * @param[in] pdm_int_mask Interrupts to check.
+ *
+ * @retval true  If all specified interrupts are enabled.
+ * @retval false If at least one of the given interrupts is not enabled.
+ */
+__STATIC_INLINE bool nrf_pdm_int_enable_check(uint32_t pdm_int_mask)
+{
+    return (bool)(NRF_PDM->INTENSET & pdm_int_mask);
+}
+
+
+/**
+ * @brief Function for disabling interrupts.
+ *
+ * @param pdm_int_mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_pdm_int_disable(uint32_t pdm_int_mask)
+{
+    NRF_PDM->INTENCLR = pdm_int_mask;
+}
+
+
+/**
+ * @brief Function for enabling the PDM peripheral.
+ *
+ * The PDM peripheral must be enabled before use.
+ */
+__STATIC_INLINE void nrf_pdm_enable(void)
+{
+    NRF_PDM->ENABLE = (PDM_ENABLE_ENABLE_Enabled << PDM_ENABLE_ENABLE_Pos);
+}
+
+
+/**
+ * @brief Function for disabling the PDM peripheral.
+ */
+__STATIC_INLINE void nrf_pdm_disable(void)
+{
+    NRF_PDM->ENABLE = (PDM_ENABLE_ENABLE_Disabled << PDM_ENABLE_ENABLE_Pos);
+}
+
+
+/**
+ * @brief Function for checking if the PDM peripheral is enabled.
+ *
+ * @retval true  If the PDM peripheral is enabled.
+ * @retval false If the PDM peripheral is not enabled.
+ */
+__STATIC_INLINE bool nrf_pdm_enable_check(void)
+{
+    return (NRF_PDM->ENABLE == (PDM_ENABLE_ENABLE_Enabled << PDM_ENABLE_ENABLE_Pos));
+}
+
+
+/**
+ * @brief Function for setting the PDM operation mode.
+ *
+ * @param[in] pdm_mode PDM operation mode.
+ * @param[in] pdm_edge PDM sampling mode.
+ */
+__STATIC_INLINE void nrf_pdm_mode_set(nrf_pdm_mode_t pdm_mode, nrf_pdm_edge_t pdm_edge)
+{
+    NRF_PDM->MODE = ((pdm_mode << PDM_MODE_OPERATION_Pos) & PDM_MODE_OPERATION_Msk)
+                    | ((pdm_edge << PDM_MODE_EDGE_Pos) & PDM_MODE_EDGE_Msk);
+}
+
+
+/**
+ * @brief Function for getting the PDM operation mode.
+ *
+ * @param[out] p_pdm_mode PDM operation mode.
+ * @param[out] p_pdm_edge PDM sampling mode.
+ */
+__STATIC_INLINE void nrf_pdm_mode_get(nrf_pdm_mode_t * p_pdm_mode, nrf_pdm_edge_t * p_pdm_edge)
+{
+    uint32_t mode = NRF_PDM->MODE;
+    *p_pdm_mode = (nrf_pdm_mode_t)((mode & PDM_MODE_OPERATION_Msk ) >> PDM_MODE_OPERATION_Pos);
+    *p_pdm_edge = (nrf_pdm_edge_t)((mode & PDM_MODE_EDGE_Msk ) >> PDM_MODE_EDGE_Pos);
+}
+
+
+/**
+ * @brief Function for setting the PDM clock frequency.
+ *
+ * @param[in] pdm_freq PDM clock frequency.
+ */
+__STATIC_INLINE void nrf_pdm_clock_set(nrf_pdm_freq_t pdm_freq)
+{
+    NRF_PDM->PDMCLKCTRL = ((pdm_freq << PDM_PDMCLKCTRL_FREQ_Pos) & PDM_PDMCLKCTRL_FREQ_Msk);
+}
+
+
+/**
+ * @brief Function for getting the PDM clock frequency.
+ */
+__STATIC_INLINE nrf_pdm_freq_t nrf_pdm_clock_get(void)
+{
+     return (nrf_pdm_freq_t) ((NRF_PDM->PDMCLKCTRL << PDM_PDMCLKCTRL_FREQ_Pos) & PDM_PDMCLKCTRL_FREQ_Msk);
+}
+
+
+/**
+ * @brief Function for setting up the PDM pins.
+ *
+ * @param[in] psel_clk CLK pin number.
+ * @param[in] psel_din DIN pin number.
+ */
+__STATIC_INLINE void nrf_pdm_psel_connect(uint32_t psel_clk, uint32_t psel_din)
+{
+    NRF_PDM->PSEL.CLK = psel_clk;
+    NRF_PDM->PSEL.DIN = psel_din;
+}
+
+/**
+ * @brief Function for disconnecting the PDM pins.
+ */
+__STATIC_INLINE void nrf_pdm_psel_disconnect()
+{
+    NRF_PDM->PSEL.CLK = ((PDM_PSEL_CLK_CONNECT_Disconnected << PDM_PSEL_CLK_CONNECT_Pos)
+                         & PDM_PSEL_CLK_CONNECT_Msk);
+    NRF_PDM->PSEL.DIN = ((PDM_PSEL_DIN_CONNECT_Disconnected << PDM_PSEL_DIN_CONNECT_Pos)
+                         & PDM_PSEL_DIN_CONNECT_Msk);
+}
+
+
+/**
+ * @brief Function for setting the PDM gain.
+ *
+ * @param[in] gain_l Left channel gain.
+ * @param[in] gain_r Right channel gain.
+ */
+__STATIC_INLINE void nrf_pdm_gain_set(nrf_pdm_gain_t gain_l, nrf_pdm_gain_t gain_r)
+{
+    NRF_PDM->GAINL = gain_l;
+    NRF_PDM->GAINR = gain_r;
+}
+
+
+/**
+ * @brief Function for getting the PDM gain.
+ *
+ * @param[out] p_gain_l Left channel gain.
+ * @param[out] p_gain_r Right channel gain.
+ */
+__STATIC_INLINE void nrf_pdm_gain_get(nrf_pdm_gain_t * p_gain_l, nrf_pdm_gain_t * p_gain_r)
+{
+    *p_gain_l = NRF_PDM->GAINL;
+    *p_gain_r = NRF_PDM->GAINR;
+}
+
+
+/**
+ * @brief Function for setting the PDM sample buffer.
+ *
+ * @param[in] p_buffer Pointer to the RAM address where samples should be written with EasyDMA.
+ * @param[in] num    Number of samples to allocate memory for in EasyDMA mode.
+ *
+ * The amount of allocated RAM depends on the operation mode.
+ * - For stereo mode: N 32-bit words.
+ * - For mono mode: Ceil(N/2) 32-bit words.
+ */
+__STATIC_INLINE void nrf_pdm_buffer_set(uint32_t * p_buffer, uint32_t num)
+{
+    NRF_PDM->SAMPLE.PTR = (uint32_t)p_buffer;
+    NRF_PDM->SAMPLE.MAXCNT = num;
+}
+
+/**
+ * @brief Function for getting the current PDM sample buffer address.
+ *
+ * @return Pointer to the current sample buffer.
+ */
+__STATIC_INLINE uint32_t * nrf_pdm_buffer_get()
+{
+    return (uint32_t *)NRF_PDM->SAMPLE.PTR;
+}
+
+
+/**
+ *@}
+ **/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF_PDM_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_peripherals.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,68 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_PERIPHERALS_H
+#define NRF_PERIPHERALS_H
+
+/*lint ++flb "Enter library region */
+
+#ifdef NRF51422
+#include "nrf51422_peripherals.h"
+#endif
+
+#ifdef NRF51802
+#include "nrf51802_peripherals.h"
+#endif
+
+#ifdef NRF51822
+#include "nrf51822_peripherals.h"
+#endif
+
+#ifdef NRF52832
+#include "nrf52832_peripherals.h"
+#endif
+
+#ifdef NRF52840_XXAA
+#include "nrf52840_peripherals.h"
+#endif
+
+
+/*lint --flb "Leave library region" */
+
+#endif /* NRF_PERIPHERALS_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_power.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,1037 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef NRF_POWER_H__
+#define NRF_POWER_H__
+
+/**
+ * @ingroup nrf_power
+ * @defgroup nrf_power_hal POWER HAL
+ * @{
+ *
+ * Hardware access layer for (POWER) peripheral.
+ */
+#include "nrf.h"
+#include "sdk_config.h"
+#include "nordic_common.h"
+#include "nrf_assert.h"
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name The implemented functionality
+ * @{
+ *
+ * Macros that defines functionality that is implemented into POWER peripheral.
+ */
+#if defined(POWER_INTENSET_SLEEPENTER_Msk) || defined(__SDK_DOXYGEN__)
+/**
+ * @brief The fact that sleep events are present
+ *
+ * In some MCUs there is possibility to process sleep entering and exiting
+ * events.
+ */
+#define NRF_POWER_HAS_SLEEPEVT 1
+#else
+#define NRF_POWER_HAS_SLEEPEVT 0
+#endif
+
+#if defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__SDK_DOXYGEN__)
+/**
+ * @brief The fact that RAMPOWER registers are present
+ *
+ * After nRF51, new way to manage RAM power was implemented.
+ * Special registers, one for every RAM block that makes it possible to
+ * power ON or OFF RAM segments and turn ON and OFF RAM retention in system OFF
+ * state.
+ */
+#define NRF_POWER_HAS_RAMPOWER_REGS 1
+#else
+#define NRF_POWER_HAS_RAMPOWER_REGS 0
+#endif
+
+#if defined(POWER_POFCON_THRESHOLDVDDH_Msk) || defined(__SDK_DOXYGEN__)
+/**
+ * @brief Auxiliary definition to mark the fact that VDDH is present
+ *
+ * This definition can be used in a code to decide if the part with VDDH
+ * related settings should be implemented.
+ */
+#define NRF_POWER_HAS_VDDH 1
+#else
+#define NRF_POWER_HAS_VDDH 0
+#endif
+
+#if defined(POWER_USBREGSTATUS_VBUSDETECT_Msk) || defined(__SDK_DOXYGEN__)
+/**
+ * @brief The fact that power module manages USB regulator
+ *
+ * In devices that have USB, power peripheral manages also connection
+ * detection and USB power regulator, that converts 5&nbsp;V to 3.3&nbsp;V
+ * used by USBD peripheral.
+ */
+#define NRF_POWER_HAS_USBREG 1
+#else
+#define NRF_POWER_HAS_USBREG 0
+#endif
+/** @} */
+
+/* ------------------------------------------------------------------------------------------------
+ *  Begin of automatically generated part
+ * ------------------------------------------------------------------------------------------------
+ */
+
+/**
+ * @brief POWER tasks
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_POWER_TASK_CONSTLAT  = offsetof(NRF_POWER_Type, TASKS_CONSTLAT), /**< Enable constant latency mode */
+    NRF_POWER_TASK_LOWPWR    = offsetof(NRF_POWER_Type, TASKS_LOWPWR  ), /**< Enable low power mode (variable latency) */
+}nrf_power_task_t; /*lint -restore */
+
+/**
+ * @brief POWER events
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_POWER_EVENT_POFWARN      = offsetof(NRF_POWER_Type, EVENTS_POFWARN    ), /**< Power failure warning */
+#if NRF_POWER_HAS_SLEEPEVT
+    NRF_POWER_EVENT_SLEEPENTER   = offsetof(NRF_POWER_Type, EVENTS_SLEEPENTER ), /**< CPU entered WFI/WFE sleep */
+    NRF_POWER_EVENT_SLEEPEXIT    = offsetof(NRF_POWER_Type, EVENTS_SLEEPEXIT  ), /**< CPU exited WFI/WFE sleep */
+#endif
+#if NRF_POWER_HAS_USBREG
+    NRF_POWER_EVENT_USBDETECTED  = offsetof(NRF_POWER_Type, EVENTS_USBDETECTED), /**< Voltage supply detected on VBUS */
+    NRF_POWER_EVENT_USBREMOVED   = offsetof(NRF_POWER_Type, EVENTS_USBREMOVED ), /**< Voltage supply removed from VBUS */
+    NRF_POWER_EVENT_USBPWRRDY    = offsetof(NRF_POWER_Type, EVENTS_USBPWRRDY  ), /**< USB 3.3&nbsp;V supply ready */
+#endif
+}nrf_power_event_t; /*lint -restore */
+
+/**
+ * @brief POWER interrupts
+ */
+typedef enum
+{
+    NRF_POWER_INT_POFWARN_MASK     = POWER_INTENSET_POFWARN_Msk    , /**< Write '1' to Enable interrupt for POFWARN event */
+#if NRF_POWER_HAS_SLEEPEVT
+    NRF_POWER_INT_SLEEPENTER_MASK  = POWER_INTENSET_SLEEPENTER_Msk , /**< Write '1' to Enable interrupt for SLEEPENTER event */
+    NRF_POWER_INT_SLEEPEXIT_MASK   = POWER_INTENSET_SLEEPEXIT_Msk  , /**< Write '1' to Enable interrupt for SLEEPEXIT event */
+#endif
+#if NRF_POWER_HAS_USBREG
+    NRF_POWER_INT_USBDETECTED_MASK = POWER_INTENSET_USBDETECTED_Msk, /**< Write '1' to Enable interrupt for USBDETECTED event */
+    NRF_POWER_INT_USBREMOVED_MASK  = POWER_INTENSET_USBREMOVED_Msk , /**< Write '1' to Enable interrupt for USBREMOVED event */
+    NRF_POWER_INT_USBPWRRDY_MASK   = POWER_INTENSET_USBPWRRDY_Msk  , /**< Write '1' to Enable interrupt for USBPWRRDY event */
+#endif
+}nrf_power_int_mask_t;
+
+/**
+ * @brief Function for activating a specific POWER task.
+ *
+ * @param task Task.
+ */
+__STATIC_INLINE void nrf_power_task_trigger(nrf_power_task_t task);
+
+/**
+ * @brief Function for returning the address of a specific POWER task register.
+ *
+ * @param task Task.
+ *
+ * @return Task address.
+ */
+__STATIC_INLINE uint32_t nrf_power_task_address_get(nrf_power_task_t task);
+
+/**
+ * @brief Function for clearing a specific event.
+ *
+ * @param event Event.
+ */
+__STATIC_INLINE void nrf_power_event_clear(nrf_power_event_t event);
+
+/**
+ * @brief Function for returning the state of a specific event.
+ *
+ * @param event Event.
+ *
+ * @retval true If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_power_event_check(nrf_power_event_t event);
+
+/**
+ * @brief Function for getting and clearing the state of specific event
+ *
+ * This function checks the state of the event and clears it.
+ *
+ * @param event Event.
+ *
+ * @retval true If the event was set.
+ * @retval false If the event was not set.
+ */
+__STATIC_INLINE bool nrf_power_event_get_and_clear(nrf_power_event_t event);
+
+/**
+ * @brief Function for returning the address of a specific POWER event register.
+ *
+ * @param     event  Event.
+ *
+ * @return Address.
+ */
+__STATIC_INLINE uint32_t nrf_power_event_address_get(nrf_power_event_t event);
+
+/**
+ * @brief Function for enabling selected interrupts.
+ *
+ * @param     int_mask Interrupts mask.
+ */
+__STATIC_INLINE void nrf_power_int_enable(uint32_t int_mask);
+
+/**
+ * @brief Function for retrieving the state of selected interrupts.
+ *
+ * @param     int_mask Interrupts mask.
+ *
+ * @retval true If any of selected interrupts is enabled.
+ * @retval false If none of selected interrupts is enabled.
+ */
+__STATIC_INLINE bool nrf_power_int_enable_check(uint32_t int_mask);
+
+/**
+ * @brief Function for retrieving the information about enabled interrupts.
+ *
+ * @return The flags of enabled interrupts.
+ */
+__STATIC_INLINE uint32_t nrf_power_int_enable_get(void);
+
+/**
+ * @brief Function for disabling selected interrupts.
+ *
+ * @param     int_mask Interrupts mask.
+ */
+__STATIC_INLINE void nrf_power_int_disable(uint32_t int_mask);
+
+
+/** @} */ /*  End of nrf_power_hal */
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+/* ------------------------------------------------------------------------------------------------
+ *  Internal functions
+ */
+
+/**
+ * @internal
+ * @brief Internal function for getting task/event register address
+ *
+ * @oaram offset Offset of the register from the instance beginning
+ *
+ * @attention offset has to be modulo 4 value. In other case we can get hardware fault.
+ * @return Pointer to the register
+ */
+__STATIC_INLINE volatile uint32_t * nrf_power_regptr_get(uint32_t offset)
+{
+    return (volatile uint32_t *)(((uint8_t *)NRF_POWER) + (uint32_t)offset);
+}
+
+/**
+ * @internal
+ * @brief Internal function for getting task/event register address - constant version
+ *
+ * @oaram offset Offset of the register from the instance beginning
+ *
+ * @attention offset has to be modulo 4 value. In other case we can get hardware fault.
+ * @return Pointer to the register
+ */
+__STATIC_INLINE volatile const uint32_t * nrf_power_regptr_get_c(
+    uint32_t offset)
+{
+    return (volatile const uint32_t *)(((uint8_t *)NRF_POWER) +
+        (uint32_t)offset);
+}
+
+/* ------------------------------------------------------------------------------------------------
+ *  Interface functions definitions
+ */
+
+void nrf_power_task_trigger(nrf_power_task_t task)
+{
+    *(nrf_power_regptr_get((uint32_t)task)) = 1UL;
+}
+
+uint32_t nrf_power_task_address_get(nrf_power_task_t task)
+{
+    return (uint32_t)nrf_power_regptr_get_c((uint32_t)task);
+}
+
+void nrf_power_event_clear(nrf_power_event_t event)
+{
+    *(nrf_power_regptr_get((uint32_t)event)) = 0UL;
+}
+
+bool nrf_power_event_check(nrf_power_event_t event)
+{
+    return (bool)*nrf_power_regptr_get_c((uint32_t)event);
+}
+
+bool nrf_power_event_get_and_clear(nrf_power_event_t event)
+{
+    bool ret = nrf_power_event_check(event);
+    if(ret)
+    {
+        nrf_power_event_clear(event);
+    }
+    return ret;
+}
+
+uint32_t nrf_power_event_address_get(nrf_power_event_t event)
+{
+    return (uint32_t)nrf_power_regptr_get_c((uint32_t)event);
+}
+
+void nrf_power_int_enable(uint32_t int_mask)
+{
+    NRF_POWER->INTENSET = int_mask;
+}
+
+bool nrf_power_int_enable_check(uint32_t int_mask)
+{
+    return !!(NRF_POWER->INTENSET & int_mask);
+}
+
+uint32_t nrf_power_int_enable_get(void)
+{
+    return NRF_POWER->INTENSET;
+}
+
+void nrf_power_int_disable(uint32_t int_mask)
+{
+    NRF_POWER->INTENCLR = int_mask;
+}
+
+#endif /* SUPPRESS_INLINE_IMPLEMENTATION */
+
+/* ------------------------------------------------------------------------------------------------
+ *  End of automatically generated part
+ * ------------------------------------------------------------------------------------------------
+ */
+/**
+ * @ingroup nrf_power_hal
+ * @{
+ */
+
+/**
+ * @brief Reset reason
+ */
+typedef enum
+{
+    NRF_POWER_RESETREAS_RESETPIN_MASK = POWER_RESETREAS_RESETPIN_Msk, /*!< Bit mask of RESETPIN field. *///!< NRF_POWER_RESETREAS_RESETPIN_MASK
+    NRF_POWER_RESETREAS_DOG_MASK      = POWER_RESETREAS_DOG_Msk     , /*!< Bit mask of DOG field. */     //!< NRF_POWER_RESETREAS_DOG_MASK
+    NRF_POWER_RESETREAS_SREQ_MASK     = POWER_RESETREAS_SREQ_Msk    , /*!< Bit mask of SREQ field. */    //!< NRF_POWER_RESETREAS_SREQ_MASK
+    NRF_POWER_RESETREAS_LOCKUP_MASK   = POWER_RESETREAS_LOCKUP_Msk  , /*!< Bit mask of LOCKUP field. */  //!< NRF_POWER_RESETREAS_LOCKUP_MASK
+    NRF_POWER_RESETREAS_OFF_MASK      = POWER_RESETREAS_OFF_Msk     , /*!< Bit mask of OFF field. */     //!< NRF_POWER_RESETREAS_OFF_MASK
+    NRF_POWER_RESETREAS_LPCOMP_MASK   = POWER_RESETREAS_LPCOMP_Msk  , /*!< Bit mask of LPCOMP field. */  //!< NRF_POWER_RESETREAS_LPCOMP_MASK
+    NRF_POWER_RESETREAS_DIF_MASK      = POWER_RESETREAS_DIF_Msk     , /*!< Bit mask of DIF field. */     //!< NRF_POWER_RESETREAS_DIF_MASK
+#if defined(POWER_RESETREAS_NFC_Msk) || defined(__SDK_DOXYGEN__)
+    NRF_POWER_RESETREAS_NFC_MASK      = POWER_RESETREAS_NFC_Msk     , /*!< Bit mask of NFC field. */
+#endif
+#if defined(POWER_RESETREAS_VBUS_Msk) || defined(__SDK_DOXYGEN__)
+    NRF_POWER_RESETREAS_VBUS_MASK     = POWER_RESETREAS_VBUS_Msk    , /*!< Bit mask of VBUS field. */
+#endif
+}nrf_power_resetreas_mask_t;
+
+#if NRF_POWER_HAS_USBREG
+/**
+ * @brief USBREGSTATUS register bit masks
+ *
+ * @sa nrf_power_usbregstatus_get
+ */
+typedef enum
+{
+    NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK = POWER_USBREGSTATUS_VBUSDETECT_Msk, /**< USB detected or removed     */
+    NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK  = POWER_USBREGSTATUS_OUTPUTRDY_Msk   /**< USB 3.3&nbsp;V supply ready */
+}nrf_power_usbregstatus_mask_t;
+#endif
+
+/**
+ * @brief RAM blocks numbers
+ *
+ * @sa nrf_power_ramblock_mask_t
+ * @note
+ * Ram blocks has to been used in nrf51.
+ * In new CPU ram is divided into segments and this functionality is depreciated.
+ * For the newer MCU see the PS for mapping between internal RAM and RAM blocks,
+ * because this mapping is not 1:1, and functions related to old style blocks
+ * should not be used.
+ */
+typedef enum
+{
+    NRF_POWER_RAMBLOCK0 = POWER_RAMSTATUS_RAMBLOCK0_Pos,
+    NRF_POWER_RAMBLOCK1 = POWER_RAMSTATUS_RAMBLOCK1_Pos,
+    NRF_POWER_RAMBLOCK2 = POWER_RAMSTATUS_RAMBLOCK2_Pos,
+    NRF_POWER_RAMBLOCK3 = POWER_RAMSTATUS_RAMBLOCK3_Pos
+}nrf_power_ramblock_t;
+
+/**
+ * @brief RAM blocks masks
+ *
+ * @sa nrf_power_ramblock_t
+ */
+typedef enum
+{
+    NRF_POWER_RAMBLOCK0_MASK = POWER_RAMSTATUS_RAMBLOCK0_Msk,
+    NRF_POWER_RAMBLOCK1_MASK = POWER_RAMSTATUS_RAMBLOCK1_Msk,
+    NRF_POWER_RAMBLOCK2_MASK = POWER_RAMSTATUS_RAMBLOCK2_Msk,
+    NRF_POWER_RAMBLOCK3_MASK = POWER_RAMSTATUS_RAMBLOCK3_Msk
+}nrf_power_ramblock_mask_t;
+
+/**
+ * @brief RAM power state position of the bits
+ *
+ * @sa nrf_power_onoffram_mask_t
+ */
+typedef enum
+{
+    NRF_POWER_ONRAM0,  /**< Keep RAM block 0 on or off in system ON Mode                 */
+    NRF_POWER_OFFRAM0, /**< Keep retention on RAM block 0 when RAM block is switched off */
+    NRF_POWER_ONRAM1,  /**< Keep RAM block 1 on or off in system ON Mode                 */
+    NRF_POWER_OFFRAM1, /**< Keep retention on RAM block 1 when RAM block is switched off */
+    NRF_POWER_ONRAM2,  /**< Keep RAM block 2 on or off in system ON Mode                 */
+    NRF_POWER_OFFRAM2, /**< Keep retention on RAM block 2 when RAM block is switched off */
+    NRF_POWER_ONRAM3,  /**< Keep RAM block 3 on or off in system ON Mode                 */
+    NRF_POWER_OFFRAM3, /**< Keep retention on RAM block 3 when RAM block is switched off */
+}nrf_power_onoffram_t;
+
+/**
+ * @brief RAM power state bit masks
+ *
+ * @sa nrf_power_onoffram_t
+ */
+typedef enum
+{
+    NRF_POWER_ONRAM0_MASK  = 1U << NRF_POWER_ONRAM0,  /**< Keep RAM block 0 on or off in system ON Mode                 */
+    NRF_POWER_OFFRAM0_MASK = 1U << NRF_POWER_OFFRAM0, /**< Keep retention on RAM block 0 when RAM block is switched off */
+    NRF_POWER_ONRAM1_MASK  = 1U << NRF_POWER_ONRAM1,  /**< Keep RAM block 1 on or off in system ON Mode                 */
+    NRF_POWER_OFFRAM1_MASK = 1U << NRF_POWER_OFFRAM1, /**< Keep retention on RAM block 1 when RAM block is switched off */
+    NRF_POWER_ONRAM2_MASK  = 1U << NRF_POWER_ONRAM2,  /**< Keep RAM block 2 on or off in system ON Mode                 */
+    NRF_POWER_OFFRAM2_MASK = 1U << NRF_POWER_OFFRAM2, /**< Keep retention on RAM block 2 when RAM block is switched off */
+    NRF_POWER_ONRAM3_MASK  = 1U << NRF_POWER_ONRAM3,  /**< Keep RAM block 3 on or off in system ON Mode                 */
+    NRF_POWER_OFFRAM3_MASK = 1U << NRF_POWER_OFFRAM3, /**< Keep retention on RAM block 3 when RAM block is switched off */
+}nrf_power_onoffram_mask_t;
+
+/**
+ * @brief Power failure comparator thresholds
+ */
+typedef enum
+{
+    NRF_POWER_POFTHR_V21 = POWER_POFCON_THRESHOLD_V21, /**< Set threshold to 2.1&nbsp;V */
+    NRF_POWER_POFTHR_V23 = POWER_POFCON_THRESHOLD_V23, /**< Set threshold to 2.3&nbsp;V */
+    NRF_POWER_POFTHR_V25 = POWER_POFCON_THRESHOLD_V25, /**< Set threshold to 2.5&nbsp;V */
+    NRF_POWER_POFTHR_V27 = POWER_POFCON_THRESHOLD_V27, /**< Set threshold to 2.7&nbsp;V */
+#if defined(POWER_POFCON_THRESHOLD_V17) || defined(__SDK_DOXYGEN__)
+    NRF_POWER_POFTHR_V17 = POWER_POFCON_THRESHOLD_V17, /**< Set threshold to 1.7&nbsp;V */
+    NRF_POWER_POFTHR_V18 = POWER_POFCON_THRESHOLD_V18, /**< Set threshold to 1.8&nbsp;V */
+    NRF_POWER_POFTHR_V19 = POWER_POFCON_THRESHOLD_V19, /**< Set threshold to 1.9&nbsp;V */
+    NRF_POWER_POFTHR_V20 = POWER_POFCON_THRESHOLD_V20, /**< Set threshold to 2.0&nbsp;V */
+    NRF_POWER_POFTHR_V22 = POWER_POFCON_THRESHOLD_V22, /**< Set threshold to 2.2&nbsp;V */
+    NRF_POWER_POFTHR_V24 = POWER_POFCON_THRESHOLD_V24, /**< Set threshold to 2.4&nbsp;V */
+    NRF_POWER_POFTHR_V26 = POWER_POFCON_THRESHOLD_V26, /**< Set threshold to 2.6&nbsp;V */
+    NRF_POWER_POFTHR_V28 = POWER_POFCON_THRESHOLD_V28, /**< Set threshold to 2.8&nbsp;V */
+#endif
+}nrf_power_pof_thr_t;
+
+#if NRF_POWER_HAS_VDDH
+/**
+ * @brief Power failure comparator thresholds for VDDH
+ */
+typedef enum
+{
+    NRF_POWER_POFTHRVDDH_V27 = POWER_POFCON_THRESHOLDVDDH_V27, /**< Set threshold to 2.7&nbsp;V */
+    NRF_POWER_POFTHRVDDH_V28 = POWER_POFCON_THRESHOLDVDDH_V28, /**< Set threshold to 2.8&nbsp;V */
+    NRF_POWER_POFTHRVDDH_V29 = POWER_POFCON_THRESHOLDVDDH_V29, /**< Set threshold to 2.9&nbsp;V */
+    NRF_POWER_POFTHRVDDH_V30 = POWER_POFCON_THRESHOLDVDDH_V30, /**< Set threshold to 3.0&nbsp;V */
+    NRF_POWER_POFTHRVDDH_V31 = POWER_POFCON_THRESHOLDVDDH_V31, /**< Set threshold to 3.1&nbsp;V */
+    NRF_POWER_POFTHRVDDH_V32 = POWER_POFCON_THRESHOLDVDDH_V32, /**< Set threshold to 3.2&nbsp;V */
+    NRF_POWER_POFTHRVDDH_V33 = POWER_POFCON_THRESHOLDVDDH_V33, /**< Set threshold to 3.3&nbsp;V */
+    NRF_POWER_POFTHRVDDH_V34 = POWER_POFCON_THRESHOLDVDDH_V34, /**< Set threshold to 3.4&nbsp;V */
+    NRF_POWER_POFTHRVDDH_V35 = POWER_POFCON_THRESHOLDVDDH_V35, /**< Set threshold to 3.5&nbsp;V */
+    NRF_POWER_POFTHRVDDH_V36 = POWER_POFCON_THRESHOLDVDDH_V36, /**< Set threshold to 3.6&nbsp;V */
+    NRF_POWER_POFTHRVDDH_V37 = POWER_POFCON_THRESHOLDVDDH_V37, /**< Set threshold to 3.7&nbsp;V */
+    NRF_POWER_POFTHRVDDH_V38 = POWER_POFCON_THRESHOLDVDDH_V38, /**< Set threshold to 3.8&nbsp;V */
+    NRF_POWER_POFTHRVDDH_V39 = POWER_POFCON_THRESHOLDVDDH_V39, /**< Set threshold to 3.9&nbsp;V */
+    NRF_POWER_POFTHRVDDH_V40 = POWER_POFCON_THRESHOLDVDDH_V40, /**< Set threshold to 4.0&nbsp;V */
+    NRF_POWER_POFTHRVDDH_V41 = POWER_POFCON_THRESHOLDVDDH_V41, /**< Set threshold to 4.1&nbsp;V */
+    NRF_POWER_POFTHRVDDH_V42 = POWER_POFCON_THRESHOLDVDDH_V42, /**< Set threshold to 4.2&nbsp;V */
+}nrf_power_pof_thrvddh_t;
+
+/**
+ * @brief Main regulator status
+ */
+typedef enum
+{
+    NRF_POWER_MAINREGSTATUS_NORMAL = POWER_MAINREGSTATUS_MAINREGSTATUS_Normal, /**< Normal voltage mode. Voltage supplied on VDD. */
+    NRF_POWER_MAINREGSTATUS_HIGH   = POWER_MAINREGSTATUS_MAINREGSTATUS_High    /**< High voltage mode. Voltage supplied on VDDH.  */
+}nrf_power_mainregstatus_t;
+
+#endif /* NRF_POWER_HAS_VDDH */
+
+#if NRF_POWER_HAS_RAMPOWER_REGS
+/**
+ * @brief Bit positions for RAMPOWER register
+ *
+ * All possible bits described, even if they are not used in selected MCU.
+ */
+typedef enum
+{
+    /** Keep RAM section S0 ON in System ON mode */
+    NRF_POWER_RAMPOWER_S0POWER = POWER_RAM_POWER_S0POWER_Pos,
+    NRF_POWER_RAMPOWER_S1POWER,  /**< Keep RAM section S1 ON in System ON mode */
+    NRF_POWER_RAMPOWER_S2POWER,  /**< Keep RAM section S2 ON in System ON mode */
+    NRF_POWER_RAMPOWER_S3POWER,  /**< Keep RAM section S3 ON in System ON mode */
+    NRF_POWER_RAMPOWER_S4POWER,  /**< Keep RAM section S4 ON in System ON mode */
+    NRF_POWER_RAMPOWER_S5POWER,  /**< Keep RAM section S5 ON in System ON mode */
+    NRF_POWER_RAMPOWER_S6POWER,  /**< Keep RAM section S6 ON in System ON mode */
+    NRF_POWER_RAMPOWER_S7POWER,  /**< Keep RAM section S7 ON in System ON mode */
+    NRF_POWER_RAMPOWER_S8POWER,  /**< Keep RAM section S8 ON in System ON mode */
+    NRF_POWER_RAMPOWER_S9POWER,  /**< Keep RAM section S9 ON in System ON mode */
+    NRF_POWER_RAMPOWER_S10POWER, /**< Keep RAM section S10 ON in System ON mode */
+    NRF_POWER_RAMPOWER_S11POWER, /**< Keep RAM section S11 ON in System ON mode */
+    NRF_POWER_RAMPOWER_S12POWER, /**< Keep RAM section S12 ON in System ON mode */
+    NRF_POWER_RAMPOWER_S13POWER, /**< Keep RAM section S13 ON in System ON mode */
+    NRF_POWER_RAMPOWER_S14POWER, /**< Keep RAM section S14 ON in System ON mode */
+    NRF_POWER_RAMPOWER_S15POWER, /**< Keep RAM section S15 ON in System ON mode */
+
+    /** Keep section retention in OFF mode when section is OFF */
+    NRF_POWER_RAMPOWER_S0RETENTION = POWER_RAM_POWER_S0RETENTION_Pos,
+    NRF_POWER_RAMPOWER_S1RETENTION,  /**< Keep section retention in OFF mode when section is OFF */
+    NRF_POWER_RAMPOWER_S2RETENTION,  /**< Keep section retention in OFF mode when section is OFF */
+    NRF_POWER_RAMPOWER_S3RETENTION,  /**< Keep section retention in OFF mode when section is OFF */
+    NRF_POWER_RAMPOWER_S4RETENTION,  /**< Keep section retention in OFF mode when section is OFF */
+    NRF_POWER_RAMPOWER_S5RETENTION,  /**< Keep section retention in OFF mode when section is OFF */
+    NRF_POWER_RAMPOWER_S6RETENTION,  /**< Keep section retention in OFF mode when section is OFF */
+    NRF_POWER_RAMPOWER_S7RETENTION,  /**< Keep section retention in OFF mode when section is OFF */
+    NRF_POWER_RAMPOWER_S8RETENTION,  /**< Keep section retention in OFF mode when section is OFF */
+    NRF_POWER_RAMPOWER_S9RETENTION,  /**< Keep section retention in OFF mode when section is OFF */
+    NRF_POWER_RAMPOWER_S10RETENTION, /**< Keep section retention in OFF mode when section is OFF */
+    NRF_POWER_RAMPOWER_S11RETENTION, /**< Keep section retention in OFF mode when section is OFF */
+    NRF_POWER_RAMPOWER_S12RETENTION, /**< Keep section retention in OFF mode when section is OFF */
+    NRF_POWER_RAMPOWER_S13RETENTION, /**< Keep section retention in OFF mode when section is OFF */
+    NRF_POWER_RAMPOWER_S14RETENTION, /**< Keep section retention in OFF mode when section is OFF */
+    NRF_POWER_RAMPOWER_S15RETENTION, /**< Keep section retention in OFF mode when section is OFF */
+}nrf_power_rampower_t;
+
+#if defined ( __CC_ARM )
+#pragma push
+#pragma diag_suppress 66
+#endif
+/**
+ * @brief Bit masks for RAMPOWER register
+ *
+ * All possible bits described, even if they are not used in selected MCU.
+ */
+typedef enum
+{
+    NRF_POWER_RAMPOWER_S0POWER_MASK  = 1UL << NRF_POWER_RAMPOWER_S0POWER ,
+    NRF_POWER_RAMPOWER_S1POWER_MASK  = 1UL << NRF_POWER_RAMPOWER_S1POWER ,
+    NRF_POWER_RAMPOWER_S2POWER_MASK  = 1UL << NRF_POWER_RAMPOWER_S2POWER ,
+    NRF_POWER_RAMPOWER_S3POWER_MASK  = 1UL << NRF_POWER_RAMPOWER_S3POWER ,
+    NRF_POWER_RAMPOWER_S4POWER_MASK  = 1UL << NRF_POWER_RAMPOWER_S4POWER ,
+    NRF_POWER_RAMPOWER_S5POWER_MASK  = 1UL << NRF_POWER_RAMPOWER_S5POWER ,
+    NRF_POWER_RAMPOWER_S7POWER_MASK  = 1UL << NRF_POWER_RAMPOWER_S7POWER ,
+    NRF_POWER_RAMPOWER_S8POWER_MASK  = 1UL << NRF_POWER_RAMPOWER_S8POWER ,
+    NRF_POWER_RAMPOWER_S9POWER_MASK  = 1UL << NRF_POWER_RAMPOWER_S9POWER ,
+    NRF_POWER_RAMPOWER_S10POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S10POWER,
+    NRF_POWER_RAMPOWER_S11POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S11POWER,
+    NRF_POWER_RAMPOWER_S12POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S12POWER,
+    NRF_POWER_RAMPOWER_S13POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S13POWER,
+    NRF_POWER_RAMPOWER_S14POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S14POWER,
+    NRF_POWER_RAMPOWER_S15POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S15POWER,
+
+    NRF_POWER_RAMPOWER_S0RETENTION_MASK  = 1UL << NRF_POWER_RAMPOWER_S0RETENTION ,
+    NRF_POWER_RAMPOWER_S1RETENTION_MASK  = 1UL << NRF_POWER_RAMPOWER_S1RETENTION ,
+    NRF_POWER_RAMPOWER_S2RETENTION_MASK  = 1UL << NRF_POWER_RAMPOWER_S2RETENTION ,
+    NRF_POWER_RAMPOWER_S3RETENTION_MASK  = 1UL << NRF_POWER_RAMPOWER_S3RETENTION ,
+    NRF_POWER_RAMPOWER_S4RETENTION_MASK  = 1UL << NRF_POWER_RAMPOWER_S4RETENTION ,
+    NRF_POWER_RAMPOWER_S5RETENTION_MASK  = 1UL << NRF_POWER_RAMPOWER_S5RETENTION ,
+    NRF_POWER_RAMPOWER_S7RETENTION_MASK  = 1UL << NRF_POWER_RAMPOWER_S7RETENTION ,
+    NRF_POWER_RAMPOWER_S8RETENTION_MASK  = 1UL << NRF_POWER_RAMPOWER_S8RETENTION ,
+    NRF_POWER_RAMPOWER_S9RETENTION_MASK  = 1UL << NRF_POWER_RAMPOWER_S9RETENTION ,
+    NRF_POWER_RAMPOWER_S10RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S10RETENTION,
+    NRF_POWER_RAMPOWER_S11RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S11RETENTION,
+    NRF_POWER_RAMPOWER_S12RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S12RETENTION,
+    NRF_POWER_RAMPOWER_S13RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S13RETENTION,
+    NRF_POWER_RAMPOWER_S14RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S14RETENTION,
+    NRF_POWER_RAMPOWER_S15RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S15RETENTION,
+}nrf_power_rampower_mask_t;
+#if defined ( __CC_ARM )
+#pragma pop
+#endif
+#endif /* NRF_POWER_HAS_RAMPOWER_REGS */
+
+
+/**
+ * @brief Get reset reason mask
+ *
+ * Function returns the reset reason.
+ * Unless cleared, the RESETREAS register is cumulative.
+ * A field is cleared by writing '1' to it (see @ref nrf_power_resetreas_clear).
+ * If none of the reset sources are flagged,
+ * this indicates that the chip was reset from the on-chip reset generator,
+ * which indicates a power-on-reset or a brown out reset.
+ *
+ * @return The mask of reset reasons constructed with @ref nrf_power_resetreas_mask_t.
+ */
+__STATIC_INLINE uint32_t nrf_power_resetreas_get(void);
+
+/**
+ * @brief Clear selected reset reason field
+ *
+ * Function clears selected reset reason fields.
+ *
+ * @param[in] mask The mask constructed from @ref nrf_power_resetreas_mask_t enumerator values.
+ * @sa nrf_power_resetreas_get
+ */
+__STATIC_INLINE void nrf_power_resetreas_clear(uint32_t mask);
+
+/**
+ * @brief Get RAMSTATUS register
+ *
+ * Returns the masks of RAM blocks that are powered ON.
+ *
+ * @return Value with bits sets according to masks in @ref nrf_power_ramblock_mask_t.
+ */
+__STATIC_INLINE uint32_t nrf_power_ramstatus_get(void);
+
+/**
+ * @brief Go to system OFF
+ *
+ * This function puts the CPU into system off mode.
+ * The only way to wake up the CPU is by reset.
+ *
+ * @note This function never returns.
+ */
+__STATIC_INLINE void nrf_power_system_off(void);
+
+/**
+ * @brief Set power failure comparator configuration
+ *
+ * Sets power failure comparator threshold and enable/disable flag.
+ *
+ * @param enabled Set to true if power failure comparator should be enabled.
+ * @param thr     Set the voltage threshold value.
+ *
+ * @note
+ * If VDDH settings is present in the device, this function would
+ * clear it settings (set to the lowest voltage).
+ * Use @ref nrf_power_pofcon_vddh_set function to set new value.
+ */
+__STATIC_INLINE void nrf_power_pofcon_set(bool enabled, nrf_power_pof_thr_t thr);
+
+/**
+ * @brief Get power failure comparator configuration
+ *
+ * Get power failure comparator threshold and enable bit.
+ *
+ * @param[out] p_enabled Function would set this boolean variable to true
+ *                       if power failure comparator is enabled.
+ *                       The pointer can be NULL if we do not need this information.
+ * @return Threshold setting for power failure comparator
+ */
+__STATIC_INLINE nrf_power_pof_thr_t nrf_power_pofcon_get(bool * p_enabled);
+
+#if NRF_POWER_HAS_VDDH
+/**
+ * @brief Set VDDH power failure comparator threshold
+ *
+ * @param thr Threshold to be set
+ */
+__STATIC_INLINE void nrf_power_pofcon_vddh_set(nrf_power_pof_thrvddh_t thr);
+
+/**
+ * @brief Get VDDH power failure comparator threshold
+ *
+ * @return VDDH threshold currently configured
+ */
+__STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(void);
+#endif
+
+/**
+ * @brief Set general purpose retention register
+ *
+ * @param val Value to be set in the register
+ */
+__STATIC_INLINE void nrf_power_gpregret_set(uint8_t val);
+
+/**
+ * @brief Get general purpose retention register
+ *
+ * @return The value from the register
+ */
+__STATIC_INLINE uint8_t nrf_power_gpregret_get(void);
+
+#if defined(POWER_GPREGRET2_GPREGRET_Msk) || defined(__SDK_DOXYGEN__)
+/**
+ * @brief Set general purpose retention register 2
+ *
+ * @param val Value to be set in the register
+ * @note This register is not available in nrf51 MCU family
+ */
+__STATIC_INLINE void nrf_power_gpregret2_set(uint8_t val);
+
+/**
+ * @brief Get general purpose retention register 2
+ *
+ * @return The value from the register
+ * @note This register is not available in all MCUs.
+ */
+__STATIC_INLINE uint8_t nrf_power_gpregret2_get(void);
+#endif
+
+/**
+ * @brief Enable or disable DCDC converter
+ *
+ * @param enable Set true to enable or false to disable DCDC converter.
+ *
+ * @note
+ * If the device consist of high voltage power input (VDDH) this setting
+ * would relate to the converter on low voltage side (1.3&nbsp;V output).
+ */
+__STATIC_INLINE void nrf_power_dcdcen_set(bool enable);
+
+/**
+ * @brief Get the state of DCDC converter
+ *
+ * @retval true  Converter is enabled
+ * @retval false Converter is disabled
+ *
+ * @note
+ * If the device consist of high voltage power input (VDDH) this setting
+ * would relate to the converter on low voltage side (1.3&nbsp;V output).
+ */
+__STATIC_INLINE bool nrf_power_dcdcen_get(void);
+
+#if NRF_POWER_HAS_RAMPOWER_REGS
+/**
+ * @brief Turn ON sections in selected RAM block.
+ *
+ * This function turns ON sections in block and also block retention.
+ *
+ * @sa nrf_power_rampower_mask_t
+ * @sa nrf_power_rampower_mask_off
+ *
+ * @param block        RAM block index.
+ * @param section_mask Mask of the sections created by merging
+ *                     @ref nrf_power_rampower_mask_t flags.
+ */
+__STATIC_INLINE void nrf_power_rampower_mask_on(uint8_t block, uint32_t section_mask);
+
+/**
+ * @brief Turn ON sections in selected RAM block.
+ *
+ * This function turns OFF sections in block and also block retention.
+ *
+ * @sa nrf_power_rampower_mask_t
+ * @sa nrf_power_rampower_mask_off
+ *
+ * @param block        RAM block index.
+ * @param section_mask Mask of the sections created by merging
+ *                     @ref nrf_power_rampower_mask_t flags.
+ */
+__STATIC_INLINE void nrf_power_rampower_mask_off(uint8_t block, uint32_t section_mask);
+
+/**
+ * @brief Get the mask of ON and retention sections in selected RAM block.
+ *
+ * @param block RAM block index.
+ * @return Mask of sections state composed from @ref nrf_power_rampower_mask_t flags.
+ */
+__STATIC_INLINE uint32_t nrf_power_rampower_mask_get(uint8_t block);
+#endif /* NRF_POWER_HAS_RAMPOWER_REGS */
+
+#if NRF_POWER_HAS_VDDH
+/**
+ * @brief Enable of disable DCDC converter on VDDH
+ *
+ * @param enable Set true to enable or false to disable DCDC converter.
+ */
+__STATIC_INLINE void nrf_power_dcdcen_vddh_set(bool enable);
+
+/**
+ * @brief Get the state of DCDC converter on VDDH
+ *
+ * @retval true  Converter is enabled
+ * @retval false Converter is disabled
+ */
+__STATIC_INLINE bool nrf_power_dcdcen_vddh_get(void);
+
+/**
+ * @brief Get main supply status
+ *
+ * @return Current main supply status
+ */
+__STATIC_INLINE nrf_power_mainregstatus_t nrf_power_mainregstatus_get(void);
+#endif /* NRF_POWER_HAS_VDDH */
+
+#if NRF_POWER_HAS_USBREG
+/**
+ *
+ * @return Get the whole USBREGSTATUS register
+ *
+ * @return The USBREGSTATUS register value.
+ *         Use @ref nrf_power_usbregstatus_mask_t values for bit masking.
+ *
+ * @sa nrf_power_usbregstatus_vbusdet_get
+ * @sa nrf_power_usbregstatus_outrdy_get
+ */
+__STATIC_INLINE uint32_t nrf_power_usbregstatus_get(void);
+
+/**
+ * @brief VBUS input detection status
+ *
+ * USBDETECTED and USBREMOVED events are derived from this information
+ *
+ * @retval false VBUS voltage below valid threshold
+ * @retval true  VBUS voltage above valid threshold
+ *
+ * @sa nrf_power_usbregstatus_get
+ */
+__STATIC_INLINE bool nrf_power_usbregstatus_vbusdet_get(void);
+
+/**
+ * @brief USB supply output settling time elapsed
+ *
+ * @retval false USBREG output settling time not elapsed
+ * @retval true  USBREG output settling time elapsed
+ *               (same information as USBPWRRDY event)
+ *
+ * @sa nrf_power_usbregstatus_get
+ */
+__STATIC_INLINE bool nrf_power_usbregstatus_outrdy_get(void);
+#endif /* NRF_POWER_HAS_USBREG */
+
+/** @} */
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE uint32_t nrf_power_resetreas_get(void)
+{
+    return NRF_POWER->RESETREAS;
+}
+
+__STATIC_INLINE void nrf_power_resetreas_clear(uint32_t mask)
+{
+    NRF_POWER->RESETREAS = mask;
+}
+
+__STATIC_INLINE uint32_t nrf_power_ramstatus_get(void)
+{
+    return NRF_POWER->RAMSTATUS;
+}
+
+__STATIC_INLINE void nrf_power_system_off(void)
+{
+    NRF_POWER->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter;
+    /* Solution for simulated System OFF in debug mode.
+     * Also, because dead loop is placed here, we do not need to implement
+     * any barriers here. */
+    while(true)
+    {
+        /* Intentionally empty - we would be here only in debug mode */
+    }
+}
+
+__STATIC_INLINE void nrf_power_pofcon_set(bool enabled, nrf_power_pof_thr_t thr)
+{
+    ASSERT(thr == (thr & (POWER_POFCON_THRESHOLD_Msk >> POWER_POFCON_THRESHOLD_Pos)));
+    NRF_POWER->POFCON = (((uint32_t)thr) << POWER_POFCON_THRESHOLD_Pos) |
+        (enabled ?
+        (POWER_POFCON_POF_Enabled << POWER_POFCON_POF_Pos)
+        :
+        (POWER_POFCON_POF_Disabled << POWER_POFCON_POF_Pos));
+}
+
+__STATIC_INLINE nrf_power_pof_thr_t nrf_power_pofcon_get(bool * p_enabled)
+{
+    uint32_t pofcon = NRF_POWER->POFCON;
+    if(NULL != p_enabled)
+    {
+        (*p_enabled) = ((pofcon & POWER_POFCON_POF_Msk) >> POWER_POFCON_POF_Pos)
+            == POWER_POFCON_POF_Enabled;
+    }
+    return (nrf_power_pof_thr_t)((pofcon & POWER_POFCON_THRESHOLD_Msk) >>
+        POWER_POFCON_THRESHOLD_Pos);
+}
+
+#if NRF_POWER_HAS_VDDH
+__STATIC_INLINE void nrf_power_pofcon_vddh_set(nrf_power_pof_thrvddh_t thr)
+{
+    ASSERT(thr == (thr & (POWER_POFCON_THRESHOLDVDDH_Msk >> POWER_POFCON_THRESHOLDVDDH_Pos)));
+    uint32_t pofcon = NRF_POWER->POFCON;
+    pofcon &= ~POWER_POFCON_THRESHOLDVDDH_Msk;
+    pofcon |= (((uint32_t)thr) << POWER_POFCON_THRESHOLDVDDH_Pos);
+    NRF_POWER->POFCON = pofcon;
+}
+
+__STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(void)
+{
+    return (nrf_power_pof_thrvddh_t)((NRF_POWER->POFCON &
+        POWER_POFCON_THRESHOLDVDDH_Msk) >> POWER_POFCON_THRESHOLDVDDH_Pos);
+}
+#endif /* NRF_POWER_HAS_VDDH */
+
+__STATIC_INLINE void nrf_power_gpregret_set(uint8_t val)
+{
+    NRF_POWER->GPREGRET = val;
+}
+
+__STATIC_INLINE uint8_t nrf_power_gpregret_get(void)
+{
+    return NRF_POWER->GPREGRET;
+}
+
+#if defined(POWER_GPREGRET2_GPREGRET_Msk) || defined(__SDK_DOXYGEN__)
+void nrf_power_gpregret2_set(uint8_t val)
+{
+    NRF_POWER->GPREGRET2 = val;
+}
+
+__STATIC_INLINE uint8_t nrf_power_gpregret2_get(void)
+{
+    return NRF_POWER->GPREGRET2;
+}
+#endif
+
+__STATIC_INLINE void nrf_power_dcdcen_set(bool enable)
+{
+#if NRF_POWER_HAS_VDDH
+    NRF_POWER->DCDCEN = (enable ?
+        POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
+            POWER_DCDCEN_DCDCEN_Pos;
+#else
+    NRF_POWER->DCDCEN = (enable ?
+        POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
+            POWER_DCDCEN_DCDCEN_Pos;
+#endif
+}
+
+__STATIC_INLINE bool nrf_power_dcdcen_get(void)
+{
+#if NRF_POWER_HAS_VDDH
+    return (NRF_POWER->DCDCEN & POWER_DCDCEN_DCDCEN_Msk)
+            ==
+           (POWER_DCDCEN_DCDCEN_Enabled << POWER_DCDCEN_DCDCEN_Pos);
+#else
+    return (NRF_POWER->DCDCEN & POWER_DCDCEN_DCDCEN_Msk)
+            ==
+           (POWER_DCDCEN_DCDCEN_Enabled << POWER_DCDCEN_DCDCEN_Pos);
+#endif
+}
+
+#if NRF_POWER_HAS_RAMPOWER_REGS
+__STATIC_INLINE void nrf_power_rampower_mask_on(uint8_t block, uint32_t section_mask)
+{
+    ASSERT(block < ARRAY_SIZE(NRF_POWER->RAM));
+    NRF_POWER->RAM[block].POWERSET = section_mask;
+}
+
+__STATIC_INLINE void nrf_power_rampower_mask_off(uint8_t block, uint32_t section_mask)
+{
+    ASSERT(block < ARRAY_SIZE(NRF_POWER->RAM));
+    NRF_POWER->RAM[block].POWERCLR = section_mask;
+}
+
+__STATIC_INLINE uint32_t nrf_power_rampower_mask_get(uint8_t block)
+{
+    ASSERT(block < ARRAY_SIZE(NRF_POWER->RAM));
+    return NRF_POWER->RAM[block].POWER;
+}
+#endif /* NRF_POWER_HAS_RAMPOWER_REGS */
+
+#if NRF_POWER_HAS_VDDH
+__STATIC_INLINE void nrf_power_dcdcen_vddh_set(bool enable)
+{
+    NRF_POWER->DCDCEN0 = (enable ?
+        POWER_DCDCEN0_DCDCEN_Enabled : POWER_DCDCEN0_DCDCEN_Disabled) <<
+            POWER_DCDCEN0_DCDCEN_Pos;
+}
+
+bool nrf_power_dcdcen_vddh_get(void)
+{
+    return (NRF_POWER->DCDCEN0 & POWER_DCDCEN0_DCDCEN_Msk)
+            ==
+           (POWER_DCDCEN0_DCDCEN_Enabled << POWER_DCDCEN0_DCDCEN_Pos);
+}
+
+nrf_power_mainregstatus_t nrf_power_mainregstatus_get(void)
+{
+    return (nrf_power_mainregstatus_t)(((NRF_POWER->MAINREGSTATUS) &
+        POWER_MAINREGSTATUS_MAINREGSTATUS_Msk) >>
+        POWER_MAINREGSTATUS_MAINREGSTATUS_Pos);
+}
+#endif /* NRF_POWER_HAS_VDDH */
+
+#if NRF_POWER_HAS_USBREG
+__STATIC_INLINE uint32_t nrf_power_usbregstatus_get(void)
+{
+    return NRF_POWER->USBREGSTATUS;
+}
+
+__STATIC_INLINE bool nrf_power_usbregstatus_vbusdet_get(void)
+{
+    return (nrf_power_usbregstatus_get() &
+        NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK) != 0;
+}
+
+__STATIC_INLINE bool nrf_power_usbregstatus_outrdy_get(void)
+{
+    return (nrf_power_usbregstatus_get() &
+        NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK) != 0;
+}
+#endif /* NRF_POWER_HAS_USBREG */
+
+#endif /* SUPPRESS_INLINE_IMPLEMENTATION */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF_POWER_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_ppi.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,438 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_PPI_H__
+#define NRF_PPI_H__
+
+#include <stddef.h>
+#include "nrf.h"
+#include "nrf_peripherals.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrf_ppi_hal PPI HAL
+ * @{
+ * @ingroup nrf_ppi
+ * @brief Hardware access layer for setting up Programmable Peripheral Interconnect (PPI) channels.
+ */
+
+#define NRF_PPI_TASK_SET    (1UL)
+
+/**
+ * @enum nrf_ppi_channel_t
+ * @brief PPI channels.
+ */
+typedef enum
+{
+    NRF_PPI_CHANNEL0  = PPI_CHEN_CH0_Pos,  /**< Channel 0. */
+    NRF_PPI_CHANNEL1  = PPI_CHEN_CH1_Pos,  /**< Channel 1. */
+    NRF_PPI_CHANNEL2  = PPI_CHEN_CH2_Pos,  /**< Channel 2. */
+    NRF_PPI_CHANNEL3  = PPI_CHEN_CH3_Pos,  /**< Channel 3. */
+    NRF_PPI_CHANNEL4  = PPI_CHEN_CH4_Pos,  /**< Channel 4. */
+    NRF_PPI_CHANNEL5  = PPI_CHEN_CH5_Pos,  /**< Channel 5. */
+    NRF_PPI_CHANNEL6  = PPI_CHEN_CH6_Pos,  /**< Channel 6. */
+    NRF_PPI_CHANNEL7  = PPI_CHEN_CH7_Pos,  /**< Channel 7. */
+    NRF_PPI_CHANNEL8  = PPI_CHEN_CH8_Pos,  /**< Channel 8. */
+    NRF_PPI_CHANNEL9  = PPI_CHEN_CH9_Pos,  /**< Channel 9. */
+    NRF_PPI_CHANNEL10 = PPI_CHEN_CH10_Pos, /**< Channel 10. */
+    NRF_PPI_CHANNEL11 = PPI_CHEN_CH11_Pos, /**< Channel 11. */
+    NRF_PPI_CHANNEL12 = PPI_CHEN_CH12_Pos, /**< Channel 12. */
+    NRF_PPI_CHANNEL13 = PPI_CHEN_CH13_Pos, /**< Channel 13. */
+    NRF_PPI_CHANNEL14 = PPI_CHEN_CH14_Pos, /**< Channel 14. */
+    NRF_PPI_CHANNEL15 = PPI_CHEN_CH15_Pos, /**< Channel 15. */
+#if (PPI_CH_NUM > 16) || defined(__SDK_DOXYGEN__)
+    NRF_PPI_CHANNEL16 = PPI_CHEN_CH16_Pos, /**< Channel 16. */
+    NRF_PPI_CHANNEL17 = PPI_CHEN_CH17_Pos, /**< Channel 17. */
+    NRF_PPI_CHANNEL18 = PPI_CHEN_CH18_Pos, /**< Channel 18. */
+    NRF_PPI_CHANNEL19 = PPI_CHEN_CH19_Pos, /**< Channel 19. */
+#endif
+    NRF_PPI_CHANNEL20 = PPI_CHEN_CH20_Pos, /**< Channel 20. */
+    NRF_PPI_CHANNEL21 = PPI_CHEN_CH21_Pos, /**< Channel 21. */
+    NRF_PPI_CHANNEL22 = PPI_CHEN_CH22_Pos, /**< Channel 22. */
+    NRF_PPI_CHANNEL23 = PPI_CHEN_CH23_Pos, /**< Channel 23. */
+    NRF_PPI_CHANNEL24 = PPI_CHEN_CH24_Pos, /**< Channel 24. */
+    NRF_PPI_CHANNEL25 = PPI_CHEN_CH25_Pos, /**< Channel 25. */
+    NRF_PPI_CHANNEL26 = PPI_CHEN_CH26_Pos, /**< Channel 26. */
+    NRF_PPI_CHANNEL27 = PPI_CHEN_CH27_Pos, /**< Channel 27. */
+    NRF_PPI_CHANNEL28 = PPI_CHEN_CH28_Pos, /**< Channel 28. */
+    NRF_PPI_CHANNEL29 = PPI_CHEN_CH29_Pos, /**< Channel 29. */
+    NRF_PPI_CHANNEL30 = PPI_CHEN_CH30_Pos, /**< Channel 30. */
+    NRF_PPI_CHANNEL31 = PPI_CHEN_CH31_Pos  /**< Channel 31. */
+} nrf_ppi_channel_t;
+
+/**
+ * @enum nrf_ppi_channel_group_t
+ * @brief PPI channel groups.
+ */
+typedef enum
+{
+    NRF_PPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */
+    NRF_PPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */
+    NRF_PPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */
+    NRF_PPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */
+#if (PPI_GROUP_NUM > 4) || defined(__SDK_DOXYGEN__)
+    NRF_PPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */
+    NRF_PPI_CHANNEL_GROUP5 = 5  /**< Channel group 5. */
+#endif
+} nrf_ppi_channel_group_t;
+
+/**
+ * @enum nrf_ppi_channel_include_t
+ * @brief Definition of which PPI channels belong to a group.
+ */
+typedef enum
+{
+    NRF_PPI_CHANNEL_EXCLUDE = PPI_CHG_CH0_Excluded, /**< Channel excluded from a group. */
+    NRF_PPI_CHANNEL_INCLUDE = PPI_CHG_CH0_Included  /**< Channel included in a group. */
+} nrf_ppi_channel_include_t;
+
+/**
+ * @enum nrf_ppi_channel_enable_t
+ * @brief Definition if a PPI channel is enabled.
+ */
+typedef enum
+{
+    NRF_PPI_CHANNEL_DISABLED = PPI_CHEN_CH0_Disabled, /**< Channel disabled. */
+    NRF_PPI_CHANNEL_ENABLED  = PPI_CHEN_CH0_Enabled   /**< Channel enabled. */
+} nrf_ppi_channel_enable_t;
+
+/**
+ * @enum nrf_ppi_task_t
+ * @brief PPI tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30 -esym(628,__INTADDR__)*/
+    NRF_PPI_TASK_CHG0_EN  = offsetof(NRF_PPI_Type, TASKS_CHG[0].EN),  /**< Task for enabling channel group 0 */
+    NRF_PPI_TASK_CHG0_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[0].DIS), /**< Task for disabling channel group 0 */
+    NRF_PPI_TASK_CHG1_EN  = offsetof(NRF_PPI_Type, TASKS_CHG[1].EN),  /**< Task for enabling channel group 1 */
+    NRF_PPI_TASK_CHG1_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[1].DIS), /**< Task for disabling channel group 1 */
+    NRF_PPI_TASK_CHG2_EN  = offsetof(NRF_PPI_Type, TASKS_CHG[2].EN),  /**< Task for enabling channel group 2 */
+    NRF_PPI_TASK_CHG2_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[2].DIS), /**< Task for disabling channel group 2 */
+    NRF_PPI_TASK_CHG3_EN  = offsetof(NRF_PPI_Type, TASKS_CHG[3].EN),  /**< Task for enabling channel group 3 */
+    NRF_PPI_TASK_CHG3_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[3].DIS), /**< Task for disabling channel group 3 */
+#if (PPI_GROUP_NUM > 4) || defined(__SDK_DOXYGEN__)
+    NRF_PPI_TASK_CHG4_EN  = offsetof(NRF_PPI_Type, TASKS_CHG[4].EN),  /**< Task for enabling channel group 4 */
+    NRF_PPI_TASK_CHG4_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[4].DIS), /**< Task for disabling channel group 4 */
+    NRF_PPI_TASK_CHG5_EN  = offsetof(NRF_PPI_Type, TASKS_CHG[5].EN),  /**< Task for enabling channel group 5 */
+    NRF_PPI_TASK_CHG5_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[5].DIS)  /**< Task for disabling channel group 5 */
+#endif
+    /*lint -restore*/
+} nrf_ppi_task_t;
+
+/**
+ * @brief Function for enabling a given PPI channel.
+ *
+ * @details This function enables only one channel.
+ *
+ * @param[in] channel Channel to enable.
+ *
+ *  */
+__STATIC_INLINE void nrf_ppi_channel_enable(nrf_ppi_channel_t channel)
+{
+    NRF_PPI->CHENSET = PPI_CHENSET_CH0_Set << ((uint32_t) channel);
+}
+
+
+/**
+ * @brief Function for disabling a given PPI channel.
+ *
+ * @details This function disables only one channel.
+ *
+ * @param[in] channel Channel to disable.
+ */
+__STATIC_INLINE void nrf_ppi_channel_disable(nrf_ppi_channel_t channel)
+{
+    NRF_PPI->CHENCLR = PPI_CHENCLR_CH0_Clear << ((uint32_t) channel);
+}
+
+
+/**
+ * @brief Function for checking if a given PPI channel is enabled.
+ *
+ * @details This function checks only one channel.
+ *
+ * @param[in] channel Channel to check.
+ *
+ * @retval     NRF_PPI_CHANNEL_ENABLED     If the channel is enabled.
+ * @retval     NRF_PPI_CHANNEL_DISABLED    If the channel is not enabled.
+ *
+ */
+__STATIC_INLINE nrf_ppi_channel_enable_t nrf_ppi_channel_enable_get(nrf_ppi_channel_t channel)
+{
+    if (NRF_PPI->CHEN & (PPI_CHEN_CH0_Msk << ((uint32_t) channel)))
+    {
+        return NRF_PPI_CHANNEL_ENABLED;
+    }
+    else
+    {
+        return NRF_PPI_CHANNEL_DISABLED;
+    }
+}
+
+
+/**
+ * @brief Function for disabling all PPI channels.
+ */
+__STATIC_INLINE void nrf_ppi_channel_disable_all(void)
+{
+    NRF_PPI->CHENCLR = ((uint32_t)0xFFFFFFFFuL);
+}
+
+/**
+ * @brief Function for disabling multiple PPI channels.
+ *
+ * @param[in] mask Channel mask.
+ */
+__STATIC_INLINE void nrf_ppi_channels_disable(uint32_t mask)
+{
+    NRF_PPI->CHENCLR = mask;
+}
+
+/**
+ * @brief Function for setting up event and task endpoints for a given PPI channel.
+ *
+ * @param[in] eep Event register address.
+ *
+ * @param[in] tep Task register address.
+ *
+ * @param[in] channel Channel to which the given endpoints are assigned.
+ */
+__STATIC_INLINE void nrf_ppi_channel_endpoint_setup(nrf_ppi_channel_t channel,
+                                                    uint32_t          eep,
+                                                    uint32_t          tep)
+{
+    NRF_PPI->CH[(uint32_t) channel].EEP = eep;
+    NRF_PPI->CH[(uint32_t) channel].TEP = tep;
+}
+
+#if defined(PPI_FEATURE_FORKS_PRESENT) || defined(__SDK_DOXYGEN__)
+/**
+ * @brief Function for setting up task endpoint for a given PPI fork.
+ *
+ * @param[in] fork_tep Task register address.
+ *
+ * @param[in] channel Channel to which the given fork endpoint is assigned.
+ */
+__STATIC_INLINE void nrf_ppi_fork_endpoint_setup(nrf_ppi_channel_t channel,
+                                                 uint32_t          fork_tep)
+{
+    NRF_PPI->FORK[(uint32_t) channel].TEP = fork_tep;
+}
+
+/**
+ * @brief Function for setting up event and task endpoints for a given PPI channel and fork.
+ *
+ * @param[in] eep Event register address.
+ *
+ * @param[in] tep Task register address.
+ *
+ * @param[in] fork_tep Fork task register address (register value).
+ *
+ * @param[in] channel Channel to which the given endpoints are assigned.
+ */
+__STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(nrf_ppi_channel_t channel,
+                                                             uint32_t          eep,
+                                                             uint32_t          tep,
+                                                             uint32_t          fork_tep)
+{
+    nrf_ppi_channel_endpoint_setup(channel, eep, tep);
+    nrf_ppi_fork_endpoint_setup(channel, fork_tep);
+}
+#endif
+
+/**
+ * @brief Function for including a PPI channel in a channel group.
+ *
+ * @details This function adds only one channel to the group.
+ *
+ * @param[in] channel       Channel to be included in the group.
+ *
+ * @param[in] channel_group Channel group.
+ *
+ */
+__STATIC_INLINE void nrf_ppi_channel_include_in_group(nrf_ppi_channel_t       channel,
+                                                      nrf_ppi_channel_group_t channel_group)
+{
+    NRF_PPI->CHG[(uint32_t) channel_group] =
+        NRF_PPI->CHG[(uint32_t) channel_group] | (PPI_CHG_CH0_Included << ((uint32_t)  channel));
+}
+
+/**
+ * @brief Function for including multiple PPI channels in a channel group.
+ *
+ * @details This function adds all specified channels to the group.
+ *
+ * @param[in] channel_mask  Channels to be included in the group.
+ *
+ * @param[in] channel_group Channel group.
+ *
+ */
+__STATIC_INLINE void nrf_ppi_channels_include_in_group(uint32_t                channel_mask,
+                                                       nrf_ppi_channel_group_t channel_group)
+{
+    NRF_PPI->CHG[(uint32_t) channel_group] =
+        NRF_PPI->CHG[(uint32_t) channel_group] | (channel_mask);
+}
+
+
+/**
+ * @brief Function for removing a PPI channel from a channel group.
+ *
+ * @details This function removes only one channel from the group.
+ *
+ * @param[in] channel       Channel to be removed from the group.
+ *
+ * @param[in] channel_group Channel group.
+ */
+__STATIC_INLINE void nrf_ppi_channel_remove_from_group(nrf_ppi_channel_t       channel,
+                                                       nrf_ppi_channel_group_t channel_group)
+{
+    NRF_PPI->CHG[(uint32_t) channel_group] =
+        NRF_PPI->CHG[(uint32_t) channel_group] & ~(PPI_CHG_CH0_Included << ((uint32_t) channel));
+}
+
+/**
+ * @brief Function for removing multiple PPI channels from a channel group.
+ *
+ * @details This function removes all specified channels from the group.
+ *
+ * @param[in] channel_mask  Channels to be removed from the group.
+ *
+ * @param[in] channel_group Channel group.
+ */
+__STATIC_INLINE void nrf_ppi_channels_remove_from_group(uint32_t                channel_mask,
+                                                        nrf_ppi_channel_group_t channel_group)
+{
+    NRF_PPI->CHG[(uint32_t) channel_group] =
+        NRF_PPI->CHG[(uint32_t) channel_group] & ~(channel_mask);
+}
+
+
+/**
+ * @brief Function for removing all PPI channels from a channel group.
+ *
+ * @param[in] group Channel group.
+ *
+ */
+__STATIC_INLINE void nrf_ppi_channel_group_clear(nrf_ppi_channel_group_t group)
+{
+    NRF_PPI->CHG[(uint32_t) group] = 0;
+}
+
+
+/**
+ * @brief Function for enabling a channel group.
+ *
+ * @param[in] group Channel group.
+ *
+ */
+__STATIC_INLINE void nrf_ppi_group_enable(nrf_ppi_channel_group_t group)
+{
+    NRF_PPI->TASKS_CHG[(uint32_t) group].EN = NRF_PPI_TASK_SET;
+}
+
+
+/**
+ * @brief Function for disabling a channel group.
+ *
+ * @param[in] group Channel group.
+ *
+ */
+__STATIC_INLINE void nrf_ppi_group_disable(nrf_ppi_channel_group_t group)
+{
+    NRF_PPI->TASKS_CHG[(uint32_t) group].DIS = NRF_PPI_TASK_SET;
+}
+
+
+/**
+ * @brief Function for setting a PPI task.
+ *
+ * @param[in] ppi_task PPI task to set.
+ */
+__STATIC_INLINE void nrf_ppi_task_trigger(nrf_ppi_task_t ppi_task)
+{
+    *((volatile uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task)) = NRF_PPI_TASK_SET;
+}
+
+
+/**
+ * @brief Function for returning the address of a specific PPI task register.
+ *
+ * @param[in] ppi_task PPI task.
+ */
+__STATIC_INLINE uint32_t * nrf_ppi_task_address_get(nrf_ppi_task_t ppi_task)
+{
+    return (uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task);
+}
+
+/**
+ * @brief Function for returning the PPI enable task address of a specific group.
+ *
+ * @param[in] group  PPI group.
+ */
+__STATIC_INLINE uint32_t * nrf_ppi_task_group_enable_address_get(nrf_ppi_channel_group_t group)
+{
+    return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].EN;
+}
+
+/**
+ * @brief Function for returning the PPI disable task address of a specific group.
+ *
+ * @param[in] group  PPI group.
+ */
+__STATIC_INLINE uint32_t * nrf_ppi_task_group_disable_address_get(nrf_ppi_channel_group_t group)
+{
+    return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].DIS;
+}
+
+
+/**
+ *@}
+ **/
+
+/*lint --flb "Leave library region" */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_PPI_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_pwm.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,700 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @defgroup nrf_pwm_hal PWM HAL
+ * @{
+ * @ingroup nrf_pwm
+ *
+ * @brief @tagAPI52 Hardware access layer for managing the Pulse Width Modulation (PWM)
+ *        peripheral.
+ */
+
+#ifndef NRF_PWM_H__
+#define NRF_PWM_H__
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "nrf.h"
+#include "nrf_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @brief This value can be provided as a parameter for the @ref nrf_pwm_pins_set
+ *        function call to specify that a given output channel shall not be
+ *        connected to a physical pin.
+ */
+#define NRF_PWM_PIN_NOT_CONNECTED   0xFFFFFFFF
+
+/**
+ * @brief Number of channels in each Pointer to the peripheral registers structure.
+ */
+#define NRF_PWM_CHANNEL_COUNT   4
+
+
+/**
+ * @brief PWM tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_PWM_TASK_STOP      = offsetof(NRF_PWM_Type, TASKS_STOP),        ///< Stops PWM pulse generation on all channels at the end of the current PWM period, and stops the sequence playback.
+    NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[0]), ///< Starts playback of sequence 0.
+    NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[1]), ///< Starts playback of sequence 1.
+    NRF_PWM_TASK_NEXTSTEP  = offsetof(NRF_PWM_Type, TASKS_NEXTSTEP)     ///< Steps by one value in the current sequence if the decoder is set to @ref NRF_PWM_STEP_TRIGGERED mode.
+    /*lint -restore*/
+} nrf_pwm_task_t;
+
+/**
+ * @brief PWM events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_PWM_EVENT_STOPPED      = offsetof(NRF_PWM_Type, EVENTS_STOPPED),       ///< Response to STOP task, emitted when PWM pulses are no longer generated.
+    NRF_PWM_EVENT_SEQSTARTED0  = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[0]), ///< First PWM period started on sequence 0.
+    NRF_PWM_EVENT_SEQSTARTED1  = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[1]), ///< First PWM period started on sequence 1.
+    NRF_PWM_EVENT_SEQEND0      = offsetof(NRF_PWM_Type, EVENTS_SEQEND[0]),     ///< Emitted at the end of every sequence 0 when its last value has been read from RAM.
+    NRF_PWM_EVENT_SEQEND1      = offsetof(NRF_PWM_Type, EVENTS_SEQEND[1]),     ///< Emitted at the end of every sequence 1 when its last value has been read from RAM.
+    NRF_PWM_EVENT_PWMPERIODEND = offsetof(NRF_PWM_Type, EVENTS_PWMPERIODEND),  ///< Emitted at the end of each PWM period.
+    NRF_PWM_EVENT_LOOPSDONE    = offsetof(NRF_PWM_Type, EVENTS_LOOPSDONE)      ///< Concatenated sequences have been played the requested number of times.
+    /*lint -restore*/
+} nrf_pwm_event_t;
+
+/**
+ * @brief PWM interrupts.
+ */
+typedef enum
+{
+    NRF_PWM_INT_STOPPED_MASK      = PWM_INTENSET_STOPPED_Msk,      ///< Interrupt on STOPPED event.
+    NRF_PWM_INT_SEQSTARTED0_MASK  = PWM_INTENSET_SEQSTARTED0_Msk,  ///< Interrupt on SEQSTARTED[0] event.
+    NRF_PWM_INT_SEQSTARTED1_MASK  = PWM_INTENSET_SEQSTARTED1_Msk,  ///< Interrupt on SEQSTARTED[1] event.
+    NRF_PWM_INT_SEQEND0_MASK      = PWM_INTENSET_SEQEND0_Msk,      ///< Interrupt on SEQEND[0] event.
+    NRF_PWM_INT_SEQEND1_MASK      = PWM_INTENSET_SEQEND1_Msk,      ///< Interrupt on SEQEND[1] event.
+    NRF_PWM_INT_PWMPERIODEND_MASK = PWM_INTENSET_PWMPERIODEND_Msk, ///< Interrupt on PWMPERIODEND event.
+    NRF_PWM_INT_LOOPSDONE_MASK    = PWM_INTENSET_LOOPSDONE_Msk     ///< Interrupt on LOOPSDONE event.
+} nrf_pwm_int_mask_t;
+
+/**
+ * @brief PWM shortcuts.
+ */
+typedef enum
+{
+    NRF_PWM_SHORT_SEQEND0_STOP_MASK        = PWM_SHORTS_SEQEND0_STOP_Msk,        ///< Shortcut between SEQEND[0] event and STOP task.
+    NRF_PWM_SHORT_SEQEND1_STOP_MASK        = PWM_SHORTS_SEQEND1_STOP_Msk,        ///< Shortcut between SEQEND[1] event and STOP task.
+    NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[0] task.
+    NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[1] task.
+    NRF_PWM_SHORT_LOOPSDONE_STOP_MASK      = PWM_SHORTS_LOOPSDONE_STOP_Msk       ///< Shortcut between LOOPSDONE event and STOP task.
+} nrf_pwm_short_mask_t;
+
+/**
+ * @brief PWM modes of operation.
+ */
+typedef enum
+{
+    NRF_PWM_MODE_UP          = PWM_MODE_UPDOWN_Up,        ///< Up counter (edge-aligned PWM duty cycle).
+    NRF_PWM_MODE_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown, ///< Up and down counter (center-aligned PWM duty cycle).
+} nrf_pwm_mode_t;
+
+/**
+ * @brief PWM base clock frequencies.
+ */
+typedef enum
+{
+    NRF_PWM_CLK_16MHz  = PWM_PRESCALER_PRESCALER_DIV_1,  ///< 16 MHz / 1 = 16 MHz.
+    NRF_PWM_CLK_8MHz   = PWM_PRESCALER_PRESCALER_DIV_2,  ///< 16 MHz / 2 = 8 MHz.
+    NRF_PWM_CLK_4MHz   = PWM_PRESCALER_PRESCALER_DIV_4,  ///< 16 MHz / 4 = 4 MHz.
+    NRF_PWM_CLK_2MHz   = PWM_PRESCALER_PRESCALER_DIV_8,  ///< 16 MHz / 8 = 2 MHz.
+    NRF_PWM_CLK_1MHz   = PWM_PRESCALER_PRESCALER_DIV_16, ///< 16 MHz / 16 = 1 MHz.
+    NRF_PWM_CLK_500kHz = PWM_PRESCALER_PRESCALER_DIV_32, ///< 16 MHz / 32 = 500 kHz.
+    NRF_PWM_CLK_250kHz = PWM_PRESCALER_PRESCALER_DIV_64, ///< 16 MHz / 64 = 250 kHz.
+    NRF_PWM_CLK_125kHz = PWM_PRESCALER_PRESCALER_DIV_128 ///< 16 MHz / 128 = 125 kHz.
+} nrf_pwm_clk_t;
+
+/**
+ * @brief PWM decoder load modes.
+ *
+ * The selected mode determines how the sequence data is read from RAM and
+ * spread to the compare registers.
+ */
+typedef enum
+{
+    NRF_PWM_LOAD_COMMON     = PWM_DECODER_LOAD_Common,     ///< 1st half word (16-bit) used in all PWM channels (0-3).
+    NRF_PWM_LOAD_GROUPED    = PWM_DECODER_LOAD_Grouped,    ///< 1st half word (16-bit) used in channels 0 and 1; 2nd word in channels 2 and 3.
+    NRF_PWM_LOAD_INDIVIDUAL = PWM_DECODER_LOAD_Individual, ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; 3rd in channel 2; 4th in channel 3.
+    NRF_PWM_LOAD_WAVE_FORM  = PWM_DECODER_LOAD_WaveForm    ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; ... ; 4th as the top value for the pulse generator counter.
+} nrf_pwm_dec_load_t;
+
+/**
+ * @brief PWM decoder next step modes.
+ *
+ * The selected mode determines when the next value from the active sequence
+ * is loaded.
+ */
+typedef enum
+{
+    NRF_PWM_STEP_AUTO      = PWM_DECODER_MODE_RefreshCount, ///< Automatically after the current value is played and repeated the requested number of times.
+    NRF_PWM_STEP_TRIGGERED = PWM_DECODER_MODE_NextStep      ///< When the @ref NRF_PWM_TASK_NEXTSTEP task is triggered.
+} nrf_pwm_dec_step_t;
+
+
+/**
+ * @brief Type used for defining duty cycle values for a sequence
+ *        loaded in @ref NRF_PWM_LOAD_COMMON mode.
+ */
+typedef uint16_t nrf_pwm_values_common_t;
+
+/**
+ * @brief Structure for defining duty cycle values for a sequence
+ *        loaded in @ref NRF_PWM_LOAD_GROUPED mode.
+ */
+typedef struct {
+    uint16_t group_0; ///< Duty cycle value for group 0 (channels 0 and 1).
+    uint16_t group_1; ///< Duty cycle value for group 1 (channels 2 and 3).
+} nrf_pwm_values_grouped_t;
+
+/**
+ * @brief Structure for defining duty cycle values for a sequence
+ *        loaded in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
+ */
+typedef struct
+{
+    uint16_t channel_0; ///< Duty cycle value for channel 0.
+    uint16_t channel_1; ///< Duty cycle value for channel 1.
+    uint16_t channel_2; ///< Duty cycle value for channel 2.
+    uint16_t channel_3; ///< Duty cycle value for channel 3.
+} nrf_pwm_values_individual_t;
+
+/**
+ * @brief Structure for defining duty cycle values for a sequence
+ *        loaded in @ref NRF_PWM_LOAD_WAVE_FORM mode.
+ */
+typedef struct {
+    uint16_t channel_0;   ///< Duty cycle value for channel 0.
+    uint16_t channel_1;   ///< Duty cycle value for channel 1.
+    uint16_t channel_2;   ///< Duty cycle value for channel 2.
+    uint16_t counter_top; ///< Top value for the pulse generator counter.
+} nrf_pwm_values_wave_form_t;
+
+/**
+ * @brief Union grouping pointers to arrays of duty cycle values applicable to
+ *        various loading modes.
+ */
+typedef union {
+    nrf_pwm_values_common_t     const * p_common;     ///< Pointer to be used in @ref NRF_PWM_LOAD_COMMON mode.
+    nrf_pwm_values_grouped_t    const * p_grouped;    ///< Pointer to be used in @ref NRF_PWM_LOAD_GROUPED mode.
+    nrf_pwm_values_individual_t const * p_individual; ///< Pointer to be used in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
+    nrf_pwm_values_wave_form_t  const * p_wave_form;  ///< Pointer to be used in @ref NRF_PWM_LOAD_WAVE_FORM mode.
+    uint16_t                    const * p_raw;        ///< Pointer providing raw access to the values.
+} nrf_pwm_values_t;
+
+/**
+ * @brief Structure for defining a sequence of PWM duty cycles.
+ *
+ * When the sequence is set (by a call to @ref nrf_pwm_sequence_set), the
+ * provided duty cycle values are not copied. The @p values pointer is stored
+ * in the peripheral's internal register, and the values are loaded from RAM
+ * during the sequence playback. Therefore, you must ensure that the values
+ * do not change before and during the sequence playback (for example,
+ * the values cannot be placed in a local variable that is allocated on stack).
+ * If the sequence is played in a loop and the values should be updated
+ * before the next iteration, it is safe to modify them when the corresponding
+ * event signaling the end of sequence occurs (@ref NRF_PWM_EVENT_SEQEND0
+ * or @ref NRF_PWM_EVENT_SEQEND1, respectively).
+ *
+ * @note The @p repeats and @p end_delay values (which are written to the
+ *       SEQ[n].REFRESH and SEQ[n].ENDDELAY registers in the peripheral,
+ *       respectively) are ignored at the end of a complex sequence
+ *       playback, indicated by the LOOPSDONE event.
+ *       See the @linkProductSpecification52 for more information.
+ */
+typedef struct
+{
+    nrf_pwm_values_t values; ///< Pointer to an array with duty cycle values. This array must be in Data RAM.
+                             /**< This field is defined as an union of pointers
+                              *   to provide a convenient way to define duty
+                              *   cycle values in various loading modes
+                              *   (see @ref nrf_pwm_dec_load_t).
+                              *   In each value, the most significant bit (15)
+                              *   determines the polarity of the output and the
+                              *   others (14-0) compose the 15-bit value to be
+                              *   compared with the pulse generator counter. */
+    uint16_t length;    ///< Number of 16-bit values in the array pointed by @p values.
+    uint32_t repeats;   ///< Number of times that each duty cycle should be repeated (after being played once). Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
+    uint32_t end_delay; ///< Additional time (in PWM periods) that the last duty cycle is to be kept after the sequence is played. Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
+} nrf_pwm_sequence_t;
+
+/**
+ * @brief Helper macro for calculating the number of 16-bit values in specified
+ *        array of duty cycle values.
+ */
+#define NRF_PWM_VALUES_LENGTH(array)  (sizeof(array) / sizeof(uint16_t))
+
+
+/**
+ * @brief Function for activating a specific PWM task.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] task  Task to activate.
+ */
+__STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
+                                          nrf_pwm_task_t task);
+
+/**
+ * @brief Function for getting the address of a specific PWM task register.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] task  Requested task.
+ *
+ * @return Address of the specified task register.
+ */
+__STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
+                                                  nrf_pwm_task_t task);
+
+/**
+ * @brief Function for clearing a specific PWM event.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] event Event to clear.
+ */
+__STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
+                                         nrf_pwm_event_t event);
+
+/**
+ * @brief Function for checking the state of a specific PWM event.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] event Event to check.
+ *
+ * @retval true  If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
+                                         nrf_pwm_event_t event);
+
+/**
+ * @brief Function for getting the address of a specific PWM event register.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] event Requested event.
+ *
+ * @return Address of the specified event register.
+ */
+__STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
+                                                   nrf_pwm_event_t event);
+
+/**
+ * @brief Function for enabling specified shortcuts.
+ *
+ * @param[in] p_reg           Pointer to the peripheral registers structure.
+ * @param[in] pwm_shorts_mask Shortcuts to enable.
+ */
+__STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,
+                                           uint32_t pwm_shorts_mask);
+
+/**
+ * @brief Function for disabling specified shortcuts.
+ *
+ * @param[in] p_reg           Pointer to the peripheral registers structure.
+ * @param[in] pwm_shorts_mask Shortcuts to disable.
+ */
+__STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,
+                                            uint32_t pwm_shorts_mask);
+
+/**
+ * @brief Function for setting the configuration of PWM shortcuts.
+ *
+ * @param[in] p_reg           Pointer to the peripheral registers structure.
+ * @param[in] pwm_shorts_mask Shortcuts configuration to set.
+ */
+__STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,
+                                        uint32_t pwm_shorts_mask);
+
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] p_reg        Pointer to the peripheral registers structure.
+ * @param[in] pwm_int_mask Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg,
+                                        uint32_t pwm_int_mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] p_reg        Pointer to the peripheral registers structure.
+ * @param[in] pwm_int_mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg,
+                                         uint32_t pwm_int_mask);
+
+/**
+ * @brief Function for setting the configuration of PWM interrupts.
+ *
+ * @param[in] p_reg        Pointer to the peripheral registers structure.
+ * @param[in] pwm_int_mask Interrupts configuration to set.
+ */
+__STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg,
+                                     uint32_t pwm_int_mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param[in] pwm_int Interrupt to check.
+ *
+ * @retval true  If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,
+                                              nrf_pwm_int_mask_t pwm_int);
+
+/**
+ * @brief Function for enabling the PWM peripheral.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg);
+
+/**
+ * @brief Function for disabling the PWM peripheral.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg);
+
+/**
+ * @brief Function for assigning pins to PWM output channels.
+ *
+ * Usage of all PWM output channels is optional. If a given channel is not
+ * needed, pass the @ref NRF_PWM_PIN_NOT_CONNECTED value instead of its pin
+ * number.
+ *
+ * @param[in] p_reg    Pointer to the peripheral registers structure.
+ * @param[in] out_pins Array with pin numbers for individual PWM output channels.
+ */
+__STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
+                                      uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]);
+
+/**
+ * @brief Function for configuring the PWM peripheral.
+ *
+ * @param[in] p_reg      Pointer to the peripheral registers structure.
+ * @param[in] base_clock Base clock frequency.
+ * @param[in] mode       Operating mode of the pulse generator counter.
+ * @param[in] top_value  Value up to which the pulse generator counter counts.
+ */
+__STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
+                                       nrf_pwm_clk_t  base_clock,
+                                       nrf_pwm_mode_t mode,
+                                       uint16_t       top_value);
+
+/**
+ * @brief Function for defining a sequence of PWM duty cycles.
+ *
+ * @param[in] p_reg  Pointer to the peripheral registers structure.
+ * @param[in] seq_id Identifier of the sequence (0 or 1).
+ * @param[in] p_seq  Pointer to the sequence definition.
+ */
+__STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
+                                          uint8_t                    seq_id,
+                                          nrf_pwm_sequence_t const * p_seq);
+
+/**
+ * @brief Function for modifying the pointer to the duty cycle values
+ *        in the specified sequence.
+ *
+ * @param[in] p_reg    Pointer to the peripheral registers structure.
+ * @param[in] seq_id   Identifier of the sequence (0 or 1).
+ * @param[in] p_values Pointer to an array with duty cycle values.
+ */
+__STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
+                                         uint8_t          seq_id,
+                                         uint16_t const * p_values);
+
+/**
+ * @brief Function for modifying the total number of duty cycle values
+ *        in the specified sequence.
+ *
+ * @param[in] p_reg  Pointer to the peripheral registers structure.
+ * @param[in] seq_id Identifier of the sequence (0 or 1).
+ * @param[in] length Number of duty cycle values.
+ */
+__STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
+                                         uint8_t  seq_id,
+                                         uint16_t length);
+
+/**
+ * @brief Function for modifying the additional number of PWM periods spent
+ *        on each duty cycle value in the specified sequence.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param[in] seq_id  Identifier of the sequence (0 or 1).
+ * @param[in] refresh Number of additional PWM periods for each duty cycle value.
+ */
+__STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
+                                             uint8_t  seq_id,
+                                             uint32_t refresh);
+
+/**
+ * @brief Function for modifying the additional time added after the sequence
+ *        is played.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @param[in] seq_id    Identifier of the sequence (0 or 1).
+ * @param[in] end_delay Number of PWM periods added at the end of the sequence.
+ */
+__STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
+                                               uint8_t  seq_id,
+                                               uint32_t end_delay);
+
+/**
+ * @brief Function for setting the mode of loading sequence data from RAM
+ *        and advancing the sequence.
+ *
+ * @param[in] p_reg    Pointer to the peripheral registers structure.
+ * @param[in] dec_load Mode of loading sequence data from RAM.
+ * @param[in] dec_step Mode of advancing the active sequence.
+ */
+__STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
+                                         nrf_pwm_dec_load_t dec_load,
+                                         nrf_pwm_dec_step_t dec_step);
+
+/**
+ * @brief Function for setting the number of times the sequence playback
+ *        should be performed.
+ *
+ * This function applies to two-sequence playback (concatenated sequence 0 and 1).
+ * A single sequence can be played back only once.
+ *
+ * @param[in] p_reg      Pointer to the peripheral registers structure.
+ * @param[in] loop_count Number of times to perform the sequence playback.
+ */
+__STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg,
+                                      uint16_t loop_count);
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_reg,
+                                          nrf_pwm_task_t task)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_reg,
+                                                  nrf_pwm_task_t task)
+{
+    return ((uint32_t)p_reg + (uint32_t)task);
+}
+
+__STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
+                                         nrf_pwm_event_t event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
+    (void)dummy;
+#endif
+}
+
+__STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
+                                         nrf_pwm_event_t event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_reg,
+                                                   nrf_pwm_event_t event)
+{
+    return ((uint32_t)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_reg,
+                                           uint32_t pwm_shorts_mask)
+{
+    p_reg->SHORTS |= pwm_shorts_mask;
+}
+
+__STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_reg,
+                                            uint32_t pwm_shorts_mask)
+{
+    p_reg->SHORTS &= ~(pwm_shorts_mask);
+}
+
+__STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_reg,
+                                        uint32_t pwm_shorts_mask)
+{
+    p_reg->SHORTS = pwm_shorts_mask;
+}
+
+__STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_reg,
+                                        uint32_t pwm_int_mask)
+{
+    p_reg->INTENSET = pwm_int_mask;
+}
+
+__STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_reg,
+                                         uint32_t pwm_int_mask)
+{
+    p_reg->INTENCLR = pwm_int_mask;
+}
+
+__STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_reg,
+                                     uint32_t pwm_int_mask)
+{
+    p_reg->INTEN = pwm_int_mask;
+}
+
+__STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_reg,
+                                              nrf_pwm_int_mask_t pwm_int)
+{
+    return (bool)(p_reg->INTENSET & pwm_int);
+}
+
+__STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_reg)
+{
+    p_reg->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_reg)
+{
+    p_reg->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
+                                      uint32_t out_pins[NRF_PWM_CHANNEL_COUNT])
+{
+    uint8_t i;
+    for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i)
+    {
+        p_reg->PSEL.OUT[i] = out_pins[i];
+    }
+}
+
+__STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
+                                       nrf_pwm_clk_t  base_clock,
+                                       nrf_pwm_mode_t mode,
+                                       uint16_t       top_value)
+{
+    ASSERT(top_value <= PWM_COUNTERTOP_COUNTERTOP_Msk);
+
+    p_reg->PRESCALER  = base_clock;
+    p_reg->MODE       = mode;
+    p_reg->COUNTERTOP = top_value;
+}
+
+__STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg,
+                                          uint8_t                    seq_id,
+                                          nrf_pwm_sequence_t const * p_seq)
+{
+    ASSERT(p_seq != NULL);
+
+    nrf_pwm_seq_ptr_set(      p_reg, seq_id, p_seq->values.p_raw);
+    nrf_pwm_seq_cnt_set(      p_reg, seq_id, p_seq->length);
+    nrf_pwm_seq_refresh_set(  p_reg, seq_id, p_seq->repeats);
+    nrf_pwm_seq_end_delay_set(p_reg, seq_id, p_seq->end_delay);
+}
+
+__STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg,
+                                         uint8_t          seq_id,
+                                         uint16_t const * p_values)
+{
+    ASSERT(seq_id <= 1);
+    ASSERT(p_values != NULL);
+    p_reg->SEQ[seq_id].PTR = (uint32_t)p_values;
+}
+
+__STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg,
+                                         uint8_t  seq_id,
+                                         uint16_t length)
+{
+    ASSERT(seq_id <= 1);
+    ASSERT(length != 0);
+    ASSERT(length <= PWM_SEQ_CNT_CNT_Msk);
+    p_reg->SEQ[seq_id].CNT = length;
+}
+
+__STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg,
+                                             uint8_t  seq_id,
+                                             uint32_t refresh)
+{
+    ASSERT(seq_id <= 1);
+    ASSERT(refresh <= PWM_SEQ_REFRESH_CNT_Msk);
+    p_reg->SEQ[seq_id].REFRESH  = refresh;
+}
+
+__STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_reg,
+                                               uint8_t  seq_id,
+                                               uint32_t end_delay)
+{
+    ASSERT(seq_id <= 1);
+    ASSERT(end_delay <= PWM_SEQ_ENDDELAY_CNT_Msk);
+    p_reg->SEQ[seq_id].ENDDELAY = end_delay;
+}
+
+__STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_reg,
+                                         nrf_pwm_dec_load_t dec_load,
+                                         nrf_pwm_dec_step_t dec_step)
+{
+    p_reg->DECODER = ((uint32_t)dec_load << PWM_DECODER_LOAD_Pos) |
+                     ((uint32_t)dec_step << PWM_DECODER_MODE_Pos);
+}
+
+__STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_reg,
+                                      uint16_t loop_count)
+{
+    p_reg->LOOP = loop_count;
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_PWM_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_qdec.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,502 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef NRF_QDEC_H__
+#define NRF_QDEC_H__
+
+#include <stddef.h>
+#include "nrf_error.h"
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*lint ++flb "Enter library region" */
+
+/**
+ * @defgroup nrf_qdec_hal QDEC HAL
+ * @{
+ * @ingroup nrf_qdec
+ * @brief Hardware access layer for accessing the quadrature decoder (QDEC) peripheral.
+ */
+
+/**
+ * @enum nrf_qdec_task_t
+ * @brief QDEC tasks.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_QDEC_TASK_START      = offsetof(NRF_QDEC_Type, TASKS_START),     /**< Starting the quadrature decoder. */
+    NRF_QDEC_TASK_STOP       = offsetof(NRF_QDEC_Type, TASKS_STOP),      /**< Stopping the quadrature decoder. */
+    NRF_QDEC_TASK_READCLRACC = offsetof(NRF_QDEC_Type, TASKS_READCLRACC) /**< Reading and clearing ACC and ACCDBL registers. */
+} nrf_qdec_task_t;
+
+/**
+ * @enum nrf_qdec_event_t
+ * @brief QDEC events.
+ */
+typedef enum
+{
+    NRF_QDEC_EVENT_SAMPLERDY = offsetof(NRF_QDEC_Type, EVENTS_SAMPLERDY), /**< Event generated for every new sample.  */
+    NRF_QDEC_EVENT_REPORTRDY = offsetof(NRF_QDEC_Type, EVENTS_REPORTRDY), /**< Event generated for every new report.  */
+    NRF_QDEC_EVENT_ACCOF     = offsetof(NRF_QDEC_Type, EVENTS_ACCOF)      /**< Event generated for every accumulator overflow. */
+} nrf_qdec_event_t;                                                       /*lint -restore */
+
+/**
+ * @enum nrf_qdec_short_mask_t
+ * @brief QDEC shortcuts.
+ */
+typedef enum
+{
+    NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK = QDEC_SHORTS_REPORTRDY_READCLRACC_Msk, /**< Shortcut between REPORTRDY event and READCLRACC task.  */
+    NRF_QDEC_SHORT_SAMPLERDY_STOP_MASK       = QDEC_SHORTS_SAMPLERDY_STOP_Msk        /**< Shortcut between SAMPLERDY event and STOP task.  */
+} nrf_qdec_short_mask_t;
+
+/**
+ * @enum nrf_qdec_int_mask_t
+ * @brief QDEC interrupts.
+ */
+typedef enum
+{
+    NRF_QDEC_INT_SAMPLERDY_MASK = QDEC_INTENSET_SAMPLERDY_Msk, /**< Mask for enabling or disabling an interrupt on SAMPLERDY event.  */
+    NRF_QDEC_INT_REPORTRDY_MASK = QDEC_INTENSET_REPORTRDY_Msk, /**< Mask for enabling or disabling an interrupt on REPORTRDY event.  */
+    NRF_QDEC_INT_ACCOF_MASK     = QDEC_INTENSET_ACCOF_Msk      /**< Mask for enabling or disabling an interrupt on ACCOF event.  */
+} nrf_qdec_int_mask_t;
+
+/**
+ * @enum nrf_qdec_enable_t
+ * @brief States of the enable bit.
+ */
+typedef enum
+{
+    NRF_QDEC_DISABLE = QDEC_ENABLE_ENABLE_Disabled, /**< Mask for disabling the QDEC periperal. When disabled, the QDEC decoder pins are not active.  */
+    NRF_QDEC_ENABLE  = QDEC_ENABLE_ENABLE_Enabled   /**< Mask for enabling the QDEC periperal. When enabled, the QDEC pins are active. */
+} nrf_qdec_enable_t;
+
+
+/**
+ * @enum nrf_qdec_dbfen_t
+ * @brief States of the debounce filter enable bit.
+ */
+typedef enum
+{
+    NRF_QDEC_DBFEN_DISABLE = QDEC_DBFEN_DBFEN_Disabled, /**< Mask for disabling the debounce filter.  */
+    NRF_QDEC_DBFEN_ENABLE  = QDEC_DBFEN_DBFEN_Enabled   /**< Mask for enabling the debounce filter.  */
+} nrf_qdec_dbfen_t;
+
+/**
+ * @enum nrf_qdec_ledpol_t
+ * @brief Active LED polarity.
+ */
+typedef enum
+{
+    NRF_QDEC_LEPOL_ACTIVE_LOW  = QDEC_LEDPOL_LEDPOL_ActiveLow, /**< QDEC LED active on output pin low.  */
+    NRF_QDEC_LEPOL_ACTIVE_HIGH = QDEC_LEDPOL_LEDPOL_ActiveHigh /**< QDEC LED active on output pin high.  */
+} nrf_qdec_ledpol_t;
+
+
+/**
+ * @enum nrf_qdec_sampleper_t
+ * @brief Available sampling periods.
+ */
+typedef enum
+{
+    NRF_QDEC_SAMPLEPER_128us   = QDEC_SAMPLEPER_SAMPLEPER_128us,  /**< QDEC sampling period 128 microseconds.  */
+    NRF_QDEC_SAMPLEPER_256us   = QDEC_SAMPLEPER_SAMPLEPER_256us,  /**< QDEC sampling period 256 microseconds.  */
+    NRF_QDEC_SAMPLEPER_512us   = QDEC_SAMPLEPER_SAMPLEPER_512us,  /**< QDEC sampling period 512 microseconds.  */
+    NRF_QDEC_SAMPLEPER_1024us  = QDEC_SAMPLEPER_SAMPLEPER_1024us, /**< QDEC sampling period 1024 microseconds.  */
+    NRF_QDEC_SAMPLEPER_2048us  = QDEC_SAMPLEPER_SAMPLEPER_2048us, /**< QDEC sampling period 2048 microseconds.  */
+    NRF_QDEC_SAMPLEPER_4096us  = QDEC_SAMPLEPER_SAMPLEPER_4096us, /**< QDEC sampling period 4096 microseconds.  */
+    NRF_QDEC_SAMPLEPER_8192us  = QDEC_SAMPLEPER_SAMPLEPER_8192us, /**< QDEC sampling period 8192 microseconds.  */
+    NRF_QDEC_SAMPLEPER_16384us = QDEC_SAMPLEPER_SAMPLEPER_16384us /**< QDEC sampling period 16384 microseconds.  */
+} nrf_qdec_sampleper_t;
+
+/**
+ * @enum nrf_qdec_reportper_t
+ * @brief Available report periods.
+ */
+typedef enum
+{
+    NRF_QDEC_REPORTPER_10  = QDEC_REPORTPER_REPORTPER_10Smpl,  /**< QDEC report period 10 samples.  */
+    NRF_QDEC_REPORTPER_40  = QDEC_REPORTPER_REPORTPER_40Smpl,  /**< QDEC report period 40 samples.  */
+    NRF_QDEC_REPORTPER_80  = QDEC_REPORTPER_REPORTPER_80Smpl,  /**< QDEC report period 80 samples.  */
+    NRF_QDEC_REPORTPER_120 = QDEC_REPORTPER_REPORTPER_120Smpl, /**< QDEC report period 120 samples. */
+    NRF_QDEC_REPORTPER_160 = QDEC_REPORTPER_REPORTPER_160Smpl, /**< QDEC report period 160 samples. */
+    NRF_QDEC_REPORTPER_200 = QDEC_REPORTPER_REPORTPER_200Smpl, /**< QDEC report period 200 samples. */
+    NRF_QDEC_REPORTPER_240 = QDEC_REPORTPER_REPORTPER_240Smpl, /**< QDEC report period 240 samples. */
+    NRF_QDEC_REPORTPER_280 = QDEC_REPORTPER_REPORTPER_280Smpl, /**< QDEC report period 280 samples. */
+    NRF_QDEC_REPORTPER_DISABLED                                /**< QDEC reporting disabled.        */
+} nrf_qdec_reportper_t;
+
+/**
+ * @brief Function for enabling QDEC.
+ */
+__STATIC_INLINE void nrf_qdec_enable(void)
+{
+    NRF_QDEC->ENABLE = NRF_QDEC_ENABLE;
+}
+
+
+/**
+ * @brief Function for disabling QDEC.
+ */
+__STATIC_INLINE void nrf_qdec_disable(void)
+{
+    NRF_QDEC->ENABLE = NRF_QDEC_DISABLE;
+}
+
+
+/**
+ * @brief Function for returning the enable state of QDEC.
+ * @return State of the register.
+ */
+__STATIC_INLINE uint32_t nrf_qdec_enable_get(void)
+{
+    return NRF_QDEC->ENABLE;
+}
+
+
+/**
+ * @brief Function for enabling QDEC interrupts by mask.
+ * @param[in] qdec_int_mask Sources of the interrupts to enable.
+ */
+__STATIC_INLINE void nrf_qdec_int_enable(uint32_t qdec_int_mask)
+{
+    NRF_QDEC->INTENSET = qdec_int_mask; // writing 0 has no effect
+}
+
+
+/**
+ * @brief Function for disabling QDEC interrupts by mask.
+ * @param[in] qdec_int_mask Sources of the interrupts to disable.
+ *
+ */
+__STATIC_INLINE void nrf_qdec_int_disable(uint32_t qdec_int_mask)
+{
+    NRF_QDEC->INTENCLR = qdec_int_mask; // writing 0 has no effect
+}
+
+
+/**
+ * @brief Function for getting the enabled interrupts of the QDEC.
+ */
+__STATIC_INLINE uint32_t nrf_qdec_int_enable_check(nrf_qdec_int_mask_t qdec_int_mask)
+{
+    return NRF_QDEC->INTENSET & qdec_int_mask; // when read this register will return the value of INTEN.
+}
+
+
+/**
+ * @brief Function for enabling the debouncing filter of the QED.
+ */
+__STATIC_INLINE void nrf_qdec_dbfen_enable(void)
+{
+    NRF_QDEC->DBFEN = NRF_QDEC_DBFEN_ENABLE;
+}
+
+
+/**
+ * @brief Function for disabling the debouncing filter of the QED.
+ */
+__STATIC_INLINE void nrf_qdec_dbfen_disable(void)
+{
+    NRF_QDEC->DBFEN = NRF_QDEC_DBFEN_DISABLE;
+}
+
+
+/**
+ * @brief Function for getting the state of the QDEC's debouncing filter.
+ * @retval NRF_QDEC_DBFEN_DISABLE If the debouncing filter is disabled.
+ * @retval NRF_QDEC_DBFEN_ENABLE If the debouncing filter is enabled.
+ */
+__STATIC_INLINE uint32_t nrf_qdec_dbfen_get(void)
+{
+    return NRF_QDEC->DBFEN;
+}
+
+
+/**
+ * @brief Function for assigning QDEC pins.
+ * @param[in] psela   Pin number.
+ * @param[in] pselb   Pin number.
+ * @param[in] pselled Pin number.
+ */
+__STATIC_INLINE void nrf_qdec_pio_assign( uint32_t psela, uint32_t pselb, uint32_t pselled)
+{
+    NRF_QDEC->PSELA = psela;
+    NRF_QDEC->PSELB = pselb;
+    NRF_QDEC->PSELLED = pselled;
+
+}
+
+/**
+ * @brief Function for setting a specific QDEC task.
+ * @param[in] qdec_task QDEC task to be set.
+ */
+__STATIC_INLINE void nrf_qdec_task_trigger(nrf_qdec_task_t qdec_task)
+{
+    *( (volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_task) ) = 1;
+}
+
+
+/**
+ * @brief Function for retrieving the address of a QDEC task register.
+ * @param[in] qdec_task QDEC task.
+ */
+__STATIC_INLINE uint32_t * nrf_qdec_task_address_get(nrf_qdec_task_t qdec_task)
+{
+    return (uint32_t *)( (uint8_t *)NRF_QDEC + qdec_task);
+}
+
+
+/**
+ * @brief Function for clearing a specific QDEC event.
+ * @param[in] qdec_event QDEC event to clear.
+ */
+__STATIC_INLINE void nrf_qdec_event_clear(nrf_qdec_event_t qdec_event)
+{
+    *( (volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event) ) = 0;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_QDEC + qdec_event));
+    (void)dummy;
+#endif
+}
+
+
+/**
+ * @brief Function for retrieving the state of a specific QDEC event.
+ * @return State of the QDEC event.
+ */
+__STATIC_INLINE uint32_t nrf_qdec_event_check(nrf_qdec_event_t qdec_event)
+{
+    return *(volatile uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event);
+}
+
+
+/**
+ * @brief Function for retrieving the address of a specific QDEC event register.
+ * @param[in] qdec_event QDEC event.
+ * @return Address of the specified QDEC event.
+ */
+__STATIC_INLINE uint32_t * nrf_qdec_event_address_get(nrf_qdec_event_t qdec_event)
+{
+    return (uint32_t *)( (uint8_t *)NRF_QDEC + qdec_event);
+}
+
+
+/**
+ * @brief  Function for setting QDEC shortcuts.
+ * @param[in] qdec_short_mask QDEC shortcut by mask.
+ */
+__STATIC_INLINE void nrf_qdec_shorts_enable(uint32_t qdec_short_mask)
+{
+    NRF_QDEC->SHORTS |= qdec_short_mask;
+}
+
+
+/**
+ * @brief Function for clearing shortcuts of the QDEC by mask.
+ * @param[in] qdec_short_mask QDEC shortcute to be cleared.
+ */
+__STATIC_INLINE void nrf_qdec_shorts_disable(uint32_t qdec_short_mask)
+{
+    NRF_QDEC->SHORTS &= ~qdec_short_mask;
+}
+
+
+/**
+ * @brief Function for retrieving the value of QDEC's SAMPLEPER register.
+ * @return Value of the SAMPLEPER register.
+ */
+__STATIC_INLINE int32_t nrf_qdec_sampleper_reg_get(void)
+{
+    return NRF_QDEC->SAMPLEPER;
+}
+
+
+/**
+ * @brief Function for converting the value of QDEC's SAMPLE PERIOD to microseconds.
+ * @retval sampling period in microseconds.
+ */
+__STATIC_INLINE uint32_t nrf_qdec_sampleper_to_value(uint32_t sampleper)
+{
+    return (1 << (7 + sampleper));
+}
+
+/**
+ * @brief Function for setting the value of QDEC's SAMPLEPER register.
+ * @param[in] sample_per Sampling period.
+ */
+__STATIC_INLINE void nrf_qdec_sampleper_set(nrf_qdec_sampleper_t sample_per)
+{
+    NRF_QDEC->SAMPLEPER = sample_per;
+}
+
+
+/**
+ * @brief Function for retrieving the value of QDEC's SAMPLE register.
+ * @return Value of the SAMPLE register.
+ */
+__STATIC_INLINE int32_t nrf_qdec_sample_get(void)
+{
+    return NRF_QDEC->SAMPLE;
+}
+
+
+/**
+ * @brief Function for retrieving the value of QDEC's ACC register.
+ * @return Value of the ACC register.
+ */
+__STATIC_INLINE int32_t nrf_qdec_acc_get(void)
+{
+    return NRF_QDEC->ACC;
+}
+
+
+/**
+ * @brief Function for retrieving the value of QDEC's ACCREAD register.
+ * @return Value of the ACCREAD register.
+ */
+__STATIC_INLINE int32_t nrf_qdec_accread_get(void)
+{
+    return NRF_QDEC->ACCREAD;
+}
+
+
+/**
+ * @brief Function for retrieving the value of QDEC's ACCDBL register.
+ * @return Value of the ACCDBL register.
+ */
+__STATIC_INLINE uint32_t nrf_qdec_accdbl_get(void)
+{
+    return NRF_QDEC->ACCDBL;
+}
+
+
+/**
+ * @brief Function for retrieving the value of QDEC's ACCDBLREAD register.
+ * @return Value of the ACCDBLREAD register.
+ */
+__STATIC_INLINE uint32_t nrf_qdec_accdblread_get(void)
+{
+    return NRF_QDEC->ACCDBLREAD;
+}
+
+
+/**
+ * @brief Function for setting how long the LED is switched on before sampling.
+ * @param[in] time_us Time (in microseconds) how long the LED is switched on before sampling.
+ */
+__STATIC_INLINE void nrf_qdec_ledpre_set(uint32_t time_us)
+{
+    NRF_QDEC->LEDPRE = time_us;
+}
+
+
+/**
+ * @brief Function for retrieving how long the LED is switched on before sampling.
+ * @retval time_us Time (in microseconds) how long the LED is switched on before sampling.
+ */
+__STATIC_INLINE uint32_t nrf_qdec_ledpre_get(void)
+{
+    return NRF_QDEC->LEDPRE;
+}
+
+
+/**
+ * @brief Function for setting the report period (in samples).
+ * @param[in] reportper Number of samples.
+ */
+__STATIC_INLINE void nrf_qdec_reportper_set(nrf_qdec_reportper_t reportper)
+{
+    NRF_QDEC->REPORTPER = reportper;
+}
+
+
+/**
+ * @brief Function for retrieving the report period.
+ * @retval reportper Number of samples as encoded in the register.
+ */
+__STATIC_INLINE uint32_t nrf_qdec_reportper_reg_get(void)
+{
+    return NRF_QDEC->REPORTPER;
+}
+
+
+/**
+ * @brief Function for retrieving the value of QDEC's SAMPLEPER register.
+ * @param [in] reportper  Reportper to be converted to amount of samples per report.
+
+ */
+__STATIC_INLINE uint32_t nrf_qdec_reportper_to_value(uint32_t reportper)
+{
+    return (reportper == NRF_QDEC_REPORTPER_10) ? 10 : reportper * 40;
+}
+
+
+/**
+ * @brief Function for setting the active level for the LED.
+ * @param[in] pol Active level for the LED.
+ */
+__STATIC_INLINE void nrf_qdec_ledpol_set(nrf_qdec_ledpol_t pol)
+{
+    NRF_QDEC->LEDPOL = pol;
+}
+
+
+/**
+ * @brief Function for retrieving the active level for the LED.
+ * @return Active level for the LED.
+ */
+__STATIC_INLINE uint32_t nrf_qdec_ledpol_get(void)
+{
+    return NRF_QDEC->LEDPOL;
+}
+
+
+/**
+   *@}
+ **/
+
+/*lint --flb "Leave library region" */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_rng.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,281 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @file
+ * @brief RNG HAL API.
+ */
+
+#ifndef NRF_RNG_H__
+#define NRF_RNG_H__
+/**
+ * @defgroup nrf_rng_hal RNG HAL
+ * @{
+ * @ingroup nrf_rng
+ * @brief Hardware access layer for managing the random number generator (RNG).
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NRF_RNG_TASK_SET    (1UL)
+#define NRF_RNG_EVENT_CLEAR (0UL)
+/**
+ * @enum nrf_rng_task_t
+ * @brief RNG tasks.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_RNG_TASK_START = offsetof(NRF_RNG_Type, TASKS_START), /**< Start the random number generator. */
+    NRF_RNG_TASK_STOP  = offsetof(NRF_RNG_Type, TASKS_STOP)   /**< Stop the random number generator. */
+} nrf_rng_task_t;                                             /*lint -restore */
+
+/**
+ * @enum nrf_rng_event_t
+ * @brief RNG events.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_RNG_EVENT_VALRDY = offsetof(NRF_RNG_Type, EVENTS_VALRDY) /**< New random number generated event. */
+} nrf_rng_event_t;                                               /*lint -restore */
+
+/**
+ * @enum nrf_rng_int_mask_t
+ * @brief RNG interrupts.
+ */
+typedef enum
+{
+    NRF_RNG_INT_VALRDY_MASK = RNG_INTENSET_VALRDY_Msk /**< Mask for enabling or disabling an interrupt on VALRDY event.  */
+} nrf_rng_int_mask_t;
+
+/**
+ * @enum nrf_rng_short_mask_t
+ * @brief Types of RNG shortcuts.
+ */
+typedef enum
+{
+    NRF_RNG_SHORT_VALRDY_STOP_MASK = RNG_SHORTS_VALRDY_STOP_Msk /**<  Mask for setting shortcut between EVENT_VALRDY and TASK_STOP. */
+} nrf_rng_short_mask_t;
+
+/**
+ * @brief Function for enabling interrupts.
+ *
+ * @param[in]  rng_int_mask              Mask of interrupts.
+ */
+__STATIC_INLINE void nrf_rng_int_enable(uint32_t rng_int_mask);
+
+/**
+ * @brief Function for disabling interrupts.
+ *
+ * @param[in]  rng_int_mask              Mask of interrupts.
+ */
+__STATIC_INLINE void nrf_rng_int_disable(uint32_t rng_int_mask);
+
+/**
+ * @brief Function for getting the state of a specific interrupt.
+ *
+ * @param[in]  rng_int_mask              Interrupt.
+ *
+ * @retval     true                   If the interrupt is not enabled.
+ * @retval     false                  If the interrupt is enabled.
+ */
+__STATIC_INLINE bool nrf_rng_int_get(nrf_rng_int_mask_t rng_int_mask);
+
+/**
+ * @brief Function for getting the address of a specific task.
+ *
+ * This function can be used by the PPI module.
+ *
+ * @param[in]  rng_task              Task.
+ */
+__STATIC_INLINE uint32_t * nrf_rng_task_address_get(nrf_rng_task_t rng_task);
+
+/**
+ * @brief Function for setting a specific task.
+ *
+ * @param[in]  rng_task              Task.
+ */
+__STATIC_INLINE void nrf_rng_task_trigger(nrf_rng_task_t rng_task);
+
+/**
+ * @brief Function for getting address of a specific event.
+ *
+ * This function can be used by the PPI module.
+ *
+ * @param[in]  rng_event              Event.
+ */
+__STATIC_INLINE uint32_t * nrf_rng_event_address_get(nrf_rng_event_t rng_event);
+
+/**
+ * @brief Function for clearing a specific event.
+ *
+ * @param[in]  rng_event              Event.
+ */
+__STATIC_INLINE void nrf_rng_event_clear(nrf_rng_event_t rng_event);
+
+/**
+ * @brief Function for getting the state of a specific event.
+ *
+ * @param[in]  rng_event              Event.
+ *
+ * @retval     true               If the event is not set.
+ * @retval     false              If the event is set.
+ */
+__STATIC_INLINE bool nrf_rng_event_get(nrf_rng_event_t rng_event);
+
+/**
+ * @brief Function for setting shortcuts.
+ *
+ * @param[in]  rng_short_mask              Mask of shortcuts.
+ *
+ */
+__STATIC_INLINE void nrf_rng_shorts_enable(uint32_t rng_short_mask);
+
+/**
+ * @brief Function for clearing shortcuts.
+ *
+ * @param[in]  rng_short_mask              Mask of shortcuts.
+ *
+ */
+__STATIC_INLINE void nrf_rng_shorts_disable(uint32_t rng_short_mask);
+
+/**
+ * @brief Function for getting the previously generated random value.
+ *
+ * @return     Previously generated random value.
+ */
+__STATIC_INLINE uint8_t nrf_rng_random_value_get(void);
+
+/**
+ * @brief Function for enabling digital error correction.
+ */
+__STATIC_INLINE void nrf_rng_error_correction_enable(void);
+
+/**
+ * @brief Function for disabling digital error correction.
+ */
+__STATIC_INLINE void nrf_rng_error_correction_disable(void);
+
+/**
+ *@}
+ **/
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_rng_int_enable(uint32_t rng_int_mask)
+{
+    NRF_RNG->INTENSET = rng_int_mask;
+}
+
+__STATIC_INLINE void nrf_rng_int_disable(uint32_t rng_int_mask)
+{
+    NRF_RNG->INTENCLR = rng_int_mask;
+}
+
+__STATIC_INLINE bool nrf_rng_int_get(nrf_rng_int_mask_t rng_int_mask)
+{
+    return (bool)(NRF_RNG->INTENCLR & rng_int_mask);
+}
+
+__STATIC_INLINE uint32_t * nrf_rng_task_address_get(nrf_rng_task_t rng_task)
+{
+    return (uint32_t *)((uint8_t *)NRF_RNG + rng_task);
+}
+
+__STATIC_INLINE void nrf_rng_task_trigger(nrf_rng_task_t rng_task)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_task)) = NRF_RNG_TASK_SET;
+}
+
+__STATIC_INLINE uint32_t * nrf_rng_event_address_get(nrf_rng_event_t rng_event)
+{
+    return (uint32_t *)((uint8_t *)NRF_RNG + rng_event);
+}
+
+__STATIC_INLINE void nrf_rng_event_clear(nrf_rng_event_t rng_event)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event)) = NRF_RNG_EVENT_CLEAR;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event));
+    (void)dummy;
+#endif
+}
+
+__STATIC_INLINE bool nrf_rng_event_get(nrf_rng_event_t rng_event)
+{
+    return (bool) * ((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event));
+}
+
+__STATIC_INLINE void nrf_rng_shorts_enable(uint32_t rng_short_mask)
+{
+     NRF_RNG->SHORTS |= rng_short_mask;
+}
+
+__STATIC_INLINE void nrf_rng_shorts_disable(uint32_t rng_short_mask)
+{
+     NRF_RNG->SHORTS &= ~rng_short_mask;
+}
+
+__STATIC_INLINE uint8_t nrf_rng_random_value_get(void)
+{
+    return (uint8_t)(NRF_RNG->VALUE & RNG_VALUE_VALUE_Msk);
+}
+
+__STATIC_INLINE void nrf_rng_error_correction_enable(void)
+{
+    NRF_RNG->CONFIG |= RNG_CONFIG_DERCEN_Msk;
+}
+
+__STATIC_INLINE void nrf_rng_error_correction_disable(void)
+{
+    NRF_RNG->CONFIG &= ~RNG_CONFIG_DERCEN_Msk;
+}
+
+#endif
+ 
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF_RNG_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_rtc.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,342 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @file
+ * @brief RTC HAL API.
+ */
+
+#ifndef NRF_RTC_H
+#define NRF_RTC_H
+
+/**
+ * @defgroup nrf_rtc_hal RTC HAL
+ * @{
+ * @ingroup nrf_rtc
+ * @brief Hardware access layer for managing the real time counter (RTC).
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+#include "nrf.h"
+#include "nrf_assert.h"
+#include "nrf_peripherals.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Macro for getting the number of compare channels available
+ *        in a given RTC instance.
+ */
+
+#define NRF_RTC_CC_CHANNEL_COUNT(id) CONCAT_3(RTC, id, _CC_NUM)
+
+#define RTC_INPUT_FREQ 32768 /**< Input frequency of the RTC instance. */
+
+/**
+ * @brief Macro for converting expected frequency to prescaler setting.
+ */
+#define RTC_FREQ_TO_PRESCALER(FREQ) (uint16_t)((RTC_INPUT_FREQ / (FREQ)) - 1)
+
+/**< Macro for wrapping values to RTC capacity. */
+#define RTC_WRAP(val) (val & RTC_COUNTER_COUNTER_Msk)
+
+#define RTC_CHANNEL_INT_MASK(ch)    ((uint32_t)NRF_RTC_INT_COMPARE0_MASK << ch)
+#define RTC_CHANNEL_EVENT_ADDR(ch)  (nrf_rtc_event_t)(NRF_RTC_EVENT_COMPARE_0 + ch * sizeof(uint32_t))
+/**
+ * @enum nrf_rtc_task_t
+ * @brief RTC tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_RTC_TASK_START            = offsetof(NRF_RTC_Type,TASKS_START),     /**< Start. */
+    NRF_RTC_TASK_STOP             = offsetof(NRF_RTC_Type,TASKS_STOP),      /**< Stop. */
+    NRF_RTC_TASK_CLEAR            = offsetof(NRF_RTC_Type,TASKS_CLEAR),     /**< Clear. */
+    NRF_RTC_TASK_TRIGGER_OVERFLOW = offsetof(NRF_RTC_Type,TASKS_TRIGOVRFLW),/**< Trigger overflow. */
+    /*lint -restore*/
+} nrf_rtc_task_t;
+
+/**
+ * @enum nrf_rtc_event_t
+ * @brief RTC events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_RTC_EVENT_TICK        = offsetof(NRF_RTC_Type,EVENTS_TICK),       /**< Tick event. */
+    NRF_RTC_EVENT_OVERFLOW    = offsetof(NRF_RTC_Type,EVENTS_OVRFLW),     /**< Overflow event. */
+    NRF_RTC_EVENT_COMPARE_0   = offsetof(NRF_RTC_Type,EVENTS_COMPARE[0]), /**< Compare 0 event. */
+    NRF_RTC_EVENT_COMPARE_1   = offsetof(NRF_RTC_Type,EVENTS_COMPARE[1]), /**< Compare 1 event. */
+    NRF_RTC_EVENT_COMPARE_2   = offsetof(NRF_RTC_Type,EVENTS_COMPARE[2]), /**< Compare 2 event. */
+    NRF_RTC_EVENT_COMPARE_3   = offsetof(NRF_RTC_Type,EVENTS_COMPARE[3])  /**< Compare 3 event. */
+    /*lint -restore*/
+} nrf_rtc_event_t;
+
+/**
+ * @enum nrf_rtc_int_t
+ * @brief RTC interrupts.
+ */
+typedef enum
+{
+    NRF_RTC_INT_TICK_MASK     = RTC_INTENSET_TICK_Msk,     /**< RTC interrupt from tick event. */
+    NRF_RTC_INT_OVERFLOW_MASK = RTC_INTENSET_OVRFLW_Msk,   /**< RTC interrupt from overflow event. */
+    NRF_RTC_INT_COMPARE0_MASK = RTC_INTENSET_COMPARE0_Msk, /**< RTC interrupt from compare event on channel 0. */
+    NRF_RTC_INT_COMPARE1_MASK = RTC_INTENSET_COMPARE1_Msk, /**< RTC interrupt from compare event on channel 1. */
+    NRF_RTC_INT_COMPARE2_MASK = RTC_INTENSET_COMPARE2_Msk, /**< RTC interrupt from compare event on channel 2. */
+    NRF_RTC_INT_COMPARE3_MASK = RTC_INTENSET_COMPARE3_Msk  /**< RTC interrupt from compare event on channel 3. */
+} nrf_rtc_int_t;
+
+/**@brief Function for setting a compare value for a channel.
+ *
+ * @param[in]  p_rtc         Pointer to the peripheral registers structure.
+ * @param[in]  ch            Channel.
+ * @param[in]  cc_val        Compare value to set.
+ */
+__STATIC_INLINE  void nrf_rtc_cc_set(NRF_RTC_Type * p_rtc, uint32_t ch, uint32_t cc_val);
+
+/**@brief Function for returning the compare value for a channel.
+ *
+ * @param[in]  p_rtc         Pointer to the peripheral registers structure.
+ * @param[in]  ch            Channel.
+ *
+ * @return                   COMPARE[ch] value.
+ */
+__STATIC_INLINE  uint32_t nrf_rtc_cc_get(NRF_RTC_Type * p_rtc, uint32_t ch);
+
+/**@brief Function for enabling interrupts.
+ *
+ * @param[in]  p_rtc         Pointer to the peripheral registers structure.
+ * @param[in]  mask          Interrupt mask to be enabled.
+ */
+__STATIC_INLINE void nrf_rtc_int_enable(NRF_RTC_Type * p_rtc, uint32_t mask);
+
+/**@brief Function for disabling interrupts.
+ *
+ * @param[in]  p_rtc         Pointer to the peripheral registers structure.
+ * @param[in]  mask          Interrupt mask to be disabled.
+ */
+__STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_rtc, uint32_t mask);
+
+/**@brief Function for checking if interrupts are enabled.
+ *
+ * @param[in]  p_rtc         Pointer to the peripheral registers structure.
+ * @param[in]  mask          Mask of interrupt flags to check.
+ *
+ * @return                   Mask with enabled interrupts.
+ */
+__STATIC_INLINE uint32_t nrf_rtc_int_is_enabled(NRF_RTC_Type * p_rtc, uint32_t mask);
+
+/**@brief Function for returning the status of currently enabled interrupts.
+ *
+ * @param[in]  p_rtc         Pointer to the peripheral registers structure.
+ *
+ * @return                   Value in INTEN register.
+ */
+__STATIC_INLINE uint32_t nrf_rtc_int_get(NRF_RTC_Type * p_rtc);
+
+/**@brief Function for checking if an event is pending.
+ *
+ * @param[in]  p_rtc         Pointer to the peripheral registers structure.
+ * @param[in]  event         Address of the event.
+ *
+ * @return                   Mask of pending events.
+ */
+__STATIC_INLINE uint32_t nrf_rtc_event_pending(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event);
+
+/**@brief Function for clearing an event.
+ *
+ * @param[in]  p_rtc         Pointer to the peripheral registers structure.
+ * @param[in]  event         Event to clear.
+ */
+__STATIC_INLINE void nrf_rtc_event_clear(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event);
+
+/**@brief Function for returning a counter value.
+ *
+ * @param[in]  p_rtc         Pointer to the peripheral registers structure.
+ *
+ * @return                   Counter value.
+ */
+__STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type * p_rtc);
+
+/**@brief Function for setting a prescaler value.
+ *
+ * @param[in]  p_rtc         Pointer to the peripheral registers structure.
+ * @param[in]  val           Value to set the prescaler to.
+ */
+__STATIC_INLINE void nrf_rtc_prescaler_set(NRF_RTC_Type * p_rtc, uint32_t val);
+
+/**@brief Function for returning the address of an event.
+ *
+ * @param[in]  p_rtc         Pointer to the peripheral registers structure.
+ * @param[in]  event         Requested event.
+ *
+ * @return     Address of the requested event register.
+ */
+__STATIC_INLINE uint32_t nrf_rtc_event_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event);
+
+/**@brief Function for returning the address of a task.
+ *
+ * @param[in]  p_rtc         Pointer to the peripheral registers structure.
+ * @param[in]  task          Requested task.
+ *
+ * @return     Address of the requested task register.
+ */
+__STATIC_INLINE uint32_t nrf_rtc_task_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task);
+
+/**@brief Function for starting a task.
+ *
+ * @param[in]  p_rtc         Pointer to the peripheral registers structure.
+ * @param[in]  task          Requested task.
+ */
+__STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task);
+
+/**@brief Function for enabling events.
+ *
+ * @param[in]  p_rtc         Pointer to the peripheral registers structure.
+ * @param[in]  mask          Mask of event flags to enable.
+ */
+__STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_rtc, uint32_t mask);
+
+/**@brief Function for disabling an event.
+ *
+ * @param[in]  p_rtc         Pointer to the peripheral registers structure.
+ * @param[in]  event         Requested event.
+ */
+__STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_rtc, uint32_t event);
+
+/**
+ *@}
+ **/
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE  void nrf_rtc_cc_set(NRF_RTC_Type * p_rtc, uint32_t ch, uint32_t cc_val)
+{
+    p_rtc->CC[ch] = cc_val;
+}
+
+__STATIC_INLINE  uint32_t nrf_rtc_cc_get(NRF_RTC_Type * p_rtc, uint32_t ch)
+{
+    return p_rtc->CC[ch];
+}
+
+__STATIC_INLINE void nrf_rtc_int_enable(NRF_RTC_Type * p_rtc, uint32_t mask)
+{
+    p_rtc->INTENSET = mask;
+}
+
+__STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_rtc, uint32_t mask)
+{
+    p_rtc->INTENCLR = mask;
+}
+
+__STATIC_INLINE uint32_t nrf_rtc_int_is_enabled(NRF_RTC_Type * p_rtc, uint32_t mask)
+{
+    return (p_rtc->INTENSET & mask);
+}
+
+__STATIC_INLINE uint32_t nrf_rtc_int_get(NRF_RTC_Type * p_rtc)
+{
+    return p_rtc->INTENSET;
+}
+
+__STATIC_INLINE uint32_t nrf_rtc_event_pending(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event)
+{
+    return *(volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event);
+}
+
+__STATIC_INLINE void nrf_rtc_event_clear(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event)) = 0;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event));
+    (void)dummy;
+#endif
+}
+
+__STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type * p_rtc)
+{
+     return p_rtc->COUNTER;
+}
+
+__STATIC_INLINE void nrf_rtc_prescaler_set(NRF_RTC_Type * p_rtc, uint32_t val)
+{
+    ASSERT(val <= (RTC_PRESCALER_PRESCALER_Msk >> RTC_PRESCALER_PRESCALER_Pos));
+    p_rtc->PRESCALER = val;
+}
+__STATIC_INLINE uint32_t rtc_prescaler_get(NRF_RTC_Type * p_rtc)
+{
+    return p_rtc->PRESCALER;
+}
+
+__STATIC_INLINE uint32_t nrf_rtc_event_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event)
+{
+    return (uint32_t)p_rtc + event;
+}
+
+__STATIC_INLINE uint32_t nrf_rtc_task_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task)
+{
+    return (uint32_t)p_rtc + task;
+}
+
+__STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task)
+{
+    *(__IO uint32_t *)((uint32_t)p_rtc + task) = 1;
+}
+
+__STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_rtc, uint32_t mask)
+{
+    p_rtc->EVTENSET = mask;
+}
+__STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_rtc, uint32_t mask)
+{
+    p_rtc->EVTENCLR = mask;
+}
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* NRF_RTC_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_saadc.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,61 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @file
+ * @brief SAADC HAL implementation
+ */
+#include "sdk_config.h"
+#if SAADC_ENABLED
+#include "nrf_saadc.h"
+
+void nrf_saadc_channel_init(uint8_t channel, nrf_saadc_channel_config_t const * const config)
+{
+    NRF_SAADC->CH[channel].CONFIG =
+            ((config->resistor_p   << SAADC_CH_CONFIG_RESP_Pos)   & SAADC_CH_CONFIG_RESP_Msk)
+            | ((config->resistor_n << SAADC_CH_CONFIG_RESN_Pos)   & SAADC_CH_CONFIG_RESN_Msk)
+            | ((config->gain       << SAADC_CH_CONFIG_GAIN_Pos)   & SAADC_CH_CONFIG_GAIN_Msk)
+            | ((config->reference  << SAADC_CH_CONFIG_REFSEL_Pos) & SAADC_CH_CONFIG_REFSEL_Msk)
+            | ((config->acq_time   << SAADC_CH_CONFIG_TACQ_Pos)   & SAADC_CH_CONFIG_TACQ_Msk)
+            | ((config->mode       << SAADC_CH_CONFIG_MODE_Pos)   & SAADC_CH_CONFIG_MODE_Msk)
+            | ((config->burst      << SAADC_CH_CONFIG_BURST_Pos)  & SAADC_CH_CONFIG_BURST_Msk);
+    nrf_saadc_channel_input_set(channel, config->pin_p, config->pin_n);
+    return;
+}
+#endif //SAADC_ENABLED
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_saadc.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,609 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_SAADC_H_
+#define NRF_SAADC_H_
+
+/**
+ * @defgroup nrf_saadc_hal SAADC HAL
+ * @{
+ * @ingroup nrf_saadc
+ *
+ * @brief @tagAPI52 Hardware access layer for accessing the SAADC peripheral.
+ */
+
+#include <stdbool.h>
+#include <stddef.h>
+#include "nrf.h"
+#include "nrf_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NRF_SAADC_CHANNEL_COUNT 8
+
+/**
+ * @brief Resolution of the analog-to-digital converter.
+ */
+typedef enum
+{
+    NRF_SAADC_RESOLUTION_8BIT  = SAADC_RESOLUTION_VAL_8bit,  ///< 8 bit resolution.
+    NRF_SAADC_RESOLUTION_10BIT = SAADC_RESOLUTION_VAL_10bit, ///< 10 bit resolution.
+    NRF_SAADC_RESOLUTION_12BIT = SAADC_RESOLUTION_VAL_12bit, ///< 12 bit resolution.
+    NRF_SAADC_RESOLUTION_14BIT = SAADC_RESOLUTION_VAL_14bit  ///< 14 bit resolution.
+} nrf_saadc_resolution_t;
+
+
+/**
+ * @brief Input selection for the analog-to-digital converter.
+ */
+typedef enum
+{
+    NRF_SAADC_INPUT_DISABLED = SAADC_CH_PSELP_PSELP_NC,           ///< Not connected.
+    NRF_SAADC_INPUT_AIN0     = SAADC_CH_PSELP_PSELP_AnalogInput0, ///< Analog input 0 (AIN0).
+    NRF_SAADC_INPUT_AIN1     = SAADC_CH_PSELP_PSELP_AnalogInput1, ///< Analog input 1 (AIN1).
+    NRF_SAADC_INPUT_AIN2     = SAADC_CH_PSELP_PSELP_AnalogInput2, ///< Analog input 2 (AIN2).
+    NRF_SAADC_INPUT_AIN3     = SAADC_CH_PSELP_PSELP_AnalogInput3, ///< Analog input 3 (AIN3).
+    NRF_SAADC_INPUT_AIN4     = SAADC_CH_PSELP_PSELP_AnalogInput4, ///< Analog input 4 (AIN4).
+    NRF_SAADC_INPUT_AIN5     = SAADC_CH_PSELP_PSELP_AnalogInput5, ///< Analog input 5 (AIN5).
+    NRF_SAADC_INPUT_AIN6     = SAADC_CH_PSELP_PSELP_AnalogInput6, ///< Analog input 6 (AIN6).
+    NRF_SAADC_INPUT_AIN7     = SAADC_CH_PSELP_PSELP_AnalogInput7, ///< Analog input 7 (AIN7).
+    NRF_SAADC_INPUT_VDD      = SAADC_CH_PSELP_PSELP_VDD           ///< VDD as input.
+} nrf_saadc_input_t;
+
+
+/**
+ * @brief Analog-to-digital converter oversampling mode.
+ */
+typedef enum
+{
+    NRF_SAADC_OVERSAMPLE_DISABLED = SAADC_OVERSAMPLE_OVERSAMPLE_Bypass,   ///< No oversampling.
+    NRF_SAADC_OVERSAMPLE_2X       = SAADC_OVERSAMPLE_OVERSAMPLE_Over2x,   ///< Oversample 2x.
+    NRF_SAADC_OVERSAMPLE_4X       = SAADC_OVERSAMPLE_OVERSAMPLE_Over4x,   ///< Oversample 4x.
+    NRF_SAADC_OVERSAMPLE_8X       = SAADC_OVERSAMPLE_OVERSAMPLE_Over8x,   ///< Oversample 8x.
+    NRF_SAADC_OVERSAMPLE_16X      = SAADC_OVERSAMPLE_OVERSAMPLE_Over16x,  ///< Oversample 16x.
+    NRF_SAADC_OVERSAMPLE_32X      = SAADC_OVERSAMPLE_OVERSAMPLE_Over32x,  ///< Oversample 32x.
+    NRF_SAADC_OVERSAMPLE_64X      = SAADC_OVERSAMPLE_OVERSAMPLE_Over64x,  ///< Oversample 64x.
+    NRF_SAADC_OVERSAMPLE_128X     = SAADC_OVERSAMPLE_OVERSAMPLE_Over128x, ///< Oversample 128x.
+    NRF_SAADC_OVERSAMPLE_256X     = SAADC_OVERSAMPLE_OVERSAMPLE_Over256x  ///< Oversample 256x.
+} nrf_saadc_oversample_t;
+
+
+/**
+ * @brief Analog-to-digital converter channel resistor control.
+ */
+typedef enum
+{
+    NRF_SAADC_RESISTOR_DISABLED = SAADC_CH_CONFIG_RESP_Bypass,   ///< Bypass resistor ladder.
+    NRF_SAADC_RESISTOR_PULLDOWN = SAADC_CH_CONFIG_RESP_Pulldown, ///< Pull-down to GND.
+    NRF_SAADC_RESISTOR_PULLUP   = SAADC_CH_CONFIG_RESP_Pullup,   ///< Pull-up to VDD.
+    NRF_SAADC_RESISTOR_VDD1_2   = SAADC_CH_CONFIG_RESP_VDD1_2    ///< Set input at VDD/2.
+} nrf_saadc_resistor_t;
+
+
+/**
+ * @brief Gain factor of the analog-to-digital converter input.
+ */
+typedef enum
+{
+    NRF_SAADC_GAIN1_6 = SAADC_CH_CONFIG_GAIN_Gain1_6, ///< Gain factor 1/6.
+    NRF_SAADC_GAIN1_5 = SAADC_CH_CONFIG_GAIN_Gain1_5, ///< Gain factor 1/5.
+    NRF_SAADC_GAIN1_4 = SAADC_CH_CONFIG_GAIN_Gain1_4, ///< Gain factor 1/4.
+    NRF_SAADC_GAIN1_3 = SAADC_CH_CONFIG_GAIN_Gain1_3, ///< Gain factor 1/3.
+    NRF_SAADC_GAIN1_2 = SAADC_CH_CONFIG_GAIN_Gain1_2, ///< Gain factor 1/2.
+    NRF_SAADC_GAIN1   = SAADC_CH_CONFIG_GAIN_Gain1,   ///< Gain factor 1.
+    NRF_SAADC_GAIN2   = SAADC_CH_CONFIG_GAIN_Gain2,   ///< Gain factor 2.
+    NRF_SAADC_GAIN4   = SAADC_CH_CONFIG_GAIN_Gain4,   ///< Gain factor 4.
+} nrf_saadc_gain_t;
+
+
+/**
+ * @brief Reference selection for the analog-to-digital converter.
+ */
+typedef enum
+{
+    NRF_SAADC_REFERENCE_INTERNAL = SAADC_CH_CONFIG_REFSEL_Internal, ///< Internal reference (0.6 V).
+    NRF_SAADC_REFERENCE_VDD4     = SAADC_CH_CONFIG_REFSEL_VDD1_4    ///< VDD/4 as reference.
+} nrf_saadc_reference_t;
+
+
+/**
+ * @brief Analog-to-digital converter acquisition time.
+ */
+typedef enum
+{
+    NRF_SAADC_ACQTIME_3US  = SAADC_CH_CONFIG_TACQ_3us,  ///< 3 us.
+    NRF_SAADC_ACQTIME_5US  = SAADC_CH_CONFIG_TACQ_5us,  ///< 5 us.
+    NRF_SAADC_ACQTIME_10US = SAADC_CH_CONFIG_TACQ_10us, ///< 10 us.
+    NRF_SAADC_ACQTIME_15US = SAADC_CH_CONFIG_TACQ_15us, ///< 15 us.
+    NRF_SAADC_ACQTIME_20US = SAADC_CH_CONFIG_TACQ_20us, ///< 20 us.
+    NRF_SAADC_ACQTIME_40US = SAADC_CH_CONFIG_TACQ_40us  ///< 40 us.
+} nrf_saadc_acqtime_t;
+
+
+/**
+ * @brief Analog-to-digital converter channel mode.
+ */
+typedef enum
+{
+    NRF_SAADC_MODE_SINGLE_ENDED = SAADC_CH_CONFIG_MODE_SE,  ///< Single ended, PSELN will be ignored, negative input to ADC shorted to GND.
+    NRF_SAADC_MODE_DIFFERENTIAL = SAADC_CH_CONFIG_MODE_Diff ///< Differential mode.
+} nrf_saadc_mode_t;
+
+
+/**
+ * @brief Analog-to-digital converter channel burst mode.
+ */
+typedef enum
+{
+    NRF_SAADC_BURST_DISABLED = SAADC_CH_CONFIG_BURST_Disabled, ///< Burst mode is disabled (normal operation).
+    NRF_SAADC_BURST_ENABLED  = SAADC_CH_CONFIG_BURST_Enabled   ///< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM.
+} nrf_saadc_burst_t;
+
+
+/**
+ * @brief Analog-to-digital converter tasks.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_SAADC_TASK_START           = offsetof(NRF_SAADC_Type, TASKS_START),           ///< Start the ADC and prepare the result buffer in RAM.
+    NRF_SAADC_TASK_SAMPLE          = offsetof(NRF_SAADC_Type, TASKS_SAMPLE),          ///< Take one ADC sample. If scan is enabled, all channels are sampled.
+    NRF_SAADC_TASK_STOP            = offsetof(NRF_SAADC_Type, TASKS_STOP),            ///< Stop the ADC and terminate any on-going conversion.
+    NRF_SAADC_TASK_CALIBRATEOFFSET = offsetof(NRF_SAADC_Type, TASKS_CALIBRATEOFFSET), ///< Starts offset auto-calibration.
+} nrf_saadc_task_t;
+
+
+/**
+ * @brief Analog-to-digital converter events.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_SAADC_EVENT_STARTED       = offsetof(NRF_SAADC_Type, EVENTS_STARTED),       ///< The ADC has started.
+    NRF_SAADC_EVENT_END           = offsetof(NRF_SAADC_Type, EVENTS_END),           ///< The ADC has filled up the result buffer.
+    NRF_SAADC_EVENT_DONE          = offsetof(NRF_SAADC_Type, EVENTS_DONE),          ///< A conversion task has been completed.
+    NRF_SAADC_EVENT_RESULTDONE    = offsetof(NRF_SAADC_Type, EVENTS_RESULTDONE),    ///< A result is ready to get transferred to RAM.
+    NRF_SAADC_EVENT_CALIBRATEDONE = offsetof(NRF_SAADC_Type, EVENTS_CALIBRATEDONE), ///< Calibration is complete.
+    NRF_SAADC_EVENT_STOPPED       = offsetof(NRF_SAADC_Type, EVENTS_STOPPED),       ///< The ADC has stopped.
+    NRF_SAADC_EVENT_CH0_LIMITH    = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITH),  ///< Last result is equal or above CH[0].LIMIT.HIGH.
+    NRF_SAADC_EVENT_CH0_LIMITL    = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITL),  ///< Last result is equal or below CH[0].LIMIT.LOW.
+    NRF_SAADC_EVENT_CH1_LIMITH    = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITH),  ///< Last result is equal or above CH[1].LIMIT.HIGH.
+    NRF_SAADC_EVENT_CH1_LIMITL    = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITL),  ///< Last result is equal or below CH[1].LIMIT.LOW.
+    NRF_SAADC_EVENT_CH2_LIMITH    = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITH),  ///< Last result is equal or above CH[2].LIMIT.HIGH.
+    NRF_SAADC_EVENT_CH2_LIMITL    = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITL),  ///< Last result is equal or below CH[2].LIMIT.LOW.
+    NRF_SAADC_EVENT_CH3_LIMITH    = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITH),  ///< Last result is equal or above CH[3].LIMIT.HIGH.
+    NRF_SAADC_EVENT_CH3_LIMITL    = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITL),  ///< Last result is equal or below CH[3].LIMIT.LOW.
+    NRF_SAADC_EVENT_CH4_LIMITH    = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITH),  ///< Last result is equal or above CH[4].LIMIT.HIGH.
+    NRF_SAADC_EVENT_CH4_LIMITL    = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITL),  ///< Last result is equal or below CH[4].LIMIT.LOW.
+    NRF_SAADC_EVENT_CH5_LIMITH    = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITH),  ///< Last result is equal or above CH[5].LIMIT.HIGH.
+    NRF_SAADC_EVENT_CH5_LIMITL    = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITL),  ///< Last result is equal or below CH[5].LIMIT.LOW.
+    NRF_SAADC_EVENT_CH6_LIMITH    = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITH),  ///< Last result is equal or above CH[6].LIMIT.HIGH.
+    NRF_SAADC_EVENT_CH6_LIMITL    = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITL),  ///< Last result is equal or below CH[6].LIMIT.LOW.
+    NRF_SAADC_EVENT_CH7_LIMITH    = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITH),  ///< Last result is equal or above CH[7].LIMIT.HIGH.
+    NRF_SAADC_EVENT_CH7_LIMITL    = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITL)   ///< Last result is equal or below CH[7].LIMIT.LOW.
+} nrf_saadc_event_t;
+
+
+/**
+ * @brief Analog-to-digital converter interrupt masks.
+ */
+typedef enum
+{
+    NRF_SAADC_INT_STARTED       = SAADC_INTENSET_STARTED_Msk,       ///< Interrupt on EVENTS_STARTED event.
+    NRF_SAADC_INT_END           = SAADC_INTENSET_END_Msk,           ///< Interrupt on EVENTS_END event.
+    NRF_SAADC_INT_DONE          = SAADC_INTENSET_DONE_Msk,          ///< Interrupt on EVENTS_DONE event.
+    NRF_SAADC_INT_RESULTDONE    = SAADC_INTENSET_RESULTDONE_Msk,    ///< Interrupt on EVENTS_RESULTDONE event.
+    NRF_SAADC_INT_CALIBRATEDONE = SAADC_INTENSET_CALIBRATEDONE_Msk, ///< Interrupt on EVENTS_CALIBRATEDONE event.
+    NRF_SAADC_INT_STOPPED       = SAADC_INTENSET_STOPPED_Msk,       ///< Interrupt on EVENTS_STOPPED event.
+    NRF_SAADC_INT_CH0LIMITH     = SAADC_INTENSET_CH0LIMITH_Msk,     ///< Interrupt on EVENTS_CH[0].LIMITH event.
+    NRF_SAADC_INT_CH0LIMITL     = SAADC_INTENSET_CH0LIMITL_Msk,     ///< Interrupt on EVENTS_CH[0].LIMITL event.
+    NRF_SAADC_INT_CH1LIMITH     = SAADC_INTENSET_CH1LIMITH_Msk,     ///< Interrupt on EVENTS_CH[1].LIMITH event.
+    NRF_SAADC_INT_CH1LIMITL     = SAADC_INTENSET_CH1LIMITL_Msk,     ///< Interrupt on EVENTS_CH[1].LIMITL event.
+    NRF_SAADC_INT_CH2LIMITH     = SAADC_INTENSET_CH2LIMITH_Msk,     ///< Interrupt on EVENTS_CH[2].LIMITH event.
+    NRF_SAADC_INT_CH2LIMITL     = SAADC_INTENSET_CH2LIMITL_Msk,     ///< Interrupt on EVENTS_CH[2].LIMITL event.
+    NRF_SAADC_INT_CH3LIMITH     = SAADC_INTENSET_CH3LIMITH_Msk,     ///< Interrupt on EVENTS_CH[3].LIMITH event.
+    NRF_SAADC_INT_CH3LIMITL     = SAADC_INTENSET_CH3LIMITL_Msk,     ///< Interrupt on EVENTS_CH[3].LIMITL event.
+    NRF_SAADC_INT_CH4LIMITH     = SAADC_INTENSET_CH4LIMITH_Msk,     ///< Interrupt on EVENTS_CH[4].LIMITH event.
+    NRF_SAADC_INT_CH4LIMITL     = SAADC_INTENSET_CH4LIMITL_Msk,     ///< Interrupt on EVENTS_CH[4].LIMITL event.
+    NRF_SAADC_INT_CH5LIMITH     = SAADC_INTENSET_CH5LIMITH_Msk,     ///< Interrupt on EVENTS_CH[5].LIMITH event.
+    NRF_SAADC_INT_CH5LIMITL     = SAADC_INTENSET_CH5LIMITL_Msk,     ///< Interrupt on EVENTS_CH[5].LIMITL event.
+    NRF_SAADC_INT_CH6LIMITH     = SAADC_INTENSET_CH6LIMITH_Msk,     ///< Interrupt on EVENTS_CH[6].LIMITH event.
+    NRF_SAADC_INT_CH6LIMITL     = SAADC_INTENSET_CH6LIMITL_Msk,     ///< Interrupt on EVENTS_CH[6].LIMITL event.
+    NRF_SAADC_INT_CH7LIMITH     = SAADC_INTENSET_CH7LIMITH_Msk,     ///< Interrupt on EVENTS_CH[7].LIMITH event.
+    NRF_SAADC_INT_CH7LIMITL     = SAADC_INTENSET_CH7LIMITL_Msk,     ///< Interrupt on EVENTS_CH[7].LIMITL event.
+    NRF_SAADC_INT_ALL           = 0x7FFFFFFFUL                      ///< Mask of all interrupts.
+} nrf_saadc_int_mask_t;
+
+
+/**
+ * @brief Analog-to-digital converter value limit type.
+ */
+typedef enum
+{
+    NRF_SAADC_LIMIT_LOW  = 0,
+    NRF_SAADC_LIMIT_HIGH = 1
+} nrf_saadc_limit_t;
+
+
+typedef int16_t nrf_saadc_value_t;  ///< Type of a single ADC conversion result.
+
+
+/**
+ * @brief Analog-to-digital converter configuration structure.
+ */
+typedef struct
+{
+    nrf_saadc_resolution_t resolution;
+    nrf_saadc_oversample_t oversample;
+    nrf_saadc_value_t *    buffer;
+    uint32_t               buffer_size;
+} nrf_saadc_config_t;
+
+
+/**
+ * @brief Analog-to-digital converter channel configuration structure.
+ */
+typedef struct
+{
+    nrf_saadc_resistor_t  resistor_p;
+    nrf_saadc_resistor_t  resistor_n;
+    nrf_saadc_gain_t      gain;
+    nrf_saadc_reference_t reference;
+    nrf_saadc_acqtime_t   acq_time;
+    nrf_saadc_mode_t      mode;
+    nrf_saadc_burst_t     burst;
+    nrf_saadc_input_t     pin_p;
+    nrf_saadc_input_t     pin_n;
+} nrf_saadc_channel_config_t;
+
+
+/**
+ * @brief Function for triggering a specific SAADC task.
+ *
+ * @param[in] saadc_task SAADC task.
+ */
+__STATIC_INLINE void nrf_saadc_task_trigger(nrf_saadc_task_t saadc_task)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_task)) = 0x1UL;
+}
+
+
+/**
+ * @brief Function for getting the address of a specific SAADC task register.
+ *
+ * @param[in] saadc_task SAADC task.
+ *
+ * @return Address of the specified SAADC task.
+ */
+__STATIC_INLINE uint32_t nrf_saadc_task_address_get(nrf_saadc_task_t saadc_task)
+{
+    return (uint32_t)((uint8_t *)NRF_SAADC + (uint32_t)saadc_task);
+}
+
+
+/**
+ * @brief Function for getting the state of a specific SAADC event.
+ *
+ * @param[in] saadc_event SAADC event.
+ *
+ * @return State of the specified SAADC event.
+ */
+__STATIC_INLINE bool nrf_saadc_event_check(nrf_saadc_event_t saadc_event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event);
+}
+
+
+/**
+ * @brief Function for clearing the specific SAADC event.
+ *
+ * @param[in] saadc_event SAADC event.
+ */
+__STATIC_INLINE void nrf_saadc_event_clear(nrf_saadc_event_t saadc_event)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event)) = 0x0UL;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event));
+    (void)dummy;
+#endif
+}
+
+
+/**
+ * @brief Function for getting the address of a specific SAADC event register.
+ *
+ * @param[in] saadc_event SAADC event.
+ *
+ * @return Address of the specified SAADC event.
+ */
+__STATIC_INLINE uint32_t  nrf_saadc_event_address_get(nrf_saadc_event_t saadc_event)
+{
+    return (uint32_t )((uint8_t *)NRF_SAADC + (uint32_t)saadc_event);
+}
+
+
+/**
+ * @brief Function for getting the address of a specific SAADC limit event register.
+ *
+ * @param[in] channel Channel number.
+ * @param[in] limit_type Low limit or high limit.
+ *
+ * @return Address of the specified SAADC limit event.
+ */
+__STATIC_INLINE volatile uint32_t * nrf_saadc_event_limit_address_get(uint8_t channel, nrf_saadc_limit_t limit_type)
+{
+    ASSERT(channel < NRF_SAADC_CHANNEL_COUNT);
+    if (limit_type == NRF_SAADC_LIMIT_HIGH)
+    {
+        return &NRF_SAADC->EVENTS_CH[channel].LIMITH;
+    }
+    else
+    {
+        return &NRF_SAADC->EVENTS_CH[channel].LIMITL;
+    }
+}
+
+
+/**
+ * @brief Function for getting the SAADC channel monitoring limit events.
+ *
+ * @param[in] channel    Channel number.
+ * @param[in] limit_type Low limit or high limit.
+ */
+__STATIC_INLINE nrf_saadc_event_t nrf_saadc_event_limit_get(uint8_t channel, nrf_saadc_limit_t limit_type)
+{
+    if (limit_type == NRF_SAADC_LIMIT_HIGH)
+    {
+        return (nrf_saadc_event_t)( (uint32_t) NRF_SAADC_EVENT_CH0_LIMITH +
+                        (uint32_t) (NRF_SAADC_EVENT_CH1_LIMITH - NRF_SAADC_EVENT_CH0_LIMITH)
+                        * (uint32_t) channel );
+    }
+    else
+    {
+        return (nrf_saadc_event_t)( (uint32_t) NRF_SAADC_EVENT_CH0_LIMITL +
+                        (uint32_t) (NRF_SAADC_EVENT_CH1_LIMITL - NRF_SAADC_EVENT_CH0_LIMITL)
+                        * (uint32_t) channel );
+    }
+}
+
+
+/**
+ * @brief Function for configuring the input pins for a specific SAADC channel.
+ *
+ * @param[in] channel Channel number.
+ * @param[in] pselp   Positive input.
+ * @param[in] pseln   Negative input. Set to NRF_SAADC_INPUT_DISABLED in single ended mode.
+ */
+__STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel,
+                                                 nrf_saadc_input_t pselp,
+                                                 nrf_saadc_input_t pseln)
+{
+    NRF_SAADC->CH[channel].PSELN = pseln;
+    NRF_SAADC->CH[channel].PSELP = pselp;
+}
+
+
+/**
+ * @brief Function for setting the SAADC channel monitoring limits.
+ *
+ * @param[in] channel Channel number.
+ * @param[in] low     Low limit.
+ * @param[in] high    High limit.
+ */
+__STATIC_INLINE void nrf_saadc_channel_limits_set(uint8_t channel, int16_t low, int16_t high)
+{
+    NRF_SAADC->CH[channel].LIMIT = (
+            (((uint32_t) low << SAADC_CH_LIMIT_LOW_Pos) & SAADC_CH_LIMIT_LOW_Msk)
+          | (((uint32_t) high << SAADC_CH_LIMIT_HIGH_Pos) & SAADC_CH_LIMIT_HIGH_Msk));
+}
+
+
+/**
+ * @brief Function for enabling specified SAADC interrupts.
+ *
+ * @param[in] saadc_int_mask Interrupt(s) to enable.
+ */
+__STATIC_INLINE void nrf_saadc_int_enable(uint32_t saadc_int_mask)
+{
+    NRF_SAADC->INTENSET = saadc_int_mask;
+}
+
+
+/**
+ * @brief Function for retrieving the state of specified SAADC interrupts.
+ *
+ * @param[in] saadc_int_mask Interrupt(s) to check.
+ *
+ * @retval true  If all specified interrupts are enabled.
+ * @retval false If at least one of the given interrupts is not enabled.
+ */
+__STATIC_INLINE bool nrf_saadc_int_enable_check(uint32_t saadc_int_mask)
+{
+    return (bool)(NRF_SAADC->INTENSET & saadc_int_mask);
+}
+
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param saadc_int_mask Interrupt(s) to disable.
+ */
+__STATIC_INLINE void nrf_saadc_int_disable(uint32_t saadc_int_mask)
+{
+    NRF_SAADC->INTENCLR = saadc_int_mask;
+}
+
+
+/**
+ * @brief Function for generating masks for SAADC channel limit interrupts.
+ *
+ * @param[in] channel    SAADC channel number.
+ * @param[in] limit_type Limit type.
+ *
+ * @returns Interrupt mask.
+ */
+__STATIC_INLINE uint32_t nrf_saadc_limit_int_get(uint8_t channel, nrf_saadc_limit_t limit_type)
+{
+    ASSERT(channel < NRF_SAADC_CHANNEL_COUNT);
+    uint32_t mask = (limit_type == NRF_SAADC_LIMIT_LOW) ? NRF_SAADC_INT_CH0LIMITL : NRF_SAADC_INT_CH0LIMITH;
+    return mask << (channel * 2);
+}
+
+
+/**
+ * @brief Function for checking whether the SAADC is busy.
+ *
+ * This function checks whether the analog-to-digital converter is busy with a conversion.
+ *
+ * @retval true  If the SAADC is busy.
+ * @retval false If the SAADC is not busy.
+ */
+__STATIC_INLINE bool nrf_saadc_busy_check(void)
+{
+    //return ((NRF_SAADC->STATUS & SAADC_STATUS_STATUS_Msk) == SAADC_STATUS_STATUS_Msk);
+    //simplified for performance
+    return NRF_SAADC->STATUS;
+}
+
+
+/**
+ * @brief Function for enabling the SAADC.
+ *
+ * The analog-to-digital converter must be enabled before use.
+ */
+__STATIC_INLINE void nrf_saadc_enable(void)
+{
+    NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos);
+}
+
+
+/**
+ * @brief Function for disabling the SAADC.
+ */
+__STATIC_INLINE void nrf_saadc_disable(void)
+{
+    NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Disabled << SAADC_ENABLE_ENABLE_Pos);
+}
+
+
+/**
+ * @brief Function for checking if the SAADC is enabled.
+ *
+ * @retval true  If the SAADC is enabled.
+ * @retval false If the SAADC is not enabled.
+ */
+__STATIC_INLINE bool nrf_saadc_enable_check(void)
+{
+    //simplified for performance
+    return NRF_SAADC->ENABLE;
+}
+
+
+/**
+ * @brief Function for initializing the SAADC result buffer.
+ *
+ * @param[in] buffer Pointer to the result buffer.
+ * @param[in] num    Size of buffer in words.
+ */
+__STATIC_INLINE void nrf_saadc_buffer_init(nrf_saadc_value_t * buffer, uint32_t num)
+{
+    NRF_SAADC->RESULT.PTR = (uint32_t)buffer;
+    NRF_SAADC->RESULT.MAXCNT = num;
+}
+
+/**
+ * @brief Function for getting the number of buffer words transferred since last START operation.
+ *
+ * @returns Number of words transferred.
+ */
+__STATIC_INLINE uint16_t nrf_saadc_amount_get(void)
+{
+    return NRF_SAADC->RESULT.AMOUNT;
+}
+
+
+/**
+ * @brief Function for setting the SAADC sample resolution.
+ *
+ * @param[in] resolution Bit resolution.
+ */
+__STATIC_INLINE void nrf_saadc_resolution_set(nrf_saadc_resolution_t resolution)
+{
+    NRF_SAADC->RESOLUTION = resolution;
+}
+
+
+/**
+ * @brief Function for configuring the oversampling feature.
+ *
+ * @param[in] oversample Oversampling mode.
+ */
+__STATIC_INLINE void nrf_saadc_oversample_set(nrf_saadc_oversample_t oversample)
+{
+    NRF_SAADC->OVERSAMPLE = oversample;
+}
+
+/**
+ * @brief Function for getting the oversampling feature configuration.
+ *
+ * @return Oversampling configuration.
+ */
+__STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(void)
+{
+    return (nrf_saadc_oversample_t)NRF_SAADC->OVERSAMPLE;
+}
+
+/**
+ * @brief Function for initializing the SAADC channel.
+ *
+ * @param[in] channel Channel number.
+ * @param[in] config  Pointer to the channel configuration structure.
+ */
+void nrf_saadc_channel_init(uint8_t channel, nrf_saadc_channel_config_t const * const config);
+
+/**
+ *@}
+ **/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF_SAADC_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_spi.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,373 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @defgroup nrf_spi_hal SPI HAL
+ * @{
+ * @ingroup nrf_spi
+ *
+ * @brief Hardware access layer for accessing the SPI peripheral.
+ */
+
+#ifndef NRF_SPI_H__
+#define NRF_SPI_H__
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @brief This value can be used as a parameter for the @ref nrf_spi_pins_set
+ *        function to specify that a given SPI signal (SCK, MOSI, or MISO)
+ *        shall not be connected to a physical pin.
+ */
+#define NRF_SPI_PIN_NOT_CONNECTED  0xFFFFFFFF
+
+
+/**
+ * @brief SPI events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_SPI_EVENT_READY = offsetof(NRF_SPI_Type, EVENTS_READY) ///< TXD byte sent and RXD byte received.
+    /*lint -restore*/
+} nrf_spi_event_t;
+
+/**
+ * @brief SPI interrupts.
+ */
+typedef enum
+{
+    NRF_SPI_INT_READY_MASK = SPI_INTENSET_READY_Msk ///< Interrupt on READY event.
+} nrf_spi_int_mask_t;
+
+/**
+ * @brief SPI data rates.
+ */
+typedef enum
+{
+    NRF_SPI_FREQ_125K = SPI_FREQUENCY_FREQUENCY_K125,   ///< 125 kbps.
+    NRF_SPI_FREQ_250K = SPI_FREQUENCY_FREQUENCY_K250,   ///< 250 kbps.
+    NRF_SPI_FREQ_500K = SPI_FREQUENCY_FREQUENCY_K500,   ///< 500 kbps.
+    NRF_SPI_FREQ_1M   = SPI_FREQUENCY_FREQUENCY_M1,     ///< 1 Mbps.
+    NRF_SPI_FREQ_2M   = SPI_FREQUENCY_FREQUENCY_M2,     ///< 2 Mbps.
+    NRF_SPI_FREQ_4M   = SPI_FREQUENCY_FREQUENCY_M4,     ///< 4 Mbps.
+    // [conversion to 'int' needed to prevent compilers from complaining
+    //  that the provided value (0x80000000UL) is out of range of "int"]
+    NRF_SPI_FREQ_8M   = (int)SPI_FREQUENCY_FREQUENCY_M8 ///< 8 Mbps.
+} nrf_spi_frequency_t;
+
+/**
+ * @brief SPI modes.
+ */
+typedef enum
+{
+    NRF_SPI_MODE_0, ///< SCK active high, sample on leading edge of clock.
+    NRF_SPI_MODE_1, ///< SCK active high, sample on trailing edge of clock.
+    NRF_SPI_MODE_2, ///< SCK active low, sample on leading edge of clock.
+    NRF_SPI_MODE_3  ///< SCK active low, sample on trailing edge of clock.
+} nrf_spi_mode_t;
+
+/**
+ * @brief SPI bit orders.
+ */
+typedef enum
+{
+    NRF_SPI_BIT_ORDER_MSB_FIRST = SPI_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
+    NRF_SPI_BIT_ORDER_LSB_FIRST = SPI_CONFIG_ORDER_LsbFirst  ///< Least significant bit shifted out first.
+} nrf_spi_bit_order_t;
+
+
+/**
+ * @brief Function for clearing a specific SPI event.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @param[in] spi_event Event to clear.
+ */
+__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_reg,
+                                         nrf_spi_event_t spi_event);
+
+/**
+ * @brief Function for checking the state of a specific SPI event.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @param[in] spi_event Event to check.
+ *
+ * @retval true  If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_reg,
+                                         nrf_spi_event_t spi_event);
+
+/**
+ * @brief Function for getting the address of a specific SPI event register.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @param[in] spi_event Requested event.
+ *
+ * @return Address of the specified event register.
+ */
+__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type  * p_reg,
+                                                     nrf_spi_event_t spi_event);
+
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] p_reg         Pointer to the peripheral registers structure.
+ * @param[in] spi_int_mask  Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_spi_int_enable(NRF_SPI_Type * p_reg,
+                                        uint32_t spi_int_mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] p_reg         Pointer to the peripheral registers structure.
+ * @param[in] spi_int_mask  Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_reg,
+                                         uint32_t spi_int_mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param[in] spi_int Interrupt to check.
+ *
+ * @retval true  If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_reg,
+                                              nrf_spi_int_mask_t spi_int);
+
+/**
+ * @brief Function for enabling the SPI peripheral.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_spi_enable(NRF_SPI_Type * p_reg);
+
+/**
+ * @brief Function for disabling the SPI peripheral.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_reg);
+
+/**
+ * @brief Function for configuring SPI pins.
+ *
+ * If a given signal is not needed, pass the @ref NRF_SPI_PIN_NOT_CONNECTED
+ * value instead of its pin number.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @param[in] sck_pin   SCK pin number.
+ * @param[in] mosi_pin  MOSI pin number.
+ * @param[in] miso_pin  MISO pin number.
+ */
+__STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_reg,
+                                      uint32_t sck_pin,
+                                      uint32_t mosi_pin,
+                                      uint32_t miso_pin);
+
+/**
+ * @brief Function for writing data to the SPI transmitter register.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] data  TX data to send.
+ */
+__STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_reg, uint8_t data);
+
+/**
+ * @brief Function for reading data from the SPI receiver register.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ *
+ * @return RX data received.
+ */
+__STATIC_INLINE uint8_t nrf_spi_rxd_get(NRF_SPI_Type * p_reg);
+
+/**
+ * @brief Function for setting the SPI master data rate.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @param[in] frequency SPI frequency.
+ */
+__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_reg,
+                                           nrf_spi_frequency_t frequency);
+
+/**
+ * @brief Function for setting the SPI configuration.
+ *
+ * @param[in] p_reg         Pointer to the peripheral registers structure.
+ * @param[in] spi_mode      SPI mode.
+ * @param[in] spi_bit_order SPI bit order.
+ */
+__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_reg,
+                                       nrf_spi_mode_t spi_mode,
+                                       nrf_spi_bit_order_t spi_bit_order);
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_reg,
+                                         nrf_spi_event_t spi_event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event)) = 0x0UL;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event));
+    (void)dummy;
+#endif
+}
+
+__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_reg,
+                                         nrf_spi_event_t spi_event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event);
+}
+
+__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type * p_reg,
+                                                     nrf_spi_event_t spi_event)
+{
+    return (uint32_t *)((uint8_t *)p_reg + (uint32_t)spi_event);
+}
+
+__STATIC_INLINE void nrf_spi_int_enable(NRF_SPI_Type * p_reg,
+                                        uint32_t spi_int_mask)
+{
+    p_reg->INTENSET = spi_int_mask;
+}
+
+__STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_reg,
+                                         uint32_t spi_int_mask)
+{
+    p_reg->INTENCLR = spi_int_mask;
+}
+
+__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_reg,
+                                              nrf_spi_int_mask_t spi_int)
+{
+    return (bool)(p_reg->INTENSET & spi_int);
+}
+
+__STATIC_INLINE void nrf_spi_enable(NRF_SPI_Type * p_reg)
+{
+    p_reg->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_reg)
+{
+    p_reg->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_reg,
+                                      uint32_t sck_pin,
+                                      uint32_t mosi_pin,
+                                      uint32_t miso_pin)
+{
+    p_reg->PSELSCK  = sck_pin;
+    p_reg->PSELMOSI = mosi_pin;
+    p_reg->PSELMISO = miso_pin;
+}
+
+__STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_reg, uint8_t data)
+{
+    p_reg->TXD = data;
+}
+
+__STATIC_INLINE uint8_t nrf_spi_rxd_get(NRF_SPI_Type * p_reg)
+{
+    return p_reg->RXD;
+}
+
+__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_reg,
+                                           nrf_spi_frequency_t frequency)
+{
+    p_reg->FREQUENCY = frequency;
+}
+
+__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_reg,
+                                       nrf_spi_mode_t spi_mode,
+                                       nrf_spi_bit_order_t spi_bit_order)
+{
+    uint32_t config = (spi_bit_order == NRF_SPI_BIT_ORDER_MSB_FIRST ?
+        SPI_CONFIG_ORDER_MsbFirst : SPI_CONFIG_ORDER_LsbFirst);
+    switch (spi_mode)
+    {
+    default:
+    case NRF_SPI_MODE_0:
+        config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) |
+                  (SPI_CONFIG_CPHA_Leading    << SPI_CONFIG_CPHA_Pos);
+        break;
+
+    case NRF_SPI_MODE_1:
+        config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) |
+                  (SPI_CONFIG_CPHA_Trailing   << SPI_CONFIG_CPHA_Pos);
+        break;
+
+    case NRF_SPI_MODE_2:
+        config |= (SPI_CONFIG_CPOL_ActiveLow  << SPI_CONFIG_CPOL_Pos) |
+                  (SPI_CONFIG_CPHA_Leading    << SPI_CONFIG_CPHA_Pos);
+        break;
+
+    case NRF_SPI_MODE_3:
+        config |= (SPI_CONFIG_CPOL_ActiveLow  << SPI_CONFIG_CPOL_Pos) |
+                  (SPI_CONFIG_CPHA_Trailing   << SPI_CONFIG_CPHA_Pos);
+        break;
+    }
+    p_reg->CONFIG = config;
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_SPI_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_spim.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,550 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @defgroup nrf_spim_hal SPIM HAL
+ * @{
+ * @ingroup nrf_spi
+ *
+ * @brief Hardware access layer for accessing the SPIM peripheral.
+ */
+
+#ifndef NRF_SPIM_H__
+#define NRF_SPIM_H__
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @brief This value can be used as a parameter for the @ref nrf_spim_pins_set
+ *        function to specify that a given SPI signal (SCK, MOSI, or MISO)
+ *        shall not be connected to a physical pin.
+ */
+#define NRF_SPIM_PIN_NOT_CONNECTED  0xFFFFFFFF
+
+
+/**
+ * @brief SPIM tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_SPIM_TASK_START   = offsetof(NRF_SPIM_Type, TASKS_START),   ///< Start SPI transaction.
+    NRF_SPIM_TASK_STOP    = offsetof(NRF_SPIM_Type, TASKS_STOP),    ///< Stop SPI transaction.
+    NRF_SPIM_TASK_SUSPEND = offsetof(NRF_SPIM_Type, TASKS_SUSPEND), ///< Suspend SPI transaction.
+    NRF_SPIM_TASK_RESUME  = offsetof(NRF_SPIM_Type, TASKS_RESUME)   ///< Resume SPI transaction.
+    /*lint -restore*/
+} nrf_spim_task_t;
+
+/**
+ * @brief SPIM events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_SPIM_EVENT_STOPPED = offsetof(NRF_SPIM_Type, EVENTS_STOPPED), ///< SPI transaction has stopped.
+    NRF_SPIM_EVENT_ENDRX   = offsetof(NRF_SPIM_Type, EVENTS_ENDRX),   ///< End of RXD buffer reached.
+    NRF_SPIM_EVENT_END     = offsetof(NRF_SPIM_Type, EVENTS_END),     ///< End of RXD buffer and TXD buffer reached.
+    NRF_SPIM_EVENT_ENDTX   = offsetof(NRF_SPIM_Type, EVENTS_ENDTX),   ///< End of TXD buffer reached.
+    NRF_SPIM_EVENT_STARTED = offsetof(NRF_SPIM_Type, EVENTS_STARTED)  ///< Transaction started.
+    /*lint -restore*/
+} nrf_spim_event_t;
+
+/**
+ * @brief SPIM shortcuts.
+ */
+typedef enum
+{
+    NRF_SPIM_SHORT_END_START_MASK = SPIM_SHORTS_END_START_Msk ///< Shortcut between END event and START task.
+} nrf_spim_short_mask_t;
+
+/**
+ * @brief SPIM interrupts.
+ */
+typedef enum
+{
+    NRF_SPIM_INT_STOPPED_MASK = SPIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
+    NRF_SPIM_INT_ENDRX_MASK   = SPIM_INTENSET_ENDRX_Msk,   ///< Interrupt on ENDRX event.
+    NRF_SPIM_INT_END_MASK     = SPIM_INTENSET_END_Msk,     ///< Interrupt on END event.
+    NRF_SPIM_INT_ENDTX_MASK   = SPIM_INTENSET_ENDTX_Msk,   ///< Interrupt on ENDTX event.
+    NRF_SPIM_INT_STARTED_MASK = SPIM_INTENSET_STARTED_Msk  ///< Interrupt on STARTED event.
+} nrf_spim_int_mask_t;
+
+/**
+ * @brief SPI master data rates.
+ */
+typedef enum
+{
+    NRF_SPIM_FREQ_125K = SPIM_FREQUENCY_FREQUENCY_K125,   ///< 125 kbps.
+    NRF_SPIM_FREQ_250K = SPIM_FREQUENCY_FREQUENCY_K250,   ///< 250 kbps.
+    NRF_SPIM_FREQ_500K = SPIM_FREQUENCY_FREQUENCY_K500,   ///< 500 kbps.
+    NRF_SPIM_FREQ_1M   = SPIM_FREQUENCY_FREQUENCY_M1,     ///< 1 Mbps.
+    NRF_SPIM_FREQ_2M   = SPIM_FREQUENCY_FREQUENCY_M2,     ///< 2 Mbps.
+    NRF_SPIM_FREQ_4M   = SPIM_FREQUENCY_FREQUENCY_M4,     ///< 4 Mbps.
+    // [conversion to 'int' needed to prevent compilers from complaining
+    //  that the provided value (0x80000000UL) is out of range of "int"]
+    NRF_SPIM_FREQ_8M   = (int)SPIM_FREQUENCY_FREQUENCY_M8 ///< 8 Mbps.
+} nrf_spim_frequency_t;
+
+/**
+ * @brief SPI modes.
+ */
+typedef enum
+{
+    NRF_SPIM_MODE_0, ///< SCK active high, sample on leading edge of clock.
+    NRF_SPIM_MODE_1, ///< SCK active high, sample on trailing edge of clock.
+    NRF_SPIM_MODE_2, ///< SCK active low, sample on leading edge of clock.
+    NRF_SPIM_MODE_3  ///< SCK active low, sample on trailing edge of clock.
+} nrf_spim_mode_t;
+
+/**
+ * @brief SPI bit orders.
+ */
+typedef enum
+{
+    NRF_SPIM_BIT_ORDER_MSB_FIRST = SPIM_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
+    NRF_SPIM_BIT_ORDER_LSB_FIRST = SPIM_CONFIG_ORDER_LsbFirst  ///< Least significant bit shifted out first.
+} nrf_spim_bit_order_t;
+
+
+/**
+ * @brief Function for activating a specific SPIM task.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @param[in] spim_task Task to activate.
+ */
+__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,
+                                           nrf_spim_task_t spim_task);
+
+/**
+ * @brief Function for getting the address of a specific SPIM task register.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @param[in] spim_task Requested task.
+ *
+ * @return Address of the specified task register.
+ */
+__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_reg,
+                                                   nrf_spim_task_t spim_task);
+
+/**
+ * @brief Function for clearing a specific SPIM event.
+ *
+ * @param[in] p_reg      Pointer to the peripheral registers structure.
+ * @param[in] spim_event Event to clear.
+ */
+__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
+                                          nrf_spim_event_t spim_event);
+
+/**
+ * @brief Function for checking the state of a specific SPIM event.
+ *
+ * @param[in] p_reg      Pointer to the peripheral registers structure.
+ * @param[in] spim_event Event to check.
+ *
+ * @retval true  If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_reg,
+                                          nrf_spim_event_t spim_event);
+
+/**
+ * @brief Function for getting the address of a specific SPIM event register.
+ *
+ * @param[in] p_reg      Pointer to the peripheral registers structure.
+ * @param[in] spim_event Requested event.
+ *
+ * @return Address of the specified event register.
+ */
+__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type  * p_reg,
+                                                    nrf_spim_event_t spim_event);
+/**
+ * @brief Function for enabling specified shortcuts.
+ *
+ * @param[in] p_reg            Pointer to the peripheral registers structure.
+ * @param[in] spim_shorts_mask Shortcuts to enable.
+ */
+__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,
+                                            uint32_t spim_shorts_mask);
+
+/**
+ * @brief Function for disabling specified shortcuts.
+ *
+ * @param[in] p_reg            Pointer to the peripheral registers structure.
+ * @param[in] spim_shorts_mask Shortcuts to disable.
+ */
+__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,
+                                             uint32_t spim_shorts_mask);
+
+/**
+ * @brief Function for getting shorts setting.
+ *
+ * @param[in] p_reg           Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_reg);
+
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] p_reg        Pointer to the peripheral registers structure.
+ * @param[in] spim_int_mask Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg,
+                                         uint32_t spim_int_mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] p_reg        Pointer to the peripheral registers structure.
+ * @param[in] spim_int_mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg,
+                                          uint32_t spim_int_mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param[in] spim_int Interrupt to check.
+ *
+ * @retval true  If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_reg,
+                                               nrf_spim_int_mask_t spim_int);
+
+/**
+ * @brief Function for enabling the SPIM peripheral.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg);
+
+/**
+ * @brief Function for disabling the SPIM peripheral.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg);
+
+/**
+ * @brief Function for configuring SPIM pins.
+ *
+ * If a given signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
+ * value instead of its pin number.
+ *
+ * @param[in] p_reg    Pointer to the peripheral registers structure.
+ * @param[in] sck_pin   SCK pin number.
+ * @param[in] mosi_pin  MOSI pin number.
+ * @param[in] miso_pin  MISO pin number.
+ */
+__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
+                                       uint32_t sck_pin,
+                                       uint32_t mosi_pin,
+                                       uint32_t miso_pin);
+
+/**
+ * @brief Function for setting the SPI master data rate.
+ *
+ * @param[in] p_reg    Pointer to the peripheral registers structure.
+ * @param[in] frequency SPI frequency.
+ */
+__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
+                                            nrf_spim_frequency_t frequency);
+
+/**
+ * @brief Function for setting the transmit buffer.
+ *
+ * @param[in]  p_reg   Pointer to the peripheral registers structure.
+ * @param[in]  p_buffer Pointer to the buffer with data to send.
+ * @param[in]  length   Maximum number of data bytes to transmit.
+ */
+__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
+                                            uint8_t const * p_buffer,
+                                            uint8_t         length);
+
+/**
+ * @brief Function for setting the receive buffer.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param[in] p_buffer Pointer to the buffer for received data.
+ * @param[in] length   Maximum number of data bytes to receive.
+ */
+__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
+                                            uint8_t * p_buffer,
+                                            uint8_t   length);
+
+/**
+ * @brief Function for setting the SPI configuration.
+ *
+ * @param[in] p_reg        Pointer to the peripheral registers structure.
+ * @param[in] spi_mode      SPI mode.
+ * @param[in] spi_bit_order SPI bit order.
+ */
+__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
+                                        nrf_spim_mode_t spi_mode,
+                                        nrf_spim_bit_order_t spi_bit_order);
+
+/**
+ * @brief Function for setting the over-read character.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] orc    Over-read character that is clocked out in case of
+ *                   an over-read of the TXD buffer.
+ */
+__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
+                                      uint8_t orc);
+
+/**
+ * @brief Function for enabling the TX list feature.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg);
+
+/**
+ * @brief Function for disabling the TX list feature.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg);
+
+/**
+ * @brief Function for enabling the RX list feature.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg);
+
+/**
+ * @brief Function for disabling the RX list feature.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,
+                                           nrf_spim_task_t spim_task)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_task)) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_reg,
+                                                   nrf_spim_task_t spim_task)
+{
+    return (uint32_t)((uint8_t *)p_reg + (uint32_t)spim_task);
+}
+
+__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
+                                          nrf_spim_event_t spim_event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event)) = 0x0UL;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event));
+    (void)dummy;
+#endif
+}
+
+__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_reg,
+                                          nrf_spim_event_t spim_event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spim_event);
+}
+
+__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_reg,
+                                                    nrf_spim_event_t spim_event)
+{
+    return (uint32_t)((uint8_t *)p_reg + (uint32_t)spim_event);
+}
+
+__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,
+                                            uint32_t spim_shorts_mask)
+{
+    p_reg->SHORTS |= spim_shorts_mask;
+}
+
+__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,
+                                             uint32_t spim_shorts_mask)
+{
+    p_reg->SHORTS &= ~(spim_shorts_mask);
+}
+
+__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_reg)
+{
+    return p_reg->SHORTS;
+}
+
+__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg,
+                                         uint32_t spim_int_mask)
+{
+    p_reg->INTENSET = spim_int_mask;
+}
+
+__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg,
+                                          uint32_t spim_int_mask)
+{
+    p_reg->INTENCLR = spim_int_mask;
+}
+
+__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_reg,
+                                               nrf_spim_int_mask_t spim_int)
+{
+    return (bool)(p_reg->INTENSET & spim_int);
+}
+
+__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg)
+{
+    p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg)
+{
+    p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
+                                       uint32_t sck_pin,
+                                       uint32_t mosi_pin,
+                                       uint32_t miso_pin)
+{
+    p_reg->PSEL.SCK  = sck_pin;
+    p_reg->PSEL.MOSI = mosi_pin;
+    p_reg->PSEL.MISO = miso_pin;
+}
+
+__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
+                                            nrf_spim_frequency_t frequency)
+{
+    p_reg->FREQUENCY = frequency;
+}
+
+__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
+                                            uint8_t const * p_buffer,
+                                            uint8_t         length)
+{
+    p_reg->TXD.PTR    = (uint32_t)p_buffer;
+    p_reg->TXD.MAXCNT = length;
+}
+
+__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
+                                            uint8_t * p_buffer,
+                                            uint8_t   length)
+{
+    p_reg->RXD.PTR    = (uint32_t)p_buffer;
+    p_reg->RXD.MAXCNT = length;
+}
+
+__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
+                                        nrf_spim_mode_t spi_mode,
+                                        nrf_spim_bit_order_t spi_bit_order)
+{
+    uint32_t config = (spi_bit_order == NRF_SPIM_BIT_ORDER_MSB_FIRST ?
+        SPIM_CONFIG_ORDER_MsbFirst : SPIM_CONFIG_ORDER_LsbFirst);
+    switch (spi_mode)
+    {
+    default:
+    case NRF_SPIM_MODE_0:
+        config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
+                  (SPIM_CONFIG_CPHA_Leading    << SPIM_CONFIG_CPHA_Pos);
+        break;
+
+    case NRF_SPIM_MODE_1:
+        config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
+                  (SPIM_CONFIG_CPHA_Trailing   << SPIM_CONFIG_CPHA_Pos);
+        break;
+
+    case NRF_SPIM_MODE_2:
+        config |= (SPIM_CONFIG_CPOL_ActiveLow  << SPIM_CONFIG_CPOL_Pos) |
+                  (SPIM_CONFIG_CPHA_Leading    << SPIM_CONFIG_CPHA_Pos);
+        break;
+
+    case NRF_SPIM_MODE_3:
+        config |= (SPIM_CONFIG_CPOL_ActiveLow  << SPIM_CONFIG_CPOL_Pos) |
+                  (SPIM_CONFIG_CPHA_Trailing   << SPIM_CONFIG_CPHA_Pos);
+        break;
+    }
+    p_reg->CONFIG = config;
+}
+
+__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
+                                      uint8_t orc)
+{
+    p_reg->ORC = orc;
+}
+
+
+__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg)
+{
+    p_reg->TXD.LIST = 1;
+}
+
+__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg)
+{
+    p_reg->TXD.LIST = 0;
+}
+
+__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg)
+{
+    p_reg->RXD.LIST = 1;
+}
+
+__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg)
+{
+    p_reg->RXD.LIST = 0;
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_SPIM_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_spis.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,552 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @defgroup nrf_spis_hal SPIS HAL
+ * @{
+ * @ingroup nrf_spis
+ *
+ * @brief Hardware access layer for accessing the SPIS peripheral.
+ */
+
+#ifndef NRF_SPIS_H__
+#define NRF_SPIS_H__
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "nrf.h"
+#include "nrf_peripherals.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @brief This value can be used as a parameter for the @ref nrf_spis_pins_set
+ *        function to specify that a given SPI signal (SCK, MOSI, or MISO)
+ *        shall not be connected to a physical pin.
+ */
+#define NRF_SPIS_PIN_NOT_CONNECTED  0xFFFFFFFF
+
+
+/**
+ * @brief SPIS tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_SPIS_TASK_ACQUIRE = offsetof(NRF_SPIS_Type, TASKS_ACQUIRE), ///< Acquire SPI semaphore.
+    NRF_SPIS_TASK_RELEASE = offsetof(NRF_SPIS_Type, TASKS_RELEASE), ///< Release SPI semaphore, enabling the SPI slave to acquire it.
+    /*lint -restore*/
+} nrf_spis_task_t;
+
+/**
+ * @brief SPIS events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_SPIS_EVENT_END      = offsetof(NRF_SPIS_Type, EVENTS_END),     ///< Granted transaction completed.
+    NRF_SPIS_EVENT_ACQUIRED = offsetof(NRF_SPIS_Type, EVENTS_ACQUIRED) ///< Semaphore acquired.
+    /*lint -restore*/
+} nrf_spis_event_t;
+
+/**
+ * @brief SPIS shortcuts.
+ */
+typedef enum
+{
+    NRF_SPIS_SHORT_END_ACQUIRE = SPIS_SHORTS_END_ACQUIRE_Msk ///< Shortcut between END event and ACQUIRE task.
+} nrf_spis_short_mask_t;
+
+/**
+ * @brief SPIS interrupts.
+ */
+typedef enum
+{
+    NRF_SPIS_INT_END_MASK      = SPIS_INTENSET_END_Msk,     ///< Interrupt on END event.
+    NRF_SPIS_INT_ACQUIRED_MASK = SPIS_INTENSET_ACQUIRED_Msk ///< Interrupt on ACQUIRED event.
+} nrf_spis_int_mask_t;
+
+/**
+ * @brief SPI modes.
+ */
+typedef enum
+{
+    NRF_SPIS_MODE_0, ///< SCK active high, sample on leading edge of clock.
+    NRF_SPIS_MODE_1, ///< SCK active high, sample on trailing edge of clock.
+    NRF_SPIS_MODE_2, ///< SCK active low, sample on leading edge of clock.
+    NRF_SPIS_MODE_3  ///< SCK active low, sample on trailing edge of clock.
+} nrf_spis_mode_t;
+
+/**
+ * @brief SPI bit orders.
+ */
+typedef enum
+{
+    NRF_SPIS_BIT_ORDER_MSB_FIRST = SPIS_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
+    NRF_SPIS_BIT_ORDER_LSB_FIRST = SPIS_CONFIG_ORDER_LsbFirst  ///< Least significant bit shifted out first.
+} nrf_spis_bit_order_t;
+
+/**
+ * @brief SPI semaphore status.
+ */
+typedef enum
+{
+    NRF_SPIS_SEMSTAT_FREE       = 0, ///< Semaphore is free.
+    NRF_SPIS_SEMSTAT_CPU        = 1, ///< Semaphore is assigned to the CPU.
+    NRF_SPIS_SEMSTAT_SPIS       = 2, ///< Semaphore is assigned to the SPI slave.
+    NRF_SPIS_SEMSTAT_CPUPENDING = 3  ///< Semaphore is assigned to the SPI, but a handover to the CPU is pending.
+} nrf_spis_semstat_t;
+
+/**
+ * @brief SPIS status.
+ */
+typedef enum
+{
+    NRF_SPIS_STATUS_OVERREAD = SPIS_STATUS_OVERREAD_Msk, ///< TX buffer over-read detected and prevented.
+    NRF_SPIS_STATUS_OVERFLOW = SPIS_STATUS_OVERFLOW_Msk  ///< RX buffer overflow detected and prevented.
+} nrf_spis_status_mask_t;
+
+/**
+ * @brief Function for activating a specific SPIS task.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @param[in] spis_task Task to activate.
+ */
+__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg,
+                                           nrf_spis_task_t spis_task);
+
+/**
+ * @brief Function for getting the address of a specific SPIS task register.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @param[in] spis_task Requested task.
+ *
+ * @return Address of the specified task register.
+ */
+__STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg,
+                                                   nrf_spis_task_t spis_task);
+
+/**
+ * @brief Function for clearing a specific SPIS event.
+ *
+ * @param[in] p_reg      Pointer to the peripheral registers structure.
+ * @param[in] spis_event Event to clear.
+ */
+__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg,
+                                          nrf_spis_event_t spis_event);
+
+/**
+ * @brief Function for checking the state of a specific SPIS event.
+ *
+ * @param[in] p_reg      Pointer to the peripheral registers structure.
+ * @param[in] spis_event Event to check.
+ *
+ * @retval true  If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg,
+                                          nrf_spis_event_t spis_event);
+
+/**
+ * @brief Function for getting the address of a specific SPIS event register.
+ *
+ * @param[in] p_reg      Pointer to the peripheral registers structure.
+ * @param[in] spis_event Requested event.
+ *
+ * @return Address of the specified event register.
+ */
+__STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg,
+                                                    nrf_spis_event_t spis_event);
+
+/**
+ * @brief Function for enabling specified shortcuts.
+ *
+ * @param[in] p_reg            Pointer to the peripheral registers structure.
+ * @param[in] spis_shorts_mask Shortcuts to enable.
+ */
+__STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg,
+                                            uint32_t spis_shorts_mask);
+
+/**
+ * @brief Function for disabling specified shortcuts.
+ *
+ * @param[in] p_reg            Pointer to the peripheral registers structure.
+ * @param[in] spis_shorts_mask Shortcuts to disable.
+ */
+__STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg,
+                                             uint32_t spis_shorts_mask);
+
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] p_reg         Pointer to the peripheral registers structure.
+ * @param[in] spis_int_mask Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_reg,
+                                         uint32_t spis_int_mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] p_reg         Pointer to the peripheral registers structure.
+ * @param[in] spis_int_mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_reg,
+                                          uint32_t spis_int_mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param[in] p_reg    Pointer to the peripheral registers structure.
+ * @param[in] spis_int Interrupt to check.
+ *
+ * @retval true  If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg,
+                                               nrf_spis_int_mask_t spis_int);
+
+/**
+ * @brief Function for enabling the SPIS peripheral.
+ *
+ * @param[in] p_reg  Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_reg);
+
+/**
+ * @brief Function for disabling the SPIS peripheral.
+ *
+ * @param[in] p_reg  Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_reg);
+
+/**
+ * @brief Function for retrieving the SPIS semaphore status.
+ *
+ * @param[in] p_reg  Pointer to the peripheral registers structure.
+ *
+ * @returns Current semaphore status.
+ */
+__STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type * p_reg);
+
+/**
+ * @brief Function for retrieving the SPIS status.
+ *
+ * @param[in] p_reg  Pointer to the peripheral registers structure.
+ *
+ * @returns Current SPIS status.
+ */
+__STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_reg);
+
+/**
+ * @brief Function for configuring SPIS pins.
+ *
+ * If a given signal is not needed, pass the @ref NRF_SPIS_PIN_NOT_CONNECTED
+ * value instead of its pin number.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @param[in] sck_pin   SCK pin number.
+ * @param[in] mosi_pin  MOSI pin number.
+ * @param[in] miso_pin  MISO pin number.
+ * @param[in] csn_pin   CSN pin number.
+ */
+__STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg,
+                                       uint32_t sck_pin,
+                                       uint32_t mosi_pin,
+                                       uint32_t miso_pin,
+                                       uint32_t csn_pin);
+
+/**
+ * @brief Function for setting the transmit buffer.
+ *
+ * @param[in]  p_reg    Pointer to the peripheral registers structure.
+ * @param[in]  p_buffer Pointer to the buffer that contains the data to send.
+ * @param[in]  length   Maximum number of data bytes to transmit.
+ */
+__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,
+                                            uint8_t const * p_buffer,
+                                            uint8_t         length);
+
+/**
+ * @brief Function for setting the receive buffer.
+ *
+ * @param[in] p_reg    Pointer to the peripheral registers structure.
+ * @param[in] p_buffer Pointer to the buffer for received data.
+ * @param[in] length   Maximum number of data bytes to receive.
+ */
+__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg,
+                                            uint8_t * p_buffer,
+                                            uint8_t   length);
+
+/**
+ * @brief Function for getting the number of bytes transmitted
+ *        in the last granted transaction.
+ *
+ * @param[in]  p_reg    Pointer to the peripheral registers structure.
+ *
+ * @returns Number of bytes transmitted.
+ */
+__STATIC_INLINE uint8_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg);
+
+/**
+ * @brief Function for getting the number of bytes received
+ *        in the last granted transaction.
+ *
+ * @param[in]  p_reg    Pointer to the peripheral registers structure.
+ *
+ * @returns Number of bytes received.
+ */
+__STATIC_INLINE uint8_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg);
+
+/**
+ * @brief Function for setting the SPI configuration.
+ *
+ * @param[in] p_reg         Pointer to the peripheral registers structure.
+ * @param[in] spi_mode      SPI mode.
+ * @param[in] spi_bit_order SPI bit order.
+ */
+__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg,
+                                        nrf_spis_mode_t spi_mode,
+                                        nrf_spis_bit_order_t spi_bit_order);
+
+/**
+ * @brief Function for setting the default character.
+ *
+ * @param[in] p_reg  Pointer to the peripheral registers structure.
+ * @param[in] def    Default character that is clocked out in case of
+ *                   an overflow of the RXD buffer.
+ */
+__STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_reg,
+                                      uint8_t def);
+
+/**
+ * @brief Function for setting the over-read character.
+ *
+ * @param[in] p_reg  Pointer to the peripheral registers structure.
+ * @param[in] orc    Over-read character that is clocked out in case of
+ *                   an over-read of the TXD buffer.
+ */
+__STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_reg,
+                                      uint8_t orc);
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg,
+                                           nrf_spis_task_t spis_task)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_task)) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg,
+                                                   nrf_spis_task_t spis_task)
+{
+    return (uint32_t)p_reg + (uint32_t)spis_task;
+}
+
+__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type *  p_reg,
+                                          nrf_spis_event_t spis_event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_event)) = 0x0UL;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_event));
+    (void)dummy;
+#endif
+}
+
+__STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg,
+                                          nrf_spis_event_t spis_event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)spis_event);
+}
+
+__STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg,
+                                                    nrf_spis_event_t spis_event)
+{
+    return (uint32_t)p_reg + (uint32_t)spis_event;
+}
+
+__STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg,
+                                            uint32_t spis_shorts_mask)
+{
+    p_reg->SHORTS |= spis_shorts_mask;
+}
+
+__STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg,
+                                             uint32_t spis_shorts_mask)
+{
+    p_reg->SHORTS &= ~(spis_shorts_mask);
+}
+
+__STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_reg,
+                                         uint32_t spis_int_mask)
+{
+    p_reg->INTENSET = spis_int_mask;
+}
+
+__STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_reg,
+                                          uint32_t spis_int_mask)
+{
+    p_reg->INTENCLR = spis_int_mask;
+}
+
+__STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg,
+                                               nrf_spis_int_mask_t spis_int)
+{
+    return (bool)(p_reg->INTENSET & spis_int);
+}
+
+__STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_reg)
+{
+    p_reg->ENABLE = (SPIS_ENABLE_ENABLE_Enabled << SPIS_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_reg)
+{
+    p_reg->ENABLE = (SPIS_ENABLE_ENABLE_Disabled << SPIS_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type * p_reg)
+{
+    return (nrf_spis_semstat_t) ((p_reg->SEMSTAT & SPIS_SEMSTAT_SEMSTAT_Msk)
+                                 >> SPIS_SEMSTAT_SEMSTAT_Pos);
+}
+
+__STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_reg)
+{
+    return (nrf_spis_status_mask_t) p_reg->STATUS;
+}
+
+__STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg,
+                                       uint32_t sck_pin,
+                                       uint32_t mosi_pin,
+                                       uint32_t miso_pin,
+                                       uint32_t csn_pin)
+{
+    p_reg->PSELSCK  = sck_pin;
+    p_reg->PSELMOSI = mosi_pin;
+    p_reg->PSELMISO = miso_pin;
+    p_reg->PSELCSN  = csn_pin;
+}
+
+__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,
+                                            uint8_t const * p_buffer,
+                                            uint8_t         length)
+{
+    p_reg->TXDPTR = (uint32_t)p_buffer;
+    p_reg->MAXTX  = length;
+}
+
+__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg,
+                                            uint8_t * p_buffer,
+                                            uint8_t   length)
+{
+    p_reg->RXDPTR = (uint32_t)p_buffer;
+    p_reg->MAXRX  = length;
+}
+
+__STATIC_INLINE uint8_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg)
+{
+    return (uint8_t) p_reg->AMOUNTTX;
+}
+
+__STATIC_INLINE uint8_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg)
+{
+    return (uint8_t) p_reg->AMOUNTRX;
+}
+
+__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg,
+                                        nrf_spis_mode_t spi_mode,
+                                        nrf_spis_bit_order_t spi_bit_order)
+{
+    uint32_t config = (spi_bit_order == NRF_SPIS_BIT_ORDER_MSB_FIRST ?
+        SPIS_CONFIG_ORDER_MsbFirst : SPIS_CONFIG_ORDER_LsbFirst);
+
+    switch (spi_mode)
+    {
+    default:
+    case NRF_SPIS_MODE_0:
+        config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) |
+                  (SPIS_CONFIG_CPHA_Leading    << SPIS_CONFIG_CPHA_Pos);
+        break;
+
+    case NRF_SPIS_MODE_1:
+        config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) |
+                  (SPIS_CONFIG_CPHA_Trailing   << SPIS_CONFIG_CPHA_Pos);
+        break;
+
+    case NRF_SPIS_MODE_2:
+        config |= (SPIS_CONFIG_CPOL_ActiveLow  << SPIS_CONFIG_CPOL_Pos) |
+                  (SPIS_CONFIG_CPHA_Leading    << SPIS_CONFIG_CPHA_Pos);
+        break;
+
+    case NRF_SPIS_MODE_3:
+        config |= (SPIS_CONFIG_CPOL_ActiveLow  << SPIS_CONFIG_CPOL_Pos) |
+                  (SPIS_CONFIG_CPHA_Trailing   << SPIS_CONFIG_CPHA_Pos);
+        break;
+    }
+    p_reg->CONFIG = config;
+}
+
+__STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_reg,
+                                      uint8_t orc)
+{
+    p_reg->ORC = orc;
+}
+
+__STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_reg,
+                                      uint8_t def)
+{
+    p_reg->DEF = def;
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_SPIS_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_temp.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,90 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_TEMP_H__
+#define NRF_TEMP_H__
+
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+* @defgroup nrf_temperature TEMP (temperature) abstraction
+* @{
+* @ingroup nrf_drivers temperature_example
+* @brief Temperature module init and read functions.
+*
+*/
+
+/**@cond NO_DOXYGEN */
+#define MASK_SIGN           (0x00000200UL)
+#define MASK_SIGN_EXTENSION (0xFFFFFC00UL)
+
+/**
+ * @brief Function for preparing the temp module for temperature measurement.
+ *
+ * This function initializes the TEMP module and writes to the hidden configuration register.
+ */
+static __INLINE void nrf_temp_init(void)
+{
+    /**@note Workaround for PAN_028 rev2.0A anomaly 31 - TEMP: Temperature offset value has to be manually loaded to the TEMP module */
+    *(uint32_t *) 0x4000C504 = 0;
+}
+
+/**
+ * @brief Function for reading temperature measurement.
+ *
+ * The function reads the 10 bit 2's complement value and transforms it to a 32 bit 2's complement value.
+ */
+static __INLINE int32_t nrf_temp_read(void)
+{
+    /**@note Workaround for PAN_028 rev2.0A anomaly 28 - TEMP: Negative measured values are not represented correctly */
+    return ((NRF_TEMP->TEMP & MASK_SIGN) != 0) ? (NRF_TEMP->TEMP | MASK_SIGN_EXTENSION) : (NRF_TEMP->TEMP);
+}
+/**@endcond */
+
+/** @} */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_timer.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,629 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @defgroup nrf_timer_hal Timer HAL
+ * @{
+ * @ingroup nrf_timer
+ *
+ * @brief Hardware access layer for accessing the timer peripheral.
+ */
+
+#ifndef NRF_TIMER_H__
+#define NRF_TIMER_H__
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "nrf_peripherals.h"
+#include "nrf.h"
+#include "nrf_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @brief Macro for validating the correctness of the BIT_WIDTH setting.
+ */
+
+#define TIMER_MAX_SIZE(id) CONCAT_3(TIMER, id, _MAX_SIZE)
+
+#define TIMER_BIT_WIDTH_MAX(id, bit_width) \
+    (TIMER_MAX_SIZE(id) == 8   ? (bit_width == NRF_TIMER_BIT_WIDTH_8)  :  \
+    (TIMER_MAX_SIZE(id) == 16  ? (bit_width == NRF_TIMER_BIT_WIDTH_8)  || \
+                                 (bit_width == NRF_TIMER_BIT_WIDTH_16)  : \
+    (TIMER_MAX_SIZE(id) == 24  ? (bit_width == NRF_TIMER_BIT_WIDTH_8)  || \
+                                 (bit_width == NRF_TIMER_BIT_WIDTH_16) || \
+                                 (bit_width == NRF_TIMER_BIT_WIDTH_24) :  \
+    (TIMER_MAX_SIZE(id) == 32  ? (bit_width == NRF_TIMER_BIT_WIDTH_8)  || \
+                                 (bit_width == NRF_TIMER_BIT_WIDTH_16) || \
+                                 (bit_width == NRF_TIMER_BIT_WIDTH_24) || \
+                                 (bit_width == NRF_TIMER_BIT_WIDTH_32) :  \
+    false))))
+
+#if TIMER_COUNT > 3
+#define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) (                \
+       ((p_reg == NRF_TIMER0) && (TIMER_BIT_WIDTH_MAX(0, bit_width)))   \
+    || ((p_reg == NRF_TIMER1) && (TIMER_BIT_WIDTH_MAX(1, bit_width)))   \
+    || ((p_reg == NRF_TIMER2) && (TIMER_BIT_WIDTH_MAX(2, bit_width)))   \
+    || ((p_reg == NRF_TIMER3) && (TIMER_BIT_WIDTH_MAX(3, bit_width)))   \
+    || ((p_reg == NRF_TIMER4) && (TIMER_BIT_WIDTH_MAX(4, bit_width))) )
+
+#else
+#define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) (             \
+       ((p_reg == NRF_TIMER0) && TIMER_BIT_WIDTH_MAX(0, bit_width))  \
+    || ((p_reg == NRF_TIMER1) && TIMER_BIT_WIDTH_MAX(1, bit_width))  \
+    || ((p_reg == NRF_TIMER2) && TIMER_BIT_WIDTH_MAX(2, bit_width)) )
+
+#endif
+
+/**
+ * @brief Macro for getting the number of capture/compare channels available
+ *        in a given timer instance.
+ */
+#define NRF_TIMER_CC_CHANNEL_COUNT(id)  CONCAT_3(TIMER, id, _CC_NUM)
+
+/**
+ * @brief Timer tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30 -esym(628,__INTADDR__)*/
+    NRF_TIMER_TASK_START    = offsetof(NRF_TIMER_Type, TASKS_START),      ///< Task for starting the timer.
+    NRF_TIMER_TASK_STOP     = offsetof(NRF_TIMER_Type, TASKS_STOP),       ///< Task for stopping the timer.
+    NRF_TIMER_TASK_COUNT    = offsetof(NRF_TIMER_Type, TASKS_COUNT),      ///< Task for incrementing the timer (in counter mode).
+    NRF_TIMER_TASK_CLEAR    = offsetof(NRF_TIMER_Type, TASKS_CLEAR),      ///< Task for resetting the timer value.
+    NRF_TIMER_TASK_SHUTDOWN = offsetof(NRF_TIMER_Type, TASKS_SHUTDOWN),   ///< Task for powering off the timer.
+    NRF_TIMER_TASK_CAPTURE0 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[0]), ///< Task for capturing the timer value on channel 0.
+    NRF_TIMER_TASK_CAPTURE1 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[1]), ///< Task for capturing the timer value on channel 1.
+    NRF_TIMER_TASK_CAPTURE2 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[2]), ///< Task for capturing the timer value on channel 2.
+    NRF_TIMER_TASK_CAPTURE3 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[3]), ///< Task for capturing the timer value on channel 3.
+#if (TIMER_COUNT > 3) || defined(__SDK_DOXYGEN__)
+    NRF_TIMER_TASK_CAPTURE4 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[4]), ///< Task for capturing the timer value on channel 4.
+    NRF_TIMER_TASK_CAPTURE5 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[5]), ///< Task for capturing the timer value on channel 5.
+#endif
+    /*lint -restore*/
+} nrf_timer_task_t;
+
+/**
+ * @brief Timer events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_TIMER_EVENT_COMPARE0 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[0]), ///< Event from compare channel 0.
+    NRF_TIMER_EVENT_COMPARE1 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[1]), ///< Event from compare channel 1.
+    NRF_TIMER_EVENT_COMPARE2 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[2]), ///< Event from compare channel 2.
+    NRF_TIMER_EVENT_COMPARE3 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[3]), ///< Event from compare channel 3.
+#if (TIMER_COUNT > 3) || defined(__SDK_DOXYGEN__)
+    NRF_TIMER_EVENT_COMPARE4 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[4]), ///< Event from compare channel 4.
+    NRF_TIMER_EVENT_COMPARE5 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[5]), ///< Event from compare channel 5.
+#endif
+    /*lint -restore*/
+} nrf_timer_event_t;
+
+/**
+ * @brief Types of timer shortcuts.
+ */
+typedef enum
+{
+    NRF_TIMER_SHORT_COMPARE0_STOP_MASK = TIMER_SHORTS_COMPARE0_STOP_Msk,   ///< Shortcut for stopping the timer based on compare 0.
+    NRF_TIMER_SHORT_COMPARE1_STOP_MASK = TIMER_SHORTS_COMPARE1_STOP_Msk,   ///< Shortcut for stopping the timer based on compare 1.
+    NRF_TIMER_SHORT_COMPARE2_STOP_MASK = TIMER_SHORTS_COMPARE2_STOP_Msk,   ///< Shortcut for stopping the timer based on compare 2.
+    NRF_TIMER_SHORT_COMPARE3_STOP_MASK = TIMER_SHORTS_COMPARE3_STOP_Msk,   ///< Shortcut for stopping the timer based on compare 3.
+#if (TIMER_COUNT > 3) || defined(__SDK_DOXYGEN__)
+    NRF_TIMER_SHORT_COMPARE4_STOP_MASK = TIMER_SHORTS_COMPARE4_STOP_Msk,   ///< Shortcut for stopping the timer based on compare 4.
+    NRF_TIMER_SHORT_COMPARE5_STOP_MASK = TIMER_SHORTS_COMPARE5_STOP_Msk,   ///< Shortcut for stopping the timer based on compare 5.
+#endif
+    NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK = TIMER_SHORTS_COMPARE0_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 0.
+    NRF_TIMER_SHORT_COMPARE1_CLEAR_MASK = TIMER_SHORTS_COMPARE1_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 1.
+    NRF_TIMER_SHORT_COMPARE2_CLEAR_MASK = TIMER_SHORTS_COMPARE2_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 2.
+    NRF_TIMER_SHORT_COMPARE3_CLEAR_MASK = TIMER_SHORTS_COMPARE3_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 3.
+#if (TIMER_COUNT > 3) || defined(__SDK_DOXYGEN__)
+    NRF_TIMER_SHORT_COMPARE4_CLEAR_MASK = TIMER_SHORTS_COMPARE4_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 4.
+    NRF_TIMER_SHORT_COMPARE5_CLEAR_MASK = TIMER_SHORTS_COMPARE5_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 5.
+#endif
+} nrf_timer_short_mask_t;
+
+/**
+ * @brief Timer modes.
+ */
+typedef enum
+{
+    NRF_TIMER_MODE_TIMER             = TIMER_MODE_MODE_Timer,           ///< Timer mode: timer.
+    NRF_TIMER_MODE_COUNTER           = TIMER_MODE_MODE_Counter,         ///< Timer mode: counter.
+#if defined(TIMER_MODE_MODE_LowPowerCounter) || defined(__SDK_DOXYGEN__)
+    NRF_TIMER_MODE_LOW_POWER_COUNTER = TIMER_MODE_MODE_LowPowerCounter, ///< Timer mode: low-power counter.
+#endif
+} nrf_timer_mode_t;
+
+/**
+ * @brief Timer bit width.
+ */
+typedef enum
+{
+    NRF_TIMER_BIT_WIDTH_8  = TIMER_BITMODE_BITMODE_08Bit, ///< Timer bit width 8 bit.
+    NRF_TIMER_BIT_WIDTH_16 = TIMER_BITMODE_BITMODE_16Bit, ///< Timer bit width 16 bit.
+    NRF_TIMER_BIT_WIDTH_24 = TIMER_BITMODE_BITMODE_24Bit, ///< Timer bit width 24 bit.
+    NRF_TIMER_BIT_WIDTH_32 = TIMER_BITMODE_BITMODE_32Bit  ///< Timer bit width 32 bit.
+} nrf_timer_bit_width_t;
+
+/**
+ * @brief Timer prescalers.
+ */
+typedef enum
+{
+    NRF_TIMER_FREQ_16MHz = 0, ///< Timer frequency 16 MHz.
+    NRF_TIMER_FREQ_8MHz,      ///< Timer frequency 8 MHz.
+    NRF_TIMER_FREQ_4MHz,      ///< Timer frequency 4 MHz.
+    NRF_TIMER_FREQ_2MHz,      ///< Timer frequency 2 MHz.
+    NRF_TIMER_FREQ_1MHz,      ///< Timer frequency 1 MHz.
+    NRF_TIMER_FREQ_500kHz,    ///< Timer frequency 500 kHz.
+    NRF_TIMER_FREQ_250kHz,    ///< Timer frequency 250 kHz.
+    NRF_TIMER_FREQ_125kHz,    ///< Timer frequency 125 kHz.
+    NRF_TIMER_FREQ_62500Hz,   ///< Timer frequency 62500 Hz.
+    NRF_TIMER_FREQ_31250Hz    ///< Timer frequency 31250 Hz.
+} nrf_timer_frequency_t;
+
+/**
+ * @brief Timer capture/compare channels.
+ */
+typedef enum
+{
+    NRF_TIMER_CC_CHANNEL0 = 0, ///< Timer capture/compare channel 0.
+    NRF_TIMER_CC_CHANNEL1,     ///< Timer capture/compare channel 1.
+    NRF_TIMER_CC_CHANNEL2,     ///< Timer capture/compare channel 2.
+    NRF_TIMER_CC_CHANNEL3,     ///< Timer capture/compare channel 3.
+#if (TIMER_COUNT > 3) || defined(__SDK_DOXYGEN__)
+    NRF_TIMER_CC_CHANNEL4,     ///< Timer capture/compare channel 4.
+    NRF_TIMER_CC_CHANNEL5,     ///< Timer capture/compare channel 5.
+#endif
+} nrf_timer_cc_channel_t;
+
+/**
+ * @brief Timer interrupts.
+ */
+typedef enum
+{
+    NRF_TIMER_INT_COMPARE0_MASK = TIMER_INTENSET_COMPARE0_Msk, ///< Timer interrupt from compare event on channel 0.
+    NRF_TIMER_INT_COMPARE1_MASK = TIMER_INTENSET_COMPARE1_Msk, ///< Timer interrupt from compare event on channel 1.
+    NRF_TIMER_INT_COMPARE2_MASK = TIMER_INTENSET_COMPARE2_Msk, ///< Timer interrupt from compare event on channel 2.
+    NRF_TIMER_INT_COMPARE3_MASK = TIMER_INTENSET_COMPARE3_Msk, ///< Timer interrupt from compare event on channel 3.
+#if (TIMER_COUNT > 3) || defined(__SDK_DOXYGEN__)
+    NRF_TIMER_INT_COMPARE4_MASK = TIMER_INTENSET_COMPARE4_Msk, ///< Timer interrupt from compare event on channel 4.
+    NRF_TIMER_INT_COMPARE5_MASK = TIMER_INTENSET_COMPARE5_Msk, ///< Timer interrupt from compare event on channel 5.
+#endif
+} nrf_timer_int_mask_t;
+
+
+/**
+ * @brief Function for activating a specific timer task.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param[in] task    Task to activate.
+ */
+__STATIC_INLINE void nrf_timer_task_trigger(NRF_TIMER_Type * p_reg,
+                                            nrf_timer_task_t task);
+
+/**
+ * @brief Function for getting the address of a specific timer task register.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param[in] task    Requested task.
+ *
+ * @return Address of the specified task register.
+ */
+__STATIC_INLINE uint32_t * nrf_timer_task_address_get(NRF_TIMER_Type * p_reg,
+                                                      nrf_timer_task_t task);
+
+/**
+ * @brief Function for clearing a specific timer event.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param[in] event   Event to clear.
+ */
+__STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_reg,
+                                           nrf_timer_event_t event);
+
+/**
+ * @brief Function for checking the state of a specific timer event.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param[in] event   Event to check.
+ *
+ * @retval true  If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type * p_reg,
+                                           nrf_timer_event_t event);
+
+/**
+ * @brief Function for getting the address of a specific timer event register.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param[in] event   Requested event.
+ *
+ * @return Address of the specified event register.
+ */
+__STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_reg,
+                                                       nrf_timer_event_t event);
+
+/**
+ * @brief Function for enabling specified shortcuts.
+ *
+ * @param[in] p_reg             Pointer to the peripheral registers structure.
+ * @param[in] timer_shorts_mask Shortcuts to enable.
+ */
+__STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_reg,
+                                             uint32_t timer_shorts_mask);
+
+/**
+ * @brief Function for disabling specified shortcuts.
+ *
+ * @param[in] p_reg             Pointer to the peripheral registers structure.
+ * @param[in] timer_shorts_mask Shortcuts to disable.
+ */
+__STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_reg,
+                                              uint32_t timer_shorts_mask);
+
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] p_reg          Pointer to the peripheral registers structure.
+ * @param[in] timer_int_mask Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_reg,
+                                          uint32_t timer_int_mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] p_reg          Pointer to the peripheral registers structure.
+ * @param[in] timer_int_mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_timer_int_disable(NRF_TIMER_Type * p_reg,
+                                           uint32_t timer_int_mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @param[in] timer_int Interrupt to check.
+ *
+ * @retval true  If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_timer_int_enable_check(NRF_TIMER_Type * p_reg,
+                                                uint32_t timer_int);
+
+/**
+ * @brief Function for setting the timer mode.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param[in] mode    Timer mode.
+ */
+__STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_reg,
+                                        nrf_timer_mode_t mode);
+
+/**
+ * @brief Function for retrieving the timer mode.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ *
+ * @return Timer mode.
+ */
+__STATIC_INLINE nrf_timer_mode_t nrf_timer_mode_get(NRF_TIMER_Type * p_reg);
+
+/**
+ * @brief Function for setting the timer bit width.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @param[in] bit_width Timer bit width.
+ */
+__STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_reg,
+                                             nrf_timer_bit_width_t bit_width);
+
+/**
+ * @brief Function for retrieving the timer bit width.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ *
+ * @return Timer bit width.
+ */
+__STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type * p_reg);
+
+/**
+ * @brief Function for setting the timer frequency.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @param[in] frequency Timer frequency.
+ */
+__STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_reg,
+                                             nrf_timer_frequency_t frequency);
+
+/**
+ * @brief Function for retrieving the timer frequency.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ *
+ * @return Timer frequency.
+ */
+__STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type * p_reg);
+
+/**
+ * @brief Function for writing the capture/compare register for a specified channel.
+ *
+ * @param[in] p_reg      Pointer to the peripheral registers structure.
+ * @param[in] cc_channel Requested capture/compare channel.
+ * @param[in] cc_value   Value to write to the capture/compare register.
+ */
+__STATIC_INLINE void nrf_timer_cc_write(NRF_TIMER_Type * p_reg,
+                                        nrf_timer_cc_channel_t cc_channel,
+                                        uint32_t               cc_value);
+
+/**
+ * @brief Function for retrieving the capture/compare value for a specified channel.
+ *
+ * @param[in] p_reg      Pointer to the peripheral registers structure.
+ * @param[in] cc_channel Requested capture/compare channel.
+ *
+ * @return Value from the requested capture/compare register.
+ */
+__STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_reg,
+                                           nrf_timer_cc_channel_t cc_channel);
+
+/**
+ * @brief Function for getting a specific timer capture task.
+ *
+ * @param[in] channel Capture channel.
+ *
+ * @return Capture task.
+ */
+__STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel);
+
+/**
+ * @brief Function for getting a specific timer compare event.
+ *
+ * @param[in] channel Compare channel.
+ *
+ * @return Compare event.
+ */
+__STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel);
+
+/**
+ * @brief Function for getting a specific timer compare interrupt.
+ *
+ * @param[in] channel Compare channel.
+ *
+ * @return Compare interrupt.
+ */
+__STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel);
+
+/**
+ * @brief Function for calculating the number of timer ticks for a given time
+ *        (in microseconds) and timer frequency.
+ *
+ * @param[in] time_us   Time in microseconds.
+ * @param[in] frequency Timer frequency.
+ *
+ * @return Number of timer ticks.
+ */
+__STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us,
+                                               nrf_timer_frequency_t frequency);
+
+/**
+ * @brief Function for calculating the number of timer ticks for a given time
+ *        (in milliseconds) and timer frequency.
+ *
+ * @param[in] time_ms   Time in milliseconds.
+ * @param[in] frequency Timer frequency.
+ *
+ * @return Number of timer ticks.
+ */
+__STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms,
+                                               nrf_timer_frequency_t frequency);
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_timer_task_trigger(NRF_TIMER_Type * p_reg,
+                                            nrf_timer_task_t task)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t * nrf_timer_task_address_get(NRF_TIMER_Type * p_reg,
+                                                      nrf_timer_task_t task)
+{
+    return (uint32_t *)((uint8_t *)p_reg + (uint32_t)task);
+}
+
+__STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_reg,
+                                           nrf_timer_event_t event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
+    (void)dummy;
+#endif
+}
+
+__STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type * p_reg,
+                                           nrf_timer_event_t event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_reg,
+                                                       nrf_timer_event_t event)
+{
+    return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_reg,
+                                             uint32_t timer_shorts_mask)
+{
+    p_reg->SHORTS |= timer_shorts_mask;
+}
+
+__STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_reg,
+                                              uint32_t timer_shorts_mask)
+{
+    p_reg->SHORTS &= ~(timer_shorts_mask);
+}
+
+__STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_reg,
+                                          uint32_t timer_int_mask)
+{
+    p_reg->INTENSET = timer_int_mask;
+}
+
+__STATIC_INLINE void nrf_timer_int_disable(NRF_TIMER_Type * p_reg,
+                                           uint32_t timer_int_mask)
+{
+    p_reg->INTENCLR = timer_int_mask;
+}
+
+__STATIC_INLINE bool nrf_timer_int_enable_check(NRF_TIMER_Type * p_reg,
+                                                uint32_t timer_int)
+{
+    return (bool)(p_reg->INTENSET & timer_int);
+}
+
+__STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_reg,
+                                        nrf_timer_mode_t mode)
+{
+    p_reg->MODE = (p_reg->MODE & ~TIMER_MODE_MODE_Msk) |
+                    ((mode << TIMER_MODE_MODE_Pos) & TIMER_MODE_MODE_Msk);
+}
+
+__STATIC_INLINE nrf_timer_mode_t nrf_timer_mode_get(NRF_TIMER_Type * p_reg)
+{
+    return (nrf_timer_mode_t)(p_reg->MODE);
+}
+
+__STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_reg,
+                                             nrf_timer_bit_width_t bit_width)
+{
+    p_reg->BITMODE = (p_reg->BITMODE & ~TIMER_BITMODE_BITMODE_Msk) |
+                       ((bit_width << TIMER_BITMODE_BITMODE_Pos) &
+                            TIMER_BITMODE_BITMODE_Msk);
+}
+
+__STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type * p_reg)
+{
+    return (nrf_timer_bit_width_t)(p_reg->BITMODE);
+}
+
+__STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_reg,
+                                             nrf_timer_frequency_t frequency)
+{
+    p_reg->PRESCALER = (p_reg->PRESCALER & ~TIMER_PRESCALER_PRESCALER_Msk) |
+                         ((frequency << TIMER_PRESCALER_PRESCALER_Pos) &
+                              TIMER_PRESCALER_PRESCALER_Msk);
+}
+
+__STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type * p_reg)
+{
+    return (nrf_timer_frequency_t)(p_reg->PRESCALER);
+}
+
+__STATIC_INLINE void nrf_timer_cc_write(NRF_TIMER_Type * p_reg,
+                                        nrf_timer_cc_channel_t cc_channel,
+                                        uint32_t               cc_value)
+{
+    p_reg->CC[cc_channel] = cc_value;
+}
+
+__STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_reg,
+                                           nrf_timer_cc_channel_t cc_channel)
+{
+    return (uint32_t)p_reg->CC[cc_channel];
+}
+
+__STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel)
+{
+    return (nrf_timer_task_t)
+        ((uint32_t)NRF_TIMER_TASK_CAPTURE0 + (channel * sizeof(uint32_t)));
+}
+
+__STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel)
+{
+    return (nrf_timer_event_t)
+        ((uint32_t)NRF_TIMER_EVENT_COMPARE0 + (channel * sizeof(uint32_t)));
+}
+
+__STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel)
+{
+    return (nrf_timer_int_mask_t)
+        ((uint32_t)NRF_TIMER_INT_COMPARE0_MASK << channel);
+}
+
+__STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us,
+                                               nrf_timer_frequency_t frequency)
+{
+    // The "frequency" parameter here is actually the prescaler value, and the
+    // timer runs at the following frequency: f = 16 MHz / 2^prescaler.
+    uint32_t prescaler = (uint32_t)frequency;
+    ASSERT(time_us <= (UINT32_MAX / 16UL));
+    return ((time_us * 16UL) >> prescaler);
+}
+
+__STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms,
+                                               nrf_timer_frequency_t frequency)
+{
+    // The "frequency" parameter here is actually the prescaler value, and the
+    // timer runs at the following frequency: f = 16000 kHz / 2^prescaler.
+    uint32_t prescaler = (uint32_t)frequency;
+    ASSERT(time_ms <= (UINT32_MAX / 16000UL));
+    return ((time_ms * 16000UL) >> prescaler);
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_TIMER_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_twi.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,451 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_TWI_H__
+#define NRF_TWI_H__
+
+/**
+ * @defgroup nrf_twi_hal TWI HAL
+ * @{
+ * @ingroup nrf_twi
+ *
+ * @brief Hardware access layer for managing the TWI peripheral.
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+#include "nrf_peripherals.h"
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief TWI tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_TWI_TASK_STARTRX = offsetof(NRF_TWI_Type, TASKS_STARTRX), ///< Start TWI receive sequence.
+    NRF_TWI_TASK_STARTTX = offsetof(NRF_TWI_Type, TASKS_STARTTX), ///< Start TWI transmit sequence.
+    NRF_TWI_TASK_STOP    = offsetof(NRF_TWI_Type, TASKS_STOP),    ///< Stop TWI transaction.
+    NRF_TWI_TASK_SUSPEND = offsetof(NRF_TWI_Type, TASKS_SUSPEND), ///< Suspend TWI transaction.
+    NRF_TWI_TASK_RESUME  = offsetof(NRF_TWI_Type, TASKS_RESUME)   ///< Resume TWI transaction.
+    /*lint -restore*/
+} nrf_twi_task_t;
+
+/**
+ * @brief TWI events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_TWI_EVENT_STOPPED   = offsetof(NRF_TWI_Type, EVENTS_STOPPED),  ///< TWI stopped.
+    NRF_TWI_EVENT_RXDREADY  = offsetof(NRF_TWI_Type, EVENTS_RXDREADY), ///< TWI RXD byte received.
+    NRF_TWI_EVENT_TXDSENT   = offsetof(NRF_TWI_Type, EVENTS_TXDSENT),  ///< TWI TXD byte sent.
+    NRF_TWI_EVENT_ERROR     = offsetof(NRF_TWI_Type, EVENTS_ERROR),    ///< TWI error.
+    NRF_TWI_EVENT_BB        = offsetof(NRF_TWI_Type, EVENTS_BB),       ///< TWI byte boundary, generated before each byte that is sent or received.
+    NRF_TWI_EVENT_SUSPENDED = offsetof(NRF_TWI_Type, EVENTS_SUSPENDED) ///< TWI entered the suspended state.
+    /*lint -restore*/
+} nrf_twi_event_t;
+
+/**
+ * @brief TWI shortcuts.
+ */
+typedef enum
+{
+    NRF_TWI_SHORT_BB_SUSPEND_MASK = TWI_SHORTS_BB_SUSPEND_Msk, ///< Shortcut between BB event and SUSPEND task.
+    NRF_TWI_SHORT_BB_STOP_MASK    = TWI_SHORTS_BB_STOP_Msk,    ///< Shortcut between BB event and STOP task.
+} nrf_twi_short_mask_t;
+
+/**
+ * @brief TWI interrupts.
+ */
+typedef enum
+{
+    NRF_TWI_INT_STOPPED_MASK    = TWI_INTENSET_STOPPED_Msk,  ///< Interrupt on STOPPED event.
+    NRF_TWI_INT_RXDREADY_MASK   = TWI_INTENSET_RXDREADY_Msk, ///< Interrupt on RXDREADY event.
+    NRF_TWI_INT_TXDSENT_MASK    = TWI_INTENSET_TXDSENT_Msk,  ///< Interrupt on TXDSENT event.
+    NRF_TWI_INT_ERROR_MASK      = TWI_INTENSET_ERROR_Msk,    ///< Interrupt on ERROR event.
+    NRF_TWI_INT_BB_MASK         = TWI_INTENSET_BB_Msk,       ///< Interrupt on BB event.
+    NRF_TWI_INT_SUSPENDED_MASK  = TWI_INTENSET_SUSPENDED_Msk ///< Interrupt on SUSPENDED event.
+} nrf_twi_int_mask_t;
+
+/**
+ * @brief TWI error source.
+ */
+typedef enum
+{
+    NRF_TWI_ERROR_ADDRESS_NACK = TWI_ERRORSRC_ANACK_Msk,  ///< NACK received after sending the address.
+    NRF_TWI_ERROR_DATA_NACK    = TWI_ERRORSRC_DNACK_Msk,  ///< NACK received after sending a data byte.
+    NRF_TWI_ERROR_OVERRUN      = TWI_ERRORSRC_OVERRUN_Msk ///< Overrun error.
+                                                          /**< A new byte was received before the previous byte was read
+                                                           *   from the RXD register (previous data is lost). */
+} nrf_twi_error_t;
+
+/**
+ * @brief TWI master clock frequency.
+ */
+typedef enum
+{
+    NRF_TWI_FREQ_100K = TWI_FREQUENCY_FREQUENCY_K100, ///< 100 kbps.
+    NRF_TWI_FREQ_250K = TWI_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
+    NRF_TWI_FREQ_400K = TWI_FREQUENCY_FREQUENCY_K400  ///< 400 kbps.
+} nrf_twi_frequency_t;
+
+
+/**
+ * @brief Function for activating a specific TWI task.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] task  Task to activate.
+ */
+__STATIC_INLINE void nrf_twi_task_trigger(NRF_TWI_Type * p_reg,
+                                          nrf_twi_task_t task);
+
+/**
+ * @brief Function for getting the address of a specific TWI task register.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] task  Requested task.
+ *
+ * @return Address of the specified task register.
+ */
+__STATIC_INLINE uint32_t * nrf_twi_task_address_get(NRF_TWI_Type * p_reg,
+                                                    nrf_twi_task_t task);
+
+/**
+ * @brief Function for clearing a specific TWI event.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] event Event to clear.
+ */
+__STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type * p_reg,
+                                         nrf_twi_event_t event);
+
+/**
+ * @brief Function for checking the state of a specific event.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] event Event to check.
+ *
+ * @retval true If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type  * p_reg,
+                                         nrf_twi_event_t event);
+
+/**
+ * @brief Function for getting the address of a specific TWI event register.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] event Requested event.
+ *
+ * @return Address of the specified event register.
+ */
+__STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type  * p_reg,
+                                                     nrf_twi_event_t event);
+
+/**
+ * @brief Function for enabling specified shortcuts.
+ *
+ * @param[in] p_reg       Pointer to the peripheral registers structure.
+ * @param[in] shorts_mask Shortcuts to enable.
+ */
+__STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_reg,
+                                           uint32_t shorts_mask);
+
+/**
+ * @brief Function for disabling specified shortcuts.
+ *
+ * @param[in] p_reg       Pointer to the peripheral registers structure.
+ * @param[in] shorts_mask Shortcuts to disable.
+ */
+__STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_reg,
+                                            uint32_t shorts_mask);
+
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] p_reg    Pointer to the peripheral registers structure.
+ * @param[in] int_mask Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_reg,
+                                        uint32_t int_mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] p_reg    Pointer to the peripheral registers structure.
+ * @param[in] int_mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_reg,
+                                         uint32_t int_mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param[in] p_reg    Pointer to the peripheral registers structure.
+ * @param[in] int_mask Interrupt to check.
+ *
+ * @retval true  If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_reg,
+                                              nrf_twi_int_mask_t int_mask);
+
+/**
+ * @brief Function for enabling the TWI peripheral.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_twi_enable(NRF_TWI_Type * p_reg);
+
+/**
+ * @brief Function for disabling the TWI peripheral.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_reg);
+
+/**
+ * @brief Function for configuring TWI pins.
+ *
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param[in] scl_pin SCL pin number.
+ * @param[in] sda_pin SDA pin number.
+ */
+__STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_reg,
+                                      uint32_t scl_pin,
+                                      uint32_t sda_pin);
+
+/**
+ * @brief Function for setting the TWI master clock frequency.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @param[in] frequency TWI frequency.
+ */
+__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_reg,
+                                           nrf_twi_frequency_t frequency);
+
+/**
+ * @brief Function for checking the TWI error source.
+ *
+ * The error flags are cleared after reading.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ *
+ * @return Mask with error source flags.
+ */
+__STATIC_INLINE uint32_t nrf_twi_errorsrc_get_and_clear(NRF_TWI_Type * p_reg);
+
+/**
+ * @brief Function for setting the address to be used in TWI transfers.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param[in] address Address to be used in transfers.
+ */
+__STATIC_INLINE void nrf_twi_address_set(NRF_TWI_Type * p_reg, uint8_t address);
+
+/**
+ * @brief Function for reading data received by TWI.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ *
+ * @return Received data.
+ */
+__STATIC_INLINE uint8_t nrf_twi_rxd_get(NRF_TWI_Type * p_reg);
+
+/**
+ * @brief Function for writing data to be transmitted by TWI.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] data  Data to be transmitted.
+ */
+__STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_reg, uint8_t data);
+
+__STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_reg,
+                                        uint32_t shorts_mask);
+
+/**
+ * @}
+ */
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_twi_task_trigger(NRF_TWI_Type * p_reg,
+                                          nrf_twi_task_t task)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t * nrf_twi_task_address_get(NRF_TWI_Type * p_reg,
+                                                    nrf_twi_task_t task)
+{
+    return (uint32_t *)((uint8_t *)p_reg + (uint32_t)task);
+}
+
+__STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type  * p_reg,
+                                         nrf_twi_event_t event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
+    (void)dummy;
+#endif
+}
+
+__STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type  * p_reg,
+                                         nrf_twi_event_t event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type  * p_reg,
+                                                     nrf_twi_event_t event)
+{
+    return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_reg,
+                                           uint32_t shorts_mask)
+{
+    p_reg->SHORTS |= shorts_mask;
+}
+
+__STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_reg,
+                                            uint32_t shorts_mask)
+{
+    p_reg->SHORTS &= ~(shorts_mask);
+}
+
+__STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_reg,
+                                        uint32_t int_mask)
+{
+    p_reg->INTENSET = int_mask;
+}
+
+__STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_reg,
+                                         uint32_t int_mask)
+{
+    p_reg->INTENCLR = int_mask;
+}
+
+__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_reg,
+                                              nrf_twi_int_mask_t int_mask)
+{
+    return (bool)(p_reg->INTENSET & int_mask);
+}
+
+__STATIC_INLINE void nrf_twi_enable(NRF_TWI_Type * p_reg)
+{
+    p_reg->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_reg)
+{
+    p_reg->ENABLE = (TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_reg,
+                                      uint32_t scl_pin,
+                                      uint32_t sda_pin)
+{
+#if defined(TWI_PSEL_SCL_CONNECT_Pos)
+    p_reg->PSEL.SCL = scl_pin;
+#else
+    p_reg->PSELSCL = scl_pin;
+#endif
+
+#if defined(TWI_PSEL_SDA_CONNECT_Pos)
+    p_reg->PSEL.SDA = sda_pin;
+#else
+    p_reg->PSELSDA = sda_pin;
+#endif
+}
+
+__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_reg,
+                                           nrf_twi_frequency_t frequency)
+{
+    p_reg->FREQUENCY = frequency;
+}
+
+__STATIC_INLINE uint32_t nrf_twi_errorsrc_get_and_clear(NRF_TWI_Type * p_reg)
+{
+    uint32_t error_source = p_reg->ERRORSRC;
+
+    // [error flags are cleared by writing '1' on their position]
+    p_reg->ERRORSRC = error_source;
+
+    return error_source;
+}
+
+__STATIC_INLINE void nrf_twi_address_set(NRF_TWI_Type * p_reg, uint8_t address)
+{
+    p_reg->ADDRESS = address;
+}
+
+__STATIC_INLINE uint8_t nrf_twi_rxd_get(NRF_TWI_Type * p_reg)
+{
+    return (uint8_t)p_reg->RXD;
+}
+
+__STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_reg, uint8_t data)
+{
+    p_reg->TXD = data;
+}
+
+__STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_reg,
+                                        uint32_t shorts_mask)
+{
+    p_reg->SHORTS = shorts_mask;
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_TWI_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_twim.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,517 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_TWIM_H__
+#define NRF_TWIM_H__
+
+/**
+ * @defgroup nrf_twim_hal TWIM HAL
+ * @{
+ * @ingroup nrf_twi
+ *
+ * @brief Hardware access layer for managing the TWIM peripheral.
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief TWIM tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_TWIM_TASK_STARTRX = offsetof(NRF_TWIM_Type, TASKS_STARTRX), ///< Start TWI receive sequence.
+    NRF_TWIM_TASK_STARTTX = offsetof(NRF_TWIM_Type, TASKS_STARTTX), ///< Start TWI transmit sequence.
+    NRF_TWIM_TASK_STOP    = offsetof(NRF_TWIM_Type, TASKS_STOP),    ///< Stop TWI transaction.
+    NRF_TWIM_TASK_SUSPEND = offsetof(NRF_TWIM_Type, TASKS_SUSPEND), ///< Suspend TWI transaction.
+    NRF_TWIM_TASK_RESUME  = offsetof(NRF_TWIM_Type, TASKS_RESUME)   ///< Resume TWI transaction.
+    /*lint -restore*/
+} nrf_twim_task_t;
+
+/**
+ * @brief TWIM events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_TWIM_EVENT_STOPPED   = offsetof(NRF_TWIM_Type, EVENTS_STOPPED),   ///< TWI stopped.
+    NRF_TWIM_EVENT_ERROR     = offsetof(NRF_TWIM_Type, EVENTS_ERROR),     ///< TWI error.
+    NRF_TWIM_EVENT_SUSPENDED = 0x148,                                     ///< TWI suspended.
+    NRF_TWIM_EVENT_RXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_RXSTARTED), ///< Receive sequence started.
+    NRF_TWIM_EVENT_TXSTARTED = offsetof(NRF_TWIM_Type, EVENTS_TXSTARTED), ///< Transmit sequence started.
+    NRF_TWIM_EVENT_LASTRX    = offsetof(NRF_TWIM_Type, EVENTS_LASTRX),    ///< Byte boundary, starting to receive the last byte.
+    NRF_TWIM_EVENT_LASTTX    = offsetof(NRF_TWIM_Type, EVENTS_LASTTX)     ///< Byte boundary, starting to transmit the last byte.
+    /*lint -restore*/
+} nrf_twim_event_t;
+
+/**
+ * @brief TWIM shortcuts.
+ */
+typedef enum
+{
+    NRF_TWIM_SHORT_LASTTX_STARTRX_MASK = TWIM_SHORTS_LASTTX_STARTRX_Msk, ///< Shortcut between LASTTX event and STARTRX task.
+    NRF_TWIM_SHORT_LASTTX_SUSPEND_MASK = TWIM_SHORTS_LASTTX_SUSPEND_Msk, ///< Shortcut between LASTTX event and SUSPEND task.
+    NRF_TWIM_SHORT_LASTTX_STOP_MASK    = TWIM_SHORTS_LASTTX_STOP_Msk,    ///< Shortcut between LASTTX event and STOP task.
+    NRF_TWIM_SHORT_LASTRX_STARTTX_MASK = TWIM_SHORTS_LASTRX_STARTTX_Msk, ///< Shortcut between LASTRX event and STARTTX task.
+    NRF_TWIM_SHORT_LASTRX_STOP_MASK    = TWIM_SHORTS_LASTRX_STOP_Msk     ///< Shortcut between LASTRX event and STOP task.
+} nrf_twim_short_mask_t;
+
+/**
+ * @brief TWIM interrupts.
+ */
+typedef enum
+{
+    NRF_TWIM_INT_STOPPED_MASK   = TWIM_INTENSET_STOPPED_Msk,   ///< Interrupt on STOPPED event.
+    NRF_TWIM_INT_ERROR_MASK     = TWIM_INTENSET_ERROR_Msk,     ///< Interrupt on ERROR event.
+    NRF_TWIM_INT_SUSPENDED_MASK = (1 << 18),                   ///< Interrupt on SUSPENDED event.
+    NRF_TWIM_INT_RXSTARTED_MASK = TWIM_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event.
+    NRF_TWIM_INT_TXSTARTED_MASK = TWIM_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event.
+    NRF_TWIM_INT_LASTRX_MASK    = TWIM_INTENSET_LASTRX_Msk,    ///< Interrupt on LASTRX event.
+    NRF_TWIM_INT_LASTTX_MASK    = TWIM_INTENSET_LASTTX_Msk     ///< Interrupt on LASTTX event.
+} nrf_twim_int_mask_t;
+
+/**
+ * @brief TWIM master clock frequency.
+ */
+typedef enum
+{
+    NRF_TWIM_FREQ_100K = TWIM_FREQUENCY_FREQUENCY_K100, ///< 100 kbps.
+    NRF_TWIM_FREQ_250K = TWIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
+    NRF_TWIM_FREQ_400K = TWIM_FREQUENCY_FREQUENCY_K400  ///< 400 kbps.
+} nrf_twim_frequency_t;
+
+/**
+ * @brief TWIM error source.
+ */
+typedef enum
+{
+    NRF_TWIM_ERROR_ADDRESS_NACK = TWIM_ERRORSRC_ANACK_Msk, ///< NACK received after sending the address.
+    NRF_TWIM_ERROR_DATA_NACK    = TWIM_ERRORSRC_DNACK_Msk  ///< NACK received after sending a data byte.
+} nrf_twim_error_t;
+
+
+/**
+ * @brief Function for activating a specific TWIM task.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] task   Task to activate.
+ */
+__STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_reg,
+                                           nrf_twim_task_t task);
+
+/**
+ * @brief Function for getting the address of a specific TWIM task register.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] task   Requested task.
+ *
+ * @return Address of the specified task register.
+ */
+__STATIC_INLINE uint32_t * nrf_twim_task_address_get(NRF_TWIM_Type * p_reg,
+                                                     nrf_twim_task_t task);
+
+/**
+ * @brief Function for clearing a specific TWIM event.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] event  Event to clear.
+ */
+__STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_reg,
+                                          nrf_twim_event_t event);
+
+/**
+ * @brief Function for checking the state of a specific TWIM event.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] event  Event to check.
+ *
+ * @retval true  If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type * p_reg,
+                                          nrf_twim_event_t event);
+
+/**
+ * @brief Function for getting the address of a specific TWIM event register.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param[in] event  Requested event.
+ *
+ * @return Address of the specified event register.
+ */
+__STATIC_INLINE uint32_t * nrf_twim_event_address_get(NRF_TWIM_Type  * p_reg,
+                                                      nrf_twim_event_t event);
+
+/**
+ * @brief Function for enabling specified shortcuts.
+ *
+ * @param[in] p_reg      Pointer to the peripheral registers structure.
+ * @param[in] shorts_mask Shortcuts to enable.
+ */
+__STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg,
+                                            uint32_t shorts_mask);
+
+/**
+ * @brief Function for disabling specified shortcuts.
+ *
+ * @param[in] p_reg      Pointer to the peripheral registers structure.
+ * @param[in] shorts_mask Shortcuts to disable.
+ */
+__STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg,
+                                             uint32_t shorts_mask);
+
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param[in] int_mask Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_reg,
+                                         uint32_t int_mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param[in] int_mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_reg,
+                                          uint32_t int_mask);
+
+/**
+ * @brief Function for checking the state of a given interrupt.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param[in] int_mask Interrupt to check.
+ *
+ * @retval true  If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_twim_int_enable_check(NRF_TWIM_Type * p_reg,
+                                               nrf_twim_int_mask_t int_mask);
+
+/**
+ * @brief Function for enabling the TWIM peripheral.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_reg);
+
+/**
+ * @brief Function for disabling the TWIM peripheral.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_reg);
+
+/**
+ * @brief Function for configuring TWI pins.
+ *
+ *
+ * @param[in] p_reg  Pointer to the peripheral registers structure.
+ * @param[in] scl_pin SCL pin number.
+ * @param[in] sda_pin SDA pin number.
+ */
+__STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_reg,
+                                       uint32_t scl_pin,
+                                       uint32_t sda_pin);
+
+/**
+ * @brief Function for setting the TWI master clock frequency.
+ *
+ * @param[in] p_reg    Pointer to the peripheral registers structure.
+ * @param[in] frequency TWI frequency.
+ */
+__STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_reg,
+                                            nrf_twim_frequency_t frequency);
+
+/**
+ * @brief Function for checking the TWI error source.
+ *
+ * The error flags are cleared after reading.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ *
+ * @return Mask with error source flags.
+ */
+__STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_reg);
+
+/**
+ * @brief Function for setting the address to be used in TWI transfers.
+ *
+ * @param[in] p_reg  Pointer to the peripheral registers structure.
+ * @param[in] address Address to be used in transfers.
+ */
+__STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_reg,
+                                          uint8_t address);
+
+/**
+ * @brief Function for setting the transmit buffer.
+ *
+ * @param[in]  p_reg   Pointer to the peripheral registers structure.
+ * @param[in]  p_buffer Pointer to the buffer with data to send.
+ * @param[in]  length   Maximum number of data bytes to transmit.
+ */
+__STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,
+                                            uint8_t const * p_buffer,
+                                            uint8_t         length);
+
+/**
+ * @brief Function for setting the receive buffer.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param[in] p_buffer Pointer to the buffer for received data.
+ * @param[in] length   Maximum number of data bytes to receive.
+ */
+__STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg,
+                                            uint8_t * p_buffer,
+                                            uint8_t   length);
+
+__STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,
+                                         uint32_t shorts_mask);
+
+__STATIC_INLINE uint32_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_reg);
+
+__STATIC_INLINE uint32_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_reg);
+
+/**
+ * @brief Function for enabling the TX list feature.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_reg);
+
+/**
+ * @brief Function for disabling the TX list feature.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_reg);
+
+/**
+ * @brief Function for enabling the RX list feature.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_reg);
+
+/**
+ * @brief Function for disabling the RX list feature.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_reg);
+
+/**
+ * @}
+ */
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_twim_task_trigger(NRF_TWIM_Type * p_reg,
+                                           nrf_twim_task_t task)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t * nrf_twim_task_address_get(NRF_TWIM_Type * p_reg,
+                                                     nrf_twim_task_t task)
+{
+    return (uint32_t *)((uint8_t *)p_reg + (uint32_t)task);
+}
+
+__STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_reg,
+                                          nrf_twim_event_t event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
+    (void)dummy;
+#endif
+}
+
+__STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type * p_reg,
+                                          nrf_twim_event_t event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE uint32_t * nrf_twim_event_address_get(NRF_TWIM_Type  * p_reg,
+                                                      nrf_twim_event_t event)
+{
+    return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE void nrf_twim_shorts_enable(NRF_TWIM_Type * p_reg,
+                                            uint32_t shorts_mask)
+{
+    p_reg->SHORTS |= shorts_mask;
+}
+
+__STATIC_INLINE void nrf_twim_shorts_disable(NRF_TWIM_Type * p_reg,
+                                             uint32_t shorts_mask)
+{
+    p_reg->SHORTS &= ~(shorts_mask);
+}
+
+__STATIC_INLINE void nrf_twim_int_enable(NRF_TWIM_Type * p_reg,
+                                         uint32_t int_mask)
+{
+    p_reg->INTENSET = int_mask;
+}
+
+__STATIC_INLINE void nrf_twim_int_disable(NRF_TWIM_Type * p_reg,
+                                          uint32_t int_mask)
+{
+    p_reg->INTENCLR = int_mask;
+}
+
+__STATIC_INLINE bool nrf_twim_int_enable_check(NRF_TWIM_Type * p_reg,
+                                               nrf_twim_int_mask_t int_mask)
+{
+    return (bool)(p_reg->INTENSET & int_mask);
+}
+
+__STATIC_INLINE void nrf_twim_enable(NRF_TWIM_Type * p_reg)
+{
+    p_reg->ENABLE = (TWIM_ENABLE_ENABLE_Enabled << TWIM_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_twim_disable(NRF_TWIM_Type * p_reg)
+{
+    p_reg->ENABLE = (TWIM_ENABLE_ENABLE_Disabled << TWIM_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_reg,
+                                       uint32_t scl_pin,
+                                       uint32_t sda_pin)
+{
+    p_reg->PSEL.SCL = scl_pin;
+    p_reg->PSEL.SDA = sda_pin;
+}
+
+__STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_reg,
+                                            nrf_twim_frequency_t frequency)
+{
+    p_reg->FREQUENCY = frequency;
+}
+
+__STATIC_INLINE uint32_t nrf_twim_errorsrc_get_and_clear(NRF_TWIM_Type * p_reg)
+{
+    uint32_t error_source = p_reg->ERRORSRC;
+
+    // [error flags are cleared by writing '1' on their position]
+    p_reg->ERRORSRC = error_source;
+
+    return error_source;
+}
+
+__STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_reg,
+                                          uint8_t address)
+{
+    p_reg->ADDRESS = address;
+}
+
+__STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,
+                                            uint8_t const * p_buffer,
+                                            uint8_t         length)
+{
+    p_reg->TXD.PTR    = (uint32_t)p_buffer;
+    p_reg->TXD.MAXCNT = length;
+}
+
+__STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg,
+                                            uint8_t * p_buffer,
+                                            uint8_t   length)
+{
+    p_reg->RXD.PTR    = (uint32_t)p_buffer;
+    p_reg->RXD.MAXCNT = length;
+}
+
+__STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,
+                                         uint32_t shorts_mask)
+{
+    p_reg->SHORTS = shorts_mask;
+}
+
+__STATIC_INLINE uint32_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_reg)
+{
+    return p_reg->TXD.AMOUNT;
+}
+
+__STATIC_INLINE uint32_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_reg)
+{
+    return p_reg->RXD.AMOUNT;
+}
+
+__STATIC_INLINE void nrf_twim_tx_list_enable(NRF_TWIM_Type * p_reg)
+{
+    p_reg->TXD.LIST = 1;
+}
+
+__STATIC_INLINE void nrf_twim_tx_list_disable(NRF_TWIM_Type * p_reg)
+{
+    p_reg->TXD.LIST = 0;
+}
+
+__STATIC_INLINE void nrf_twim_rx_list_enable(NRF_TWIM_Type * p_reg)
+{
+    p_reg->RXD.LIST = 1;
+}
+
+__STATIC_INLINE void nrf_twim_rx_list_disable(NRF_TWIM_Type * p_reg)
+{
+    p_reg->RXD.LIST = 0;
+}
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_TWIM_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_twis.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,705 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @ingroup nrf_twis
+ * @defgroup nrf_twis_hal TWIS HAL
+ * @{
+ *
+ * @brief @tagAPI52 Hardware access layer for Two Wire Interface Slave with EasyDMA
+ * (TWIS) peripheral.
+ */
+#ifndef NRF_TWIS_H__
+#define NRF_TWIS_H__
+
+#include "nrf.h"
+#include "sdk_config.h"
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief TWIS tasks
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_TWIS_TASK_STOP      = offsetof(NRF_TWIS_Type, TASKS_STOP),      /**< Stop TWIS transaction */
+    NRF_TWIS_TASK_SUSPEND   = offsetof(NRF_TWIS_Type, TASKS_SUSPEND),   /**< Suspend TWIS transaction */
+    NRF_TWIS_TASK_RESUME    = offsetof(NRF_TWIS_Type, TASKS_RESUME),    /**< Resume TWIS transaction */
+    NRF_TWIS_TASK_PREPARERX = offsetof(NRF_TWIS_Type, TASKS_PREPARERX), /**< Prepare the TWIS slave to respond to a write command */
+    NRF_TWIS_TASK_PREPARETX = offsetof(NRF_TWIS_Type, TASKS_PREPARETX)  /**< Prepare the TWIS slave to respond to a read command */
+    /*lint -restore*/
+} nrf_twis_task_t;
+
+/**
+ * @brief TWIS events
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_TWIS_EVENT_STOPPED   = offsetof(NRF_TWIS_Type, EVENTS_STOPPED),   /**< TWIS stopped */
+    NRF_TWIS_EVENT_ERROR     = offsetof(NRF_TWIS_Type, EVENTS_ERROR),     /**< TWIS error */
+    NRF_TWIS_EVENT_RXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_RXSTARTED), /**< Receive sequence started */
+    NRF_TWIS_EVENT_TXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_TXSTARTED), /**< Transmit sequence started */
+    NRF_TWIS_EVENT_WRITE     = offsetof(NRF_TWIS_Type, EVENTS_WRITE),     /**< Write command received */
+    NRF_TWIS_EVENT_READ      = offsetof(NRF_TWIS_Type, EVENTS_READ)       /**< Read command received */
+    /*lint -restore*/
+} nrf_twis_event_t;
+
+/**
+ * @brief TWIS shortcuts
+ */
+typedef enum
+{
+    NRF_TWIS_SHORT_WRITE_SUSPEND_MASK   = TWIS_SHORTS_WRITE_SUSPEND_Msk,   /**< Shortcut between WRITE event and SUSPEND task */
+    NRF_TWIS_SHORT_READ_SUSPEND_MASK    = TWIS_SHORTS_READ_SUSPEND_Msk,    /**< Shortcut between READ event and SUSPEND task */
+} nrf_twis_short_mask_t;
+
+/**
+ * @brief TWIS interrupts
+ */
+typedef enum
+{
+    NRF_TWIS_INT_STOPPED_MASK   = TWIS_INTEN_STOPPED_Msk,   /**< Interrupt on STOPPED event */
+    NRF_TWIS_INT_ERROR_MASK     = TWIS_INTEN_ERROR_Msk,     /**< Interrupt on ERROR event */
+    NRF_TWIS_INT_RXSTARTED_MASK = TWIS_INTEN_RXSTARTED_Msk, /**< Interrupt on RXSTARTED event */
+    NRF_TWIS_INT_TXSTARTED_MASK = TWIS_INTEN_TXSTARTED_Msk, /**< Interrupt on TXSTARTED event */
+    NRF_TWIS_INT_WRITE_MASK     = TWIS_INTEN_WRITE_Msk,     /**< Interrupt on WRITE event */
+    NRF_TWIS_INT_READ_MASK      = TWIS_INTEN_READ_Msk,      /**< Interrupt on READ event */
+} nrf_twis_int_mask_t;
+
+/**
+ * @brief TWIS error source
+ */
+typedef enum
+{
+    NRF_TWIS_ERROR_OVERFLOW  = TWIS_ERRORSRC_OVERFLOW_Msk, /**< RX buffer overflow detected, and prevented */
+    NRF_TWIS_ERROR_DATA_NACK = TWIS_ERRORSRC_DNACK_Msk,    /**< NACK sent after receiving a data byte */
+    NRF_TWIS_ERROR_OVERREAD  = TWIS_ERRORSRC_OVERREAD_Msk  /**< TX buffer over-read detected, and prevented */
+} nrf_twis_error_t;
+
+/**
+ * @brief TWIS address matching configuration
+ */
+typedef enum
+{
+    NRF_TWIS_CONFIG_ADDRESS0_MASK  = TWIS_CONFIG_ADDRESS0_Msk, /**< Enable or disable address matching on ADDRESS[0] */
+    NRF_TWIS_CONFIG_ADDRESS1_MASK  = TWIS_CONFIG_ADDRESS1_Msk, /**< Enable or disable address matching on ADDRESS[1] */
+    NRF_TWIS_CONFIG_ADDRESS01_MASK = TWIS_CONFIG_ADDRESS0_Msk | TWIS_CONFIG_ADDRESS1_Msk /**< Enable both address matching */
+} nrf_twis_config_addr_mask_t;
+
+/**
+ * @brief Variable type to hold amount of data for EasyDMA
+ *
+ * Variable of the minimum size that can hold the amount of data to transfer.
+ *
+ * @note
+ * Defined to make it simple to change if EasyDMA would be updated to support more data in
+ * the future devices to.
+ */
+typedef uint8_t nrf_twis_amount_t;
+
+/**
+ * @brief Smallest variable type to hold TWI address
+ *
+ * Variable of the minimum size that can hold single TWI address.
+ *
+ * @note
+ * Defined to make it simple to change if new TWI would support for example
+ * 10 bit addressing mode.
+ */
+typedef uint8_t nrf_twis_address_t;
+
+
+/**
+ * @brief Function for activating a specific TWIS task.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param     task   Task.
+ */
+__STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * const p_reg, nrf_twis_task_t task);
+
+/**
+ * @brief Function for returning the address of a specific TWIS task register.
+ *
+ * @param[in]  p_reg Pointer to the peripheral registers structure.
+ * @param      task   Task.
+ *
+ * @return Task address.
+ */
+__STATIC_INLINE uint32_t nrf_twis_task_address_get(
+        NRF_TWIS_Type const * const p_reg,
+        nrf_twis_task_t      task);
+
+/**
+ * @brief Function for clearing a specific event.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param     event  Event.
+ */
+__STATIC_INLINE void nrf_twis_event_clear(
+        NRF_TWIS_Type     * const p_reg,
+        nrf_twis_event_t   event);
+/**
+ * @brief Function for returning the state of a specific event.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param     event  Event.
+ *
+ * @retval true If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_twis_event_check(
+        NRF_TWIS_Type const * const p_reg,
+        nrf_twis_event_t     event);
+
+
+/**
+ * @brief Function for getting and clearing the state of specific event
+ *
+ * This function checks the state of the event and clears it.
+ * @param[in,out] p_reg Pointer to the peripheral registers structure.
+ * @param         event Event.
+ *
+ * @retval true If the event was set.
+ * @retval false If the event was not set.
+ */
+__STATIC_INLINE bool nrf_twis_event_get_and_clear(
+        NRF_TWIS_Type    * const p_reg,
+        nrf_twis_event_t   event);
+
+
+/**
+ * @brief Function for returning the address of a specific TWIS event register.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param     event  Event.
+ *
+ * @return Address.
+ */
+__STATIC_INLINE uint32_t nrf_twis_event_address_get(
+        NRF_TWIS_Type const * const p_reg,
+        nrf_twis_event_t     event);
+
+/**
+ * @brief Function for setting a shortcut.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @param     short_mask Shortcuts mask.
+ */
+__STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * const p_reg, uint32_t short_mask);
+
+/**
+ * @brief Function for clearing shortcuts.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @param     short_mask Shortcuts mask.
+ */
+__STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * const p_reg, uint32_t short_mask);
+
+/**
+ * @brief Get the shorts mask
+ *
+ * Function returns shorts register.
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @return Flags of currently enabled shortcuts
+ */
+__STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type * const p_reg);
+
+/**
+ * @brief Function for enabling selected interrupts.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param     int_mask Interrupts mask.
+ */
+__STATIC_INLINE void nrf_twis_int_enable(NRF_TWIS_Type * const p_reg, uint32_t int_mask);
+
+/**
+ * @brief Function for retrieving the state of selected interrupts.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param     int_mask Interrupts mask.
+ *
+ * @retval true If any of selected interrupts is enabled.
+ * @retval false If none of selected interrupts is enabled.
+ */
+__STATIC_INLINE bool nrf_twis_int_enable_check(NRF_TWIS_Type const * const p_reg, uint32_t int_mask);
+
+/**
+ * @brief Function for disabling selected interrupts.
+ *
+ * @param[in] p_reg   Pointer to the peripheral registers structure.
+ * @param     int_mask Interrupts mask.
+ */
+__STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * const p_reg, uint32_t int_mask);
+
+/**
+ * @brief Function for retrieving and clearing the TWIS error source.
+ *
+ * @attention Error sources are cleared after read.
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @return Error source mask with values from @ref nrf_twis_error_t.
+ */
+__STATIC_INLINE uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_reg);
+
+/**
+ * @brief Get information which of addresses matched
+ *
+ * Function returns index in the address table
+ * that points to the address that already matched.
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @return Index of matched address
+ */
+__STATIC_INLINE uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg);
+
+/**
+ * @brief Function for enabling TWIS.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_twis_enable(NRF_TWIS_Type * const p_reg);
+
+/**
+ * @brief Function for disabling TWIS.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * const p_reg);
+
+/**
+ * @brief Function for configuring TWIS pins.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param scl SCL pin number.
+ * @param sda SDA pin number.
+ */
+__STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * const p_reg, uint32_t scl, uint32_t sda);
+
+/**
+ * @brief Function for setting the receive buffer.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param     p_buf  Pointer to the buffer for received data.
+ * @param     length Maximum number of data bytes to receive.
+ */
+__STATIC_INLINE void nrf_twis_rx_buffer_set(
+        NRF_TWIS_Type     * const p_reg,
+        uint8_t           * p_buf,
+        nrf_twis_amount_t   length);
+
+/**
+ * @brief Function that prepares TWIS for receiving
+ *
+ * This function sets receive buffer and then sets NRF_TWIS_TASK_PREPARERX task.
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param     p_buf  Pointer to the buffer for received data.
+ * @param     length Maximum number of data bytes to receive.
+ */
+__STATIC_INLINE void nrf_twis_rx_prepare(
+        NRF_TWIS_Type     * const p_reg,
+        uint8_t           * p_buf,
+        nrf_twis_amount_t   length);
+
+/**
+ * @brief Function for getting number of bytes received in the last transaction.
+ *
+ * @param[in] p_reg TWIS instance.
+ * @return Amount of bytes received.
+ * */
+__STATIC_INLINE nrf_twis_amount_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * const p_reg);
+
+/**
+ * @brief Function for setting the transmit buffer.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param     p_buf  Pointer to the buffer with data to send.
+ * @param     length Maximum number of data bytes to transmit.
+ */
+__STATIC_INLINE void nrf_twis_tx_buffer_set(
+        NRF_TWIS_Type     * const p_reg,
+        uint8_t const     * p_buf,
+        nrf_twis_amount_t   length);
+
+/**
+ * @brief Function that prepares TWIS for transmitting
+ *
+ * This function sets transmit buffer and then sets NRF_TWIS_TASK_PREPARETX task.
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param     p_buf  Pointer to the buffer with data to send.
+ * @param     length Maximum number of data bytes to transmit.
+ */
+__STATIC_INLINE void nrf_twis_tx_prepare(
+        NRF_TWIS_Type     * const p_reg,
+        uint8_t const     * p_buf,
+        nrf_twis_amount_t   length);
+
+/**
+ * @brief Function for getting number of bytes transmitted in the last transaction.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @return Amount of bytes transmitted.
+ */
+__STATIC_INLINE nrf_twis_amount_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * const p_reg);
+
+/**
+ * @brief Function for setting slave address
+ *
+ * Function sets the selected address for this TWI interface.
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param     n Index of address to set
+ * @param     addr Addres to set
+ * @sa nrf_twis_config_address_set
+ * @sa nrf_twis_config_address_get
+ */
+__STATIC_INLINE void nrf_twis_address_set(
+        NRF_TWIS_Type      * const p_reg,
+        uint_fast8_t         n,
+        nrf_twis_address_t   addr);
+
+/**
+ * @brief Function for retrieving configured slave address
+ *
+ * Function gets the selected address for this TWI interface.
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @param n   Index of address to get
+ */
+__STATIC_INLINE nrf_twis_address_t nrf_twis_address_get(
+        NRF_TWIS_Type const * const p_reg,
+        uint_fast8_t          n);
+
+/**
+ * @brief Function for setting the device address configuration.
+ *
+ * @param[in] p_reg    Pointer to the peripheral registers structure.
+ * @param     addr_mask Mask of address indexes of what device should answer to.
+ *
+ * @sa nrf_twis_address_set
+ */
+__STATIC_INLINE void nrf_twis_config_address_set(
+        NRF_TWIS_Type              * const p_reg,
+        nrf_twis_config_addr_mask_t        addr_mask);
+
+/**
+ * @brief Function for retrieving the device address configuration.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ *
+ * @return Mask of address indexes of what device should answer to.
+ */
+__STATIC_INLINE nrf_twis_config_addr_mask_t nrf_twis_config_address_get(
+        NRF_TWIS_Type const * const p_reg);
+
+/**
+ * @brief Function for setting the over-read character.
+ *
+ * @param[in] p_reg    Pointer to the peripheral registers structure.
+ * @param[in] orc       Over-read character. Character clocked out in case of
+ *                      over-read of the TXD buffer.
+ */
+__STATIC_INLINE void nrf_twis_orc_set(
+        NRF_TWIS_Type * const p_reg,
+        uint8_t         orc);
+
+/**
+ * @brief Function for setting the over-read character.
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ *
+ * @return Over-read character configured for selected instance.
+ */
+__STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * const p_reg);
+
+
+/** @} */ /*  End of nrf_twis_hal */
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+/* ------------------------------------------------------------------------------------------------
+ *  Internal functions
+ */
+
+/**
+ * @internal
+ * @brief Internal function for getting task/event register address
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @oaram     offset Offset of the register from the instance beginning
+ *
+ * @attention offset has to be modulo 4 value. In other case we can get hardware fault.
+ * @return Pointer to the register
+ */
+__STATIC_INLINE volatile uint32_t* nrf_twis_getRegPtr(NRF_TWIS_Type * const p_reg, uint32_t offset)
+{
+    return (volatile uint32_t*)((uint8_t *)p_reg + (uint32_t)offset);
+}
+
+/**
+ * @internal
+ * @brief Internal function for getting task/event register address - constant version
+ *
+ * @param[in] p_reg Pointer to the peripheral registers structure.
+ * @oaram     offset Offset of the register from the instance beginning
+ *
+ * @attention offset has to be modulo 4 value. In other case we can get hardware fault.
+ * @return Pointer to the register
+ */
+__STATIC_INLINE volatile const uint32_t* nrf_twis_getRegPtr_c(NRF_TWIS_Type const * const p_reg, uint32_t offset)
+{
+    return (volatile const uint32_t*)((uint8_t *)p_reg + (uint32_t)offset);
+}
+
+
+/* ------------------------------------------------------------------------------------------------
+ *  Interface functions definitions
+ */
+
+
+void nrf_twis_task_trigger(NRF_TWIS_Type * const p_reg, nrf_twis_task_t task)
+{
+    *(nrf_twis_getRegPtr(p_reg, (uint32_t)task)) = 1UL;
+}
+
+uint32_t nrf_twis_task_address_get(
+        NRF_TWIS_Type const * const p_reg,
+        nrf_twis_task_t       task)
+{
+    return (uint32_t)nrf_twis_getRegPtr_c(p_reg, (uint32_t)task);
+}
+
+void nrf_twis_event_clear(
+        NRF_TWIS_Type     * const p_reg,
+        nrf_twis_event_t    event)
+{
+    *(nrf_twis_getRegPtr(p_reg, (uint32_t)event)) = 0UL;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
+    (void)dummy;
+#endif
+}
+
+bool nrf_twis_event_check(
+        NRF_TWIS_Type const * const p_reg,
+        nrf_twis_event_t      event)
+{
+    return (bool)*nrf_twis_getRegPtr_c(p_reg, (uint32_t)event);
+}
+
+bool nrf_twis_event_get_and_clear(
+        NRF_TWIS_Type    * const p_reg,
+        nrf_twis_event_t   event)
+{
+    bool ret = nrf_twis_event_check(p_reg, event);
+    if (ret)
+    {
+        nrf_twis_event_clear(p_reg, event);
+    }
+    return ret;
+}
+
+uint32_t nrf_twis_event_address_get(
+        NRF_TWIS_Type const * const p_reg,
+        nrf_twis_event_t      event)
+{
+    return (uint32_t)nrf_twis_getRegPtr_c(p_reg, (uint32_t)event);
+}
+
+void nrf_twis_shorts_enable(NRF_TWIS_Type * const p_reg, uint32_t short_mask)
+{
+    p_reg->SHORTS |= short_mask;
+}
+
+void nrf_twis_shorts_disable(NRF_TWIS_Type * const p_reg, uint32_t short_mask)
+{
+    if (~0U == short_mask)
+    {
+        /* Optimized version for "disable all" */
+        p_reg->SHORTS = 0;
+    }
+    else
+    {
+        p_reg->SHORTS &= ~short_mask;
+    }
+}
+
+uint32_t nrf_twis_shorts_get(NRF_TWIS_Type * const p_reg)
+{
+    return p_reg->SHORTS;
+}
+
+void nrf_twis_int_enable(NRF_TWIS_Type * const p_reg, uint32_t int_mask)
+{
+    p_reg->INTENSET = int_mask;
+}
+
+bool nrf_twis_int_enable_check(NRF_TWIS_Type const * const p_reg, uint32_t int_mask)
+{
+    return (bool)(p_reg->INTENSET & int_mask);
+}
+
+void nrf_twis_int_disable(NRF_TWIS_Type * const p_reg, uint32_t int_mask)
+{
+    p_reg->INTENCLR = int_mask;
+}
+
+uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_reg)
+{
+    uint32_t ret = p_reg->ERRORSRC;
+    p_reg->ERRORSRC = ret;
+    return ret;
+}
+
+uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg)
+{
+    return (uint_fast8_t)p_reg->MATCH;
+}
+
+void nrf_twis_enable(NRF_TWIS_Type * const p_reg)
+{
+    p_reg->ENABLE = (TWIS_ENABLE_ENABLE_Enabled << TWIS_ENABLE_ENABLE_Pos);
+}
+
+void nrf_twis_disable(NRF_TWIS_Type * const p_reg)
+{
+    p_reg->ENABLE = (TWIS_ENABLE_ENABLE_Disabled << TWIS_ENABLE_ENABLE_Pos);
+}
+
+void nrf_twis_pins_set(NRF_TWIS_Type * const p_reg, uint32_t scl, uint32_t sda)
+{
+    p_reg->PSEL.SCL = scl;
+    p_reg->PSEL.SDA = sda;
+}
+
+void nrf_twis_rx_buffer_set(
+        NRF_TWIS_Type     * const p_reg,
+        uint8_t           * p_buf,
+        nrf_twis_amount_t   length)
+{
+    p_reg->RXD.PTR    = (uint32_t)p_buf;
+    p_reg->RXD.MAXCNT = length;
+}
+
+__STATIC_INLINE void nrf_twis_rx_prepare(
+        NRF_TWIS_Type     * const p_reg,
+        uint8_t           * p_buf,
+        nrf_twis_amount_t   length)
+{
+    nrf_twis_rx_buffer_set(p_reg, p_buf, length);
+    nrf_twis_task_trigger(p_reg, NRF_TWIS_TASK_PREPARERX);
+}
+
+nrf_twis_amount_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * const p_reg)
+{
+    return (nrf_twis_amount_t)p_reg->RXD.AMOUNT;
+}
+
+void nrf_twis_tx_buffer_set(
+        NRF_TWIS_Type     * const p_reg,
+        uint8_t const     * p_buf,
+        nrf_twis_amount_t   length)
+{
+    p_reg->TXD.PTR    = (uint32_t)p_buf;
+    p_reg->TXD.MAXCNT = length;
+}
+
+__STATIC_INLINE void nrf_twis_tx_prepare(
+        NRF_TWIS_Type     * const p_reg,
+        uint8_t const     * p_buf,
+        nrf_twis_amount_t   length)
+{
+    nrf_twis_tx_buffer_set(p_reg, p_buf, length);
+    nrf_twis_task_trigger(p_reg, NRF_TWIS_TASK_PREPARETX);
+}
+
+nrf_twis_amount_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * const p_reg)
+{
+    return (nrf_twis_amount_t)p_reg->TXD.AMOUNT;
+}
+
+void nrf_twis_address_set(
+        NRF_TWIS_Type      * const p_reg,
+        uint_fast8_t         n,
+        nrf_twis_address_t   addr)
+{
+    p_reg->ADDRESS[n] = addr;
+}
+
+nrf_twis_address_t nrf_twis_address_get(
+        NRF_TWIS_Type const * const p_reg,
+        uint_fast8_t          n)
+{
+    return (nrf_twis_address_t)p_reg->ADDRESS[n];
+}
+void nrf_twis_config_address_set(
+        NRF_TWIS_Type              * const p_reg,
+        nrf_twis_config_addr_mask_t        addr_mask)
+{
+    /* This is the only configuration in TWIS - just write it without masking */
+    p_reg->CONFIG = addr_mask;
+}
+
+nrf_twis_config_addr_mask_t nrf_twis_config_address_get(NRF_TWIS_Type const * const p_reg)
+{
+    return (nrf_twis_config_addr_mask_t)(p_reg->CONFIG & TWIS_ADDRESS_ADDRESS_Msk);
+}
+
+void nrf_twis_orc_set(
+        NRF_TWIS_Type * const p_reg,
+        uint8_t         orc)
+{
+    p_reg->ORC = orc;
+}
+
+uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * const p_reg)
+{
+    return (uint8_t)p_reg->ORC;
+}
+
+#endif /* SUPPRESS_INLINE_IMPLEMENTATION */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF_TWIS_H__ */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_uart.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,547 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef NRF_UART_H__
+#define NRF_UART_H__
+
+#include "nrf.h"
+#include "nrf_peripherals.h"
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//Temporary defining legacy UART for instance 1
+#define NRF_UART1 (NRF_UART_Type *)NRF_UARTE1
+
+/**
+ * @defgroup nrf_uart_hal UART HAL
+ * @{
+ * @ingroup nrf_uart
+ *
+ * @brief Hardware access layer for accessing the UART peripheral.
+ */
+
+#define NRF_UART_PSEL_DISCONNECTED 0xFFFFFFFF
+
+/**
+ * @enum nrf_uart_task_t
+ * @brief UART tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30 -esym(628,__INTADDR__)*/
+    NRF_UART_TASK_STARTRX = offsetof(NRF_UART_Type, TASKS_STARTRX), /**< Task for starting reception. */
+    NRF_UART_TASK_STOPRX  = offsetof(NRF_UART_Type, TASKS_STOPRX),  /**< Task for stopping reception. */
+    NRF_UART_TASK_STARTTX = offsetof(NRF_UART_Type, TASKS_STARTTX), /**< Task for starting transmission. */
+    NRF_UART_TASK_STOPTX  = offsetof(NRF_UART_Type, TASKS_STOPTX),  /**< Task for stopping transmission. */
+    NRF_UART_TASK_SUSPEND = offsetof(NRF_UART_Type, TASKS_SUSPEND), /**< Task for suspending UART. */
+    /*lint -restore*/
+} nrf_uart_task_t;
+
+/**
+ * @enum nrf_uart_event_t
+ * @brief UART events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_UART_EVENT_CTS    = offsetof(NRF_UART_Type, EVENTS_CTS),   /**< Event from CTS line activation. */
+    NRF_UART_EVENT_NCTS   = offsetof(NRF_UART_Type, EVENTS_NCTS),  /**< Event from CTS line deactivation. */
+    NRF_UART_EVENT_RXDRDY = offsetof(NRF_UART_Type, EVENTS_RXDRDY),/**< Event from data ready in RXD. */
+    NRF_UART_EVENT_TXDRDY = offsetof(NRF_UART_Type, EVENTS_TXDRDY),/**< Event from data sent from TXD. */
+    NRF_UART_EVENT_ERROR  = offsetof(NRF_UART_Type, EVENTS_ERROR), /**< Event from error detection. */
+    NRF_UART_EVENT_RXTO   = offsetof(NRF_UART_Type, EVENTS_RXTO)   /**< Event from receiver timeout. */
+    /*lint -restore*/
+} nrf_uart_event_t;
+
+/**
+ * @enum nrf_uart_int_mask_t
+ * @brief UART interrupts.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_UART_INT_MASK_CTS    = UART_INTENCLR_CTS_Msk,    /**< CTS line activation interrupt. */
+    NRF_UART_INT_MASK_NCTS   = UART_INTENCLR_NCTS_Msk,   /**< CTS line deactivation interrupt. */
+    NRF_UART_INT_MASK_RXDRDY = UART_INTENCLR_RXDRDY_Msk, /**< Data ready in RXD interrupt. */
+    NRF_UART_INT_MASK_TXDRDY = UART_INTENCLR_TXDRDY_Msk,  /**< Data sent from TXD interrupt. */
+    NRF_UART_INT_MASK_ERROR  = UART_INTENCLR_ERROR_Msk,  /**< Error detection interrupt. */
+    NRF_UART_INT_MASK_RXTO   = UART_INTENCLR_RXTO_Msk    /**< Receiver timeout interrupt. */
+    /*lint -restore*/
+} nrf_uart_int_mask_t;
+
+/**
+ * @enum nrf_uart_baudrate_t
+ * @brief Baudrates supported by UART.
+ */
+typedef enum
+{
+#ifdef UARTE_PRESENT
+    NRF_UART_BAUDRATE_1200   =  UARTE_BAUDRATE_BAUDRATE_Baud1200, /**< 1200 baud. */
+    NRF_UART_BAUDRATE_2400   =  UARTE_BAUDRATE_BAUDRATE_Baud2400, /**< 2400 baud. */
+    NRF_UART_BAUDRATE_4800   =  UARTE_BAUDRATE_BAUDRATE_Baud4800, /**< 4800 baud. */
+    NRF_UART_BAUDRATE_9600   =  UARTE_BAUDRATE_BAUDRATE_Baud9600, /**< 9600 baud. */
+    NRF_UART_BAUDRATE_14400  =  UARTE_BAUDRATE_BAUDRATE_Baud14400, /**< 14400 baud. */
+    NRF_UART_BAUDRATE_19200  =  UARTE_BAUDRATE_BAUDRATE_Baud19200, /**< 19200 baud. */
+    NRF_UART_BAUDRATE_28800  =  UARTE_BAUDRATE_BAUDRATE_Baud28800, /**< 28800 baud. */
+    NRF_UART_BAUDRATE_38400  =  UARTE_BAUDRATE_BAUDRATE_Baud38400, /**< 38400 baud. */
+    NRF_UART_BAUDRATE_57600  =  UARTE_BAUDRATE_BAUDRATE_Baud57600, /**< 57600 baud. */
+    NRF_UART_BAUDRATE_76800  =  UARTE_BAUDRATE_BAUDRATE_Baud76800, /**< 76800 baud. */
+    NRF_UART_BAUDRATE_115200 =  UARTE_BAUDRATE_BAUDRATE_Baud115200, /**< 115200 baud. */
+    NRF_UART_BAUDRATE_230400 =  UARTE_BAUDRATE_BAUDRATE_Baud230400, /**< 230400 baud. */
+    NRF_UART_BAUDRATE_250000 =  UARTE_BAUDRATE_BAUDRATE_Baud250000, /**< 250000 baud. */
+    NRF_UART_BAUDRATE_460800 =  UARTE_BAUDRATE_BAUDRATE_Baud460800, /**< 460800 baud. */
+    NRF_UART_BAUDRATE_921600 =  UARTE_BAUDRATE_BAUDRATE_Baud921600, /**< 921600 baud. */
+    NRF_UART_BAUDRATE_1000000 =  UARTE_BAUDRATE_BAUDRATE_Baud1M, /**< 1000000 baud. */
+#else
+    NRF_UART_BAUDRATE_1200   =  UART_BAUDRATE_BAUDRATE_Baud1200, /**< 1200 baud. */
+    NRF_UART_BAUDRATE_2400   =  UART_BAUDRATE_BAUDRATE_Baud2400, /**< 2400 baud. */
+    NRF_UART_BAUDRATE_4800   =  UART_BAUDRATE_BAUDRATE_Baud4800, /**< 4800 baud. */
+    NRF_UART_BAUDRATE_9600   =  UART_BAUDRATE_BAUDRATE_Baud9600, /**< 9600 baud. */
+    NRF_UART_BAUDRATE_14400  =  UART_BAUDRATE_BAUDRATE_Baud14400, /**< 14400 baud. */
+    NRF_UART_BAUDRATE_19200  =  UART_BAUDRATE_BAUDRATE_Baud19200, /**< 19200 baud. */
+    NRF_UART_BAUDRATE_28800  =  UART_BAUDRATE_BAUDRATE_Baud28800, /**< 28800 baud. */
+    NRF_UART_BAUDRATE_38400  =  UART_BAUDRATE_BAUDRATE_Baud38400, /**< 38400 baud. */
+    NRF_UART_BAUDRATE_57600  =  UART_BAUDRATE_BAUDRATE_Baud57600, /**< 57600 baud. */
+    NRF_UART_BAUDRATE_76800  =  UART_BAUDRATE_BAUDRATE_Baud76800, /**< 76800 baud. */
+    NRF_UART_BAUDRATE_115200 =  UART_BAUDRATE_BAUDRATE_Baud115200, /**< 115200 baud. */
+    NRF_UART_BAUDRATE_230400 =  UART_BAUDRATE_BAUDRATE_Baud230400, /**< 230400 baud. */
+    NRF_UART_BAUDRATE_250000 =  UART_BAUDRATE_BAUDRATE_Baud250000, /**< 250000 baud. */
+    NRF_UART_BAUDRATE_460800 =  UART_BAUDRATE_BAUDRATE_Baud460800, /**< 460800 baud. */
+    NRF_UART_BAUDRATE_921600 =  UART_BAUDRATE_BAUDRATE_Baud921600, /**< 921600 baud. */
+    NRF_UART_BAUDRATE_1000000 =  UART_BAUDRATE_BAUDRATE_Baud1M, /**< 1000000 baud. */
+#endif
+} nrf_uart_baudrate_t;
+
+/**
+ * @enum nrf_uart_error_mask_t
+ * @brief Types of UART error masks.
+ */
+typedef enum
+{
+    NRF_UART_ERROR_OVERRUN_MASK = UART_ERRORSRC_OVERRUN_Msk,   /**< Overrun error. */
+    NRF_UART_ERROR_PARITY_MASK  = UART_ERRORSRC_PARITY_Msk,    /**< Parity error. */
+    NRF_UART_ERROR_FRAMING_MASK = UART_ERRORSRC_FRAMING_Msk,   /**< Framing error. */
+    NRF_UART_ERROR_BREAK_MASK   = UART_ERRORSRC_BREAK_Msk,     /**< Break error. */
+} nrf_uart_error_mask_t;
+
+/**
+ * @enum nrf_uart_parity_t
+ * @brief Types of UART parity modes.
+ */
+typedef enum
+{
+    NRF_UART_PARITY_EXCLUDED = UART_CONFIG_PARITY_Excluded << UART_CONFIG_PARITY_Pos, /**< Parity excluded. */
+    NRF_UART_PARITY_INCLUDED = UART_CONFIG_PARITY_Included << UART_CONFIG_PARITY_Pos, /**< Parity included. */
+} nrf_uart_parity_t;
+
+/**
+ * @enum nrf_uart_hwfc_t
+ * @brief Types of UART flow control modes.
+ */
+typedef enum
+{
+    NRF_UART_HWFC_DISABLED = UART_CONFIG_HWFC_Disabled, /**< HW flow control disabled. */
+    NRF_UART_HWFC_ENABLED  = UART_CONFIG_HWFC_Enabled,  /**< HW flow control enabled. */
+} nrf_uart_hwfc_t;
+
+/**
+ * @brief Function for clearing a specific UART event.
+ *
+ * @param[in] p_reg  Pointer to the peripheral registers structure.
+ * @param[in] event  Event to clear.
+ */
+__STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event);
+
+/**
+ * @brief Function for checking the state of a specific UART event.
+ *
+ * @param[in] p_reg  Pointer to the peripheral registers structure.
+ * @param[in] event  Event to check.
+ *
+ * @retval True if event is set, False otherwise.
+ */
+__STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_t event);
+
+/**
+ * @brief Function for returning the address of a specific UART event register.
+ *
+ * @param[in] p_reg  Pointer to the peripheral registers structure.
+ * @param[in] event  Desired event.
+ *
+ * @retval Address of specified event register.
+ */
+__STATIC_INLINE uint32_t nrf_uart_event_address_get(NRF_UART_Type  * p_reg,
+                                                    nrf_uart_event_t  event);
+
+/**
+ * @brief Function for enabling a specific interrupt.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ * @param int_mask Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t int_mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param p_reg     Pointer to the peripheral registers structure.
+ * @param int_mask  Mask of interrupt to check.
+ *
+ * @retval true  If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t int_mask);
+
+/**
+ * @brief Function for disabling specific interrupts.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ * @param int_mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t int_mask);
+
+/**
+ * @brief Function for getting error source mask. Function is clearing error source flags after reading.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ * @return         Mask with error source flags.
+ */
+__STATIC_INLINE uint32_t nrf_uart_errorsrc_get_and_clear(NRF_UART_Type * p_reg);
+
+/**
+ * @brief Function for enabling UART.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_uart_enable(NRF_UART_Type * p_reg);
+
+/**
+ * @brief Function for disabling UART.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_uart_disable(NRF_UART_Type * p_reg);
+
+/**
+ * @brief Function for configuring TX/RX pins.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ * @param pseltxd  TXD pin number.
+ * @param pselrxd  RXD pin number.
+ */
+__STATIC_INLINE void nrf_uart_txrx_pins_set(NRF_UART_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd);
+
+/**
+ * @brief Function for disconnecting TX/RX pins.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_uart_txrx_pins_disconnect(NRF_UART_Type * p_reg);
+
+/**
+ * @brief Function for getting TX pin.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE uint32_t nrf_uart_tx_pin_get(NRF_UART_Type * p_reg);
+
+/**
+ * @brief Function for getting RX pin.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE uint32_t nrf_uart_rx_pin_get(NRF_UART_Type * p_reg);
+
+/**
+ * @brief Function for getting RTS pin.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE uint32_t nrf_uart_rts_pin_get(NRF_UART_Type * p_reg);
+
+/**
+ * @brief Function for getting CTS pin.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE uint32_t nrf_uart_cts_pin_get(NRF_UART_Type * p_reg);
+
+
+/**
+ * @brief Function for configuring flow control pins.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ * @param pselrts  RTS pin number.
+ * @param pselcts  CTS pin number.
+ */
+__STATIC_INLINE void nrf_uart_hwfc_pins_set(NRF_UART_Type * p_reg,
+                                            uint32_t        pselrts,
+                                            uint32_t        pselcts);
+
+/**
+ * @brief Function for disconnecting flow control pins.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_uart_hwfc_pins_disconnect(NRF_UART_Type * p_reg);
+
+/**
+ * @brief Function for reading RX data.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ * @return         Received byte.
+ */
+__STATIC_INLINE uint8_t nrf_uart_rxd_get(NRF_UART_Type * p_reg);
+
+/**
+ * @brief Function for setting Tx data.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ * @param txd      Byte.
+ */
+__STATIC_INLINE void nrf_uart_txd_set(NRF_UART_Type * p_reg, uint8_t txd);
+
+/**
+ * @brief Function for starting an UART task.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ * @param task     Task.
+ */
+__STATIC_INLINE void nrf_uart_task_trigger(NRF_UART_Type * p_reg, nrf_uart_task_t task);
+
+/**
+ * @brief Function for returning the address of a specific task register.
+ *
+ * @param p_reg Pointer to the peripheral registers structure.
+ * @param task  Task.
+ *
+ * @return      Task address.
+ */
+__STATIC_INLINE uint32_t nrf_uart_task_address_get(NRF_UART_Type * p_reg, nrf_uart_task_t task);
+
+/**
+ * @brief Function for configuring UART.
+ *
+ * @param p_reg  Pointer to the peripheral registers structure.
+ * @param hwfc   Hardware flow control. Enabled if true.
+ * @param parity Parity. Included if true.
+ */
+__STATIC_INLINE void nrf_uart_configure(NRF_UART_Type   * p_reg,
+                                            nrf_uart_parity_t parity,
+                                            nrf_uart_hwfc_t   hwfc);
+
+/**
+ * @brief Function for setting UART baudrate.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ * @param baudrate Baudrate.
+ */
+__STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type   * p_reg, nrf_uart_baudrate_t baudrate);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+__STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
+    (void)dummy;
+#endif
+
+}
+
+__STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_t event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE uint32_t nrf_uart_event_address_get(NRF_UART_Type  * p_reg,
+                                                    nrf_uart_event_t  event)
+{
+    return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t int_mask)
+{
+    p_reg->INTENSET = int_mask;
+}
+
+__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t int_mask)
+{
+    return (bool)(p_reg->INTENSET & int_mask);
+}
+
+__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t int_mask)
+{
+    p_reg->INTENCLR = int_mask;
+}
+
+__STATIC_INLINE uint32_t nrf_uart_errorsrc_get_and_clear(NRF_UART_Type * p_reg)
+{
+    uint32_t errsrc_mask = p_reg->ERRORSRC;
+    p_reg->ERRORSRC = errsrc_mask;
+    return errsrc_mask;
+}
+
+__STATIC_INLINE void nrf_uart_enable(NRF_UART_Type * p_reg)
+{
+    p_reg->ENABLE = UART_ENABLE_ENABLE_Enabled;
+}
+
+__STATIC_INLINE void nrf_uart_disable(NRF_UART_Type * p_reg)
+{
+    p_reg->ENABLE = UART_ENABLE_ENABLE_Disabled;
+}
+
+__STATIC_INLINE void nrf_uart_txrx_pins_set(NRF_UART_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd)
+{
+#if defined(UART_PSEL_RXD_CONNECT_Pos)
+    p_reg->PSEL.RXD = pselrxd;
+#else
+    p_reg->PSELRXD = pselrxd;
+#endif
+#if defined(UART_PSEL_TXD_CONNECT_Pos)
+    p_reg->PSEL.TXD = pseltxd;
+#else
+    p_reg->PSELTXD = pseltxd;
+#endif
+}
+
+__STATIC_INLINE void nrf_uart_txrx_pins_disconnect(NRF_UART_Type * p_reg)
+{
+    nrf_uart_txrx_pins_set(p_reg, NRF_UART_PSEL_DISCONNECTED, NRF_UART_PSEL_DISCONNECTED);
+}
+
+__STATIC_INLINE uint32_t nrf_uart_tx_pin_get(NRF_UART_Type * p_reg)
+{
+#if defined(UART_PSEL_TXD_CONNECT_Pos)
+    return p_reg->PSEL.TXD;
+#else
+    return p_reg->PSELTXD;
+#endif
+}
+
+__STATIC_INLINE uint32_t nrf_uart_rx_pin_get(NRF_UART_Type * p_reg)
+{
+#if defined(UART_PSEL_RXD_CONNECT_Pos)
+    return p_reg->PSEL.RXD;
+#else
+    return p_reg->PSELRXD;
+#endif
+}
+
+__STATIC_INLINE uint32_t nrf_uart_rts_pin_get(NRF_UART_Type * p_reg)
+{
+#if defined(UART_PSEL_RTS_CONNECT_Pos)
+    return p_reg->PSEL.RTS;
+#else
+    return p_reg->PSELRTS;
+#endif
+}
+
+__STATIC_INLINE uint32_t nrf_uart_cts_pin_get(NRF_UART_Type * p_reg)
+{
+#if defined(UART_PSEL_RTS_CONNECT_Pos)
+    return p_reg->PSEL.CTS;
+#else
+    return p_reg->PSELCTS;
+#endif
+}
+
+__STATIC_INLINE void nrf_uart_hwfc_pins_set(NRF_UART_Type * p_reg, uint32_t pselrts, uint32_t pselcts)
+{
+#if defined(UART_PSEL_RTS_CONNECT_Pos)
+    p_reg->PSEL.RTS = pselrts;
+#else
+    p_reg->PSELRTS = pselrts;
+#endif
+
+#if defined(UART_PSEL_RTS_CONNECT_Pos)
+    p_reg->PSEL.CTS = pselcts;
+#else
+    p_reg->PSELCTS = pselcts;
+#endif
+}
+
+__STATIC_INLINE void nrf_uart_hwfc_pins_disconnect(NRF_UART_Type * p_reg)
+{
+    nrf_uart_hwfc_pins_set(p_reg, NRF_UART_PSEL_DISCONNECTED, NRF_UART_PSEL_DISCONNECTED);
+}
+
+__STATIC_INLINE uint8_t nrf_uart_rxd_get(NRF_UART_Type * p_reg)
+{
+    return p_reg->RXD;
+}
+
+__STATIC_INLINE void nrf_uart_txd_set(NRF_UART_Type * p_reg, uint8_t txd)
+{
+    p_reg->TXD = txd;
+}
+
+__STATIC_INLINE void nrf_uart_task_trigger(NRF_UART_Type * p_reg, nrf_uart_task_t task)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t nrf_uart_task_address_get(NRF_UART_Type * p_reg, nrf_uart_task_t task)
+{
+    return (uint32_t)p_reg + (uint32_t)task;
+}
+
+__STATIC_INLINE void nrf_uart_configure(NRF_UART_Type   * p_reg,
+                                            nrf_uart_parity_t parity,
+                                            nrf_uart_hwfc_t   hwfc)
+{
+    p_reg->CONFIG = (uint32_t)parity | (uint32_t)hwfc;
+}
+
+__STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type   * p_reg, nrf_uart_baudrate_t baudrate)
+{
+    p_reg->BAUDRATE = baudrate;
+}
+#endif //SUPPRESS_INLINE_IMPLEMENTATION
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //NRF_UART_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_uarte.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,573 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef NRF_UARTE_H__
+#define NRF_UARTE_H__
+
+#include "nrf.h"
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NRF_UARTE_PSEL_DISCONNECTED 0xFFFFFFFF
+
+/**
+ * @defgroup nrf_uarte_hal UARTE HAL
+ * @{
+ * @ingroup nrf_uart
+ *
+ * @brief Hardware access layer for accessing the UARTE peripheral.
+ */
+
+/**
+ * @enum  nrf_uarte_task_t
+ * @brief UARTE tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_UARTE_TASK_STARTRX   = offsetof(NRF_UARTE_Type, TASKS_STARTRX),///< Start UART receiver.
+    NRF_UARTE_TASK_STOPRX    = offsetof(NRF_UARTE_Type, TASKS_STOPRX), ///< Stop UART receiver.
+    NRF_UARTE_TASK_STARTTX   = offsetof(NRF_UARTE_Type, TASKS_STARTTX),///< Start UART transmitter.
+    NRF_UARTE_TASK_STOPTX    = offsetof(NRF_UARTE_Type, TASKS_STOPTX), ///< Stop UART transmitter.
+    NRF_UARTE_TASK_FLUSHRX   = offsetof(NRF_UARTE_Type, TASKS_FLUSHRX) ///< Flush RX FIFO in RX buffer.
+    /*lint -restore*/
+} nrf_uarte_task_t;
+
+/**
+ * @enum  nrf_uarte_event_t
+ * @brief UARTE events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_UARTE_EVENT_CTS       = offsetof(NRF_UARTE_Type, EVENTS_CTS),      ///< CTS is activated.
+    NRF_UARTE_EVENT_NCTS      = offsetof(NRF_UARTE_Type, EVENTS_NCTS),     ///< CTS is deactivated.
+    NRF_UARTE_EVENT_ENDRX     = offsetof(NRF_UARTE_Type, EVENTS_ENDRX),    ///< Receive buffer is filled up.
+    NRF_UARTE_EVENT_ENDTX     = offsetof(NRF_UARTE_Type, EVENTS_ENDTX),    ///< Last TX byte transmitted.
+    NRF_UARTE_EVENT_ERROR     = offsetof(NRF_UARTE_Type, EVENTS_ERROR),    ///< Error detected.
+    NRF_UARTE_EVENT_RXTO      = offsetof(NRF_UARTE_Type, EVENTS_RXTO),     ///< Receiver timeout.
+    NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_RXSTARTED),///< Receiver has started.
+    NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_TXSTARTED),///< Transmitter has started.
+    NRF_UARTE_EVENT_TXSTOPPED = offsetof(NRF_UARTE_Type, EVENTS_TXSTOPPED) ///< Transmitted stopped.
+    /*lint -restore*/
+} nrf_uarte_event_t;
+
+/**
+ * @brief Types of UARTE shortcuts.
+ */
+typedef enum
+{
+    NRF_UARTE_SHORT_ENDRX_STARTRX = UARTE_SHORTS_ENDRX_STARTRX_Msk,///< Shortcut between ENDRX event and STARTRX task.
+    NRF_UARTE_SHORT_ENDRX_STOPRX  = UARTE_SHORTS_ENDRX_STOPRX_Msk, ///< Shortcut between ENDRX event and STOPRX task.
+} nrf_uarte_short_t;
+
+
+/**
+ * @enum  nrf_uarte_int_mask_t
+ * @brief UARTE interrupts.
+ */
+typedef enum
+{
+    NRF_UARTE_INT_CTS_MASK       = UARTE_INTENSET_CTS_Msk,      ///< Interrupt on CTS event.
+    NRF_UARTE_INT_NCTSRX_MASK    = UARTE_INTENSET_NCTS_Msk,     ///< Interrupt on NCTS event.
+    NRF_UARTE_INT_ENDRX_MASK     = UARTE_INTENSET_ENDRX_Msk,    ///< Interrupt on ENDRX event.
+    NRF_UARTE_INT_ENDTX_MASK     = UARTE_INTENSET_ENDTX_Msk,    ///< Interrupt on ENDTX event.
+    NRF_UARTE_INT_ERROR_MASK     = UARTE_INTENSET_ERROR_Msk,    ///< Interrupt on ERROR event.
+    NRF_UARTE_INT_RXTO_MASK      = UARTE_INTENSET_RXTO_Msk,     ///< Interrupt on RXTO event.
+    NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_RXSTARTED_Msk,///< Interrupt on RXSTARTED event.
+    NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_TXSTARTED_Msk,///< Interrupt on TXSTARTED event.
+    NRF_UARTE_INT_TXSTOPPED_MASK = UARTE_INTENSET_TXSTOPPED_Msk ///< Interrupt on TXSTOPPED event.
+} nrf_uarte_int_mask_t;
+
+/**
+ * @enum nrf_uarte_baudrate_t
+ * @brief Baudrates supported by UARTE.
+ */
+typedef enum
+{
+    NRF_UARTE_BAUDRATE_1200   =  UARTE_BAUDRATE_BAUDRATE_Baud1200,   ///< 1200 baud.
+    NRF_UARTE_BAUDRATE_2400   =  UARTE_BAUDRATE_BAUDRATE_Baud2400,   ///< 2400 baud.
+    NRF_UARTE_BAUDRATE_4800   =  UARTE_BAUDRATE_BAUDRATE_Baud4800,   ///< 4800 baud.
+    NRF_UARTE_BAUDRATE_9600   =  UARTE_BAUDRATE_BAUDRATE_Baud9600,   ///< 9600 baud.
+    NRF_UARTE_BAUDRATE_14400  =  UARTE_BAUDRATE_BAUDRATE_Baud14400,  ///< 14400 baud.
+    NRF_UARTE_BAUDRATE_19200  =  UARTE_BAUDRATE_BAUDRATE_Baud19200,  ///< 19200 baud.
+    NRF_UARTE_BAUDRATE_28800  =  UARTE_BAUDRATE_BAUDRATE_Baud28800,  ///< 28800 baud.
+    NRF_UARTE_BAUDRATE_38400  =  UARTE_BAUDRATE_BAUDRATE_Baud38400,  ///< 38400 baud.
+    NRF_UARTE_BAUDRATE_57600  =  UARTE_BAUDRATE_BAUDRATE_Baud57600,  ///< 57600 baud.
+    NRF_UARTE_BAUDRATE_76800  =  UARTE_BAUDRATE_BAUDRATE_Baud76800,  ///< 76800 baud.
+    NRF_UARTE_BAUDRATE_115200 =  UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud.
+    NRF_UARTE_BAUDRATE_230400 =  UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud.
+    NRF_UARTE_BAUDRATE_250000 =  UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud.
+    NRF_UARTE_BAUDRATE_460800 =  UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud.
+    NRF_UARTE_BAUDRATE_921600 =  UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud.
+    NRF_UARTE_BAUDRATE_1000000 =  UARTE_BAUDRATE_BAUDRATE_Baud1M,    ///< 1000000 baud.
+} nrf_uarte_baudrate_t;
+
+/**
+ * @enum nrf_uarte_error_mask_t
+ * @brief Types of UARTE error masks.
+ */
+typedef enum
+{
+    NRF_UARTE_ERROR_OVERRUN_MASK = UARTE_ERRORSRC_OVERRUN_Msk,   ///< Overrun error.
+    NRF_UARTE_ERROR_PARITY_MASK  = UARTE_ERRORSRC_PARITY_Msk,    ///< Parity error.
+    NRF_UARTE_ERROR_FRAMING_MASK = UARTE_ERRORSRC_FRAMING_Msk,   ///< Framing error.
+    NRF_UARTE_ERROR_BREAK_MASK   = UARTE_ERRORSRC_BREAK_Msk,     ///< Break error.
+} nrf_uarte_error_mask_t;
+
+/**
+ * @enum nrf_uarte_parity_t
+ * @brief Types of UARTE parity modes.
+ */
+typedef enum
+{
+    NRF_UARTE_PARITY_EXCLUDED = UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos, ///< Parity excluded.
+    NRF_UARTE_PARITY_INCLUDED = UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos, ///< Parity included.
+} nrf_uarte_parity_t;
+
+/**
+ * @enum nrf_uarte_hwfc_t
+ * @brief Types of UARTE flow control modes.
+ */
+typedef enum
+{
+    NRF_UARTE_HWFC_DISABLED = UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos, ///< HW flow control disabled.
+    NRF_UARTE_HWFC_ENABLED  = UARTE_CONFIG_HWFC_Enabled  << UARTE_CONFIG_HWFC_Pos, ///< HW flow control enabled.
+} nrf_uarte_hwfc_t;
+
+
+/**
+ * @brief Function for clearing a specific UARTE event.
+ *
+ * @param[in] p_reg  Pointer to the peripheral registers structure.
+ * @param[in] event  Event to clear.
+ */
+__STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event);
+
+/**
+ * @brief Function for checking the state of a specific UARTE event.
+ *
+ * @param[in] p_reg  Pointer to the peripheral registers structure.
+ * @param[in] event  Event to check.
+ *
+ * @retval True if event is set, False otherwise.
+ */
+__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event);
+
+/**
+ * @brief Function for returning the address of a specific UARTE event register.
+ *
+ * @param[in] p_reg  Pointer to the peripheral registers structure.
+ * @param[in] event  Desired event.
+ *
+ * @retval Address of specified event register.
+ */
+__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type  * p_reg,
+                                                    nrf_uarte_event_t  event);
+
+/**
+ * @brief Function for enabling UARTE shortcuts.
+ *
+ * @param p_reg       Pointer to the peripheral registers structure.
+ * @param shorts_mask Shortcuts to enable.
+ */
+__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask);
+
+/**
+ * @brief Function for disabling UARTE shortcuts.
+ *
+ * @param p_reg       Pointer to the peripheral registers structure.
+ * @param shorts_mask Shortcuts to disable.
+ */
+__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask);
+
+/**
+ * @brief Function for enabling UARTE interrupts.
+ *
+ * @param p_reg     Pointer to the peripheral registers structure.
+ * @param int_mask  Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t int_mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param p_reg     Pointer to the peripheral registers structure.
+ * @param int_mask  Mask of interrupt to check.
+ *
+ * @retval true  If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t int_mask);
+
+/**
+ * @brief Function for disabling specific interrupts.
+ *
+ * @param p_reg    Instance.
+ * @param int_mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t int_mask);
+
+/**
+ * @brief Function for getting error source mask. Function is clearing error source flags after reading.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ * @return         Mask with error source flags.
+ */
+__STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg);
+
+/**
+ * @brief Function for enabling UARTE.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg);
+
+/**
+ * @brief Function for disabling UARTE.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg);
+
+/**
+ * @brief Function for configuring TX/RX pins.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ * @param pseltxd  TXD pin number.
+ * @param pselrxd  RXD pin number.
+ */
+__STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd);
+
+/**
+ * @brief Function for disconnecting TX/RX pins.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg);
+
+/**
+ * @brief Function for getting TX pin.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg);
+
+/**
+ * @brief Function for getting RX pin.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg);
+
+/**
+ * @brief Function for getting RTS pin.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg);
+
+/**
+ * @brief Function for getting CTS pin.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg);
+
+
+/**
+ * @brief Function for configuring flow control pins.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ * @param pselrts  RTS pin number.
+ * @param pselcts  CTS pin number.
+ */
+__STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,
+                                                uint32_t        pselrts,
+                                                uint32_t        pselcts);
+
+/**
+ * @brief Function for disconnecting flow control pins.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ */
+__STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg);
+
+/**
+ * @brief Function for starting an UARTE task.
+ *
+ * @param p_reg    Pointer to the peripheral registers structure.
+ * @param task     Task.
+ */
+__STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task);
+
+/**
+ * @brief Function for returning the address of a specific task register.
+ *
+ * @param p_reg Pointer to the peripheral registers structure.
+ * @param task  Task.
+ *
+ * @return      Task address.
+ */
+__STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task);
+
+/**
+ * @brief Function for configuring UARTE.
+ *
+ * @param p_reg  Pointer to the peripheral registers structure.
+ * @param hwfc   Hardware flow control. Enabled if true.
+ * @param parity Parity. Included if true.
+ */
+__STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type   * p_reg,
+                                            nrf_uarte_parity_t parity,
+                                            nrf_uarte_hwfc_t   hwfc);
+
+
+/**
+ * @brief Function for setting UARTE baudrate.
+ *
+ * @param p_reg    Instance.
+ * @param baudrate Baudrate.
+ */
+__STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type   * p_reg, nrf_uarte_baudrate_t baudrate);
+
+/**
+ * @brief Function for setting the transmit buffer.
+ *
+ * @param[in] p_reg     Instance.
+ * @param[in] p_buffer  Pointer to the buffer with data to send.
+ * @param[in] length    Maximum number of data bytes to transmit.
+ */
+__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
+                                             uint8_t  const * p_buffer,
+                                             uint8_t          length);
+
+/**
+ * @brief Function for getting number of bytes transmitted in the last transaction.
+ *
+ * @param[in] p_reg     Instance.
+ *
+ * @retval Amount of bytes transmitted.
+ */
+__STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg);
+
+/**
+ * @brief Function for setting the receive buffer.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ * @param[in] p_buffer  Pointer to the buffer for received data.
+ * @param[in] length    Maximum number of data bytes to receive.
+ */
+__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
+                                             uint8_t * p_buffer,
+                                             uint8_t   length);
+
+/**
+ * @brief Function for getting number of bytes received in the last transaction.
+ *
+ * @param[in] p_reg     Pointer to the peripheral registers structure.
+ *
+ * @retval Amount of bytes received.
+ */
+__STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+__STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
+    (void)dummy;
+#endif
+
+}
+
+__STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type  * p_reg,
+                                                    nrf_uarte_event_t  event)
+{
+    return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask)
+{
+    p_reg->SHORTS |= shorts_mask;
+}
+
+__STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t shorts_mask)
+{
+    p_reg->SHORTS &= ~(shorts_mask);
+}
+
+__STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t int_mask)
+{
+    p_reg->INTENSET = int_mask;
+}
+
+__STATIC_INLINE bool nrf_uarte_int_enable_check(NRF_UARTE_Type * p_reg, nrf_uarte_int_mask_t int_mask)
+{
+    return (bool)(p_reg->INTENSET & int_mask);
+}
+
+__STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t int_mask)
+{
+    p_reg->INTENCLR = int_mask;
+}
+
+__STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg)
+{
+    uint32_t errsrc_mask = p_reg->ERRORSRC;
+    p_reg->ERRORSRC = errsrc_mask;
+    return errsrc_mask;
+}
+
+__STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg)
+{
+    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
+}
+
+__STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg)
+{
+    p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
+}
+
+__STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd)
+{
+    p_reg->PSEL.TXD = pseltxd;
+    p_reg->PSEL.RXD = pselrxd;
+}
+
+__STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg)
+{
+    nrf_uarte_txrx_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED);
+}
+
+__STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type * p_reg)
+{
+    return p_reg->PSEL.TXD;
+}
+
+__STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type * p_reg)
+{
+    return p_reg->PSEL.RXD;
+}
+
+__STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type * p_reg)
+{
+    return p_reg->PSEL.RTS;
+}
+
+__STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type * p_reg)
+{
+    return p_reg->PSEL.CTS;
+}
+
+__STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg, uint32_t pselrts, uint32_t pselcts)
+{
+    p_reg->PSEL.RTS = pselrts;
+    p_reg->PSEL.CTS = pselcts;
+}
+
+__STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg)
+{
+    nrf_uarte_hwfc_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED);
+}
+
+__STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task)
+{
+    return (uint32_t)p_reg + (uint32_t)task;
+}
+
+__STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type   * p_reg,
+                                            nrf_uarte_parity_t parity,
+                                            nrf_uarte_hwfc_t   hwfc)
+{
+    p_reg->CONFIG = (uint32_t)parity | (uint32_t)hwfc;
+}
+
+__STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type   * p_reg, nrf_uarte_baudrate_t baudrate)
+{
+    p_reg->BAUDRATE = baudrate;
+}
+
+__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
+                                             uint8_t  const * p_buffer,
+                                             uint8_t          length)
+{
+    p_reg->TXD.PTR    = (uint32_t)p_buffer;
+    p_reg->TXD.MAXCNT = length;
+}
+
+__STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg)
+{
+    return p_reg->TXD.AMOUNT;
+}
+
+__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
+                                             uint8_t * p_buffer,
+                                             uint8_t   length)
+{
+    p_reg->RXD.PTR    = (uint32_t)p_buffer;
+    p_reg->RXD.MAXCNT = length;
+}
+
+__STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type * p_reg)
+{
+    return p_reg->RXD.AMOUNT;
+}
+#endif //SUPPRESS_INLINE_IMPLEMENTATION
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //NRF_UARTE_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_wdt.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,338 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @defgroup nrf_wdt_hal WDT HAL
+ * @{
+ * @ingroup nrf_wdt
+ *
+ * @brief Hardware access layer for accessing the watchdog timer (WDT) peripheral.
+ */
+
+#ifndef NRF_WDT_H__
+#define NRF_WDT_H__
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NRF_WDT_CHANNEL_NUMBER 0x8UL
+#define NRF_WDT_RR_VALUE       0x6E524635UL /* Fixed value, shouldn't be modified.*/
+
+#define NRF_WDT_TASK_SET       1UL
+#define NRF_WDT_EVENT_CLEAR    0UL
+
+/**
+ * @enum nrf_wdt_task_t
+ * @brief WDT tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30 -esym(628,__INTADDR__)*/
+    NRF_WDT_TASK_START = offsetof(NRF_WDT_Type, TASKS_START), /**< Task for starting WDT. */
+    /*lint -restore*/
+} nrf_wdt_task_t;
+
+/**
+ * @enum nrf_wdt_event_t
+ * @brief WDT events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_WDT_EVENT_TIMEOUT = offsetof(NRF_WDT_Type, EVENTS_TIMEOUT), /**< Event from WDT time-out. */
+    /*lint -restore*/
+} nrf_wdt_event_t;
+
+/**
+ * @enum nrf_wdt_behaviour_t
+ * @brief WDT behavior in CPU SLEEP or HALT mode.
+ */
+typedef enum
+{
+    NRF_WDT_BEHAVIOUR_RUN_SLEEP        = WDT_CONFIG_SLEEP_Msk,                       /**< WDT will run when CPU is in SLEEP mode. */
+    NRF_WDT_BEHAVIOUR_RUN_HALT         = WDT_CONFIG_HALT_Msk,                        /**< WDT will run when CPU is in HALT mode. */
+    NRF_WDT_BEHAVIOUR_RUN_SLEEP_HALT   = WDT_CONFIG_SLEEP_Msk | WDT_CONFIG_HALT_Msk, /**< WDT will run when CPU is in SLEEP or HALT mode. */
+    NRF_WDT_BEHAVIOUR_PAUSE_SLEEP_HALT = 0,                                          /**< WDT will be paused when CPU is in SLEEP or HALT mode. */
+} nrf_wdt_behaviour_t;
+
+/**
+ * @enum nrf_wdt_rr_register_t
+ * @brief WDT reload request registers.
+ */
+typedef enum
+{
+    NRF_WDT_RR0 = 0, /**< Reload request register 0. */
+    NRF_WDT_RR1,     /**< Reload request register 1. */
+    NRF_WDT_RR2,     /**< Reload request register 2. */
+    NRF_WDT_RR3,     /**< Reload request register 3. */
+    NRF_WDT_RR4,     /**< Reload request register 4. */
+    NRF_WDT_RR5,     /**< Reload request register 5. */
+    NRF_WDT_RR6,     /**< Reload request register 6. */
+    NRF_WDT_RR7      /**< Reload request register 7. */
+} nrf_wdt_rr_register_t;
+
+/**
+ * @enum nrf_wdt_int_mask_t
+ * @brief WDT interrupts.
+ */
+typedef enum
+{
+    NRF_WDT_INT_TIMEOUT_MASK = WDT_INTENSET_TIMEOUT_Msk, /**< WDT interrupt from time-out event. */
+} nrf_wdt_int_mask_t;
+
+/**
+ * @brief Function for configuring the watchdog behavior when the CPU is sleeping or halted.
+ *
+ * @param behaviour Watchdog behavior when CPU is in SLEEP or HALT mode.
+ */
+__STATIC_INLINE void nrf_wdt_behaviour_set(nrf_wdt_behaviour_t behaviour)
+{
+    NRF_WDT->CONFIG = behaviour;
+}
+
+
+/**
+ * @brief Function for starting the watchdog.
+ *
+ * @param[in]  task             Task.
+ */
+__STATIC_INLINE void nrf_wdt_task_trigger(nrf_wdt_task_t task)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_WDT + task)) = NRF_WDT_TASK_SET;
+}
+
+
+/**
+ * @brief Function for clearing the WDT event.
+ *
+ * @param[in]  event       Event.
+ */
+__STATIC_INLINE void nrf_wdt_event_clear(nrf_wdt_event_t event)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_WDT + (uint32_t)event)) = NRF_WDT_EVENT_CLEAR;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_WDT + (uint32_t)event));
+    (void)dummy;
+#endif
+}
+
+
+/**
+ * @brief Function for retrieving the state of the WDT event.
+ *
+ * @param[in]  event       Event.
+ *
+ * @retval     true              If the event is set.
+ * @retval     false             If the event is not set.
+ */
+__STATIC_INLINE bool nrf_wdt_event_check(nrf_wdt_event_t event)
+{
+    return (bool)*((volatile uint32_t *)((uint8_t *)NRF_WDT + event));
+}
+
+
+/**
+ * @brief Function for enabling a specific interrupt.
+ *
+ * @param[in]  int_mask         Interrupt.
+ */
+__STATIC_INLINE void nrf_wdt_int_enable(uint32_t int_mask)
+{
+    NRF_WDT->INTENSET = int_mask;
+}
+
+
+/**
+ * @brief Function for retrieving the state of given interrupt.
+ *
+ * @param[in]  int_mask         Interrupt.
+ *
+ * @retval     true                   Interrupt is enabled.
+ * @retval     false                  Interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_wdt_int_enable_check(uint32_t int_mask)
+{
+    return (bool)(NRF_WDT->INTENSET & int_mask);
+}
+
+
+/**
+ * @brief Function for disabling a specific interrupt.
+ *
+ * @param[in]  int_mask         Interrupt.
+ */
+__STATIC_INLINE void nrf_wdt_int_disable(uint32_t int_mask)
+{
+    NRF_WDT->INTENCLR = int_mask;
+}
+
+
+/**
+ * @brief Function for returning the address of a specific WDT task register.
+ *
+ * @param[in]  task             Task.
+ */
+__STATIC_INLINE uint32_t nrf_wdt_task_address_get(nrf_wdt_task_t task)
+{
+    return ((uint32_t)NRF_WDT + task);
+}
+
+
+/**
+ * @brief Function for returning the address of a specific WDT event register.
+ *
+ * @param[in]  event       Event.
+ *
+ * @retval     address of requested event register
+ */
+__STATIC_INLINE uint32_t nrf_wdt_event_address_get(nrf_wdt_event_t event)
+{
+    return ((uint32_t)NRF_WDT + event);
+}
+
+
+/**
+ * @brief Function for retrieving the watchdog status.
+ *
+ * @retval     true             If the watchdog is started.
+ * @retval     false            If the watchdog is not started.
+ */
+__STATIC_INLINE bool nrf_wdt_started(void)
+{
+    return (bool)(NRF_WDT->RUNSTATUS);
+}
+
+
+/**
+ * @brief Function for retrieving the watchdog reload request status.
+ *
+ * @param[in]  rr_register      Reload request register to check.
+ *
+ * @retval     true             If a reload request is running.
+ * @retval     false            If no reload request is running.
+ */
+__STATIC_INLINE bool nrf_wdt_request_status(nrf_wdt_rr_register_t rr_register)
+{
+    return (bool)(((NRF_WDT->REQSTATUS) >> rr_register) & 0x1UL);
+}
+
+
+/**
+ * @brief Function for setting the watchdog reload value.
+ *
+ * @param[in]  reload_value     Watchdog counter initial value.
+ */
+__STATIC_INLINE void nrf_wdt_reload_value_set(uint32_t reload_value)
+{
+    NRF_WDT->CRV = reload_value;
+}
+
+
+/**
+ * @brief Function for retrieving the watchdog reload value.
+ *
+ * @retval                      Reload value.
+ */
+__STATIC_INLINE uint32_t nrf_wdt_reload_value_get(void)
+{
+    return (uint32_t)NRF_WDT->CRV;
+}
+
+
+/**
+ * @brief Function for enabling a specific reload request register.
+ *
+ * @param[in]  rr_register       Reload request register to enable.
+ */
+__STATIC_INLINE void nrf_wdt_reload_request_enable(nrf_wdt_rr_register_t rr_register)
+{
+    NRF_WDT->RREN |= 0x1UL << rr_register;
+}
+
+
+/**
+ * @brief Function for disabling a specific reload request register.
+ *
+ * @param[in]  rr_register       Reload request register to disable.
+ */
+__STATIC_INLINE void nrf_wdt_reload_request_disable(nrf_wdt_rr_register_t rr_register)
+{
+    NRF_WDT->RREN &= ~(0x1UL << rr_register);
+}
+
+
+/**
+ * @brief Function for retrieving the status of a specific reload request register.
+ *
+ * @param[in]  rr_register       Reload request register to check.
+ *
+ * @retval     true              If the reload request register is enabled.
+ * @retval     false             If the reload request register is not enabled.
+ */
+__STATIC_INLINE bool nrf_wdt_reload_request_is_enabled(nrf_wdt_rr_register_t rr_register)
+{
+    return (bool)(NRF_WDT->RREN & (0x1UL << rr_register));
+}
+
+
+/**
+ * @brief Function for setting a specific reload request register.
+ *
+ * @param[in]  rr_register       Reload request register to set.
+ */
+__STATIC_INLINE void nrf_wdt_reload_request_set(nrf_wdt_rr_register_t rr_register)
+{
+    NRF_WDT->RR[rr_register] = NRF_WDT_RR_VALUE;
+}
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/i2s/nrf_drv_i2s.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,436 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(I2S)
+#include "nrf_drv_i2s.h"
+#include "nrf_drv_common.h"
+#include "nrf_gpio.h"
+#include "nrf_assert.h"
+#include "app_util_platform.h"
+
+#define NRF_LOG_MODULE_NAME "I2S"
+
+#if I2S_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       I2S_CONFIG_LOG_LEVEL
+#define NRF_LOG_INFO_COLOR  I2S_CONFIG_INFO_COLOR
+#define NRF_LOG_DEBUG_COLOR I2S_CONFIG_DEBUG_COLOR
+#define EVT_TO_STR(event)   (event == NRF_I2S_EVENT_RXPTRUPD ? "NRF_I2S_EVENT_RXPTRUPD" :                \
+                            (event == NRF_I2S_EVENT_TXPTRUPD ? "NRF_I2S_EVENT_TXPTRUPD" :                \
+                            (event == NRF_I2S_EVENT_STOPPED ? "NRF_I2S_EVENT_STOPPED" : "UNKNOWN EVENT")))
+#else //I2S_CONFIG_LOG_ENABLED
+#define EVT_TO_STR(event)   ""
+#define NRF_LOG_LEVEL       0
+#endif //I2S_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+
+#define MODULE_INITIALIZED (m_cb.state == NRF_DRV_STATE_INITIALIZED) /**< Macro designating whether the module has been initialized properly. */
+
+// Control block - driver instance local data.
+typedef struct
+{
+    nrf_drv_i2s_data_handler_t handler;
+    nrf_drv_state_t            state;
+
+    bool       synchronized_mode : 1;
+    bool       rx_ready          : 1;
+    bool       tx_ready          : 1;
+    bool       just_started      : 1;
+    uint16_t   buffer_half_size;
+    uint32_t * p_rx_buffer;
+    uint32_t * p_tx_buffer;
+} i2s_control_block_t;
+static i2s_control_block_t m_cb;
+
+
+static nrf_drv_i2s_config_t const m_default_config = NRF_DRV_I2S_DEFAULT_CONFIG;
+
+
+static void configure_pins(nrf_drv_i2s_config_t const * p_config)
+{
+    uint32_t mck_pin, sdout_pin, sdin_pin;
+
+    // Configure pins used by the peripheral:
+
+    // - SCK and LRCK (required) - depending on the mode of operation these
+    //   pins are configured as outputs (in Master mode) or inputs (in Slave
+    //   mode).
+    if (p_config->mode == NRF_I2S_MODE_MASTER)
+    {
+        nrf_gpio_cfg_output(p_config->sck_pin);
+        nrf_gpio_cfg_output(p_config->lrck_pin);
+    }
+    else
+    {
+        nrf_gpio_cfg_input(p_config->sck_pin,  NRF_GPIO_PIN_NOPULL);
+        nrf_gpio_cfg_input(p_config->lrck_pin, NRF_GPIO_PIN_NOPULL);
+    }
+
+    // - MCK (optional) - always output,
+    if (p_config->mck_pin != NRF_DRV_I2S_PIN_NOT_USED)
+    {
+        mck_pin = p_config->mck_pin;
+        nrf_gpio_cfg_output(mck_pin);
+    }
+    else
+    {
+        mck_pin = NRF_I2S_PIN_NOT_CONNECTED;
+    }
+
+    // - SDOUT (optional) - always output,
+    if (p_config->sdout_pin != NRF_DRV_I2S_PIN_NOT_USED)
+    {
+        sdout_pin = p_config->sdout_pin;
+        nrf_gpio_cfg_output(sdout_pin);
+    }
+    else
+    {
+        sdout_pin = NRF_I2S_PIN_NOT_CONNECTED;
+    }
+
+    // - SDIN (optional) - always input.
+    if (p_config->sdin_pin != NRF_DRV_I2S_PIN_NOT_USED)
+    {
+        sdin_pin = p_config->sdin_pin;
+        nrf_gpio_cfg_input(sdin_pin, NRF_GPIO_PIN_NOPULL);
+    }
+    else
+    {
+        sdin_pin = NRF_I2S_PIN_NOT_CONNECTED;
+    }
+
+    nrf_i2s_pins_set(NRF_I2S, p_config->sck_pin, p_config->lrck_pin,
+        mck_pin, sdout_pin, sdin_pin);
+}
+
+
+ret_code_t nrf_drv_i2s_init(nrf_drv_i2s_config_t const * p_config,
+                            nrf_drv_i2s_data_handler_t   handler)
+{
+    ASSERT(handler);
+
+    ret_code_t err_code;
+
+    if (m_cb.state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    if (p_config == NULL)
+    {
+        p_config = &m_default_config;
+    }
+
+    if (!nrf_i2s_configure(NRF_I2S, p_config->mode,
+                                    p_config->format,
+                                    p_config->alignment,
+                                    p_config->sample_width,
+                                    p_config->channels,
+                                    p_config->mck_setup,
+                                    p_config->ratio))
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+    configure_pins(p_config);
+
+    m_cb.handler = handler;
+
+    nrf_drv_common_irq_enable(I2S_IRQn, p_config->irq_priority);
+
+    m_cb.state = NRF_DRV_STATE_INITIALIZED;
+
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+void nrf_drv_i2s_uninit(void)
+{
+    ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
+
+    nrf_drv_i2s_stop();
+
+    nrf_drv_common_irq_disable(I2S_IRQn);
+
+    m_cb.state = NRF_DRV_STATE_UNINITIALIZED;
+    NRF_LOG_INFO("Initialized.\r\n");
+}
+
+
+ret_code_t nrf_drv_i2s_start(uint32_t * p_rx_buffer,
+                             uint32_t * p_tx_buffer,
+                             uint16_t   buffer_size,
+                             uint8_t    flags)
+{
+    ASSERT((p_rx_buffer != NULL) || (p_tx_buffer != NULL));
+
+    uint16_t buffer_half_size = buffer_size / 2;
+    ASSERT(buffer_half_size != 0);
+
+    VERIFY_MODULE_INITIALIZED();
+
+    ret_code_t err_code;
+
+    if ((p_rx_buffer != NULL) && !nrf_drv_is_in_RAM(p_rx_buffer))
+    {
+        err_code = NRF_ERROR_INVALID_ADDR;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    if ((p_tx_buffer != NULL) && !nrf_drv_is_in_RAM(p_tx_buffer))
+    {
+        err_code = NRF_ERROR_INVALID_ADDR;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    // Initially we set up the peripheral to use the first half of each buffer,
+    // then in 'I2S_IRQHandler' we will switch to the second half.
+    nrf_i2s_transfer_set(NRF_I2S, buffer_half_size, p_rx_buffer, p_tx_buffer);
+
+    m_cb.p_rx_buffer      = p_rx_buffer;
+    m_cb.p_tx_buffer      = p_tx_buffer;
+    m_cb.buffer_half_size = buffer_half_size;
+    m_cb.just_started     = true;
+
+    if ((flags & NRF_DRV_I2S_FLAG_SYNCHRONIZED_MODE) &&
+        // [synchronized mode makes sense only when both RX and TX are enabled]
+        (m_cb.p_rx_buffer != NULL) && (m_cb.p_tx_buffer != NULL))
+    {
+        m_cb.synchronized_mode = true;
+        m_cb.rx_ready          = false;
+        m_cb.tx_ready          = false;
+    }
+    else
+    {
+        m_cb.synchronized_mode = false;
+    }
+
+    nrf_i2s_enable(NRF_I2S);
+
+    m_cb.state = NRF_DRV_STATE_POWERED_ON;
+
+    if (m_cb.p_tx_buffer != NULL)
+    {
+        // Get from the application the first portion of data to be sent - we
+        // need to have it in the transmit buffer before we start the transfer.
+        // Unless the synchronized mode is active. In this mode we must wait
+        // with this until the first portion of data is received, so here we
+        // just make sure that there will be silence on the SDOUT line prior
+        // to that moment.
+        if (m_cb.synchronized_mode)
+        {
+            memset(m_cb.p_tx_buffer, 0, buffer_size);
+        }
+        else
+        {
+            m_cb.handler(NULL, m_cb.p_tx_buffer, m_cb.buffer_half_size);
+        }
+    }
+
+    nrf_i2s_event_clear(NRF_I2S, NRF_I2S_EVENT_RXPTRUPD);
+    nrf_i2s_event_clear(NRF_I2S, NRF_I2S_EVENT_TXPTRUPD);
+    nrf_i2s_int_enable(NRF_I2S,
+        NRF_I2S_INT_RXPTRUPD_MASK | NRF_I2S_INT_TXPTRUPD_MASK);
+    nrf_i2s_task_trigger(NRF_I2S, NRF_I2S_TASK_START);
+
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+void nrf_drv_i2s_stop(void)
+{
+    ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
+
+    // First disable interrupts, then trigger the STOP task, so no spurious
+    // RXPTRUPD and TXPTRUPD events (see FTPAN-55) will be processed.
+    nrf_i2s_int_disable(NRF_I2S,
+        NRF_I2S_INT_RXPTRUPD_MASK | NRF_I2S_INT_TXPTRUPD_MASK);
+
+    nrf_i2s_task_trigger(NRF_I2S, NRF_I2S_TASK_STOP);
+
+    nrf_i2s_disable(NRF_I2S);
+
+    m_cb.state = NRF_DRV_STATE_INITIALIZED;
+
+    NRF_LOG_INFO("Disabled.");
+}
+
+
+void I2S_IRQHandler(void)
+{
+    uint32_t * p_data_received = NULL;
+    uint32_t * p_data_to_send  = NULL;
+
+    if (nrf_i2s_event_check(NRF_I2S, NRF_I2S_EVENT_TXPTRUPD))
+    {
+        nrf_i2s_event_clear(NRF_I2S, NRF_I2S_EVENT_TXPTRUPD);
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_I2S_EVENT_TXPTRUPD));
+
+        // If transmission is not enabled, but for some reason the TXPTRUPD
+        // event has been generated, just ignore it.
+        if (m_cb.p_tx_buffer != NULL)
+        {
+            uint32_t * p_tx_buffer_next;
+            if (nrf_i2s_tx_buffer_get(NRF_I2S) == m_cb.p_tx_buffer)
+            {
+                p_tx_buffer_next = m_cb.p_tx_buffer + m_cb.buffer_half_size;
+            }
+            else
+            {
+                p_tx_buffer_next = m_cb.p_tx_buffer;
+            }
+            nrf_i2s_tx_buffer_set(NRF_I2S, p_tx_buffer_next);
+
+            m_cb.tx_ready = true;
+
+            // Now the part of the buffer that we've configured as "next" should
+            // be filled by the application with proper data to be sent;
+            // the peripheral is sending data from the other part of the buffer
+            // (but it will finish soon...).
+            p_data_to_send = p_tx_buffer_next;
+
+        }
+    }
+
+    if (nrf_i2s_event_check(NRF_I2S, NRF_I2S_EVENT_RXPTRUPD))
+    {
+        nrf_i2s_event_clear(NRF_I2S, NRF_I2S_EVENT_RXPTRUPD);
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_I2S_EVENT_RXPTRUPD));
+
+        // If reception is not enabled, but for some reason the RXPTRUPD event
+        // has been generated, just ignore it.
+        if (m_cb.p_rx_buffer != NULL)
+        {
+            uint32_t * p_rx_buffer_next;
+            if (nrf_i2s_rx_buffer_get(NRF_I2S) == m_cb.p_rx_buffer)
+            {
+                p_rx_buffer_next = m_cb.p_rx_buffer + m_cb.buffer_half_size;
+            }
+            else
+            {
+                p_rx_buffer_next = m_cb.p_rx_buffer;
+            }
+            nrf_i2s_rx_buffer_set(NRF_I2S, p_rx_buffer_next);
+
+            m_cb.rx_ready = true;
+
+            // The RXPTRUPD event is generated for the first time right after
+            // the transfer is started. Since there is no data received yet at
+            // this point we only update the buffer pointer (it is done above),
+            // there is no callback to the application.
+            // [for synchronized mode this has to be handled differently -
+            //  see below]
+            if (m_cb.just_started && !m_cb.synchronized_mode)
+            {
+                m_cb.just_started = false;
+            }
+            else
+            {
+                // The RXPTRUPD event indicates that from now on the peripheral
+                // will be filling the part of the buffer that was pointed at
+                // the time the event has been generated, hence now we can let
+                // the application process the data stored in the other part of
+                // the buffer - the one that we've just set to be filled next.
+                p_data_received = p_rx_buffer_next;
+            }
+        }
+    }
+
+    // Call the data handler passing received data to the application and/or
+    // requesting data to be sent.
+    if (!m_cb.synchronized_mode)
+    {
+        if ((p_data_received != NULL) || (p_data_to_send != NULL))
+        {
+            if (p_data_received != NULL) 
+            {
+                NRF_LOG_DEBUG("Rx data:\r\n");
+                NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_data_received,
+                                        m_cb.buffer_half_size * sizeof(p_data_received));
+            }
+            m_cb.handler(p_data_received, p_data_to_send,
+                m_cb.buffer_half_size);
+            if (p_data_to_send != NULL) 
+            {
+                NRF_LOG_DEBUG("Tx data:\r\n");
+                NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_data_to_send, 
+                                        m_cb.buffer_half_size * sizeof(p_data_to_send));
+            }
+        }
+    }
+    // In the synchronized mode wait until the events for both RX and TX occur.
+    // And ignore the initial occurrences of these events, since they only
+    // indicate that the transfer has started - no data is received yet at
+    // that moment, so we have got nothing to pass to the application.
+    else
+    {
+        if (m_cb.rx_ready && m_cb.tx_ready)
+        {
+            m_cb.rx_ready = false;
+            m_cb.tx_ready = false;
+
+            if (m_cb.just_started)
+            {
+                m_cb.just_started = false;
+            }
+            else
+            {
+                NRF_LOG_DEBUG("Rx data:\r\n");
+                NRF_LOG_HEXDUMP_DEBUG((uint8_t *)nrf_i2s_rx_buffer_get(NRF_I2S), 
+                                        m_cb.buffer_half_size * sizeof(p_data_to_send));
+                m_cb.handler(nrf_i2s_rx_buffer_get(NRF_I2S),
+                             nrf_i2s_tx_buffer_get(NRF_I2S),
+                             m_cb.buffer_half_size);
+                NRF_LOG_DEBUG("Tx data:\r\n");
+                NRF_LOG_HEXDUMP_DEBUG((uint8_t *)nrf_i2s_tx_buffer_get(NRF_I2S), 
+                                        m_cb.buffer_half_size * sizeof(p_data_to_send));
+            }
+        }
+    }
+}
+#endif //NRF_MODULE_ENABLED(I2S)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/i2s/nrf_drv_i2s.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,254 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**@file
+ * @addtogroup nrf_i2s I2S HAL and driver
+ * @ingroup    nrf_drivers
+ * @brief      @tagAPI52 Inter-IC Sound (I2S) interface APIs.
+ *
+ * @defgroup   nrf_drv_i2s I2S driver
+ * @{
+ * @ingroup    nrf_i2s
+ * @brief      @tagAPI52 Inter-IC Sound (I2S) interface driver.
+ */
+
+
+#ifndef NRF_DRV_I2S_H__
+#define NRF_DRV_I2S_H__
+
+#include "nordic_common.h"
+#include "sdk_config.h"
+#include "nrf_i2s.h"
+#include "sdk_errors.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @brief This value can be provided instead of a pin number for the signals
+ *        SDOUT, SDIN, and MCK to specify that a given signal is not used
+ *        and therefore does not need to be connected to a pin.
+ */
+#define NRF_DRV_I2S_PIN_NOT_USED  0xFF
+
+/**
+ * @brief Flag indicating that calls to the data handler for RX and TX should
+ *        be synchronized, thus always combined into one call.
+ *
+ * Use this flag when calling @ref nrf_drv_i2s_start to force a common call
+ * to the @ref nrf_drv_i2s_data_handler_t "data handler" for RX and TX data.
+ * This is useful, for example, when received data should be processed and
+ * then be sent back. Obviously, this flag is only applicable when both
+ * directions (RX and TX) are enabled.
+ */
+#define NRF_DRV_I2S_FLAG_SYNCHRONIZED_MODE  0x01
+
+/**
+ * @brief I2S driver configuration structure.
+ */
+typedef struct
+{
+    uint8_t sck_pin;      ///< SCK pin number.
+    uint8_t lrck_pin;     ///< LRCK pin number.
+    uint8_t mck_pin;      ///< MCK pin number.
+                          /**< Optional. Use @ref NRF_DRV_I2S_PIN_NOT_USED
+                           *   if this signal is not needed. */
+    uint8_t sdout_pin;    ///< SDOUT pin number.
+                          /**< Optional. Use @ref NRF_DRV_I2S_PIN_NOT_USED
+                           *   if this signal is not needed. */
+    uint8_t sdin_pin;     ///< SDIN pin number.
+                          /**< Optional. Use @ref NRF_DRV_I2S_PIN_NOT_USED
+                           *   if this signal is not needed. */
+    uint8_t irq_priority; ///< Interrupt priority.
+
+    nrf_i2s_mode_t     mode;         ///< Mode of operation.
+    nrf_i2s_format_t   format;       ///< Frame format.
+    nrf_i2s_align_t    alignment;    ///< Alignment of sample within a frame.
+    nrf_i2s_swidth_t   sample_width; ///< Sample width.
+    nrf_i2s_channels_t channels;     ///< Enabled channels.
+    nrf_i2s_mck_t      mck_setup;    ///< Master clock setup.
+    nrf_i2s_ratio_t    ratio;        ///< MCK/LRCK ratio.
+} nrf_drv_i2s_config_t;
+
+/**
+ * @brief I2S driver default configuration.
+ */
+#define NRF_DRV_I2S_DEFAULT_CONFIG           \
+{                                            \
+    .sck_pin      = I2S_CONFIG_SCK_PIN,      \
+    .lrck_pin     = I2S_CONFIG_LRCK_PIN,     \
+    .mck_pin      = I2S_CONFIG_MCK_PIN,      \
+    .sdout_pin    = I2S_CONFIG_SDOUT_PIN,    \
+    .sdin_pin     = I2S_CONFIG_SDIN_PIN,     \
+    .irq_priority = I2S_CONFIG_IRQ_PRIORITY, \
+    .mode         = (nrf_i2s_mode_t)I2S_CONFIG_MASTER,       \
+    .format       = (nrf_i2s_format_t)I2S_CONFIG_FORMAT,       \
+    .alignment    = (nrf_i2s_align_t)I2S_CONFIG_ALIGN,        \
+    .sample_width = (nrf_i2s_swidth_t)I2S_CONFIG_SWIDTH,       \
+    .channels     = (nrf_i2s_channels_t)I2S_CONFIG_CHANNELS,     \
+    .mck_setup    = (nrf_i2s_mck_t)I2S_CONFIG_MCK_SETUP,    \
+    .ratio        = (nrf_i2s_ratio_t)I2S_CONFIG_RATIO,        \
+}
+
+/**
+ * @brief I2S driver data handler type.
+ *
+ * A data handling function of this type must be specified during initialization
+ * of the driver. The driver will call this function when a new portion of data
+ * is received or a new portion of data should be prepared for transmission.
+ * The first case is indicated by a non-NULL value in the @p p_data_received
+ * parameter (which points to the memory containing the received data).
+ * Similarly, the second case is indicated by a non-NULL value in the
+ * @p p_data_to_send parameter (which points to where the data to be transmitted
+ * should be placed).
+ *
+ * @note The two cases mentioned above may be indicated separately or combined
+ *       into one call (depending on the environment in which the driver is
+ *       used). Therefore, both parameters should be checked and handled
+ *       properly in every call. @ref NRF_DRV_I2S_FLAG_SYNCHRONIZED_MODE
+ *       "Synchronized mode" can be used to always combine these indications.
+ *
+ * @param[in]  p_data_received Pointer to the buffer with received data,
+ *                             or NULL if the handler is called to prepare
+ *                             transmission only.
+ * @param[out] p_data_to_send  Pointer to the buffer where data to be sent
+ *                             should be written, or NULL if the handler is
+ *                             called for received data only.
+ * @param[in]  number_of_words Length of data received and/or to be written
+ *                             (in 32-bit words). This value is always equal to
+ *                             half the size of the buffers set by the call
+ *                             to the @ref nrf_drv_i2s_start function.
+ */
+typedef void (* nrf_drv_i2s_data_handler_t)(uint32_t const * p_data_received,
+                                            uint32_t       * p_data_to_send,
+                                            uint16_t         number_of_words);
+
+
+/**
+ * @brief Function for initializing the I2S driver.
+ *
+ * @param[in] p_config Pointer to the structure with initial configuration.
+ *                     If NULL, the default configuration is used.
+ * @param[in] handler  Data handler provided by the user. Must not be NULL.
+ *
+ * @retval NRF_SUCCESS             If initialization was successful.
+ * @retval NRF_ERROR_INVALID_STATE If the driver was already initialized.
+ * @retval NRF_ERROR_INVALID_PARAM If the requested combination of configuration
+ *                                 options is not allowed by the I2S peripheral.
+ */
+ret_code_t nrf_drv_i2s_init(nrf_drv_i2s_config_t const * p_config,
+                            nrf_drv_i2s_data_handler_t   handler);
+
+/**
+ * @brief Function for uninitializing the I2S driver.
+ */
+void       nrf_drv_i2s_uninit(void);
+
+/**
+ * @brief Function for starting the continuous I2S transfer.
+ *
+ * The I2S data transfer can be performed in one of three modes: RX (reception)
+ * only, TX (transmission) only, or in both directions simultaneously.
+ * The mode is selected by specifying a proper buffer for a given direction
+ * in the call to this function or by passing NULL instead if this direction
+ * should be disabled.
+ *
+ * The length of the buffer (which is a common value for RX and TX if both
+ * directions are enabled) is specified in 32-bit words. One 32-bit memory
+ * word can either contain four 8-bit samples, two 16-bit samples, or one
+ * right-aligned 24-bit sample sign-extended to a 32-bit value.
+ * For a detailed memory mapping for different supported configurations,
+ * see the @linkProductSpecification52.
+ *
+ * The provided buffers are logically divided into two parts of equal size.
+ * One of them is in use by the peripheral (for storing received data or for
+ * getting data to be transmitted, respectively). The other part is provided
+ * to the application via a call to the defined @ref nrf_drv_i2s_data_handler_t
+ * "data handling function", so that the application can process the received
+ * data or prepare the next portion of data to be sent. The two parts are
+ * swapped every time @p buffer_size/2 data words are received or transmitted.
+ *
+ * Additional options are provided using the @p flags parameter:
+ * - @ref NRF_DRV_I2S_FLAG_SYNCHRONIZED_MODE - the calls to data handler should
+ *   be done in a synchronized manner (one common call for TX and RX).
+ *   Applicable only when both RX and TX are enabled.
+ *
+ * @attention All data exchange is done in the data handler only. In particular,
+ *            no data should be written to the transmit buffer before calling
+ *            this function (a proper call to the data handler to get the first
+ *            portion of data to be sent will be done before the actual transfer
+ *            starts).
+ *
+ * @note Peripherals using EasyDMA (like I2S) require the transfer buffers
+ *       to be placed in the Data RAM region. If this condition is not met,
+ *       this function will fail with the error code NRF_ERROR_INVALID_ADDR.
+ *
+ * @param[in] p_rx_buffer Pointer to the receive buffer.
+ *                        Pass NULL if reception is not required.
+ * @param[in] p_tx_buffer Pointer to the transmit buffer.
+ *                        Pass NULL if transmission is not required.
+ * @param[in] buffer_size Size of the buffers (in 32-bit words).
+ *                        The size must be an even number greater than 0.
+ * @param[in] flags       Transfer options (0 for default settings).
+ *
+ * @retval NRF_SUCCESS             If the operation was successful.
+ * @retval NRF_ERROR_INVALID_STATE If a transfer was already started or
+ *                                 the driver has not been initialized.
+ * @retval NRF_ERROR_INVALID_ADDR  If the provided buffers are not placed
+ *                                 in the Data RAM region.
+ */
+ret_code_t nrf_drv_i2s_start(uint32_t * p_rx_buffer,
+                             uint32_t * p_tx_buffer,
+                             uint16_t   buffer_size,
+                             uint8_t    flags);
+
+/**
+ * @brief Function for stopping the I2S transfer.
+ */
+void       nrf_drv_i2s_stop(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_DRV_I2S_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/lpcomp/nrf_drv_lpcomp.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,203 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(LPCOMP)
+#include "nrf_drv_lpcomp.h"
+#include "nrf_assert.h"
+#include "nrf_error.h"
+#include "nrf_soc.h"
+#include "nrf_drv_common.h"
+#include "app_util_platform.h"
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#define NRF_LOG_MODULE_NAME "LPCOMP"
+
+#if LPCOMP_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       LPCOMP_CONFIG_LOG_LEVEL
+#define NRF_LOG_INFO_COLOR  LPCOMP_CONFIG_INFO_COLOR
+#define NRF_LOG_DEBUG_COLOR LPCOMP_CONFIG_DEBUG_COLOR
+#define EVT_TO_STR(event)   (event == NRF_LPCOMP_EVENT_READY ? "NRF_LPCOMP_EVENT_READY" :                \
+                            (event == NRF_LPCOMP_EVENT_DOWN ? "NRF_LPCOMP_EVENT_DOWN" :                  \
+                            (event == NRF_LPCOMP_EVENT_UP ? "NRF_LPCOMP_EVENT_UP" :                      \
+                            (event == NRF_LPCOMP_EVENT_CROSS ? "NRF_LPCOMP_EVENT_CROSS" : "UNKNOWN EVENT"))))
+#else //LPCOMP_CONFIG_LOG_ENABLED
+#define EVT_TO_STR(event)   ""
+#define NRF_LOG_LEVEL       0
+#endif //LPCOMP_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+
+
+static lpcomp_events_handler_t m_lpcomp_events_handler = NULL;
+static nrf_drv_state_t         m_state = NRF_DRV_STATE_UNINITIALIZED;
+
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+    #define IRQ_HANDLER_NAME     irq_handler_for_lpcomp
+    #define IRQ_HANDLER          static void IRQ_HANDLER_NAME(void)
+
+    IRQ_HANDLER;
+#else
+    #define IRQ_HANDLER void LPCOMP_IRQHandler(void)
+#endif // NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+
+static void lpcomp_execute_handler(nrf_lpcomp_event_t event, uint32_t event_mask)
+{
+    if ( nrf_lpcomp_event_check(event) && nrf_lpcomp_int_enable_check(event_mask) )
+    {
+        nrf_lpcomp_event_clear(event);
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(event));
+
+        m_lpcomp_events_handler(event);
+    }
+}
+
+
+IRQ_HANDLER
+{
+    lpcomp_execute_handler(NRF_LPCOMP_EVENT_READY, LPCOMP_INTENSET_READY_Msk);
+    lpcomp_execute_handler(NRF_LPCOMP_EVENT_DOWN, LPCOMP_INTENSET_DOWN_Msk);
+    lpcomp_execute_handler(NRF_LPCOMP_EVENT_UP, LPCOMP_INTENSET_UP_Msk);
+    lpcomp_execute_handler(NRF_LPCOMP_EVENT_CROSS, LPCOMP_INTENSET_CROSS_Msk);
+}
+
+
+ret_code_t nrf_drv_lpcomp_init(const nrf_drv_lpcomp_config_t * p_config,
+                               lpcomp_events_handler_t   events_handler)
+{
+    ASSERT(p_config);
+    ret_code_t err_code;
+
+    if (m_state != NRF_DRV_STATE_UNINITIALIZED)
+    { // LPCOMP driver is already initialized
+        err_code = NRF_ERROR_INVALID_STATE;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+    if (nrf_drv_common_per_res_acquire(NRF_LPCOMP, IRQ_HANDLER_NAME) != NRF_SUCCESS)
+    {
+        err_code = NRF_ERROR_BUSY;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+#endif
+
+    nrf_lpcomp_configure(&(p_config->hal) );
+
+    if (events_handler)
+    {
+        m_lpcomp_events_handler = events_handler;
+    }
+    else
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    nrf_lpcomp_input_select(p_config->input);
+
+    switch (p_config->hal.detection)
+    {
+        case NRF_LPCOMP_DETECT_UP:
+            nrf_lpcomp_int_enable(LPCOMP_INTENSET_UP_Msk);
+            break;
+
+        case NRF_LPCOMP_DETECT_DOWN:
+            nrf_lpcomp_int_enable(LPCOMP_INTENSET_DOWN_Msk);
+            break;
+
+        case NRF_LPCOMP_DETECT_CROSS:
+            nrf_lpcomp_int_enable(LPCOMP_INTENSET_CROSS_Msk);
+            break;
+
+        default:
+            break;
+    }
+    nrf_lpcomp_shorts_enable(NRF_LPCOMP_SHORT_READY_SAMPLE_MASK);
+
+    nrf_drv_common_irq_enable(LPCOMP_IRQn, p_config->interrupt_priority);
+
+    m_state = NRF_DRV_STATE_INITIALIZED;
+
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+void nrf_drv_lpcomp_uninit(void)
+{
+    ASSERT(m_state != NRF_DRV_STATE_UNINITIALIZED);
+    nrf_drv_common_irq_disable(LPCOMP_IRQn);
+    nrf_drv_lpcomp_disable();
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+    nrf_drv_common_per_res_release(NRF_LPCOMP);
+#endif
+    m_state = NRF_DRV_STATE_UNINITIALIZED;
+    m_lpcomp_events_handler = NULL;
+    NRF_LOG_INFO("Uninitialized.\r\n");
+}
+
+void nrf_drv_lpcomp_enable(void)
+{
+    ASSERT(m_state == NRF_DRV_STATE_INITIALIZED);
+    nrf_lpcomp_enable();
+    nrf_lpcomp_task_trigger(NRF_LPCOMP_TASK_START);
+    m_state = NRF_DRV_STATE_POWERED_ON;
+    NRF_LOG_INFO("Enabled.\r\n");
+}
+
+void nrf_drv_lpcomp_disable(void)
+{
+    ASSERT(m_state == NRF_DRV_STATE_POWERED_ON);
+    nrf_lpcomp_disable();
+    nrf_lpcomp_task_trigger(NRF_LPCOMP_TASK_STOP);
+    m_state = NRF_DRV_STATE_POWERED_ON;
+    NRF_LOG_INFO("Disabled.\r\n");
+}
+
+void nrf_drv_lpcomp_event_handler_register(lpcomp_events_handler_t lpcomp_events_handler)
+{
+    m_lpcomp_events_handler = lpcomp_events_handler;
+}
+
+#endif //NRF_MODULE_ENABLED(LPCOMP)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/lpcomp/nrf_drv_lpcomp.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,152 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_DRV_LPCOMP_H__
+#define NRF_DRV_LPCOMP_H__
+
+#include "nrf_lpcomp.h"
+#include "sdk_errors.h"
+#include "nrf_drv_common.h"
+#include "sdk_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @addtogroup nrf_lpcomp LPCOMP HAL and driver
+ * @ingroup nrf_drivers
+ * @brief Low Power Comparator (LPCOMP) APIs.
+ * @details The LPCOMP HAL provides basic APIs for accessing the registers of Low Power Comparator.
+ * The LPCOMP driver provides APIs on a higher level.
+ *
+ * @defgroup nrf_drv_lpcomp LPCOMP driver
+ * @{
+ * @ingroup nrf_lpcomp
+ * @brief Low Power Comparator (LPCOMP) driver.
+ */
+
+/**@brief LPCOMP event handler function type.
+ * @param[in] event  LPCOMP event.
+ */
+typedef void (* lpcomp_events_handler_t)(nrf_lpcomp_event_t event);
+
+/**@brief LPCOMP configuration.
+ */
+typedef struct
+{
+    nrf_lpcomp_config_t    hal;                /**< LPCOMP HAL configuration. */
+    nrf_lpcomp_input_t     input;              /**< Input to be monitored. */
+    uint8_t                interrupt_priority; /**< LPCOMP interrupt priority. */
+} nrf_drv_lpcomp_config_t;
+
+/** @brief LPCOMP driver default configuration including the LPCOMP HAL configuration. */
+#ifdef NRF52_SERIES
+#define NRF_DRV_LPCOMP_DEFAULT_CONFIG                                                                                     \
+    {                                                                                                                     \
+        .hal                = {(nrf_lpcomp_ref_t)LPCOMP_CONFIG_REFERENCE , (nrf_lpcomp_detect_t)LPCOMP_CONFIG_DETECTION,  \
+                               (nrf_lpcomp_hysteresis_t)LPCOMP_CONFIG_HYST},                                              \
+        .input              = (nrf_lpcomp_input_t)LPCOMP_CONFIG_INPUT,                                                    \
+        .interrupt_priority = LPCOMP_CONFIG_IRQ_PRIORITY                                                                  \
+    }
+#else
+#define NRF_DRV_LPCOMP_DEFAULT_CONFIG                                                                                     \
+    {                                                                                                                     \
+        .hal                = {(nrf_lpcomp_ref_t)LPCOMP_CONFIG_REFERENCE , (nrf_lpcomp_detect_t)LPCOMP_CONFIG_DETECTION},  \
+        .input              = (nrf_lpcomp_input_t)LPCOMP_CONFIG_INPUT,                                                    \
+        .interrupt_priority = LPCOMP_CONFIG_IRQ_PRIORITY                                                                  \
+    }
+#endif
+
+/**
+ * @brief Function for initializing the LPCOMP driver.
+ *
+ * This function initializes the LPCOMP driver, but does not enable the peripheral or any interrupts.
+ * To start the driver, call the function nrf_drv_lpcomp_enable() after initialization.
+ *
+ * If no configuration structure is provided, the driver is initialized with the default settings.
+ *
+ * @param[in] p_config              Initial configuration. If NULL, the default configuration is used.
+ * @param[in] events_handler        Handler function.
+ * @retval NRF_ERROR_INVALID_PARAM If the configuration is invalid.
+ * @retval NRF_ERROR_INVALID_STATE If the driver has already been initialized.
+ */
+ret_code_t nrf_drv_lpcomp_init(const nrf_drv_lpcomp_config_t * p_config,
+                               lpcomp_events_handler_t   events_handler);
+
+
+/**
+ *  @brief Function for uninitializing the LCOMP driver.
+ *
+ *  This function uninitializes the LPCOMP driver. The LPCOMP peripheral and
+ *  its interrupts are disabled, and local variables are cleaned. After this call, you must
+ *  initialize the driver again by calling nrf_drv_lpcomp_init() if you want to use it.
+ *
+ *  @sa nrf_drv_lpcomp_disable()
+ *  @sa nrf_drv_lpcomp_init()
+ */
+void     nrf_drv_lpcomp_uninit(void);
+
+/**@brief Function for enabling the LPCOMP peripheral and interrupts.
+ *
+ * Before calling this function, the driver must be initialized. This function
+ * enables the LPCOMP peripheral and its interrupts.
+ *
+ * @sa nrf_drv_lpcomp_disable()
+ */
+void nrf_drv_lpcomp_enable(void);
+
+/**@brief Function for disabling the LPCOMP peripheral.
+ *
+ * Before calling this function, the driver must be initialized. This function disables the LPCOMP
+ * peripheral and its interrupts.
+ *
+ * @sa nrf_drv_lpcomp_enable()
+ */
+void nrf_drv_lpcomp_disable(void);
+
+/**
+ *@}
+ **/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+ #endif /* NRF_DRV_LPCOMP_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/pdm/nrf_drv_pdm.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,247 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(PDM)
+#include "nrf_drv_pdm.h"
+#include "nrf_assert.h"
+#include "nrf_drv_common.h"
+#include "nrf_gpio.h"
+
+#define NRF_LOG_MODULE_NAME "PDM"
+
+#if PDM_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       PDM_CONFIG_LOG_LEVEL
+#define NRF_LOG_INFO_COLOR  PDM_CONFIG_INFO_COLOR
+#define NRF_LOG_DEBUG_COLOR PDM_CONFIG_DEBUG_COLOR
+#define EVT_TO_STR(event)   (event == NRF_PDM_EVENT_STARTED ? "NRF_PDM_EVENT_STARTED" :                \
+                            (event == NRF_PDM_EVENT_STOPPED ? "NRF_COMP_EVENT_DOWN" :                  \
+                            (event == NRF_PDM_EVENT_END ? "NRF_COMP_EVENT_CROSS" : "UNKNOWN EVENT")))
+#else //PDM_CONFIG_LOG_ENABLED
+#define EVT_TO_STR(event)   ""
+#define NRF_LOG_LEVEL       0
+#endif //PDM_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+
+
+/** @brief PDM interface status. */
+typedef enum
+{
+    NRF_PDM_STATE_IDLE,
+    NRF_PDM_STATE_RUNNING,
+    NRF_PDM_STATE_TRANSITION
+} nrf_drv_pdm_state_t;
+
+
+/** @brief PDM interface control block.*/
+typedef struct
+{
+    nrf_drv_state_t             drv_state;        ///< Driver state.
+    nrf_drv_pdm_state_t         status;           ///< Sampling state.
+    nrf_drv_pdm_event_handler_t event_handler;    ///< Event handler function pointer.
+    uint16_t                    buffer_length;    ///< Length of a single buffer in 16-bit words.
+    uint32_t *                  buffers[2];       ///< Sample buffers.
+} nrf_drv_pdm_cb_t;
+
+static nrf_drv_pdm_cb_t m_cb;
+
+
+void PDM_IRQHandler(void)
+{
+    if (nrf_pdm_event_check(NRF_PDM_EVENT_END))
+    {
+        nrf_pdm_event_clear(NRF_PDM_EVENT_END);
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_PDM_EVENT_END));
+
+        //Buffer is ready to process.
+        if (nrf_pdm_buffer_get() == m_cb.buffers[0])
+        {
+            NRF_LOG_DEBUG("PDM data:\r\n");
+            NRF_LOG_HEXDUMP_DEBUG((uint8_t *)m_cb.buffers[1], m_cb.buffer_length * sizeof(m_cb.buffers[1]));
+            m_cb.event_handler(m_cb.buffers[1], m_cb.buffer_length);
+        }
+        else
+        {
+            NRF_LOG_DEBUG("PDM data:\r\n");
+            NRF_LOG_HEXDUMP_DEBUG((uint8_t *)m_cb.buffers[0], m_cb.buffer_length * sizeof(m_cb.buffers[0]));
+            m_cb.event_handler(m_cb.buffers[0], m_cb.buffer_length);
+        }
+    }
+    else if (nrf_pdm_event_check(NRF_PDM_EVENT_STARTED))
+    {
+        nrf_pdm_event_clear(NRF_PDM_EVENT_STARTED);
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_PDM_EVENT_STARTED));
+        m_cb.status = NRF_PDM_STATE_RUNNING;
+
+        //Swap buffer.
+        if (nrf_pdm_buffer_get() == m_cb.buffers[0])
+        {
+            nrf_pdm_buffer_set(m_cb.buffers[1],m_cb.buffer_length);
+        }
+        else
+        {
+            nrf_pdm_buffer_set(m_cb.buffers[0],m_cb.buffer_length);
+        }
+    }
+    else if (nrf_pdm_event_check(NRF_PDM_EVENT_STOPPED))
+    {
+        nrf_pdm_event_clear(NRF_PDM_EVENT_STOPPED);
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_PDM_EVENT_STOPPED));
+        nrf_pdm_disable();
+        m_cb.status = NRF_PDM_STATE_IDLE;
+    }
+}
+
+
+ret_code_t nrf_drv_pdm_init(nrf_drv_pdm_config_t const * p_config,
+                              nrf_drv_pdm_event_handler_t event_handler)
+{
+    ret_code_t err_code;
+
+    if (m_cb.drv_state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+    if ((p_config == NULL)
+        || (event_handler == NULL))
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+    if (p_config->gain_l > NRF_PDM_GAIN_MAXIMUM
+        || p_config->gain_r > NRF_PDM_GAIN_MAXIMUM
+        || p_config->buffer_length > NRF_PDM_MAX_BUFFER_SIZE)
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    m_cb.buffers[0] = (uint32_t*)p_config->buffer_a;
+    m_cb.buffers[1] = (uint32_t*)p_config->buffer_b;
+    m_cb.buffer_length = p_config->buffer_length;
+    m_cb.event_handler = event_handler;
+    m_cb.status = NRF_PDM_STATE_IDLE;
+
+    nrf_pdm_buffer_set(m_cb.buffers[0],m_cb.buffer_length);
+    nrf_pdm_clock_set(p_config->clock_freq);
+    nrf_pdm_mode_set(p_config->mode, p_config->edge);
+    nrf_pdm_gain_set(p_config->gain_l, p_config->gain_r);
+
+    nrf_gpio_cfg_output(p_config->pin_clk);
+    nrf_gpio_pin_clear(p_config->pin_clk);
+    nrf_gpio_cfg_input(p_config->pin_din, NRF_GPIO_PIN_NOPULL);
+    nrf_pdm_psel_connect(p_config->pin_clk, p_config->pin_din);
+
+    m_cb.drv_state = NRF_DRV_STATE_INITIALIZED;
+    nrf_pdm_int_enable(NRF_PDM_INT_STARTED | NRF_PDM_INT_END | NRF_PDM_INT_STOPPED);
+    nrf_drv_common_irq_enable(PDM_IRQn, p_config->interrupt_priority);
+
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+void nrf_drv_pdm_uninit(void)
+{
+    nrf_pdm_disable();
+    nrf_pdm_psel_disconnect();
+    m_cb.drv_state = NRF_DRV_STATE_UNINITIALIZED;
+    NRF_LOG_INFO("Uninitialized.\r\n");
+}
+
+
+ret_code_t nrf_drv_pdm_start(void)
+{
+    ASSERT(m_cb.drv_state != NRF_DRV_STATE_UNINITIALIZED);
+    ret_code_t err_code;
+        
+    if (m_cb.status != NRF_PDM_STATE_IDLE)
+    {
+        if (m_cb.status == NRF_PDM_STATE_RUNNING)
+        {
+            err_code = NRF_SUCCESS;
+            NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+            return err_code;
+        }
+        err_code = NRF_ERROR_BUSY;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+    m_cb.status = NRF_PDM_STATE_TRANSITION;
+    m_cb.drv_state = NRF_DRV_STATE_POWERED_ON;
+    nrf_pdm_enable();
+    nrf_pdm_event_clear(NRF_PDM_EVENT_STARTED);
+    nrf_pdm_task_trigger(NRF_PDM_TASK_START);
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+ret_code_t nrf_drv_pdm_stop(void)
+{
+    ASSERT(m_cb.drv_state != NRF_DRV_STATE_UNINITIALIZED);
+    ret_code_t err_code;
+    
+    if (m_cb.status != NRF_PDM_STATE_RUNNING)
+    {
+        if (m_cb.status == NRF_PDM_STATE_IDLE)
+        {
+            nrf_pdm_disable();
+            err_code = NRF_SUCCESS;
+            NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+            return err_code;
+        }
+        err_code = NRF_ERROR_BUSY;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+    m_cb.status = NRF_PDM_STATE_TRANSITION;
+    m_cb.drv_state = NRF_DRV_STATE_INITIALIZED;
+    nrf_pdm_task_trigger(NRF_PDM_TASK_STOP);
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+#endif //NRF_MODULE_ENABLED(PDM)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/pdm/nrf_drv_pdm.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,202 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @addtogroup nrf_pdm PDM HAL and driver
+ * @ingroup    nrf_drivers
+ * @brief      @tagAPI52 Pulse density modulation (PDM) interface APIs.
+ *
+ * The PDM HAL provides basic APIs for accessing the registers of the PDM interface peripheral.
+ * The PDM driver provides APIs on a higher level.
+ *
+ * @defgroup nrf_drv_pdm PDM driver
+ * @{
+ * @ingroup  nrf_pdm
+ *
+ * @brief    @tagAPI52 Pulse density modulation (PDM) interface driver.
+ */
+
+
+#ifndef NRF_DRV_PDM_H__
+#define NRF_DRV_PDM_H__
+
+#include "sdk_config.h"
+#include "nrf_pdm.h"
+#include "sdk_errors.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define NRF_PDM_MAX_BUFFER_SIZE 32768
+
+
+/**
+ * @brief PDM interface driver configuration structure.
+ */
+typedef struct
+{
+    nrf_pdm_mode_t mode;               ///< Interface operation mode.
+    nrf_pdm_edge_t edge;               ///< Sampling mode.
+    uint8_t        pin_clk;            ///< CLK pin.
+    uint8_t        pin_din;            ///< DIN pin.
+    nrf_pdm_freq_t clock_freq;         ///< Clock frequency.
+    nrf_pdm_gain_t gain_l;             ///< Left channel gain.
+    nrf_pdm_gain_t gain_r;             ///< Right channel gain.
+    uint8_t        interrupt_priority; ///< Interrupt priority.
+    uint16_t       buffer_length;      ///< Length of a single buffer (in 16-bit words).
+    int16_t *      buffer_a;           ///< Sample buffer A (filled first).
+    int16_t *      buffer_b;           ///< Sample buffer B (filled after buffer A).
+} nrf_drv_pdm_config_t;
+
+
+/**
+ * @brief Macro for setting @ref nrf_drv_pdm_config_t to default settings
+ *        in single ended mode.
+ *
+ * @param PIN_CLK  CLK output pin.
+ * @param PIN_DIN  DIN input pin.
+ * @param BUFF_A   Sample buffer A (filled first).
+ * @param BUFF_B   Sample buffer B (filled after buffer A).
+ * @param BUFF_LEN Length of a single buffer (in 16-bit words).
+ */
+#define NRF_DRV_PDM_DEFAULT_CONFIG(PIN_CLK, PIN_DIN, BUFF_A, BUFF_B, BUFF_LEN) \
+{                                                                              \
+    .mode               = (nrf_pdm_mode_t)PDM_CONFIG_MODE,                     \
+    .edge               = (nrf_pdm_edge_t)PDM_CONFIG_EDGE,                     \
+    .pin_clk            = PIN_CLK,                                             \
+    .pin_din            = PIN_DIN,                                             \
+    .clock_freq         = (nrf_pdm_freq_t)PDM_CONFIG_CLOCK_FREQ,               \
+    .gain_l             = NRF_PDM_GAIN_DEFAULT,                                \
+    .gain_r             = NRF_PDM_GAIN_DEFAULT,                                \
+    .interrupt_priority = PDM_CONFIG_IRQ_PRIORITY,                             \
+    .buffer_length      = BUFF_LEN,                                            \
+    .buffer_a           = BUFF_A,                                              \
+    .buffer_b           = BUFF_B                                               \
+}
+
+
+/**
+ * @brief   Handler for PDM interface ready events.
+ *
+ * This event handler is called when a buffer is full and ready to be processed.
+ *
+ * @param[in] p_buffer Sample buffer pointer.
+ * @param[in] length   Buffer length in 16-bit words.
+ */
+typedef void (*nrf_drv_pdm_event_handler_t)(uint32_t * buffer, uint16_t length);
+
+
+/**
+ * @brief Function for initializing the PDM interface.
+ *
+ * @param[in] p_config      Pointer to a configuration structure. If NULL, the default one is used.
+ * @param[in] event_handler Event handler provided by the user.
+ *
+ * @retval    NRF_SUCCESS If initialization was successful.
+ * @retval    NRF_ERROR_INVALID_STATE If the driver is already initialized.
+ * @retval    NRF_ERROR_INVALID_PARAM If invalid parameters were specified.
+ */
+ret_code_t nrf_drv_pdm_init(nrf_drv_pdm_config_t const * p_config,
+                            nrf_drv_pdm_event_handler_t event_handler);
+
+
+/**
+ * @brief Function for uninitializing the PDM interface.
+ *
+ * This function stops PDM sampling, if it is in progress.
+ */
+void nrf_drv_pdm_uninit(void);
+
+
+/**
+ * @brief Function for getting the address of a PDM interface task.
+ *
+ * @param[in]  task Task.
+ *
+ * @return     Task address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_pdm_task_address_get(nrf_pdm_task_t task)
+{
+    return nrf_pdm_task_address_get(task);
+}
+
+
+/**
+ * @brief Function for getting the state of the PDM interface.
+ *
+ * @retval TRUE  If the PDM interface is enabled.
+ * @retval FALSE If the PDM interface is disabled.
+ */
+__STATIC_INLINE bool nrf_drv_pdm_enable_check()
+{
+    return nrf_pdm_enable_check();
+}
+
+
+/**
+ * @brief Function for starting PDM sampling.
+ *
+ * @retval NRF_SUCCESS    If sampling was started successfully or was already in progress.
+ * @retval NRF_ERROR_BUSY If a previous start/stop operation is in progress.
+ */
+ret_code_t nrf_drv_pdm_start(void);
+
+
+/**
+ * @brief   Function for stopping PDM sampling.
+ *
+ * When this function is called, the PDM interface is stopped after finishing
+ * the current frame.
+ * The event handler function might be called once more after calling this function.
+ *
+ * @retval NRF_SUCCESS    If sampling was stopped successfully or was already stopped before.
+ * @retval NRF_ERROR_BUSY If a previous start/stop operation is in progress.
+ */
+ret_code_t nrf_drv_pdm_stop(void);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_DRV_PDM_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/power/nrf_drv_power.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,270 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "sdk_config.h"
+#if POWER_ENABLED
+
+#include "nrf_drv_power.h"
+#include "nrf_assert.h"
+#include "nordic_common.h"
+
+/* Validate configuration */
+INTERRUPT_PRIORITY_VALIDATION(POWER_CONFIG_IRQ_PRIORITY);
+
+/**
+ * @internal
+ * @defgroup nrf_drv_power_internals POWER driver internals
+ * @ingroup nrf_drv_power
+ *
+ * Internal variables, auxiliary macros and functions of POWER driver.
+ * @{
+ */
+
+/**
+ * @brief Default configuration
+ *
+ * The structure with default configuration data.
+ * This structure would be used if configuration pointer given
+ * to the @ref nrf_drv_power_init is set to NULL.
+ */
+static const nrf_drv_power_config_t m_drv_power_config_default =
+{
+    .dcdcen = POWER_CONFIG_DEFAULT_DCDCEN,
+#if NRF_POWER_HAS_VDDH
+    .dcdcenhv = POWER_CONFIG_DEFAULT_DCDCENHV,
+#endif
+};
+
+/**
+ * @brief The initialization flag
+ */
+static bool m_initialized;
+
+/**
+ * @brief The handler of power fail comparator warning event
+ */
+static nrf_drv_power_pofwarn_event_handler_t m_pofwarn_handler;
+
+#if NRF_POWER_HAS_SLEEPEVT
+/**
+ * @brief The handler of sleep event handler
+ */
+static nrf_drv_power_sleep_event_handler_t m_sleepevt_handler;
+#endif
+
+#if NRF_POWER_HAS_USBREG
+/**
+ * @brief The handler of USB power events
+ */
+static nrf_drv_power_usb_event_handler_t m_usbevt_handler;
+#endif
+
+/** @} */
+
+bool nrf_drv_power_init_check(void)
+{
+    return m_initialized;
+}
+
+ret_code_t nrf_drv_power_init(nrf_drv_power_config_t const * p_config)
+{
+    nrf_drv_power_config_t const * p_used_config;
+    if(m_initialized)
+    {
+        return NRF_ERROR_MODULE_ALREADY_INITIALIZED;
+    }
+
+    p_used_config = (p_config != NULL) ?
+        p_config : (&m_drv_power_config_default);
+    nrf_power_dcdcen_set(p_used_config->dcdcen);
+#if NRF_POWER_HAS_VDDH
+    nrf_power_dcdcen_vddh_set(p_used_config->dcdcenhv);
+#endif
+
+    nrf_drv_common_power_clock_irq_init();
+
+    m_initialized = true;
+    return NRF_SUCCESS;
+}
+
+void nrf_drv_power_uninit(void)
+{
+    ASSERT(m_initialized);
+    nrf_drv_power_pof_uninit();
+#if NRF_POWER_HAS_SLEEPEVT
+    nrf_drv_power_sleepevt_uninit();
+#endif
+#if NRF_POWER_HAS_USBREG
+    nrf_drv_power_usbevt_uninit();
+#endif
+    m_initialized = false;
+}
+
+void nrf_drv_power_pof_init(nrf_drv_power_pofwarn_config_t const * p_config)
+{
+    ASSERT(p_config != NULL);
+
+    nrf_drv_power_pof_uninit();
+    nrf_power_pofcon_set(true, p_config->thr);
+#if NRF_POWER_HAS_VDDH
+    nrf_power_pofcon_vddh_set(p_config->thrvddh);
+#endif
+    if(p_config->handler != NULL)
+    {
+        m_pofwarn_handler = p_config->handler;
+        nrf_power_int_enable(NRF_POWER_INT_POFWARN_MASK);
+    }
+}
+
+void nrf_drv_power_pof_uninit(void)
+{
+    nrf_power_int_disable(NRF_POWER_INT_POFWARN_MASK);
+    m_pofwarn_handler = NULL;
+}
+
+#if NRF_POWER_HAS_SLEEPEVT
+void nrf_drv_power_sleepevt_init(nrf_drv_power_sleepevt_config_t const * p_config)
+{
+    ASSERT(p_config != NULL);
+
+    nrf_drv_power_sleepevt_uninit();
+    if(p_config->handler != NULL)
+    {
+        uint32_t enmask = 0;
+        m_sleepevt_handler = p_config->handler;
+        if(p_config->en_enter)
+        {
+            enmask |= NRF_POWER_INT_SLEEPENTER_MASK;
+        }
+        if(p_config->en_exit)
+        {
+            enmask |= NRF_POWER_INT_SLEEPEXIT_MASK;
+        }
+        nrf_power_int_enable(enmask);
+    }
+}
+
+void nrf_drv_power_sleepevt_uninit(void)
+{
+    nrf_power_int_disable(
+        NRF_POWER_INT_SLEEPENTER_MASK |
+        NRF_POWER_INT_SLEEPEXIT_MASK);
+    m_sleepevt_handler = NULL;
+}
+#endif /* NRF_POWER_HAS_SLEEPEVT */
+
+#if NRF_POWER_HAS_USBREG
+void nrf_drv_power_usbevt_init(nrf_drv_power_usbevt_config_t const * p_config)
+{
+    nrf_drv_power_usbevt_uninit();
+    if(p_config->handler != NULL)
+    {
+        m_usbevt_handler = p_config->handler;
+        nrf_power_int_enable(
+            NRF_POWER_INT_USBDETECTED_MASK |
+            NRF_POWER_INT_USBREMOVED_MASK  |
+            NRF_POWER_INT_USBPWRRDY_MASK);
+    }
+}
+
+void nrf_drv_power_usbevt_uninit(void)
+{
+    nrf_power_int_disable(
+        NRF_POWER_INT_USBDETECTED_MASK |
+        NRF_POWER_INT_USBREMOVED_MASK  |
+        NRF_POWER_INT_USBPWRRDY_MASK);
+    m_usbevt_handler = NULL;
+}
+#endif /* NRF_POWER_HAS_USBREG */
+
+
+/**
+ * @ingroup nrf_drv_power_internals
+ * @brief Interrupt handler
+ *
+ * POWER peripheral interrupt handler
+ */
+#if NRF_DRV_COMMON_POWER_CLOCK_ISR
+void nrf_drv_power_onIRQ(void)
+#else
+void POWER_POWER_IRQHandler(void)
+#endif
+{
+    uint32_t enabled = nrf_power_int_enable_get();
+    if((0 != (enabled & NRF_POWER_INT_POFWARN_MASK)) &&
+        nrf_power_event_get_and_clear(NRF_POWER_EVENT_POFWARN))
+    {
+        ASSERT(m_pofwarn_handler != NULL); /* Cannot be null if event is enabled */
+        m_pofwarn_handler();
+    }
+#if NRF_POWER_HAS_SLEEPEVT
+    if((0 != (enabled & NRF_POWER_INT_SLEEPENTER_MASK)) &&
+        nrf_power_event_get_and_clear(NRF_POWER_EVENT_SLEEPENTER))
+    {
+        ASSERT(m_sleepevt_handler != NULL); /* Cannot be null if event is enabled */
+        m_sleepevt_handler(NRF_DRV_POWER_SLEEP_EVT_ENTER);
+    }
+    if((0 != (enabled & NRF_POWER_INT_SLEEPEXIT_MASK)) &&
+        nrf_power_event_get_and_clear(NRF_POWER_EVENT_SLEEPEXIT))
+    {
+        ASSERT(m_sleepevt_handler != NULL); /* Cannot be null if event is enabled */
+        m_sleepevt_handler(NRF_DRV_POWER_SLEEP_EVT_EXIT);
+    }
+#endif
+#if NRF_POWER_HAS_USBREG
+    if((0 != (enabled & NRF_POWER_INT_USBDETECTED_MASK)) &&
+        nrf_power_event_get_and_clear(NRF_POWER_EVENT_USBDETECTED))
+    {
+        ASSERT(m_usbevt_handler != NULL); /* Cannot be null if event is enabled */
+        m_usbevt_handler(NRF_DRV_POWER_USB_EVT_DETECTED);
+    }
+    if((0 != (enabled & NRF_POWER_INT_USBREMOVED_MASK)) &&
+        nrf_power_event_get_and_clear(NRF_POWER_EVENT_USBREMOVED))
+    {
+        ASSERT(m_usbevt_handler != NULL); /* Cannot be null if event is enabled */
+        m_usbevt_handler(NRF_DRV_POWER_USB_EVT_REMOVED);
+    }
+    if((0 != (enabled & NRF_POWER_INT_USBPWRRDY_MASK)) &&
+        nrf_power_event_get_and_clear(NRF_POWER_EVENT_USBPWRRDY))
+    {
+        ASSERT(m_usbevt_handler != NULL); /* Cannot be null if event is enabled */
+        m_usbevt_handler(NRF_DRV_POWER_USB_EVT_READY);
+    }
+#endif
+}
+
+#endif /* POWER_ENABLED */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/power/nrf_drv_power.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,347 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef NRF_DRV_POWER_H__
+#define NRF_DRV_POWER_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "nrf_power.h"
+#include "sdk_config.h"
+#include "nrf_drv_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrf_power Power HAL and driver
+ * @ingroup nrf_drivers
+ * @brief POWER peripheral APIs.
+ *
+ * The power peripheral HAL provides basic APIs for accessing
+ * the registers of the POWER peripheral.
+ * The POWER driver provides APIs on a higher level.
+ */
+
+/**
+ * @defgroup nrf_drv_power POWER driver
+ * @{
+ * @ingroup nrf_power
+ * @brief Driver for managing events and the state of POWER peripheral.
+ *
+ */
+
+/**
+ * @brief Power mode possible configurations
+ */
+typedef enum
+{
+    NRF_DRV_POWER_MODE_CONSTLAT, /**< Constant latency mode *///!< NRF_DRV_POWER_MODE_CONSTLAT
+    NRF_DRV_POWER_MODE_LOWPWR    /**< Low power mode        *///!< NRF_DRV_POWER_MODE_LOWPWR
+}nrf_drv_power_mode_t;
+
+#if NRF_POWER_HAS_SLEEPEVT
+/**
+ * @brief Events from power system
+ */
+typedef enum
+{
+    NRF_DRV_POWER_SLEEP_EVT_ENTER, /**< CPU entered WFI/WFE sleep
+                                    *
+                                    * Keep in mind that if this interrupt is enabled,
+                                    * it means that CPU was waken up just after WFI by this interrupt.
+                                    */
+    NRF_DRV_POWER_SLEEP_EVT_EXIT   /**< CPU exited WFI/WFE sleep */
+}nrf_drv_power_sleep_evt_t;
+#endif /* NRF_POWER_HAS_SLEEPEVT */
+
+#if NRF_POWER_HAS_USBREG
+/**
+ * @brief Events from USB power system
+ */
+typedef enum
+{
+    NRF_DRV_POWER_USB_EVT_DETECTED, /**< USB power detected on the connector (plugged in). */
+    NRF_DRV_POWER_USB_EVT_REMOVED,  /**< USB power removed from the connector. */
+    NRF_DRV_POWER_USB_EVT_READY     /**< USB power regulator ready. */
+}nrf_drv_power_usb_evt_t;
+
+/**
+ * @brief USB power state
+ *
+ * The single enumerator that holds all data about current state of USB
+ * related POWER.
+ *
+ * Organized this way that higher power state has higher numeric value
+ */
+typedef enum
+{
+    NRF_DRV_POWER_USB_STATE_DISCONNECTED, /**< No power on USB lines detected */
+    NRF_DRV_POWER_USB_STATE_CONNECTED,    /**< The USB power is detected, but USB power regulator is not ready */
+    NRF_DRV_POWER_USB_STATE_READY         /**< From the power point of view USB is ready for working */
+}nrf_drv_power_usb_state_t;
+#endif /* NRF_POWER_HAS_USBREG */
+
+/**
+ * @name Callback types
+ *
+ * Defined types of callback functions
+ * @{
+ */
+/**
+ * @brief Event handler for power failure warning
+ */
+typedef void (*nrf_drv_power_pofwarn_event_handler_t)(void);
+
+#if NRF_POWER_HAS_SLEEPEVT
+/**
+ * @brief Event handler for entering/exiting sleep
+ *
+ * @param event Event type
+ */
+typedef void (*nrf_drv_power_sleep_event_handler_t)(nrf_drv_power_sleep_evt_t event);
+#endif
+
+#if NRF_POWER_HAS_USBREG
+/**
+ * @brief Event handler for USB related power events
+ *
+ * @param event Event type
+ */
+typedef void (*nrf_drv_power_usb_event_handler_t)(nrf_drv_power_usb_evt_t event);
+#endif
+/** @} */
+
+/**
+ * @brief General power configuration
+ *
+ * Parameters required to initialize power driver.
+ */
+typedef struct
+{
+    /**
+     * @brief Enable main DCDC regulator
+     *
+     * This bit only informs the driver that elements for DCDC regulator
+     * are installed and regulator can be used.
+     * The regulator would be enabled or disabled automatically
+     * automatically by the hardware, basing on current power requirement.
+     */
+    bool dcdcen:1;
+
+#if NRF_POWER_HAS_VDDH
+    /**
+     * @brief Enable HV DCDC regulator
+     *
+     * This bit only informs the driver that elements for DCDC regulator
+     * are installed and regulator can be used.
+     * The regulator would be enabled or disabled automatically
+     * automatically by the hardware, basing on current power requirement.
+     */
+    bool dcdcenhv: 1;
+#endif
+}nrf_drv_power_config_t;
+
+/**
+ * @brief The configuration for power failure comparator
+ *
+ * Configuration used to enable and configure power failure comparator
+ */
+typedef struct
+{
+    nrf_drv_power_pofwarn_event_handler_t handler; //!< Event handler
+    nrf_power_pof_thr_t                   thr;     //!< Threshold for power failure detection
+#if NRF_POWER_HAS_VDDH
+    nrf_power_pof_thrvddh_t               thrvddh; //!< Threshold for power failure detection on VDDH pin
+#endif
+}nrf_drv_power_pofwarn_config_t;
+
+#if NRF_POWER_HAS_SLEEPEVT
+/**
+ * @brief The configuration of sleep event processing
+ *
+ * Configuration used to enable and configure sleep event handling
+ */
+typedef struct
+{
+    nrf_drv_power_sleep_event_handler_t handler;    //!< Event handler
+    bool                                en_enter:1; //!< Enable event on sleep entering
+    bool                                en_exit :1; //!< Enable event on sleep exiting
+}nrf_drv_power_sleepevt_config_t;
+#endif
+
+#if NRF_POWER_HAS_USBREG
+/**
+ * @brief The configuration of USB related power events
+ *
+ * Configuration used to enable and configure USB power event handling
+ */
+typedef struct
+{
+    nrf_drv_power_usb_event_handler_t handler; //!< Event processing
+}nrf_drv_power_usbevt_config_t;
+#endif /* NRF_POWER_HAS_USBREG */
+
+/**
+ * @brief Function for checking if driver is already initialized
+ *
+ * This function is used to check whatever common POWER_CLOCK common interrupt
+ * should be disabled or not if @ref nrf_drv_clock tries to disable the interrupt.
+ *
+ * @retval true  Driver is initialized
+ * @retval false Driver is uninitialized
+ *
+ * @sa nrf_drv_power_uninit
+ */
+bool nrf_drv_power_init_check(void);
+
+/**
+ * @brief Initialize power module driver
+ *
+ * Enabled power module driver would process all the interrupts from power system.
+ *
+ * @param[in] p_config Driver configuration. Can be NULL - the default configuration
+ *                     from @em sdk_config.h file would be used then.
+ *
+ * @retval NRF_ERROR_MODULE_ALREADY_INITIALIZED Module is initialized already.
+ * @retval NRF_SUCCESS                          Successfully initialized.
+ */
+ret_code_t nrf_drv_power_init(nrf_drv_power_config_t const * p_config);
+
+/**
+ * @brief Unintialize power module driver
+ *
+ * Disables all the interrupt handling in the module.
+ *
+ * @sa nrf_drv_power_init
+ */
+void nrf_drv_power_uninit(void);
+
+/**
+ * @brief Initialize power failure comparator
+ *
+ * Configures and setups the power failure comparator and enables it.
+ *
+ * @param[in] p_config Configuration with values and event handler.
+ *                     If event handler is set to NULL, interrupt would be disabled.
+ */
+void nrf_drv_power_pof_init(nrf_drv_power_pofwarn_config_t const * p_config);
+
+/**
+ * @brief Turn off the power failure comparator
+ *
+ * Disables and clears the settings of the power failure comparator.
+ */
+void nrf_drv_power_pof_uninit(void);
+
+#if NRF_POWER_HAS_SLEEPEVT
+/**
+ * @brief Initialize sleep entering and exiting events processing
+ *
+ * Configures and setups the sleep event processing.
+ *
+ * @param[in] p_config Configuration with values and event handler.
+ *
+ * @sa nrf_drv_power_sleepevt_uninit
+ */
+void nrf_drv_power_sleepevt_init(nrf_drv_power_sleepevt_config_t const * p_config);
+
+/**
+ * @brief Uninitialize sleep entering and exiting events processing
+ *
+ * @sa nrf_drv_power_sleepevt_init
+ */
+void nrf_drv_power_sleepevt_uninit(void);
+#endif /* NRF_POWER_HAS_SLEEPEVT */
+
+#if NRF_POWER_HAS_USBREG
+/**
+ * @brief Initialize USB power event processing
+ *
+ * Configures and setups the USB power event processing.
+ *
+ * @param[in] p_config Configuration with values and event handler.
+ *
+ * @sa nrf_drv_power_usbevt_uninit
+ */
+void nrf_drv_power_usbevt_init(nrf_drv_power_usbevt_config_t const * p_config);
+
+/**
+ * @brief Uninitalize USB power event processing
+ *
+ * @sa nrf_drv_power_usbevt_init
+ */
+void nrf_drv_power_usbevt_uninit(void);
+
+/**
+ *  @brief Get the status of USB power
+ *
+ *  @return Current USB power status
+ */
+__STATIC_INLINE nrf_drv_power_usb_state_t nrf_drv_power_usbstatus_get(void);
+
+#endif /* NRF_POWER_HAS_USBREG */
+
+/** @} */
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+#if NRF_POWER_HAS_USBREG
+__STATIC_INLINE nrf_drv_power_usb_state_t nrf_drv_power_usbstatus_get(void)
+{
+    uint32_t status = nrf_power_usbregstatus_get();
+    if(0 == (status & NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK))
+    {
+        return NRF_DRV_POWER_USB_STATE_DISCONNECTED;
+    }
+    if(0 == (status & NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK))
+    {
+        return NRF_DRV_POWER_USB_STATE_CONNECTED;
+    }
+    return NRF_DRV_POWER_USB_STATE_READY;
+}
+#endif /* NRF_POWER_HAS_USBREG */
+
+#endif /* SUPPRESS_INLINE_IMPLEMENTATION */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF_DRV_POWER_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/ppi/nrf_drv_ppi.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,538 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(PPI)
+#include <stdlib.h>
+
+#include "nrf.h"
+#include "nrf_drv_ppi.h"
+#include "nrf_drv_common.h"
+#include "nrf_ppi.h"
+#include "app_util_platform.h"
+
+#define NRF_LOG_MODULE_NAME "PPI"
+
+#if PPI_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       PPI_CONFIG_LOG_LEVEL
+#define NRF_LOG_INFO_COLOR  PPI_CONFIG_INFO_COLOR
+#define NRF_LOG_DEBUG_COLOR PPI_CONFIG_DEBUG_COLOR
+#else //PPI_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       0
+#endif //PPI_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+
+
+static nrf_drv_state_t     m_drv_state;            /**< Driver state */
+static uint32_t            m_channels_allocated;   /**< Bitmap representing channels availability. 1 when a channel is allocated, 0 otherwise. */
+static uint8_t             m_groups_allocated;     /**< Bitmap representing groups availability. 1 when a group is allocated, 0 otherwise.*/
+
+
+/**@brief  Compute a group mask (needed for driver internals, not used for NRF_PPI registers).
+ * @param[in]  group  Group number to transform to a mask.
+ * @retval     Group mask.
+ */
+__STATIC_INLINE uint32_t group_to_mask(nrf_ppi_channel_group_t group)
+{
+    return (1uL << (uint32_t) group);
+}
+
+
+/**@brief  Check whether a channel is a programmable channel and can be used by an application.
+ * @param[in]  channel  Channel to check.
+ * @retval     true     The channel is a programmable application channel.
+ *             false    The channel is used by a SoftDevice or is preprogrammed.
+ */
+__STATIC_INLINE bool is_programmable_app_channel(nrf_ppi_channel_t channel)
+{
+    return ((NRF_PPI_PROG_APP_CHANNELS_MASK & nrf_drv_ppi_channel_to_mask(channel)) != 0);
+}
+
+
+/**@brief  Check whether a channels can be used by an application.
+ * @param[in]  channel  Channel mask to check.
+ * @retval     true     All specified channels can be used by an application.
+ *             false    At least one specified channel is used by a SoftDevice.
+ */
+__STATIC_INLINE bool are_app_channels(uint32_t channel_mask)
+{
+    //lint -e(587)
+    return ((~(NRF_PPI_ALL_APP_CHANNELS_MASK) & channel_mask) == 0);
+}
+
+
+/**@brief  Check whether a channel can be used by an application.
+ * @param[in]  channel  Channel to check.
+ * @retval     true     The channel can be used by an application.
+ *             false    The channel is used by a SoftDevice.
+ */
+__STATIC_INLINE bool is_app_channel(nrf_ppi_channel_t channel)
+{
+    return are_app_channels(nrf_drv_ppi_channel_to_mask(channel));
+}
+
+
+/**@brief  Check whether a channel group can be used by an application.
+ * @param[in]  group    Group to check.
+ * @retval     true     The group is an application group.
+ *             false    The group is not an application group (this group either does not exist or
+ *                      it is used by a SoftDevice).
+ */
+__STATIC_INLINE bool is_app_group(nrf_ppi_channel_group_t group)
+{
+    return ((NRF_PPI_ALL_APP_GROUPS_MASK & group_to_mask(group)) != 0);
+}
+
+
+/**@brief  Check whether a channel is allocated.
+ * @param[in]  channel_num  Channel number to check.
+ * @retval     true         The channel is allocated.
+ *             false        The channel is not allocated.
+ */
+__STATIC_INLINE bool is_allocated_channel(nrf_ppi_channel_t channel)
+{
+    return ((m_channels_allocated & nrf_drv_ppi_channel_to_mask(channel)) != 0);
+}
+
+
+/**@brief  Set channel allocated indication.
+ * @param[in]  channel_num  Specifies the channel to set the "allocated" indication.
+ */
+__STATIC_INLINE void channel_allocated_set(nrf_ppi_channel_t channel)
+{
+    m_channels_allocated |= nrf_drv_ppi_channel_to_mask(channel);
+}
+
+
+/**@brief  Clear channel allocated indication.
+ * @param[in]  channel_num  Specifies the channel to clear the "allocated" indication.
+ */
+__STATIC_INLINE void channel_allocated_clr(nrf_ppi_channel_t channel)
+{
+    m_channels_allocated &= ~nrf_drv_ppi_channel_to_mask(channel);
+}
+
+
+/**@brief  Clear all allocated channels.
+ */
+__STATIC_INLINE void channel_allocated_clr_all(void)
+{
+    m_channels_allocated &= ~NRF_PPI_ALL_APP_CHANNELS_MASK;
+}
+
+
+/**@brief  Check whether a group is allocated.
+ * @param[in]  group_num    Group number to check.
+ * @retval     true         The group is allocated.
+ *             false        The group is not allocated.
+ */
+__STATIC_INLINE bool is_allocated_group(nrf_ppi_channel_group_t group)
+{
+    return ((m_groups_allocated & group_to_mask(group)) != 0);
+}
+
+
+/**@brief  Set group allocated indication.
+ * @param[in]  group_num  Specifies the group to set the "allocated" indication.
+ */
+__STATIC_INLINE void group_allocated_set(nrf_ppi_channel_group_t group)
+{
+    m_groups_allocated |= group_to_mask(group);
+}
+
+
+/**@brief  Clear group allocated indication.
+ * @param[in]  group_num  Specifies the group to clear the "allocated" indication.
+ */
+__STATIC_INLINE void group_allocated_clr(nrf_ppi_channel_group_t group)
+{
+    m_groups_allocated &= ~group_to_mask(group);
+}
+
+
+/**@brief  Clear all allocated groups.
+ */
+__STATIC_INLINE void group_allocated_clr_all()
+{
+    m_groups_allocated &= ~NRF_PPI_ALL_APP_GROUPS_MASK;
+}
+
+
+uint32_t nrf_drv_ppi_init(void)
+{
+    uint32_t err_code;
+
+    if (m_drv_state == NRF_DRV_STATE_UNINITIALIZED)
+    {
+        m_drv_state = NRF_DRV_STATE_INITIALIZED;
+        err_code    = NRF_SUCCESS;
+    }
+    else
+    {
+
+        err_code = NRF_ERROR_MODULE_ALREADY_INITIALIZED;
+    }
+
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+uint32_t nrf_drv_ppi_uninit(void)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+    uint32_t mask = NRF_PPI_ALL_APP_GROUPS_MASK;
+    nrf_ppi_channel_group_t group;
+
+    if (m_drv_state == NRF_DRV_STATE_UNINITIALIZED)
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    m_drv_state = NRF_DRV_STATE_UNINITIALIZED;
+
+    // Disable all channels and groups
+    nrf_ppi_channels_disable(NRF_PPI_ALL_APP_CHANNELS_MASK);
+
+    for (group = NRF_PPI_CHANNEL_GROUP0; mask != 0; mask &= ~group_to_mask(group), group++)
+    {
+        if (mask & group_to_mask(group))
+        {
+            nrf_ppi_channel_group_clear(group);
+        }
+    }
+    channel_allocated_clr_all();
+    group_allocated_clr_all();
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+uint32_t nrf_drv_ppi_channel_alloc(nrf_ppi_channel_t * p_channel)
+{
+    uint32_t err_code = NRF_SUCCESS;
+    nrf_ppi_channel_t channel;
+    uint32_t mask = 0;
+
+    err_code = NRF_ERROR_NO_MEM;
+
+    mask = NRF_PPI_PROG_APP_CHANNELS_MASK;
+    for (channel = NRF_PPI_CHANNEL0; mask != 0; mask &= ~nrf_drv_ppi_channel_to_mask(channel), channel++)
+    {
+        CRITICAL_REGION_ENTER();
+        if ((mask & nrf_drv_ppi_channel_to_mask(channel)) && (!is_allocated_channel(channel)))
+        {
+            channel_allocated_set(channel);
+            *p_channel = channel;
+            err_code   = NRF_SUCCESS;
+        }
+        CRITICAL_REGION_EXIT();
+        if (err_code == NRF_SUCCESS)
+        {
+            NRF_LOG_INFO("Allocated channel: %d.\r\n", channel);
+            break;
+        }
+    }
+
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+uint32_t nrf_drv_ppi_channel_free(nrf_ppi_channel_t channel)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+
+    if (!is_programmable_app_channel(channel))
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+    }
+    else
+    {
+        // First disable this channel
+        nrf_ppi_channel_disable(channel);
+        CRITICAL_REGION_ENTER();
+        channel_allocated_clr(channel);
+        CRITICAL_REGION_EXIT();
+    }
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+uint32_t nrf_drv_ppi_channel_assign(nrf_ppi_channel_t channel, uint32_t eep, uint32_t tep)
+{
+    VERIFY_PARAM_NOT_NULL((uint32_t *)eep);
+    VERIFY_PARAM_NOT_NULL((uint32_t *)tep);
+
+    ret_code_t err_code = NRF_SUCCESS;
+
+    if (!is_programmable_app_channel(channel))
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+    }
+    else if (!is_allocated_channel(channel))
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+    }
+    else
+    {
+        nrf_ppi_channel_endpoint_setup(channel, eep, tep);
+        NRF_LOG_INFO("Assigned channel: %d, event end point: %x, task end point: %x.\r\n", channel, eep, tep);
+    }
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+uint32_t nrf_drv_ppi_channel_fork_assign(nrf_ppi_channel_t channel, uint32_t fork_tep)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+#ifdef PPI_FEATURE_FORKS_PRESENT
+    if (!is_programmable_app_channel(channel))
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+    }
+    else if (!is_allocated_channel(channel))
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+    }
+    else
+    {
+        nrf_ppi_fork_endpoint_setup(channel, fork_tep);
+        NRF_LOG_INFO("Fork assigned channel: %d, task end point: %d.\r\n", channel, fork_tep);
+    }
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+#else   
+    err_code = NRF_ERROR_NOT_SUPPORTED;
+    NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+#endif
+}
+
+uint32_t nrf_drv_ppi_channel_enable(nrf_ppi_channel_t channel)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+
+    if (!is_app_channel(channel))
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+    }
+    else if (is_programmable_app_channel(channel) && !is_allocated_channel(channel))
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+    }
+    else
+    {
+        nrf_ppi_channel_enable(channel);
+    }
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+uint32_t nrf_drv_ppi_channel_disable(nrf_ppi_channel_t channel)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+
+    if (!is_app_channel(channel))
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+    }
+    else if (is_programmable_app_channel(channel) && !is_allocated_channel(channel))
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+    }
+    else
+    {
+        nrf_ppi_channel_disable(channel);
+        err_code = NRF_SUCCESS;
+    }
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+uint32_t nrf_drv_ppi_group_alloc(nrf_ppi_channel_group_t * p_group)
+{
+    uint32_t err_code;
+    uint32_t mask = 0;
+    nrf_ppi_channel_group_t group;
+
+    err_code = NRF_ERROR_NO_MEM;
+
+    mask = NRF_PPI_ALL_APP_GROUPS_MASK;
+    for (group = NRF_PPI_CHANNEL_GROUP0; mask != 0; mask &= ~group_to_mask(group), group++)
+    {
+        CRITICAL_REGION_ENTER();
+        if ((mask & group_to_mask(group)) && (!is_allocated_group(group)))
+        {
+            group_allocated_set(group);
+            *p_group = group;
+            err_code = NRF_SUCCESS;
+        }
+        CRITICAL_REGION_EXIT();
+        if (err_code == NRF_SUCCESS)
+        {
+            NRF_LOG_INFO("Allocated group: %d.\r\n", group);
+            break;
+        }
+    }
+
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+uint32_t nrf_drv_ppi_group_free(nrf_ppi_channel_group_t group)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+
+    if (!is_app_group(group))
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+    }
+    if (!is_allocated_group(group))
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+    }
+    else
+    {
+        nrf_ppi_group_disable(group);
+        CRITICAL_REGION_ENTER();
+        group_allocated_clr(group);
+        CRITICAL_REGION_EXIT();
+    }
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+uint32_t nrf_drv_ppi_group_enable(nrf_ppi_channel_group_t group)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+
+    if (!is_app_group(group))
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+    }
+    else if (!is_allocated_group(group))
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+    }
+    else
+    {
+        nrf_ppi_group_enable(group);
+    }
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+uint32_t nrf_drv_ppi_group_disable(nrf_ppi_channel_group_t group)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+
+    if (!is_app_group(group))
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+    }
+    else
+    {
+        nrf_ppi_group_disable(group);
+    }
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+uint32_t nrf_drv_ppi_channels_remove_from_group(uint32_t channel_mask,
+                                                nrf_ppi_channel_group_t group)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+
+    if (!is_app_group(group))
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+    }
+    else if (!is_allocated_group(group))
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+    }
+    else if (!are_app_channels(channel_mask))
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+    }
+    else
+    {
+        CRITICAL_REGION_ENTER();
+        nrf_ppi_channels_remove_from_group(channel_mask, group);
+        CRITICAL_REGION_EXIT();
+    }
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+uint32_t nrf_drv_ppi_channels_include_in_group(uint32_t channel_mask,
+                                               nrf_ppi_channel_group_t group)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+    
+    if (!is_app_group(group))
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+    }
+    else if (!is_allocated_group(group))
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+    }
+    else if (!are_app_channels(channel_mask))
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+    }
+    else
+    {   
+        CRITICAL_REGION_ENTER();
+        nrf_ppi_channels_include_in_group(channel_mask, group);
+        CRITICAL_REGION_EXIT();
+    }
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+#endif //NRF_MODULE_ENABLED(PPI)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/ppi/nrf_drv_ppi.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,315 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_DRV_PPI_H
+#define NRF_DRV_PPI_H
+
+/*lint ++flb "Enter library region" */
+#include "sdk_errors.h"
+#include "nrf_ppi.h"
+#include <stdbool.h>
+#include <stdint.h>
+
+/** @file
+ *
+ * @addtogroup nrf_ppi PPI HAL and driver
+ * @ingroup nrf_drivers
+ * @brief Programmable Peripheral Interconnect (PPI) APIs.
+ *
+ * @details The PPI HAL provides basic APIs for accessing the registers of the PPI.
+ * The PPI driver provides APIs on a higher level.
+ *
+ * @defgroup nrf_drv_ppi PPI driver
+ * @{
+ * @ingroup  nrf_ppi
+ *
+ * @brief Programmable Peripheral Interconnect (PPI) driver.
+ */
+
+#include "sdk_resources.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if PPI_CH_NUM > 16
+#define NRF_PPI_ALL_APP_CHANNELS_MASK   ((uint32_t)0xFFFFFFFFuL & ~(NRF_PPI_CHANNELS_USED))  /**< All PPI channels available to the application. */
+#define NRF_PPI_PROG_APP_CHANNELS_MASK  ((uint32_t)0x000FFFFFuL & ~(NRF_PPI_CHANNELS_USED))  /**< Programmable PPI channels available to the application. */
+#else
+#define NRF_PPI_ALL_APP_CHANNELS_MASK   ((uint32_t)0xFFF0FFFFuL & ~(NRF_PPI_CHANNELS_USED))  /**< All PPI channels available to the application. */
+#define NRF_PPI_PROG_APP_CHANNELS_MASK  ((uint32_t)0x0000FFFFuL & ~(NRF_PPI_CHANNELS_USED))  /**< Programmable PPI channels available to the application. */
+#endif
+
+#define NRF_PPI_ALL_APP_GROUPS_MASK     (((1uL << PPI_GROUP_NUM) - 1) & ~(NRF_PPI_GROUPS_USED))    /**< All PPI groups available to the application. */
+
+
+/**@brief Function for initializing PPI module.
+ *
+ * @retval     NRF_SUCCESS                           If the module was successfully initialized.
+ * @retval     NRF_ERROR_MODULE_ALREADY_INITIALIZED  If the module has already been initialized.
+ */
+uint32_t nrf_drv_ppi_init(void);
+
+/**@brief Function for uninitializing the PPI module.
+ *
+ * This function also disables all channels and clears the channel groups.
+ *
+ * @retval     NRF_SUCCESS             If the module was successfully uninitialized.
+ * @retval     NRF_ERROR_INVALID_STATE If the module has not been initialized yet.
+ * @retval     NRF_ERROR_INTERNAL      If the channels or groups could not be disabled.
+ */
+uint32_t nrf_drv_ppi_uninit(void);
+
+/**@brief Function for allocating a PPI channel.
+ * @details This function allocates the first unused PPI channel.
+ *
+ * @param[out] p_channel               Pointer to the PPI channel that has been allocated.
+ *
+ * @retval     NRF_SUCCESS             If the channel was successfully allocated.
+ * @retval     NRF_ERROR_NO_MEM        If there is no available channel to be used.
+ */
+uint32_t nrf_drv_ppi_channel_alloc(nrf_ppi_channel_t * p_channel);
+
+/**@brief Function for freeing a PPI channel.
+ * @details This function also disables the chosen channel.
+ *
+ * @param[in]  channel                 PPI channel to be freed.
+ *
+ * @retval     NRF_SUCCESS             If the channel was successfully freed.
+ * @retval     NRF_ERROR_INVALID_PARAM If the channel is not user-configurable.
+ */
+uint32_t nrf_drv_ppi_channel_free(nrf_ppi_channel_t channel);
+
+/**@brief Function for assigning task and event endpoints to the PPI channel.
+ *
+ * @param[in]  channel                 PPI channel to be assigned endpoints.
+ *
+ * @param[in]  eep                     Event endpoint address.
+ *
+ * @param[in]  tep                     Task endpoint address.
+ *
+ * @retval     NRF_SUCCESS             If the channel was successfully assigned.
+ * @retval     NRF_ERROR_INVALID_STATE If the channel is not allocated for the user.
+ * @retval     NRF_ERROR_INVALID_PARAM If the channel is not user-configurable.
+ */
+uint32_t nrf_drv_ppi_channel_assign(nrf_ppi_channel_t channel, uint32_t eep, uint32_t tep);
+
+/**@brief Function for assigning or clearing fork endpoint to the PPI channel.
+ *
+ * @param[in]  channel                 PPI channel to be assigned endpoints.
+ *
+ * @param[in]  fork_tep                Fork task endpoint address or 0 to clear.
+ *
+ * @retval     NRF_SUCCESS             If the channel was successfully assigned.
+ * @retval     NRF_ERROR_INVALID_STATE If the channel is not allocated for the user.
+ * @retval     NRF_ERROR_INVALID_PARAM If the channel is not user-configurable.
+ * @retval     NRF_ERROR_NOT_SUPPORTED If function is not supported.
+ */
+uint32_t nrf_drv_ppi_channel_fork_assign(nrf_ppi_channel_t channel, uint32_t fork_tep);
+
+/**@brief Function for enabling a PPI channel.
+ *
+ * @param[in]  channel                 PPI channel to be enabled.
+ *
+ * @retval     NRF_SUCCESS             If the channel was successfully enabled.
+ * @retval     NRF_ERROR_INVALID_STATE If the user-configurable channel is not allocated.
+ * @retval     NRF_ERROR_INVALID_PARAM If the channel cannot be enabled by the user.
+ */
+uint32_t nrf_drv_ppi_channel_enable(nrf_ppi_channel_t channel);
+
+/**@brief Function for disabling a PPI channel.
+ *
+ * @param[in]  channel                 PPI channel to be disabled.
+ *
+ * @retval     NRF_SUCCESS             If the channel was successfully disabled.
+ * @retval     NRF_ERROR_INVALID_STATE If the user-configurable channel is not allocated.
+ * @retval     NRF_ERROR_INVALID_PARAM If the channel cannot be disabled by the user.
+ */
+uint32_t nrf_drv_ppi_channel_disable(nrf_ppi_channel_t channel);
+
+/**@brief Function for allocating a PPI channel group.
+ * @details This function allocates the first unused PPI group.
+ *
+ * @param[out] p_group                 Pointer to the PPI channel group that has been allocated.
+ *
+ * @retval     NRF_SUCCESS             If the channel group was successfully allocated.
+ * @retval     NRF_ERROR_NO_MEM        If there is no available channel group to be used.
+ */
+uint32_t nrf_drv_ppi_group_alloc(nrf_ppi_channel_group_t * p_group);
+
+/**@brief Function for freeing a PPI channel group.
+ * @details This function also disables the chosen group.
+ *
+ * @param[in]  group                   PPI channel group to be freed.
+ *
+ * @retval     NRF_SUCCESS             If the channel group was successfully freed.
+ * @retval     NRF_ERROR_INVALID_PARAM If the channel group is not user-configurable.
+ */
+uint32_t nrf_drv_ppi_group_free(nrf_ppi_channel_group_t group);
+
+/**@brief  Compute a channel mask for NRF_PPI registers.
+ *
+ * @param[in]  channel  Channel number to transform to a mask.
+ *
+ * @retval     Channel mask.
+ */
+__STATIC_INLINE uint32_t nrf_drv_ppi_channel_to_mask(nrf_ppi_channel_t channel)
+{
+    return (1uL << (uint32_t) channel);
+}
+
+/**@brief Function for including multiple PPI channels in a channel group.
+ *
+ * @param[in]  channel_mask            PPI channels to be added.
+ * @param[in]  group                   Channel group in which to include the channels.
+ *
+ * @retval     NRF_SUCCESS             If the channels was successfully included.
+ */
+uint32_t nrf_drv_ppi_channels_include_in_group(uint32_t channel_mask,
+                                               nrf_ppi_channel_group_t group);
+
+/**@brief Function for including a PPI channel in a channel group.
+ *
+ * @param[in]  channel                 PPI channel to be added.
+ * @param[in]  group                   Channel group in which to include the channel.
+ *
+ * @retval     NRF_SUCCESS             If the channel was successfully included.
+ */
+__STATIC_INLINE uint32_t nrf_drv_ppi_channel_include_in_group(nrf_ppi_channel_t       channel,
+                                                              nrf_ppi_channel_group_t group)
+{
+    return nrf_drv_ppi_channels_include_in_group(nrf_drv_ppi_channel_to_mask(channel), group);
+}
+
+/**@brief Function for removing multiple PPI channels from a channel group.
+ *
+ * @param[in]  channel_mask            PPI channels to be removed.
+ * @param[in]  group                   Channel group from which to remove the channels.
+ *
+ * @retval     NRF_SUCCESS             If the channel was successfully removed.
+ */
+uint32_t nrf_drv_ppi_channels_remove_from_group(uint32_t channel_mask,
+                                                nrf_ppi_channel_group_t group);
+
+/**@brief Function for removing a PPI channel from a channel group.
+ *
+ * @param[in]  channel                 PPI channel to be removed.
+ * @param[in]  group                   Channel group from which to remove the channel.
+ *
+ * @retval     NRF_SUCCESS             If the channel was successfully removed.
+ */
+__STATIC_INLINE uint32_t nrf_drv_ppi_channel_remove_from_group(nrf_ppi_channel_t       channel,
+                                                               nrf_ppi_channel_group_t group)
+{
+    return nrf_drv_ppi_channels_remove_from_group(nrf_drv_ppi_channel_to_mask(channel), group);
+}
+
+/**@brief Function for clearing a PPI channel group.
+ *
+ * @param[in]  group                   Channel group to be cleared.
+ *
+ * @retval     NRF_SUCCESS             If the group was successfully cleared.
+ */
+__STATIC_INLINE uint32_t nrf_drv_ppi_group_clear(nrf_ppi_channel_group_t group)
+{
+    return nrf_drv_ppi_channels_remove_from_group(NRF_PPI_ALL_APP_CHANNELS_MASK, group);
+}
+
+/**@brief Function for enabling a PPI channel group.
+ *
+ * @param[in]  group                   Channel group to be enabled.
+ *
+ * @retval     NRF_SUCCESS             If the group was successfully enabled.
+ */
+uint32_t nrf_drv_ppi_group_enable(nrf_ppi_channel_group_t group);
+
+/**@brief Function for disabling a PPI channel group.
+ *
+ * @param[in]  group                   Channel group to be disabled.
+ *
+ * @retval     NRF_SUCCESS             If the group was successfully disabled.
+ */
+uint32_t nrf_drv_ppi_group_disable(nrf_ppi_channel_group_t group);
+
+/**
+ * @brief Function for getting the address of a PPI task.
+ *
+ * @param[in]  task                      Task.
+ *
+ * @retval     Task address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_ppi_task_addr_get(nrf_ppi_task_t task)
+{
+    return (uint32_t) nrf_ppi_task_address_get(task);
+}
+
+/**
+ * @brief Function for getting the address of a PPI group enable task.
+ *
+ * @param[in]  group                     PPI channel group
+ *
+ * @retval     Task address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_ppi_task_addr_group_enable_get(nrf_ppi_channel_group_t group)
+{
+    return (uint32_t) nrf_ppi_task_group_enable_address_get(group);
+}
+
+/**
+ * @brief Function for getting the address of a PPI group enable task.
+ *
+ * @param[in]  group                     PPI channel group
+ *
+ * @retval     Task address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_ppi_task_addr_group_disable_get(nrf_ppi_channel_group_t group)
+{
+    return (uint32_t) nrf_ppi_task_group_disable_address_get(group);
+}
+
+/**
+ *@}
+ **/
+
+/*lint --flb "Leave library region" */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_DRV_PPI_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/pwm/nrf_drv_pwm.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,410 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(PWM)
+#define ENABLED_PWM_COUNT (PWM0_ENABLED+PWM1_ENABLED+PWM2_ENABLED)
+#if ENABLED_PWM_COUNT
+#include <string.h>
+#include "nrf_drv_pwm.h"
+#include "nrf_drv_common.h"
+#include "nrf_gpio.h"
+#include "app_util_platform.h"
+
+#define NRF_LOG_MODULE_NAME "PWM"
+
+#if PWM_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       PWM_CONFIG_LOG_LEVEL
+#define NRF_LOG_INFO_COLOR  PWM_CONFIG_INFO_COLOR
+#define NRF_LOG_DEBUG_COLOR PWM_CONFIG_DEBUG_COLOR
+#else //PWM_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       0
+#endif //PWM_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+
+// Control block - driver instance local data.
+typedef struct
+{
+    nrf_drv_pwm_handler_t    handler;
+    nrf_drv_state_t volatile state;
+} pwm_control_block_t;
+static pwm_control_block_t m_cb[ENABLED_PWM_COUNT];
+
+static void configure_pins(nrf_drv_pwm_t const * const p_instance,
+                           nrf_drv_pwm_config_t const * p_config)
+{
+    uint32_t out_pins[NRF_PWM_CHANNEL_COUNT];
+    uint8_t i;
+
+    for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i)
+    {
+        uint8_t output_pin = p_config->output_pins[i];
+        if (output_pin != NRF_DRV_PWM_PIN_NOT_USED)
+        {
+            bool inverted = output_pin &  NRF_DRV_PWM_PIN_INVERTED;
+            out_pins[i]   = output_pin & ~NRF_DRV_PWM_PIN_INVERTED;
+
+            if (inverted)
+            {
+                nrf_gpio_pin_set(out_pins[i]);
+            }
+            else
+            {
+                nrf_gpio_pin_clear(out_pins[i]);
+            }
+
+            nrf_gpio_cfg_output(out_pins[i]);
+        }
+        else
+        {
+            out_pins[i] = NRF_PWM_PIN_NOT_CONNECTED;
+        }
+    }
+
+    nrf_pwm_pins_set(p_instance->p_registers, out_pins);
+}
+
+
+ret_code_t nrf_drv_pwm_init(nrf_drv_pwm_t const * const p_instance,
+                            nrf_drv_pwm_config_t const * p_config,
+                            nrf_drv_pwm_handler_t        handler)
+{
+    ASSERT(p_config);
+
+    ret_code_t err_code;
+    
+    pwm_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
+
+    if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    p_cb->handler = handler;
+
+    configure_pins(p_instance, p_config);
+
+    nrf_pwm_enable(p_instance->p_registers);
+    nrf_pwm_configure(p_instance->p_registers,
+        p_config->base_clock, p_config->count_mode, p_config->top_value);
+    nrf_pwm_decoder_set(p_instance->p_registers,
+        p_config->load_mode, p_config->step_mode);
+
+    nrf_pwm_shorts_set(p_instance->p_registers, 0);
+    nrf_pwm_int_set(p_instance->p_registers, 0);
+    nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_LOOPSDONE);
+    nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_SEQEND0);
+    nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_SEQEND1);
+    nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_STOPPED);
+
+    if (p_cb->handler)
+    {
+        nrf_drv_common_irq_enable(nrf_drv_get_IRQn(p_instance->p_registers),
+            p_config->irq_priority);
+    }
+
+    p_cb->state = NRF_DRV_STATE_INITIALIZED;
+
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+void nrf_drv_pwm_uninit(nrf_drv_pwm_t const * const p_instance)
+{
+    pwm_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+
+    nrf_drv_common_irq_disable(nrf_drv_get_IRQn(p_instance->p_registers));
+
+    nrf_pwm_disable(p_instance->p_registers);
+
+    p_cb->state = NRF_DRV_STATE_UNINITIALIZED;
+}
+
+
+static void start_playback(nrf_drv_pwm_t const * const p_instance,
+                           pwm_control_block_t * p_cb,
+                           uint8_t               flags,
+                           nrf_pwm_task_t        starting_task)
+{
+    p_cb->state = NRF_DRV_STATE_POWERED_ON;
+
+    if (p_cb->handler)
+    {
+        // The notification about finished playback is by default enabled, but
+        // this can be suppressed. The notification that the peripheral has been
+        // stopped is always enable.
+        uint32_t int_mask = NRF_PWM_INT_LOOPSDONE_MASK |
+                            NRF_PWM_INT_STOPPED_MASK;
+
+        if (flags & NRF_DRV_PWM_FLAG_SIGNAL_END_SEQ0)
+        {
+            int_mask |= NRF_PWM_INT_SEQEND0_MASK;
+        }
+        if (flags & NRF_DRV_PWM_FLAG_SIGNAL_END_SEQ1)
+        {
+            int_mask |= NRF_PWM_INT_SEQEND1_MASK;
+        }
+        if (flags & NRF_DRV_PWM_FLAG_NO_EVT_FINISHED)
+        {
+            int_mask &= ~NRF_PWM_INT_LOOPSDONE_MASK;
+        }
+
+        nrf_pwm_int_set(p_instance->p_registers, int_mask);
+    }
+
+    nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_STOPPED);
+
+    nrf_pwm_task_trigger(p_instance->p_registers, starting_task);
+}
+
+
+void nrf_drv_pwm_simple_playback(nrf_drv_pwm_t const * const p_instance,
+                                 nrf_pwm_sequence_t const * p_sequence,
+                                 uint16_t                   playback_count,
+                                 uint32_t                   flags)
+{
+    pwm_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+    ASSERT(playback_count > 0);
+    ASSERT(nrf_drv_is_in_RAM(p_sequence->values.p_raw));
+
+    // To take advantage of the looping mechanism, we need to use both sequences
+    // (single sequence can be played back only once).
+    nrf_pwm_sequence_set(p_instance->p_registers, 0, p_sequence);
+    nrf_pwm_sequence_set(p_instance->p_registers, 1, p_sequence);
+    bool odd = (playback_count & 1);
+    nrf_pwm_loop_set(p_instance->p_registers, playback_count / 2 + (odd ? 1 : 0));
+
+    uint32_t shorts_mask;
+    if (flags & NRF_DRV_PWM_FLAG_STOP)
+    {
+        shorts_mask = NRF_PWM_SHORT_LOOPSDONE_STOP_MASK;
+    }
+    else if (flags & NRF_DRV_PWM_FLAG_LOOP)
+    {
+        shorts_mask = odd ? NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK
+                          : NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK;
+    }
+    else
+    {
+        shorts_mask = 0;
+    }
+    nrf_pwm_shorts_set(p_instance->p_registers, shorts_mask);
+
+    NRF_LOG_INFO("Function: %s, sequence length: %d.\r\n", (uint32_t)__func__,
+                    p_sequence->length * sizeof(p_sequence->values));
+    NRF_LOG_DEBUG("Sequence data:\r\n");
+    NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_sequence->values.p_raw,  p_sequence->length * sizeof(p_sequence->values));
+    start_playback(p_instance, p_cb, flags, odd ? NRF_PWM_TASK_SEQSTART1
+                                                : NRF_PWM_TASK_SEQSTART0);
+}
+
+
+void nrf_drv_pwm_complex_playback(nrf_drv_pwm_t const * const p_instance,
+                                  nrf_pwm_sequence_t const * p_sequence_0,
+                                  nrf_pwm_sequence_t const * p_sequence_1,
+                                  uint16_t                   playback_count,
+                                  uint32_t                   flags)
+{
+    pwm_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+    ASSERT(playback_count > 0);
+    ASSERT(nrf_drv_is_in_RAM(p_sequence_0->values.p_raw));
+    ASSERT(nrf_drv_is_in_RAM(p_sequence_1->values.p_raw));
+
+    nrf_pwm_sequence_set(p_instance->p_registers, 0, p_sequence_0);
+    nrf_pwm_sequence_set(p_instance->p_registers, 1, p_sequence_1);
+    nrf_pwm_loop_set(p_instance->p_registers, playback_count);
+
+    uint32_t shorts_mask;
+    if (flags & NRF_DRV_PWM_FLAG_STOP)
+    {
+        shorts_mask = NRF_PWM_SHORT_LOOPSDONE_STOP_MASK;
+    }
+    else if (flags & NRF_DRV_PWM_FLAG_LOOP)
+    {
+        shorts_mask = NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK;
+    }
+    else
+    {
+        shorts_mask = 0;
+    }
+    nrf_pwm_shorts_set(p_instance->p_registers, shorts_mask);
+
+    NRF_LOG_INFO("Function: %s, sequence 0 length: %d.\r\n", (uint32_t)__func__,
+                    p_sequence_0->length * sizeof(p_sequence_0->values));
+    NRF_LOG_INFO("Function: %s, sequence 1 length: %d.\r\n", (uint32_t)__func__,
+                    p_sequence_1->length * sizeof(p_sequence_1->values));
+    NRF_LOG_DEBUG("Sequence 0 data:\r\n");
+    NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_sequence_0->values.p_raw,
+                            p_sequence_0->length * sizeof(p_sequence_0->values));
+    NRF_LOG_DEBUG("Sequence 1 data:\r\n");
+    NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_sequence_1->values.p_raw,
+                            p_sequence_1->length * sizeof(p_sequence_1->values));
+    start_playback(p_instance, p_cb, flags, NRF_PWM_TASK_SEQSTART0);
+}
+
+
+bool nrf_drv_pwm_stop(nrf_drv_pwm_t const * const p_instance,
+                      bool wait_until_stopped)
+{
+    ASSERT(m_cb[p_instance->drv_inst_idx].state != NRF_DRV_STATE_UNINITIALIZED);
+
+    bool ret_val = false;
+
+    if (nrf_drv_pwm_is_stopped(p_instance))
+    {
+        ret_val = true;
+    }
+    else
+    {
+        nrf_pwm_task_trigger(p_instance->p_registers, NRF_PWM_TASK_STOP);
+
+        do {
+            if (nrf_drv_pwm_is_stopped(p_instance))
+            {
+                ret_val = true;
+                break;
+            }
+        } while (wait_until_stopped);
+    }
+
+    NRF_LOG_INFO("%s returned %d.\r\n", (uint32_t)__func__, ret_val);
+    return ret_val;
+}
+
+
+bool nrf_drv_pwm_is_stopped(nrf_drv_pwm_t const * const p_instance)
+{
+    pwm_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+
+    bool ret_val = false;
+
+    // If the event handler is used (interrupts are enabled), the state will
+    // be changed in interrupt handler when the STOPPED event occurs.
+    if (p_cb->state != NRF_DRV_STATE_POWERED_ON)
+    {
+        ret_val = true;
+    }
+    // If interrupts are disabled, we must check the STOPPED event here.
+    if (nrf_pwm_event_check(p_instance->p_registers, NRF_PWM_EVENT_STOPPED))
+    {
+        p_cb->state = NRF_DRV_STATE_INITIALIZED;
+        NRF_LOG_INFO("Disabled.\r\n");
+        ret_val = true;
+    }
+
+    NRF_LOG_INFO("%s returned %d.\r\n", (uint32_t)__func__, ret_val);
+    return ret_val;
+}
+
+
+static void irq_handler(NRF_PWM_Type * p_pwm, pwm_control_block_t * p_cb)
+{
+    ASSERT(p_cb->handler);
+
+    // The SEQEND0 and SEQEND1 events are only handled when the user asked for
+    // it (by setting proper flags when starting the playback).
+    if (nrf_pwm_int_enable_check(p_pwm, NRF_PWM_INT_SEQEND0_MASK) &&
+        nrf_pwm_event_check(p_pwm, NRF_PWM_EVENT_SEQEND0))
+    {
+        nrf_pwm_event_clear(p_pwm, NRF_PWM_EVENT_SEQEND0);
+        p_cb->handler(NRF_DRV_PWM_EVT_END_SEQ0);
+    }
+    if (nrf_pwm_int_enable_check(p_pwm, NRF_PWM_INT_SEQEND1_MASK) &&
+        nrf_pwm_event_check(p_pwm, NRF_PWM_EVENT_SEQEND1))
+    {
+        nrf_pwm_event_clear(p_pwm, NRF_PWM_EVENT_SEQEND1);
+        p_cb->handler(NRF_DRV_PWM_EVT_END_SEQ1);
+    }
+
+    // The LOOPSDONE event is handled by default, but this can be disabled.
+    if (nrf_pwm_int_enable_check(p_pwm, NRF_PWM_INT_LOOPSDONE_MASK) &&
+        nrf_pwm_event_check(p_pwm, NRF_PWM_EVENT_LOOPSDONE))
+    {
+        nrf_pwm_event_clear(p_pwm, NRF_PWM_EVENT_LOOPSDONE);
+        p_cb->handler(NRF_DRV_PWM_EVT_FINISHED);
+    }
+
+    if (nrf_pwm_event_check(p_pwm, NRF_PWM_EVENT_STOPPED))
+    {
+        nrf_pwm_event_clear(p_pwm, NRF_PWM_EVENT_STOPPED);
+
+        p_cb->state = NRF_DRV_STATE_INITIALIZED;
+
+        p_cb->handler(NRF_DRV_PWM_EVT_STOPPED);
+    }
+}
+
+
+#if NRF_MODULE_ENABLED(PWM0)
+void PWM0_IRQHandler(void)
+{
+    irq_handler(NRF_PWM0, &m_cb[PWM0_INSTANCE_INDEX]);
+}
+#endif
+
+#if NRF_MODULE_ENABLED(PWM1)
+void PWM1_IRQHandler(void)
+{
+    irq_handler(NRF_PWM1, &m_cb[PWM1_INSTANCE_INDEX]);
+}
+#endif
+
+#if NRF_MODULE_ENABLED(PWM2)
+void PWM2_IRQHandler(void)
+{
+    irq_handler(NRF_PWM2, &m_cb[PWM2_INSTANCE_INDEX]);
+}
+#endif
+
+#if PWM3_ENABLED
+void PWM3_IRQHandler(void)
+{
+    irq_handler(NRF_PWM3, &m_cb[PWM3_INSTANCE_INDEX]);
+}
+#endif
+#endif //ENABLED_PWM_COUNT
+#endif //NRF_MODULE_ENABLED(PWM)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/pwm/nrf_drv_pwm.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,477 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**@file
+ * @addtogroup nrf_pwm PWM HAL and driver
+ * @ingroup    nrf_drivers
+ * @brief      @tagAPI52 Pulse Width Modulation (PWM) module APIs.
+ *
+ * @defgroup   nrf_drv_pwm PWM driver
+ * @{
+ * @ingroup    nrf_pwm
+ * @brief      @tagAPI52 Pulse Width Modulation (PWM) module driver.
+ */
+
+
+#ifndef NRF_DRV_PWM_H__
+#define NRF_DRV_PWM_H__
+
+#include "nordic_common.h"
+#include "sdk_config.h"
+#include "nrf_pwm.h"
+#include "sdk_errors.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef PWM0_ENABLED
+#define PWM0_ENABLED 0
+#endif
+#ifndef PWM1_ENABLED
+#define PWM1_ENABLED 0
+#endif
+#ifndef PWM2_ENABLED
+#define PWM2_ENABLED 0
+#endif
+#ifndef PWM3_ENABLED
+#define PWM3_ENABLED 0
+#endif
+/**
+ * @brief PWM driver instance data structure.
+ */
+typedef struct
+{
+    NRF_PWM_Type * p_registers;  ///< Pointer to the structure with PWM peripheral instance registers.
+    uint8_t        drv_inst_idx; ///< Driver instance index.
+} nrf_drv_pwm_t;
+
+#define PWM0_INSTANCE_INDEX 0
+#define PWM1_INSTANCE_INDEX PWM0_INSTANCE_INDEX+PWM0_ENABLED
+#define PWM2_INSTANCE_INDEX PWM1_INSTANCE_INDEX+PWM1_ENABLED
+#define PWM3_INSTANCE_INDEX PWM2_INSTANCE_INDEX+PWM2_ENABLED
+
+/**
+ * @brief Macro for creating a PWM driver instance.
+ */
+#define NRF_DRV_PWM_INSTANCE(id)                        \
+{                                                       \
+    .p_registers  = CONCAT_2(NRF_PWM, id),              \
+    .drv_inst_idx = CONCAT_3(PWM, id, _INSTANCE_INDEX), \
+}
+
+
+/**
+ * @brief This value can be provided instead of a pin number for any channel
+ *        to specify that its output is not used and therefore does not need
+ *        to be connected to a pin.
+ */
+#define NRF_DRV_PWM_PIN_NOT_USED    0xFF
+
+/**
+ * @brief This value can be added to a pin number to inverse its polarity
+ *        (set idle state = 1).
+ */
+#define NRF_DRV_PWM_PIN_INVERTED    0x80
+
+/**
+ * @brief PWM driver configuration structure.
+ */
+typedef struct
+{
+    uint8_t output_pins[NRF_PWM_CHANNEL_COUNT]; ///< Pin numbers for individual output channels (optional).
+                                                /**< Use @ref NRF_DRV_PWM_PIN_NOT_USED
+                                                 *   if a given output channel is not needed. */
+    uint8_t            irq_priority; ///< Interrupt priority.
+    nrf_pwm_clk_t      base_clock;   ///< Base clock frequency.
+    nrf_pwm_mode_t     count_mode;   ///< Operating mode of the pulse generator counter.
+    uint16_t           top_value;    ///< Value up to which the pulse generator counter counts.
+    nrf_pwm_dec_load_t load_mode;    ///< Mode of loading sequence data from RAM.
+    nrf_pwm_dec_step_t step_mode;    ///< Mode of advancing the active sequence.
+} nrf_drv_pwm_config_t;
+
+/**
+ * @brief PWM driver default configuration.
+ */
+#define NRF_DRV_PWM_DEFAULT_CONFIG                                            \
+{                                                                             \
+    .output_pins  = {PWM_DEFAULT_CONFIG_OUT0_PIN,                             \
+                     PWM_DEFAULT_CONFIG_OUT1_PIN,                             \
+                     PWM_DEFAULT_CONFIG_OUT2_PIN,                             \
+                     PWM_DEFAULT_CONFIG_OUT3_PIN },                           \
+    .irq_priority = PWM_DEFAULT_CONFIG_IRQ_PRIORITY,                          \
+    .base_clock   = (nrf_pwm_clk_t)PWM_DEFAULT_CONFIG_BASE_CLOCK,             \
+    .count_mode   = (nrf_pwm_mode_t)PWM_DEFAULT_CONFIG_COUNT_MODE,            \
+    .top_value    = PWM_DEFAULT_CONFIG_TOP_VALUE,                             \
+    .load_mode    = (nrf_pwm_dec_load_t)PWM_DEFAULT_CONFIG_LOAD_MODE,         \
+    .step_mode    = (nrf_pwm_dec_step_t)PWM_DEFAULT_CONFIG_STEP_MODE,         \
+}
+
+
+/**
+ * @brief PWM flags providing additional playback options.
+ */
+typedef enum
+{
+    NRF_DRV_PWM_FLAG_STOP = 0x01, /**< When the requested playback is finished,
+                                       the peripheral should be stopped.
+                                       @note The STOP task is triggered when
+                                       the last value of the final sequence is
+                                       loaded from RAM, and the peripheral stops
+                                       at the end of the current PWM period.
+                                       For sequences with configured repeating
+                                       of duty cycle values, this might result in
+                                       less than the requested number of repeats
+                                       of the last value. */
+    NRF_DRV_PWM_FLAG_LOOP = 0x02, /**< When the requested playback is finished,
+                                       it should be started from the beginning.
+                                       This flag is ignored if used together
+                                       with @ref NRF_DRV_PWM_FLAG_STOP. */
+    NRF_DRV_PWM_FLAG_SIGNAL_END_SEQ0 = 0x04, /**< The event handler should be
+                                                  called when the last value
+                                                  from sequence 0 is loaded. */
+    NRF_DRV_PWM_FLAG_SIGNAL_END_SEQ1 = 0x08, /**< The event handler should be
+                                                  called when the last value
+                                                  from sequence 1 is loaded. */
+    NRF_DRV_PWM_FLAG_NO_EVT_FINISHED = 0x10, /**< The playback finished event
+                                                  (enabled by default) should be
+                                                  suppressed. */
+} nrf_drv_pwm_flag_t;
+
+
+/**
+ * @brief PWM driver event type.
+ */
+typedef enum
+{
+    NRF_DRV_PWM_EVT_FINISHED, ///< Sequence playback finished.
+    NRF_DRV_PWM_EVT_END_SEQ0, /**< End of sequence 0 reached. Its data can be
+                                   safely modified now. */
+    NRF_DRV_PWM_EVT_END_SEQ1, /**< End of sequence 1 reached. Its data can be
+                                   safely modified now. */
+    NRF_DRV_PWM_EVT_STOPPED,  ///< The PWM peripheral has been stopped.
+} nrf_drv_pwm_evt_type_t;
+
+/**
+ * @brief PWM driver event handler type.
+ */
+typedef void (* nrf_drv_pwm_handler_t)(nrf_drv_pwm_evt_type_t event_type);
+
+
+/**
+ * @brief Function for initializing the PWM driver.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_config   Pointer to the structure with initial configuration.
+ *                       If NULL, the default configuration is used.
+ * @param[in] handler    Event handler provided by the user. If NULL is passed
+ *                       instead, event notifications are not done and PWM
+ *                       interrupts are disabled.
+ *
+ * @retval NRF_SUCCESS             If initialization was successful.
+ * @retval NRF_ERROR_INVALID_STATE If the driver was already initialized.
+ */
+ret_code_t nrf_drv_pwm_init(nrf_drv_pwm_t const * const p_instance,
+                            nrf_drv_pwm_config_t const * p_config,
+                            nrf_drv_pwm_handler_t        handler);
+
+/**
+ * @brief Function for uninitializing the PWM driver.
+ *
+ * If any sequence playback is in progress, it is stopped immediately.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ */
+void nrf_drv_pwm_uninit(nrf_drv_pwm_t const * const p_instance);
+
+/**
+ * @brief Function for starting a single sequence playback.
+ *
+ * To take advantage of the looping mechanism in the PWM peripheral, both
+ * sequences must be used (single sequence can be played back only once by
+ * the peripheral). Therefore, the provided sequence is internally set and
+ * played back as both sequence 0 and sequence 1. Consequently, if end of
+ * sequence notifications are required, events for both sequences should be
+ * used (that means that both the @ref NRF_DRV_PWM_FLAG_SIGNAL_END_SEQ0 flag
+ * and the @ref NRF_DRV_PWM_FLAG_SIGNAL_END_SEQ1 flag should be specified and
+ * the @ref NRF_DRV_PWM_EVT_END_SEQ0 event and the @ref NRF_DRV_PWM_EVT_END_SEQ1
+ * event should be handled in the same way).
+ *
+ * @note The array containing the duty cycle values for the specified sequence
+ *       must be in RAM and cannot be allocated on stack.
+ *       For detailed information, see @ref nrf_pwm_sequence_t.
+ *
+ * @param[in] p_instance     Pointer to the driver instance structure.
+ * @param[in] p_sequence     Sequence to be played back.
+ * @param[in] playback_count Number of playbacks to be performed (must not be 0).
+ * @param[in] flags          Additional options. Pass any combination of
+ *                           @ref nrf_drv_pwm_flag_t "playback flags", or 0
+ *                           for default settings.
+ */
+void nrf_drv_pwm_simple_playback(nrf_drv_pwm_t const * const p_instance,
+                                 nrf_pwm_sequence_t const * p_sequence,
+                                 uint16_t                   playback_count,
+                                 uint32_t                   flags);
+
+/**
+ * @brief Function for starting a two-sequence playback.
+ *
+ * @note The array containing the duty cycle values for the specified sequence
+ *       must be in RAM and cannot be allocated on stack.
+ *       For detailed information, see @ref nrf_pwm_sequence_t.
+ *
+ * @param[in] p_instance     Pointer to the driver instance structure.
+ * @param[in] p_sequence_0   First sequence to be played back.
+ * @param[in] p_sequence_1   Second sequence to be played back.
+ * @param[in] playback_count Number of playbacks to be performed (must not be 0).
+ * @param[in] flags          Additional options. Pass any combination of
+ *                           @ref nrf_drv_pwm_flag_t "playback flags", or 0
+ *                           for default settings.
+ */
+void nrf_drv_pwm_complex_playback(nrf_drv_pwm_t const * const p_instance,
+                                  nrf_pwm_sequence_t const * p_sequence_0,
+                                  nrf_pwm_sequence_t const * p_sequence_1,
+                                  uint16_t                   playback_count,
+                                  uint32_t                   flags);
+
+/**
+ * @brief Function for advancing the active sequence.
+ *
+ * This function only applies to @ref NRF_PWM_STEP_TRIGGERED mode.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ */
+__STATIC_INLINE void nrf_drv_pwm_step(nrf_drv_pwm_t const * const p_instance);
+
+/**
+ * @brief Function for stopping the sequence playback.
+ *
+ * The playback is stopped at the end of the current PWM period.
+ * This means that if the active sequence is configured to repeat each duty
+ * cycle value for a certain number of PWM periods, the last played value
+ * might appear on the output less times than requested.
+ *
+ * @note This function can be instructed to wait until the playback is stopped
+ *       (by setting @p wait_until_stopped to true). Note that, depending on
+ *       the length of the PMW period, this might take a significant amount of
+ *       time. Alternatively, the @ref nrf_drv_pwm_is_stopped function can be
+ *       used to poll the status, or the @ref NRF_DRV_PWM_EVT_STOPPED event can
+ *       be used to get the notification when the playback is stopped, provided
+ *       the event handler is defined.
+ *
+ * @param[in] p_instance         Pointer to the driver instance structure.
+ * @param[in] wait_until_stopped If true, the function will not return until
+ *                               the playback is stopped.
+ *
+ * @retval true  If the PWM peripheral is stopped.
+ * @retval false If the PWM peripheral is not stopped.
+ */
+bool nrf_drv_pwm_stop(nrf_drv_pwm_t const * const p_instance,
+                      bool wait_until_stopped);
+
+/**
+ * @brief Function for checking the status of the PWM peripheral.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ *
+ * @retval true  If the PWM peripheral is stopped.
+ * @retval false If the PWM peripheral is not stopped.
+ */
+bool nrf_drv_pwm_is_stopped(nrf_drv_pwm_t const * const p_instance);
+
+/**
+ * @brief Function for updating the sequence data during playback.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] seq_id     Identifier of the sequence (0 or 1).
+ * @param[in] p_sequence Pointer to the new sequence definition.
+ */
+__STATIC_INLINE void nrf_drv_pwm_sequence_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t                    seq_id,
+                                        nrf_pwm_sequence_t const * p_sequence);
+
+/**
+ * @brief Function for updating the pointer to the duty cycle values
+ *        in the specified sequence during playback.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] seq_id     Identifier of the sequence (0 or 1).
+ * @param[in] values     New pointer to the duty cycle values.
+ */
+__STATIC_INLINE void nrf_drv_pwm_sequence_values_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t          seq_id,
+                                        nrf_pwm_values_t values);
+
+/**
+ * @brief Function for updating the number of duty cycle values
+ *        in the specified sequence during playback.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] seq_id     Identifier of the sequence (0 or 1).
+ * @param[in] length     New number of the duty cycle values.
+ */
+__STATIC_INLINE void nrf_drv_pwm_sequence_length_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t  seq_id,
+                                        uint16_t length);
+
+/**
+ * @brief Function for updating the number of repeats for duty cycle values
+ *        in specified sequence during playback.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] seq_id     Identifier of the sequence (0 or 1).
+ * @param[in] repeats    New number of repeats.
+ */
+__STATIC_INLINE void nrf_drv_pwm_sequence_repeats_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t  seq_id,
+                                        uint32_t repeats);
+
+/**
+ * @brief Function for updating the additional delay after the specified
+ *        sequence during playback.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] seq_id     Identifier of the sequence (0 or 1).
+ * @param[in] end_delay  New end delay value (in PWM periods).
+ */
+__STATIC_INLINE void nrf_drv_pwm_sequence_end_delay_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t  seq_id,
+                                        uint32_t end_delay);
+
+/**
+ * @brief Function for returning the address of a specified PWM task that can
+ *        be used in PPI module.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] task       Requested task.
+ *
+ * @return Task address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_pwm_task_address_get(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        nrf_pwm_task_t task);
+
+/**@brief Function for returning the address of a specified PWM event that can
+ *        be used in PPI module.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] event      Requested event.
+ *
+ * @return Event address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_pwm_event_address_get(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        nrf_pwm_event_t event);
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_drv_pwm_step(nrf_drv_pwm_t const * const p_instance)
+{
+    nrf_pwm_task_trigger(p_instance->p_registers, NRF_PWM_TASK_NEXTSTEP);
+}
+
+__STATIC_INLINE void nrf_drv_pwm_sequence_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t                    seq_id,
+                                        nrf_pwm_sequence_t const * p_sequence)
+{
+    nrf_pwm_sequence_set(p_instance->p_registers, seq_id, p_sequence);
+}
+
+__STATIC_INLINE void nrf_drv_pwm_sequence_values_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t          seq_id,
+                                        nrf_pwm_values_t values)
+{
+    nrf_pwm_seq_ptr_set(p_instance->p_registers, seq_id, values.p_raw);
+}
+
+__STATIC_INLINE void nrf_drv_pwm_sequence_length_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t  seq_id,
+                                        uint16_t length)
+{
+    nrf_pwm_seq_cnt_set(p_instance->p_registers, seq_id, length);
+}
+
+__STATIC_INLINE void nrf_drv_pwm_sequence_repeats_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t  seq_id,
+                                        uint32_t repeats)
+{
+    nrf_pwm_seq_refresh_set(p_instance->p_registers, seq_id, repeats);
+}
+
+__STATIC_INLINE void nrf_drv_pwm_sequence_end_delay_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t  seq_id,
+                                        uint32_t end_delay)
+{
+    nrf_pwm_seq_end_delay_set(p_instance->p_registers, seq_id, end_delay);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_pwm_task_address_get(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        nrf_pwm_task_t task)
+{
+    return nrf_pwm_task_address_get(p_instance->p_registers, task);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_pwm_event_address_get(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        nrf_pwm_event_t event)
+{
+    return nrf_pwm_event_address_get(p_instance->p_registers, event);
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_DRV_PWM_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/qdec/nrf_drv_qdec.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,233 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(QDEC)
+#include <stdint.h>
+#include <stddef.h>
+
+#include "nrf.h"
+#include "nrf_gpio.h"
+#include "nrf_error.h"
+#include "nrf_assert.h"
+#include "nrf_drv_common.h"
+#include "nrf_drv_qdec.h"
+#include "app_util_platform.h"
+#include "nrf_assert.h"
+
+#define NRF_LOG_MODULE_NAME "QDEC"
+
+#if QDEC_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       QDEC_CONFIG_LOG_LEVEL
+#define NRF_LOG_INFO_COLOR  QDEC_CONFIG_INFO_COLOR
+#define NRF_LOG_DEBUG_COLOR QDEC_CONFIG_DEBUG_COLOR
+#define EVT_TO_STR(event)   (event == NRF_QDEC_EVENT_SAMPLERDY ? "NRF_QDEC_EVENT_SAMPLERDY" :        \
+                            (event == NRF_QDEC_EVENT_REPORTRDY ? "NRF_QDEC_EVENT_REPORTRDY" :        \
+                            (event == NRF_QDEC_EVENT_ACCOF ? "NRF_QDEC_EVENT_ACCOF" : "UNKNOWN EVENT")))
+#else //QDEC_CONFIG_LOG_ENABLED
+#define EVT_TO_STR(event)   ""
+#define NRF_LOG_LEVEL       0
+#endif //QDEC_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+
+
+static qdec_event_handler_t m_qdec_event_handler = NULL;
+static const nrf_drv_qdec_config_t m_default_config = NRF_DRV_QDEC_DEFAULT_CONFIG;
+static nrf_drv_state_t m_state = NRF_DRV_STATE_UNINITIALIZED;
+
+void QDEC_IRQHandler(void)
+{
+    nrf_drv_qdec_event_t event;
+    if ( nrf_qdec_event_check(NRF_QDEC_EVENT_SAMPLERDY) &&
+         nrf_qdec_int_enable_check(NRF_QDEC_INT_SAMPLERDY_MASK) )
+    {
+        nrf_qdec_event_clear(NRF_QDEC_EVENT_SAMPLERDY); 
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_QDEC_EVENT_SAMPLERDY));
+
+        event.type = NRF_QDEC_EVENT_SAMPLERDY;
+        event.data.sample.value = (int8_t)nrf_qdec_sample_get();
+        m_qdec_event_handler(event);
+    }
+
+    if ( nrf_qdec_event_check(NRF_QDEC_EVENT_REPORTRDY) &&
+         nrf_qdec_int_enable_check(NRF_QDEC_INT_REPORTRDY_MASK) )
+    {
+        nrf_qdec_event_clear(NRF_QDEC_EVENT_REPORTRDY);
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_QDEC_INT_REPORTRDY_MASK));
+
+        event.type = NRF_QDEC_EVENT_REPORTRDY;
+
+        event.data.report.acc    = (int16_t)nrf_qdec_accread_get();
+        event.data.report.accdbl = (uint16_t)nrf_qdec_accdblread_get();
+        m_qdec_event_handler(event);
+    }
+
+    if ( nrf_qdec_event_check(NRF_QDEC_EVENT_ACCOF) &&
+         nrf_qdec_int_enable_check(NRF_QDEC_INT_ACCOF_MASK) )
+    {
+        nrf_qdec_event_clear(NRF_QDEC_EVENT_ACCOF);
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_QDEC_EVENT_ACCOF));
+
+        event.type = NRF_QDEC_EVENT_ACCOF;
+        m_qdec_event_handler(event);
+    }
+}
+
+
+ret_code_t nrf_drv_qdec_init(const nrf_drv_qdec_config_t * p_config,
+                             qdec_event_handler_t event_handler)
+{
+    ret_code_t err_code;
+
+    if (m_state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    if (p_config == NULL)
+    {
+        p_config = &m_default_config;
+    }
+
+    if (event_handler)
+    {
+        m_qdec_event_handler = event_handler;
+    }
+    else
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    nrf_qdec_sampleper_set(p_config->sampleper);
+    nrf_gpio_cfg_input(p_config->pselled, NRF_GPIO_PIN_NOPULL);
+    nrf_gpio_cfg_input(p_config->psela, NRF_GPIO_PIN_NOPULL);
+    nrf_gpio_cfg_input(p_config->pselb, NRF_GPIO_PIN_NOPULL);
+    nrf_qdec_pio_assign( p_config->psela, p_config->pselb, p_config->pselled);
+    nrf_qdec_ledpre_set(p_config->ledpre);
+    nrf_qdec_ledpol_set(p_config->ledpol);
+    nrf_qdec_shorts_enable(NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK);
+
+    if (p_config->dbfen)
+    {
+        nrf_qdec_dbfen_enable();
+    }
+    else
+    {
+        nrf_qdec_dbfen_disable();
+    }
+
+    uint32_t int_mask = NRF_QDEC_INT_ACCOF_MASK;
+
+    if (p_config->reportper != NRF_QDEC_REPORTPER_DISABLED)
+    {
+        nrf_qdec_reportper_set(p_config->reportper);
+        int_mask |= NRF_QDEC_INT_REPORTRDY_MASK;
+    }
+
+    if (p_config->sample_inten)
+    {
+        int_mask |= NRF_QDEC_INT_SAMPLERDY_MASK;
+    }
+
+    nrf_qdec_int_enable(int_mask);
+    nrf_drv_common_irq_enable(QDEC_IRQn, p_config->interrupt_priority);
+
+    m_state = NRF_DRV_STATE_INITIALIZED;
+
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+void nrf_drv_qdec_uninit(void)
+{
+    ASSERT(m_state != NRF_DRV_STATE_UNINITIALIZED);
+    nrf_drv_qdec_disable();
+    nrf_drv_common_irq_disable(QDEC_IRQn);
+    m_state = NRF_DRV_STATE_UNINITIALIZED;
+    NRF_LOG_INFO("Uninitialized.\r\n");
+}
+
+void nrf_drv_qdec_enable(void)
+{
+    ASSERT(m_state == NRF_DRV_STATE_INITIALIZED);
+    nrf_qdec_enable();
+    nrf_qdec_task_trigger(NRF_QDEC_TASK_START);
+    m_state = NRF_DRV_STATE_POWERED_ON;
+    NRF_LOG_INFO("Enabled.\r\n");
+}
+
+void nrf_drv_qdec_disable(void)
+{
+    ASSERT(m_state == NRF_DRV_STATE_POWERED_ON);
+    nrf_qdec_task_trigger(NRF_QDEC_TASK_STOP);
+    nrf_qdec_disable();
+    m_state = NRF_DRV_STATE_INITIALIZED;
+    NRF_LOG_INFO("Disabled.\r\n");
+}
+
+void nrf_drv_qdec_accumulators_read(int16_t * p_acc, int16_t * p_accdbl)
+{
+    ASSERT(m_state == NRF_DRV_STATE_POWERED_ON);
+    nrf_qdec_task_trigger(NRF_QDEC_TASK_READCLRACC);
+
+    *p_acc    = (int16_t)nrf_qdec_accread_get();
+    *p_accdbl = (int16_t)nrf_qdec_accdblread_get();
+
+    NRF_LOG_DEBUG("Accumulators data, ACC register:\r\n");
+    NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_acc, sizeof(p_acc));
+    NRF_LOG_DEBUG("Accumulators data, ACCDBL register:\r\n");
+    NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_accdbl, sizeof(p_accdbl));
+}
+
+void nrf_drv_qdec_task_address_get(nrf_qdec_task_t task, uint32_t * p_task)
+{
+    *p_task = (uint32_t)nrf_qdec_task_address_get(task);
+}
+
+void nrf_drv_qdec_event_address_get(nrf_qdec_event_t event, uint32_t * p_event)
+{
+    *p_event = (uint32_t)nrf_qdec_event_address_get(event);
+}
+
+#endif //NRF_MODULE_ENABLED(QDEC)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/qdec/nrf_drv_qdec.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,184 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_DRV_QDEC_H__
+#define NRF_DRV_QDEC_H__
+
+#include "nrf_qdec.h"
+#include "sdk_config.h"
+#include "sdk_errors.h"
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @addtogroup nrf_qdec QDEC HAL and driver
+ * @ingroup nrf_drivers
+ * @brief Quadrature decoder (QDEC) APIs.
+ * @details The QDEC HAL provides basic APIs for accessing the registers of the QDEC.
+ * The QDEC driver provides APIs on a higher level.
+ *
+ * @defgroup nrf_drv_qdec QDEC driver
+ * @{
+ * @ingroup nrf_qdec
+ * @brief Quadrature decoder (QDEC) driver.
+ */
+
+/**@brief QDEC configuration structure.*/
+typedef struct
+{
+    nrf_qdec_reportper_t   reportper;          /**< Report period in samples. */
+    nrf_qdec_sampleper_t   sampleper;          /**< Sampling period in microseconds. */
+    uint32_t               psela;              /**< Pin number for A input. */
+    uint32_t               pselb;              /**< Pin number for B input. */
+    uint32_t               pselled;            /**< Pin number for LED output. */
+    uint32_t               ledpre;             /**< Time (in microseconds) how long LED is switched on before sampling. */
+    nrf_qdec_ledpol_t      ledpol;             /**< Active LED polarity. */
+    bool                   dbfen;              /**< State of debouncing filter. */
+    bool                   sample_inten;       /**< Enabling sample ready interrupt. */
+    uint8_t                interrupt_priority; /**< QDEC interrupt priority. */
+} nrf_drv_qdec_config_t;
+
+/**@brief QDEC default configuration. */
+#define NRF_DRV_QDEC_DEFAULT_CONFIG                                         \
+    {                                                                       \
+        .reportper          = (nrf_qdec_reportper_t)QDEC_CONFIG_REPORTPER,  \
+        .sampleper          = (nrf_qdec_sampleper_t)QDEC_CONFIG_SAMPLEPER,  \
+        .psela              = QDEC_CONFIG_PIO_A,                            \
+        .pselb              = QDEC_CONFIG_PIO_B,                            \
+        .pselled            = QDEC_CONFIG_PIO_LED,                          \
+        .ledpre             = QDEC_CONFIG_LEDPRE,                           \
+        .ledpol             = (nrf_qdec_ledpol_t)QDEC_CONFIG_LEDPOL,        \
+        .interrupt_priority = QDEC_CONFIG_IRQ_PRIORITY,                     \
+        .dbfen              = QDEC_CONFIG_DBFEN,                            \
+        .sample_inten       = QDEC_CONFIG_SAMPLE_INTEN                      \
+    }
+
+/**@brief QDEC sample event data.*/
+typedef struct
+{
+    int8_t value; /**< Sample value. */
+} nrf_drv_qdec_sample_data_evt_t;
+
+/**@brief QDEC report event data.*/
+typedef struct
+{
+    int16_t acc;     /**< Accumulated transitions. */
+    uint16_t accdbl;  /**< Accumulated double transitions. */
+} nrf_drv_qdec_report_data_evt_t;
+
+/**@brief QDEC event handler structure. */
+typedef struct
+{
+    nrf_qdec_event_t  type;
+    union
+    {
+        nrf_drv_qdec_sample_data_evt_t sample; /**< Sample event data. */
+        nrf_drv_qdec_report_data_evt_t report; /**< Report event data. */
+    } data;
+} nrf_drv_qdec_event_t;
+
+/**@brief QDEC event handler.
+ * @param[in] event  QDEC event structure.
+ */
+typedef void (*qdec_event_handler_t)(nrf_drv_qdec_event_t event);
+
+/**@brief Function for initializing QDEC.
+ *
+ * @param[in] p_config            Pointer to configuration parameters.
+ * @param[in] event_handler  Event handler function.
+ *
+ * @retval NRF_SUCCESS If initialization was successful.
+ * @retval NRF_ERROR_INVALID_PARAM If invalid parameters were supplied.
+ * @retval NRF_ERROR_INVALID_STATE If QDEC was already initialized.
+ */
+ret_code_t nrf_drv_qdec_init(nrf_drv_qdec_config_t const * p_config,
+                             qdec_event_handler_t event_handler);
+
+/**@brief Function for uninitializing QDEC.
+ * @note  Function asserts if module is uninitialized.
+ */
+void nrf_drv_qdec_uninit(void);
+
+/**@brief Function for enabling QDEC.
+ * @note  Function asserts if module is uninitialized or enabled.
+ */
+void nrf_drv_qdec_enable(void);
+
+/**@brief Function for disabling QDEC.
+ * @note  Function asserts if module is uninitialized or disabled.
+ */
+void nrf_drv_qdec_disable(void);
+
+/**@brief Function for reading accumulated transitions QDEC.
+ * @note  Function asserts if module is not enabled.
+ * @note  Accumulators are cleared after reading.
+ *
+ * @param[out] p_acc      Pointer to store accumulated transitions.
+ * @param[out] p_accdbl   Pointer to store accumulated double transitions.
+ */
+void nrf_drv_qdec_accumulators_read(int16_t * p_acc, int16_t * p_accdbl);
+
+/**
+ * @brief Function for returning the address of a specific timer task.
+ *
+ * @param[in]  task       QDEC task.
+ * @param[out] p_task     Task address.
+ */
+void nrf_drv_qdec_task_address_get(nrf_qdec_task_t task, uint32_t * p_task);
+
+/**
+ * @brief Function for returning the address of a specific timer event.
+ *
+ * @param[in]  event       QDEC event.
+ * @param[out] p_event     Event address.
+ */
+void nrf_drv_qdec_event_address_get(nrf_qdec_event_t event, uint32_t * p_event);
+
+/**
+   *@}
+ **/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF_DRV_QDEC_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/radio_config/radio_config.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,186 @@
+/* 
+ * Copyright (c) 2009 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+/** @file
+* @addtogroup nrf_dev_radio_rx_example_main nrf_dev_radio_tx_example_main
+* @{
+*/
+
+#include "radio_config.h"
+#include "nrf_delay.h"
+
+/* These are set to zero as ShockBurst packets don't have corresponding fields. */
+#define PACKET_S1_FIELD_SIZE      (0UL)  /**< Packet S1 field size in bits. */
+#define PACKET_S0_FIELD_SIZE      (0UL)  /**< Packet S0 field size in bits. */
+#define PACKET_LENGTH_FIELD_SIZE  (0UL)  /**< Packet length field size in bits. */
+
+/**
+ * @brief Function for swapping/mirroring bits in a byte.
+ *
+ *@verbatim
+ * output_bit_7 = input_bit_0
+ * output_bit_6 = input_bit_1
+ *           :
+ * output_bit_0 = input_bit_7
+ *@endverbatim
+ *
+ * @param[in] inp is the input byte to be swapped.
+ *
+ * @return
+ * Returns the swapped/mirrored input byte.
+ */
+static uint32_t swap_bits(uint32_t inp);
+
+/**
+ * @brief Function for swapping bits in a 32 bit word for each byte individually.
+ *
+ * The bits are swapped as follows:
+ * @verbatim
+ * output[31:24] = input[24:31]
+ * output[23:16] = input[16:23]
+ * output[15:8]  = input[8:15]
+ * output[7:0]   = input[0:7]
+ * @endverbatim
+ * @param[in] input is the input word to be swapped.
+ *
+ * @return
+ * Returns the swapped input byte.
+ */
+static uint32_t bytewise_bitswap(uint32_t inp);
+
+static uint32_t swap_bits(uint32_t inp)
+{
+    uint32_t i;
+    uint32_t retval = 0;
+
+    inp = (inp & 0x000000FFUL);
+
+    for (i = 0; i < 8; i++)
+    {
+        retval |= ((inp >> i) & 0x01) << (7 - i);
+    }
+
+    return retval;
+}
+
+
+static uint32_t bytewise_bitswap(uint32_t inp)
+{
+      return (swap_bits(inp >> 24) << 24)
+           | (swap_bits(inp >> 16) << 16)
+           | (swap_bits(inp >> 8) << 8)
+           | (swap_bits(inp));
+}
+
+
+/**
+ * @brief Function for configuring the radio to operate in ShockBurst compatible mode.
+ *
+ * To configure the application running on nRF24L series devices:
+ *
+ * @verbatim
+ * uint8_t tx_address[5] = { 0xC0, 0x01, 0x23, 0x45, 0x67 };
+ * hal_nrf_set_rf_channel(7);
+ * hal_nrf_set_address_width(HAL_NRF_AW_5BYTES);
+ * hal_nrf_set_address(HAL_NRF_TX, tx_address);
+ * hal_nrf_set_address(HAL_NRF_PIPE0, tx_address);
+ * hal_nrf_open_pipe(0, false);
+ * hal_nrf_set_datarate(HAL_NRF_1MBPS);
+ * hal_nrf_set_crc_mode(HAL_NRF_CRC_16BIT);
+ * hal_nrf_setup_dynamic_payload(0xFF);
+ * hal_nrf_enable_dynamic_payload(false);
+ * @endverbatim
+ *
+ * When transmitting packets with hal_nrf_write_tx_payload(const uint8_t *tx_pload, uint8_t length),
+ * match the length with PACKET_STATIC_LENGTH.
+ * hal_nrf_write_tx_payload(payload, PACKET_STATIC_LENGTH);
+ *
+*/
+void radio_configure()
+{
+    // Radio config
+    NRF_RADIO->TXPOWER   = (RADIO_TXPOWER_TXPOWER_0dBm << RADIO_TXPOWER_TXPOWER_Pos);
+    NRF_RADIO->FREQUENCY = 7UL;  // Frequency bin 7, 2407MHz
+    NRF_RADIO->MODE      = (RADIO_MODE_MODE_Nrf_1Mbit << RADIO_MODE_MODE_Pos);
+
+    // Radio address config
+    NRF_RADIO->PREFIX0 =
+        ((uint32_t)swap_bits(0xC3) << 24) // Prefix byte of address 3 converted to nRF24L series format
+      | ((uint32_t)swap_bits(0xC2) << 16) // Prefix byte of address 2 converted to nRF24L series format
+      | ((uint32_t)swap_bits(0xC1) << 8)  // Prefix byte of address 1 converted to nRF24L series format
+      | ((uint32_t)swap_bits(0xC0) << 0); // Prefix byte of address 0 converted to nRF24L series format
+
+    NRF_RADIO->PREFIX1 =
+        ((uint32_t)swap_bits(0xC7) << 24) // Prefix byte of address 7 converted to nRF24L series format
+      | ((uint32_t)swap_bits(0xC6) << 16) // Prefix byte of address 6 converted to nRF24L series format
+      | ((uint32_t)swap_bits(0xC4) << 0); // Prefix byte of address 4 converted to nRF24L series format
+
+    NRF_RADIO->BASE0 = bytewise_bitswap(0x01234567UL);  // Base address for prefix 0 converted to nRF24L series format
+    NRF_RADIO->BASE1 = bytewise_bitswap(0x89ABCDEFUL);  // Base address for prefix 1-7 converted to nRF24L series format
+
+    NRF_RADIO->TXADDRESS   = 0x00UL;  // Set device address 0 to use when transmitting
+    NRF_RADIO->RXADDRESSES = 0x01UL;  // Enable device address 0 to use to select which addresses to receive
+
+    // Packet configuration
+    NRF_RADIO->PCNF0 = (PACKET_S1_FIELD_SIZE     << RADIO_PCNF0_S1LEN_Pos) |
+                       (PACKET_S0_FIELD_SIZE     << RADIO_PCNF0_S0LEN_Pos) |
+                       (PACKET_LENGTH_FIELD_SIZE << RADIO_PCNF0_LFLEN_Pos); //lint !e845 "The right argument to operator '|' is certain to be 0"
+
+    // Packet configuration
+    NRF_RADIO->PCNF1 = (RADIO_PCNF1_WHITEEN_Disabled << RADIO_PCNF1_WHITEEN_Pos) |
+                       (RADIO_PCNF1_ENDIAN_Big       << RADIO_PCNF1_ENDIAN_Pos)  |
+                       (PACKET_BASE_ADDRESS_LENGTH   << RADIO_PCNF1_BALEN_Pos)   |
+                       (PACKET_STATIC_LENGTH         << RADIO_PCNF1_STATLEN_Pos) |
+                       (PACKET_PAYLOAD_MAXSIZE       << RADIO_PCNF1_MAXLEN_Pos); //lint !e845 "The right argument to operator '|' is certain to be 0"
+
+    // CRC Config
+    NRF_RADIO->CRCCNF = (RADIO_CRCCNF_LEN_Two << RADIO_CRCCNF_LEN_Pos); // Number of checksum bits
+    if ((NRF_RADIO->CRCCNF & RADIO_CRCCNF_LEN_Msk) == (RADIO_CRCCNF_LEN_Two << RADIO_CRCCNF_LEN_Pos))
+    {
+        NRF_RADIO->CRCINIT = 0xFFFFUL;   // Initial value
+        NRF_RADIO->CRCPOLY = 0x11021UL;  // CRC poly: x^16 + x^12^x^5 + 1
+    }
+    else if ((NRF_RADIO->CRCCNF & RADIO_CRCCNF_LEN_Msk) == (RADIO_CRCCNF_LEN_One << RADIO_CRCCNF_LEN_Pos))
+    {
+        NRF_RADIO->CRCINIT = 0xFFUL;   // Initial value
+        NRF_RADIO->CRCPOLY = 0x107UL;  // CRC poly: x^8 + x^2^x^1 + 1
+    }
+}
+
+/**
+ * @}
+ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/radio_config/radio_config.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,56 @@
+/* 
+ * Copyright (c) 2009 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef RADIO_CONFIG_H
+#define RADIO_CONFIG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PACKET_BASE_ADDRESS_LENGTH  (4UL)                   //!< Packet base address length field size in bytes
+#define PACKET_STATIC_LENGTH        (1UL)                   //!< Packet static length in bytes
+#define PACKET_PAYLOAD_MAXSIZE      (PACKET_STATIC_LENGTH)  //!< Packet payload maximum size in bytes
+
+void radio_configure(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/rng/nrf_drv_rng.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,295 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(RNG)
+
+#include <stdint.h>
+#include <stddef.h>
+#include "nrf_drv_rng.h"
+#include "nrf_drv_common.h"
+#include "nordic_common.h"
+#include "nrf_assert.h"
+#include "nrf_queue.h"
+
+#ifdef SOFTDEVICE_PRESENT
+    #include "softdevice_handler.h"
+    #include "nrf_soc.h"
+    #include "app_util_platform.h"
+#endif // SOFTDEVICE_PRESENT
+
+#define NRF_LOG_MODULE_NAME "RNG"
+
+#if RNG_CONFIG_LOG_ENABLED
+    #define NRF_LOG_LEVEL       RNG_CONFIG_LOG_LEVEL
+    #define NRF_LOG_INFO_COLOR  RNG_CONFIG_INFO_COLOR
+    #define NRF_LOG_DEBUG_COLOR RNG_CONFIG_DEBUG_COLOR
+#else //RNG_CONFIG_LOG_ENABLED
+    #define NRF_LOG_LEVEL       0
+#endif //RNG_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+
+/* Validate configuration */
+INTERRUPT_PRIORITY_VALIDATION(RNG_CONFIG_IRQ_PRIORITY);
+
+typedef struct
+{
+    nrf_drv_state_t      state;
+    nrf_drv_rng_config_t config;
+} nrf_drv_rng_cb_t;
+
+static nrf_drv_rng_cb_t m_rng_cb;
+NRF_QUEUE_DEF(uint8_t, m_rand_pool, RNG_CONFIG_POOL_SIZE, NRF_QUEUE_MODE_OVERFLOW);
+static const nrf_drv_rng_config_t m_default_config = NRF_DRV_RNG_DEFAULT_CONFIG;
+
+#ifdef SOFTDEVICE_PRESENT
+    #define SD_RAND_POOL_SIZE           (32)
+    STATIC_ASSERT(RNG_CONFIG_POOL_SIZE == SD_RAND_POOL_SIZE);
+
+    #define NRF_DRV_RNG_LOCK()          CRITICAL_REGION_ENTER()
+    #define NRF_DRV_RNG_RELEASE()       CRITICAL_REGION_EXIT()
+    #define NRF_DRV_RNG_SD_IS_ENABLED() softdevice_handler_is_enabled()
+#else
+    #define NRF_DRV_RNG_LOCK()          do { } while (0)
+    #define NRF_DRV_RNG_RELEASE()       do { } while (0)
+    #define NRF_DRV_RNG_SD_IS_ENABLED() false
+#endif // SOFTDEVICE_PRESENT
+
+/**
+ * @brief Function for starting generation.
+ */
+static void nrf_drv_rng_start(void)
+{
+    ASSERT(!NRF_DRV_RNG_SD_IS_ENABLED());
+
+    nrf_rng_event_clear(NRF_RNG_EVENT_VALRDY);
+    nrf_rng_int_enable(NRF_RNG_INT_VALRDY_MASK);
+    nrf_rng_task_trigger(NRF_RNG_TASK_START);
+}
+
+/**
+ * @brief Function for stoping generation.
+ */
+static void nrf_drv_rng_stop(void)
+{
+    ASSERT(!NRF_DRV_RNG_SD_IS_ENABLED());
+
+    nrf_rng_int_disable(NRF_RNG_INT_VALRDY_MASK);
+    nrf_rng_task_trigger(NRF_RNG_TASK_STOP);
+}
+
+/**
+ * @brief Function for setting up RNG hardware.
+ */
+static void nrf_drv_rng_setup(void)
+{
+    ASSERT(!NRF_DRV_RNG_SD_IS_ENABLED());
+
+    if (m_rng_cb.config.error_correction)
+    {
+        nrf_rng_error_correction_enable();
+    }
+    nrf_rng_shorts_disable(NRF_RNG_SHORT_VALRDY_STOP_MASK);
+    nrf_drv_common_irq_enable(RNG_IRQn, m_rng_cb.config.interrupt_priority);
+}
+
+ret_code_t nrf_drv_rng_init(nrf_drv_rng_config_t const * p_config)
+{
+    if (m_rng_cb.state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        return NRF_ERROR_MODULE_ALREADY_INITIALIZED;
+    }
+
+    if (p_config == NULL)
+    {
+        p_config = &m_default_config;
+    }
+    m_rng_cb.config = *p_config;
+
+    NRF_DRV_RNG_LOCK();
+
+    if (!NRF_DRV_RNG_SD_IS_ENABLED())
+    {
+        nrf_drv_rng_setup();
+        nrf_drv_rng_start();
+    }
+
+    NRF_DRV_RNG_RELEASE();
+
+    m_rng_cb.state = NRF_DRV_STATE_INITIALIZED;
+
+    return NRF_SUCCESS;
+}
+
+void nrf_drv_rng_uninit(void)
+{
+    ASSERT(m_rng_cb.state == NRF_DRV_STATE_INITIALIZED);
+
+    NRF_DRV_RNG_LOCK();
+
+    if (!NRF_DRV_RNG_SD_IS_ENABLED())
+    {
+        nrf_drv_rng_stop();
+        nrf_drv_common_irq_disable(RNG_IRQn);
+    }
+
+    NRF_DRV_RNG_RELEASE();
+
+    nrf_queue_reset(&m_rand_pool);
+    m_rng_cb.state = NRF_DRV_STATE_UNINITIALIZED;
+    NRF_LOG_INFO("Uninitialized.\r\n");
+}
+
+void nrf_drv_rng_bytes_available(uint8_t * p_bytes_available)
+{
+    ASSERT(m_rng_cb.state == NRF_DRV_STATE_INITIALIZED);
+
+#ifdef SOFTDEVICE_PRESENT
+    if (NRF_DRV_RNG_SD_IS_ENABLED())
+    {
+        if (NRF_SUCCESS == sd_rand_application_bytes_available_get(p_bytes_available))
+        {
+            return;
+        }
+    }
+#endif // SOFTDEVICE_PRESENT
+
+    *p_bytes_available  = nrf_queue_utilization_get(&m_rand_pool);
+
+    NRF_LOG_INFO("Function: %s, available bytes: %d.\r\n", (uint32_t)__func__, *p_bytes_available);
+}
+
+ret_code_t nrf_drv_rng_rand(uint8_t * p_buff, uint8_t length)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+    ASSERT(m_rng_cb.state == NRF_DRV_STATE_INITIALIZED);
+
+#ifdef SOFTDEVICE_PRESENT
+    do {
+        bool sd_is_enabled;
+        NRF_DRV_RNG_LOCK();
+        sd_is_enabled = NRF_DRV_RNG_SD_IS_ENABLED();
+        if (!sd_is_enabled)
+#endif // SOFTDEVICE_PRESENT
+        {
+            err_code = nrf_queue_read(&m_rand_pool, p_buff, (uint32_t)length);
+            nrf_drv_rng_start();
+        }
+#ifdef SOFTDEVICE_PRESENT
+        NRF_DRV_RNG_RELEASE();
+
+        if (sd_is_enabled)
+        {
+            err_code = sd_rand_application_vector_get(p_buff, length);
+            if (err_code == NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES)
+            {
+                err_code = NRF_ERROR_NOT_FOUND;
+            }
+        }
+    } while (err_code == NRF_ERROR_SOFTDEVICE_NOT_ENABLED);
+#endif // SOFTDEVICE_PRESENT
+    ASSERT((err_code == NRF_SUCCESS) || (err_code == NRF_ERROR_NOT_FOUND));
+
+    NRF_LOG_DEBUG("Rand buffer data:\r\n");
+    NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_buff, length);
+    NRF_LOG_WARNING("Function: %s, error code: %s.\r\n",
+                    (uint32_t)__func__,
+                    (uint32_t)ERR_TO_STR(err_code));
+
+    return err_code;
+}
+
+void nrf_drv_rng_block_rand(uint8_t * p_buff, uint32_t length)
+{
+    ASSERT(m_rng_cb.state == NRF_DRV_STATE_INITIALIZED);
+
+    while (length)
+    {
+        uint32_t    len = MIN(length, RNG_CONFIG_POOL_SIZE);
+        ret_code_t  err_code;
+
+        do {
+            err_code = nrf_drv_rng_rand(p_buff, len);
+        } while(err_code != NRF_SUCCESS);
+
+        length -= len;
+        p_buff += len;
+    }
+
+    NRF_LOG_DEBUG("Rand buffer data:\r\n");
+    NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_buff, length);
+}
+
+#ifdef SOFTDEVICE_PRESENT
+void nrf_drv_rng_on_sd_disable(void)
+{
+    NRF_DRV_RNG_LOCK();
+    if (m_rng_cb.state == NRF_DRV_STATE_INITIALIZED)
+    {
+        nrf_drv_rng_setup();
+        nrf_drv_rng_start();
+    }
+    NRF_DRV_RNG_RELEASE();
+}
+#endif // SOFTDEVICE_PRESENT
+
+void RNG_IRQHandler(void)
+{
+    NRF_DRV_RNG_LOCK();
+    if (
+        !NRF_DRV_RNG_SD_IS_ENABLED()            &&
+        nrf_rng_event_get(NRF_RNG_EVENT_VALRDY) &&
+        nrf_rng_int_get(NRF_RNG_INT_VALRDY_MASK))
+    {
+        nrf_rng_event_clear(NRF_RNG_EVENT_VALRDY);
+
+        uint8_t new_value = nrf_rng_random_value_get();
+        UNUSED_RETURN_VALUE(nrf_queue_push(&m_rand_pool, &new_value));
+
+        if (nrf_queue_is_full(&m_rand_pool))
+        {
+            nrf_drv_rng_stop();
+        }
+
+        NRF_LOG_DEBUG("Event: NRF_RNG_EVENT_VALRDY.\r\n");
+    }
+    NRF_DRV_RNG_RELEASE();
+}
+
+#endif // NRF_MODULE_ENABLED(RNG)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/rng/nrf_drv_rng.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,146 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_DRV_RNG_H__
+#define NRF_DRV_RNG_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "nrf_rng.h"
+#include "sdk_errors.h"
+#include "sdk_config.h"
+#include "nrf_drv_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @addtogroup nrf_rng RNG HAL and driver
+ * @ingroup nrf_drivers
+ * @brief Random number generator (RNG) APIs.
+ * @details The RNG HAL provides basic APIs for accessing the registers of the random number
+ * generator. The RNG driver provides APIs on a higher level.
+ *
+ * @defgroup nrf_drv_rng RNG driver
+ * @{
+ * @ingroup nrf_rng
+ * @brief Driver for managing the random number generator (RNG).
+ */
+
+/**@brief Struct for RNG configuration. */
+typedef struct
+{
+    bool     error_correction : 1;  /**< Error correction flag. */
+    uint8_t  interrupt_priority;    /**< interrupt priority */
+} nrf_drv_rng_config_t;
+
+/**@brief RNG default configuration. */
+#define NRF_DRV_RNG_DEFAULT_CONFIG                                                    \
+    {                                                                                 \
+        .error_correction   = RNG_CONFIG_ERROR_CORRECTION,                            \
+        .interrupt_priority = RNG_CONFIG_IRQ_PRIORITY,                                \
+    }
+
+/**
+ * @brief Function for initializing the nrf_drv_rng module.
+ *
+ * @param[in]  p_config                 Initial configuration. Default configuration used if NULL.
+ *
+ * @retval  NRF_SUCCESS                             Driver was successfully initialized.
+ * @retval  NRF_ERROR_MODULE_ALREADY_INITIALIZED    Driver was already initialized.
+ */
+ret_code_t nrf_drv_rng_init(nrf_drv_rng_config_t const * p_config);
+
+/**
+ * @brief Function for uninitializing the nrf_drv_rng module.
+ */
+void nrf_drv_rng_uninit(void);
+
+/**
+ * @brief Function for getting the number of currently available random bytes.
+ *
+ * @param[out] p_bytes_available        The number of bytes currently available in the pool.
+ */
+void nrf_drv_rng_bytes_available(uint8_t * p_bytes_available);
+
+/**
+ * @brief Function for getting the vector of random numbers.
+ *
+ * @param[out] p_buff                   Pointer to uint8_t buffer for storing the bytes.
+ * @param[in]  length                   Number of bytes to take from the pool and place in p_buff.
+ *
+ * @retval     NRF_SUCCESS              If the requested bytes were written to p_buff.
+ * @retval     NRF_ERROR_NOT_FOUND      If no bytes were written to the buffer because there were
+ *                                      not enough bytes available in the pool.
+ */
+ret_code_t nrf_drv_rng_rand(uint8_t * p_buff, uint8_t length);
+
+/**
+ * @brief Blocking function for getting an arbitrary array of random numbers.
+ *
+ * @note This function may execute for a substantial amount of time depending on the length
+ *       of the buffer required and on the state of the current internal pool of random numbers.
+ *
+ * @param[out] p_buff                   Pointer to uint8_t buffer for storing the bytes.
+ * @param[in]  length                   Number of bytes place in p_buff.
+ */
+void nrf_drv_rng_block_rand(uint8_t * p_buff, uint32_t length);
+
+#ifdef SOFTDEVICE_PRESENT
+/**
+ * @brief Function called by the SoftDevice handler when the SoftDevice has been disabled.
+ *
+ * This function is called just after the SoftDevice has been properly disabled.
+ * It has two purposes:
+ * 1. Reinitializes RNG hardware.
+ * 2. Trigger new random numbers generation.
+ */
+void nrf_drv_rng_on_sd_disable(void);
+
+#endif
+/**
+ *@}
+ **/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_DRV_RNG_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/rtc/nrf_drv_rtc.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,355 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(RTC)
+#define ENABLED_RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED)
+#if ENABLED_RTC_COUNT
+
+#include "nrf_drv_rtc.h"
+#include "nrf_rtc.h"
+#include "nrf_assert.h"
+#include "app_util_platform.h"
+
+#define NRF_LOG_MODULE_NAME "RTC"
+
+#if RTC_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       RTC_CONFIG_LOG_LEVEL
+#define NRF_LOG_INFO_COLOR  RTC_CONFIG_INFO_COLOR
+#define NRF_LOG_DEBUG_COLOR RTC_CONFIG_DEBUG_COLOR
+#define EVT_TO_STR(event)   (event == NRF_RTC_EVENT_TICK ? "NRF_RTC_EVENT_TICK" :               \
+                            (event == NRF_RTC_EVENT_OVERFLOW ? "NRF_RTC_EVENT_OVERFLOW" :       \
+                            (event == NRF_RTC_EVENT_COMPARE_0 ? "NRF_RTC_EVENT_COMPARE_0" :     \
+                            (event == NRF_RTC_EVENT_COMPARE_1 ? "NRF_RTC_EVENT_COMPARE_1" :     \
+                            (event == NRF_RTC_EVENT_COMPARE_2 ? "NRF_RTC_EVENT_COMPARE_2" :     \
+                            (event == NRF_RTC_EVENT_COMPARE_3 ? "NRF_RTC_EVENT_COMPARE_3" : "UNKNOWN EVENT")
+#else //RTC_CONFIG_LOG_ENABLED
+#define EVT_TO_STR(event)   ""
+#define NRF_LOG_LEVEL       0
+#endif //RTC_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+
+/**@brief RTC driver instance control block structure. */
+typedef struct
+{
+    nrf_drv_state_t state;        /**< Instance state. */
+    bool            reliable;     /**< Reliable mode flag. */
+    uint8_t         tick_latency; /**< Maximum length of interrupt handler in ticks (max 7.7 ms). */
+} nrf_drv_rtc_cb_t;
+
+// User callbacks local storage.
+static nrf_drv_rtc_handler_t m_handlers[ENABLED_RTC_COUNT];
+static nrf_drv_rtc_cb_t      m_cb[ENABLED_RTC_COUNT];
+
+ret_code_t nrf_drv_rtc_init(nrf_drv_rtc_t const * const p_instance,
+                            nrf_drv_rtc_config_t const * p_config,
+                            nrf_drv_rtc_handler_t handler)
+{
+    ASSERT(p_config);
+
+    ret_code_t err_code;
+
+    if (handler)
+    {
+        m_handlers[p_instance->instance_id] = handler;
+    }
+    else
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    if (m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    nrf_drv_common_irq_enable(p_instance->irq, p_config->interrupt_priority);
+    nrf_rtc_prescaler_set(p_instance->p_reg, p_config->prescaler);
+    m_cb[p_instance->instance_id].reliable     = p_config->reliable;
+    m_cb[p_instance->instance_id].tick_latency = p_config->tick_latency;
+    m_cb[p_instance->instance_id].state        = NRF_DRV_STATE_INITIALIZED;
+
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+void nrf_drv_rtc_uninit(nrf_drv_rtc_t const * const p_instance)
+{
+    uint32_t mask = NRF_RTC_INT_TICK_MASK     |
+                    NRF_RTC_INT_OVERFLOW_MASK |
+                    NRF_RTC_INT_COMPARE0_MASK |
+                    NRF_RTC_INT_COMPARE1_MASK |
+                    NRF_RTC_INT_COMPARE2_MASK |
+                    NRF_RTC_INT_COMPARE3_MASK;
+    ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED);
+
+    nrf_drv_common_irq_disable(p_instance->irq);
+
+    nrf_rtc_task_trigger(p_instance->p_reg, NRF_RTC_TASK_STOP);
+    nrf_rtc_event_disable(p_instance->p_reg, mask);
+    nrf_rtc_int_disable(p_instance->p_reg, mask);
+
+    m_cb[p_instance->instance_id].state = NRF_DRV_STATE_UNINITIALIZED;
+    NRF_LOG_INFO("Uninitialized.\r\n");
+}
+
+void nrf_drv_rtc_enable(nrf_drv_rtc_t const * const p_instance)
+{
+    ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_INITIALIZED);
+
+    nrf_rtc_task_trigger(p_instance->p_reg, NRF_RTC_TASK_START);
+    m_cb[p_instance->instance_id].state = NRF_DRV_STATE_POWERED_ON;
+    NRF_LOG_INFO("Enabled.\r\n");
+}
+
+void nrf_drv_rtc_disable(nrf_drv_rtc_t const * const p_instance)
+{
+    ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED);
+
+    nrf_rtc_task_trigger(p_instance->p_reg, NRF_RTC_TASK_STOP);
+    m_cb[p_instance->instance_id].state = NRF_DRV_STATE_INITIALIZED;
+    NRF_LOG_INFO("Disabled.\r\n");
+}
+
+ret_code_t nrf_drv_rtc_cc_disable(nrf_drv_rtc_t const * const p_instance, uint32_t channel)
+{
+    ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED);
+    ASSERT(channel<p_instance->cc_channel_count);
+
+    ret_code_t err_code;
+    uint32_t int_mask = RTC_CHANNEL_INT_MASK(channel);
+    nrf_rtc_event_t event    = RTC_CHANNEL_EVENT_ADDR(channel);
+
+    nrf_rtc_event_disable(p_instance->p_reg,int_mask);
+    if (nrf_rtc_int_is_enabled(p_instance->p_reg,int_mask))
+    {
+        nrf_rtc_int_disable(p_instance->p_reg,int_mask);
+        if (nrf_rtc_event_pending(p_instance->p_reg,event))
+        {
+            nrf_rtc_event_clear(p_instance->p_reg,event);
+            err_code = NRF_ERROR_TIMEOUT;
+            NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+            return err_code;
+        }
+    }
+    NRF_LOG_INFO("RTC id: %d, channel disabled: %d.\r\n", p_instance->instance_id, channel);
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+ret_code_t nrf_drv_rtc_cc_set(nrf_drv_rtc_t const * const p_instance,
+                              uint32_t channel,
+                              uint32_t val,
+                              bool enable_irq)
+{
+    ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED);
+    ASSERT(channel<p_instance->cc_channel_count);
+
+    ret_code_t err_code;
+    uint32_t int_mask = RTC_CHANNEL_INT_MASK(channel);
+    nrf_rtc_event_t event    = RTC_CHANNEL_EVENT_ADDR(channel);
+
+    nrf_rtc_event_disable(p_instance->p_reg, int_mask);
+    nrf_rtc_int_disable(p_instance->p_reg, int_mask);
+
+    val = RTC_WRAP(val);
+    if (m_cb[p_instance->instance_id].reliable)
+    {
+        nrf_rtc_cc_set(p_instance->p_reg,channel,val);
+        uint32_t cnt = nrf_rtc_counter_get(p_instance->p_reg);
+        int32_t diff = cnt - val;
+        if (cnt < val)
+        {
+            diff += RTC_COUNTER_COUNTER_Msk;
+        }
+        if (diff < m_cb[p_instance->instance_id].tick_latency)
+        {
+            err_code = NRF_ERROR_TIMEOUT;
+            NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+            return err_code;
+        }
+    }
+    else
+    {
+        nrf_rtc_cc_set(p_instance->p_reg,channel,val);
+    }
+
+    if (enable_irq)
+    {
+        nrf_rtc_event_clear(p_instance->p_reg,event);
+        nrf_rtc_int_enable(p_instance->p_reg, int_mask);
+    }
+    nrf_rtc_event_enable(p_instance->p_reg,int_mask);
+
+    NRF_LOG_INFO("RTC id: %d, channel enabled: %d, compare value: %d.\r\n", p_instance->instance_id, channel, val);
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+void nrf_drv_rtc_tick_enable(nrf_drv_rtc_t const * const p_instance, bool enable_irq)
+{
+    nrf_rtc_event_t event = NRF_RTC_EVENT_TICK;
+    uint32_t mask = NRF_RTC_INT_TICK_MASK;
+
+    nrf_rtc_event_clear(p_instance->p_reg, event);
+    nrf_rtc_event_enable(p_instance->p_reg, mask);
+    if (enable_irq)
+    {
+        nrf_rtc_int_enable(p_instance->p_reg, mask);
+    }
+    NRF_LOG_INFO("Tick events enabled.\r\n");
+}
+
+void nrf_drv_rtc_tick_disable(nrf_drv_rtc_t const * const p_instance)
+{
+    uint32_t mask = NRF_RTC_INT_TICK_MASK;
+
+    nrf_rtc_event_disable(p_instance->p_reg, mask);
+    nrf_rtc_int_disable(p_instance->p_reg, mask);
+    NRF_LOG_INFO("Tick events disabled.\r\n");
+}
+
+void nrf_drv_rtc_overflow_enable(nrf_drv_rtc_t const * const p_instance, bool enable_irq)
+{
+    nrf_rtc_event_t event = NRF_RTC_EVENT_OVERFLOW;
+    uint32_t mask = NRF_RTC_INT_OVERFLOW_MASK;
+
+    nrf_rtc_event_clear(p_instance->p_reg, event);
+    nrf_rtc_event_enable(p_instance->p_reg, mask);
+    if (enable_irq)
+    {
+        nrf_rtc_int_enable(p_instance->p_reg, mask);
+    }
+}
+void nrf_drv_rtc_overflow_disable(nrf_drv_rtc_t const * const p_instance)
+{
+    uint32_t mask = NRF_RTC_INT_OVERFLOW_MASK;
+    nrf_rtc_event_disable(p_instance->p_reg, mask);
+    nrf_rtc_int_disable(p_instance->p_reg, mask);
+}
+
+uint32_t nrf_drv_rtc_max_ticks_get(nrf_drv_rtc_t const * const p_instance)
+{
+    uint32_t ticks;
+    if (m_cb[p_instance->instance_id].reliable)
+    {
+        ticks = RTC_COUNTER_COUNTER_Msk - m_cb[p_instance->instance_id].tick_latency;
+    }
+    else
+    {
+        ticks = RTC_COUNTER_COUNTER_Msk;
+    }
+    return ticks;
+}
+
+/**@brief Generic function for handling RTC interrupt
+ *
+ * @param[in]  p_reg         Pointer to instance register structure.
+ * @param[in]  instance_id   Index of instance.
+ */
+__STATIC_INLINE void nrf_drv_rtc_int_handler(NRF_RTC_Type * p_reg,
+                                             uint32_t instance_id,
+                                             uint32_t channel_count)
+{
+    uint32_t i;
+    uint32_t int_mask = (uint32_t)NRF_RTC_INT_COMPARE0_MASK;
+    nrf_rtc_event_t event = NRF_RTC_EVENT_COMPARE_0;
+
+    for (i = 0; i < channel_count; i++)
+    {
+        if (nrf_rtc_int_is_enabled(p_reg,int_mask) && nrf_rtc_event_pending(p_reg,event))
+        {
+            nrf_rtc_event_disable(p_reg,int_mask);
+            nrf_rtc_int_disable(p_reg,int_mask);
+            nrf_rtc_event_clear(p_reg,event);
+            NRF_LOG_DEBUG("Event: %s, instance id: %d.\r\n",
+                         (uint32_t)EVT_TO_STR(event), (uint32_t)instance_id);
+            m_handlers[instance_id]((nrf_drv_rtc_int_type_t)i);
+        }
+        int_mask <<= 1;
+        event    = (nrf_rtc_event_t)((uint32_t)event + sizeof(uint32_t));
+    }
+    event = NRF_RTC_EVENT_TICK;
+    if (nrf_rtc_int_is_enabled(p_reg,NRF_RTC_INT_TICK_MASK) &&
+        nrf_rtc_event_pending(p_reg, event))
+    {
+        nrf_rtc_event_clear(p_reg, event);
+        NRF_LOG_DEBUG("Event: %s, instance id: %d.\r\n", (uint32_t)EVT_TO_STR(event), instance_id);
+        m_handlers[instance_id](NRF_DRV_RTC_INT_TICK);
+    }
+
+    event = NRF_RTC_EVENT_OVERFLOW;
+    if (nrf_rtc_int_is_enabled(p_reg,NRF_RTC_INT_OVERFLOW_MASK) &&
+        nrf_rtc_event_pending(p_reg, event))
+    {
+        nrf_rtc_event_clear(p_reg,event);
+        NRF_LOG_DEBUG("Event: %s, instance id: %d.\r\n", (uint32_t)EVT_TO_STR(event), instance_id);
+        m_handlers[instance_id](NRF_DRV_RTC_INT_OVERFLOW);
+    }
+}
+
+#if NRF_MODULE_ENABLED(RTC0)
+void RTC0_IRQHandler(void)
+{
+    nrf_drv_rtc_int_handler(NRF_RTC0,RTC0_INSTANCE_INDEX, NRF_RTC_CC_CHANNEL_COUNT(0));
+}
+#endif
+
+#if NRF_MODULE_ENABLED(RTC1)
+void RTC1_IRQHandler(void)
+{
+    nrf_drv_rtc_int_handler(NRF_RTC1,RTC1_INSTANCE_INDEX, NRF_RTC_CC_CHANNEL_COUNT(1));
+}
+#endif
+
+#if NRF_MODULE_ENABLED(RTC2)
+void RTC2_IRQHandler(void)
+{
+    nrf_drv_rtc_int_handler(NRF_RTC2,RTC2_INSTANCE_INDEX, NRF_RTC_CC_CHANNEL_COUNT(2));
+}
+#endif
+#endif //ENABLED_RTC_COUNT
+#endif //NRF_MODULE_ENABLED(RTC)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/rtc/nrf_drv_rtc.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,364 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_DRV_RTC_H
+#define NRF_DRV_RTC_H
+
+
+#include "sdk_config.h"
+#include "nordic_common.h"
+#include "nrf_drv_common.h"
+#include "nrf_rtc.h"
+#include "sdk_errors.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @addtogroup nrf_rtc RTC HAL and driver
+ * @ingroup nrf_drivers
+ * @brief Real timer counter (RTC) APIs.
+ * @details The RTC HAL provides basic APIs for accessing the registers of the real time counter (RTC).
+ * The RTC driver provides APIs on a higher level.
+ *
+ * @defgroup nrf_drv_rtc RTC driver
+ * @{
+ * @ingroup nrf_rtc
+ * @brief Real timer counter (RTC) driver.
+ */
+
+/**@brief Macro to convert microseconds into ticks. */
+#define RTC_US_TO_TICKS(us,freq) ((us * freq) / 1000000)
+
+/**
+ * @enum nrf_drv_rtc_int_type_t
+ * @brief RTC driver interrupt types.
+ */
+typedef enum
+{
+    NRF_DRV_RTC_INT_COMPARE0 = 0, /**< Interrupt from COMPARE0 event. */
+    NRF_DRV_RTC_INT_COMPARE1 = 1, /**< Interrupt from COMPARE1 event. */
+    NRF_DRV_RTC_INT_COMPARE2 = 2, /**< Interrupt from COMPARE2 event. */
+    NRF_DRV_RTC_INT_COMPARE3 = 3, /**< Interrupt from COMPARE3 event. */
+    NRF_DRV_RTC_INT_TICK     = 4, /**< Interrupt from TICK event. */
+    NRF_DRV_RTC_INT_OVERFLOW = 5  /**< Interrupt from OVERFLOW event. */
+} nrf_drv_rtc_int_type_t;
+
+/**@brief RTC driver instance  structure. */
+typedef struct
+{
+    NRF_RTC_Type  * p_reg;            /**< Pointer to instance register set. */
+    IRQn_Type       irq;              /**< Instance IRQ ID. */
+    uint8_t         instance_id;      /**< Instance index. */
+    uint8_t         cc_channel_count; /**< Number of capture/compare channels. */
+} nrf_drv_rtc_t;
+
+#define RTC0_INSTANCE_INDEX 0
+#define RTC1_INSTANCE_INDEX RTC0_INSTANCE_INDEX+RTC0_ENABLED
+#define RTC2_INSTANCE_INDEX RTC1_INSTANCE_INDEX+RTC1_ENABLED
+
+/**@brief Macro for creating RTC driver instance.*/
+#define NRF_DRV_RTC_INSTANCE(id)                           \
+{                                                          \
+    .p_reg            = CONCAT_2(NRF_RTC, id),             \
+    .irq              = CONCAT_3(RTC, id, _IRQn),          \
+    .instance_id      = CONCAT_3(RTC, id, _INSTANCE_INDEX),\
+    .cc_channel_count = NRF_RTC_CC_CHANNEL_COUNT(id),      \
+}
+
+/**@brief RTC driver instance configuration structure. */
+typedef struct
+{
+    uint16_t prescaler;          /**< Prescaler. */
+    uint8_t  interrupt_priority; /**< Interrupt priority. */
+    uint8_t  tick_latency;       /**< Maximum length of interrupt handler in ticks (max 7.7 ms). */
+    bool     reliable;           /**< Reliable mode flag. */
+} nrf_drv_rtc_config_t;
+
+/**@brief RTC instance default configuration. */
+#define NRF_DRV_RTC_DEFAULT_CONFIG                                                               \
+{                                                                                                \
+    .prescaler          = RTC_FREQ_TO_PRESCALER(RTC_DEFAULT_CONFIG_FREQUENCY),                   \
+    .interrupt_priority = RTC_DEFAULT_CONFIG_IRQ_PRIORITY,                                       \
+    .reliable           = RTC_DEFAULT_CONFIG_RELIABLE,                                           \
+    .tick_latency       = RTC_US_TO_TICKS(NRF_MAXIMUM_LATENCY_US, RTC_DEFAULT_CONFIG_FREQUENCY), \
+}
+
+/**@brief RTC driver instance handler type. */
+typedef void (*nrf_drv_rtc_handler_t)(nrf_drv_rtc_int_type_t int_type);
+
+/**@brief Function for initializing the RTC driver instance.
+ *
+ * After initialization, the instance is in power off state.
+ *
+ * @param[in]  p_instance         Pointer to the driver instance structure.
+ * @param[in]  p_config           Initial configuration. Default configuration used if NULL.
+ * @param[in]  handler            User's event handler.
+ *
+ * @retval     NRF_SUCCESS               If successfully initialized.
+ * @retval     NRF_ERROR_INVALID_PARAM   If no handler was provided.
+ * @retval     NRF_ERROR_INVALID_STATE   If the instance is already initialized.
+ */
+ret_code_t nrf_drv_rtc_init(nrf_drv_rtc_t const * const p_instance,
+                            nrf_drv_rtc_config_t const * p_config,
+                            nrf_drv_rtc_handler_t handler);
+
+/**@brief Function for uninitializing the RTC driver instance.
+ *
+ * After uninitialization, the instance is in idle state. The hardware should return to the state
+ *       before initialization. The function asserts if the instance is in idle state.
+ *
+ * @param[in]  p_instance         Pointer to the driver instance structure.
+ */
+void nrf_drv_rtc_uninit(nrf_drv_rtc_t const * const p_instance);
+
+/**@brief Function for enabling the RTC driver instance.
+ *
+ * @note Function asserts if instance is enabled.
+ *
+ * @param[in]  p_instance         Pointer to the driver instance structure.
+ */
+void nrf_drv_rtc_enable(nrf_drv_rtc_t const * const p_instance);
+
+/**@brief Function for disabling the RTC driver instance.
+ *
+ * @note Function asserts if instance is disabled.
+ *
+ * @param[in]  p_instance         Pointer to the driver instance structure.
+ */
+void nrf_drv_rtc_disable(nrf_drv_rtc_t const * const p_instance);
+
+/**@brief Function for setting a compare channel.
+ *
+ * The function asserts if the instance is not initialized or if the channel parameter is
+ *       wrong. The function powers on the instance if the instance was in power off state.
+ *
+ * The driver is not entering a critical section when configuring RTC, which means that it can be
+ *       preempted for a certain amount of time. When the driver was preempted and the value to be set
+ *       is short in time, there is a risk that the driver sets a compare value that is
+ *       behind. If RTCn_CONFIG_RELIABLE is 1 for the given instance, the Reliable mode handles that case.
+ *       However, to detect if the requested value is behind, this mode makes the following assumptions:
+ *        -  The maximum preemption time in ticks (8 - bit value) is known and is less than 7.7 ms
+ *         (for prescaler = 0, RTC frequency 32 kHz).
+ *        -  The requested absolute compare value is not bigger than (0x00FFFFFF) - tick_latency. It is
+ *         the user's responsibility to ensure that.
+ *
+ * @param[in]  p_instance         Pointer to the driver instance structure.
+ * @param[in]  channel            One of the instance's channels.
+ * @param[in]  val                Absolute value to be set in the compare register.
+ * @param[in]  enable_irq         True to enable the interrupt. False to disable the interrupt.
+ *
+ * @retval     NRF_SUCCESS         If the procedure was successful.
+ * @retval     NRF_ERROR_TIMEOUT   If the compare was not set because the request value is behind the current counter
+ *                                 value. This error can only be reported if RTCn_CONFIG_RELIABLE = 1.
+ */
+ret_code_t nrf_drv_rtc_cc_set(nrf_drv_rtc_t const * const p_instance,
+                              uint32_t channel,
+                              uint32_t val,
+                              bool enable_irq);
+
+/**@brief Function for disabling a channel.
+ *
+ * This function disables channel events and channel interrupts. The function asserts if the instance is not
+ *       initialized or if the channel parameter is wrong.
+ *
+ * @param[in]  p_instance          Pointer to the driver instance structure.
+ * @param[in]  channel             One of the instance's channels.
+ *
+ * @retval     NRF_SUCCESS         If the procedure was successful.
+ * @retval     NRF_ERROR_TIMEOUT   If an interrupt was pending on the requested channel.
+ */
+ret_code_t nrf_drv_rtc_cc_disable(nrf_drv_rtc_t const * const p_instance, uint32_t channel);
+
+/**@brief Function for enabling tick.
+ *
+ * This function enables the tick event and optionally the interrupt. The function asserts if the instance is not
+ *       powered on.
+ *
+ * @param[in]  p_instance         Pointer to the driver instance structure.
+ * @param[in]  enable_irq         True to enable the interrupt. False to disable the interrupt.
+ */
+void nrf_drv_rtc_tick_enable(nrf_drv_rtc_t const * const p_instance, bool enable_irq);
+
+/**@brief Function for disabling tick.
+ *
+ * This function disables the tick event and interrupt.
+ *
+ * @param[in]  p_instance         Pointer to the driver instance structure.
+ */
+void nrf_drv_rtc_tick_disable(nrf_drv_rtc_t const * const p_instance);
+
+/**@brief Function for enabling overflow.
+ *
+ * This function enables the overflow event and optionally the interrupt. The function asserts if the instance is
+ *       not powered on.
+ *
+ * @param[in]  p_instance         Pointer to the driver instance structure.
+ * @param[in]  enable_irq         True to enable the interrupt. False to disable the interrupt.
+ */
+void nrf_drv_rtc_overflow_enable(nrf_drv_rtc_t const * const p_instance, bool enable_irq);
+
+/**@brief Function for disabling overflow.
+ *
+ * This function disables the overflow event and interrupt.
+ *
+ * @param[in]  p_instance         Pointer to the driver instance structure.
+ */
+void nrf_drv_rtc_overflow_disable(nrf_drv_rtc_t const * const p_instance);
+
+/**@brief Function for getting the maximum relative ticks value that can be set in the compare channel.
+ *
+ * When a SoftDevice is used, it occupies the highest level interrupt, so that the application code can be
+ *       interrupted at any moment for a certain period of time. If Reliable mode is enabled, the provided
+ *       maximum latency is taken into account and the return value is smaller than the RTC counter
+ *       resolution. If Reliable mode is disabled, the return value equals the counter resolution.
+ *
+ * @param[in]  p_instance  Pointer to the driver instance structure.
+ *
+ * @retval     ticks         Maximum ticks value.
+ */
+uint32_t nrf_drv_rtc_max_ticks_get(nrf_drv_rtc_t const * const p_instance);
+
+/**@brief Function for disabling all instance interrupts.
+  *
+ * @param[in]  p_instance          Pointer to the driver instance structure.
+ * @param[in]  p_mask              Pointer to the location where the mask is filled.
+ */
+__STATIC_INLINE void nrf_drv_rtc_int_disable(nrf_drv_rtc_t const * const p_instance,
+                                             uint32_t * p_mask);
+
+/**@brief Function for enabling instance interrupts.
+ *
+ * @param[in]  p_instance         Pointer to the driver instance structure.
+ * @param[in]  mask               Mask of interrupts to enable.
+ */
+__STATIC_INLINE void nrf_drv_rtc_int_enable(nrf_drv_rtc_t const * const p_instance, uint32_t mask);
+
+/**@brief Function for retrieving the current counter value.
+ *
+ * This function asserts if the instance is not powered on or if p_val is NULL.
+ *
+ * @param[in]  p_instance    Pointer to the driver instance structure.
+ *
+ * @retval     value         Counter value.
+ */
+__STATIC_INLINE uint32_t nrf_drv_rtc_counter_get(nrf_drv_rtc_t const * const p_instance);
+
+/**@brief Function for clearing the counter value.
+ *
+ * This function asserts if the instance is not powered on.
+ *
+ * @param[in]  p_instance         Pointer to the driver instance structure.
+ */
+__STATIC_INLINE void nrf_drv_rtc_counter_clear(nrf_drv_rtc_t const * const p_instance);
+
+/**@brief Function for returning a requested task address for the RTC driver instance.
+ *
+ * This function asserts if the output pointer is NULL. The task address can be used by the PPI module.
+ *
+ * @param[in]  p_instance         Pointer to the instance.
+ * @param[in]  task                One of the peripheral tasks.
+ *
+ * @retval     Address of task register.
+ */
+__STATIC_INLINE uint32_t nrf_drv_rtc_task_address_get(nrf_drv_rtc_t const * const p_instance,
+                                                      nrf_rtc_task_t task);
+
+/**@brief Function for returning a requested event address for the RTC driver instance.
+ *
+ * This function asserts if the output pointer is NULL. The event address can be used by the PPI module.
+ *
+ * @param[in]  p_instance          Pointer to the driver instance structure.
+ * @param[in]  event               One of the peripheral events.
+ *
+ * @retval     Address of event register.
+ */
+__STATIC_INLINE uint32_t nrf_drv_rtc_event_address_get(nrf_drv_rtc_t const * const p_instance,
+                                                       nrf_rtc_event_t event);
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_drv_rtc_int_disable(nrf_drv_rtc_t const * const p_instance,
+                                                 uint32_t * p_mask)
+{
+    *p_mask = nrf_rtc_int_get(p_instance->p_reg);
+    nrf_rtc_int_disable(p_instance->p_reg, NRF_RTC_INT_TICK_MASK |
+                                           NRF_RTC_INT_OVERFLOW_MASK |
+                                           NRF_RTC_INT_COMPARE0_MASK |
+                                           NRF_RTC_INT_COMPARE1_MASK |
+                                           NRF_RTC_INT_COMPARE2_MASK |
+                                           NRF_RTC_INT_COMPARE3_MASK);
+}
+
+__STATIC_INLINE void nrf_drv_rtc_int_enable(nrf_drv_rtc_t const * const p_instance, uint32_t mask)
+{
+    nrf_rtc_int_enable(p_instance->p_reg, mask);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_rtc_counter_get(nrf_drv_rtc_t const * const p_instance)
+{
+    return nrf_rtc_counter_get(p_instance->p_reg);
+}
+
+__STATIC_INLINE void nrf_drv_rtc_counter_clear(nrf_drv_rtc_t const * const p_instance)
+{
+    nrf_rtc_task_trigger(p_instance->p_reg,NRF_RTC_TASK_CLEAR);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_rtc_task_address_get(nrf_drv_rtc_t const * const p_instance,
+                                                      nrf_rtc_task_t task)
+{
+    return nrf_rtc_task_address_get(p_instance->p_reg, task);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_rtc_event_address_get(nrf_drv_rtc_t const * const p_instance,
+                                                       nrf_rtc_event_t event)
+{
+    return nrf_rtc_event_address_get(p_instance->p_reg, event);
+}
+#endif /* SUPPRESS_INLINE_IMPLEMENTATION */
+
+/**
+ *@}
+ **/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF_DRV_RTC_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/saadc/nrf_drv_saadc.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,634 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(SAADC)
+#include "nrf_drv_saadc.h"
+#include "nrf_assert.h"
+#include "nrf_drv_common.h"
+#include "app_util_platform.h"
+
+#define NRF_LOG_MODULE_NAME "SAADC"
+
+#if SAADC_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       SAADC_CONFIG_LOG_LEVEL
+#define NRF_LOG_INFO_COLOR  SAADC_CONFIG_INFO_COLOR
+#define NRF_LOG_DEBUG_COLOR SAADC_CONFIG_DEBUG_COLOR
+#define EVT_TO_STR(event)   (event == NRF_SAADC_EVENT_STARTED ? "NRF_SAADC_EVENT_STARTED" :                         \
+                            (event == NRF_SAADC_EVENT_END ? "NRF_SAADC_EVENT_END" :                                 \
+                            (event == NRF_SAADC_EVENT_DONE ? "NRF_SAADC_EVENT_DONE" :                               \
+                            (event == NRF_SAADC_EVENT_RESULTDONE ? "NRF_SAADC_EVENT_RESULTDONE" :                   \
+                            (event == NRF_SAADC_EVENT_CALIBRATEDONE ? "NRF_SAADC_EVENT_CALIBRATEDONE" :             \
+                            (event == NRF_SAADC_EVENT_STOPPED ? "NRF_SAADC_EVENT_STOPPED" : "UNKNOWN EVENT"))))))
+#define EVT_TO_STR_LIMIT(event) (event == NRF_SAADC_LIMIT_LOW ? "NRF_SAADC_LIMIT_LOW" :                                \
+                                (event == NRF_SAADC_LIMIT_HIGH ? "NRF_SAADC_LIMIT_HIGH" : "UNKNOWN EVENT"))
+#else //SAADC_CONFIG_LOG_ENABLED
+#define EVT_TO_STR(event)   ""
+#define NRF_LOG_LEVEL       0
+#endif //SAADC_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+
+
+typedef enum
+{
+    NRF_SAADC_STATE_IDLE        = 0,
+    NRF_SAADC_STATE_BUSY        = 1,
+    NRF_SAADC_STATE_CALIBRATION = 2
+} nrf_saadc_state_t;
+
+
+typedef struct
+{
+    nrf_saadc_input_t pselp;
+    nrf_saadc_input_t pseln;
+} nrf_saadc_psel_buffer;
+
+static const nrf_drv_saadc_config_t m_default_config = NRF_DRV_SAADC_DEFAULT_CONFIG;
+
+/** @brief SAADC control block.*/
+typedef struct
+{
+    nrf_drv_saadc_event_handler_t event_handler;                 ///< Event handler function pointer.
+    volatile nrf_saadc_value_t  * p_buffer;                      ///< Sample buffer.
+    volatile uint16_t             buffer_size;                   ///< Size of the sample buffer.
+    volatile nrf_saadc_value_t  * p_secondary_buffer;            ///< Secondary sample buffer.
+    uint32_t                      limits_enabled_flags;          ///< Enabled limits flags.
+    uint16_t                      secondary_buffer_size;         ///< Size of the secondary buffer.
+    uint16_t                      buffer_size_left;              ///< When low power mode is active indicates how many samples left to convert on current buffer.
+    nrf_saadc_psel_buffer         psel[NRF_SAADC_CHANNEL_COUNT]; ///< Pin configurations of SAADC channels.
+    nrf_drv_state_t               state;                         ///< Driver initialization state.
+    nrf_saadc_state_t             adc_state;                     ///< State of the SAADC.
+    uint8_t                       active_channels;               ///< Number of enabled SAADC channels.
+    bool                          low_power_mode;                ///< Indicates if low power mode is active.
+    bool                          conversions_end;               ///< When low power mode is active indicates end of conversions on current buffer.
+} nrf_drv_saadc_cb_t;
+
+static nrf_drv_saadc_cb_t m_cb;
+
+#define LOW_LIMIT_TO_FLAG(channel)      ((2 * channel + 1))
+#define HIGH_LIMIT_TO_FLAG(channel)     ((2 * channel))
+#define FLAG_IDX_TO_EVENT(idx)          ((nrf_saadc_event_t)((uint32_t)NRF_SAADC_EVENT_CH0_LIMITH + \
+                                            4 * idx))
+#define LIMIT_EVENT_TO_CHANNEL(event)   (uint8_t)(((uint32_t)event - \
+                                            (uint32_t)NRF_SAADC_EVENT_CH0_LIMITH) / 8)
+#define LIMIT_EVENT_TO_LIMIT_TYPE(event)((((uint32_t)event - (uint32_t)NRF_SAADC_EVENT_CH0_LIMITH) & 4) \
+                                            ? NRF_SAADC_LIMIT_LOW : NRF_SAADC_LIMIT_HIGH)
+#define HW_TIMEOUT 10000
+
+void SAADC_IRQHandler(void)
+{
+    if (nrf_saadc_event_check(NRF_SAADC_EVENT_END))
+    {
+        nrf_saadc_event_clear(NRF_SAADC_EVENT_END);
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_SAADC_EVENT_END));
+
+        if (!m_cb.low_power_mode || m_cb.conversions_end)
+        {
+            nrf_drv_saadc_evt_t evt;
+            evt.type               = NRF_DRV_SAADC_EVT_DONE;
+            evt.data.done.p_buffer = (nrf_saadc_value_t *)m_cb.p_buffer;
+            evt.data.done.size     = m_cb.buffer_size;
+
+            if (m_cb.p_secondary_buffer == NULL)
+            {
+                m_cb.adc_state = NRF_SAADC_STATE_IDLE;
+            }
+            else
+            {
+                m_cb.p_buffer           = m_cb.p_secondary_buffer;
+                m_cb.buffer_size        = m_cb.secondary_buffer_size;
+                m_cb.p_secondary_buffer = NULL;
+                if (!m_cb.low_power_mode)
+                {
+                    nrf_saadc_task_trigger(NRF_SAADC_TASK_START);
+                }
+            }
+            m_cb.event_handler(&evt);
+            m_cb.conversions_end = false;
+        }
+    }
+    if (m_cb.low_power_mode && nrf_saadc_event_check(NRF_SAADC_EVENT_STARTED))
+    {
+        nrf_saadc_event_clear(NRF_SAADC_EVENT_STARTED);
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_SAADC_EVENT_STARTED));
+
+        if (m_cb.buffer_size_left == 0) 
+        {
+            // Sampling finished, next buffer in progress.
+            m_cb.buffer_size_left = m_cb.buffer_size - m_cb.active_channels;
+            nrf_saadc_buffer_init((nrf_saadc_value_t *)&m_cb.p_buffer[m_cb.buffer_size -
+                                                                      m_cb.buffer_size_left],
+                                  m_cb.active_channels);
+        }
+        else if (m_cb.buffer_size_left > m_cb.active_channels)
+        {
+            // More samples to convert than for single event.
+            m_cb.buffer_size_left -= m_cb.active_channels;
+            nrf_saadc_buffer_init((nrf_saadc_value_t *)&m_cb.p_buffer[m_cb.buffer_size -
+                                                                      m_cb.buffer_size_left],
+                                  m_cb.active_channels);
+        }
+        else if ((m_cb.buffer_size_left == m_cb.active_channels) &&
+
+                 (m_cb.p_secondary_buffer != NULL)) 
+        {
+            // Samples to convert for one event, prepare next buffer.
+            m_cb.conversions_end  = true;
+            m_cb.buffer_size_left = 0;
+            nrf_saadc_buffer_init((nrf_saadc_value_t *)m_cb.p_secondary_buffer,
+                                  m_cb.active_channels);
+        }
+
+        else if (m_cb.buffer_size_left == m_cb.active_channels) 
+        {
+            // Samples to convert for one event, but no second buffer.
+            m_cb.conversions_end  = true;
+            m_cb.buffer_size_left = 0;
+        }
+        nrf_saadc_event_clear(NRF_SAADC_EVENT_END);
+        nrf_saadc_task_trigger(NRF_SAADC_TASK_SAMPLE);
+    }
+    if (nrf_saadc_event_check(NRF_SAADC_EVENT_CALIBRATEDONE))
+    {
+        nrf_saadc_event_clear(NRF_SAADC_EVENT_CALIBRATEDONE);
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_SAADC_EVENT_CALIBRATEDONE));
+        m_cb.adc_state = NRF_SAADC_STATE_IDLE;
+
+        nrf_drv_saadc_evt_t evt;
+        evt.type = NRF_DRV_SAADC_EVT_CALIBRATEDONE;
+        m_cb.event_handler(&evt);
+    }
+    if (nrf_saadc_event_check(NRF_SAADC_EVENT_STOPPED))
+    {
+        nrf_saadc_event_clear(NRF_SAADC_EVENT_STOPPED);
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_SAADC_EVENT_STOPPED));
+        m_cb.adc_state = NRF_SAADC_STATE_IDLE;
+    }
+    else
+    {
+        uint32_t          limit_flags = m_cb.limits_enabled_flags;
+        uint32_t          flag_idx;
+        nrf_saadc_event_t event;
+
+        while (limit_flags)
+        {
+            flag_idx     = __CLZ(limit_flags);
+            limit_flags &= ~((1UL << 31) >> flag_idx);
+            event        = FLAG_IDX_TO_EVENT(flag_idx);
+            if (nrf_saadc_event_check(event))
+            {
+                nrf_saadc_event_clear(event);
+                nrf_drv_saadc_evt_t evt;
+                evt.type                  = NRF_DRV_SAADC_EVT_LIMIT;
+                evt.data.limit.channel    = LIMIT_EVENT_TO_CHANNEL(event);
+                evt.data.limit.limit_type = LIMIT_EVENT_TO_LIMIT_TYPE(event);
+                NRF_LOG_DEBUG("Event limit, channel: %d, limit type: %s.\r\n", evt.data.limit.channel, (uint32_t)EVT_TO_STR(evt.data.limit.limit_type));
+                m_cb.event_handler(&evt);
+            }
+        }
+    }
+}
+
+
+ret_code_t nrf_drv_saadc_init(nrf_drv_saadc_config_t const * p_config,
+                              nrf_drv_saadc_event_handler_t  event_handler)
+{
+    ret_code_t err_code;
+
+    if (m_cb.state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", 
+                        (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+    if (event_handler == NULL)
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", 
+                        (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    if (p_config == NULL)
+    {
+        p_config = &m_default_config;
+    }
+
+    m_cb.event_handler = event_handler;
+    nrf_saadc_resolution_set(p_config->resolution);
+    nrf_saadc_oversample_set(p_config->oversample);
+    m_cb.low_power_mode       = p_config->low_power_mode;
+    m_cb.state                = NRF_DRV_STATE_INITIALIZED;
+    m_cb.adc_state            = NRF_SAADC_STATE_IDLE;
+    m_cb.active_channels      = 0;
+    m_cb.limits_enabled_flags = 0;
+    m_cb.conversions_end      = false;
+
+    nrf_saadc_int_disable(NRF_SAADC_INT_ALL);
+    nrf_saadc_event_clear(NRF_SAADC_EVENT_END);
+    nrf_drv_common_irq_enable(SAADC_IRQn, p_config->interrupt_priority);
+    nrf_saadc_int_enable(NRF_SAADC_INT_END);
+    if (m_cb.low_power_mode)
+    {
+        nrf_saadc_int_enable(NRF_SAADC_INT_STARTED);
+    }
+
+    nrf_saadc_enable();
+
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+void nrf_drv_saadc_uninit(void)
+{
+    ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
+
+    nrf_saadc_int_disable(NRF_SAADC_INT_ALL);
+    nrf_drv_common_irq_disable(SAADC_IRQn);
+    nrf_saadc_task_trigger(NRF_SAADC_TASK_STOP);
+
+    // Wait for ADC being stopped.
+    uint32_t timeout = HW_TIMEOUT;
+
+    while (nrf_saadc_event_check(NRF_SAADC_EVENT_STOPPED) == 0 && timeout > 0)
+    {
+        --timeout;
+    }
+    ASSERT(timeout > 0);
+
+    nrf_saadc_disable();
+    m_cb.adc_state = NRF_SAADC_STATE_IDLE;
+
+    for (uint8_t channel = 0; channel < NRF_SAADC_CHANNEL_COUNT; ++channel)
+    {
+        if (m_cb.psel[channel].pselp != NRF_SAADC_INPUT_DISABLED)
+        {
+            (void)nrf_drv_saadc_channel_uninit(channel);
+        }
+    }
+
+    m_cb.state = NRF_DRV_STATE_UNINITIALIZED;
+}
+
+
+ret_code_t nrf_drv_saadc_channel_init(uint8_t                                  channel,
+                                      nrf_saadc_channel_config_t const * const p_config)
+{
+    ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
+    ASSERT(channel < NRF_SAADC_CHANNEL_COUNT);
+    // Oversampling can be used only with one channel.
+    ASSERT((nrf_saadc_oversample_get() == NRF_SAADC_OVERSAMPLE_DISABLED) ||
+           (m_cb.active_channels == 0));
+    ASSERT((p_config->pin_p <= NRF_SAADC_INPUT_VDD) &&
+           (p_config->pin_p > NRF_SAADC_INPUT_DISABLED));
+    ASSERT(p_config->pin_n <= NRF_SAADC_INPUT_VDD);
+
+    ret_code_t err_code;
+
+    // A channel can only be initialized if the driver is in the idle state.
+    if (m_cb.adc_state != NRF_SAADC_STATE_IDLE)
+    {
+        err_code = NRF_ERROR_BUSY;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", 
+                        (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    if (!m_cb.psel[channel].pselp)
+    {
+        ++m_cb.active_channels;
+    }
+    m_cb.psel[channel].pselp = p_config->pin_p;
+    m_cb.psel[channel].pseln = p_config->pin_n;
+    nrf_saadc_channel_init(channel, p_config);
+    nrf_saadc_channel_input_set(channel, p_config->pin_p, p_config->pin_n);
+    NRF_LOG_INFO("Channel initialized: %d.\r\n", channel);
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+ret_code_t nrf_drv_saadc_channel_uninit(uint8_t channel)
+{
+    ASSERT(channel < NRF_SAADC_CHANNEL_COUNT)
+    ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
+
+    ret_code_t err_code;
+
+    // A channel can only be uninitialized if the driver is in the idle state.
+    if (m_cb.adc_state != NRF_SAADC_STATE_IDLE)
+    {
+        err_code = NRF_ERROR_BUSY;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", 
+                        (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    if (m_cb.psel[channel].pselp)
+    {
+        --m_cb.active_channels;
+    }
+    m_cb.psel[channel].pselp = NRF_SAADC_INPUT_DISABLED;
+    m_cb.psel[channel].pseln = NRF_SAADC_INPUT_DISABLED;
+    nrf_saadc_channel_input_set(channel, NRF_SAADC_INPUT_DISABLED, NRF_SAADC_INPUT_DISABLED);
+    nrf_drv_saadc_limits_set(channel, NRF_DRV_SAADC_LIMITL_DISABLED, NRF_DRV_SAADC_LIMITH_DISABLED);
+    NRF_LOG_INFO("Channel denitialized: %d.\r\n", channel);
+
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", 
+                    (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+uint32_t nrf_drv_saadc_sample_task_get(void)
+{
+    return nrf_saadc_task_address_get(
+        m_cb.low_power_mode ? NRF_SAADC_TASK_START : NRF_SAADC_TASK_SAMPLE);
+}
+
+
+ret_code_t nrf_drv_saadc_sample_convert(uint8_t channel, nrf_saadc_value_t * p_value)
+{
+    ret_code_t err_code;
+
+    if (m_cb.adc_state != NRF_SAADC_STATE_IDLE)
+    {
+        err_code = NRF_ERROR_BUSY;
+        NRF_LOG_WARNING("Function: %s error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+    m_cb.adc_state = NRF_SAADC_STATE_BUSY;
+    nrf_saadc_int_disable(NRF_SAADC_INT_STARTED | NRF_SAADC_INT_END);
+    nrf_saadc_buffer_init(p_value, 1);
+    if (m_cb.active_channels > 1)
+    {
+        for (uint8_t i = 0; i < NRF_SAADC_CHANNEL_COUNT; ++i)
+        {
+            nrf_saadc_channel_input_set(i, NRF_SAADC_INPUT_DISABLED, NRF_SAADC_INPUT_DISABLED);
+        }
+    }
+    nrf_saadc_channel_input_set(channel,
+                                m_cb.psel[channel].pselp, m_cb.psel[channel].pseln);
+    nrf_saadc_task_trigger(NRF_SAADC_TASK_START);
+    nrf_saadc_task_trigger(NRF_SAADC_TASK_SAMPLE);
+
+    uint32_t timeout = HW_TIMEOUT;
+
+    while (0 == nrf_saadc_event_check(NRF_SAADC_EVENT_END) && timeout > 0)
+    {
+        timeout--;
+    }
+    nrf_saadc_event_clear(NRF_SAADC_EVENT_END);
+
+    NRF_LOG_INFO("Conversion value: %d, channel.\r\n", *p_value, channel);
+
+    if (m_cb.active_channels > 1)
+    {
+        for (uint8_t i = 0; i < NRF_SAADC_CHANNEL_COUNT; ++i)
+        {
+            nrf_saadc_channel_input_set(i, m_cb.psel[i].pselp, m_cb.psel[i].pseln);
+        }
+    }
+
+    if (m_cb.low_power_mode)
+    {
+        nrf_saadc_int_enable(NRF_SAADC_INT_STARTED | NRF_SAADC_INT_END);
+    }
+    else
+    {
+        nrf_saadc_int_enable(NRF_SAADC_INT_END);
+    }
+
+    m_cb.adc_state = NRF_SAADC_STATE_IDLE;
+
+    err_code = NRF_SUCCESS;
+    NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+ret_code_t nrf_drv_saadc_buffer_convert(nrf_saadc_value_t * p_buffer, uint16_t size)
+{
+    ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
+    ASSERT((size % m_cb.active_channels) == 0);
+    ret_code_t err_code;    
+
+        
+    nrf_saadc_int_disable(NRF_SAADC_INT_END | NRF_SAADC_INT_CALIBRATEDONE);
+    if (m_cb.adc_state == NRF_SAADC_STATE_CALIBRATION)
+    {
+        nrf_saadc_int_enable(NRF_SAADC_INT_END | NRF_SAADC_INT_CALIBRATEDONE);
+        err_code = NRF_ERROR_BUSY;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+    if (m_cb.adc_state == NRF_SAADC_STATE_BUSY)
+    {
+        if ( m_cb.p_secondary_buffer)
+        {
+            nrf_saadc_int_enable(NRF_SAADC_INT_END);
+            err_code = NRF_ERROR_BUSY;
+            NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+            return err_code;
+        }
+        else
+        {
+            m_cb.p_secondary_buffer    = p_buffer;
+            m_cb.secondary_buffer_size = size;
+            if (!m_cb.low_power_mode)
+            {
+                while (nrf_saadc_event_check(NRF_SAADC_EVENT_STARTED) == 0);
+                nrf_saadc_event_clear(NRF_SAADC_EVENT_STARTED);
+                nrf_saadc_buffer_init(p_buffer, size);
+            }
+            nrf_saadc_int_enable(NRF_SAADC_INT_END);
+            err_code = NRF_SUCCESS;
+            NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+            return err_code;
+        }
+    }
+    nrf_saadc_int_enable(NRF_SAADC_INT_END);
+    m_cb.adc_state = NRF_SAADC_STATE_BUSY;
+
+    m_cb.p_buffer           = p_buffer;
+    m_cb.buffer_size        = size;
+    m_cb.p_secondary_buffer = NULL;
+
+    NRF_LOG_INFO("Function: %d, buffer length: %d, active channels: %d.\r\n", 
+                    (uint32_t)__func__, size, m_cb.active_channels);
+
+    if (m_cb.low_power_mode)
+    {
+        m_cb.buffer_size_left = size;
+        nrf_saadc_buffer_init(p_buffer, m_cb.active_channels);
+    }
+    else
+    {
+        nrf_saadc_buffer_init(p_buffer, size);
+        nrf_saadc_event_clear(NRF_SAADC_EVENT_STARTED);
+        nrf_saadc_task_trigger(NRF_SAADC_TASK_START);
+    }
+
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+ret_code_t nrf_drv_saadc_sample()
+{
+    ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
+
+    ret_code_t err_code = NRF_SUCCESS;
+    if (m_cb.adc_state != NRF_SAADC_STATE_BUSY)
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+    }
+    else if (m_cb.low_power_mode)
+    {
+        nrf_saadc_task_trigger(NRF_SAADC_TASK_START);
+    }
+    else
+    {
+        nrf_saadc_task_trigger(NRF_SAADC_TASK_SAMPLE);
+    }
+
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+ret_code_t nrf_drv_saadc_calibrate_offset()
+{
+    ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
+
+    ret_code_t err_code;
+
+    if (m_cb.adc_state != NRF_SAADC_STATE_IDLE)
+    {
+        err_code = NRF_ERROR_BUSY;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    m_cb.adc_state = NRF_SAADC_STATE_CALIBRATION;
+
+    nrf_saadc_event_clear(NRF_SAADC_EVENT_CALIBRATEDONE);
+    nrf_saadc_int_enable(NRF_SAADC_EVENT_CALIBRATEDONE);
+    nrf_saadc_task_trigger(NRF_SAADC_TASK_CALIBRATEOFFSET);
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+bool nrf_drv_saadc_is_busy(void)
+{
+    return (m_cb.adc_state != NRF_SAADC_STATE_IDLE);
+}
+
+
+void nrf_drv_saadc_abort(void)
+{
+    if (nrf_drv_saadc_is_busy())
+    {
+        nrf_saadc_event_clear(NRF_SAADC_EVENT_STOPPED);
+        nrf_saadc_task_trigger(NRF_SAADC_TASK_STOP);
+
+        if (m_cb.adc_state == NRF_SAADC_STATE_CALIBRATION)
+        {
+            m_cb.adc_state = NRF_SAADC_STATE_IDLE;
+        }
+        else
+        {
+            // Wait for ADC being stopped.
+            uint32_t timeout = HW_TIMEOUT;
+
+            while ((m_cb.adc_state != NRF_SAADC_STATE_IDLE) && (timeout > 0))
+            {
+                --timeout;
+            }
+            ASSERT(timeout > 0);
+        }
+
+        m_cb.p_buffer           = 0;
+        m_cb.p_secondary_buffer = 0;
+        NRF_LOG_INFO("Conversion aborted.\r\n");
+    }
+}
+
+
+void nrf_drv_saadc_limits_set(uint8_t channel, int16_t limit_low, int16_t limit_high)
+{
+    ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
+    ASSERT(m_cb.event_handler); // only non blocking mode supported
+    ASSERT(limit_low >= NRF_DRV_SAADC_LIMITL_DISABLED);
+    ASSERT(limit_high <= NRF_DRV_SAADC_LIMITH_DISABLED);
+    ASSERT(limit_low < limit_high);
+    nrf_saadc_channel_limits_set(channel, limit_low, limit_high);
+
+    uint32_t int_mask = nrf_saadc_limit_int_get(channel, NRF_SAADC_LIMIT_LOW);
+    if (limit_low == NRF_DRV_SAADC_LIMITL_DISABLED)
+    {
+        m_cb.limits_enabled_flags &= ~(0x80000000 >> LOW_LIMIT_TO_FLAG(channel));
+        nrf_saadc_int_disable(int_mask);
+    }
+    else
+    {
+        m_cb.limits_enabled_flags |= (0x80000000 >> LOW_LIMIT_TO_FLAG(channel));
+        nrf_saadc_int_enable(int_mask);
+    }
+
+    int_mask = nrf_saadc_limit_int_get(channel, NRF_SAADC_LIMIT_HIGH);
+    if (limit_high == NRF_DRV_SAADC_LIMITH_DISABLED)
+    {
+        m_cb.limits_enabled_flags &= ~(0x80000000 >> HIGH_LIMIT_TO_FLAG(channel));
+        nrf_saadc_int_disable(int_mask);
+    }
+    else
+    {
+        m_cb.limits_enabled_flags |= (0x80000000 >> HIGH_LIMIT_TO_FLAG(channel));
+        nrf_saadc_int_enable(int_mask);
+    }
+}
+#endif //NRF_MODULE_ENABLED(SAADC)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/saadc/nrf_drv_saadc.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,325 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @addtogroup nrf_saadc SAADC HAL and driver
+ * @ingroup    nrf_drivers
+ * @brief      @tagAPI52 Successive Approximation Analog-to-Digital Converter (SAADC) APIs.
+ * @details The SAADC HAL provides basic APIs for accessing the registers of the SAADC peripheral.
+ * The SAADC driver provides APIs on a higher level.
+ *
+ * @defgroup nrf_drv_saadc SAADC driver
+ * @{
+ * @ingroup  nrf_saadc
+ *
+ * @brief    @tagAPI52 Successive Approximation Analog-to-Digital Converter (SAADC) driver.
+ */
+
+#ifndef NRF_DRV_SAADC_H__
+#define NRF_DRV_SAADC_H__
+
+#include "sdk_config.h"
+#include "nrf_saadc.h"
+#include "sdk_errors.h"
+#include "nrf_drv_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Value that should be set as high limit to disable limit detection.
+ */
+#define NRF_DRV_SAADC_LIMITH_DISABLED (2047)
+/**
+ * @brief Value that should be set as low limit to disable limit detection.
+ */
+#define NRF_DRV_SAADC_LIMITL_DISABLED (-2048)
+
+/**
+ * @brief Macro for setting @ref nrf_drv_saadc_config_t to default settings.
+ */
+#define NRF_DRV_SAADC_DEFAULT_CONFIG                                        \
+    {                                                                       \
+    .resolution         = (nrf_saadc_resolution_t)SAADC_CONFIG_RESOLUTION,  \
+    .oversample         = (nrf_saadc_oversample_t)SAADC_CONFIG_OVERSAMPLE,  \
+    .interrupt_priority = SAADC_CONFIG_IRQ_PRIORITY,                        \
+    .low_power_mode     = SAADC_CONFIG_LP_MODE                              \
+    }
+
+/**
+ * @brief Macro for setting @ref nrf_saadc_channel_config_t to default settings
+ *        in single ended mode.
+ *
+ * @param PIN_P Analog input.
+ */
+#define NRF_DRV_SAADC_DEFAULT_CHANNEL_CONFIG_SE(PIN_P) \
+    {                                                  \
+        .resistor_p = NRF_SAADC_RESISTOR_DISABLED,     \
+        .resistor_n = NRF_SAADC_RESISTOR_DISABLED,     \
+        .gain       = NRF_SAADC_GAIN1_6,               \
+        .reference  = NRF_SAADC_REFERENCE_INTERNAL,    \
+        .acq_time   = NRF_SAADC_ACQTIME_10US,          \
+        .mode       = NRF_SAADC_MODE_SINGLE_ENDED,     \
+        .burst      = NRF_SAADC_BURST_DISABLED,        \
+        .pin_p      = (nrf_saadc_input_t)(PIN_P),      \
+        .pin_n      = NRF_SAADC_INPUT_DISABLED         \
+    }
+
+/**
+ * @brief Macro for setting @ref nrf_saadc_channel_config_t to default settings
+ *        in differential mode.
+ *
+ * @param PIN_P Positive analog input.
+ * @param PIN_N Negative analog input.
+ */
+#define NRF_DRV_SAADC_DEFAULT_CHANNEL_CONFIG_DIFFERENTIAL(PIN_P, PIN_N) \
+    {                                                                   \
+        .resistor_p = NRF_SAADC_RESISTOR_DISABLED,                      \
+        .resistor_n = NRF_SAADC_RESISTOR_DISABLED,                      \
+        .gain       = NRF_SAADC_GAIN1_6,                                \
+        .reference  = NRF_SAADC_REFERENCE_INTERNAL,                     \
+        .acq_time   = NRF_SAADC_ACQTIME_10US,                           \
+        .mode       = NRF_SAADC_MODE_DIFFERENTIAL,                      \
+        .pin_p      = (nrf_saadc_input_t)(PIN_P),                       \
+        .pin_n      = (nrf_saadc_input_t)(PIN_N)                        \
+    }
+
+/**
+ * @brief Analog-to-digital converter driver configuration structure.
+ */
+typedef struct
+{
+    nrf_saadc_resolution_t resolution;         ///< Resolution configuration.
+    nrf_saadc_oversample_t oversample;         ///< Oversampling configuration.
+    uint8_t                interrupt_priority; ///< Interrupt priority.
+    bool                   low_power_mode;     ///< Indicates if low power mode is active.
+} nrf_drv_saadc_config_t;
+
+/**
+ * @brief Driver event types.
+ */
+typedef enum
+{
+    NRF_DRV_SAADC_EVT_DONE,         ///< Event generated when the buffer is filled with samples.
+    NRF_DRV_SAADC_EVT_LIMIT,        ///< Event generated after one of the limits is reached.
+    NRF_DRV_SAADC_EVT_CALIBRATEDONE ///< Event generated when the calibration is complete.
+} nrf_drv_saadc_evt_type_t;
+
+/**
+ * @brief Analog-to-digital converter driver done event data.
+ */
+typedef struct
+{
+    nrf_saadc_value_t * p_buffer; ///< Pointer to buffer with converted samples.
+    uint16_t            size;     ///< Number of samples in the buffer.
+} nrf_drv_saadc_done_evt_t;
+
+/**
+ * @brief Analog-to-digital converter driver limit event data.
+ */
+typedef struct
+{
+    uint8_t           channel;    ///< Channel on which the limit was detected.
+    nrf_saadc_limit_t limit_type; ///< Type of limit detected.
+} nrf_drv_saadc_limit_evt_t;
+
+/**
+ * @brief Analog-to-digital converter driver event structure.
+ */
+typedef struct
+{
+    nrf_drv_saadc_evt_type_t type; ///< Event type.
+    union
+    {
+        nrf_drv_saadc_done_evt_t  done;  ///< Data for @ref NRF_DRV_SAADC_EVT_DONE event.
+        nrf_drv_saadc_limit_evt_t limit; ///< Data for @ref NRF_DRV_SAADC_EVT_LIMIT event.
+    } data;
+} nrf_drv_saadc_evt_t;
+
+/**
+ * @brief ADC event handler.
+ *
+ * @param[in] p_event     Pointer to an ADC event. The event structure is allocated on
+ *                        the stack, so it is valid only within the context of
+ *                        the event handler.
+ */
+typedef void (* nrf_drv_saadc_event_handler_t)(nrf_drv_saadc_evt_t const * p_event);
+
+/**
+ * @brief Function for initializing the SAADC.
+ *
+ * @param[in] p_config      Pointer to a configuration structure. If NULL, the default one is used.
+ * @param[in] event_handler Event handler provided by the user.
+ *
+ * @retval    NRF_SUCCESS If initialization was successful.
+ * @retval    NRF_ERROR_INVALID_STATE If the driver is already initialized.
+ * @retval    NRF_ERROR_INVALID_PARAM If event_handler is NULL.
+ */
+ret_code_t nrf_drv_saadc_init(nrf_drv_saadc_config_t const * p_config,
+                              nrf_drv_saadc_event_handler_t  event_handler);
+
+/**
+ * @brief Function for uninitializing the SAADC.
+ *
+ * This function stops all ongoing conversions and disables all channels.
+ */
+void nrf_drv_saadc_uninit(void);
+
+
+/**
+ * @brief Function for getting the address of a SAMPLE SAADC task.
+ *
+ * @return     Task address.
+ */
+uint32_t nrf_drv_saadc_sample_task_get(void);
+
+/**
+ * @brief Function for initializing an SAADC channel.
+ *
+ * This function configures and enables the channel.
+ *
+ * @retval NRF_SUCCESS             If initialization was successful.
+ * @retval NRF_ERROR_INVALID_STATE If the ADC was not initialized.
+ * @retval NRF_ERROR_NO_MEM        If the specified channel was already allocated.
+ */
+ret_code_t nrf_drv_saadc_channel_init(uint8_t                                  channel,
+                                      nrf_saadc_channel_config_t const * const p_config);
+
+
+/**
+ * @brief Function for uninitializing an SAADC channel.
+ *
+ * @retval NRF_SUCCESS    If uninitialization was successful.
+ * @retval NRF_ERROR_BUSY If the ADC is busy.
+ */
+ret_code_t nrf_drv_saadc_channel_uninit(uint8_t channel);
+
+/**
+ * @brief Function for starting SAADC sampling.
+ *
+ * @retval NRF_SUCCESS             If ADC sampling was triggered.
+ * @retval NRF_ERROR_INVALID_STATE If ADC is in idle state.
+ */
+ret_code_t nrf_drv_saadc_sample(void);
+
+/**
+ * @brief Blocking function for executing a single ADC conversion.
+ *
+ * This function selects the desired input, starts a single conversion,
+ * waits for it to finish, and returns the result.
+ *
+ * The function will fail if ADC is busy.
+ *
+ * @param[in]  channel Channel.
+ * @param[out] p_value Pointer to the location where the result should be placed.
+ *
+ * @retval NRF_SUCCESS    If conversion was successful.
+ * @retval NRF_ERROR_BUSY If the ADC driver is busy.
+ */
+ret_code_t nrf_drv_saadc_sample_convert(uint8_t channel, nrf_saadc_value_t * p_value);
+
+/**
+ * @brief Function for issuing conversion of data to the buffer.
+ *
+ * This function is non-blocking. The application is notified about filling the buffer by the event handler.
+ * Conversion will be done on all enabled channels. If the ADC is in idle state, the function will set up Easy
+ * DMA for the conversion. The ADC will be ready for sampling and wait for the SAMPLE task. It can be
+ * triggered manually by the @ref nrf_drv_saadc_sample function or by PPI using the @ref NRF_SAADC_TASK_SAMPLE
+ * task. If one buffer is already set and the conversion is ongoing, calling this function will
+ * result in queuing the given buffer. The driver will start filling the issued buffer when the first one is
+ * completed. If the function is called again before the first buffer is filled or calibration is in progress,
+ * it will return with error.
+ *
+ * @param[in] buffer Result buffer.
+ * @param[in] size   Buffer size in words.
+ *
+ * @retval NRF_SUCCESS    If conversion was successful.
+ * @retval NRF_ERROR_BUSY If the driver already has two buffers set or calibration is in progress.
+ */
+ret_code_t nrf_drv_saadc_buffer_convert(nrf_saadc_value_t * buffer, uint16_t size);
+
+/**
+ * @brief Function for triggering the ADC offset calibration.
+ *
+ * This function is non-blocking. The application is notified about completion by the event handler.
+ * Calibration will also trigger DONE and RESULTDONE events.
+ *
+ * The function will fail if ADC is busy or calibration is already in progress.
+ *
+ * @retval NRF_SUCCESS    If calibration was started successfully.
+ * @retval NRF_ERROR_BUSY If the ADC driver is busy.
+ */
+ret_code_t nrf_drv_saadc_calibrate_offset(void);
+
+/**
+ * @brief Function for retrieving the SAADC state.
+ *
+ * @retval true  If the ADC is busy.
+ * @retval false If the ADC is ready.
+ */
+bool nrf_drv_saadc_is_busy(void);
+
+/**
+ * @brief Function for aborting ongoing and buffered conversions.
+ * @note @ref NRF_DRV_SAADC_EVT_DONE event will be generated if there is a conversion in progress.
+ *       Event will contain number of words in the sample buffer.
+ */
+void nrf_drv_saadc_abort(void);
+
+/**
+ * @brief Function for setting the SAADC channel limits.
+ *        When limits are enabled and the result exceeds the defined bounds, the limit handler function is called.
+ *
+ * @param[in] channel SAADC channel number.
+ * @param[in] limit_low Lower limit (valid values from @ref NRF_DRV_SAADC_LIMITL_DISABLED to
+ *            @ref NRF_DRV_SAADC_LIMITH_DISABLED). Conversion results below this value will trigger
+ *            the handler function. Set to @ref NRF_DRV_SAADC_LIMITL_DISABLED to disable this limit.
+ * @param[in] limit_high Upper limit (valid values from @ref NRF_DRV_SAADC_LIMITL_DISABLED to
+ *            @ref NRF_DRV_SAADC_LIMITH_DISABLED). Conversion results above this value will trigger
+ *            the handler function. Set to @ref NRF_DRV_SAADC_LIMITH_DISABLED to disable this limit.
+ */
+void nrf_drv_saadc_limits_set(uint8_t channel, int16_t limit_low, int16_t limit_high);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_DRV_SAADC_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/sdio/config/sdio_config.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,53 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef SDIO_CONFIG_H
+#define SDIO_CONFIG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SDIO_CONFIG_CLOCK_PIN_NUMBER 24
+#define SDIO_CONFIG_DATA_PIN_NUMBER 25
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/sdio/sdio.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,243 @@
+/* 
+ * Copyright (c) 2009 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include <stdint.h>
+
+#include "nrf.h"
+#include "nrf_delay.h"
+#include "sdio.h"
+#include "nrf_gpio.h"
+
+#include "sdio_config.h"
+
+/*lint ++flb "Enter library region" */
+
+/*lint -e717 -save "Suppress do {} while (0) for these macros" */
+#define SDIO_CLOCK_HIGH()   do { NRF_GPIO->OUTSET = (1UL << SDIO_CONFIG_CLOCK_PIN_NUMBER); } while (0) /*!< Pulls SCL line high */
+#define SDIO_CLOCK_LOW()    do { NRF_GPIO->OUTCLR = (1UL << SDIO_CONFIG_CLOCK_PIN_NUMBER); } while (0) /*!< Pulls SCL line low */
+#define SDIO_DATA_HIGH()    do { NRF_GPIO->OUTSET = (1UL << SDIO_CONFIG_DATA_PIN_NUMBER); } while (0)  /*!< Pulls SDA line high */
+#define SDIO_DATA_LOW()     do { NRF_GPIO->OUTCLR = (1UL << SDIO_CONFIG_DATA_PIN_NUMBER); } while (0)  /*!< Pulls SDA line low */
+#define SDIO_DATA_OUTPUT()  do { NRF_GPIO->DIRSET = (1UL << SDIO_CONFIG_DATA_PIN_NUMBER); } while (0)  /*!< Configures SDA pin as output */
+#define SDIO_CLOCK_OUTPUT() do { NRF_GPIO->DIRSET = (1UL << SDIO_CONFIG_CLOCK_PIN_NUMBER); } while (0) /*!< Configures SCL pin as output */
+/*lint -restore */
+
+/*lint -emacro(845,SDIO_DATA_INPUT) // A zero has been given as right argument to operator '|'" */
+
+#define SDIO_DATA_INPUT() do {                       \
+        nrf_gpio_cfg_input(25, NRF_GPIO_PIN_NOPULL); \
+} while (0)
+
+#define SDIO_DATA_READ()  ((NRF_GPIO->IN >> SDIO_CONFIG_DATA_PIN_NUMBER) & 0x1UL)  /*!< Reads current state of SDA */
+#define SDIO_CLOCK_READ() ((NRF_GPIO->IN >> SDIO_CONFIG_CLOCK_PIN_NUMBER) & 0x1UL) /*!< Reads current state of SCL */
+#define SDIO_DELAY()      nrf_delay_us(10)                                         /*!< Time to wait when pin states are changed. For fast-mode the delay can be zero and for standard-mode 4 us delay is sufficient. */
+
+void sdio_init(void)
+{
+    SDIO_CLOCK_HIGH();
+    SDIO_DATA_HIGH();
+    SDIO_CLOCK_OUTPUT();
+    SDIO_DATA_INPUT();
+
+    // If slave is stuck in the middle of transfer, clock out bits until the slave ACKs the transfer
+    for (uint_fast8_t i = 16; i--;)
+    {
+        SDIO_DELAY();
+        SDIO_CLOCK_LOW();
+        SDIO_DELAY();
+        SDIO_CLOCK_HIGH();
+        SDIO_DELAY();
+
+        if (SDIO_DATA_READ())
+        {
+            break;
+        }
+    }
+
+    for (uint_fast8_t i = 5; i--;)
+    {
+        SDIO_DELAY();
+        SDIO_CLOCK_LOW();
+        SDIO_DELAY();
+        SDIO_CLOCK_HIGH();
+    }
+
+    SDIO_DATA_OUTPUT();
+    SDIO_DATA_HIGH();
+
+    SDIO_DELAY();
+}
+
+uint8_t sdio_read_byte(uint8_t address)
+{
+    uint8_t data_byte = 0;
+
+    SDIO_DATA_OUTPUT();
+
+    for (uint_fast8_t i = 8; i--;)
+    {
+        SDIO_DELAY();
+
+        SDIO_CLOCK_LOW();
+
+        if (address & (1U << i))
+        {
+            SDIO_DATA_HIGH();
+        }
+        else
+        {
+            SDIO_DATA_LOW();
+        }
+
+        SDIO_DELAY();
+
+        SDIO_CLOCK_HIGH();
+    }
+
+    nrf_delay_us(20);
+
+    SDIO_DATA_INPUT();
+
+    for (uint_fast8_t i = 8; i--;)
+    {
+        SDIO_CLOCK_LOW();
+        SDIO_DELAY();
+        SDIO_CLOCK_HIGH();
+        SDIO_DELAY();
+        data_byte |= (uint8_t)(SDIO_DATA_READ() << i);
+    }
+
+    SDIO_DATA_HIGH();
+    SDIO_DATA_OUTPUT();
+
+    SDIO_DELAY();
+
+    return data_byte;
+}
+
+void sdio_read_burst(uint8_t * target_buffer, uint8_t target_buffer_size)
+{
+    uint_fast8_t address = 0x63;
+
+    SDIO_DATA_OUTPUT();
+
+    for (uint_fast8_t bit_index=8; bit_index--;)
+    {
+        SDIO_CLOCK_LOW();
+
+        if (address & (1U << bit_index))
+        {
+            SDIO_DATA_HIGH();
+        }
+        else
+        {
+            SDIO_DATA_LOW();
+        }
+
+        SDIO_CLOCK_HIGH();
+    }
+
+    SDIO_DATA_INPUT();
+
+    for (uint_fast8_t target_buffer_index = 0; target_buffer_index < target_buffer_size; target_buffer_index++)
+    {
+        target_buffer[target_buffer_index] = 0;
+
+        for (uint_fast8_t bit_index = 8; bit_index--;)
+        {
+            SDIO_CLOCK_LOW();
+            SDIO_CLOCK_HIGH();
+            target_buffer[target_buffer_index] |= (uint8_t)(SDIO_DATA_READ() << bit_index);
+        }
+    }
+}
+
+void sdio_write_byte(uint8_t address, uint8_t data_byte)
+{
+    // Add write indication bit
+    address |= 0x80;
+
+    SDIO_DATA_OUTPUT();
+
+    for (uint_fast8_t i = 8; i--;)
+    {
+        SDIO_DELAY();
+
+        SDIO_CLOCK_LOW();
+
+        if (address & (1U << i))
+        {
+            SDIO_DATA_HIGH();
+        }
+        else
+        {
+            SDIO_DATA_LOW();
+        }
+
+        SDIO_DELAY();
+
+        SDIO_CLOCK_HIGH();
+    }
+
+    SDIO_DELAY();
+
+    for (uint_fast8_t i = 8; i--;)
+    {
+        SDIO_CLOCK_LOW();
+
+        if (data_byte & (1U << i))
+        {
+            SDIO_DATA_HIGH();
+        }
+        else
+        {
+            SDIO_DATA_LOW();
+        }
+
+        SDIO_DELAY();
+
+        SDIO_CLOCK_HIGH();
+
+        SDIO_DELAY();
+    }
+
+    SDIO_DATA_HIGH();
+
+    SDIO_DELAY();
+}
+
+/*lint --flb "Leave library region" */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/sdio/sdio.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,104 @@
+ /* 
+ * Copyright (c) 2009 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef SDIO_H
+#define SDIO_H
+
+/*lint ++flb "Enter library region" */
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @file
+* @brief 2-wire serial interface driver (compatible with ADNS2080 mouse sensor driver)
+*
+*
+* @defgroup nrf_drivers_sdio SDIO driver
+* @{
+* @ingroup nrf_drivers
+* @brief 2-wire serial interface driver.
+*/
+
+/**
+ * @brief Function for initializing 2-wire serial interface and trying to handle stuck slaves.
+ *
+ */
+void sdio_init(void);
+
+/**
+ * @brief Function for reading a byte over 2-wire serial interface.
+ *
+ * Developer needs to implement this function in a way that suits the hardware.
+ * @param address Register address to read from
+ * @return Byte read
+ */
+uint8_t sdio_read_byte(uint8_t address);
+
+/**
+ * @brief Function for reading several bytes over 2-wire serial interface using burst mode.
+ *
+ * Developer needs to implement this function in a way that suits the hardware.
+ * @param target_buffer Buffer location to store read bytes to
+ * @param target_buffer_size Bytes allocated for target_buffer
+ */
+void sdio_read_burst(uint8_t *target_buffer, uint8_t target_buffer_size);
+
+/**
+ * @brief Function for writing a byte over 2-wire serial interface.
+ *
+ * Developer needs to implement this function in a way that suits the hardware.
+ * @param address Register address to write to
+ * @param data_byte Data byte to write
+ */
+void sdio_write_byte(uint8_t address, uint8_t data_byte);
+
+/**
+ *@}
+ **/
+
+/*lint --flb "Leave library region" */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/spi_master/nrf_drv_spi.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,717 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(SPI)
+#define ENABLED_SPI_COUNT (SPI0_ENABLED+SPI1_ENABLED+SPI2_ENABLED)
+#if ENABLED_SPI_COUNT
+
+#include "nrf_drv_spi.h"
+#include "nrf_drv_common.h"
+#include "nrf_gpio.h"
+#include "nrf_assert.h"
+#include "app_util_platform.h"
+
+#define NRF_LOG_MODULE_NAME "SPI"
+
+#if SPI_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       SPI_CONFIG_LOG_LEVEL
+#define NRF_LOG_INFO_COLOR  SPI_CONFIG_INFO_COLOR
+#define NRF_LOG_DEBUG_COLOR SPI_CONFIG_DEBUG_COLOR
+#else //SPI_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       0
+#endif //SPI_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+
+#ifndef SPIM_PRESENT
+    // Make sure SPIx_USE_EASY_DMA is 0 for nRF51 (if a common
+    // "nrf_drv_config.h" file is provided for nRF51 and nRF52).
+    #undef  SPI0_USE_EASY_DMA
+    #define SPI0_USE_EASY_DMA 0
+    #undef  SPI1_USE_EASY_DMA
+    #define SPI1_USE_EASY_DMA 0
+    #undef  SPI2_USE_EASY_DMA
+    #define SPI2_USE_EASY_DMA 0
+#endif
+
+#ifndef SPI0_USE_EASY_DMA
+#define SPI0_USE_EASY_DMA 0
+#endif
+
+#ifndef SPI1_USE_EASY_DMA
+#define SPI1_USE_EASY_DMA 0
+#endif
+
+#ifndef SPI2_USE_EASY_DMA
+#define SPI2_USE_EASY_DMA 0
+#endif
+
+// This set of macros makes it possible to exclude parts of code when one type
+// of supported peripherals is not used.
+#if ((NRF_MODULE_ENABLED(SPI0) && SPI0_USE_EASY_DMA) || \
+     (NRF_MODULE_ENABLED(SPI1) && SPI1_USE_EASY_DMA) || \
+     (NRF_MODULE_ENABLED(SPI2) && SPI2_USE_EASY_DMA))
+    #define SPIM_IN_USE
+#endif
+#if ((NRF_MODULE_ENABLED(SPI0) && !SPI0_USE_EASY_DMA) || \
+     (NRF_MODULE_ENABLED(SPI1) && !SPI1_USE_EASY_DMA) || \
+     (NRF_MODULE_ENABLED(SPI2) && !SPI2_USE_EASY_DMA))
+    #define SPI_IN_USE
+#endif
+#if defined(SPIM_IN_USE) && defined(SPI_IN_USE)
+    // SPIM and SPI combined
+    #define CODE_FOR_SPIM(code) if (p_instance->use_easy_dma) { code }
+    #define CODE_FOR_SPI(code)  else { code }
+#elif defined(SPIM_IN_USE) && !defined(SPI_IN_USE)
+    // SPIM only
+    #define CODE_FOR_SPIM(code) { code }
+    #define CODE_FOR_SPI(code)
+#elif !defined(SPIM_IN_USE) && defined(SPI_IN_USE)
+    // SPI only
+    #define CODE_FOR_SPIM(code)
+    #define CODE_FOR_SPI(code)  { code }
+#else
+    #error "Wrong configuration."
+#endif
+
+#ifdef SPIM_IN_USE
+#define END_INT_MASK     NRF_SPIM_INT_END_MASK
+#endif
+
+// Control block - driver instance local data.
+typedef struct
+{
+    nrf_drv_spi_handler_t handler;
+    nrf_drv_spi_evt_t     evt;  // Keep the struct that is ready for event handler. Less memcpy.
+    nrf_drv_state_t       state;
+    volatile bool         transfer_in_progress;
+
+    // [no need for 'volatile' attribute for the following members, as they
+    //  are not concurrently used in IRQ handlers and main line code]
+    uint8_t         ss_pin;
+    uint8_t         orc;
+    uint8_t         bytes_transferred;
+
+    bool tx_done : 1;
+    bool rx_done : 1;
+    bool abort   : 1;
+} spi_control_block_t;
+static spi_control_block_t m_cb[ENABLED_SPI_COUNT];
+
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+    #define IRQ_HANDLER_NAME(n) irq_handler_for_instance_##n
+    #define IRQ_HANDLER(n)      static void IRQ_HANDLER_NAME(n)(void)
+
+    #if NRF_MODULE_ENABLED(SPI0)
+        IRQ_HANDLER(0);
+    #endif
+    #if NRF_MODULE_ENABLED(SPI1)
+        IRQ_HANDLER(1);
+    #endif
+    #if NRF_MODULE_ENABLED(SPI2)
+        IRQ_HANDLER(2);
+    #endif
+    static nrf_drv_irq_handler_t const m_irq_handlers[ENABLED_SPI_COUNT] = {
+    #if NRF_MODULE_ENABLED(SPI0)
+        IRQ_HANDLER_NAME(0),
+    #endif
+    #if NRF_MODULE_ENABLED(SPI1)
+        IRQ_HANDLER_NAME(1),
+    #endif
+    #if NRF_MODULE_ENABLED(SPI2)
+        IRQ_HANDLER_NAME(2),
+    #endif
+    };
+#else
+    #define IRQ_HANDLER(n) void SPI##n##_IRQ_HANDLER(void)
+#endif // NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+
+
+ret_code_t nrf_drv_spi_init(nrf_drv_spi_t const * const p_instance,
+                            nrf_drv_spi_config_t const * p_config,
+                            nrf_drv_spi_handler_t handler)
+{
+    ASSERT(p_config);
+    spi_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
+    ret_code_t err_code;
+    
+    if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+    if (nrf_drv_common_per_res_acquire(p_instance->p_registers,
+            m_irq_handlers[p_instance->drv_inst_idx]) != NRF_SUCCESS)
+    {
+        err_code = NRF_ERROR_BUSY;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+#endif
+
+    p_cb->handler = handler;
+
+    uint32_t mosi_pin;
+    uint32_t miso_pin;
+    // Configure pins used by the peripheral:
+    // - SCK - output with initial value corresponding with the SPI mode used:
+    //   0 - for modes 0 and 1 (CPOL = 0), 1 - for modes 2 and 3 (CPOL = 1);
+    //   according to the reference manual guidelines this pin and its input
+    //   buffer must always be connected for the SPI to work.
+    if (p_config->mode <= NRF_DRV_SPI_MODE_1)
+    {
+        nrf_gpio_pin_clear(p_config->sck_pin);
+    }
+    else
+    {
+        nrf_gpio_pin_set(p_config->sck_pin);
+    }
+    NRF_GPIO->PIN_CNF[p_config->sck_pin] =
+        (GPIO_PIN_CNF_DIR_Output        << GPIO_PIN_CNF_DIR_Pos)
+      | (GPIO_PIN_CNF_INPUT_Connect     << GPIO_PIN_CNF_INPUT_Pos)
+      | (GPIO_PIN_CNF_PULL_Disabled     << GPIO_PIN_CNF_PULL_Pos)
+      | (GPIO_PIN_CNF_DRIVE_S0S1        << GPIO_PIN_CNF_DRIVE_Pos)
+      | (GPIO_PIN_CNF_SENSE_Disabled    << GPIO_PIN_CNF_SENSE_Pos);
+    // - MOSI (optional) - output with initial value 0,
+    if (p_config->mosi_pin != NRF_DRV_SPI_PIN_NOT_USED)
+    {
+        mosi_pin = p_config->mosi_pin;
+        nrf_gpio_pin_clear(mosi_pin);
+        nrf_gpio_cfg_output(mosi_pin);
+    }
+    else
+    {
+        mosi_pin = NRF_SPI_PIN_NOT_CONNECTED;
+    }
+    // - MISO (optional) - input,
+    if (p_config->miso_pin != NRF_DRV_SPI_PIN_NOT_USED)
+    {
+        miso_pin = p_config->miso_pin;
+        nrf_gpio_cfg_input(miso_pin, NRF_GPIO_PIN_NOPULL);
+    }
+    else
+    {
+        miso_pin = NRF_SPI_PIN_NOT_CONNECTED;
+    }
+    // - Slave Select (optional) - output with initial value 1 (inactive).
+    if (p_config->ss_pin != NRF_DRV_SPI_PIN_NOT_USED)
+    {
+        nrf_gpio_pin_set(p_config->ss_pin);
+        nrf_gpio_cfg_output(p_config->ss_pin);
+    }
+    m_cb[p_instance->drv_inst_idx].ss_pin = p_config->ss_pin;
+
+    CODE_FOR_SPIM
+    (
+        NRF_SPIM_Type * p_spim = p_instance->p_registers;
+        nrf_spim_pins_set(p_spim, p_config->sck_pin, mosi_pin, miso_pin);
+        nrf_spim_frequency_set(p_spim,
+            (nrf_spim_frequency_t)p_config->frequency);
+        nrf_spim_configure(p_spim,
+            (nrf_spim_mode_t)p_config->mode,
+            (nrf_spim_bit_order_t)p_config->bit_order);
+
+        nrf_spim_orc_set(p_spim, p_config->orc);
+
+        if (p_cb->handler)
+        {
+            nrf_spim_int_enable(p_spim, END_INT_MASK);
+        }
+
+        nrf_spim_enable(p_spim);
+    )
+    CODE_FOR_SPI
+    (
+        NRF_SPI_Type * p_spi = p_instance->p_registers;
+        nrf_spi_pins_set(p_spi, p_config->sck_pin, mosi_pin, miso_pin);
+        nrf_spi_frequency_set(p_spi,
+            (nrf_spi_frequency_t)p_config->frequency);
+        nrf_spi_configure(p_spi,
+            (nrf_spi_mode_t)p_config->mode,
+            (nrf_spi_bit_order_t)p_config->bit_order);
+
+        m_cb[p_instance->drv_inst_idx].orc = p_config->orc;
+
+        if (p_cb->handler)
+        {
+            nrf_spi_int_enable(p_spi, NRF_SPI_INT_READY_MASK);
+        }
+
+        nrf_spi_enable(p_spi);
+    )
+
+    if (p_cb->handler)
+    {
+        nrf_drv_common_irq_enable(p_instance->irq, p_config->irq_priority);
+    }
+
+    p_cb->transfer_in_progress = false;
+    p_cb->state = NRF_DRV_STATE_INITIALIZED;
+
+    NRF_LOG_INFO("Init\r\n");
+    
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+void nrf_drv_spi_uninit(nrf_drv_spi_t const * const p_instance)
+{
+    spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+
+    if (p_cb->handler)
+    {
+        nrf_drv_common_irq_disable(p_instance->irq);
+    }
+
+    #define DISABLE_ALL  0xFFFFFFFF
+
+    CODE_FOR_SPIM
+    (
+        NRF_SPIM_Type * p_spim = p_instance->p_registers;
+        if (p_cb->handler)
+        {
+            nrf_spim_int_disable(p_spim, DISABLE_ALL);
+            if (p_cb->transfer_in_progress)
+            {
+                // Ensure that SPI is not performing any transfer.
+                nrf_spim_task_trigger(p_spim, NRF_SPIM_TASK_STOP);
+                while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_STOPPED)) {}
+                p_cb->transfer_in_progress = false;
+            }
+        }
+        nrf_spim_disable(p_spim);
+    )
+    CODE_FOR_SPI
+    (
+        NRF_SPI_Type * p_spi = p_instance->p_registers;
+        if (p_cb->handler)
+        {
+            nrf_spi_int_disable(p_spi, DISABLE_ALL);
+        }
+        nrf_spi_disable(p_spi);
+    )
+    #undef DISABLE_ALL
+
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+    nrf_drv_common_per_res_release(p_instance->p_registers);
+#endif
+
+    p_cb->state = NRF_DRV_STATE_UNINITIALIZED;
+}
+
+ret_code_t nrf_drv_spi_transfer(nrf_drv_spi_t const * const p_instance,
+                                uint8_t const * p_tx_buffer,
+                                uint8_t         tx_buffer_length,
+                                uint8_t       * p_rx_buffer,
+                                uint8_t         rx_buffer_length)
+{
+    nrf_drv_spi_xfer_desc_t xfer_desc;
+    xfer_desc.p_tx_buffer = p_tx_buffer;
+    xfer_desc.p_rx_buffer = p_rx_buffer;
+    xfer_desc.tx_length   = tx_buffer_length;
+    xfer_desc.rx_length   = rx_buffer_length;
+
+    NRF_LOG_INFO("Transfer tx_len:%d, rx_len:%d.\r\n", tx_buffer_length, rx_buffer_length);
+    NRF_LOG_DEBUG("Tx data:\r\n");
+    NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_tx_buffer, tx_buffer_length * sizeof(p_tx_buffer));
+    return nrf_drv_spi_xfer(p_instance, &xfer_desc, 0);
+}
+
+static void finish_transfer(spi_control_block_t * p_cb)
+{
+    // If Slave Select signal is used, this is the time to deactivate it.
+    if (p_cb->ss_pin != NRF_DRV_SPI_PIN_NOT_USED)
+    {
+        nrf_gpio_pin_set(p_cb->ss_pin);
+    }
+
+    // By clearing this flag before calling the handler we allow subsequent
+    // transfers to be started directly from the handler function.
+    p_cb->transfer_in_progress = false;
+    p_cb->evt.type = NRF_DRV_SPI_EVENT_DONE;
+    NRF_LOG_INFO("Transfer rx_len:%d.\r\n", p_cb->evt.data.done.rx_length);
+    NRF_LOG_DEBUG("Rx data:\r\n");
+    NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_cb->evt.data.done.p_rx_buffer, 
+                            p_cb->evt.data.done.rx_length * sizeof(p_cb->evt.data.done.p_rx_buffer));
+    p_cb->handler(&p_cb->evt);
+}
+
+#ifdef SPI_IN_USE
+// This function is called from IRQ handler or, in blocking mode, directly
+// from the 'nrf_drv_spi_transfer' function.
+// It returns true as long as the transfer should be continued, otherwise (when
+// there is nothing more to send/receive) it returns false.
+static bool transfer_byte(NRF_SPI_Type * p_spi, spi_control_block_t * p_cb)
+{
+    // Read the data byte received in this transfer and store it in RX buffer,
+    // if needed.
+    volatile uint8_t rx_data = nrf_spi_rxd_get(p_spi);
+    if (p_cb->bytes_transferred < p_cb->evt.data.done.rx_length)
+    {
+        p_cb->evt.data.done.p_rx_buffer[p_cb->bytes_transferred] = rx_data;
+    }
+
+    ++p_cb->bytes_transferred;
+
+    // Check if there are more bytes to send or receive and write proper data
+    // byte (next one from TX buffer or over-run character) to the TXD register
+    // when needed.
+    // NOTE - we've already used 'p_cb->bytes_transferred + 1' bytes from our
+    //        buffers, because we take advantage of double buffering of TXD
+    //        register (so in effect one byte is still being transmitted now);
+    //        see how the transfer is started in the 'nrf_drv_spi_transfer'
+    //        function.
+    uint16_t bytes_used = p_cb->bytes_transferred + 1;
+    
+    if (p_cb->abort)
+    {
+        if (bytes_used < p_cb->evt.data.done.tx_length)
+        {
+            p_cb->evt.data.done.tx_length = bytes_used;
+        }
+        if (bytes_used < p_cb->evt.data.done.rx_length)
+        {
+            p_cb->evt.data.done.rx_length = bytes_used;
+        }
+    }
+    
+    if (bytes_used < p_cb->evt.data.done.tx_length)
+    {
+        nrf_spi_txd_set(p_spi, p_cb->evt.data.done.p_tx_buffer[bytes_used]);
+        return true;
+    }
+    else if (bytes_used < p_cb->evt.data.done.rx_length)
+    {
+        nrf_spi_txd_set(p_spi, p_cb->orc);
+        return true;
+    }
+
+    return (p_cb->bytes_transferred < p_cb->evt.data.done.tx_length ||
+            p_cb->bytes_transferred < p_cb->evt.data.done.rx_length);
+}
+
+static void spi_xfer(NRF_SPI_Type                  * p_spi,
+                     spi_control_block_t           * p_cb,
+                     nrf_drv_spi_xfer_desc_t const * p_xfer_desc)
+{
+    p_cb->bytes_transferred = 0;
+    nrf_spi_int_disable(p_spi, NRF_SPI_INT_READY_MASK);
+
+    nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY);
+
+    // Start the transfer by writing some byte to the TXD register;
+    // if TX buffer is not empty, take the first byte from this buffer,
+    // otherwise - use over-run character.
+    nrf_spi_txd_set(p_spi,
+        (p_xfer_desc->tx_length > 0 ?  p_xfer_desc->p_tx_buffer[0] : p_cb->orc));
+
+    // TXD register is double buffered, so next byte to be transmitted can
+    // be written immediately, if needed, i.e. if TX or RX transfer is to
+    // be more that 1 byte long. Again - if there is something more in TX
+    // buffer send it, otherwise use over-run character.
+    if (p_xfer_desc->tx_length > 1)
+    {
+        nrf_spi_txd_set(p_spi, p_xfer_desc->p_tx_buffer[1]);
+    }
+    else if (p_xfer_desc->rx_length > 1)
+    {
+        nrf_spi_txd_set(p_spi, p_cb->orc);
+    }
+
+    // For blocking mode (user handler not provided) wait here for READY
+    // events (indicating that the byte from TXD register was transmitted
+    // and a new incoming byte was moved to the RXD register) and continue
+    // transaction until all requested bytes are transferred.
+    // In non-blocking mode - IRQ service routine will do this stuff.
+    if (p_cb->handler)
+    {
+        nrf_spi_int_enable(p_spi, NRF_SPI_INT_READY_MASK);
+    }
+    else
+    {
+        do {
+            while (!nrf_spi_event_check(p_spi, NRF_SPI_EVENT_READY)) {}
+            nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY);
+            NRF_LOG_DEBUG("SPI: Event: NRF_SPI_EVENT_READY.\r\n"); 
+        } while (transfer_byte(p_spi, p_cb));
+        if (p_cb->ss_pin != NRF_DRV_SPI_PIN_NOT_USED)
+        {
+            nrf_gpio_pin_set(p_cb->ss_pin);
+        }
+    }
+}
+#endif // SPI_IN_USE
+
+#ifdef SPIM_IN_USE
+__STATIC_INLINE void spim_int_enable(NRF_SPIM_Type * p_spim, bool enable)
+{
+    if (!enable)
+    {
+        nrf_spim_int_disable(p_spim, END_INT_MASK);
+    }
+    else
+    {
+        nrf_spim_int_enable(p_spim, END_INT_MASK);
+    }
+}
+
+__STATIC_INLINE void spim_list_enable_handle(NRF_SPIM_Type * p_spim, uint32_t flags)
+{
+    if (NRF_DRV_SPI_FLAG_TX_POSTINC & flags)
+    {
+        nrf_spim_tx_list_enable(p_spim);
+    }
+    else
+    {
+        nrf_spim_tx_list_disable(p_spim);
+    }
+
+    if (NRF_DRV_SPI_FLAG_RX_POSTINC & flags)
+    {
+        nrf_spim_rx_list_enable(p_spim);
+    }
+    else
+    {
+        nrf_spim_rx_list_disable(p_spim);
+    }
+}
+
+static ret_code_t spim_xfer(NRF_SPIM_Type                * p_spim,
+                           spi_control_block_t           * p_cb,
+                           nrf_drv_spi_xfer_desc_t const * p_xfer_desc,
+                           uint32_t                        flags)
+{
+    ret_code_t err_code;
+    // EasyDMA requires that transfer buffers are placed in Data RAM region;
+    // signal error if they are not.
+    if ((p_xfer_desc->p_tx_buffer != NULL && !nrf_drv_is_in_RAM(p_xfer_desc->p_tx_buffer)) ||
+        (p_xfer_desc->p_rx_buffer != NULL && !nrf_drv_is_in_RAM(p_xfer_desc->p_rx_buffer)))
+    {
+        p_cb->transfer_in_progress = false;
+        err_code = NRF_ERROR_INVALID_ADDR;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    nrf_spim_tx_buffer_set(p_spim, p_xfer_desc->p_tx_buffer, p_xfer_desc->tx_length);
+    nrf_spim_rx_buffer_set(p_spim, p_xfer_desc->p_rx_buffer, p_xfer_desc->rx_length);
+
+    nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_END);
+
+    spim_list_enable_handle(p_spim, flags);
+
+    if (!(flags & NRF_DRV_SPI_FLAG_HOLD_XFER))
+    {
+        nrf_spim_task_trigger(p_spim, NRF_SPIM_TASK_START);
+    }
+
+    if (!p_cb->handler)
+    {
+        while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END)){}
+        if (p_cb->ss_pin != NRF_DRV_SPI_PIN_NOT_USED)
+        {
+            nrf_gpio_pin_set(p_cb->ss_pin);
+        }
+    }
+        else
+        {
+            spim_int_enable(p_spim, !(flags & NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER));
+        }
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+#endif
+
+ret_code_t nrf_drv_spi_xfer(nrf_drv_spi_t     const * const p_instance,
+                            nrf_drv_spi_xfer_desc_t const * p_xfer_desc,
+                            uint32_t                        flags)
+{
+    spi_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+    ASSERT(p_xfer_desc->p_tx_buffer != NULL || p_xfer_desc->tx_length == 0);
+    ASSERT(p_xfer_desc->p_rx_buffer != NULL || p_xfer_desc->rx_length == 0);
+
+    ret_code_t err_code = NRF_SUCCESS;
+
+    if (p_cb->transfer_in_progress)
+    {
+        err_code = NRF_ERROR_BUSY;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+    else
+    {
+        if (p_cb->handler && !(flags & (NRF_DRV_SPI_FLAG_REPEATED_XFER | NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER)))
+        {
+            p_cb->transfer_in_progress = true;
+        }
+    }
+
+    p_cb->evt.data.done = *p_xfer_desc;
+    p_cb->tx_done = false;
+    p_cb->rx_done = false;
+    p_cb->abort   = false;
+
+    if (p_cb->ss_pin != NRF_DRV_SPI_PIN_NOT_USED)
+    {
+        nrf_gpio_pin_clear(p_cb->ss_pin);
+    }
+    CODE_FOR_SPIM
+    (
+        return spim_xfer(p_instance->p_registers, p_cb,  p_xfer_desc, flags);
+    )
+    CODE_FOR_SPI
+    (
+        if (flags)
+        {
+            p_cb->transfer_in_progress = false;
+            err_code = NRF_ERROR_NOT_SUPPORTED;
+        }
+        else
+        {
+            spi_xfer(p_instance->p_registers, p_cb, p_xfer_desc);
+        }
+        NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    )
+}
+
+// modification for mbed-os
+#if __MBED__
+void nrf_drv_spi_abort(nrf_drv_spi_t const * p_instance)
+{
+    spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+
+    CODE_FOR_SPIM
+    (
+        nrf_spim_task_trigger(p_instance->p_registers, NRF_SPIM_TASK_STOP);
+        while (!nrf_spim_event_check(p_instance->p_registers, NRF_SPIM_EVENT_STOPPED)) {}
+        p_cb->transfer_in_progress = false;
+    )
+    CODE_FOR_SPI
+    (
+        p_cb->abort = true;
+    )
+}
+#endif
+
+#ifdef SPIM_IN_USE
+static void irq_handler_spim(NRF_SPIM_Type * p_spim, spi_control_block_t * p_cb)
+{
+    ASSERT(p_cb->handler);
+
+    if (nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END))
+    {
+        nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_END);
+        NRF_LOG_DEBUG("SPIM: Event: NRF_SPIM_EVENT_END.\r\n");
+        finish_transfer(p_cb);
+    }
+}
+
+uint32_t nrf_drv_spi_start_task_get(nrf_drv_spi_t const * p_instance)
+{
+    NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_registers;
+    return nrf_spim_task_address_get(p_spim, NRF_SPIM_TASK_START);
+}
+
+uint32_t nrf_drv_spi_end_event_get(nrf_drv_spi_t const * p_instance)
+{
+    NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_registers;
+    return nrf_spim_event_address_get(p_spim, NRF_SPIM_EVENT_END);
+}
+#endif // SPIM_IN_USE
+
+#ifdef SPI_IN_USE
+static void irq_handler_spi(NRF_SPI_Type * p_spi, spi_control_block_t * p_cb)
+{
+    ASSERT(p_cb->handler);
+
+    nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY);
+    NRF_LOG_DEBUG("SPI: Event: NRF_SPI_EVENT_READY.\r\n"); 
+
+    if (!transfer_byte(p_spi, p_cb))
+    {
+        finish_transfer(p_cb);
+    }
+}
+#endif // SPI_IN_USE
+
+#if NRF_MODULE_ENABLED(SPI0)
+IRQ_HANDLER(0)
+{
+    spi_control_block_t * p_cb  = &m_cb[SPI0_INSTANCE_INDEX];
+    #if SPI0_USE_EASY_DMA
+        irq_handler_spim(NRF_SPIM0, p_cb);
+    #else
+        irq_handler_spi(NRF_SPI0, p_cb);
+    #endif
+}
+#endif // NRF_MODULE_ENABLED(SPI0)
+
+#if NRF_MODULE_ENABLED(SPI1)
+IRQ_HANDLER(1)
+{
+    spi_control_block_t * p_cb  = &m_cb[SPI1_INSTANCE_INDEX];
+    #if SPI1_USE_EASY_DMA
+        irq_handler_spim(NRF_SPIM1, p_cb);
+    #else
+        irq_handler_spi(NRF_SPI1, p_cb);
+    #endif
+}
+#endif // NRF_MODULE_ENABLED(SPI1)
+
+#if NRF_MODULE_ENABLED(SPI2)
+IRQ_HANDLER(2)
+{
+    spi_control_block_t * p_cb  = &m_cb[SPI2_INSTANCE_INDEX];
+    #if SPI2_USE_EASY_DMA
+        irq_handler_spim(NRF_SPIM2, p_cb);
+    #else
+        irq_handler_spi(NRF_SPI2, p_cb);
+    #endif
+}
+#endif // NRF_MODULE_ENABLED(SPI2)
+#endif // ENABLED_SPI_COUNT
+#endif // NRF_MODULE_ENABLED(SPI)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/spi_master/nrf_drv_spi.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,411 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**@file
+ * @addtogroup nrf_spi Serial peripheral interface (SPI/SPIM)
+ * @ingroup    nrf_drivers
+ * @brief      Serial peripheral interface (SPI/SPIM) APIs.
+ *
+ */
+
+#ifndef NRF_DRV_SPI_H__
+#define NRF_DRV_SPI_H__
+
+#include "nordic_common.h"
+#include "sdk_config.h"
+#include "nrf_peripherals.h"
+#include "nrf_spi.h"
+#ifdef SPIM_PRESENT
+#include "nrf_spim.h"
+#endif
+#include "sdk_errors.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(SPIM_PRESENT)
+    #define NRF_DRV_SPI_PERIPHERAL(id)           \
+        (CONCAT_3(SPI, id, _USE_EASY_DMA) == 1 ? \
+            (void *)CONCAT_2(NRF_SPIM, id)       \
+          : (void *)CONCAT_2(NRF_SPI, id))
+    #define SPI2_IRQ            SPIM2_SPIS2_SPI2_IRQn
+    #define SPI2_IRQ_HANDLER    SPIM2_SPIS2_SPI2_IRQHandler
+#else
+    #define NRF_DRV_SPI_PERIPHERAL(id)  (void *)CONCAT_2(NRF_SPI, id)
+#endif
+#define SPI0_IRQ            SPI0_TWI0_IRQn
+#define SPI0_IRQ_HANDLER    SPI0_TWI0_IRQHandler
+#define SPI1_IRQ            SPI1_TWI1_IRQn
+#define SPI1_IRQ_HANDLER    SPI1_TWI1_IRQHandler
+
+
+/**
+ * @defgroup nrf_drv_spi SPI master driver
+ * @{
+ * @ingroup  nrf_spi
+ *
+ * @brief    Multi-instance SPI master driver.
+ */
+
+/**
+ * @brief SPI master driver instance data structure.
+ */
+typedef struct
+{
+    void *    p_registers;  ///< Pointer to the structure with SPI/SPIM peripheral instance registers.
+    IRQn_Type irq;          ///< SPI/SPIM peripheral instance IRQ number.
+    uint8_t   drv_inst_idx; ///< Driver instance index.
+    bool      use_easy_dma; ///< True if the peripheral with EasyDMA (SPIM) shall be used.
+} nrf_drv_spi_t;
+
+#define SPI0_INSTANCE_INDEX 0
+#define SPI1_INSTANCE_INDEX SPI0_INSTANCE_INDEX+SPI0_ENABLED
+#define SPI2_INSTANCE_INDEX SPI1_INSTANCE_INDEX+SPI1_ENABLED
+
+/**
+ * @brief Macro for creating an SPI master driver instance.
+ */
+#define NRF_DRV_SPI_INSTANCE(id)                        \
+{                                                       \
+    .p_registers  = NRF_DRV_SPI_PERIPHERAL(id),         \
+    .irq          = CONCAT_3(SPI, id, _IRQ),            \
+    .drv_inst_idx = CONCAT_3(SPI, id, _INSTANCE_INDEX), \
+    .use_easy_dma = CONCAT_3(SPI, id, _USE_EASY_DMA)    \
+}
+
+/**
+ * @brief This value can be provided instead of a pin number for signals MOSI,
+ *        MISO, and Slave Select to specify that the given signal is not used and
+ *        therefore does not need to be connected to a pin.
+ */
+#define NRF_DRV_SPI_PIN_NOT_USED  0xFF
+
+/**
+ * @brief SPI data rates.
+ */
+typedef enum
+{
+    NRF_DRV_SPI_FREQ_125K = NRF_SPI_FREQ_125K, ///< 125 kbps.
+    NRF_DRV_SPI_FREQ_250K = NRF_SPI_FREQ_250K, ///< 250 kbps.
+    NRF_DRV_SPI_FREQ_500K = NRF_SPI_FREQ_500K, ///< 500 kbps.
+    NRF_DRV_SPI_FREQ_1M   = NRF_SPI_FREQ_1M,   ///< 1 Mbps.
+    NRF_DRV_SPI_FREQ_2M   = NRF_SPI_FREQ_2M,   ///< 2 Mbps.
+    NRF_DRV_SPI_FREQ_4M   = NRF_SPI_FREQ_4M,   ///< 4 Mbps.
+    NRF_DRV_SPI_FREQ_8M   = NRF_SPI_FREQ_8M    ///< 8 Mbps.
+} nrf_drv_spi_frequency_t;
+
+/**
+ * @brief SPI modes.
+ */
+typedef enum
+{
+    NRF_DRV_SPI_MODE_0 = NRF_SPI_MODE_0, ///< SCK active high, sample on leading edge of clock.
+    NRF_DRV_SPI_MODE_1 = NRF_SPI_MODE_1, ///< SCK active high, sample on trailing edge of clock.
+    NRF_DRV_SPI_MODE_2 = NRF_SPI_MODE_2, ///< SCK active low, sample on leading edge of clock.
+    NRF_DRV_SPI_MODE_3 = NRF_SPI_MODE_3  ///< SCK active low, sample on trailing edge of clock.
+} nrf_drv_spi_mode_t;
+
+/**
+ * @brief SPI bit orders.
+ */
+typedef enum
+{
+    NRF_DRV_SPI_BIT_ORDER_MSB_FIRST = NRF_SPI_BIT_ORDER_MSB_FIRST, ///< Most significant bit shifted out first.
+    NRF_DRV_SPI_BIT_ORDER_LSB_FIRST = NRF_SPI_BIT_ORDER_LSB_FIRST  ///< Least significant bit shifted out first.
+} nrf_drv_spi_bit_order_t;
+
+/**
+ * @brief SPI master driver instance configuration structure.
+ */
+typedef struct
+{
+    uint8_t sck_pin;      ///< SCK pin number.
+    uint8_t mosi_pin;     ///< MOSI pin number (optional).
+                          /**< Set to @ref NRF_DRV_SPI_PIN_NOT_USED
+                           *   if this signal is not needed. */
+    uint8_t miso_pin;     ///< MISO pin number (optional).
+                          /**< Set to @ref NRF_DRV_SPI_PIN_NOT_USED
+                           *   if this signal is not needed. */
+    uint8_t ss_pin;       ///< Slave Select pin number (optional).
+                          /**< Set to @ref NRF_DRV_SPI_PIN_NOT_USED
+                           *   if this signal is not needed. The driver
+                           *   supports only active low for this signal.
+                           *   If the signal should be active high,
+                           *   it must be controlled externally. */
+    uint8_t irq_priority; ///< Interrupt priority.
+    uint8_t orc;          ///< Over-run character.
+                          /**< This character is used when all bytes from the TX buffer are sent,
+                               but the transfer continues due to RX. */
+    nrf_drv_spi_frequency_t frequency; ///< SPI frequency.
+    nrf_drv_spi_mode_t      mode;      ///< SPI mode.
+    nrf_drv_spi_bit_order_t bit_order; ///< SPI bit order.
+} nrf_drv_spi_config_t;
+
+/**
+ * @brief SPI master instance default configuration.
+ */
+#define NRF_DRV_SPI_DEFAULT_CONFIG                           \
+{                                                            \
+    .sck_pin      = NRF_DRV_SPI_PIN_NOT_USED,                \
+    .mosi_pin     = NRF_DRV_SPI_PIN_NOT_USED,                \
+    .miso_pin     = NRF_DRV_SPI_PIN_NOT_USED,                \
+    .ss_pin       = NRF_DRV_SPI_PIN_NOT_USED,                \
+    .irq_priority = SPI_DEFAULT_CONFIG_IRQ_PRIORITY,         \
+    .orc          = 0xFF,                                    \
+    .frequency    = NRF_DRV_SPI_FREQ_4M,                     \
+    .mode         = NRF_DRV_SPI_MODE_0,                      \
+    .bit_order    = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST,         \
+}
+
+#define NRF_DRV_SPI_FLAG_TX_POSTINC          (1UL << 0) /**< TX buffer address incremented after transfer. */
+#define NRF_DRV_SPI_FLAG_RX_POSTINC          (1UL << 1) /**< RX buffer address incremented after transfer. */
+#define NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER (1UL << 2) /**< Interrupt after each transfer is suppressed, and the event handler is not called. */
+#define NRF_DRV_SPI_FLAG_HOLD_XFER           (1UL << 3) /**< Set up the transfer but do not start it. */
+#define NRF_DRV_SPI_FLAG_REPEATED_XFER       (1UL << 4) /**< Flag indicating that the transfer will be executed multiple times. */
+
+/**
+ * @brief Single transfer descriptor structure.
+ */
+typedef struct
+{
+    uint8_t const * p_tx_buffer; ///< Pointer to TX buffer.
+    uint8_t         tx_length;   ///< TX buffer length.
+    uint8_t       * p_rx_buffer; ///< Pointer to RX buffer.
+    uint8_t         rx_length;   ///< RX buffer length.
+}nrf_drv_spi_xfer_desc_t;
+
+
+/**
+ * @brief Macro for setting up single transfer descriptor.
+ *
+ * This macro is for internal use only.
+ */
+#define NRF_DRV_SPI_SINGLE_XFER(p_tx, tx_len, p_rx, rx_len)  \
+    {                                                        \
+    .p_tx_buffer = (uint8_t const *)(p_tx),                  \
+    .tx_length = (tx_len),                                   \
+    .p_rx_buffer = (p_rx),                                   \
+    .rx_length = (rx_len),                                   \
+    }
+
+/**
+ * @brief Macro for setting duplex TX RX transfer.
+ */
+#define NRF_DRV_SPI_XFER_TRX(p_tx_buf, tx_length, p_rx_buf, rx_length)                    \
+        NRF_DRV_SPI_SINGLE_XFER(p_tx_buf, tx_length, p_rx_buf, rx_length)
+
+/**
+ * @brief Macro for setting TX transfer.
+ */
+#define NRF_DRV_SPI_XFER_TX(p_buf, length) \
+        NRF_DRV_SPI_SINGLE_XFER(p_buf, length, NULL, 0)
+
+/**
+ * @brief Macro for setting RX transfer.
+ */
+#define NRF_DRV_SPI_XFER_RX(p_buf, length) \
+        NRF_DRV_SPI_SINGLE_XFER(NULL, 0, p_buf, length)
+
+/**
+ * @brief SPI master driver event types, passed to the handler routine provided
+ *        during initialization.
+ */
+typedef enum
+{
+    NRF_DRV_SPI_EVENT_DONE, ///< Transfer done.
+} nrf_drv_spi_evt_type_t;
+
+typedef struct
+{
+    nrf_drv_spi_evt_type_t  type;      ///< Event type.
+    union
+    {
+        nrf_drv_spi_xfer_desc_t done;  ///< Event data for DONE event.
+    } data;
+} nrf_drv_spi_evt_t;
+
+/**
+ * @brief SPI master driver event handler type.
+ */
+typedef void (*nrf_drv_spi_handler_t)(nrf_drv_spi_evt_t const * p_event);
+
+
+/**
+ * @brief Function for initializing the SPI master driver instance.
+ *
+ * This function configures and enables the specified peripheral.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_config   Pointer to the structure with the initial configuration.
+ *                       If NULL, the default configuration is used.
+ * @param     handler    Event handler provided by the user. If NULL, transfers
+ *                       will be performed in blocking mode.
+ *
+ * @retval NRF_SUCCESS             If initialization was successful.
+ * @retval NRF_ERROR_INVALID_STATE If the driver was already initialized.
+ * @retval NRF_ERROR_BUSY          If some other peripheral with the same
+ *                                 instance ID is already in use. This is
+ *                                 possible only if PERIPHERAL_RESOURCE_SHARING_ENABLED
+ *                                 is set to a value other than zero.
+ */
+ret_code_t nrf_drv_spi_init(nrf_drv_spi_t const * const p_instance,
+                            nrf_drv_spi_config_t const * p_config,
+                            nrf_drv_spi_handler_t handler);
+
+/**
+ * @brief Function for uninitializing the SPI master driver instance.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ */
+void       nrf_drv_spi_uninit(nrf_drv_spi_t const * const p_instance);
+
+/**
+ * @brief Function for starting the SPI data transfer.
+ *
+ * If an event handler was provided in the @ref nrf_drv_spi_init call, this function
+ * returns immediately and the handler is called when the transfer is done.
+ * Otherwise, the transfer is performed in blocking mode, which means that this function
+ * returns when the transfer is finished.
+ *
+ * @note Peripherals using EasyDMA (for example, SPIM) require the transfer buffers
+ *       to be placed in the Data RAM region. If they are not and an SPIM instance is
+ *       used, this function will fail with the error code NRF_ERROR_INVALID_ADDR.
+ *
+ * @param[in] p_instance       Pointer to the driver instance structure.
+ * @param[in] p_tx_buffer      Pointer to the transmit buffer. Can be NULL
+ *                             if there is nothing to send.
+ * @param     tx_buffer_length Length of the transmit buffer.
+ * @param[in] p_rx_buffer      Pointer to the receive buffer. Can be NULL
+ *                             if there is nothing to receive.
+ * @param     rx_buffer_length Length of the receive buffer.
+ *
+ * @retval NRF_SUCCESS            If the operation was successful.
+ * @retval NRF_ERROR_BUSY         If a previously started transfer has not finished
+ *                                yet.
+ * @retval NRF_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data
+ *                                RAM region.
+ */
+ret_code_t nrf_drv_spi_transfer(nrf_drv_spi_t const * const p_instance,
+                                uint8_t const * p_tx_buffer,
+                                uint8_t         tx_buffer_length,
+                                uint8_t       * p_rx_buffer,
+                                uint8_t         rx_buffer_length);
+
+
+/**
+ * @brief Function for starting the SPI data transfer with additional option flags.
+ *
+ * Function enables customizing the transfer by using option flags.
+ *
+ * Additional options are provided using the flags parameter:
+ *
+ * - @ref NRF_DRV_SPI_FLAG_TX_POSTINC and @ref NRF_DRV_SPI_FLAG_RX_POSTINC<span></span>:
+ *   Post-incrementation of buffer addresses. Supported only by SPIM.
+ * - @ref NRF_DRV_SPI_FLAG_HOLD_XFER<span></span>: Driver is not starting the transfer. Use this
+ *   flag if the transfer is triggered externally by PPI. Supported only by SPIM. Use
+ *   @ref nrf_drv_twi_start_task_get to get the address of the start task.
+ * - @ref NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER<span></span>: No user event handler after transfer
+ *   completion. This also means no interrupt at the end of the transfer. Supported only by SPIM.
+ *   If @ref NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER is used, the driver does not set the instance into
+ *   busy state, so you must ensure that the next transfers are set up when SPIM is not active.
+ *   @ref nrf_drv_spi_end_event_get function can be used to detect end of transfer. Option can be used
+ *   together with @ref NRF_DRV_SPI_FLAG_REPEATED_XFER to prepare a sequence of SPI transfers
+ *   without interruptions.
+ * - @ref NRF_DRV_SPI_FLAG_REPEATED_XFER<span></span>: Prepare for repeated transfers. You can set
+ *   up a number of transfers that will be triggered externally (for example by PPI). An example is
+ *   a TXRX transfer with the options @ref NRF_DRV_SPI_FLAG_RX_POSTINC,
+ *   @ref NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER, and @ref NRF_DRV_SPI_FLAG_REPEATED_XFER. After the
+ *   transfer is set up, a set of transfers can be triggered by PPI that will read, for example,
+ *   the same register of an external component and put it into a RAM buffer without any interrupts.
+ *   @ref nrf_drv_spi_end_event_get can be used to get the address of the END event, which can be
+ *   used to count the number of transfers. If @ref NRF_DRV_SPI_FLAG_REPEATED_XFER is used,
+ *   the driver does not set the instance into busy state, so you must ensure that the next
+ *   transfers are set up when SPIM is not active. Supported only by SPIM.
+ * @note Function is intended to be used only in non-blocking mode.
+ *
+ * @param p_instance  Pointer to the driver instance structure.
+ * @param p_xfer_desc Pointer to the transfer descriptor.
+ * @param flags       Transfer options (0 for default settings).
+ *
+ * @retval NRF_SUCCESS             If the procedure was successful.
+ * @retval NRF_ERROR_BUSY          If the driver is not ready for a new transfer.
+ * @retval NRF_ERROR_NOT_SUPPORTED If the provided parameters are not supported.
+ * @retval NRF_ERROR_INVALID_ADDR  If the provided buffers are not placed in the Data
+ *                                 RAM region.
+ */
+ret_code_t nrf_drv_spi_xfer(nrf_drv_spi_t     const * const p_instance,
+                            nrf_drv_spi_xfer_desc_t const * p_xfer_desc,
+                            uint32_t                        flags);
+
+/**
+ * @brief Function for returning the address of a SPIM start task.
+ *
+ * This function should be used if @ref nrf_drv_spi_xfer was called with the flag @ref NRF_DRV_SPI_FLAG_HOLD_XFER.
+ * In that case, the transfer is not started by the driver, but it must be started externally by PPI.
+ *
+ * @param[in]  p_instance Pointer to the driver instance structure.
+ *
+ * @return     Start task address.
+ */
+uint32_t nrf_drv_spi_start_task_get(nrf_drv_spi_t const * p_instance);
+
+/**
+ * @brief Function for returning the address of a END SPIM event.
+ *
+ * A END event can be used to detect the end of a transfer if the @ref NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER
+ * option is used.
+ *
+ * @param[in]  p_instance Pointer to the driver instance structure.
+ *
+ * @return     END event address.
+ */
+uint32_t nrf_drv_spi_end_event_get(nrf_drv_spi_t const * p_instance);
+
+// modification for mbed-os
+#if __MBED__
+void nrf_drv_spi_abort(nrf_drv_spi_t const * p_instance);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_DRV_SPI_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/spi_slave/nrf_drv_spis.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,442 @@
+ /* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(SPIS)
+#define ENABLED_SPIS_COUNT (SPIS0_ENABLED+SPIS1_ENABLED+SPIS2_ENABLED)
+#if ENABLED_SPIS_COUNT
+#include "nrf_drv_spis.h"
+#include <stdbool.h>
+#include <stdio.h>
+#include "nrf.h"
+#include "nrf_gpio.h"
+#include "app_error.h"
+#include "app_util_platform.h"
+#include "nrf_drv_common.h"
+#include "nrf_assert.h"
+
+#define NRF_LOG_MODULE_NAME "SPIS"
+
+#if SPIS_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       SPIS_CONFIG_LOG_LEVEL
+#define NRF_LOG_INFO_COLOR  SPIS_CONFIG_INFO_COLOR
+#define NRF_LOG_DEBUG_COLOR SPIS_CONFIG_DEBUG_COLOR
+#define EVT_TO_STR(event)   (event == NRF_SPIS_EVENT_ACQUIRED ? "NRF_SPIS_EVENT_ACQUIRED" :                  \
+                            (event == NRF_SPIS_EVENT_END ? "NRF_SPIS_EVENT_END" :  "UNKNOWN ERROR"))
+
+#else //SPIS_CONFIG_LOG_ENABLED
+#define EVT_TO_STR(event)   ""
+#define NRF_LOG_LEVEL       0
+#endif //SPIS_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+
+
+/**@brief States of the SPI transaction state machine. */
+typedef enum
+{
+    SPIS_STATE_INIT,                                 /**< Initialization state. In this state the module waits for a call to @ref spi_slave_buffers_set. */
+    SPIS_BUFFER_RESOURCE_REQUESTED,                  /**< State where the configuration of the memory buffers, which are to be used in SPI transaction, has started. */
+    SPIS_BUFFER_RESOURCE_CONFIGURED,                 /**< State where the configuration of the memory buffers, which are to be used in SPI transaction, has completed. */
+    SPIS_XFER_COMPLETED                              /**< State where SPI transaction has been completed. */
+} nrf_drv_spis_state_t;
+
+
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+    #define IRQ_HANDLER_NAME(n) irq_handler_for_instance_##n
+    #define IRQ_HANDLER(n)      static void IRQ_HANDLER_NAME(n)(void)
+
+    #if NRF_MODULE_ENABLED(SPIS0)
+        IRQ_HANDLER(0);
+    #endif
+    #if NRF_MODULE_ENABLED(SPIS1)
+        IRQ_HANDLER(1);
+    #endif
+    #if NRF_MODULE_ENABLED(SPIS2)
+        IRQ_HANDLER(2);
+    #endif
+    static nrf_drv_irq_handler_t const m_irq_handlers[ENABLED_SPIS_COUNT] = {
+    #if NRF_MODULE_ENABLED(SPIS0)
+        IRQ_HANDLER_NAME(0),
+    #endif
+    #if NRF_MODULE_ENABLED(SPIS1)
+        IRQ_HANDLER_NAME(1),
+    #endif
+    #if NRF_MODULE_ENABLED(SPIS2)
+        IRQ_HANDLER_NAME(2),
+    #endif
+    };
+#else
+    #define IRQ_HANDLER(n) void SPIS##n##_IRQ_HANDLER(void)
+#endif // PERIPHERAL_RESOURCE_SHARING_ENABLED
+
+#define SPIS_IRQHANDLER_TEMPLATE(NUM) \
+    IRQ_HANDLER(NUM)                                                        \
+    {                                                                       \
+        spis_irq_handler(NRF_SPIS##NUM, &m_cb[SPIS##NUM##_INSTANCE_INDEX]); \
+    }
+
+
+/**@brief SPIS control block - driver instance local data. */
+typedef struct
+{
+    volatile uint32_t             tx_buffer_size;  //!< SPI slave TX buffer size in bytes.
+    volatile uint32_t             rx_buffer_size;  //!< SPI slave RX buffer size in bytes.
+    nrf_drv_spis_event_handler_t  handler;         //!< SPI event handler.
+    volatile const uint8_t *      tx_buffer;       //!< SPI slave TX buffer.
+    volatile uint8_t *            rx_buffer;       //!< SPI slave RX buffer.
+    nrf_drv_state_t               state;           //!< driver initialization state.
+    volatile nrf_drv_spis_state_t spi_state;       //!< SPI slave state.
+} spis_cb_t;
+
+static spis_cb_t m_cb[ENABLED_SPIS_COUNT];
+
+ret_code_t nrf_drv_spis_init(nrf_drv_spis_t const * const  p_instance,
+                             nrf_drv_spis_config_t const * p_config,
+                             nrf_drv_spis_event_handler_t  event_handler)
+{
+    ASSERT(p_config);
+    spis_cb_t * p_cb = &m_cb[p_instance->instance_id];
+    ret_code_t err_code;
+    
+    NRF_SPIS_Type * p_spis = p_instance->p_reg;
+
+    if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    if ((uint32_t)p_config->mode > (uint32_t)NRF_DRV_SPIS_MODE_3)
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+    if (!event_handler)
+    {
+        err_code = NRF_ERROR_NULL;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+    if (nrf_drv_common_per_res_acquire(p_spis,
+            m_irq_handlers[p_instance->instance_id]) != NRF_SUCCESS)
+    {
+        err_code = NRF_ERROR_BUSY;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+#endif
+
+    // Configure the SPI pins for input.
+    uint32_t mosi_pin;
+    uint32_t miso_pin;
+
+    if (p_config->miso_pin != NRF_DRV_SPIS_PIN_NOT_USED)
+    {
+        nrf_gpio_cfg(p_config->miso_pin,
+                    NRF_GPIO_PIN_DIR_INPUT,
+                    NRF_GPIO_PIN_INPUT_CONNECT,
+                    NRF_GPIO_PIN_NOPULL,
+                    p_config->miso_drive,
+                    NRF_GPIO_PIN_NOSENSE);
+        miso_pin = p_config->miso_pin;
+    }
+    else
+    {
+        miso_pin = NRF_SPIS_PIN_NOT_CONNECTED;
+    }
+
+    if (p_config->mosi_pin != NRF_DRV_SPIS_PIN_NOT_USED)
+    {
+        nrf_gpio_cfg(p_config->mosi_pin,
+                     NRF_GPIO_PIN_DIR_INPUT,
+                     NRF_GPIO_PIN_INPUT_CONNECT,
+                     NRF_GPIO_PIN_NOPULL,
+                     NRF_GPIO_PIN_S0S1,
+                     NRF_GPIO_PIN_NOSENSE);
+        mosi_pin = p_config->mosi_pin;
+    }
+    else
+    {
+        mosi_pin = NRF_SPIS_PIN_NOT_CONNECTED;
+    }
+
+    nrf_gpio_cfg(p_config->csn_pin,
+                 NRF_GPIO_PIN_DIR_INPUT,
+                 NRF_GPIO_PIN_INPUT_CONNECT,
+                 p_config->csn_pullup,
+                 NRF_GPIO_PIN_S0S1,
+                 NRF_GPIO_PIN_NOSENSE);
+
+    nrf_gpio_cfg(p_config->sck_pin,
+                 NRF_GPIO_PIN_DIR_INPUT,
+                 NRF_GPIO_PIN_INPUT_CONNECT,
+                 NRF_GPIO_PIN_NOPULL,
+                 NRF_GPIO_PIN_S0S1,
+                 NRF_GPIO_PIN_NOSENSE);
+
+    nrf_spis_pins_set(p_spis, p_config->sck_pin, mosi_pin, miso_pin, p_config->csn_pin);
+
+    nrf_spis_rx_buffer_set(p_spis, NULL, 0);
+    nrf_spis_tx_buffer_set(p_spis, NULL, 0);
+
+    // Configure SPI mode.
+    nrf_spis_configure(p_spis, (nrf_spis_mode_t) p_config->mode,
+                               (nrf_spis_bit_order_t) p_config->bit_order);
+
+    // Configure DEF and ORC characters.
+    nrf_spis_def_set(p_spis, p_config->def);
+    nrf_spis_orc_set(p_spis, p_config->orc);
+
+    // Clear possible pending events.
+    nrf_spis_event_clear(p_spis, NRF_SPIS_EVENT_END);
+    nrf_spis_event_clear(p_spis, NRF_SPIS_EVENT_ACQUIRED);
+
+    // Enable END_ACQUIRE shortcut.
+    nrf_spis_shorts_enable(p_spis, NRF_SPIS_SHORT_END_ACQUIRE);
+
+    m_cb[p_instance->instance_id].spi_state = SPIS_STATE_INIT;
+    m_cb[p_instance->instance_id].handler = event_handler;
+
+
+    // Enable IRQ.
+    nrf_spis_int_enable(p_spis, NRF_SPIS_INT_ACQUIRED_MASK | NRF_SPIS_INT_END_MASK);
+    nrf_drv_common_irq_enable(p_instance->irq, p_config->irq_priority);
+
+    p_cb->state = NRF_DRV_STATE_INITIALIZED;
+
+    // Enable SPI slave device.
+    nrf_spis_enable(p_spis);
+
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+void nrf_drv_spis_uninit(nrf_drv_spis_t const * const  p_instance)
+{
+    spis_cb_t * p_cb = &m_cb[p_instance->instance_id];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+
+    NRF_SPIS_Type * p_spis = p_instance->p_reg;
+
+    #define DISABLE_ALL 0xFFFFFFFF
+    nrf_spis_disable(p_spis);
+    nrf_drv_common_irq_disable(p_instance->irq);
+    nrf_spis_int_disable(p_spis, DISABLE_ALL);
+    #undef  DISABLE_ALL
+
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+    nrf_drv_common_per_res_release(p_spis);
+#endif
+
+    p_cb->state = NRF_DRV_STATE_UNINITIALIZED;
+    NRF_LOG_INFO("Initialized.\r\n");
+}
+
+
+/**@brief Function for executing the state entry action. */
+static void spis_state_entry_action_execute(NRF_SPIS_Type * p_spis,
+                                                     spis_cb_t * p_cb)
+{
+    nrf_drv_spis_event_t event;
+
+    switch (p_cb->spi_state)
+    {
+        case SPIS_BUFFER_RESOURCE_REQUESTED:
+            nrf_spis_task_trigger(p_spis, NRF_SPIS_TASK_ACQUIRE);
+            break;
+
+        case SPIS_BUFFER_RESOURCE_CONFIGURED:
+            event.evt_type  = NRF_DRV_SPIS_BUFFERS_SET_DONE;
+            event.rx_amount = 0;
+            event.tx_amount = 0;
+
+            APP_ERROR_CHECK_BOOL(p_cb->handler != NULL);
+            p_cb->handler(event);
+            break;
+
+        case SPIS_XFER_COMPLETED:
+            event.evt_type  = NRF_DRV_SPIS_XFER_DONE;
+            event.rx_amount = nrf_spis_rx_amount_get(p_spis);
+            event.tx_amount = nrf_spis_tx_amount_get(p_spis);            
+            NRF_LOG_INFO("Transfer rx_len:%d.\r\n", event.rx_amount);
+            NRF_LOG_DEBUG("Rx data:\r\n");
+            NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_cb->rx_buffer, event.rx_amount * sizeof(p_cb->rx_buffer));
+            APP_ERROR_CHECK_BOOL(p_cb->handler != NULL);
+            p_cb->handler(event);
+            break;
+
+        default:
+            // No implementation required.
+            break;
+    }
+}
+
+/**@brief Function for changing the state of the SPI state machine.
+ *
+ * @param[in] p_spis    SPIS instance register.
+ * @param[in] p_cb      SPIS instance control block.
+ * @param[in] new_state State where the state machine transits to.
+ */
+static void spis_state_change(NRF_SPIS_Type * p_spis,
+                              spis_cb_t * p_cb,
+                              nrf_drv_spis_state_t new_state)
+{
+    p_cb->spi_state = new_state;
+    spis_state_entry_action_execute(p_spis, p_cb);
+}
+
+
+ret_code_t nrf_drv_spis_buffers_set(nrf_drv_spis_t const * const  p_instance,
+                                    const uint8_t * p_tx_buffer,
+                                    uint8_t   tx_buffer_length,
+                                    uint8_t * p_rx_buffer,
+                                    uint8_t   rx_buffer_length)
+{
+    spis_cb_t * p_cb = &m_cb[p_instance->instance_id];
+    uint32_t err_code;
+
+    VERIFY_PARAM_NOT_NULL(p_rx_buffer);
+    VERIFY_PARAM_NOT_NULL(p_tx_buffer);
+
+    // EasyDMA requires that transfer buffers are placed in Data RAM region;
+    // signal error if they are not.
+    if ((p_tx_buffer != NULL && !nrf_drv_is_in_RAM(p_tx_buffer)) ||
+        (p_rx_buffer != NULL && !nrf_drv_is_in_RAM(p_rx_buffer)))
+    {
+        err_code = NRF_ERROR_INVALID_ADDR;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    switch (p_cb->spi_state)
+    {
+        case SPIS_STATE_INIT:
+        case SPIS_XFER_COMPLETED:
+        case SPIS_BUFFER_RESOURCE_CONFIGURED:
+            p_cb->tx_buffer      = p_tx_buffer;
+            p_cb->rx_buffer      = p_rx_buffer;
+            p_cb->tx_buffer_size = tx_buffer_length;
+            p_cb->rx_buffer_size = rx_buffer_length;
+            err_code             = NRF_SUCCESS;
+
+            spis_state_change(p_instance->p_reg, p_cb, SPIS_BUFFER_RESOURCE_REQUESTED);
+            break;
+
+        case SPIS_BUFFER_RESOURCE_REQUESTED:
+            err_code = NRF_ERROR_INVALID_STATE;
+            break;
+
+        default:
+            // @note: execution of this code path would imply internal error in the design.
+            err_code = NRF_ERROR_INTERNAL;
+            break;
+    }
+
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+static void spis_irq_handler(NRF_SPIS_Type * p_spis, spis_cb_t * p_cb)
+{
+    // @note: as multiple events can be pending for processing, the correct event processing order
+    // is as follows:
+    // - SPI semaphore acquired event.
+    // - SPI transaction complete event.
+
+    // Check for SPI semaphore acquired event.
+    if (nrf_spis_event_check(p_spis, NRF_SPIS_EVENT_ACQUIRED))
+    {
+        nrf_spis_event_clear(p_spis, NRF_SPIS_EVENT_ACQUIRED);
+        NRF_LOG_DEBUG("SPIS: Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_SPIS_EVENT_ACQUIRED));
+
+        switch (p_cb->spi_state)
+        {
+            case SPIS_BUFFER_RESOURCE_REQUESTED:
+                nrf_spis_tx_buffer_set(p_spis, (uint8_t *)p_cb->tx_buffer, p_cb->tx_buffer_size);
+                nrf_spis_rx_buffer_set(p_spis, (uint8_t *)p_cb->rx_buffer, p_cb->rx_buffer_size);
+
+                nrf_spis_task_trigger(p_spis, NRF_SPIS_TASK_RELEASE);
+
+                spis_state_change(p_spis, p_cb, SPIS_BUFFER_RESOURCE_CONFIGURED);
+                break;
+
+            default:
+                // No implementation required.
+                break;
+        }
+    }
+
+    // Check for SPI transaction complete event.
+    if (nrf_spis_event_check(p_spis, NRF_SPIS_EVENT_END))
+    {
+        nrf_spis_event_clear(p_spis, NRF_SPIS_EVENT_END);
+        NRF_LOG_DEBUG("SPIS: Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_SPIS_EVENT_END));
+
+        switch (p_cb->spi_state)
+        {
+            case SPIS_BUFFER_RESOURCE_CONFIGURED:
+                spis_state_change(p_spis, p_cb, SPIS_XFER_COMPLETED);
+                break;
+
+            default:
+                // No implementation required.
+                break;
+        }
+    }
+}
+
+#if NRF_MODULE_ENABLED(SPIS0)
+    SPIS_IRQHANDLER_TEMPLATE(0)
+#endif
+
+#if NRF_MODULE_ENABLED(SPIS1)
+    SPIS_IRQHANDLER_TEMPLATE(1)
+#endif
+
+#if NRF_MODULE_ENABLED(SPIS2)
+    SPIS_IRQHANDLER_TEMPLATE(2)
+#endif
+
+#endif // SPI_COUNT > 0
+#endif // NRF_MODULE_ENABLED(SPIS)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/spi_slave/nrf_drv_spis.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,256 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**@file
+ * @addtogroup nrf_spis SPIS HAL and driver
+ * @ingroup    nrf_drivers
+ * @brief      SPIS APIs.
+ *
+ */
+
+#ifndef SPI_SLAVE_H__
+#define SPI_SLAVE_H__
+
+#include <stdint.h>
+#include "nrf.h"
+#include "nrf_error.h"
+#include "sdk_config.h"
+#include "nrf_spis.h"
+#include "nrf_gpio.h"
+#include "sdk_common.h"
+#include "app_util_platform.h"
+#include "nrf_peripherals.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+    #define SPIS0_IRQ            SPI0_TWI0_IRQn
+    #define SPIS0_IRQ_HANDLER    SPI0_TWI0_IRQHandler
+    #define SPIS1_IRQ            SPI1_TWI1_IRQn
+    #define SPIS1_IRQ_HANDLER    SPI1_TWI1_IRQHandler
+
+#if SPIS_COUNT > 2
+    #define SPIS2_IRQ            SPIM2_SPIS2_SPI2_IRQn
+    #define SPIS2_IRQ_HANDLER    SPIM2_SPIS2_SPI2_IRQHandler
+#endif
+
+/**
+ * @defgroup nrf_drv_spis SPI slave driver
+ * @{
+ * @ingroup  nrf_spis
+ * @brief    Multi-instance SPI slave driver.
+ */
+
+#define NRF_DRV_SPIS_DEFAULT_CSN_PULLUP NRF_GPIO_PIN_NOPULL /**< Default pull-up configuration of the SPI CS. */
+#define NRF_DRV_SPIS_DEFAULT_MISO_DRIVE NRF_GPIO_PIN_S0S1   /**< Default drive configuration of the SPI MISO. */
+
+/**
+* @brief This value can be provided instead of a pin number for the signals MOSI
+*        and MISO to specify that the given signal is not used and therefore
+*        does not need to be connected to a pin.
+*/
+#define NRF_DRV_SPIS_PIN_NOT_USED       0xFF
+
+/** @brief SPIS transaction bit order definitions. */
+typedef enum
+{
+    NRF_DRV_SPIS_BIT_ORDER_LSB_FIRST = NRF_SPIS_BIT_ORDER_LSB_FIRST, /**< Least significant bit shifted out first. */
+    NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST = NRF_SPIS_BIT_ORDER_MSB_FIRST  /**< Most significant bit shifted out first. */
+} nrf_drv_spis_endian_t;
+
+/** @brief SPIS mode definitions for clock polarity and phase. */
+typedef enum
+{
+    NRF_DRV_SPIS_MODE_0 = NRF_SPIS_MODE_0,       /**< (CPOL = 0, CPHA = 0). */
+    NRF_DRV_SPIS_MODE_1 = NRF_SPIS_MODE_1,       /**< (CPOL = 0, CPHA = 1). */
+    NRF_DRV_SPIS_MODE_2 = NRF_SPIS_MODE_2,       /**< (CPOL = 1, CPHA = 0). */
+    NRF_DRV_SPIS_MODE_3 = NRF_SPIS_MODE_3        /**< (CPOL = 1, CPHA = 1). */
+} nrf_drv_spis_mode_t;
+
+/** @brief Event callback function event definitions. */
+typedef enum
+{
+    NRF_DRV_SPIS_BUFFERS_SET_DONE,          /**< Memory buffer set event. Memory buffers have been set successfully to the SPI slave device, and SPI transactions can be done. */
+    NRF_DRV_SPIS_XFER_DONE,                 /**< SPI transaction event. SPI transaction has been completed. */
+    NRF_DRV_SPIS_EVT_TYPE_MAX                    /**< Enumeration upper bound. */
+} nrf_drv_spis_event_type_t;
+
+/** @brief Structure containing the event context from the SPI slave driver. */
+typedef struct
+{
+    nrf_drv_spis_event_type_t evt_type;     //!< Type of event.
+    uint32_t                  rx_amount;    //!< Number of bytes received in last transaction. This parameter is only valid for @ref NRF_DRV_SPIS_XFER_DONE events.
+    uint32_t                  tx_amount;    //!< Number of bytes transmitted in last transaction. This parameter is only valid for @ref NRF_DRV_SPIS_XFER_DONE events.
+} nrf_drv_spis_event_t;
+
+/** @brief SPI slave driver instance data structure. */
+typedef struct
+{
+    NRF_SPIS_Type * p_reg;          //!< SPIS instance register.
+    uint8_t         instance_id;    //!< SPIS instance ID.
+    IRQn_Type       irq;            //!< IRQ of the specific instance.
+} nrf_drv_spis_t;
+
+#define SPIS0_INSTANCE_INDEX 0
+#define SPIS1_INSTANCE_INDEX SPIS0_INSTANCE_INDEX+SPIS0_ENABLED
+#define SPIS2_INSTANCE_INDEX SPIS1_INSTANCE_INDEX+SPIS1_ENABLED
+
+/** @brief Macro for creating an SPI slave driver instance. */
+#define NRF_DRV_SPIS_INSTANCE(id)                        \
+{                                                        \
+    .p_reg        = CONCAT_2(NRF_SPIS, id),              \
+    .irq          = CONCAT_3(SPIS, id, _IRQ),            \
+    .instance_id  = CONCAT_3(SPIS, id, _INSTANCE_INDEX), \
+}
+
+/** @brief SPI slave instance default configuration. */
+#define NRF_DRV_SPIS_DEFAULT_CONFIG                                \
+{                                                                  \
+    .sck_pin      = NRF_DRV_SPIS_PIN_NOT_USED,                     \
+    .mosi_pin     = NRF_DRV_SPIS_PIN_NOT_USED,                     \
+    .miso_pin     = NRF_DRV_SPIS_PIN_NOT_USED,                     \
+    .csn_pin      = NRF_DRV_SPIS_PIN_NOT_USED,                     \
+    .miso_drive   = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE,               \
+    .csn_pullup   = NRF_DRV_SPIS_DEFAULT_CSN_PULLUP,               \
+    .orc          = SPIS_DEFAULT_ORC,                              \
+    .def          = SPIS_DEFAULT_DEF,                              \
+    .mode         = (nrf_drv_spis_mode_t)SPIS_DEFAULT_MODE,        \
+    .bit_order    = (nrf_drv_spis_endian_t)SPIS_DEFAULT_BIT_ORDER, \
+    .irq_priority = SPIS_DEFAULT_CONFIG_IRQ_PRIORITY,              \
+}
+
+/** @brief SPI peripheral device configuration data. */
+typedef struct
+{
+    uint32_t              miso_pin;            //!< SPI MISO pin (optional).
+                                               /**< Set @ref NRF_DRV_SPIS_PIN_NOT_USED
+                                                *   if this signal is not needed. */
+    uint32_t              mosi_pin;            //!< SPI MOSI pin (optional).
+                                               /**< Set @ref NRF_DRV_SPIS_PIN_NOT_USED
+                                                *   if this signal is not needed. */
+    uint32_t              sck_pin;             //!< SPI SCK pin.
+    uint32_t              csn_pin;             //!< SPI CSN pin.
+    nrf_drv_spis_mode_t   mode;                //!< SPI mode.
+    nrf_drv_spis_endian_t bit_order;           //!< SPI transaction bit order.
+    nrf_gpio_pin_pull_t   csn_pullup;          //!< CSN pin pull-up configuration.
+    nrf_gpio_pin_drive_t  miso_drive;          //!< MISO pin drive configuration.
+    uint8_t               def;                 //!< Character clocked out in case of an ignored transaction.
+    uint8_t               orc;                 //!< Character clocked out after an over-read of the transmit buffer.
+    uint8_t               irq_priority;        //!< Interrupt priority.
+} nrf_drv_spis_config_t;
+
+
+/** @brief SPI slave event callback function type.
+ *
+ * @param[in] event                 SPI slave driver event.
+ */
+typedef void (*nrf_drv_spis_event_handler_t)(nrf_drv_spis_event_t event);
+
+/** @brief Function for initializing the SPI slave driver instance.
+ *
+ * @param[in] p_instance    Pointer to the driver instance structure.
+ * @param[in] p_config      Pointer to the structure with the initial configuration.
+ *                          If NULL, the default configuration will be used.
+ * @param[in] event_handler Function to be called by the SPI slave driver upon event.
+ *
+ * @retval NRF_SUCCESS             If the initialization was successful.
+ * @retval NRF_ERROR_INVALID_PARAM If an invalid parameter is supplied.
+ * @retval NRF_ERROR_BUSY          If some other peripheral with the same
+ *                                 instance ID is already in use. This is
+ *                                 possible only if PERIPHERAL_RESOURCE_SHARING_ENABLED
+ *                                 is set to a value other than zero.
+ */
+ret_code_t nrf_drv_spis_init(nrf_drv_spis_t const * const  p_instance,
+                             nrf_drv_spis_config_t const * p_config,
+                             nrf_drv_spis_event_handler_t  event_handler);
+
+/**
+ * @brief Function for uninitializing the SPI slave driver instance.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ */
+void nrf_drv_spis_uninit(nrf_drv_spis_t const * const p_instance);
+
+/** @brief Function for preparing the SPI slave instance for a single SPI transaction.
+ *
+ * This function prepares the SPI slave device to be ready for a single SPI transaction. It configures
+ * the SPI slave device to use the memory supplied with the function call in SPI transactions.
+ *
+ * When either the memory buffer configuration or the SPI transaction has been
+ * completed, the event callback function will be called with the appropriate event
+ * @ref nrf_drv_spis_event_type_t. Note that the callback function can be called before returning from
+ * this function, because it is called from the SPI slave interrupt context.
+ *
+ * @note This function can be called from the callback function context.
+ *
+ * @note Client applications must call this function after every @ref NRF_DRV_SPIS_XFER_DONE event if
+ * the SPI slave driver should be prepared for a possible new SPI transaction.
+ *
+ * @note Peripherals that are using EasyDMA (for example, SPIS) require the transfer buffers
+ * to be placed in the Data RAM region. Otherwise, this function will fail
+ * with the error code NRF_ERROR_INVALID_ADDR.
+ *
+ * @param[in] p_instance            Pointer to the driver instance structure.
+ * @param[in] p_tx_buffer           Pointer to the TX buffer.
+ * @param[in] p_rx_buffer           Pointer to the RX buffer.
+ * @param[in] tx_buffer_length      Length of the TX buffer in bytes.
+ * @param[in] rx_buffer_length      Length of the RX buffer in bytes.
+ *
+ * @retval NRF_SUCCESS              If the operation was successful.
+ * @retval NRF_ERROR_NULL           If the operation failed because a NULL pointer was supplied.
+ * @retval NRF_ERROR_INVALID_STATE  If the operation failed because the SPI slave device is in an incorrect state.
+ * @retval NRF_ERROR_INVALID_ADDR   If the provided buffers are not placed in the Data
+ *                                  RAM region.
+ * @retval NRF_ERROR_INTERNAL       If the operation failed because of an internal error.
+ */
+ret_code_t nrf_drv_spis_buffers_set(nrf_drv_spis_t const * const  p_instance,
+                                    const uint8_t * p_tx_buffer,
+                                    uint8_t   tx_buffer_length,
+                                    uint8_t * p_rx_buffer,
+                                    uint8_t   rx_buffer_length);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // SPI_SLAVE_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/timer/nrf_drv_timer.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,330 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(TIMER)
+#define ENABLED_TIMER_COUNT (TIMER0_ENABLED+TIMER1_ENABLED+TIMER2_ENABLED+TIMER3_ENABLED+TIMER4_ENABLED)
+#if ENABLED_TIMER_COUNT
+#include "nrf_drv_timer.h"
+#include "nrf_drv_common.h"
+#include "app_util_platform.h"
+
+#define NRF_LOG_MODULE_NAME "TIMER"
+
+#if TIMER_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       TIMER_CONFIG_LOG_LEVEL
+#define NRF_LOG_INFO_COLOR  TIMER_CONFIG_INFO_COLOR
+#define NRF_LOG_DEBUG_COLOR TIMER_CONFIG_DEBUG_COLOR
+#else //TIMER_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       0
+#endif //TIMER_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+
+/**@brief Timer control block. */
+typedef struct
+{
+    nrf_timer_event_handler_t handler;
+    void *                    context;
+    nrf_drv_state_t           state;
+} timer_control_block_t;
+
+static timer_control_block_t m_cb[ENABLED_TIMER_COUNT];
+
+ret_code_t nrf_drv_timer_init(nrf_drv_timer_t const * const p_instance,
+                              nrf_drv_timer_config_t const * p_config,
+                              nrf_timer_event_handler_t timer_event_handler)
+{
+    timer_control_block_t * p_cb = &m_cb[p_instance->instance_id];
+    ASSERT(((p_instance->p_reg == NRF_TIMER0) && TIMER0_ENABLED) || (p_instance->p_reg != NRF_TIMER0));
+    ASSERT(((p_instance->p_reg == NRF_TIMER1) && TIMER1_ENABLED) || (p_instance->p_reg != NRF_TIMER1));
+    ASSERT(((p_instance->p_reg == NRF_TIMER2) && TIMER2_ENABLED) || (p_instance->p_reg != NRF_TIMER2));
+#if TIMER_COUNT == 5
+    ASSERT(((p_instance->p_reg == NRF_TIMER3) && TIMER3_ENABLED) || (p_instance->p_reg != NRF_TIMER3));
+    ASSERT(((p_instance->p_reg == NRF_TIMER4) && TIMER4_ENABLED) || (p_instance->p_reg != NRF_TIMER4));
+#endif //TIMER_COUNT
+#ifdef SOFTDEVICE_PRESENT
+    ASSERT(p_instance->p_reg != NRF_TIMER0);
+    ASSERT(p_config);
+#endif
+    ret_code_t err_code;
+
+    if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    if (timer_event_handler == NULL)
+    {
+        err_code = NRF_ERROR_INVALID_PARAM;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    /* Warning 685: Relational operator '<=' always evaluates to 'true'"
+     * Warning in NRF_TIMER_IS_BIT_WIDTH_VALID macro. Macro validate timers resolution.
+     * Not necessary in nRF52 based systems. Obligatory in nRF51 based systems.
+     */
+
+    /*lint -save -e685 */
+
+    ASSERT(NRF_TIMER_IS_BIT_WIDTH_VALID(p_instance->p_reg, p_config->bit_width));
+
+    //lint -restore
+
+    p_cb->handler = timer_event_handler;
+    p_cb->context = p_config->p_context;
+
+    uint8_t i;
+    for (i = 0; i < p_instance->cc_channel_count; ++i)
+    {
+        nrf_timer_event_clear(p_instance->p_reg,
+            nrf_timer_compare_event_get(i));
+    }
+
+    nrf_drv_common_irq_enable(nrf_drv_get_IRQn(p_instance->p_reg),
+        p_config->interrupt_priority);
+
+    nrf_timer_mode_set(p_instance->p_reg, p_config->mode);
+    nrf_timer_bit_width_set(p_instance->p_reg, p_config->bit_width);
+    nrf_timer_frequency_set(p_instance->p_reg, p_config->frequency);
+
+    p_cb->state = NRF_DRV_STATE_INITIALIZED;
+
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+void nrf_drv_timer_uninit(nrf_drv_timer_t const * const p_instance)
+{
+    nrf_drv_common_irq_disable(nrf_drv_get_IRQn(p_instance->p_reg));
+
+    #define DISABLE_ALL UINT32_MAX
+    nrf_timer_shorts_disable(p_instance->p_reg, DISABLE_ALL);
+    nrf_timer_int_disable(p_instance->p_reg, DISABLE_ALL);
+    #undef DISABLE_ALL
+
+    if (m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON)
+    {
+        nrf_drv_timer_disable(p_instance);
+    }
+
+    m_cb[p_instance->instance_id].state = NRF_DRV_STATE_UNINITIALIZED;
+    NRF_LOG_INFO("Uninitialized instance: %d.\r\n", p_instance->instance_id);
+}
+
+void nrf_drv_timer_enable(nrf_drv_timer_t const * const p_instance)
+{
+    ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_INITIALIZED);
+    nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_START);
+    m_cb[p_instance->instance_id].state = NRF_DRV_STATE_POWERED_ON;
+    NRF_LOG_INFO("Enabled instance: %d.\r\n", p_instance->instance_id);
+}
+
+void nrf_drv_timer_disable(nrf_drv_timer_t const * const p_instance)
+{
+    ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
+    nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_SHUTDOWN);
+    m_cb[p_instance->instance_id].state = NRF_DRV_STATE_INITIALIZED;
+    NRF_LOG_INFO("Disabled instance: %d.\r\n", p_instance->instance_id);
+}
+
+void nrf_drv_timer_resume(nrf_drv_timer_t const * const p_instance)
+{
+    ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
+    nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_START);
+    NRF_LOG_INFO("Resumed instance: %d.\r\n", p_instance->instance_id);
+}
+
+void nrf_drv_timer_pause(nrf_drv_timer_t const * const p_instance)
+{
+    ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
+    nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_STOP);
+    NRF_LOG_INFO("Paused instance: %d.\r\n", p_instance->instance_id);
+}
+
+void nrf_drv_timer_clear(nrf_drv_timer_t const * const p_instance)
+{
+    ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED);
+    nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_CLEAR);
+}
+
+void nrf_drv_timer_increment(nrf_drv_timer_t const * const p_instance)
+{
+    ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
+    ASSERT(nrf_timer_mode_get(p_instance->p_reg) != NRF_TIMER_MODE_TIMER);
+
+    nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_COUNT);
+}
+
+uint32_t nrf_drv_timer_capture(nrf_drv_timer_t const * const p_instance,
+                               nrf_timer_cc_channel_t cc_channel)
+{
+    ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
+    ASSERT(cc_channel < p_instance->cc_channel_count);
+
+    nrf_timer_task_trigger(p_instance->p_reg,
+        nrf_timer_capture_task_get(cc_channel));
+    return nrf_timer_cc_read(p_instance->p_reg, cc_channel);
+}
+
+void nrf_drv_timer_compare(nrf_drv_timer_t const * const p_instance,
+                           nrf_timer_cc_channel_t cc_channel,
+                           uint32_t               cc_value,
+                           bool                   enable_int)
+{
+    nrf_timer_int_mask_t timer_int = nrf_timer_compare_int_get(cc_channel);
+
+    if (enable_int)
+    {
+        nrf_timer_int_enable(p_instance->p_reg, timer_int);
+    }
+    else
+    {
+        nrf_timer_int_disable(p_instance->p_reg, timer_int);
+    }
+
+    nrf_timer_cc_write(p_instance->p_reg, cc_channel, cc_value);
+    NRF_LOG_INFO("Timer id: %d, capture value set: %d, channel: %d.\r\n", p_instance->instance_id, cc_value, cc_channel);
+}
+
+void nrf_drv_timer_extended_compare(nrf_drv_timer_t const * const p_instance,
+                                    nrf_timer_cc_channel_t cc_channel,
+                                    uint32_t               cc_value,
+                                    nrf_timer_short_mask_t timer_short_mask,
+                                    bool                   enable_int)
+{
+    nrf_timer_shorts_disable(p_instance->p_reg,
+        (TIMER_SHORTS_COMPARE0_STOP_Msk  << cc_channel) |
+        (TIMER_SHORTS_COMPARE0_CLEAR_Msk << cc_channel));
+
+    nrf_timer_shorts_enable(p_instance->p_reg, timer_short_mask);
+
+    (void)nrf_drv_timer_compare(p_instance,
+                                cc_channel,
+                                cc_value,
+                                enable_int);
+    NRF_LOG_INFO("Timer id: %d, capture value set: %d, channel: %d.\r\n", p_instance->instance_id, cc_value, cc_channel);
+}
+
+void nrf_drv_timer_compare_int_enable(nrf_drv_timer_t const * const p_instance,
+                                      uint32_t channel)
+{
+    ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED);
+    ASSERT(channel < p_instance->cc_channel_count);
+
+    nrf_timer_event_clear(p_instance->p_reg,
+        nrf_timer_compare_event_get(channel));
+    nrf_timer_int_enable(p_instance->p_reg,
+        nrf_timer_compare_int_get(channel));
+}
+
+void nrf_drv_timer_compare_int_disable(nrf_drv_timer_t const * const p_instance,
+                                       uint32_t channel)
+{
+    ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED);
+    ASSERT(channel < p_instance->cc_channel_count);
+
+    nrf_timer_int_disable(p_instance->p_reg,
+        nrf_timer_compare_int_get(channel));
+}
+
+static void irq_handler(NRF_TIMER_Type * p_reg,
+                        timer_control_block_t * p_cb,
+                        uint8_t channel_count)
+{
+    uint8_t i;
+    for (i = 0; i < channel_count; ++i)
+    {
+        nrf_timer_event_t event = nrf_timer_compare_event_get(i);
+        nrf_timer_int_mask_t int_mask = nrf_timer_compare_int_get(i);
+
+        if (nrf_timer_event_check(p_reg, event) &&
+            nrf_timer_int_enable_check(p_reg, int_mask))
+        {
+            nrf_timer_event_clear(p_reg, event);
+            NRF_LOG_DEBUG("Compare event, channel: %d.\r\n", i);
+            p_cb->handler(event, p_cb->context);
+        }
+    }
+}
+
+#if NRF_MODULE_ENABLED(TIMER0)
+void TIMER0_IRQHandler(void)
+{
+    irq_handler(NRF_TIMER0, &m_cb[TIMER0_INSTANCE_INDEX],
+        NRF_TIMER_CC_CHANNEL_COUNT(0));
+}
+#endif
+
+#if NRF_MODULE_ENABLED(TIMER1)
+void TIMER1_IRQHandler(void)
+{
+    irq_handler(NRF_TIMER1, &m_cb[TIMER1_INSTANCE_INDEX],
+        NRF_TIMER_CC_CHANNEL_COUNT(1));
+}
+#endif
+
+#if NRF_MODULE_ENABLED(TIMER2)
+void TIMER2_IRQHandler(void)
+{
+    irq_handler(NRF_TIMER2, &m_cb[TIMER2_INSTANCE_INDEX],
+        NRF_TIMER_CC_CHANNEL_COUNT(2));
+}
+#endif
+
+#if NRF_MODULE_ENABLED(TIMER3)
+void TIMER3_IRQHandler(void)
+{
+    irq_handler(NRF_TIMER3, &m_cb[TIMER3_INSTANCE_INDEX],
+        NRF_TIMER_CC_CHANNEL_COUNT(3));
+}
+#endif
+
+#if NRF_MODULE_ENABLED(TIMER4)
+void TIMER4_IRQHandler(void)
+{
+    irq_handler(NRF_TIMER4, &m_cb[TIMER4_INSTANCE_INDEX],
+        NRF_TIMER_CC_CHANNEL_COUNT(4));
+}
+#endif
+#endif // ENABLED_TIMER_COUNT
+#endif // NRF_MODULE_ENABLED(TIMER)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/timer/nrf_drv_timer.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,410 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**@file
+ * @addtogroup nrf_timer Timer HAL and driver
+ * @ingroup    nrf_drivers
+ * @brief      Timer APIs.
+ * @details    The timer HAL provides basic APIs for accessing the registers
+ *             of the timer. The timer driver provides APIs on a higher level.
+ *
+ * @defgroup   nrf_drv_timer Timer driver
+ * @{
+ * @ingroup    nrf_timer
+ * @brief      Multi-instance timer driver.
+ */
+
+#ifndef NRF_DRV_TIMER_H__
+#define NRF_DRV_TIMER_H__
+
+#include "nordic_common.h"
+#include "sdk_config.h"
+#include "nrf_timer.h"
+#include "sdk_errors.h"
+#include "nrf_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Timer driver instance data structure.
+ */
+typedef struct
+{
+    NRF_TIMER_Type * p_reg;            ///< Pointer to the structure with TIMER peripheral instance registers.
+    uint8_t          instance_id;      ///< Driver instance index.
+    uint8_t          cc_channel_count; ///< Number of capture/compare channels.
+} nrf_drv_timer_t;
+
+#define ENABLED_TIMER_COUNT (TIMER0_ENABLED+TIMER1_ENABLED+TIMER2_ENABLED+TIMER3_ENABLED+TIMER4_ENABLED)
+
+#define TIMER0_INSTANCE_INDEX 0
+#define TIMER1_INSTANCE_INDEX TIMER0_INSTANCE_INDEX+TIMER0_ENABLED
+#define TIMER2_INSTANCE_INDEX TIMER1_INSTANCE_INDEX+TIMER1_ENABLED
+#define TIMER3_INSTANCE_INDEX TIMER2_INSTANCE_INDEX+TIMER2_ENABLED
+#define TIMER4_INSTANCE_INDEX TIMER3_INSTANCE_INDEX+TIMER3_ENABLED
+
+/**
+ * @brief Macro for creating a timer driver instance.
+ */
+#define NRF_DRV_TIMER_INSTANCE(id) \
+{                                                             \
+    .p_reg            = CONCAT_2(NRF_TIMER, id),              \
+    .instance_id      = CONCAT_3(TIMER, id, _INSTANCE_INDEX), \
+    .cc_channel_count = NRF_TIMER_CC_CHANNEL_COUNT(id),       \
+}
+
+/**
+ * @brief Timer driver instance configuration structure.
+ */
+typedef struct
+{
+    nrf_timer_frequency_t frequency;          ///< Frequency.
+    nrf_timer_mode_t      mode;               ///< Mode of operation.
+    nrf_timer_bit_width_t bit_width;          ///< Bit width.
+    uint8_t               interrupt_priority; ///< Interrupt priority.
+    void *                p_context;          ///< Context passed to interrupt handler.
+} nrf_drv_timer_config_t;
+
+/**
+ * @brief Timer driver instance default configuration.
+ */
+#define NRF_DRV_TIMER_DEFAULT_CONFIG \
+{                                                                               \
+    .frequency          = (nrf_timer_frequency_t)TIMER_DEFAULT_CONFIG_FREQUENCY,\
+    .mode               = (nrf_timer_mode_t)TIMER_DEFAULT_CONFIG_MODE,          \
+    .bit_width          = (nrf_timer_bit_width_t)TIMER_DEFAULT_CONFIG_BIT_WIDTH,\
+    .interrupt_priority = TIMER_DEFAULT_CONFIG_IRQ_PRIORITY,                    \
+    .p_context          = NULL                                                  \
+}
+
+/**
+ * @brief Timer driver event handler type.
+ *
+ * @param[in] event_type Timer event.
+ * @param[in] p_context  General purpose parameter set during initialization of
+ *                       the timer. This parameter can be used to pass
+ *                       additional information to the handler function, for
+ *                       example, the timer ID.
+ */
+typedef void (* nrf_timer_event_handler_t)(nrf_timer_event_t event_type,
+                                           void * p_context);
+
+/**
+ * @brief Function for initializing the timer.
+ *
+ * @param[in] p_instance          Pointer to the driver instance structure.
+ * @param[in] p_config            Initial configuration.
+ *                                If NULL, the default configuration is used.
+ * @param[in] timer_event_handler Event handler provided by the user.
+ *                                Must not be NULL.
+ *
+ * @retval NRF_SUCCESS             If initialization was successful.
+ * @retval NRF_ERROR_INVALID_STATE If the instance is already initialized.
+ * @retval NRF_ERROR_INVALID_PARAM If no handler was provided.
+ */
+ret_code_t nrf_drv_timer_init(nrf_drv_timer_t const * const p_instance,
+                              nrf_drv_timer_config_t const * p_config,
+                              nrf_timer_event_handler_t timer_event_handler);
+
+/**
+ * @brief Function for uninitializing the timer.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ */
+void nrf_drv_timer_uninit(nrf_drv_timer_t const * const p_instance);
+
+/**
+ * @brief Function for turning on the timer.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ */
+void nrf_drv_timer_enable(nrf_drv_timer_t const * const p_instance);
+
+/**
+ * @brief Function for turning off the timer.
+ *
+ * Note that the timer will allow to enter the lowest possible SYSTEM_ON state
+ * only after this function is called.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ */
+void nrf_drv_timer_disable(nrf_drv_timer_t const * const p_instance);
+
+/**
+ * @brief Function for pausing the timer.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ */
+void nrf_drv_timer_pause(nrf_drv_timer_t const * const p_instance);
+
+/**
+ * @brief Function for resuming the timer.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ */
+void nrf_drv_timer_resume(nrf_drv_timer_t const * const p_instance);
+
+/**
+ * @brief Function for clearing the timer.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ */
+void nrf_drv_timer_clear(nrf_drv_timer_t const * const p_instance);
+
+/**
+ * @brief Function for incrementing the timer.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ */
+void nrf_drv_timer_increment(nrf_drv_timer_t const * const p_instance);
+
+/**
+ * @brief Function for returning the address of a specific timer task.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] timer_task Timer task.
+ *
+ * @return Task address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_timer_task_address_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       nrf_timer_task_t timer_task);
+
+/**
+ * @brief Function for returning the address of a specific timer capture task.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] channel    Capture channel number.
+ *
+ * @return Task address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_timer_capture_task_address_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       uint32_t channel);
+
+/**
+ * @brief Function for returning the address of a specific timer event.
+ *
+ * @param[in] p_instance  Pointer to the driver instance structure.
+ * @param[in] timer_event Timer event.
+ *
+ * @return Event address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_timer_event_address_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       nrf_timer_event_t timer_event);
+
+/**
+ * @brief Function for returning the address of a specific timer compare event.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] channel    Compare channel number.
+ *
+ * @return Event address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_timer_compare_event_address_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       uint32_t channel);
+
+/**
+ * @brief Function for capturing the timer value.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] cc_channel Capture channel number.
+ *
+ * @return Captured value.
+ */
+uint32_t nrf_drv_timer_capture(nrf_drv_timer_t const * const p_instance,
+                               nrf_timer_cc_channel_t cc_channel);
+
+/**
+ * @brief Function for returning the capture value from a specific channel.
+ *
+ * Use this function to read channel values when PPI is used for capturing.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] cc_channel Capture channel number.
+ *
+ * @return Captured value.
+ */
+__STATIC_INLINE uint32_t nrf_drv_timer_capture_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       nrf_timer_cc_channel_t cc_channel);
+
+/**
+ * @brief Function for setting the timer channel in compare mode.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] cc_channel Compare channel number.
+ * @param[in] cc_value   Compare value.
+ * @param[in] enable_int Enable or disable the interrupt for the compare channel.
+ */
+void nrf_drv_timer_compare(nrf_drv_timer_t const * const p_instance,
+                           nrf_timer_cc_channel_t cc_channel,
+                           uint32_t               cc_value,
+                           bool                   enable_int);
+
+/**
+ * @brief Function for setting the timer channel in extended compare mode.
+ *
+ * @param[in] p_instance       Pointer to the driver instance structure.
+ * @param[in] cc_channel       Compare channel number.
+ * @param[in] cc_value         Compare value.
+ * @param[in] timer_short_mask Shortcut between the compare event on the channel
+ *                             and the timer task (STOP or CLEAR).
+ * @param[in] enable_int       Enable or disable the interrupt for the compare
+ *                             channel.
+ */
+void nrf_drv_timer_extended_compare(nrf_drv_timer_t const * const p_instance,
+                                    nrf_timer_cc_channel_t cc_channel,
+                                    uint32_t               cc_value,
+                                    nrf_timer_short_mask_t timer_short_mask,
+                                    bool                   enable_int);
+
+/**
+ * @brief Function for converting time in microseconds to timer ticks.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] time_us    Time in microseconds.
+ *
+ * @return Number of ticks.
+ */
+__STATIC_INLINE uint32_t nrf_drv_timer_us_to_ticks(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       uint32_t time_us);
+
+/**
+ * @brief Function for converting time in milliseconds to timer ticks.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] time_ms    Time in milliseconds.
+ *
+ * @return Number of ticks.
+ */
+__STATIC_INLINE uint32_t nrf_drv_timer_ms_to_ticks(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       uint32_t time_ms);
+
+/**
+ * @brief Function for enabling timer compare interrupt.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] channel    Compare channel.
+ */
+void nrf_drv_timer_compare_int_enable(nrf_drv_timer_t const * const p_instance,
+                                      uint32_t channel);
+
+/**
+ * @brief Function for disabling timer compare interrupt.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] channel    Compare channel.
+ */
+void nrf_drv_timer_compare_int_disable(nrf_drv_timer_t const * const p_instance,
+                                       uint32_t channel);
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE uint32_t nrf_drv_timer_task_address_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       nrf_timer_task_t timer_task)
+{
+    return (uint32_t)nrf_timer_task_address_get(p_instance->p_reg, timer_task);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_timer_capture_task_address_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       uint32_t channel)
+{
+    ASSERT(channel < p_instance->cc_channel_count);
+    return (uint32_t)nrf_timer_task_address_get(p_instance->p_reg,
+                         nrf_timer_capture_task_get(channel));
+}
+
+__STATIC_INLINE uint32_t nrf_drv_timer_event_address_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       nrf_timer_event_t timer_event)
+{
+    return (uint32_t)nrf_timer_event_address_get(p_instance->p_reg, timer_event);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_timer_compare_event_address_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       uint32_t channel)
+{
+    ASSERT(channel < p_instance->cc_channel_count);
+    return (uint32_t)nrf_timer_event_address_get(p_instance->p_reg,
+                         nrf_timer_compare_event_get(channel));
+}
+
+__STATIC_INLINE uint32_t nrf_drv_timer_capture_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       nrf_timer_cc_channel_t cc_channel)
+{
+    return nrf_timer_cc_read(p_instance->p_reg, cc_channel);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_timer_us_to_ticks(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       uint32_t timer_us)
+{
+    return nrf_timer_us_to_ticks(timer_us,
+        nrf_timer_frequency_get(p_instance->p_reg));
+}
+
+__STATIC_INLINE uint32_t nrf_drv_timer_ms_to_ticks(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       uint32_t timer_ms)
+{
+    return nrf_timer_ms_to_ticks(timer_ms,
+        nrf_timer_frequency_get(p_instance->p_reg));
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_DRV_TIMER_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/twi_master/nrf_drv_twi.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,1170 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(TWI)
+#define ENABLED_TWI_COUNT (TWI0_ENABLED+TWI1_ENABLED)
+#if ENABLED_TWI_COUNT
+#include "nrf_drv_twi.h"
+#include "nrf_drv_common.h"
+#include "nrf_gpio.h"
+#include "nrf_assert.h"
+#include "app_util_platform.h"
+#include "nrf_delay.h"
+
+#include <stdio.h>
+
+#define NRF_LOG_MODULE_NAME "TWI"
+
+#if TWI_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       TWI_CONFIG_LOG_LEVEL
+#define NRF_LOG_INFO_COLOR  TWI_CONFIG_INFO_COLOR
+#define NRF_LOG_DEBUG_COLOR TWI_CONFIG_DEBUG_COLOR
+#define EVT_TO_STR(event)   (event == NRF_DRV_TWI_EVT_DONE ? "EVT_DONE" :                            \
+                            (event == NRF_DRV_TWI_EVT_ADDRESS_NACK ? "EVT_ADDRESS_NACK" :            \
+                            (event == NRF_DRV_TWI_EVT_DATA_NACK ? "EVT_DATA_NACK" : "UNKNOWN ERROR")))
+#define EVT_TO_STR_TWI(event)   (event == NRF_TWI_EVENT_STOPPED ? "NRF_TWI_EVENT_STOPPED" :                            \
+                                (event == NRF_TWI_EVENT_RXDREADY ? "NRF_TWI_EVENT_RXDREADY" :                          \
+                                (event == NRF_TWI_EVENT_TXDSENT ? "NRF_TWI_EVENT_TXDSENT" :                            \
+                                (event == NRF_TWI_EVENT_ERROR ? "NRF_TWI_EVENT_ERROR" :                                \
+                                (event == NRF_TWI_EVENT_BB ? "NRF_TWI_EVENT_BB" :                                      \
+                                (event == NRF_TWI_EVENT_SUSPENDED ? "NRF_TWI_EVENT_SUSPENDED" : "UNKNOWN ERROR"))))))
+#define EVT_TO_STR_TWIM(event)  (event == NRF_TWIM_EVENT_STOPPED ? "NRF_TWIM_EVENT_STOPPED" :                      \
+                                (event == NRF_TWIM_EVENT_ERROR ? "NRF_TWIM_EVENT_ERROR" :                          \
+                                (event == NRF_TWIM_EVENT_SUSPENDED ? "NRF_TWIM_EVENT_SUSPENDED" :                  \
+                                (event == NRF_TWIM_EVENT_RXSTARTED ? "NRF_TWIM_EVENT_RXSTARTED" :                  \
+                                (event == NRF_TWIM_EVENT_TXSTARTED ? "NRF_TWIM_EVENT_TXSTARTED" :                  \
+                                (event == NRF_TWIM_EVENT_LASTRX ? "NRF_TWIM_EVENT_LASTRX" :                        \
+                                (event == NRF_TWIM_EVENT_LASTTX ? "NRF_TWIM_EVENT_LASTTX" : "UNKNOWN ERROR")))))))
+#define TRANSFER_TO_STR(type)   (type == NRF_DRV_TWI_XFER_TX ? "XFER_TX" :                             \
+                                (type == NRF_DRV_TWI_XFER_RX ? "XFER_RX" :                             \
+                                (type == NRF_DRV_TWI_XFER_TXRX ? "XFER_TXRX" :                         \
+                                (type == NRF_DRV_TWI_XFER_TXTX ? "XFER_TXTX" : "UNKNOWN TRANSFER TYPE"))))
+#else //TWI_CONFIG_LOG_ENABLED
+#define EVT_TO_STR(event)           ""
+#define EVT_TO_STR_TWI(event)       ""
+#define EVT_TO_STR_TWIM(event)      ""
+#define TRANSFER_TO_STR(event)      ""
+#define NRF_LOG_LEVEL       0
+#endif //TWI_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+
+
+#define TWI0_IRQ_HANDLER    SPI0_TWI0_IRQHandler
+#define TWI1_IRQ_HANDLER    SPI1_TWI1_IRQHandler
+
+#if (defined(TWIM_IN_USE) && defined(TWI_IN_USE))
+    // TWIM and TWI combined
+    #define CODE_FOR_TWIM(code) if (p_instance->use_easy_dma) { code }
+    #define CODE_FOR_TWI(code)  else { code }
+#elif (defined(TWIM_IN_USE) && !defined(TWI_IN_USE))
+    // TWIM only
+    #define CODE_FOR_TWIM(code) { code }
+    #define CODE_FOR_TWI(code)
+#elif (!defined(TWIM_IN_USE) && defined(TWI_IN_USE))
+    // TWI only
+    #define CODE_FOR_TWIM(code)
+    #define CODE_FOR_TWI(code)  { code }
+#else
+    #error "Wrong configuration."
+#endif
+
+// All interrupt flags
+#define DISABLE_ALL_INT_SHORT  0xFFFFFFFF
+
+#define SCL_PIN_INIT_CONF     ( (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
+                              | (GPIO_PIN_CNF_DRIVE_S0D1     << GPIO_PIN_CNF_DRIVE_Pos) \
+                              | (GPIO_PIN_CNF_PULL_Pullup    << GPIO_PIN_CNF_PULL_Pos)  \
+                              | (GPIO_PIN_CNF_INPUT_Connect  << GPIO_PIN_CNF_INPUT_Pos) \
+                              | (GPIO_PIN_CNF_DIR_Input      << GPIO_PIN_CNF_DIR_Pos))
+#define SDA_PIN_INIT_CONF        SCL_PIN_INIT_CONF
+
+#define SDA_PIN_UNINIT_CONF   ( (GPIO_PIN_CNF_SENSE_Disabled   << GPIO_PIN_CNF_SENSE_Pos) \
+                              | (GPIO_PIN_CNF_DRIVE_H0H1       << GPIO_PIN_CNF_DRIVE_Pos) \
+                              | (GPIO_PIN_CNF_PULL_Disabled    << GPIO_PIN_CNF_PULL_Pos)  \
+                              | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) \
+                              | (GPIO_PIN_CNF_DIR_Input        << GPIO_PIN_CNF_DIR_Pos))
+#define SCL_PIN_UNINIT_CONF      SDA_PIN_UNINIT_CONF
+
+#define SCL_PIN_INIT_CONF_CLR ( (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
+                              | (GPIO_PIN_CNF_DRIVE_S0D1     << GPIO_PIN_CNF_DRIVE_Pos) \
+                              | (GPIO_PIN_CNF_PULL_Pullup    << GPIO_PIN_CNF_PULL_Pos)  \
+                              | (GPIO_PIN_CNF_INPUT_Connect  << GPIO_PIN_CNF_INPUT_Pos) \
+                              | (GPIO_PIN_CNF_DIR_Output     << GPIO_PIN_CNF_DIR_Pos))
+#define SDA_PIN_INIT_CONF_CLR    SCL_PIN_INIT_CONF_CLR
+
+#define HW_TIMEOUT      10000
+
+// Control block - driver instance local data.
+typedef struct
+{
+    nrf_drv_twi_evt_handler_t handler;
+    void *                    p_context;
+    volatile uint32_t         int_mask;
+    nrf_drv_twi_xfer_desc_t   xfer_desc;
+    uint32_t                  flags;
+    uint8_t *                 p_curr_buf;
+    uint8_t                   curr_length;
+    bool                      curr_no_stop;
+    nrf_drv_state_t           state;
+    bool                      error;
+    volatile bool             busy;
+    bool                      repeated;
+    uint8_t                   bytes_transferred;
+    bool                      hold_bus_uninit;
+} twi_control_block_t;
+
+static twi_control_block_t m_cb[ENABLED_TWI_COUNT];
+
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+    #define IRQ_HANDLER_NAME(n) irq_handler_for_instance_##n
+    #define IRQ_HANDLER(n)      static void IRQ_HANDLER_NAME(n)(void)
+
+    #if NRF_MODULE_ENABLED(TWI0)
+        IRQ_HANDLER(0);
+    #endif
+    #if NRF_MODULE_ENABLED(TWI1)
+        IRQ_HANDLER(1);
+    #endif
+    static nrf_drv_irq_handler_t const m_irq_handlers[ENABLED_TWI_COUNT] = {
+    #if NRF_MODULE_ENABLED(TWI0)
+        IRQ_HANDLER_NAME(0),
+    #endif
+    #if NRF_MODULE_ENABLED(TWI1)
+        IRQ_HANDLER_NAME(1),
+    #endif
+    };
+#else
+    #define IRQ_HANDLER(n) void SPI##n##_TWI##n##_IRQHandler(void)
+#endif // NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+
+static ret_code_t twi_process_error(uint32_t errorsrc)
+{
+    ret_code_t ret = NRF_ERROR_INTERNAL;
+
+    if (errorsrc & NRF_TWI_ERROR_OVERRUN)
+    {
+        ret = NRF_ERROR_DRV_TWI_ERR_OVERRUN;
+    }
+
+    if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK)
+    {
+        ret = NRF_ERROR_DRV_TWI_ERR_ANACK;
+    }
+
+    if (errorsrc & NRF_TWI_ERROR_DATA_NACK)
+    {
+        ret = NRF_ERROR_DRV_TWI_ERR_DNACK;
+    }
+
+    return ret;
+}
+
+static void twi_clear_bus(nrf_drv_twi_config_t const * p_config)
+{
+    NRF_GPIO->PIN_CNF[p_config->scl] = SCL_PIN_INIT_CONF;
+    NRF_GPIO->PIN_CNF[p_config->sda] = SDA_PIN_INIT_CONF;
+
+    nrf_gpio_pin_set(p_config->scl);
+    nrf_gpio_pin_set(p_config->sda);
+
+    NRF_GPIO->PIN_CNF[p_config->scl] = SCL_PIN_INIT_CONF_CLR;
+    NRF_GPIO->PIN_CNF[p_config->sda] = SDA_PIN_INIT_CONF_CLR;
+
+    nrf_delay_us(4);
+
+    for (int i = 0; i < 9; i++)
+    {
+        if (nrf_gpio_pin_read(p_config->sda))
+        {
+            if (i == 0)
+            {
+                return;
+            }
+            else
+            {
+                break;
+            }
+        }
+        nrf_gpio_pin_clear(p_config->scl);
+        nrf_delay_us(4);
+        nrf_gpio_pin_set(p_config->scl);
+        nrf_delay_us(4);
+    }
+    nrf_gpio_pin_clear(p_config->sda);
+    nrf_delay_us(4);
+    nrf_gpio_pin_set(p_config->sda);
+}
+
+ret_code_t nrf_drv_twi_init(nrf_drv_twi_t const *        p_instance,
+                            nrf_drv_twi_config_t const * p_config,
+                            nrf_drv_twi_evt_handler_t    event_handler,
+                            void *                       p_context)
+{
+    ASSERT(p_config);
+    ASSERT(p_config->scl != p_config->sda);
+    twi_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
+    ret_code_t err_code;
+
+    if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+    if (nrf_drv_common_per_res_acquire(p_instance->reg.p_twi,
+            m_irq_handlers[p_instance->drv_inst_idx]) != NRF_SUCCESS)
+    {
+        err_code = NRF_ERROR_BUSY;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+#endif // NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+
+    p_cb->handler         = event_handler;
+    p_cb->p_context       = p_context;
+    p_cb->int_mask        = 0;
+    p_cb->repeated        = false;
+    p_cb->busy            = false;
+    p_cb->hold_bus_uninit = p_config->hold_bus_uninit;
+
+    if(p_config->clear_bus_init)
+    {
+        /* Send clocks (max 9) until slave device back from stuck mode */
+        twi_clear_bus(p_config);
+    }
+
+    /* To secure correct signal levels on the pins used by the TWI
+       master when the system is in OFF mode, and when the TWI master is
+       disabled, these pins must be configured in the GPIO peripheral.
+    */
+    NRF_GPIO->PIN_CNF[p_config->scl] = SCL_PIN_INIT_CONF;
+    NRF_GPIO->PIN_CNF[p_config->sda] = SDA_PIN_INIT_CONF;
+
+    CODE_FOR_TWIM
+    (
+        NRF_TWIM_Type * p_twim = p_instance->reg.p_twim;
+        nrf_twim_pins_set(p_twim, p_config->scl, p_config->sda);
+        nrf_twim_frequency_set(p_twim,
+            (nrf_twim_frequency_t)p_config->frequency);
+    )
+    CODE_FOR_TWI
+    (
+        NRF_TWI_Type * p_twi = p_instance->reg.p_twi;
+        nrf_twi_pins_set(p_twi, p_config->scl, p_config->sda);
+        nrf_twi_frequency_set(p_twi,
+            (nrf_twi_frequency_t)p_config->frequency);
+    )
+
+    if (p_cb->handler)
+    {
+        CODE_FOR_TWIM
+        (
+            nrf_drv_common_irq_enable(nrf_drv_get_IRQn((void *)p_instance->reg.p_twim),
+                p_config->interrupt_priority);
+        )
+        CODE_FOR_TWI
+        (
+            nrf_drv_common_irq_enable(nrf_drv_get_IRQn((void *)p_instance->reg.p_twi),
+                p_config->interrupt_priority);
+        )
+    }
+
+    p_cb->state = NRF_DRV_STATE_INITIALIZED;
+
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+void nrf_drv_twi_uninit(nrf_drv_twi_t const * p_instance)
+{
+    twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+
+    if (p_cb->handler)
+    {
+        CODE_FOR_TWIM
+        (
+            nrf_drv_common_irq_disable(nrf_drv_get_IRQn((void *)p_instance->reg.p_twim));
+        )
+        CODE_FOR_TWI
+        (
+            nrf_drv_common_irq_disable(nrf_drv_get_IRQn((void *)p_instance->reg.p_twi));
+        )
+    }
+    nrf_drv_twi_disable(p_instance);
+
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+    nrf_drv_common_per_res_release(p_instance->reg.p_twi);
+#endif
+
+    if (!p_cb->hold_bus_uninit)
+    {
+        CODE_FOR_TWIM
+        (
+        NRF_GPIO->PIN_CNF[p_instance->reg.p_twim->PSEL.SCL] = SCL_PIN_UNINIT_CONF;
+        NRF_GPIO->PIN_CNF[p_instance->reg.p_twim->PSEL.SDA] = SDA_PIN_UNINIT_CONF;
+        )
+        CODE_FOR_TWI
+        (
+        NRF_GPIO->PIN_CNF[p_instance->reg.p_twi->PSELSCL] = SCL_PIN_UNINIT_CONF;
+        NRF_GPIO->PIN_CNF[p_instance->reg.p_twi->PSELSDA] = SDA_PIN_UNINIT_CONF;
+        )
+    }
+
+    p_cb->state = NRF_DRV_STATE_UNINITIALIZED;
+    NRF_LOG_INFO("Instance uninitialized: %d.\r\n", p_instance->drv_inst_idx);
+}
+
+void nrf_drv_twi_enable(nrf_drv_twi_t const * p_instance)
+{
+    twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state == NRF_DRV_STATE_INITIALIZED);
+
+    CODE_FOR_TWIM
+    (
+        NRF_TWIM_Type * p_twim = p_instance->reg.p_twim;
+
+        nrf_twim_enable(p_twim);
+    )
+    CODE_FOR_TWI
+    (
+        NRF_TWI_Type * p_twi = p_instance->reg.p_twi;
+
+        nrf_twi_enable(p_twi);
+    )
+
+    p_cb->state = NRF_DRV_STATE_POWERED_ON;
+    NRF_LOG_INFO("Instance enabled: %d.\r\n", p_instance->drv_inst_idx);
+}
+
+void nrf_drv_twi_disable(nrf_drv_twi_t const * p_instance)
+{
+    twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+
+    CODE_FOR_TWIM
+    (
+        NRF_TWIM_Type * p_twim = p_instance->reg.p_twim;
+        p_cb->int_mask = 0;
+        nrf_twim_int_disable(p_twim, DISABLE_ALL_INT_SHORT);
+        nrf_twim_shorts_disable(p_twim, DISABLE_ALL_INT_SHORT);
+        nrf_twim_disable(p_twim);
+    )
+    CODE_FOR_TWI
+    (
+        NRF_TWI_Type * p_twi = p_instance->reg.p_twi;
+        nrf_twi_int_disable(p_twi, DISABLE_ALL_INT_SHORT);
+        nrf_twi_shorts_disable(p_twi, DISABLE_ALL_INT_SHORT);
+        nrf_twi_disable(p_twi);
+    )
+
+    p_cb->state = NRF_DRV_STATE_INITIALIZED;
+    NRF_LOG_INFO("Instance disabled: %d.\r\n", p_instance->drv_inst_idx);
+}
+
+#ifdef TWI_IN_USE
+static bool twi_send_byte(NRF_TWI_Type  * p_twi,
+                          uint8_t const * p_data,
+                          uint8_t         length,
+                          uint8_t       * p_bytes_transferred,
+                          bool            no_stop)
+{
+    if (*p_bytes_transferred < length)
+    {
+        nrf_twi_txd_set(p_twi, p_data[*p_bytes_transferred]);
+        ++(*p_bytes_transferred);
+    }
+    else
+    {
+        if (no_stop)
+        {
+            nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_SUSPEND);
+            return false;
+        }
+        else
+        {
+            nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STOP);
+        }
+    }
+    return true;
+}
+
+static void twi_receive_byte(NRF_TWI_Type * p_twi,
+                             uint8_t      * p_data,
+                             uint8_t        length,
+                             uint8_t      * p_bytes_transferred)
+{
+    if (*p_bytes_transferred < length)
+    {
+        p_data[*p_bytes_transferred] = nrf_twi_rxd_get(p_twi);
+
+        ++(*p_bytes_transferred);
+
+        if (*p_bytes_transferred == length - 1)
+        {
+            nrf_twi_shorts_set(p_twi, NRF_TWI_SHORT_BB_STOP_MASK);
+        }
+        else if (*p_bytes_transferred == length)
+        {
+            return;
+        }
+
+        nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_RESUME);
+    }
+}
+
+static bool twi_transfer(NRF_TWI_Type  * p_twi,
+                         bool          * p_error,
+                         uint8_t       * p_bytes_transferred,
+                         uint8_t       * p_data,
+                         uint8_t         length,
+                         bool            no_stop)
+{
+    bool do_stop_check = ((*p_error) || ((*p_bytes_transferred) == length));
+
+    if (*p_error)
+    {
+        nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR);
+        nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_TXDSENT);
+        nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_RXDREADY);
+    }
+    else if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_ERROR))
+    {
+        nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR);
+        NRF_LOG_DEBUG("TWI: Event: %s.\r\n", (uint32_t)EVT_TO_STR_TWI(NRF_TWI_EVENT_ERROR));
+        nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STOP);
+        *p_error = true;
+    }
+    else
+    {
+        if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_TXDSENT))
+        {
+            nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_TXDSENT);
+            NRF_LOG_DEBUG("TWI: Event: %s.\r\n", (uint32_t)EVT_TO_STR_TWI(NRF_TWI_EVENT_TXDSENT));
+            if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_ERROR))
+            {
+                nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR);
+                NRF_LOG_DEBUG("TWI: Event: %s.\r\n", (uint32_t)EVT_TO_STR_TWI(NRF_TWI_EVENT_ERROR));
+                nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STOP);
+                *p_error = true;
+            }
+            else
+            {
+                if (!twi_send_byte(p_twi, p_data, length, p_bytes_transferred, no_stop))
+                {
+                    return false;
+                }
+            }
+        }
+        else if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_RXDREADY))
+        {
+            nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_RXDREADY);
+            NRF_LOG_DEBUG("TWI: Event: %s.\r\n", (uint32_t)EVT_TO_STR_TWI(NRF_TWI_EVENT_RXDREADY));
+            if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_ERROR))
+            {
+                NRF_LOG_DEBUG("TWI: Event: %s.\r\n", (uint32_t)EVT_TO_STR_TWI(NRF_TWI_EVENT_ERROR));
+                nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR);
+                nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STOP);
+                *p_error = true;
+            }
+            else
+            {
+                twi_receive_byte(p_twi, p_data, length, p_bytes_transferred);
+            }
+        }
+    }
+
+    if (do_stop_check && nrf_twi_event_check(p_twi, NRF_TWI_EVENT_STOPPED))
+    {
+        nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_STOPPED);
+        NRF_LOG_DEBUG("TWI: Event: %s.\r\n", (uint32_t)EVT_TO_STR_TWI(NRF_TWI_EVENT_STOPPED));
+        return false;
+    }
+
+    return true;
+}
+
+static ret_code_t twi_tx_start_transfer(twi_control_block_t * p_cb,
+                                        NRF_TWI_Type *        p_twi,
+                                        uint8_t const *       p_data,
+                                        uint8_t               length,
+                                        bool                  no_stop)
+{
+    ret_code_t ret_code = NRF_SUCCESS;
+    volatile int32_t hw_timeout;
+    
+    hw_timeout = HW_TIMEOUT;
+    
+    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_STOPPED);
+    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR);
+    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_TXDSENT);
+    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_RXDREADY);
+    nrf_twi_shorts_set(p_twi, 0);
+
+    p_cb->bytes_transferred = 0;
+    p_cb->error             = false;
+
+    // In case TWI is suspended resume its operation.
+    nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_RESUME);
+    nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STARTTX);
+
+    (void)twi_send_byte(p_twi, p_data, length, &p_cb->bytes_transferred, no_stop);
+
+    if (p_cb->handler)
+    {
+        p_cb->int_mask = NRF_TWI_INT_STOPPED_MASK   |
+                        NRF_TWI_INT_ERROR_MASK     |
+                        NRF_TWI_INT_TXDSENT_MASK   |
+                        NRF_TWI_INT_RXDREADY_MASK;
+        nrf_twi_int_enable(p_twi, p_cb->int_mask);
+    }
+    else
+    {
+        while ((hw_timeout > 0) && twi_transfer(p_twi, &p_cb->error, &p_cb->bytes_transferred, (uint8_t *)p_data, length, no_stop))
+        {
+            hw_timeout--;
+        }
+        
+        if (p_cb->error)
+        {
+            uint32_t errorsrc =  nrf_twi_errorsrc_get_and_clear(p_twi);
+
+            if (errorsrc)
+            {
+                ret_code = twi_process_error(errorsrc);
+            }
+        }
+
+        if (hw_timeout <= 0)
+        {
+            nrf_twi_disable(p_twi);
+            nrf_twi_enable(p_twi);
+            ret_code = NRF_ERROR_INTERNAL;                     
+        }
+
+    }
+    return ret_code;
+}
+
+static ret_code_t twi_rx_start_transfer(twi_control_block_t * p_cb,
+                                        NRF_TWI_Type *        p_twi,
+                                        uint8_t const *       p_data,
+                                        uint8_t               length)
+{
+    ret_code_t ret_code = NRF_SUCCESS;
+    volatile int32_t hw_timeout; 
+    
+    hw_timeout = HW_TIMEOUT;
+
+    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_STOPPED);
+    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR);
+    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_TXDSENT);
+    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_RXDREADY);
+
+    p_cb->bytes_transferred = 0;
+    p_cb->error             = false;
+
+    if (length == 1)
+    {
+        nrf_twi_shorts_set(p_twi, NRF_TWI_SHORT_BB_STOP_MASK);
+    }
+    else
+    {
+        nrf_twi_shorts_set(p_twi, NRF_TWI_SHORT_BB_SUSPEND_MASK);
+    }
+    // In case TWI is suspended resume its operation.
+    nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_RESUME);
+    nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STARTRX);
+
+    if (p_cb->handler)
+    {
+        p_cb->int_mask = NRF_TWI_INT_STOPPED_MASK   |
+                        NRF_TWI_INT_ERROR_MASK     |
+                        NRF_TWI_INT_TXDSENT_MASK   |
+                        NRF_TWI_INT_RXDREADY_MASK;
+        nrf_twi_int_enable(p_twi, p_cb->int_mask);
+    }
+    else
+    {
+        while ((hw_timeout > 0) && twi_transfer(p_twi, &p_cb->error, &p_cb->bytes_transferred, (uint8_t*)p_data, length, false))
+        {
+            hw_timeout--;
+        }
+        
+        if (p_cb->error)
+        {
+            uint32_t errorsrc =  nrf_twi_errorsrc_get_and_clear(p_twi);
+
+            if (errorsrc)
+            {
+                ret_code = twi_process_error(errorsrc);
+            }
+        }
+
+        if (hw_timeout <= 0)
+        {
+            nrf_twi_disable(p_twi); 
+            nrf_twi_enable(p_twi);
+            ret_code = NRF_ERROR_INTERNAL;
+        }
+    }
+    return ret_code;
+}
+
+__STATIC_INLINE ret_code_t twi_xfer(twi_control_block_t           * p_cb,
+                                    NRF_TWI_Type                  * p_twi,
+                                    nrf_drv_twi_xfer_desc_t const * p_xfer_desc,
+                                    uint32_t                        flags)
+{
+
+    ret_code_t err_code = NRF_SUCCESS;
+
+    /* Block TWI interrupts to ensure that function is not interrupted by TWI interrupt. */
+    nrf_twi_int_disable(p_twi, DISABLE_ALL_INT_SHORT);
+
+    if (p_cb->busy)
+    {
+        nrf_twi_int_enable(p_twi, p_cb->int_mask);
+        err_code = NRF_ERROR_BUSY;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+    else
+    {
+        p_cb->busy = (NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER & flags) ? false : true;
+    }
+
+    if (flags & NRF_DRV_TWI_FLAG_HOLD_XFER)
+    {
+        err_code = NRF_ERROR_NOT_SUPPORTED;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    p_cb->flags       = flags;
+    p_cb->xfer_desc   = *p_xfer_desc;
+    p_cb->curr_length = p_xfer_desc->primary_length;
+    p_cb->p_curr_buf  = p_xfer_desc->p_primary_buf;
+    nrf_twi_address_set(p_twi, p_xfer_desc->address);
+
+    if (p_xfer_desc->type != NRF_DRV_TWI_XFER_RX)
+    {
+        p_cb->curr_no_stop = ((p_xfer_desc->type == NRF_DRV_TWI_XFER_TX) &&
+                             !(flags & NRF_DRV_TWI_FLAG_TX_NO_STOP)) ? false : true;
+
+        err_code = twi_tx_start_transfer(p_cb, p_twi, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length, p_cb->curr_no_stop);
+    }
+    else
+    {
+        p_cb->curr_no_stop = false;
+
+        err_code = twi_rx_start_transfer(p_cb, p_twi, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length);
+    }
+    if (p_cb->handler == NULL)
+    {
+        p_cb->busy = false;
+    }
+    return err_code;
+}
+#endif
+
+// modification for mbed-os
+#if __MBED__
+bool nrf_drv_twi_is_busy(nrf_drv_twi_t const * p_instance)
+{
+    twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
+    return p_cb->busy;
+}
+#endif
+
+#ifdef TWIM_IN_USE
+
+
+__STATIC_INLINE void twim_list_enable_handle(NRF_TWIM_Type * p_twim, uint32_t flags)
+{
+    if (NRF_DRV_TWI_FLAG_TX_POSTINC & flags)
+    {
+        nrf_twim_tx_list_enable(p_twim);
+    }
+    else
+    {
+        nrf_twim_tx_list_disable(p_twim);
+    }
+
+    if (NRF_DRV_TWI_FLAG_RX_POSTINC & flags)
+    {
+        nrf_twim_rx_list_enable(p_twim);
+    }
+    else
+    {
+        nrf_twim_rx_list_disable(p_twim);
+    }
+}
+__STATIC_INLINE ret_code_t twim_xfer(twi_control_block_t           * p_cb,
+                                     NRF_TWIM_Type                 * p_twim,
+                                     nrf_drv_twi_xfer_desc_t const * p_xfer_desc,
+                                     uint32_t                        flags)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+    nrf_twim_task_t  start_task = NRF_TWIM_TASK_STARTTX;
+    nrf_twim_event_t evt_to_wait = NRF_TWIM_EVENT_STOPPED;
+
+    if (!nrf_drv_is_in_RAM(p_xfer_desc->p_primary_buf))
+    {
+        err_code = NRF_ERROR_INVALID_ADDR;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+    /* Block TWI interrupts to ensure that function is not interrupted by TWI interrupt. */
+    nrf_twim_int_disable(p_twim, DISABLE_ALL_INT_SHORT);
+    if (p_cb->busy)
+    {
+        nrf_twim_int_enable(p_twim, p_cb->int_mask);
+        err_code = NRF_ERROR_BUSY;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+    else
+    {
+        p_cb->busy = ((NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER & flags) ||
+                      (NRF_DRV_TWI_FLAG_REPEATED_XFER & flags)) ? false: true;
+    }
+
+    p_cb->xfer_desc = *p_xfer_desc;
+    p_cb->repeated = (flags & NRF_DRV_TWI_FLAG_REPEATED_XFER) ? true : false;
+    nrf_twim_address_set(p_twim, p_xfer_desc->address);
+
+    nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_STOPPED);
+    nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_ERROR);
+
+    twim_list_enable_handle(p_twim, flags);
+    switch (p_xfer_desc->type)
+    {
+    case NRF_DRV_TWI_XFER_TXTX:
+        ASSERT(!(flags & NRF_DRV_TWI_FLAG_REPEATED_XFER));
+        ASSERT(!(flags & NRF_DRV_TWI_FLAG_HOLD_XFER));
+        ASSERT(!(flags & NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER));
+        if (!nrf_drv_is_in_RAM(p_xfer_desc->p_secondary_buf))
+        {
+            err_code = NRF_ERROR_INVALID_ADDR;
+            NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+            return err_code;
+        }
+        nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_SUSPEND_MASK);
+        nrf_twim_tx_buffer_set(p_twim, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length);
+        nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_TXSTARTED);
+        nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_LASTTX);
+        nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_SUSPENDED);
+        nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
+        nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STARTTX);
+        while (!nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_TXSTARTED))
+        {}
+        NRF_LOG_DEBUG("TWIM: Event: %s.\r\n", (uint32_t)EVT_TO_STR_TWIM(NRF_TWIM_EVENT_TXSTARTED));
+        nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_TXSTARTED);
+        nrf_twim_tx_buffer_set(p_twim, p_xfer_desc->p_secondary_buf, p_xfer_desc->secondary_length);
+        p_cb->int_mask = NRF_TWIM_INT_SUSPENDED_MASK | NRF_TWIM_INT_ERROR_MASK;
+        break;
+    case NRF_DRV_TWI_XFER_TXRX:
+        nrf_twim_tx_buffer_set(p_twim, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length);
+        if (!nrf_drv_is_in_RAM(p_xfer_desc->p_secondary_buf))
+        {
+            err_code = NRF_ERROR_INVALID_ADDR;
+            NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+            return err_code;
+        }
+        nrf_twim_rx_buffer_set(p_twim, p_xfer_desc->p_secondary_buf, p_xfer_desc->secondary_length);
+        nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_STARTRX_MASK |
+                                    NRF_TWIM_SHORT_LASTRX_STOP_MASK);
+        p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK | NRF_TWIM_INT_ERROR_MASK;
+        break;
+    case NRF_DRV_TWI_XFER_TX:
+        nrf_twim_tx_buffer_set(p_twim, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length);
+        if (NRF_DRV_TWI_FLAG_TX_NO_STOP & flags)
+        {
+            nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_SUSPEND_MASK);
+            p_cb->int_mask = NRF_TWIM_INT_SUSPENDED_MASK | NRF_TWIM_INT_ERROR_MASK;
+            nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_SUSPENDED);
+            evt_to_wait = NRF_TWIM_EVENT_SUSPENDED;
+        }
+        else
+        {
+            nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_STOP_MASK);
+            p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK | NRF_TWIM_INT_ERROR_MASK;
+        }
+        nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
+        break;
+    case NRF_DRV_TWI_XFER_RX:
+        nrf_twim_rx_buffer_set(p_twim, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length);
+        nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTRX_STOP_MASK);
+        p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK | NRF_TWIM_INT_ERROR_MASK;
+        start_task = NRF_TWIM_TASK_STARTRX;
+        nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
+        break;
+    default:
+        err_code = NRF_ERROR_INVALID_PARAM;
+        break;
+    }
+
+    if (!(flags & NRF_DRV_TWI_FLAG_HOLD_XFER) && (p_xfer_desc->type != NRF_DRV_TWI_XFER_TXTX))
+    {
+        nrf_twim_task_trigger(p_twim, start_task);
+    }
+
+    if (p_cb->handler)
+    {
+        if (flags & NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER)
+        {
+            p_cb->int_mask = NRF_TWIM_INT_ERROR_MASK;
+        }
+        nrf_twim_int_enable(p_twim, p_cb->int_mask);
+    }
+    else
+    {
+        while (!nrf_twim_event_check(p_twim, evt_to_wait))
+        {
+            if (nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_ERROR))
+            {
+                NRF_LOG_DEBUG("TWIM: Event: %s.\r\n", (uint32_t)EVT_TO_STR_TWIM(NRF_TWIM_EVENT_ERROR));
+                nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_ERROR);
+                nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
+                nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STOP);
+                evt_to_wait = NRF_TWIM_EVENT_STOPPED;
+            }
+        }
+
+        uint32_t errorsrc =  nrf_twim_errorsrc_get_and_clear(p_twim);
+
+        p_cb->busy = false;
+
+        if (errorsrc)
+        {
+            err_code = twi_process_error(errorsrc);
+        }
+    }
+    return err_code;
+}
+#endif
+
+ret_code_t nrf_drv_twi_xfer(nrf_drv_twi_t           const * p_instance,
+                            nrf_drv_twi_xfer_desc_t const * p_xfer_desc,
+                            uint32_t                        flags)
+{
+
+    ret_code_t err_code = NRF_SUCCESS;
+    twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
+
+    // TXRX and TXTX transfers are support only in non-blocking mode.
+    ASSERT( !((p_cb->handler == NULL) && (p_xfer_desc->type == NRF_DRV_TWI_XFER_TXRX)));
+    ASSERT( !((p_cb->handler == NULL) && (p_xfer_desc->type == NRF_DRV_TWI_XFER_TXTX)));
+
+    NRF_LOG_INFO("Transfer type: %s.\r\n", (uint32_t)TRANSFER_TO_STR(p_xfer_desc->type));
+    NRF_LOG_INFO("Transfer buffers length: primary: %d, secondary: %d.\r\n", p_xfer_desc->primary_length, p_xfer_desc->secondary_length);
+    NRF_LOG_DEBUG("Primary buffer data:\r\n");
+    NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length * sizeof(p_xfer_desc->p_primary_buf));
+    NRF_LOG_DEBUG("Secondary buffer data:\r\n");
+    NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_xfer_desc->p_secondary_buf, p_xfer_desc->secondary_length * sizeof(p_xfer_desc->p_secondary_buf));
+
+    CODE_FOR_TWIM
+    (
+
+        err_code = twim_xfer(p_cb, (NRF_TWIM_Type *)p_instance->reg.p_twim, p_xfer_desc, flags);
+    )
+    CODE_FOR_TWI
+    (
+        if ( (NRF_DRV_TWI_FLAG_TX_POSTINC | NRF_DRV_TWI_FLAG_RX_POSTINC) & flags)
+        {
+            err_code = NRF_ERROR_NOT_SUPPORTED;
+            NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+            return err_code;
+        }
+
+        err_code = twi_xfer(p_cb, (NRF_TWI_Type  *)p_instance->reg.p_twi, p_xfer_desc, flags);
+    )
+    NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+ret_code_t nrf_drv_twi_tx(nrf_drv_twi_t const * p_instance,
+                          uint8_t               address,
+                          uint8_t const *       p_data,
+                          uint8_t               length,
+                          bool                  no_stop)
+{
+    nrf_drv_twi_xfer_desc_t xfer = NRF_DRV_TWI_XFER_DESC_TX(address, (uint8_t*)p_data, length);
+
+    return nrf_drv_twi_xfer(p_instance, &xfer, no_stop ? NRF_DRV_TWI_FLAG_TX_NO_STOP : 0);
+}
+
+ret_code_t nrf_drv_twi_rx(nrf_drv_twi_t const * p_instance,
+                          uint8_t               address,
+                          uint8_t *             p_data,
+                          uint8_t               length)
+{
+    nrf_drv_twi_xfer_desc_t xfer = NRF_DRV_TWI_XFER_DESC_RX(address, p_data, length);
+    return nrf_drv_twi_xfer(p_instance, &xfer, 0);
+}
+
+uint32_t nrf_drv_twi_data_count_get(nrf_drv_twi_t const * const p_instance)
+{
+    CODE_FOR_TWIM
+    (
+        ASSERT(false);
+        return 0;
+    )
+    CODE_FOR_TWI
+    (
+        return m_cb[p_instance->drv_inst_idx].bytes_transferred;
+    )
+}
+uint32_t nrf_drv_twi_start_task_get(nrf_drv_twi_t const * p_instance, nrf_drv_twi_xfer_type_t xfer_type)
+{
+    CODE_FOR_TWIM
+    (
+        return (uint32_t)nrf_twim_task_address_get(p_instance->reg.p_twim,
+            (xfer_type != NRF_DRV_TWI_XFER_RX) ? NRF_TWIM_TASK_STARTTX : NRF_TWIM_TASK_STARTRX);
+    )
+    CODE_FOR_TWI
+    (
+        return (uint32_t)nrf_twi_task_address_get(p_instance->reg.p_twi,
+                (xfer_type != NRF_DRV_TWI_XFER_RX) ? NRF_TWI_TASK_STARTTX : NRF_TWI_TASK_STARTRX);
+    )
+}
+
+uint32_t nrf_drv_twi_stopped_event_get(nrf_drv_twi_t const * p_instance)
+{
+    CODE_FOR_TWIM
+    (
+        return (uint32_t)nrf_twim_event_address_get(p_instance->reg.p_twim, NRF_TWIM_EVENT_STOPPED);
+    )
+    CODE_FOR_TWI
+    (
+        return (uint32_t)nrf_twi_event_address_get(p_instance->reg.p_twi, NRF_TWI_EVENT_STOPPED);
+    )
+}
+
+#ifdef TWIM_IN_USE
+static void irq_handler_twim(NRF_TWIM_Type * p_twim, twi_control_block_t * p_cb)
+{
+    ASSERT(p_cb->handler);
+
+    if (nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_ERROR))
+    {
+        nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_ERROR);
+        NRF_LOG_DEBUG("TWIM: Event: %s.\r\n", (uint32_t)EVT_TO_STR_TWIM(NRF_TWIM_EVENT_ERROR));
+        if (!nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_STOPPED))
+        {
+            nrf_twim_int_disable(p_twim, p_cb->int_mask);
+            p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK;
+            nrf_twim_int_enable(p_twim, p_cb->int_mask);
+
+            nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
+            nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STOP);
+            return;
+        }
+    }
+
+    nrf_drv_twi_evt_t event;
+
+    if (nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_STOPPED))
+    {
+        NRF_LOG_DEBUG("TWIM: Event: %s.\r\n", (uint32_t)EVT_TO_STR_TWIM(NRF_TWIM_EVENT_STOPPED));
+        nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_STOPPED);
+        event.xfer_desc = p_cb->xfer_desc;
+        if (p_cb->error)
+        {
+
+            event.xfer_desc.primary_length = (p_cb->xfer_desc.type == NRF_DRV_TWI_XFER_RX) ?
+                (uint8_t)nrf_twim_rxd_amount_get(p_twim) : (uint8_t)nrf_twim_txd_amount_get(p_twim);
+            event.xfer_desc.secondary_length = (p_cb->xfer_desc.type == NRF_DRV_TWI_XFER_TXRX) ?
+                (uint8_t)nrf_twim_rxd_amount_get(p_twim) : (uint8_t)nrf_twim_txd_amount_get(p_twim);
+
+        }
+        nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_LASTTX);
+        nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_LASTRX);
+        if (!p_cb->repeated || p_cb->error)
+        {
+            nrf_twim_shorts_set(p_twim, 0);
+            p_cb->int_mask = 0;
+            nrf_twim_int_disable(p_twim, DISABLE_ALL_INT_SHORT);
+        }
+    }
+    else
+    {
+        nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_SUSPENDED);
+        NRF_LOG_DEBUG("TWIM: Event: %s.\r\n", (uint32_t)EVT_TO_STR_TWIM(NRF_TWIM_EVENT_SUSPENDED));
+        if (p_cb->xfer_desc.type == NRF_DRV_TWI_XFER_TX)
+        {
+            event.xfer_desc = p_cb->xfer_desc;
+            if (!p_cb->repeated)
+            {
+                nrf_twim_shorts_set(p_twim, 0);
+                p_cb->int_mask = 0;
+                nrf_twim_int_disable(p_twim, DISABLE_ALL_INT_SHORT);
+            }
+        }
+        else
+        {
+            nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_STOP_MASK);
+            p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK | NRF_TWIM_INT_ERROR_MASK;
+            nrf_twim_int_disable(p_twim, DISABLE_ALL_INT_SHORT);
+            nrf_twim_int_enable(p_twim, p_cb->int_mask);
+            nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STARTTX);
+            nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
+            return;
+        }
+    }
+
+    uint32_t errorsrc = nrf_twim_errorsrc_get_and_clear(p_twim);
+    if (errorsrc & NRF_TWIM_ERROR_ADDRESS_NACK)
+    {
+        event.type = NRF_DRV_TWI_EVT_ADDRESS_NACK;
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_DRV_TWI_EVT_ADDRESS_NACK));
+    }
+    else if (errorsrc & NRF_TWIM_ERROR_DATA_NACK)
+    {
+        event.type = NRF_DRV_TWI_EVT_DATA_NACK;
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_DRV_TWI_EVT_DATA_NACK));
+    }
+    else
+    {
+        event.type = NRF_DRV_TWI_EVT_DONE;
+        NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_DRV_TWI_EVT_DONE));
+    }
+
+    if (!p_cb->repeated)
+    {
+        p_cb->busy = false;
+    }
+    p_cb->handler(&event, p_cb->p_context);
+}
+#endif // TWIM_IN_USE
+
+#ifdef TWI_IN_USE
+static void irq_handler_twi(NRF_TWI_Type * p_twi, twi_control_block_t * p_cb)
+{
+    ASSERT(p_cb->handler);
+
+    if (twi_transfer(p_twi, &p_cb->error, &p_cb->bytes_transferred, p_cb->p_curr_buf, p_cb->curr_length, p_cb->curr_no_stop ))
+    {
+        return;
+    }
+
+    if (!p_cb->error &&
+        ((p_cb->xfer_desc.type == NRF_DRV_TWI_XFER_TXRX) ||
+         (p_cb->xfer_desc.type == NRF_DRV_TWI_XFER_TXTX)) &&
+        p_cb->p_curr_buf == p_cb->xfer_desc.p_primary_buf)
+    {
+        p_cb->p_curr_buf   = p_cb->xfer_desc.p_secondary_buf;
+        p_cb->curr_length  = p_cb->xfer_desc.secondary_length;
+        p_cb->curr_no_stop = (p_cb->flags & NRF_DRV_TWI_FLAG_TX_NO_STOP);
+
+        if (p_cb->xfer_desc.type == NRF_DRV_TWI_XFER_TXTX)
+        {
+            (void)twi_tx_start_transfer(p_cb, p_twi, p_cb->p_curr_buf, p_cb->curr_length, p_cb->curr_no_stop);
+        }
+        else
+        {
+            (void)twi_rx_start_transfer(p_cb, p_twi, p_cb->p_curr_buf, p_cb->curr_length);
+        }
+    }
+    else
+    {
+        nrf_drv_twi_evt_t event;
+        event.xfer_desc = p_cb->xfer_desc;
+
+        if (p_cb->error)
+        {
+            uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(p_twi);
+            if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK)
+            {
+                event.type = NRF_DRV_TWI_EVT_ADDRESS_NACK;
+                NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_DRV_TWI_EVT_ADDRESS_NACK));
+            }
+            else if (errorsrc & NRF_TWI_ERROR_DATA_NACK)
+            {
+                event.type = NRF_DRV_TWI_EVT_DATA_NACK;
+                NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_DRV_TWI_EVT_DATA_NACK));
+            }
+        }
+        else
+        {
+            event.type = NRF_DRV_TWI_EVT_DONE;
+            NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_DRV_TWI_EVT_DONE));
+        }
+
+        p_cb->busy = false;
+
+        if (!(NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER & p_cb->flags))
+        {
+            p_cb->handler(&event, p_cb->p_context);
+        }
+    }
+
+}
+#endif // TWI_IN_USE
+
+#if NRF_MODULE_ENABLED(TWI0)
+IRQ_HANDLER(0)
+{
+    #if (TWI0_USE_EASY_DMA == 1)
+        irq_handler_twim(NRF_TWIM0,
+    #else
+        irq_handler_twi(NRF_TWI0,
+    #endif
+            &m_cb[TWI0_INSTANCE_INDEX]);
+}
+#endif // NRF_MODULE_ENABLED(TWI0)
+
+#if NRF_MODULE_ENABLED(TWI1)
+IRQ_HANDLER(1)
+{
+    #if (TWI1_USE_EASY_DMA == 1)
+        irq_handler_twim(NRF_TWIM1,
+    #else
+        irq_handler_twi(NRF_TWI1,
+    #endif
+            &m_cb[TWI1_INSTANCE_INDEX]);
+}
+#endif // NRF_MODULE_ENABLED(TWI1)
+#endif // TWI_COUNT
+#endif // NRF_MODULE_ENABLED(TWI)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/twi_master/nrf_drv_twi.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,440 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**@file
+ * @addtogroup nrf_twi Two Wire master interface (TWI/TWIM)
+ * @ingroup    nrf_drivers
+ * @brief      Two Wire master interface (TWI/TWIM) APIs.
+ *
+ *
+ * @defgroup nrf_drv_twi TWIS driver
+ * @{
+ * @ingroup    nrf_twi
+ * @brief      TWI master APIs.
+ */
+#ifndef NRF_DRV_TWI_H__
+#define NRF_DRV_TWI_H__
+
+#include "nordic_common.h"
+#include "sdk_config.h"
+
+// This set of macros makes it possible to exclude parts of code when one type
+// of supported peripherals is not used.
+#if ((TWI0_ENABLED == 1 && TWI0_USE_EASY_DMA == 1) || \
+     (TWI1_ENABLED == 1 && TWI1_USE_EASY_DMA == 1))
+    #define TWIM_IN_USE
+#endif
+#if ((TWI0_ENABLED == 1 && TWI0_USE_EASY_DMA != 1) || \
+     (TWI1_ENABLED == 1 && TWI1_USE_EASY_DMA != 1))
+    #define TWI_IN_USE
+#endif
+
+#include "nrf_twi.h"
+#ifdef TWIM_IN_USE
+    #include "nrf_twim.h"
+#endif
+#include "sdk_errors.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(TWIM_IN_USE)
+    #define NRF_DRV_TWI_PERIPHERAL(id)           \
+        (CONCAT_3(TWI, id, _USE_EASY_DMA) == 1 ? \
+            (void *)CONCAT_2(NRF_TWIM, id)       \
+          : (void *)CONCAT_2(NRF_TWI, id))
+#else
+    #define NRF_DRV_TWI_PERIPHERAL(id)  (void *)CONCAT_2(NRF_TWI, id)
+#endif
+
+
+/**
+ * @brief Structure for the TWI master driver instance.
+ */
+typedef struct
+{
+    union
+    {
+#ifdef TWIM_IN_USE
+        NRF_TWIM_Type * p_twim; ///< Pointer to a structure with TWIM registers.
+#endif
+        NRF_TWI_Type  * p_twi;  ///< Pointer to a structure with TWI registers.
+    } reg;
+    uint8_t drv_inst_idx; ///< Driver instance index.
+    bool    use_easy_dma; ///< True if the peripheral with EasyDMA (TWIM) shall be used.
+} nrf_drv_twi_t;
+
+#define TWI0_INSTANCE_INDEX 0
+#define TWI1_INSTANCE_INDEX TWI0_INSTANCE_INDEX+TWI0_ENABLED
+
+/**
+ * @brief Macro for creating a TWI master driver instance.
+ */
+#define NRF_DRV_TWI_INSTANCE(id)                        \
+{                                                       \
+    .reg          = {NRF_DRV_TWI_PERIPHERAL(id)},       \
+    .drv_inst_idx = CONCAT_3(TWI, id, _INSTANCE_INDEX), \
+    .use_easy_dma = CONCAT_3(TWI, id, _USE_EASY_DMA)    \
+}
+
+/**
+ * @brief Structure for the TWI master driver instance configuration.
+ */
+typedef struct
+{
+    uint32_t            scl;                 ///< SCL pin number.
+    uint32_t            sda;                 ///< SDA pin number.
+    nrf_twi_frequency_t frequency;           ///< TWI frequency.
+    uint8_t             interrupt_priority;  ///< Interrupt priority.
+    bool                clear_bus_init;      ///< Clear bus during init.
+    bool                hold_bus_uninit;     ///< Hold pull up state on gpio pins after uninit.
+} nrf_drv_twi_config_t;
+
+/**
+ * @brief TWI master driver instance default configuration.
+ */
+#define NRF_DRV_TWI_DEFAULT_CONFIG                                             \
+{                                                                              \
+    .frequency          = (nrf_twi_frequency_t)TWI_DEFAULT_CONFIG_FREQUENCY,   \
+    .scl                = 31,                                                  \
+    .sda                = 31,                                                  \
+    .interrupt_priority = TWI_DEFAULT_CONFIG_IRQ_PRIORITY,                     \
+    .clear_bus_init     = TWI_DEFAULT_CONFIG_CLR_BUS_INIT,                     \
+    .hold_bus_uninit    = TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT,                  \
+}
+
+#define NRF_DRV_TWI_FLAG_TX_POSTINC          (1UL << 0) /**< TX buffer address incremented after transfer. */
+#define NRF_DRV_TWI_FLAG_RX_POSTINC          (1UL << 1) /**< RX buffer address incremented after transfer. */
+#define NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER (1UL << 2) /**< Interrupt after each transfer is suppressed, and the event handler is not called. */
+#define NRF_DRV_TWI_FLAG_HOLD_XFER           (1UL << 3) /**< Set up the transfer but do not start it. */
+#define NRF_DRV_TWI_FLAG_REPEATED_XFER       (1UL << 4) /**< Flag indicating that the transfer will be executed multiple times. */
+#define NRF_DRV_TWI_FLAG_TX_NO_STOP          (1UL << 5) /**< Flag indicating that the TX transfer will not end with a stop condition. */
+
+/**
+ * @brief TWI master driver event types.
+ */
+typedef enum
+{
+    NRF_DRV_TWI_EVT_DONE,         ///< Transfer completed event.
+    NRF_DRV_TWI_EVT_ADDRESS_NACK, ///< Error event: NACK received after sending the address.
+    NRF_DRV_TWI_EVT_DATA_NACK     ///< Error event: NACK received after sending a data byte.
+} nrf_drv_twi_evt_type_t;
+
+/**
+ * @brief TWI master driver transfer types.
+ */
+typedef enum
+{
+    NRF_DRV_TWI_XFER_TX,          ///< TX transfer.
+    NRF_DRV_TWI_XFER_RX,          ///< RX transfer.
+    NRF_DRV_TWI_XFER_TXRX,        ///< TX transfer followed by RX transfer with repeated start.
+    NRF_DRV_TWI_XFER_TXTX         ///< TX transfer followed by TX transfer with repeated start.
+} nrf_drv_twi_xfer_type_t;
+
+/**
+ * @brief Structure for a TWI transfer descriptor.
+ */
+typedef struct
+{
+    nrf_drv_twi_xfer_type_t type;             ///< Type of transfer.
+    uint8_t                 address;          ///< Slave address.
+    uint8_t                 primary_length;   ///< Number of bytes transferred.
+    uint8_t                 secondary_length; ///< Number of bytes transferred.
+    uint8_t *               p_primary_buf;    ///< Pointer to transferred data.
+    uint8_t *               p_secondary_buf;  ///< Pointer to transferred data.
+} nrf_drv_twi_xfer_desc_t;
+
+
+/**@brief Macro for setting the TX transfer descriptor. */
+#define NRF_DRV_TWI_XFER_DESC_TX(addr, p_data, length)                 \
+    {                                                                  \
+        .type = NRF_DRV_TWI_XFER_TX,                                   \
+        .address = addr,                                               \
+        .primary_length = length,                                      \
+        .p_primary_buf  = p_data,                                      \
+    }
+
+/**@brief Macro for setting the RX transfer descriptor. */
+#define NRF_DRV_TWI_XFER_DESC_RX(addr, p_data, length)                 \
+    {                                                                  \
+        .type = NRF_DRV_TWI_XFER_RX,                                   \
+        .address = addr,                                               \
+        .primary_length = length,                                      \
+        .p_primary_buf  = p_data,                                      \
+    }
+
+/**@brief Macro for setting the TXRX transfer descriptor. */
+#define NRF_DRV_TWI_XFER_DESC_TXRX(addr, p_tx, tx_len, p_rx, rx_len)   \
+    {                                                                  \
+        .type = NRF_DRV_TWI_XFER_TXRX,                                 \
+        .address = addr,                                               \
+        .primary_length   = tx_len,                                    \
+        .secondary_length = rx_len,                                    \
+        .p_primary_buf    = p_tx,                                      \
+        .p_secondary_buf  = p_rx,                                      \
+    }
+
+/**@brief Macro for setting the TXTX transfer descriptor. */
+#define NRF_DRV_TWI_XFER_DESC_TXTX(addr, p_tx, tx_len, p_tx2, tx_len2) \
+    {                                                                  \
+        .type = NRF_DRV_TWI_XFER_TXTX,                                 \
+        .address = addr,                                               \
+        .primary_length   = tx_len,                                    \
+        .secondary_length = tx_len2,                                   \
+        .p_primary_buf    = p_tx,                                      \
+        .p_secondary_buf  = p_tx2,                                     \
+    }
+
+/**
+ * @brief Structure for a TWI event.
+ */
+typedef struct
+{
+    nrf_drv_twi_evt_type_t  type;      ///< Event type.
+    nrf_drv_twi_xfer_desc_t xfer_desc; ///< Transfer details.
+} nrf_drv_twi_evt_t;
+
+/**
+ * @brief TWI event handler prototype.
+ */
+typedef void (* nrf_drv_twi_evt_handler_t)(nrf_drv_twi_evt_t const * p_event,
+                                           void *                    p_context);
+
+/**
+ * @brief Function for initializing the TWI driver instance.
+ *
+ * @param[in] p_instance      Pointer to the driver instance structure.
+ * @param[in] p_config        Initial configuration. If NULL, the default configuration is used.
+ * @param[in] event_handler   Event handler provided by the user. If NULL, blocking mode is enabled.
+ * @param[in] p_context       Context passed to event handler.
+ *
+ * @retval NRF_SUCCESS             If initialization was successful.
+ * @retval NRF_ERROR_INVALID_STATE If the driver is in invalid state.
+ * @retval NRF_ERROR_BUSY          If some other peripheral with the same
+ *                                 instance ID is already in use. This is
+ *                                 possible only if PERIPHERAL_RESOURCE_SHARING_ENABLED
+ *                                 is set to a value other than zero.
+ */
+ret_code_t nrf_drv_twi_init(nrf_drv_twi_t const *        p_instance,
+                            nrf_drv_twi_config_t const * p_config,
+                            nrf_drv_twi_evt_handler_t    event_handler,
+                            void *                       p_context);
+
+/**
+ * @brief Function for uninitializing the TWI instance.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ */
+void nrf_drv_twi_uninit(nrf_drv_twi_t const * p_instance);
+
+/**
+ * @brief Function for enabling the TWI instance.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ */
+void nrf_drv_twi_enable(nrf_drv_twi_t const * p_instance);
+
+/**
+ * @brief Function for disabling the TWI instance.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ */
+void nrf_drv_twi_disable(nrf_drv_twi_t const * p_instance);
+
+/**
+ * @brief Function for sending data to a TWI slave.
+ *
+ * The transmission will be stopped when an error occurs. If a transfer is ongoing,
+ * the function returns the error code @ref NRF_ERROR_BUSY.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] address    Address of a specific slave device (only 7 LSB).
+ * @param[in] p_data     Pointer to a transmit buffer.
+ * @param[in] length     Number of bytes to send.
+ * @param[in] no_stop    If set, the stop condition is not generated on the bus
+ *                       after the transfer has completed successfully (allowing
+ *                       for a repeated start in the next transfer).
+ *
+ * @retval NRF_SUCCESS                  If the procedure was successful.
+ * @retval NRF_ERROR_BUSY               If the driver is not ready for a new transfer.
+ * @retval NRF_ERROR_INTERNAL           If an error was detected by hardware.
+ * @retval NRF_ERROR_INVALID_ADDR       If the EasyDMA is used and memory adress in not in RAM.
+ * @retval NRF_ERROR_DRV_TWI_ERR_ANACK  If NACK received after sending the address.
+ * @retval NRF_ERROR_DRV_TWI_ERR_DNACK  If NACK received after sending a data byte.
+ */
+ret_code_t nrf_drv_twi_tx(nrf_drv_twi_t const * p_instance,
+                          uint8_t               address,
+                          uint8_t const *       p_data,
+                          uint8_t               length,
+                          bool                  no_stop);
+
+/**
+ * @brief Function for reading data from a TWI slave.
+ *
+ * The transmission will be stopped when an error occurs. If a transfer is ongoing,
+ * the function returns the error code @ref NRF_ERROR_BUSY.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] address    Address of a specific slave device (only 7 LSB).
+ * @param[in] p_data     Pointer to a receive buffer.
+ * @param[in] length     Number of bytes to be received.
+ *
+ * @retval NRF_SUCCESS                    If the procedure was successful.
+ * @retval NRF_ERROR_BUSY                 If the driver is not ready for a new transfer.
+ * @retval NRF_ERROR_INTERNAL             If an error was detected by hardware.
+ * @retval NRF_ERROR_DRV_TWI_ERR_OVERRUN  If the unread data was replaced by new data
+ * @retval NRF_ERROR_DRV_TWI_ERR_ANACK    If NACK received after sending the address.
+ * @retval NRF_ERROR_DRV_TWI_ERR_DNACK    If NACK received after sending a data byte.
+ */
+ret_code_t nrf_drv_twi_rx(nrf_drv_twi_t const * p_instance,
+                          uint8_t               address,
+                          uint8_t *             p_data,
+                          uint8_t               length);
+
+/**
+ * @brief Function for preparing a TWI transfer.
+ *
+ * The following transfer types can be configured (@ref nrf_drv_twi_xfer_desc_t::type):
+ * - @ref NRF_DRV_TWI_XFER_TXRX<span></span>: Write operation followed by a read operation (without STOP condition in between).
+ * - @ref NRF_DRV_TWI_XFER_TXTX<span></span>: Write operation followed by a write operation (without STOP condition in between).
+ * - @ref NRF_DRV_TWI_XFER_TX<span></span>:   Write operation (with or without STOP condition).
+ * - @ref NRF_DRV_TWI_XFER_RX<span></span>:   Read operation  (with STOP condition).
+ *
+ * Additional options are provided using the flags parameter:
+ * - @ref NRF_DRV_TWI_FLAG_TX_POSTINC and @ref NRF_DRV_TWI_FLAG_RX_POSTINC<span></span>: Post-incrementation of buffer addresses. Supported only by TWIM.
+ * - @ref NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER<span></span>: No user event handler after transfer completion. In most cases, this also means no interrupt at the end of the transfer.
+ * - @ref NRF_DRV_TWI_FLAG_HOLD_XFER<span></span>: Driver is not starting the transfer. Use this flag if the transfer is triggered externally by PPI. Supported only by TWIM.
+ *   Use @ref nrf_drv_twi_start_task_get to get the address of the start task.
+ * - @ref NRF_DRV_TWI_FLAG_REPEATED_XFER<span></span>: Prepare for repeated transfers. You can set up a number of transfers that will be triggered externally (for example by PPI).
+ *   An example is a TXRX transfer with the options @ref NRF_DRV_TWI_FLAG_RX_POSTINC, @ref NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER, and @ref NRF_DRV_TWI_FLAG_REPEATED_XFER.
+ *   After the transfer is set up, a set of transfers can be triggered by PPI that will read, for example, the same register of an
+ *   external component and put it into a RAM buffer without any interrupts. @ref nrf_drv_twi_stopped_event_get can be used to get the
+ *   address of the STOPPED event, which can be used to count the number of transfers. If @ref NRF_DRV_TWI_FLAG_REPEATED_XFER is used,
+ *   the driver does not set the driver instance into busy state, so you must ensure that the next transfers are set up
+ *   when TWIM is not active. Supported only by TWIM.
+ * - @ref NRF_DRV_TWI_FLAG_TX_NO_STOP<span></span>: No stop condition after TX transfer.
+ *
+ * @note
+ * Some flag combinations are invalid:
+ * - @ref NRF_DRV_TWI_FLAG_TX_NO_STOP with @ref nrf_drv_twi_xfer_desc_t::type different than @ref NRF_DRV_TWI_XFER_TX
+ * - @ref NRF_DRV_TWI_FLAG_REPEATED_XFER with @ref nrf_drv_twi_xfer_desc_t::type set to @ref NRF_DRV_TWI_XFER_TXTX
+ *
+ * If @ref nrf_drv_twi_xfer_desc_t::type is set to @ref NRF_DRV_TWI_XFER_TX and the @ref NRF_DRV_TWI_FLAG_TX_NO_STOP and @ref NRF_DRV_TWI_FLAG_REPEATED_XFER
+ * flags are set, two tasks must be used to trigger a transfer: TASKS_RESUME followed by TASKS_STARTTX. If no stop condition is generated,
+ * TWIM is in SUSPENDED state. Therefore, it must be resumed before the transfer can be started.
+ *
+ * @note
+ * This function should be used only if the instance is configured to work in non-blocking mode. If the function is used in blocking mode, the driver asserts.
+ * @note If you are using this function with TWI, the only supported flag is @ref NRF_DRV_TWI_FLAG_TX_NO_STOP. All other flags require TWIM.
+  *
+ * @param[in] p_instance        Pointer to the driver instance structure.
+ * @param[in] p_xfer_desc       Pointer to the transfer descriptor.
+ * @param[in] flags             Transfer options (0 for default settings).
+ *
+ * @retval NRF_SUCCESS                    If the procedure was successful.
+ * @retval NRF_ERROR_BUSY                 If the driver is not ready for a new transfer.
+ * @retval NRF_ERROR_NOT_SUPPORTED        If the provided parameters are not supported.
+ * @retval NRF_ERROR_INTERNAL             If an error was detected by hardware.
+ * @retval NRF_ERROR_INVALID_ADDR         If the EasyDMA is used and memory adress in not in RAM
+ * @retval NRF_ERROR_DRV_TWI_ERR_OVERRUN  If the unread data was replaced by new data (TXRX and RX)
+ * @retval NRF_ERROR_DRV_TWI_ERR_ANACK    If NACK received after sending the address.
+ * @retval NRF_ERROR_DRV_TWI_ERR_DNACK    If NACK received after sending a data byte.
+ */
+ret_code_t nrf_drv_twi_xfer(nrf_drv_twi_t           const * p_instance,
+                            nrf_drv_twi_xfer_desc_t const * p_xfer_desc,
+                            uint32_t                        flags);
+
+// modification for mbed-os
+#if __MBED__
+/**
+ * @brief Function for checking the TWI driver state.
+ *
+ * @param[in] p_instance TWI instance.
+ *
+ * @retval true  If the TWI driver is currently busy performing a transfer.
+ * @retval false If the TWI driver is ready for a new transfer.
+ */
+bool nrf_drv_twi_is_busy(nrf_drv_twi_t const * p_instance);
+#endif
+
+/**
+ * @brief Function for getting the transferred data count.
+ *
+ * This function provides valid results only in legacy mode.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ *
+ * @return     Data count.
+ */
+uint32_t nrf_drv_twi_data_count_get(nrf_drv_twi_t const * const p_instance);
+
+/**
+ * @brief Function for returning the address of a TWI/TWIM start task.
+ *
+ * This function should be used if @ref nrf_drv_twi_xfer was called with the flag @ref NRF_DRV_TWI_FLAG_HOLD_XFER.
+ * In that case, the transfer is not started by the driver, but it must be started externally by PPI.
+ *
+ * @param[in]  p_instance Pointer to the driver instance structure.
+ * @param[in]  xfer_type  Transfer type used in the last call of the @ref nrf_drv_twi_xfer function.
+ *
+ * @return     Start task address (TX or RX) depending on the value of xfer_type.
+ */
+uint32_t nrf_drv_twi_start_task_get(nrf_drv_twi_t const * p_instance, nrf_drv_twi_xfer_type_t xfer_type);
+
+/**
+ * @brief Function for returning the address of a STOPPED TWI/TWIM event.
+ *
+ * A STOPPED event can be used to detect the end of a transfer if the @ref NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER
+ * option is used.
+ *
+ * @param[in]  p_instance Pointer to the driver instance structure.
+ *
+ * @return     STOPPED event address.
+ */
+uint32_t nrf_drv_twi_stopped_event_get(nrf_drv_twi_t const * p_instance);
+/**
+ *@}
+ **/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_DRV_TWI_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/twis_slave/nrf_drv_twis.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,940 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(TWIS)
+#define ENABLED_TWIS_COUNT (TWIS0_ENABLED+TWIS1_ENABLED)
+#if ENABLED_TWIS_COUNT
+#include "nrf_drv_twis.h"
+#include "nrf_assert.h"
+#include "app_util_platform.h"
+#include "compiler_abstraction.h"
+
+#define NRF_LOG_MODULE_NAME "TWIS"
+
+#if TWIS_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       TWIS_CONFIG_LOG_LEVEL
+#define NRF_LOG_INFO_COLOR  TWIS_CONFIG_INFO_COLOR
+#define NRF_LOG_DEBUG_COLOR TWIS_CONFIG_DEBUG_COLOR
+#define EVT_TO_STR(event)   (event == NRF_TWIS_EVENT_STOPPED ? "NRF_TWIS_EVENT_STOPPED" :               \
+                            (event == NRF_TWIS_EVENT_ERROR ? "NRF_TWIS_EVENT_ERROR" :                   \
+                            (event == NRF_TWIS_EVENT_RXSTARTED ? "NRF_TWIS_EVENT_RXSTARTED" :           \
+                            (event == NRF_TWIS_EVENT_TXSTARTED ? "NRF_TWIS_EVENT_TXSTARTED" :           \
+                            (event == NRF_TWIS_EVENT_WRITE ? "NRF_TWIS_EVENT_WRITE" :                   \
+                            (event == NRF_TWIS_EVENT_READ ? "NRF_TWIS_EVENT_READ" : "UNKNOWN EVENT"))))))
+#else //TWIS_CONFIG_LOG_ENABLED
+#define EVT_TO_STR(event)   ""
+#define NRF_LOG_LEVEL       0
+#endif //TWIS_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+
+/**
+ * @internal
+ * @ingroup lib_twis_drv
+ * @defgroup lib_twis_drv_ivars Software controlled TWI Slave internal variables
+ *
+ * Internal variables for TWIS.
+ * @{
+ */
+
+/**
+ * @brief Actual state of internal state machine
+ *
+ * Current substate of powered on state.
+ */
+typedef enum
+{
+    NRF_DRV_TWIS_SUBSTATE_IDLE,          ///< No ongoing transmission
+    NRF_DRV_TWIS_SUBSTATE_READ_WAITING,  ///< Read request received, waiting for data
+    NRF_DRV_TWIS_SUBSTATE_READ_PENDING,  ///< Reading is actually pending (data sending)
+    NRF_DRV_TWIS_SUBSTATE_WRITE_WAITING, ///< Write request received, waiting for data buffer
+    NRF_DRV_TWIS_SUBSTATE_WRITE_PENDING, ///< Writing is actually pending (data receiving)
+}nrf_drv_twis_substate_t;
+
+/**
+ * @brief Constant instance part
+ *
+ * Instance data that have not to change.
+ * It may be placed in FLASH memory.
+ */
+typedef struct
+{
+    NRF_TWIS_Type * const p_reg; ///< Peripheral registry address
+} nrf_drv_twis_const_inst_t;
+
+/**
+ * @brief Variable instance part
+ *
+ * There are all informations for the instance that may change.
+ */
+typedef struct
+{
+    nrf_drv_state_t                  state;      ///< Actual driver state
+    volatile nrf_drv_twis_substate_t substate;   ///< Actual driver substate
+    nrf_drv_twis_event_handler_t     ev_handler; ///< Event handler functiomn
+    volatile uint32_t                error;      ///< Internal error flags
+                                                 /**< Internal copy of hardware errors flags merged
+                                                  *   with specific internal driver errors flags.
+                                                  *
+                                                  *   @note This value can be changed in the interrupt
+                                                  *   and cleared in the main program.
+                                                  *   Always use Atomic load-store when updating
+                                                  *   this value in main loop.
+                                                  */
+}nrf_drv_twis_var_inst_t;
+
+
+/** The constant instance part implementation */
+static const nrf_drv_twis_const_inst_t m_const_inst[ENABLED_TWIS_COUNT] =
+{
+    #define X(n)  { .p_reg = NRF_TWIS##n },
+    #include "nrf_drv_twis_inst.def"
+};
+
+/** The variable instance part implementation */
+static nrf_drv_twis_var_inst_t m_var_inst[ENABLED_TWIS_COUNT] =
+{
+    #define X(n) { .state      = NRF_DRV_STATE_UNINITIALIZED, \
+                   .substate   = NRF_DRV_TWIS_SUBSTATE_IDLE, \
+                   .ev_handler = NULL, \
+                   .error      = 0 },
+    #include "nrf_drv_twis_inst.def"
+};
+
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+    #define IRQ_HANDLER_NAME(n) irq_handler_for_instance_##n
+    #define IRQ_HANDLER(n)      static void IRQ_HANDLER_NAME(n)(void)
+
+    #if NRF_MODULE_ENABLED(TWIS0)
+        IRQ_HANDLER(0);
+    #endif
+    #if NRF_MODULE_ENABLED(TWIS1)
+        IRQ_HANDLER(1);
+    #endif
+    static nrf_drv_irq_handler_t const m_irq_handlers[ENABLED_TWIS_COUNT] = {
+    #if NRF_MODULE_ENABLED(TWIS0)
+        IRQ_HANDLER_NAME(0),
+    #endif
+    #if NRF_MODULE_ENABLED(TWIS1)
+        IRQ_HANDLER_NAME(1),
+    #endif
+    };
+#else
+    #define IRQ_HANDLER(n) \
+        void SPIM##n##_SPIS##n##_TWIM##n##_TWIS##n##_SPI##n##_TWI##n##_IRQHandler(void)
+#endif // NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+
+/**
+ * @brief State processing semaphore
+ *
+ * There are semaphores used when when working in synchronous mode (without interrupts activated).
+ * @note
+ * In synchronous mode before every state checking the state machine is executed.
+ * But the situation where state checking function is called from main task and in the same from
+ * interrupt task has to be considered.
+ * In such a situation the @ref nrf_drv_twis_state_machine function may be interrupted by second
+ * call to the same function.
+ * If in this second call any event will be detected it may be lost because new substate would be
+ * overwritten when interrupted function finishes.
+ * In the same time information about event would be lost because it is cleared in interrupting
+ * function.
+ * @note
+ * To make situation described above safe, simple semaphore is implemented.
+ * It is just a binary flag that informs that state machine is actually executing and should not
+ * be processed in any interrupting function.
+ * Because of how it is used no atomic instructions are required to support this kind of semaphore.
+ * It is not waitable semaphore - function executed or not depending of its state.
+ */
+static uint8_t m_sm_semaphore[ENABLED_TWIS_COUNT];
+
+/**
+ * @brief Used interrupts mask
+ *
+ * Mask for all interrupts used by this library
+ */
+static const uint32_t m_used_ints_mask =
+        NRF_TWIS_INT_STOPPED_MASK   |
+        NRF_TWIS_INT_ERROR_MASK     |
+        NRF_TWIS_INT_RXSTARTED_MASK |
+        NRF_TWIS_INT_TXSTARTED_MASK |
+        NRF_TWIS_INT_WRITE_MASK     |
+        NRF_TWIS_INT_READ_MASK;
+
+
+/** @} */ /* End  of lib_driver_twis_slave_ivars */
+
+/**
+ * @internal
+ * @ingroup lib_twis_drv
+ * @defgroup lib_twis_drv_ifunc Software controlled TWI Slave auxiliary internal functions
+ *
+ * Internal variables for TWIS.
+ * @{
+ */
+
+/**
+ * @brief Clear all  events
+ *
+ * Function clears all actually pending events
+ */
+static void nrf_drv_twis_clear_all_events(NRF_TWIS_Type * const p_reg)
+{
+    /* Clear all events */
+    nrf_twis_event_clear(p_reg, NRF_TWIS_EVENT_STOPPED);
+    nrf_twis_event_clear(p_reg, NRF_TWIS_EVENT_ERROR);
+    nrf_twis_event_clear(p_reg, NRF_TWIS_EVENT_RXSTARTED);
+    nrf_twis_event_clear(p_reg, NRF_TWIS_EVENT_TXSTARTED);
+    nrf_twis_event_clear(p_reg, NRF_TWIS_EVENT_WRITE);
+    nrf_twis_event_clear(p_reg, NRF_TWIS_EVENT_READ);
+}
+
+/**
+ * @brief Reset all the registers to known state
+ *
+ * This function clears all registers that requires it to known state.
+ * TWIS is left disabled after this function.
+ * All events are cleared.
+ * @param[out] p_reg TWIS to reset register address
+ */
+static inline void nrf_drv_twis_swreset(NRF_TWIS_Type * const p_reg)
+{
+    /* Disable TWIS */
+    nrf_twis_disable(p_reg);
+
+    /* Disconnect pins */
+    nrf_twis_pins_set(p_reg, ~0U, ~0U);
+
+    /* Disable interrupt global for the instance */
+    nrf_drv_common_irq_disable(nrf_drv_get_IRQn(p_reg));
+
+    /* Disable interrupts */
+    nrf_twis_int_disable(p_reg, ~0U);
+}
+
+/**
+ * @brief Configure pin
+ *
+ * Function configures selected for work as SDA or SCL.
+ * @param pin Pin number to configure
+ */
+static inline void nrf_drv_twis_config_pin(uint32_t pin, nrf_gpio_pin_pull_t pull)
+{
+    nrf_gpio_cfg(pin,
+                 NRF_GPIO_PIN_DIR_INPUT,
+                 NRF_GPIO_PIN_INPUT_DISCONNECT,
+                 pull,
+                 NRF_GPIO_PIN_S0D1,
+                 NRF_GPIO_PIN_NOSENSE);
+}
+
+/**
+ * @brief Call event handler
+ *
+ * Function that calls event handler.
+ * The event handler would be only called if its value is != NULL.
+ * @param     instNr Driver instance number that has called this runtime.
+ * @param[in] pev    Event structure to pass to event handler
+ * @note
+ * Remember about possible multithreading.
+ * It is acceptable to call old event function if it was already disabled.
+ * What is unacceptable is jump into NULL pointer.
+ */
+static void nrf_drv_call_event_handler(uint8_t instNr, nrf_drv_twis_evt_t const * const pev)
+{
+    nrf_drv_twis_event_handler_t evh = m_var_inst[instNr].ev_handler;
+    if (NULL != evh)
+    {
+        evh(pev);
+    }
+}
+
+/**
+ * @brief Auxiliary function for getting event state on right bit possition
+ *
+ * This function calls @ref nrf_twis_event_get function but the the result
+ * is shifted to match INTEN register scheme.
+ *
+ * @param[in,out] p_reg TWIS to read  event from
+ * @param ev  Event code
+ *
+ * @return Selected event state shifted by @ref nrf_drv_event_to_bitpos
+ *
+ * @sa nrf_twis_event_get
+ * @sa nrf_drv_event_to_bitpos
+ */
+static inline uint32_t nrf_drv_twis_event_bit_get(NRF_TWIS_Type * const p_reg, nrf_twis_event_t ev)
+{
+    return (uint32_t)nrf_twis_event_get_and_clear(p_reg, ev) << nrf_drv_event_to_bitpos(ev);
+}
+
+/**
+ * @brief Auxiliary function for checking event bit inside given flags value
+ *
+ * Function used here to check presence of the event inside given flags value.
+ * It transforms given event to bit possition and then checks if in given variable it is cleared.
+ *
+ * @param flags Flags to test
+ * @param ev Event code
+ *
+ * @retval true Flag for selected event is set
+ * @retval false Flag for selected event is cleared
+ */
+static inline bool nrf_drv_twis_check_bit(uint32_t flags, nrf_twis_event_t ev)
+{
+    return 0 != (flags & (1U<<nrf_drv_event_to_bitpos(ev)));
+}
+
+/**
+ * @brief Auxiliary function for clearing event bit in given flags value
+ *
+ * Function used to clear selected event bit.
+ *
+ * @param flags Flags to process
+ * @param ev    Event code to clear
+ *
+ * @return Value @em flags with cleared event bit that matches given @em ev
+ */
+static inline uint32_t nrf_drv_twis_clear_bit(uint32_t flags, nrf_twis_event_t ev)
+{
+    return flags & ~(1U<<nrf_drv_event_to_bitpos(ev));
+}
+
+/**
+ * @brief Auxiliary function for error processing
+ *
+ * Function called when in current substate the event apears and it cannot be processed.
+ * It should be called also on ERROR event.
+ * If given @em error parameter has zero value the @ref NRF_DRV_TWIS_ERROR_UNEXPECTED_EVENT
+ * would be set.
+ *
+ * @param instNr Instance number
+ * @param ev     What error event raport to event handler
+ * @param error  Error flags
+ */
+static inline void nrf_drv_twis_process_error(
+        uint8_t instNr,
+        nrf_drv_twis_evt_type_t ev,
+        uint32_t error)
+{
+    if (0 == error)
+        error = NRF_DRV_TWIS_ERROR_UNEXPECTED_EVENT;
+    nrf_drv_twis_evt_t evdata;
+    evdata.type = ev;
+    evdata.data.error = error;
+
+    m_var_inst[instNr].error |= error;
+
+    nrf_drv_call_event_handler(instNr, &evdata);
+}
+
+
+/**
+ * @brief State machine main function
+ *
+ * State machine function that reacts on events.
+ * This function gets all events and reacts on them only if there is any event detected.
+ * It makes it possible to use it either in interrupt or in polling mode.
+ * @param instNr Driver instance number that has called this runtime.
+ */
+static void nrf_drv_twis_state_machine(uint8_t instNr)
+{
+    if (!TWIS_NO_SYNC_MODE)
+    {
+        /* Exclude parallel processing of this function */
+        if (m_sm_semaphore[instNr])
+        {
+            return;
+        }
+        m_sm_semaphore[instNr] = 1;
+    }
+
+    NRF_TWIS_Type * const p_reg = m_const_inst[instNr].p_reg;
+    /* Event data structure to be passed into event handler */
+    nrf_drv_twis_evt_t evdata;
+    /* Current substate copy  */
+    nrf_drv_twis_substate_t substate = m_var_inst[instNr].substate;
+    /* Event flags */
+    uint32_t ev = 0;
+
+    /* Get all events */
+    ev |= nrf_drv_twis_event_bit_get(p_reg, NRF_TWIS_EVENT_STOPPED);
+    ev |= nrf_drv_twis_event_bit_get(p_reg, NRF_TWIS_EVENT_ERROR);
+    ev |= nrf_drv_twis_event_bit_get(p_reg, NRF_TWIS_EVENT_RXSTARTED);
+    ev |= nrf_drv_twis_event_bit_get(p_reg, NRF_TWIS_EVENT_TXSTARTED);
+    ev |= nrf_drv_twis_event_bit_get(p_reg, NRF_TWIS_EVENT_WRITE);
+    ev |= nrf_drv_twis_event_bit_get(p_reg, NRF_TWIS_EVENT_READ);
+
+    /* State machine */
+    while (0 != ev)
+    {
+        switch (substate)
+        {
+        case NRF_DRV_TWIS_SUBSTATE_IDLE:
+            if (nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_STOPPED))
+            {
+                /* Stopped event is always allowed in IDLE state - just ignore */
+                ev = nrf_drv_twis_clear_bit(ev, NRF_TWIS_EVENT_STOPPED);
+            }
+            else if (nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_READ))
+            {
+                evdata.type = TWIS_EVT_READ_REQ;
+                if (nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_TXSTARTED))
+                {
+                    substate = NRF_DRV_TWIS_SUBSTATE_READ_PENDING;
+                    evdata.data.buf_req = false;
+                }
+                else
+                {
+                    substate = NRF_DRV_TWIS_SUBSTATE_READ_WAITING;
+                    evdata.data.buf_req = true;
+                }
+                nrf_drv_call_event_handler(instNr, &evdata);
+                ev = nrf_drv_twis_clear_bit(ev, NRF_TWIS_EVENT_READ);
+                ev = nrf_drv_twis_clear_bit(ev, NRF_TWIS_EVENT_TXSTARTED);
+                ev = nrf_drv_twis_clear_bit(ev, NRF_TWIS_EVENT_WRITE);
+                ev = nrf_drv_twis_clear_bit(ev, NRF_TWIS_EVENT_RXSTARTED);
+            }
+            else if (nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_WRITE))
+            {
+                evdata.type = TWIS_EVT_WRITE_REQ;
+                if (nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_RXSTARTED))
+                {
+                    substate = NRF_DRV_TWIS_SUBSTATE_WRITE_PENDING;
+                    evdata.data.buf_req = false;
+                }
+                else
+                {
+                    substate = NRF_DRV_TWIS_SUBSTATE_WRITE_WAITING;
+                    evdata.data.buf_req = true;
+                }
+                nrf_drv_call_event_handler(instNr, &evdata);
+                ev = nrf_drv_twis_clear_bit(ev, NRF_TWIS_EVENT_READ);
+                ev = nrf_drv_twis_clear_bit(ev, NRF_TWIS_EVENT_TXSTARTED);
+                ev = nrf_drv_twis_clear_bit(ev, NRF_TWIS_EVENT_WRITE);
+                ev = nrf_drv_twis_clear_bit(ev, NRF_TWIS_EVENT_RXSTARTED);
+            }
+            else
+            {
+                nrf_drv_twis_process_error(instNr, TWIS_EVT_GENERAL_ERROR, nrf_twis_error_source_get_and_clear(p_reg));
+                ev = 0;
+            }
+            break;
+        case NRF_DRV_TWIS_SUBSTATE_READ_WAITING:
+            if (nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_TXSTARTED) ||
+               nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_WRITE)     ||
+               nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_READ)      ||
+               nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_STOPPED))
+            {
+                substate = NRF_DRV_TWIS_SUBSTATE_READ_PENDING;
+                /* Any other bits requires further processing in PENDING substate */
+                ev = nrf_drv_twis_clear_bit(ev, NRF_TWIS_EVENT_TXSTARTED);
+            }
+            else
+            {
+                nrf_drv_twis_process_error(instNr, TWIS_EVT_READ_ERROR, nrf_twis_error_source_get_and_clear(p_reg));
+                substate = NRF_DRV_TWIS_SUBSTATE_IDLE;
+                ev = 0;
+            }
+            break;
+        case NRF_DRV_TWIS_SUBSTATE_READ_PENDING:
+            if (nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_WRITE)||
+               nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_READ) ||
+               nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_STOPPED))
+            {
+                evdata.type = TWIS_EVT_READ_DONE;
+                evdata.data.tx_amount = nrf_twis_tx_amount_get(p_reg);
+                NRF_LOG_INFO("Transfer rx_len:%d\r\n", evdata.data.tx_amount);
+                NRF_LOG_DEBUG("Tx data:\r\n");
+                NRF_LOG_HEXDUMP_DEBUG((uint8_t *)p_reg->TXD.PTR, evdata.data.tx_amount * sizeof(p_reg->TXD.PTR));
+                nrf_drv_call_event_handler(instNr, &evdata);
+                /* Go to idle and repeat the state machine if READ or WRITE events detected.
+                 * This time READ or WRITE would be started */
+                substate = NRF_DRV_TWIS_SUBSTATE_IDLE;
+                ev = nrf_drv_twis_clear_bit(ev, NRF_TWIS_EVENT_STOPPED);
+            }
+            else
+            {
+                nrf_drv_twis_process_error(instNr, TWIS_EVT_READ_ERROR, nrf_twis_error_source_get_and_clear(p_reg));
+                substate = NRF_DRV_TWIS_SUBSTATE_IDLE;
+                ev = 0;
+            }
+            break;
+        case NRF_DRV_TWIS_SUBSTATE_WRITE_WAITING:
+            if (nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_RXSTARTED) ||
+               nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_WRITE)     ||
+               nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_READ)      ||
+               nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_STOPPED))
+            {
+                substate = NRF_DRV_TWIS_SUBSTATE_WRITE_PENDING;
+                /* Any other bits requires further processing in PENDING substate */
+                ev = nrf_drv_twis_clear_bit(ev, NRF_TWIS_EVENT_RXSTARTED);
+            }
+            else
+            {
+                nrf_drv_twis_process_error(instNr, TWIS_EVT_WRITE_ERROR, nrf_twis_error_source_get_and_clear(p_reg));
+                substate = NRF_DRV_TWIS_SUBSTATE_IDLE;
+                ev = 0;
+            }
+            break;
+        case NRF_DRV_TWIS_SUBSTATE_WRITE_PENDING:
+            if (nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_WRITE)||
+               nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_READ) ||
+               nrf_drv_twis_check_bit(ev, NRF_TWIS_EVENT_STOPPED))
+            {
+                evdata.type = TWIS_EVT_WRITE_DONE;
+                evdata.data.rx_amount = nrf_twis_rx_amount_get(p_reg);
+                nrf_drv_call_event_handler(instNr, &evdata);
+                /* Go to idle and repeat the state machine if READ or WRITE events detected.
+                 * This time READ or WRITE would be started */
+                substate = NRF_DRV_TWIS_SUBSTATE_IDLE;
+                ev = nrf_drv_twis_clear_bit(ev, NRF_TWIS_EVENT_STOPPED);
+            }
+            else
+            {
+                nrf_drv_twis_process_error(instNr, TWIS_EVT_WRITE_ERROR, nrf_twis_error_source_get_and_clear(p_reg));
+                substate = NRF_DRV_TWIS_SUBSTATE_IDLE;
+                ev = 0;
+            }
+            break;
+        default:
+            substate = NRF_DRV_TWIS_SUBSTATE_IDLE;
+            /* Do not clear any events and repeat the machine */
+            break;
+        }
+    }
+
+    m_var_inst[instNr].substate = substate;
+    if (!TWIS_NO_SYNC_MODE)
+    {
+        m_sm_semaphore[instNr] = 0;
+    }
+}
+
+/**
+ * @brief This function
+ */
+static inline void nrf_drv_twis_preprocess_status(uint8_t instNr)
+{
+    if (!TWIS_NO_SYNC_MODE)
+    {
+        if (NULL == m_var_inst[instNr].ev_handler)
+        {
+            nrf_drv_twis_state_machine(instNr);
+        }
+    }
+}
+
+/**
+ * @brief Interrupt service
+ *
+ * This function is called by all interrupts runtime for instances enabled in this library.
+ * @param instNr Driver instance number that has called this runtime.
+ */
+static inline void nrf_drv_twis_on_ISR(uint8_t instNr)
+{
+    nrf_drv_twis_state_machine(instNr);
+}
+
+/** @} */ /* End  of lib_driver_twis_slave_ifunc */
+
+
+/* -------------------------------------------------------------------------
+ * Implementation of IRQ Handlers
+ */
+#define X(n) \
+    IRQ_HANDLER(n) \
+    { \
+        nrf_drv_twis_on_ISR(TWIS##n##_INSTANCE_INDEX); \
+    }
+#include "nrf_drv_twis_inst.def"
+
+/* -------------------------------------------------------------------------
+ * Implementation of interface functions
+ *
+ */
+
+
+ret_code_t nrf_drv_twis_init(
+        nrf_drv_twis_t          const * const p_instance,
+        nrf_drv_twis_config_t   const * p_config,
+        nrf_drv_twis_event_handler_t    const event_handler)
+{
+    ASSERT(p_config);
+    ASSERT(p_config->scl != p_config->sda);
+    uint8_t instNr = p_instance->instNr;
+    NRF_TWIS_Type * const p_reg = m_const_inst[instNr].p_reg;
+    nrf_twis_config_addr_mask_t addr_mask = (nrf_twis_config_addr_mask_t)0;
+    ret_code_t err_code;
+
+    if ( m_var_inst[instNr].state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+    if (nrf_drv_common_per_res_acquire(p_reg, m_irq_handlers[instNr]) !=
+            NRF_SUCCESS)
+    {
+        err_code = NRF_ERROR_BUSY;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+#endif
+
+    if (!TWIS_ASSUME_INIT_AFTER_RESET_ONLY)
+    {
+        nrf_drv_twis_swreset(p_reg);
+    }
+
+    nrf_drv_twis_config_pin(p_config->scl, p_config->scl_pull);
+    nrf_drv_twis_config_pin(p_config->sda, p_config->sda_pull);
+
+    if (0 == (p_config->addr[0] | p_config->addr[1]))
+        addr_mask = NRF_TWIS_CONFIG_ADDRESS0_MASK;
+    else
+    {
+        if (0 != p_config->addr[0])
+        {
+            addr_mask |= NRF_TWIS_CONFIG_ADDRESS0_MASK;
+        }
+        if (0 != p_config->addr[1])
+        {
+            addr_mask |= NRF_TWIS_CONFIG_ADDRESS1_MASK;
+        }
+    }
+
+    /* Peripheral interrupt configure
+     * (note - interrupts still needs to be configured in INTEN register.
+     * This is done in enable function) */
+    nrf_drv_common_irq_enable(nrf_drv_get_IRQn(p_reg), p_config->interrupt_priority);
+
+    /* Configure */
+    nrf_twis_pins_set          (p_reg, p_config->scl, p_config->sda);
+    nrf_twis_address_set       (p_reg, 0, p_config->addr[0]);
+    nrf_twis_address_set       (p_reg, 1, p_config->addr[1]);
+    nrf_twis_config_address_set(p_reg, addr_mask);
+
+    /* Clear semaphore */
+    if (!TWIS_NO_SYNC_MODE)
+    {
+        m_sm_semaphore[instNr] = 0;
+    }
+    /* Set internal instance variables */
+    m_var_inst[instNr].substate   = NRF_DRV_TWIS_SUBSTATE_IDLE;
+    m_var_inst[instNr].ev_handler = event_handler;
+    m_var_inst[instNr].state      = NRF_DRV_STATE_INITIALIZED;
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+void nrf_drv_twis_uninit(nrf_drv_twis_t const * const p_instance)
+{
+    uint8_t instNr = p_instance->instNr;
+    NRF_TWIS_Type * const p_reg = m_const_inst[instNr].p_reg;
+    TWIS_PSEL_Type psel = p_reg->PSEL;
+
+    ASSERT(m_var_inst[instNr].state != NRF_DRV_STATE_UNINITIALIZED);
+
+    nrf_drv_twis_swreset(p_reg);
+
+    /* Clear pins state if */
+    if (!(TWIS_PSEL_SCL_CONNECT_Msk & psel.SCL))
+    {
+        nrf_gpio_cfg_default(psel.SCL);
+    }
+    if (!(TWIS_PSEL_SDA_CONNECT_Msk & psel.SDA))
+    {
+        nrf_gpio_cfg_default(psel.SDA);
+    }
+
+#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING)
+    nrf_drv_common_per_res_release(p_reg);
+#endif
+
+    /* Clear variables */
+    m_var_inst[instNr].ev_handler = NULL;
+    m_var_inst[instNr].state      = NRF_DRV_STATE_UNINITIALIZED;
+}
+
+
+void nrf_drv_twis_enable(nrf_drv_twis_t const * const p_instance)
+{
+    uint8_t instNr = p_instance->instNr;
+    NRF_TWIS_Type * const p_reg = m_const_inst[instNr].p_reg;
+    nrf_drv_twis_var_inst_t * const p_var_inst = &m_var_inst[instNr];
+
+    ASSERT(m_var_inst[instNr].state == NRF_DRV_STATE_INITIALIZED);
+
+    nrf_drv_twis_clear_all_events(p_reg);
+
+    /* Enable interrupts */
+    if (NULL != p_var_inst->ev_handler)
+    {
+        nrf_twis_int_enable(p_reg, m_used_ints_mask);
+    }
+
+    nrf_twis_enable(p_reg);
+    p_var_inst->error    = 0;
+    p_var_inst->state    = NRF_DRV_STATE_POWERED_ON;
+    p_var_inst->substate = NRF_DRV_TWIS_SUBSTATE_IDLE;
+}
+
+
+void nrf_drv_twis_disable(nrf_drv_twis_t const * const p_instance)
+{
+    uint8_t instNr = p_instance->instNr;
+    NRF_TWIS_Type * const p_reg = m_const_inst[instNr].p_reg;
+
+    ASSERT(m_var_inst[instNr].state != NRF_DRV_STATE_UNINITIALIZED);
+
+    nrf_twis_int_disable(p_reg, m_used_ints_mask);
+
+    nrf_twis_disable(p_reg);
+    m_var_inst[instNr].state    = NRF_DRV_STATE_INITIALIZED;
+}
+
+/* ARM recommends not using the LDREX and STREX instructions in C code.
+ * This is because the compiler might generate loads and stores between
+ * LDREX and STREX, potentially clearing the exclusive monitor set by LDREX.
+ * This recommendation also applies to the byte, halfword, and doubleword
+ * variants LDREXB, STREXB, LDREXH, STREXH, LDREXD, and STREXD.
+ *
+ * This is the reason for the function below to be implemented in assembly.
+ */
+//lint -save -e578
+#if defined (__CC_ARM )
+static __ASM uint32_t nrf_drv_twis_error_get_and_clear_internal(uint32_t volatile * const perror)
+{
+    mov   r3, r0
+    mov   r1, #0
+nrf_drv_twis_error_get_and_clear_internal_try
+    ldrex r0, [r3]
+    strex r2, r1, [r3]
+    cmp   r2, r1                                        /* did this succeed?       */
+    bne   nrf_drv_twis_error_get_and_clear_internal_try /* no – try again          */
+    bx    lr
+}
+#elif defined ( __GNUC__ )
+static uint32_t nrf_drv_twis_error_get_and_clear_internal(uint32_t volatile * const perror)
+{
+    uint32_t ret;
+    uint32_t temp;
+    __ASM volatile(
+        "   .syntax unified           \n"
+        "nrf_drv_twis_error_get_and_clear_internal_try:         \n"
+        "   ldrex %[ret], [%[perror]]                           \n"
+        "   strex %[temp], %[zero], [%[perror]]                 \n"
+        "   cmp   %[temp], %[zero]                              \n"
+        "   bne   nrf_drv_twis_error_get_and_clear_internal_try \n"
+    : /* Output */
+        [ret]"=&l"(ret),
+        [temp]"=&l"(temp)
+    : /* Input */
+        [zero]"l"(0),
+        [perror]"l"(perror)
+    );
+    UNUSED_VARIABLE(temp);
+    return ret;
+}
+#elif defined ( __ICCARM__ )
+static uint32_t nrf_drv_twis_error_get_and_clear_internal(uint32_t volatile * const perror)
+{
+    uint32_t ret;
+    uint32_t temp;
+    __ASM volatile(
+        "1:         \n"
+        "   ldrex %[ret], [%[perror]]                           \n"
+        "   strex %[temp], %[zero], [%[perror]]                 \n"
+        "   cmp   %[temp], %[zero]                              \n"
+        "   bne.n 1b \n"
+    : /* Output */
+        [ret]"=&l"(ret),
+        [temp]"=&l"(temp)
+    : /* Input */
+        [zero]"l"(0),
+        [perror]"l"(perror)
+    );
+    UNUSED_VARIABLE(temp);
+    return ret;
+}
+#else
+    #error Unknown compiler
+#endif
+//lint -restore
+
+uint32_t nrf_drv_twis_error_get_and_clear(nrf_drv_twis_t const * const p_instance)
+{
+    nrf_drv_twis_var_inst_t * const p_var_inst = &m_var_inst[p_instance->instNr];
+    nrf_drv_twis_preprocess_status(p_instance->instNr);
+    /* Make sure that access to error member is atomic
+     * so there is no bit that is cleared if it is not copied to local variable already. */
+    return nrf_drv_twis_error_get_and_clear_internal(&p_var_inst->error);
+}
+
+
+ret_code_t nrf_drv_twis_tx_prepare(
+        nrf_drv_twis_t const * const p_instance,
+        void const * const p_buf,
+        size_t size)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+    uint8_t instNr = p_instance->instNr;
+    NRF_TWIS_Type * const p_reg = m_const_inst[instNr].p_reg;
+    nrf_drv_twis_var_inst_t * const p_var_inst = &m_var_inst[instNr];
+
+    /* Check power state*/
+    if (p_var_inst->state != NRF_DRV_STATE_POWERED_ON)
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+    /* Check data address */
+    if (!nrf_drv_is_in_RAM(p_buf))
+    {
+        err_code = NRF_ERROR_INVALID_ADDR;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+    /* Check data size */
+    if ((size & TWIS_TXD_MAXCNT_MAXCNT_Msk) != size)
+    {
+        err_code = NRF_ERROR_INVALID_LENGTH;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    nrf_twis_tx_prepare(p_reg, (uint8_t const *)p_buf, (nrf_twis_amount_t)size);
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+
+}
+
+
+size_t nrf_drv_twis_tx_amount(nrf_drv_twis_t const * const p_instance)
+{
+    uint8_t instNr = p_instance->instNr;
+    NRF_TWIS_Type const * const p_reg = m_const_inst[instNr].p_reg;
+
+    return nrf_twis_tx_amount_get(p_reg);
+}
+
+
+ret_code_t nrf_drv_twis_rx_prepare(
+        nrf_drv_twis_t const * const p_instance,
+        void * const p_buf,
+        size_t size)
+{
+    ret_code_t err_code;
+    uint8_t instNr = p_instance->instNr;
+    NRF_TWIS_Type * const p_reg = m_const_inst[instNr].p_reg;
+    nrf_drv_twis_var_inst_t * const p_var_inst = &m_var_inst[instNr];
+
+    /* Check power state*/
+    if (p_var_inst->state != NRF_DRV_STATE_POWERED_ON)
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+    /* Check data address */
+    if (!nrf_drv_is_in_RAM(p_buf))
+    {
+        err_code = NRF_ERROR_INVALID_ADDR;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+    /* Check data size */
+    if ((size & TWIS_RXD_MAXCNT_MAXCNT_Msk) != size)
+    {
+        err_code = NRF_ERROR_INVALID_LENGTH;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    nrf_twis_rx_prepare(p_reg, (uint8_t *)p_buf, (nrf_twis_amount_t)size);
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+size_t nrf_drv_twis_rx_amount(nrf_drv_twis_t const * const p_instance)
+{
+    uint8_t instNr = p_instance->instNr;
+    NRF_TWIS_Type const * const p_reg = m_const_inst[instNr].p_reg;
+
+    return nrf_twis_rx_amount_get(p_reg);
+}
+
+
+bool nrf_drv_twis_is_busy(nrf_drv_twis_t const * const p_instance)
+{
+    nrf_drv_twis_preprocess_status(p_instance->instNr);
+    return NRF_DRV_TWIS_SUBSTATE_IDLE != m_var_inst[(p_instance->instNr)].substate;
+}
+
+bool nrf_drv_twis_is_waiting_tx_buff(nrf_drv_twis_t const * const p_instance)
+{
+    nrf_drv_twis_preprocess_status(p_instance->instNr);
+    return NRF_DRV_TWIS_SUBSTATE_READ_WAITING == m_var_inst[(p_instance->instNr)].substate;
+}
+
+bool nrf_drv_twis_is_waiting_rx_buff(nrf_drv_twis_t const * const p_instance)
+{
+    nrf_drv_twis_preprocess_status(p_instance->instNr);
+    return NRF_DRV_TWIS_SUBSTATE_WRITE_WAITING == m_var_inst[(p_instance->instNr)].substate;
+}
+
+bool nrf_drv_twis_is_pending_tx(nrf_drv_twis_t const * const p_instance)
+{
+    nrf_drv_twis_preprocess_status(p_instance->instNr);
+    return NRF_DRV_TWIS_SUBSTATE_READ_PENDING == m_var_inst[(p_instance->instNr)].substate;
+}
+
+bool nrf_drv_twis_is_pending_rx(nrf_drv_twis_t const * const p_instance)
+{
+    nrf_drv_twis_preprocess_status(p_instance->instNr);
+    return NRF_DRV_TWIS_SUBSTATE_WRITE_PENDING == m_var_inst[(p_instance->instNr)].substate;
+}
+#endif // TWIS_COUNT
+#endif // NRF_MODULE_ENABLED(TWIS)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/twis_slave/nrf_drv_twis.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,394 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef NRF_DRV_TWIS_H__
+#define NRF_DRV_TWIS_H__
+
+#include "sdk_config.h"
+#include "nrf_drv_common.h"
+#include "nrf_gpio.h"
+#include "sdk_errors.h"
+#include "nrf_twis.h"
+#include <stdint.h>
+#include "app_util.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**@file
+ * @addtogroup nrf_twis Two Wire slave interface (TWIS)
+ * @ingroup    nrf_drivers
+ * @brief      Two Wire slave interface (TWIS) APIs.
+ *
+ *
+ * @defgroup nrf_drv_twis TWIS driver
+ * @{
+ * @ingroup    nrf_twis
+ * @brief      TWI slave APIs.
+ */
+
+/**
+ * @brief Event callback function event definitions.
+ */
+typedef enum
+{
+    TWIS_EVT_READ_REQ,     ///< Read request detected
+                           /**< If there is no buffer prepared, buf_req flag in the even will be set.
+                                Call then @ref nrf_drv_twis_tx_prepare to give parameters for buffer.
+                                */
+    TWIS_EVT_READ_DONE,    ///< Read request has finished - free any data
+    TWIS_EVT_READ_ERROR,   ///< Read request finished with error
+    TWIS_EVT_WRITE_REQ,    ///< Write request detected
+                           /**< If there is no buffer prepared, buf_req flag in the even will be set.
+                                Call then @ref nrf_drv_twis_rx_prepare to give parameters for buffer.
+                                */
+    TWIS_EVT_WRITE_DONE,   ///< Write request has finished - process data
+    TWIS_EVT_WRITE_ERROR,  ///< Write request finished with error
+    TWIS_EVT_GENERAL_ERROR ///< Error that happens not inside WRITE or READ transaction
+} nrf_drv_twis_evt_type_t;
+
+/**
+ * @brief TWIS driver instance structure
+ *
+ * @note We only need instance number here so we could really use just a number
+ * that would be send to every driver function.
+ * But for compatibility reason this number is inserted into the structure.
+ */
+typedef struct
+{
+    uint8_t instNr; /**< Instance number */
+}nrf_drv_twis_t;
+
+/**
+ * @brief TWIS driver event structure
+ */
+typedef struct
+{
+    nrf_drv_twis_evt_type_t type; ///< Event type
+    union
+    {
+        bool buf_req;       ///< Flag for @ref TWIS_EVT_READ_REQ and @ref TWIS_EVT_WRITE_REQ
+                            /**< Information if transmission buffer requires to be prepared */
+        uint32_t tx_amount; ///< Data for @ref TWIS_EVT_READ_DONE
+        uint32_t rx_amount; ///< Data for @ref TWIS_EVT_WRITE_DONE
+        uint32_t error;     ///< Data for @ref TWIS_EVT_GENERAL_ERROR
+    }data;
+}nrf_drv_twis_evt_t;
+
+/**
+ * @brief TWI slave event callback function type.
+ *
+ * @param[in] p_event Event information structure.
+ */
+typedef void (*nrf_drv_twis_event_handler_t)(nrf_drv_twis_evt_t const * const p_event);
+
+/**
+ * @brief Structure for TWIS configuration
+ */
+typedef struct
+{
+    uint32_t addr[2];               //!< Set addresses that this slave should respond. Set 0 to disable.
+    uint32_t scl;                   //!< SCL pin number
+    nrf_gpio_pin_pull_t scl_pull;   //!< SCL pin pull
+    uint32_t sda;                   //!< SDA pin number
+    nrf_gpio_pin_pull_t sda_pull;   //!< SDA pin pull
+    uint8_t  interrupt_priority;    //!< The priority of interrupt for the module to set
+}nrf_drv_twis_config_t;
+
+/**
+ * @brief Possible error sources
+ *
+ * This is flag enum - values from this enum can be connected using logical or operator.
+ * @note
+ * We could use directly @ref nrf_twis_error_t. Error type enum is redefined here becouse
+ * of possible future extension (eg. supporting timeouts and synchronous mode).
+ */
+typedef enum
+{
+    NRF_DRV_TWIS_ERROR_OVERFLOW         = NRF_TWIS_ERROR_OVERFLOW,  /**< RX buffer overflow detected, and prevented */
+    NRF_DRV_TWIS_ERROR_DATA_NACK        = NRF_TWIS_ERROR_DATA_NACK, /**< NACK sent after receiving a data byte */
+    NRF_DRV_TWIS_ERROR_OVERREAD         = NRF_TWIS_ERROR_OVERREAD,  /**< TX buffer over-read detected, and prevented */
+    NRF_DRV_TWIS_ERROR_UNEXPECTED_EVENT = 1 << 8                    /**< Unexpected event detected by state machine */
+}nrf_drv_twis_error_t;
+
+/**
+ * @internal
+ * @brief Internal macro for creating TWIS driver instance
+ *
+ * Second level of indirection in creating the instance.
+ * Do not use this macro directly.
+ * Use @ref NRF_DRV_TWIS_INSTANCE instead.
+ */
+#define NRF_DRV_TWIS_INSTANCE_x(id) \
+    { \
+        TWIS##id##_INSTANCE_INDEX \
+    }
+
+/**
+ * @brief Macro for creating TWIS driver instance
+ *
+ * @param[in] id Instance index. Use 0 for TWIS0 and 1 for TWIS1
+ */
+#define NRF_DRV_TWIS_INSTANCE(id) NRF_DRV_TWIS_INSTANCE_x(id)
+
+#define TWIS0_INSTANCE_INDEX 0
+#define TWIS1_INSTANCE_INDEX TWIS0_INSTANCE_INDEX+TWIS0_ENABLED
+
+/**
+ * @brief Generate default configuration for TWIS driver instance
+ */
+#define NRF_DRV_TWIS_DEFAULT_CONFIG \
+{ \
+    .addr               = { TWIS_DEFAULT_CONFIG_ADDR0, TWIS_DEFAULT_CONFIG_ADDR1 }, \
+    .scl                = 31, \
+    .scl_pull           = (nrf_gpio_pin_pull_t)TWIS_DEFAULT_CONFIG_SCL_PULL, \
+    .sda                = 31, \
+    .sda_pull           = (nrf_gpio_pin_pull_t)TWIS_DEFAULT_CONFIG_SDA_PULL, \
+    .interrupt_priority = TWIS_DEFAULT_CONFIG_IRQ_PRIORITY \
+}
+
+/**
+ * @brief Function for initializing the TWIS driver instance.
+ *
+ * Function initializes and enables TWIS driver.
+ * @attention After driver initialization enable it by @ref nrf_drv_twis_enable
+ *
+ * @param[in] p_instance      Pointer to the driver instance structure.
+ * @attention                 @em p_instance has to be global object.
+ *                            It would be used by interrupts so make it sure that object
+ *                            would not be destroyed when function is leaving.
+ * @param[in] p_config        Initial configuration.
+ * @param[in] event_handler   Event handler provided by the user.
+ *
+ * @retval NRF_SUCCESS             If initialization was successful.
+ * @retval NRF_ERROR_INVALID_STATE If the driver is already initialized.
+ * @retval NRF_ERROR_BUSY          If some other peripheral with the same
+ *                                 instance ID is already in use. This is
+ *                                 possible only if PERIPHERAL_RESOURCE_SHARING_ENABLED
+ *                                 is set to a value other than zero.
+ */
+ret_code_t nrf_drv_twis_init(
+        nrf_drv_twis_t          const * const p_instance,
+        nrf_drv_twis_config_t   const * p_config,
+        nrf_drv_twis_event_handler_t    const event_handler);
+
+/**
+ * @brief Function for uninitializing the TWIS driver instance.
+ *
+ * Function initializes the peripheral and resets all registers to default values.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @note
+ * It is safe to call nrf_drv_twis_uninit even before initialization.
+ * Actually @ref nrf_drv_twis_init function calls this function to
+ * make sure that TWIS state is known.
+ * @note
+ * If TWIS driver was in uninitialized state before calling this function,
+ * selected pins would not be reset to default configuration.
+ */
+void nrf_drv_twis_uninit(nrf_drv_twis_t const * const p_instance);
+
+/**
+ * @brief Enable TWIS instance
+ *
+ * This function enables TWIS instance.
+ * Function defined if there is needs for dynamically enabling and disabling the peripheral.
+ * Use @ref nrf_drv_twis_enable and @ref nrf_drv_twis_disable functions.
+ * They do not change any configuration registers.
+ *
+ * @param p_instance Pointer to the driver instance structure.
+ */
+void nrf_drv_twis_enable(nrf_drv_twis_t const * const p_instance);
+
+/**
+ * @brief Disable TWIS instance
+ *
+ * Disabling TWIS instance gives possibility to turn off the TWIS while
+ * holding configuration done by @ref nrf_drv_twis_init
+ *
+ * @param p_instance Pointer to the driver instance structure.
+ */
+void nrf_drv_twis_disable(nrf_drv_twis_t const * const p_instance);
+
+/**
+ * @brief Get and clear last error flags
+ *
+ * Function gets information about errors.
+ * This is also the only possibility to exit from error substate of the internal state machine.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @return Error flags defined in @ref nrf_drv_twis_error_t
+ * @attention
+ * This function clears error state and flags.
+ */
+uint32_t nrf_drv_twis_error_get_and_clear(nrf_drv_twis_t const * const p_instance);
+
+
+/**
+ * @brief Prepare data for sending
+ *
+ * This function should be used in response for @ref TWIS_EVT_READ_REQ event.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_buf      Transmission buffer
+ * @attention            Transmission buffer has to be placed in RAM.
+ * @param     size       Maximum number of bytes that master may read from buffer given.
+ *
+ * @retval NRF_SUCCESS              Preparation finished properly
+ * @retval NRF_ERROR_INVALID_ADDR   Given @em p_buf is not placed inside the RAM
+ * @retval NRF_ERROR_INVALID_LENGTH Wrong value in @em size parameter
+ * @retval NRF_ERROR_INVALID_STATE  Module not initialized or not enabled
+ */
+ret_code_t nrf_drv_twis_tx_prepare(
+        nrf_drv_twis_t const * const p_instance,
+        void const * const p_buf,
+        size_t size);
+
+/**
+ * @brief Get number of transmitted bytes
+ *
+ * Function returns number of bytes sent.
+ * This function may be called after @ref TWIS_EVT_READ_DONE or @ref TWIS_EVT_READ_ERROR events.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ *
+ * @return Number of bytes sent.
+ */
+size_t nrf_drv_twis_tx_amount(nrf_drv_twis_t const * const p_instance);
+
+/**
+ * @brief Prepare data for receiving
+ *
+ * This function should be used in response for @ref TWIS_EVT_WRITE_REQ event.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_buf      Buffer that would be filled with received data
+ * @attention            Receiving buffer has to be placed in RAM.
+ * @param     size       Size of the buffer (maximum amount of data to receive)
+ *
+ * @retval NRF_SUCCESS              Preparation finished properly
+ * @retval NRF_ERROR_INVALID_ADDR   Given @em p_buf is not placed inside the RAM
+ * @retval NRF_ERROR_INVALID_LENGTH Wrong value in @em size parameter
+ * @retval NRF_ERROR_INVALID_STATE  Module not initialized or not enabled
+ */
+ret_code_t nrf_drv_twis_rx_prepare(
+        nrf_drv_twis_t const * const p_instance,
+        void * const p_buf,
+        size_t size);
+
+/**
+ * @brief Get number of received bytes
+ *
+ * Function returns number of bytes received.
+ * This function may be called after @ref TWIS_EVT_WRITE_DONE or @ref TWIS_EVT_WRITE_ERROR events.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ *
+ * @return Number of bytes received.
+ */
+size_t nrf_drv_twis_rx_amount(nrf_drv_twis_t const * const p_instance);
+
+/**
+ * @brief Function checks if driver is busy right now
+ *
+ * Actual driver substate is tested.
+ * If driver is in any other state than IDLE or ERROR this function returns true.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ *
+ * @retval true  Driver is in state other than ERROR or IDLE
+ * @retval false There is no transmission pending.
+ */
+bool nrf_drv_twis_is_busy(nrf_drv_twis_t const * const p_instance);
+
+/**
+ * @brief Function checks if driver is waiting for tx buffer
+ *
+ * If this function returns true, it means that driver is stalled expecting
+ * of the @ref nrf_drv_twis_tx_prepare function call.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ *
+ * @retval true Driver waits for @ref nrf_drv_twis_tx_prepare
+ * @retval false Driver is not in the state where it waits for preparing tx buffer.
+ */
+bool nrf_drv_twis_is_waiting_tx_buff(nrf_drv_twis_t const * const p_instance);
+
+/**
+ * @brief Function checks if driver is waiting for rx buffer
+ *
+ * If this function returns true, it means that driver is staled expecting
+ * of the @ref nrf_drv_twis_rx_prepare function call.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ *
+ * @retval true Driver waits for @ref nrf_drv_twis_rx_prepare
+ * @retval false Driver is not in the state where it waits for preparing rx buffer.
+ */
+bool nrf_drv_twis_is_waiting_rx_buff(nrf_drv_twis_t const * const p_instance);
+
+/**
+ * @brief Check if driver is sending data
+ *
+ * If this function returns true, it means that there is ongoing output transmission.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ *
+ * @retval true There is ongoing output transmission.
+ * @retval false Driver is in other state.
+ */
+bool nrf_drv_twis_is_pending_tx(nrf_drv_twis_t const * const p_instance);
+
+/**
+ * @brief Check if driver is receiving data
+ *
+ * If this function returns true, it means that there is ongoing input transmission.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ *
+ * @retval true There is ongoing input transmission.
+ * @retval false Driver is in other state.
+ */
+bool nrf_drv_twis_is_pending_rx(nrf_drv_twis_t const * const p_instance);
+
+/** @} */ /* End of lib_twis_drv group */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF_DRV_TWIS_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/twis_slave/nrf_drv_twis_inst.def	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,20 @@
+/**
+ * @file
+ * @brief Xmacro file with contains enumeration of TWIS instances to implement
+ *
+ * Use this file everywhere where anything has to be generated for all active TWIS instances.
+ * Xmacro format:
+ *
+ * @code
+   X(n)
+ * @endcode
+ *
+ * Where @em n is number of the instance itself (0 for NRF_TWIS0).
+ */
+#if (TWIS0_ENABLED == 1)
+    X(0)
+#endif
+#if (TWIS1_ENABLED == 1)
+    X(1)
+#endif
+#undef X

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/wdt/nrf_drv_wdt.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,174 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(WDT)
+#include "nrf_drv_wdt.h"
+#include "nrf_drv_common.h"
+#include "nrf_error.h"
+#include "nrf_assert.h"
+#include "nrf_wdt.h"
+#include "app_util_platform.h"
+#include <stdbool.h>
+#include <stdint.h>
+
+#define NRF_LOG_MODULE_NAME "WDT"
+
+#if WDT_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       WDT_CONFIG_LOG_LEVEL
+#define NRF_LOG_INFO_COLOR  WDT_CONFIG_INFO_COLOR
+#define NRF_LOG_DEBUG_COLOR WDT_CONFIG_DEBUG_COLOR
+#else //WDT_CONFIG_LOG_ENABLED
+#define NRF_LOG_LEVEL       0
+#endif //WDT_CONFIG_LOG_ENABLED
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+
+
+/**@brief WDT event handler. */
+static nrf_wdt_event_handler_t m_wdt_event_handler;
+
+/**@brief WDT state. */
+static nrf_drv_state_t m_state;
+
+/**@brief WDT alloc table. */
+static uint32_t m_alloc_index;
+
+static const nrf_drv_wdt_config_t m_default_config = NRF_DRV_WDT_DEAFULT_CONFIG;
+
+/**@brief WDT interrupt handler. */
+void WDT_IRQHandler(void)
+{
+    if (nrf_wdt_int_enable_check(NRF_WDT_INT_TIMEOUT_MASK) == true)
+    {
+        nrf_wdt_event_clear(NRF_WDT_EVENT_TIMEOUT);
+        m_wdt_event_handler();
+    }
+}
+
+
+ret_code_t nrf_drv_wdt_init(nrf_drv_wdt_config_t const * p_config,
+                            nrf_wdt_event_handler_t     wdt_event_handler)
+{
+    ASSERT(wdt_event_handler != NULL);
+    ret_code_t err_code;
+    m_wdt_event_handler = wdt_event_handler;
+
+    if (m_state == NRF_DRV_STATE_UNINITIALIZED)
+    {
+        m_state = NRF_DRV_STATE_INITIALIZED;
+    }
+    else
+    {
+        err_code = NRF_ERROR_INVALID_STATE;
+        NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+        return err_code;
+    }
+
+    if (p_config == NULL)
+    {
+        p_config = &m_default_config;
+    }
+
+    nrf_wdt_behaviour_set(p_config->behaviour);
+
+
+
+
+
+
+
+    nrf_wdt_reload_value_set((p_config->reload_value * 32768) / 1000);
+
+    nrf_drv_common_irq_enable(WDT_IRQn, p_config->interrupt_priority);
+
+    err_code = NRF_SUCCESS;
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code));
+    return err_code;
+}
+
+
+void nrf_drv_wdt_enable(void)
+{
+    ASSERT(m_alloc_index != 0);
+    ASSERT(m_state == NRF_DRV_STATE_INITIALIZED);
+    nrf_wdt_int_enable(NRF_WDT_INT_TIMEOUT_MASK);
+    nrf_wdt_task_trigger(NRF_WDT_TASK_START);
+    m_state = NRF_DRV_STATE_POWERED_ON;
+    NRF_LOG_INFO("Enabled.\r\n");
+}
+
+
+void nrf_drv_wdt_feed(void)
+{
+    ASSERT(m_state == NRF_DRV_STATE_POWERED_ON);
+    for (uint32_t i = 0; i < m_alloc_index; i++)
+    {
+        nrf_wdt_reload_request_set((nrf_wdt_rr_register_t)(NRF_WDT_RR0 + i));
+    }
+}
+
+ret_code_t nrf_drv_wdt_channel_alloc(nrf_drv_wdt_channel_id * p_channel_id)
+{
+    ret_code_t result;
+    ASSERT(p_channel_id);
+    ASSERT(m_state == NRF_DRV_STATE_INITIALIZED);
+
+    CRITICAL_REGION_ENTER();
+    if (m_alloc_index < NRF_WDT_CHANNEL_NUMBER)
+    {
+        *p_channel_id = (nrf_drv_wdt_channel_id)(NRF_WDT_RR0 + m_alloc_index);
+        m_alloc_index++;
+        nrf_wdt_reload_request_enable(*p_channel_id);
+        result = NRF_SUCCESS;
+    }
+    else
+    {
+        result = NRF_ERROR_NO_MEM;
+    }
+    CRITICAL_REGION_EXIT();
+    NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(result));
+    return result;
+}
+
+void nrf_drv_wdt_channel_feed(nrf_drv_wdt_channel_id channel_id)
+{
+    ASSERT(m_state == NRF_DRV_STATE_POWERED_ON);
+    nrf_wdt_reload_request_set(channel_id);
+}
+#endif //NRF_MODULE_ENABLED(WDT)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/wdt/nrf_drv_wdt.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,159 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**@file
+ * @addtogroup nrf_wdt WDT HAL and driver
+ * @ingroup nrf_drivers
+ * @brief Watchdog timer (WDT) APIs.
+ * @details The WDT HAL provides basic APIs for accessing the registers of the watchdog timer.
+ * The WDT driver provides APIs on a higher level.
+ * @defgroup nrf_drv_wdt WDT driver
+ * @{
+ * @ingroup  nrf_wdt
+ *
+ * @brief    Driver for managing the watchdog timer (WDT).
+ */
+
+#ifndef NRF_DRV_WDT_H__
+#define NRF_DRV_WDT_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "nrf_wdt.h"
+#include "sdk_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Struct for WDT initialization. */
+typedef struct
+{
+    nrf_wdt_behaviour_t    behaviour;          /**< WDT behaviour when CPU in sleep/halt mode. */
+    uint32_t               reload_value;       /**< WDT reload value in ms. */
+    uint8_t                interrupt_priority; /**< WDT interrupt priority */
+} nrf_drv_wdt_config_t;
+
+/**@brief WDT event handler function type. */
+typedef void (*nrf_wdt_event_handler_t)(void);
+
+/**@brief WDT channel id type. */
+typedef nrf_wdt_rr_register_t nrf_drv_wdt_channel_id;
+
+#define NRF_DRV_WDT_DEAFULT_CONFIG                                       \
+    {                                                                    \
+        .behaviour          = (nrf_wdt_behaviour_t)WDT_CONFIG_BEHAVIOUR, \
+        .reload_value       = WDT_CONFIG_RELOAD_VALUE,                   \
+        .interrupt_priority = WDT_CONFIG_IRQ_PRIORITY,                   \
+    }
+/**
+ * @brief This function initializes watchdog.
+ *
+ * @param[in] p_config          Initial configuration. Default configuration used if NULL.
+ * @param[in] wdt_event_handler specifies event handler provided by user.
+ *
+ * @note Function asserts if wdt_event_handler is NULL.
+ *
+ * @return    NRF_SUCCESS on success, otherwise an error code.
+ */
+ret_code_t nrf_drv_wdt_init(nrf_drv_wdt_config_t const * p_config,
+                            nrf_wdt_event_handler_t     wdt_event_handler);
+
+/**
+ * @brief This function allocate watchdog channel.
+ *
+ * @note This function can not be called after nrf_drv_wdt_start(void).
+ *
+ * @param[out] p_channel_id      ID of granted channel.
+ *
+ * @return    NRF_SUCCESS on success, otherwise an error code.
+ */
+ret_code_t nrf_drv_wdt_channel_alloc(nrf_drv_wdt_channel_id * p_channel_id);
+
+/**
+ * @brief This function starts watchdog.
+ *
+ * @note After calling this function the watchdog is started, so the user needs to feed all allocated
+ *       watchdog channels to avoid reset. At least one watchdog channel has to be allocated.
+ */
+void nrf_drv_wdt_enable(void);
+
+/**
+ * @brief This function feeds the watchdog.
+ *
+ * @details Function feeds all allocated watchdog channels.
+ */
+void nrf_drv_wdt_feed(void);
+
+/**
+ * @brief This function feeds the invidual watchdog channel.
+ *
+ * @param[in] channel_id      ID of watchdog channel.
+ */
+void nrf_drv_wdt_channel_feed(nrf_drv_wdt_channel_id channel_id);
+
+/**@brief Function for returning a requested task address for the wdt driver module.
+ *
+ * @param[in]  task                One of the peripheral tasks.
+ *
+ * @retval     Task address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_wdt_ppi_task_addr(nrf_wdt_task_t task)
+{
+    return nrf_wdt_task_address_get(task);
+}
+
+/**@brief Function for returning a requested event address for the wdt driver module.
+ *
+ * @param[in]  event               One of the peripheral events.
+ *
+ * @retval     Event address
+ */
+__STATIC_INLINE uint32_t nrf_drv_wdt_ppi_event_addr(nrf_wdt_event_t event)
+{
+    return nrf_wdt_event_address_get(event);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/bootloader/dfu/nrf_dfu_flash.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,315 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "nrf_dfu_flash.h"
+#include "nrf_dfu_types.h"
+#include "softdevice_handler.h"
+#include "nrf_nvmc.h"
+#include "nrf_log.h"
+
+#ifdef SOFTDEVICE_PRESENT
+// Only include fstorage if SD interaction is required
+#include "fstorage.h"
+#endif
+
+#define FLASH_FLAG_NONE                 (0)
+#define FLASH_FLAG_OPER                 (1<<0)
+#define FLASH_FLAG_FAILURE_SINCE_LAST   (1<<1)
+#define FLASH_FLAG_SD_ENABLED           (1<<2)
+
+static uint32_t m_flags;
+
+#ifdef BLE_STACK_SUPPORT_REQD
+
+// Function prototypes
+static void fs_evt_handler(fs_evt_t const * const evt, fs_ret_t result);
+
+FS_REGISTER_CFG(fs_config_t fs_dfu_config) =
+{
+    .callback       = fs_evt_handler,            // Function for event callbacks.
+    .p_start_addr   = (uint32_t*)MBR_SIZE,
+    .p_end_addr     = (uint32_t*)BOOTLOADER_SETTINGS_ADDRESS + CODE_PAGE_SIZE
+};
+
+
+static void fs_evt_handler(fs_evt_t const * const evt, fs_ret_t result)
+{
+    // Clear the operation flag
+    m_flags &= ~FLASH_FLAG_OPER;
+
+    if (result == FS_SUCCESS)
+    {
+        // Clear flag for ongoing operation and failure since last
+        m_flags &= ~FLASH_FLAG_FAILURE_SINCE_LAST;
+    }
+    else
+    {
+        NRF_LOG_ERROR("Generating failure\r\n");
+        m_flags |= FLASH_FLAG_FAILURE_SINCE_LAST;
+    }
+
+    if (evt->p_context)
+    {
+        //lint -e611
+        ((dfu_flash_callback_t)evt->p_context)(evt, result);
+    }
+}
+
+#endif
+
+
+uint32_t nrf_dfu_flash_init(bool sd_enabled)
+{
+    uint32_t err_code = NRF_SUCCESS;
+
+#ifdef BLE_STACK_SUPPORT_REQD
+    // Only run this initialization if SD is enabled
+    if(sd_enabled)
+    {
+        NRF_LOG_INFO("------- nrf_dfu_flash_init-------\r\n");
+        if (fs_fake_init() != FS_SUCCESS)
+        {
+            NRF_LOG_ERROR("Not initializing the thing\r\n");
+            return NRF_ERROR_INVALID_STATE;
+        }
+
+        // Enable access to the whole range
+
+
+        err_code = softdevice_sys_evt_handler_set(fs_sys_event_handler);
+        if (err_code != NRF_SUCCESS)
+        {
+            NRF_LOG_ERROR("Not initializing the thing 2\r\n");
+            return NRF_ERROR_INVALID_STATE;
+        }
+
+        // Setting flag to indicate that SD is enabled to ensure fstorage is use in calls
+        // to do flash operations.
+        m_flags = FLASH_FLAG_SD_ENABLED;
+    }
+    else
+#endif
+    {
+        m_flags = FLASH_FLAG_NONE;
+    }
+
+    return err_code;
+}
+
+
+fs_ret_t nrf_dfu_flash_store(uint32_t const * p_dest, uint32_t const * const p_src, uint32_t len_words, dfu_flash_callback_t callback)
+{
+    fs_ret_t ret_val = FS_SUCCESS;
+
+#ifdef BLE_STACK_SUPPORT_REQD
+    if ((m_flags & FLASH_FLAG_SD_ENABLED) != 0)
+    {
+        // Check if there is a pending error
+        if ((m_flags & FLASH_FLAG_FAILURE_SINCE_LAST) != 0)
+        {
+            NRF_LOG_ERROR("Flash: Failure since last\r\n");
+            return FS_ERR_FAILURE_SINCE_LAST;
+        }
+
+        // Set the flag to indicate ongoing operation
+        m_flags |= FLASH_FLAG_OPER;
+        //lint -e611
+        ret_val = fs_store(&fs_dfu_config, p_dest, p_src, len_words, (void*)callback);
+
+        if (ret_val != FS_SUCCESS)
+        {
+            NRF_LOG_ERROR("Flash: failed %d\r\n", ret_val);
+            return ret_val;
+        }
+
+        // Set the flag to indicate ongoing operation
+        m_flags |= FLASH_FLAG_OPER;
+    }
+    else
+#endif
+    {
+
+#ifndef NRF51
+        if ((p_src == NULL) || (p_dest == NULL))
+        {
+            return FS_ERR_NULL_ARG;
+        }
+
+        // Check that both pointers are word aligned.
+        if (((uint32_t)p_src  & 0x03) ||
+            ((uint32_t)p_dest & 0x03))
+        {
+            return FS_ERR_UNALIGNED_ADDR;
+        }
+
+        if (len_words == 0)
+        {
+            NRF_LOG_ERROR("Flash: Invalid length (NVMC)\r\n");
+            return FS_ERR_INVALID_ARG;
+        }
+#endif
+
+        nrf_nvmc_write_words((uint32_t)p_dest, p_src, len_words);
+
+        #if (__LINT__ != 1)
+        if (callback)
+        {
+            fs_evt_t evt =
+            {
+                .id = FS_EVT_STORE,
+                .p_context = (void*)callback,
+                .store =
+                {
+                    .length_words = len_words,
+                    .p_data = p_dest
+                }
+            };
+            callback(&evt, FS_SUCCESS);
+        }
+        #endif
+    }
+
+    return ret_val;
+}
+
+
+/** @brief Internal function to initialize DFU BLE transport
+ */
+fs_ret_t nrf_dfu_flash_erase(uint32_t const * p_dest, uint32_t num_pages, dfu_flash_callback_t callback)
+{
+    fs_ret_t ret_val = FS_SUCCESS;
+    NRF_LOG_INFO("Erasing: 0x%08x, num: %d\r\n", (uint32_t)p_dest, num_pages);
+
+#ifdef BLE_STACK_SUPPORT_REQD
+
+    if ((m_flags & FLASH_FLAG_SD_ENABLED) != 0)
+    {
+        // Check if there is a pending error
+        if ((m_flags & FLASH_FLAG_FAILURE_SINCE_LAST) != 0)
+        {
+            NRF_LOG_ERROR("Erase: Failure since last\r\n");
+            return FS_ERR_FAILURE_SINCE_LAST;
+        }
+
+        m_flags |= FLASH_FLAG_OPER;
+        ret_val = fs_erase(&fs_dfu_config, p_dest, num_pages, (void*)callback);
+
+        if (ret_val != FS_SUCCESS)
+        {
+            NRF_LOG_ERROR("Erase failed: %d\r\n", ret_val);
+            m_flags &= ~FLASH_FLAG_OPER;
+            return ret_val;
+        }
+
+        // Set the flag to indicate ongoing operation
+        m_flags |= FLASH_FLAG_OPER;
+    }
+    else
+#endif
+    {
+#ifndef NRF51
+        // Softdevice is not present or activated. Run the NVMC instead
+        if (((uint32_t)p_dest & (CODE_PAGE_SIZE-1)) != 0)
+        {
+            NRF_LOG_ERROR("Invalid address\r\n");
+            return FS_ERR_UNALIGNED_ADDR;
+        }
+#endif
+
+        uint16_t first_page = ((uint32_t)p_dest / CODE_PAGE_SIZE);
+        do
+        {
+            nrf_nvmc_page_erase((uint32_t)p_dest);
+            p_dest += CODE_PAGE_SIZE/sizeof(uint32_t);
+        }
+        while(--num_pages > 0);
+
+
+        if (callback)
+        {
+            #if (__LINT__ != 1)
+            fs_evt_t evt =
+            {
+                .id = FS_EVT_ERASE,
+                .p_context = (void*)callback,
+                .erase =
+                {
+                    .first_page = first_page,
+                    .last_page = ((uint32_t)p_dest / CODE_PAGE_SIZE)
+                }
+            };
+            callback(&evt, FS_SUCCESS);
+            #else
+            (void)first_page;
+            #endif
+        }
+    }
+
+    return ret_val;
+}
+
+
+void nrf_dfu_flash_error_clear(void)
+{
+    m_flags &= ~FLASH_FLAG_FAILURE_SINCE_LAST;
+}
+
+
+fs_ret_t nrf_dfu_flash_wait(void)
+{
+    NRF_LOG_INFO("Waiting for finished...\r\n");
+
+#ifdef BLE_STACK_SUPPORT_REQD
+    if ((m_flags & FLASH_FLAG_SD_ENABLED) != 0)
+    {
+        while ((m_flags & FLASH_FLAG_OPER) != 0)
+        {
+            (void)sd_app_evt_wait();
+        }
+
+        if ((m_flags & FLASH_FLAG_FAILURE_SINCE_LAST) != 0)
+        {
+            NRF_LOG_ERROR("Failure since last\r\n");
+            return FS_ERR_FAILURE_SINCE_LAST;
+        }
+    }
+#endif
+
+    NRF_LOG_INFO("After wait!\r\n");
+    return FS_SUCCESS;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/bootloader/dfu/nrf_dfu_flash.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,155 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**@file
+ *
+ * @defgroup sdk_nrf_dfu_flash Flash operations
+ * @{
+ * @ingroup  sdk_nrf_dfu
+ */
+
+#ifndef NRF_DFU_FLASH_H__
+#define NRF_DFU_FLASH_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fstorage.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**@brief   fstorage event handler function for DFU fstorage operations.
+ *
+ * This function is intended to be registered to the fstorage module as the event handler for all DFU flash operations.
+ * When each flash operation has completed or failed this function will be called.
+ *
+ * See ::fs_cb_t for implementation details.
+ */
+typedef fs_cb_t dfu_flash_callback_t;
+
+/**@brief Function for initializing the flash module.
+ *
+ * You can use this module with or without a SoftDevice:
+ * - If the module is initialized with the SoftDevice enabled flag set, the @ref fstorage
+ *   module is used as back end for all flash operations. Flash storage calls
+ *   are asynchronous; the SoftDevice manages when the actual operation in
+ *   flash is done.
+ * - If the module is initialized with the SoftDevice enabled flag not set,
+ *   the non-volatile memory controller (NVMC) driver handles the flash operations
+ *   by directly accessing flash. These operations are synchronous.
+ *
+ * @param[in]  sd_enabled Set the flash handling to run with or without the SoftDevice enabled.
+ *
+ * @retval NRF_SUCCESS             If the operation was successful.
+ * @retval NRF_ERROR_INVALID_STATE If the fstorage module could not be initiated or the SoftDevice could not set the event handler.
+ */
+uint32_t nrf_dfu_flash_init(bool sd_enabled);
+
+
+/**@brief Function for storing data to flash (with or without the SoftDevice enabled).
+ *
+ * @warning The content to be stored must be kept at @p p_src until the operation is
+ *          complete. Without SoftDevice, the operation is complete when the function
+ *          returns. With SoftDevice, the operation is complete when the fstorage event is received.
+ *
+ * @param[in]  p_dest    Pointer to the address where the data should be stored.
+ * @param[in]  p_src     Pointer to the address where the data should be copied from.
+ *                       This address can be in flash or RAM.
+ * @param[in]  len_words The number of words to be copied from @p p_src to @p p_dest.
+ * @param[in]  callback  Pointer to the callback function.
+ *
+ * @retval  FS_SUCCESS                If the operation was successful.
+ * @retval  FS_ERR_FAILURE_SINCE_LAST If an error occurred in another transaction and fstorage cannot continue before
+ *                                   the event has been dealt with.
+ * @retval  FS_ERR_UNALIGNED_ADDR     If @p p_src or @p p_dest is not word-aligned. Ensure that the address pointed to is divisible by four.
+ * @retval  FS_ERR_INVALID_ARG        If @p len_words is zero. It is not possible to write zero words.
+ * @retval  FS_ERR_NULL_ARG           If @p p_src or @p p_dest is NULL.
+ *
+ * @retval  FS_ERR_NOT_INITIALIZED  If the fstorage module is not initialized.
+ * @retval  FS_ERR_INVALID_CFG      If the initialization of the fstorage module is invalid.
+ * @retval  FS_ERR_QUEUE_FULL       If the internal operation queue of the fstorage module is full.
+ */
+fs_ret_t nrf_dfu_flash_store(uint32_t const * p_dest, uint32_t const * const p_src, uint32_t len_words, dfu_flash_callback_t callback);
+
+
+/**@brief Function for erasing data from flash (with or without the SoftDevice enabled).
+ *
+ * @param[in]  p_dest    The address of the first byte to be deleted.
+ * @param[in]  num_pages The number of flash pages to be deleted.
+ * @param[in]  callback  Pointer to the callback function.
+ *
+ * @retval  FS_SUCCESS              If the operation was successful.
+ * @retval  FS_ERR_UNALIGNED_ADDR   If @p p_dest is not aligned to a page boundary.
+ * @retval  FS_ERR_INVALID_ADDR     If @p p_dest does not point to the start of a flash page or the operation would
+ *                                  go beyond the flash memory boundary.
+ * @retval  FS_ERR_NOT_INITIALIZED  If the fstorage module is not initialized.
+ * @retval  FS_ERR_INVALID_CFG      If the initialization of the fstorage module is invalid.
+ * @retval  FS_ERR_NULL_ARG         If @p p_dest is NULL.
+ * @retval  FS_ERR_INVALID_ARG      If @p num_pages is zero.
+ * @retval  FS_ERR_QUEUE_FULL       If the internal operation queue of the fstorage module is full.
+ */
+fs_ret_t nrf_dfu_flash_erase(uint32_t const * p_dest, uint32_t num_pages, dfu_flash_callback_t callback);
+
+
+/**@brief Function for clearing an error that has occurred during fstorage operations.
+ */
+void nrf_dfu_flash_error_clear(void);
+
+
+/**@brief Function for waiting for an event from fstorage.
+ *
+ * This function halts execution until an event is received from the SoftDevice.
+ * You can use this function to halt execution until a flash operation has completed, to prevent
+ * tampering with the source data until fstorage is done with it.
+ *
+ * @retval FS_SUCCESS                If the operation was successful.
+ * @retval FS_ERR_FAILURE_SINCE_LAST If an error has occurred in another transaction and fstorage cannot continue before
+ *                                   the event has been dealt with.
+ */
+fs_ret_t nrf_dfu_flash_wait(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // NRF_DFU_FLASH_H__
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/bootloader/dfu/nrf_dfu_req_handler.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,202 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**@file
+ *
+ * @defgroup sdk_nrf_dfu_req_handler Request handling
+ * @{
+ * @ingroup  sdk_nrf_dfu
+ */
+
+#ifndef NRF_DFU_REQ_HANDLER_H__
+#define NRF_DFU_REQ_HANDLER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf_dfu_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**@brief DFU object types.
+ */
+typedef enum
+{
+    NRF_DFU_OBJ_TYPE_INVALID,                   /**< Invalid object type.*/
+    NRF_DFU_OBJ_TYPE_COMMAND,                   /**< Command object packet.*/
+    NRF_DFU_OBJ_TYPE_DATA,                      /**< Data object.*/
+} nrf_dfu_obj_type_t;
+
+
+/**@brief DFU request operation codes.
+ *
+ * @details The DFU transport layer creates request events of these types. The implementation of @ref nrf_dfu_req_handler_on_req handles requests of these types.
+ */
+typedef enum
+{
+
+    NRF_DFU_OBJECT_OP_NONE          = 0,        /**< No operation set. */
+    NRF_DFU_OBJECT_OP_CREATE        = 1,        /**< Create operation. The length of the request indicates the required size. When called, the created object is selected. */
+    NRF_DFU_OBJECT_OP_WRITE         = 2,        /**< Write operation. When called, offset and CRC of the selected object are reported back. */
+    NRF_DFU_OBJECT_OP_EXECUTE       = 3,        /**< Execute operation. When called, the selected object is executed. */
+    NRF_DFU_OBJECT_OP_CRC           = 4,        /**< Calculate checksum operation. When called, offset and CRC of the selected object are reported back. */
+    NRF_DFU_OBJECT_OP_SELECT        = 6,        /**< Select operation. When called, the object of the given type is selected, and information about the object is reported back. */
+    NRF_DFU_OBJECT_OP_OTHER         = 7,        /**< A user-defined DFU request type. The application must define how to interpret the request. */
+} nrf_dfu_req_op_t;
+
+
+/**@brief DFU request result codes.
+ *
+ * @details The DFU transport layer creates request events of types @ref nrf_dfu_req_op_t,
+ * which are handled by @ref nrf_dfu_req_handler_on_req. That functions returns one of these result codes.
+ */
+typedef enum
+{
+    NRF_DFU_RES_CODE_INVALID                 = 0x00,     /**< Invalid opcode. */
+    NRF_DFU_RES_CODE_SUCCESS                 = 0x01,     /**< Operation successful. */
+    NRF_DFU_RES_CODE_OP_CODE_NOT_SUPPORTED   = 0x02,     /**< Opcode not supported. */
+    NRF_DFU_RES_CODE_INVALID_PARAMETER       = 0x03,     /**< Missing or invalid parameter value. */
+    NRF_DFU_RES_CODE_INSUFFICIENT_RESOURCES  = 0x04,     /**< Not enough memory for the data object. */
+    NRF_DFU_RES_CODE_INVALID_OBJECT          = 0x05,     /**< Data object does not match the firmware and hardware requirements, the signature is missing, or parsing the command failed. */
+    NRF_DFU_RES_CODE_UNSUPPORTED_TYPE        = 0x07,     /**< Not a valid object type for a Create request. */
+    NRF_DFU_RES_CODE_OPERATION_NOT_PERMITTED = 0x08,     /**< The state of the DFU process does not allow this operation. */
+    NRF_DFU_RES_CODE_OPERATION_FAILED        = 0x0A,     /**< Operation failed. */
+    NRF_DFU_RES_CODE_EXT_ERROR               = 0x0B,     /**< Extended error. */
+} nrf_dfu_res_code_t;
+
+
+#if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__ICCARM__)
+  #pragma language=extended
+#elif defined(__GNUC__)
+  // Anonymous unions are enabled by default.
+#endif
+
+
+/** @brief Definition of a DFU request sent from the transport layer.
+ *
+ * @details When the transport layer gets a DFU event, it calls the function @ref nrf_dfu_req_handler_on_req to handle the DFU request.
+ */
+typedef struct
+{
+    nrf_dfu_req_op_t    req_type;       /**< Request operation type. */
+
+    union
+    {
+        struct
+        {
+            uint32_t        obj_type;       /**< Object type of the object to be created for a request of type @ref NRF_DFU_OBJECT_OP_CREATE. */
+            uint32_t        object_size;    /**< Size of the object to be created for a request of type @ref NRF_DFU_OBJECT_OP_CREATE. Note that the object size is not the same as the size of the firmware. */
+        };
+
+        struct
+        {
+            uint8_t *   p_req;      /**< Pointer to an array holding the serialized version of the request. */
+            uint32_t    req_len;    /**< Length of the request array. */
+        };
+    };
+} nrf_dfu_req_t;
+
+
+/** @brief Response used during DFU operations.
+ */
+typedef struct
+{
+    union
+    {
+        struct
+        {
+            uint8_t *       p_res;          /**< Pointer to an array holding the serialized version of the response. */
+            uint32_t        res_len;        /**< Length of the response array. */
+        };
+
+        struct
+        {
+            uint32_t        max_size;       /**< Maximum size of the object of a given type. */
+            uint32_t        offset;         /**< Current offset. */
+            uint32_t        crc;            /**< Current CRC. */
+        };
+    };
+} nrf_dfu_res_t;
+
+#if defined(__CC_ARM)
+  #pragma pop
+#elif defined(__ICCARM__)
+  // Leave anonymous unions enabled.
+#elif defined(__GNUC__)
+  // Anonymous unions are enabled by default.
+#endif
+
+
+/** @brief Function for initializing the request handling module.
+ *
+ * @details This function initializes the flash with or without the SoftDevice, depending on the project configuration.
+ *
+ * @retval NRF_SUCCESS             If the operation was successful.
+ * @retval NRF_ERROR_INVALID_STATE If the fstorage module could not be initiated or the SoftDevice could not set the event handler.
+ */
+uint32_t nrf_dfu_req_handler_init(void);
+
+
+/** @brief  Function type for handling a DFU request.
+ *
+ * @param[in,out]   p_context   Pointer to context-specific RAM required for
+ *                              running the command request.
+ *                              This value may be NULL if the command request
+ *                              does not require context-specific RAM.
+ * @param[in,out]   p_req       Pointer to the structure holding the DFU request.
+ * @param[in,out]   p_res       Pointer to the structure holding the DFU response.
+ *
+ * @retval NRF_DFU_RES_CODE_SUCCESS     If the command request was executed successfully.
+ *                                      Any other error code indicates that the request
+ *                                      could not be handled.
+ */
+nrf_dfu_res_code_t nrf_dfu_req_handler_on_req(void * p_context, nrf_dfu_req_t * p_req, nrf_dfu_res_t * p_res);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_DFU_REQ_HANDLER_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/bootloader/dfu/nrf_dfu_transport.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,97 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "nrf_dfu_transport.h"
+#include "nrf_log.h"
+
+
+#define DFU_TRANS_SECTION_VARS_GET(i)       NRF_SECTION_VARS_GET((i), nrf_dfu_transport_t, dfu_trans)
+#define DFU_TRANS_SECTION_VARS_COUNT        NRF_SECTION_VARS_COUNT(nrf_dfu_transport_t, dfu_trans)
+
+ //lint -save -e19 -e526
+NRF_SECTION_VARS_CREATE_SECTION(dfu_trans, const nrf_dfu_transport_t);
+//lint -restore
+
+uint32_t nrf_dfu_transports_init(void)
+{
+    uint32_t const num_transports = DFU_TRANS_SECTION_VARS_COUNT;
+    uint32_t ret_val = NRF_SUCCESS;
+
+    NRF_LOG_INFO("In nrf_dfu_transports_init\r\n");
+
+    NRF_LOG_INFO("num transports: %d\r\n", num_transports);
+
+    for (uint32_t i = 0; i < num_transports; i++)
+    {
+        nrf_dfu_transport_t * const trans = DFU_TRANS_SECTION_VARS_GET(i);
+        ret_val = trans->init_func();
+        if (ret_val != NRF_SUCCESS)
+        {
+            break;
+        }
+    }
+
+    NRF_LOG_INFO("After nrf_dfu_transports_init\r\n");
+
+    return ret_val;
+}
+
+
+uint32_t nrf_dfu_transports_close(void)
+{
+    uint32_t const num_transports = DFU_TRANS_SECTION_VARS_COUNT;
+    uint32_t ret_val = NRF_SUCCESS;
+
+    NRF_LOG_INFO("In nrf_dfu_transports_close\r\n");
+
+    NRF_LOG_INFO("num transports: %d\r\n", num_transports);
+
+    for (uint32_t i = 0; i < num_transports; i++)
+    {
+        nrf_dfu_transport_t * const trans = DFU_TRANS_SECTION_VARS_GET(i);
+        ret_val = trans->close_func();
+        if (ret_val != NRF_SUCCESS)
+        {
+            break;
+        }
+    }
+
+    NRF_LOG_INFO("After nrf_dfu_transports_init\r\n");
+
+    return ret_val;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/bootloader/dfu/nrf_dfu_transport.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,124 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**@file
+ *
+ * @defgroup sdk_nrf_dfu_transport DFU transport
+ * @{
+ * @ingroup  sdk_nrf_bootloader
+ * @brief Generic Device Firmware Update (DFU) transport interface.
+ *
+ * @details The DFU transport module defines a generic interface that must
+ *          be implemented for each transport layer.
+ */
+
+#ifndef NRF_DFU_TRANSPORT_H__
+#define NRF_DFU_TRANSPORT_H__
+
+#include <stdint.h>
+#include "section_vars.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @brief  Function type for initializing a DFU transport.
+ *
+ * @details This function initializes a DFU transport. The implementation
+ *          of the function must initialize DFU mode and stay in service
+ *          until either the device is reset or the DFU operation is finalized.
+ *          When the DFU transport receives requests, it should call @ref nrf_dfu_req_handler_on_req for handling the requests.
+ *
+ * @retval  NRF_SUCCESS     If initialization was successful for the transport. Any other return code indicates that the DFU transport could not be initialized.
+ */
+typedef uint32_t (*nrf_dfu_init_fn_t)(void);
+
+
+/** @brief  Function type for closing down a DFU transport.
+ *
+ * @details This function closes down a DFU transport in a gentle way.
+ *
+ * @retval  NRF_SUCCESS     If closing was successful for the transport. Any other return code indicates that the DFU transport could not be closed closed down.
+ */
+typedef uint32_t (*nrf_dfu_disconnect_fn_t)(void);
+
+
+/** @brief DFU transport registration.
+ *
+ * @details     Every DFU transport must provide a registration of the initialization function.
+ */
+typedef struct
+{
+    nrf_dfu_init_fn_t       init_func;          /**< Registration of the init function to run to initialize a DFU transport. */
+    nrf_dfu_disconnect_fn_t close_func;         /**< Registration of the close function to close down a DFU transport. */
+} nrf_dfu_transport_t;
+
+
+/** @brief Function for initializing all the registered DFU transports.
+ *
+ * @retval  NRF_SUCCESS     If all DFU transport were initialized successfully.
+ *                          Any other error code indicates that at least one DFU
+ *                          transport could not be initialized.
+ */
+uint32_t nrf_dfu_transports_init(void);
+
+/** @brief Function for closing down all the registered DFU transports.
+ *
+ * @retval  NRF_SUCCESS     If all DFU transport were closed down successfully.
+ *                          Any other error code indicates that at least one DFU
+ *                          transport could not be closed down.
+ */
+uint32_t nrf_dfu_transports_close(void);
+
+
+/** @brief  Macro for registering a DFU transport by using section variables.
+ *
+ * @details     This macro places a variable in a section named "dfu_trans", which
+ *              is initialized by @ref nrf_dfu_transports_init.
+ */
+#define DFU_TRANSPORT_REGISTER(trans_var) NRF_SECTION_VARS_REGISTER_VAR(dfu_trans, trans_var)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_DFU_TRANSPORT_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/bootloader/dfu/nrf_dfu_types.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,245 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**@file
+ *
+ * @defgroup sdk_nrf_dfu_types DFU types
+ * @{
+ * @ingroup  sdk_nrf_dfu
+ */
+
+#ifndef NRF_DFU_TYPES_H__
+#define NRF_DFU_TYPES_H__
+
+#include <stdint.h>
+#include <stddef.h>
+#include "nrf_mbr.h"
+#include "nrf_sdm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define INIT_COMMAND_MAX_SIZE       256     /**< Maximum size of the init command stored in dfu_settings. */
+
+
+/** @brief  Size of a flash codepage. This value is used for calculating the size of the reserved
+ *          flash space in the bootloader region. It is checked against NRF_UICR->CODEPAGESIZE
+ *          at run time to ensure that the region is correct.
+ */
+#if defined(NRF51)
+    #define CODE_PAGE_SIZE            (PAGE_SIZE_IN_WORDS * sizeof(uint32_t))
+#elif defined(NRF52) || defined(NRF52840_XXAA)
+    #define CODE_PAGE_SIZE            (MBR_PAGE_SIZE_IN_WORDS * sizeof(uint32_t))
+#else
+    #error "Architecture not set."
+#endif
+
+
+/** @brief  Maximum size of a data object.*/
+#if defined( NRF51 )
+    #define DATA_OBJECT_MAX_SIZE           (CODE_PAGE_SIZE * 4)
+#elif defined( NRF52_SERIES ) || defined ( __SDK_DOXYGEN__ )
+    #define DATA_OBJECT_MAX_SIZE           (CODE_PAGE_SIZE)
+#else
+    #error "Architecture not set."
+#endif
+
+/** @brief  Page location of the bootloader settings address.
+ */
+
+#if defined ( NRF51 )
+    #define BOOTLOADER_SETTINGS_ADDRESS     (0x0003FC00UL)
+#elif defined( NRF52832_XXAA )
+    #define BOOTLOADER_SETTINGS_ADDRESS     (0x0007F000UL)
+#elif defined( NRF52840_XXAA )
+    #define BOOTLOADER_SETTINGS_ADDRESS     (0x000FF000UL)
+#else
+    #error No valid target set for BOOTLOADER_SETTINGS_ADDRESS.
+#endif
+
+
+
+#if defined(NRF52) || defined(NRF52832)
+
+/**
+ * @brief   MBR parameters page in UICR.
+ *
+ * Register location in UICR where the page address of the MBR parameters page is stored (only used by the nRF52 MBR).
+ *
+ * @note If the value at the given location is 0xFFFFFFFF, no MBR parameters page is set.
+ */
+#define NRF_UICR_MBR_PARAMS_PAGE_ADDRESS    (NRF_UICR_BASE + 0x18)
+
+
+/** @brief Page location of the MBR parameters page address.
+ *
+ */
+#define NRF_MBR_PARAMS_PAGE_ADDRESS         (0x0007E000UL)
+
+#endif
+
+#if defined(NRF52840_XXAA)
+
+/**
+ * @brief   MBR parameters page in UICR.
+ *
+ * Register location in UICR where the page address of the MBR parameters page is stored (only used by the nRF52 MBR).
+ *
+ * @note If the value at the given location is 0xFFFFFFFF, no MBR parameters page is set.
+ */
+#define NRF_UICR_MBR_PARAMS_PAGE_ADDRESS     (NRF_UICR_BASE + 0x18)
+
+
+/** @brief Page location of the MBR parameters page address.
+ *
+ */
+#define NRF_MBR_PARAMS_PAGE_ADDRESS         (0x000FE000UL)
+
+#endif
+
+
+/** @brief  Size of the flash space reserved for application data.
+ */
+#ifndef DFU_APP_DATA_RESERVED
+#define DFU_APP_DATA_RESERVED               CODE_PAGE_SIZE * 3
+#endif
+
+
+/** @brief Total size of the region between the SoftDevice and the bootloader.
+ */
+#define DFU_REGION_TOTAL_SIZE               ((* (uint32_t *)NRF_UICR_BOOTLOADER_START_ADDRESS) - CODE_REGION_1_START)
+
+
+/** @brief Start address of the SoftDevice (excluding the area for the MBR).
+ */
+#define SOFTDEVICE_REGION_START             MBR_SIZE
+
+
+/** @brief Size of the Code Region 0, found in the UICR.CLEN0 register.
+ *
+ * @details This value is identical to the start of Code Region 1. This value is used for
+ *          compilation safety, because the linker will fail if the application expands
+ *          into the bootloader. At run time, the bootloader uses the value found in UICR.CLEN0.
+ */
+
+#ifndef CODE_REGION_1_START
+#define CODE_REGION_1_START                 SD_SIZE_GET(MBR_SIZE)
+#endif
+
+#define NRF_DFU_CURRENT_BANK_0 0x00
+#define NRF_DFU_CURRENT_BANK_1 0x01
+
+#define NRF_DFU_BANK_LAYOUT_DUAL   0x00
+#define NRF_DFU_BANK_LAYOUT_SINGLE 0x01
+
+
+/** @brief DFU bank state codes.
+ *
+ * @details The DFU bank state indicates the content of a bank:
+ *          A valid image of a certain type or an invalid image.
+ */
+
+#define NRF_DFU_BANK_INVALID     0x00 /**< Invalid image. */
+#define NRF_DFU_BANK_VALID_APP   0x01 /**< Valid application. */
+#define NRF_DFU_BANK_VALID_SD    0xA5 /**< Valid SoftDevice. */
+#define NRF_DFU_BANK_VALID_BL    0xAA /**< Valid bootloader. */
+#define NRF_DFU_BANK_VALID_SD_BL 0xAC /**< Valid SoftDevice and bootloader. */
+
+
+/** @brief Description of a single bank. */
+#pragma pack(4)
+typedef struct
+{
+    uint32_t                image_size;         /**< Size of the image in the bank. */
+    uint32_t                image_crc;          /**< CRC of the image. If set to 0, the CRC is ignored. */
+    uint32_t                bank_code;          /**< Identifier code for the bank. */
+} nrf_dfu_bank_t;
+
+/**@brief DFU progress.
+ *
+ * Be aware of the difference between objects and firmware images. A firmware image consists of multiple objects, each of a maximum size @ref DATA_OBJECT_MAX_SIZE.
+ */
+typedef struct
+{
+    uint32_t command_size;              /**< The size of the current init command stored in the DFU settings. */
+    uint32_t command_offset;            /**< The offset of the currently received init command data. The offset will increase as the init command is received. */
+    uint32_t command_crc;               /**< The calculated CRC of the init command (calculated after the transfer is completed). */
+
+    uint32_t data_object_size;          /**< The size of the last object created. Note that this size is not the size of the whole firmware image.*/
+
+    uint32_t firmware_image_crc;        /**< CRC value of the current firmware (continuously calculated as data is received). */
+    uint32_t firmware_image_crc_last;   /**< The CRC of the last executed object. */
+    uint32_t firmware_image_offset;     /**< The offset of the current firmware image being transferred. Note that this offset is the offset in the entire firmware image and not only the current object. */
+    uint32_t firmware_image_offset_last;/**< The offset of the last executed object from the start of the firmware image. */
+} dfu_progress_t;
+
+
+/**@brief DFU settings for application and bank data.
+ */
+typedef struct
+{
+    uint32_t            crc;                /**< CRC for the stored DFU settings, not including the CRC itself. If 0xFFFFFFF, the CRC has never been calculated. */
+    uint32_t            settings_version;   /**< Version of the currect dfu settings struct layout.*/
+    uint32_t            app_version;        /**< Version of the last stored application. */
+    uint32_t            bootloader_version; /**< Version of the last stored bootloader. */
+
+    uint32_t            bank_layout;        /**< Bank layout: single bank or dual bank. This value can change. */
+    uint32_t            bank_current;       /**< The bank that is currently used. */
+
+    nrf_dfu_bank_t      bank_0;             /**< Bank 0. */
+    nrf_dfu_bank_t      bank_1;             /**< Bank 1. */
+
+    uint32_t            write_offset;       /**< Write offset for the current operation. */
+    uint32_t            sd_size;            /**< SoftDevice size (if combined BL and SD). */
+
+    dfu_progress_t      progress;           /**< Current DFU progress. */
+
+    uint32_t            enter_buttonless_dfu;
+    uint8_t             init_command[INIT_COMMAND_MAX_SIZE];  /**< Buffer for storing the init command. */
+} nrf_dfu_settings_t;
+#pragma pack() // revert pack settings
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_DFU_TYPES_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/crc16/crc16.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,59 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(CRC16)
+#include "crc16.h"
+
+#include <stdlib.h>
+
+uint16_t crc16_compute(uint8_t const * p_data, uint32_t size, uint16_t const * p_crc)
+{
+    uint16_t crc = (p_crc == NULL) ? 0xFFFF : *p_crc;
+
+    for (uint32_t i = 0; i < size; i++)
+    {
+        crc  = (uint8_t)(crc >> 8) | (crc << 8);
+        crc ^= p_data[i];
+        crc ^= (uint8_t)(crc & 0xFF) >> 4;
+        crc ^= (crc << 8) << 4;
+        crc ^= ((crc & 0xFF) << 4) << 1;
+    }
+
+    return crc;
+}
+#endif //NRF_MODULE_ENABLED(CRC16)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/crc16/crc16.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,79 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup crc16 CRC16 compute
+ * @{
+ * @ingroup hci_transport
+ *
+ * @brief    This module implements CRC-16-CCITT (polynomial 0x1021) with 0xFFFF initial value.
+ *           The data can be passed in multiple blocks.
+ */
+
+#ifndef CRC16_H__
+#define CRC16_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Function for calculating CRC-16 in blocks.
+ *
+ * Feed each consecutive data block into this function, along with the current value of p_crc as
+ * returned by the previous call of this function. The first call of this function should pass NULL
+ * as the initial value of the crc in p_crc.
+ *
+ * @param[in] p_data The input data block for computation.
+ * @param[in] size   The size of the input data block in bytes.
+ * @param[in] p_crc  The previous calculated CRC-16 value or NULL if first call.
+ *
+ * @return The updated CRC-16 value, based on the input supplied.
+ */
+uint16_t crc16_compute(uint8_t const * p_data, uint32_t size, uint16_t const * p_crc);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // CRC16_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/crc32/crc32.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,59 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(CRC32)
+#include "crc32.h"
+
+#include <stdlib.h>
+
+uint32_t crc32_compute(uint8_t const * p_data, uint32_t size, uint32_t const * p_crc)
+{
+    uint32_t crc;
+
+    crc = (p_crc == NULL) ? 0xFFFFFFFF : ~(*p_crc);
+    for (uint32_t i = 0; i < size; i++)
+    {
+        crc = crc ^ p_data[i];
+        for (uint32_t j = 8; j > 0; j--)
+        {
+            crc = (crc >> 1) ^ (0xEDB88320U & ((crc & 1) ? 0xFFFFFFFF : 0));
+        }
+    }
+    return ~crc;
+}
+#endif //NRF_MODULE_ENABLED(CRC32)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/crc32/crc32.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,78 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup crc32 CRC32 compute
+ * @{
+ * @ingroup hci_transport
+ *
+ * @brief    This module implements the CRC-32 calculation in the blocks.
+ */
+
+#ifndef CRC32_H__
+#define CRC32_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Function for calculating CRC-32 in blocks.
+ *
+ * Feed each consecutive data block into this function, along with the current value of p_crc as
+ * returned by the previous call of this function. The first call of this function should pass NULL
+ * as the initial value of the crc in p_crc.
+ *
+ * @param[in] p_data The input data block for computation.
+ * @param[in] size   The size of the input data block in bytes.
+ * @param[in] p_crc  The previous calculated CRC-32 value or NULL if first call.
+ *
+ * @return The updated CRC-32 value, based on the input supplied.
+ */
+uint32_t crc32_compute(uint8_t const * p_data, uint32_t size, uint32_t const * p_crc);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // CRC32_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/experimental_section_vars/section_vars.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,282 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef SECTION_VARS_H__
+#define SECTION_VARS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @defgroup section_vars Section variables
+ * @ingroup app_common
+ * @{
+ *
+ * @brief Section variables.
+ */
+
+
+#if defined(__ICCARM__)
+// Enable IAR language extensions
+#pragma language=extended
+#endif
+
+
+// Macro to delay macro expansion.
+#define NRF_PRAGMA(x)                                       _Pragma(#x)
+
+
+//lint -save -e27 Illegal character (0x24)
+
+
+/**@brief   Macro to obtain the symbol marking the beginning of a given section.
+ *
+ * @details The symbol that this macro resolves to is used to obtain a section start address.
+ *
+ * @param[in]   section_name    Name of the section.
+ */
+#if defined(__CC_ARM)
+
+#define NRF_SECTION_VARS_START_SYMBOL(section_name)         section_name ## $$Base
+
+#elif defined(__GNUC__)
+
+#define NRF_SECTION_VARS_START_SYMBOL(section_name)         __start_ ## section_name
+
+#elif defined(__ICCARM__)
+
+#define NRF_SECTION_VARS_START_SYMBOL(section_name)         __section_begin(#section_name)
+
+#endif
+
+
+/**@brief   Macro to obtain the symbol marking the end of a given section.
+ *
+ * @details The symbol that this macro resolves to is used to obtain a section stop address.
+ *
+ * @param[in]   section_name    Name of the section.
+ */
+#if defined(__CC_ARM)
+
+#define NRF_SECTION_VARS_END_SYMBOL(section_name)           section_name ## $$Limit
+
+#elif defined(__GNUC__)
+
+#define NRF_SECTION_VARS_END_SYMBOL(section_name)           __stop_ ## section_name
+
+#elif defined(__ICCARM__)
+
+#define NRF_SECTION_VARS_END_SYMBOL(section_name)           __section_end(#section_name)
+
+#endif
+
+
+//lint -restore
+
+
+/**@brief   Macro for retrieving the length of a given section, in bytes.
+ *
+ * @param[in]   section_name    Name of the section.
+ */
+#if defined(__CC_ARM)
+
+#define NRF_SECTION_VARS_LENGTH(section_name) \
+    ((uint32_t)&NRF_SECTION_VARS_END_SYMBOL(section_name) - (uint32_t)&NRF_SECTION_VARS_START_SYMBOL(section_name))
+
+#elif defined(__GNUC__)
+
+ #define NRF_SECTION_VARS_LENGTH(section_name) \
+    ((uint32_t)&NRF_SECTION_VARS_END_SYMBOL(section_name) - (uint32_t)&NRF_SECTION_VARS_START_SYMBOL(section_name))
+
+#elif defined(__ICCARM__)
+
+ #define NRF_SECTION_VARS_LENGTH(section_name) \
+    ((uint32_t)NRF_SECTION_VARS_END_SYMBOL(section_name) - (uint32_t)NRF_SECTION_VARS_START_SYMBOL(section_name))
+
+#endif
+
+
+/**@brief   Macro to obtain the address of the beginning of a section.
+ *
+ * param[in]    section_name    Name of the section.
+ */
+#if defined(__CC_ARM)
+
+#define NRF_SECTION_VARS_START_ADDR(section_name)       (uint32_t)&NRF_SECTION_VARS_START_SYMBOL(section_name)
+
+#elif defined(__GNUC__)
+
+#define NRF_SECTION_VARS_START_ADDR(section_name)       (uint32_t)&NRF_SECTION_VARS_START_SYMBOL(section_name)
+
+#elif defined(__ICCARM__)
+
+#define NRF_SECTION_VARS_START_ADDR(section_name)       (uint32_t)iar_ ## section_name ## _start
+
+#endif
+
+
+/**@brief    Macro to obtain the address of end of a section.
+ *
+ * @param[in]   section_name    Name of the section.
+ */
+#if defined(__CC_ARM)
+
+#define NRF_SECTION_VARS_END_ADDR(section_name)         (uint32_t)&NRF_SECTION_VARS_END_SYMBOL(section_name)
+
+#elif defined(__GNUC__)
+
+#define NRF_SECTION_VARS_END_ADDR(section_name)         (uint32_t)&NRF_SECTION_VARS_END_SYMBOL(section_name)
+
+#elif defined(__ICCARM__)
+
+#define NRF_SECTION_VARS_END_ADDR(section_name)         (uint32_t)iar_ ## section_name ## _end
+
+#endif
+
+
+//lint -save -e19 -esym(526, fs_dataBase) -esym(526, fs_dataLimit) -esym(526, dfu_transBase) -esym(526, dfu_transLimit)
+
+/**@brief   Macro to create a section to register variables in.
+ *
+ * @param[in]   data_type       The data type of the variables to be registered in the section.
+ * @param[in]   section_name    Name of the section.
+ *
+ * @warning The data type must be word aligned to prevent padding.
+ */
+#if defined(__CC_ARM)
+
+#define NRF_SECTION_VARS_CREATE_SECTION(section_name, data_type)    \
+    extern data_type * NRF_SECTION_VARS_START_SYMBOL(section_name); \
+    extern void      * NRF_SECTION_VARS_END_SYMBOL(section_name)
+
+#elif defined(__GNUC__)
+
+#define NRF_SECTION_VARS_CREATE_SECTION(section_name, data_type)    \
+    extern data_type * NRF_SECTION_VARS_START_SYMBOL(section_name); \
+    extern void      * NRF_SECTION_VARS_END_SYMBOL(section_name)
+
+#elif defined(__ICCARM__)
+
+// No symbol registration required for IAR.
+#define NRF_SECTION_VARS_CREATE_SECTION(section_name, data_type)                    \
+    NRF_PRAGMA(section = #section_name);                                            \
+    extern void * iar_ ## section_name ## _start = __section_begin(#section_name);  \
+    extern void * iar_ ## section_name ## _end   = __section_end(#section_name)
+
+#endif
+
+//lint -restore
+
+
+/**@brief   Macro to declare a variable and register it in a section.
+ *
+ * @details Declares a variable and registers it in a named section. This macro ensures that the
+ *          variable is not stripped away when using optimizations.
+ *
+ * @note The order with which variables are placed in a section is dependant on the order with
+ *       which the linker encouters the variables during linking.
+ *
+ * @param[in]   section_name    Name of the section.
+ * @param[in]   section_var     The variable to register in the given section.
+ */
+#if defined(__CC_ARM)
+
+#define NRF_SECTION_VARS_REGISTER_VAR(section_name, section_var) \
+    static section_var __attribute__ ((section(#section_name))) __attribute__((used))
+
+#elif defined(__GNUC__)
+
+#define NRF_SECTION_VARS_REGISTER_VAR(section_name, section_var) \
+    static section_var __attribute__ ((section("."#section_name))) __attribute__((used))
+
+#elif defined(__ICCARM__)
+
+#define NRF_SECTION_VARS_REGISTER_VAR(section_name, section_var) \
+    __root section_var @ #section_name
+
+#endif
+
+
+/**@brief   Macro to retrieve a variable from a section.
+ *
+ * @warning     The stored symbol can only be resolved using this macro if the
+ *              type of the data is word aligned. The operation of acquiring
+ *              the stored symbol relies on sizeof of the stored type, no
+ *              padding can exist in the named section in between individual
+ *              stored items or this macro will fail.
+ *
+ * @param[in]   i               Index of the variable in section.
+ * @param[in]   data_type       Data type of the variable.
+ * @param[in]   section_name    Name of the section.
+ */
+#if defined(__CC_ARM)
+
+#define NRF_SECTION_VARS_GET(i, data_type, section_name) \
+    (data_type*)(NRF_SECTION_VARS_START_ADDR(section_name) + i * sizeof(data_type))
+
+#elif defined(__GNUC__)
+
+#define NRF_SECTION_VARS_GET(i, data_type, section_name) \
+    (data_type*)(NRF_SECTION_VARS_START_ADDR(section_name) + i * sizeof(data_type))
+
+#elif defined(__ICCARM__)
+
+#define NRF_SECTION_VARS_GET(i, data_type, section_name) \
+    (data_type*)(NRF_SECTION_VARS_START_ADDR(section_name) + i * sizeof(data_type))
+
+#endif
+
+
+/**@brief   Macro to get number of variables registered in a section.
+ *
+ * @param[in]   data_type       Data type of the variables in the section.
+ * @param[in]   section_name    Name of the section.
+ */
+#define NRF_SECTION_VARS_COUNT(data_type, section_name) \
+    NRF_SECTION_VARS_LENGTH(section_name) / sizeof(data_type)
+
+/** @} */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // SECTION_VARS_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fds/fds.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,2101 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(FDS)
+#include "fds.h"
+#include "fds_internal_defs.h"
+
+#include <stdint.h>
+#include <string.h>
+#include <stdbool.h>
+#include "fstorage.h"
+#include "nrf_error.h"
+
+#if defined(FDS_CRC_ENABLED)
+    #include "crc16.h"
+#endif
+
+
+static void fs_event_handler(fs_evt_t const * const evt, fs_ret_t result);
+
+// Our fstorage configuration.
+FS_REGISTER_CFG(fs_config_t fs_config) =
+{
+    .callback  = fs_event_handler,
+    .num_pages = FDS_PHY_PAGES,
+    // We register with the highest priority in order to be assigned
+    // the pages with the highest memory address (closest to the bootloader).
+    .priority  = 0xFF
+};
+
+// Used to flag a record as dirty, i.e. ready for garbage collection.
+static fds_tl_t const m_fds_tl_dirty =
+{
+    .record_key   = FDS_RECORD_KEY_DIRTY,
+    .length_words = 0xFFFF  // Leave the record length field unchanged in flash.
+};
+
+// Internal status flags.
+static uint8_t              m_flags;
+
+// The number of registered users and their callback functions.
+static uint8_t              m_users;
+static fds_cb_t             m_cb_table[FDS_MAX_USERS];
+
+// The latest (largest) record ID written so far.
+static uint32_t             m_latest_rec_id;
+
+// The internal queues.
+static fds_op_queue_t       m_op_queue;
+static fds_chunk_queue_t    m_chunk_queue;
+
+// Structures used to hold informations about virtual pages.
+static fds_page_t           m_pages[FDS_MAX_PAGES];
+static fds_swap_page_t      m_swap_page;
+
+// Garbage collection data.
+static fds_gc_data_t        m_gc;
+
+
+static void flag_set(fds_flags_t flag)
+{
+    CRITICAL_SECTION_ENTER();
+    m_flags |= flag;
+    CRITICAL_SECTION_EXIT();
+}
+
+
+static void flag_clear(fds_flags_t flag)
+{
+    CRITICAL_SECTION_ENTER();
+    m_flags &= ~(flag);
+    CRITICAL_SECTION_EXIT();
+}
+
+
+static bool flag_is_set(fds_flags_t flag)
+{
+    return (m_flags & flag);
+}
+
+
+static void event_send(fds_evt_t const * const p_evt)
+{
+    for (uint32_t user = 0; user < FDS_MAX_USERS; user++)
+    {
+        if (m_cb_table[user] != NULL)
+        {
+            m_cb_table[user](p_evt);
+        }
+    }
+}
+
+
+static void event_prepare(fds_op_t const * const p_op, fds_evt_t * const p_evt)
+{
+    switch (p_op->op_code)
+    {
+        case FDS_OP_INIT:
+            p_evt->id = FDS_EVT_INIT;
+            break;
+
+        case FDS_OP_WRITE:
+            p_evt->id               = FDS_EVT_WRITE;
+            p_evt->write.file_id    = p_op->write.header.ic.file_id;
+            p_evt->write.record_key = p_op->write.header.tl.record_key;
+            p_evt->write.record_id  = p_op->write.header.record_id;
+            break;
+
+        case FDS_OP_UPDATE:
+            p_evt->id                      = FDS_EVT_UPDATE;
+            p_evt->write.file_id           = p_op->write.header.ic.file_id;
+            p_evt->write.record_key        = p_op->write.header.tl.record_key;
+            p_evt->write.record_id         = p_op->write.header.record_id;
+            p_evt->write.is_record_updated = (p_op->write.step == FDS_OP_WRITE_DONE);
+            break;
+
+        case FDS_OP_DEL_RECORD:
+            p_evt->id             = FDS_EVT_DEL_RECORD;
+            p_evt->del.file_id    = p_op->del.file_id;
+            p_evt->del.record_key = p_op->del.record_key;
+            p_evt->del.record_id  = p_op->del.record_to_delete;
+            break;
+
+        case FDS_OP_DEL_FILE:
+            p_evt->id             = FDS_EVT_DEL_FILE;
+            p_evt->del.file_id    = p_op->del.file_id;
+            p_evt->del.record_key = FDS_RECORD_KEY_DIRTY;
+            break;
+
+        case FDS_OP_GC:
+            p_evt->id = FDS_EVT_GC;
+            break;
+
+        default:
+            // Should not happen.
+            break;
+    }
+}
+
+
+static bool header_is_valid(fds_header_t const * const p_header)
+{
+    return ((p_header->ic.file_id    != FDS_FILE_ID_INVALID) &&
+            (p_header->tl.record_key != FDS_RECORD_KEY_DIRTY));
+}
+
+
+static bool address_is_valid(uint32_t const * const p_addr)
+{
+    return ((p_addr != NULL) &&
+            (p_addr >= fs_config.p_start_addr) &&
+            (p_addr <= fs_config.p_end_addr)   &&
+            (is_word_aligned(p_addr)));
+}
+
+
+static bool chunk_is_aligned(fds_record_chunk_t const * const p_chunk, uint32_t num_chunks)
+{
+    for (uint32_t i = 0; i < num_chunks; i++)
+    {
+        if (!is_word_aligned(p_chunk[i].p_data))
+        {
+            return false;
+        }
+    }
+    return true;
+}
+
+
+// Reads a page tag, and determines if the page is used to store data or as swap.
+static fds_page_type_t page_identify(uint32_t const * const p_page_addr)
+{
+    if (p_page_addr[FDS_PAGE_TAG_WORD_0] != FDS_PAGE_TAG_MAGIC)
+    {
+        return FDS_PAGE_UNDEFINED;
+    }
+
+    switch (p_page_addr[FDS_PAGE_TAG_WORD_1])
+    {
+        case FDS_PAGE_TAG_SWAP:
+            return FDS_PAGE_SWAP;
+
+        case FDS_PAGE_TAG_DATA:
+            return FDS_PAGE_DATA;
+
+        default:
+            return FDS_PAGE_UNDEFINED;
+    }
+}
+
+
+static bool page_is_erased(uint32_t const * const p_page_addr)
+{
+    for (uint32_t i = 0; i < FDS_PAGE_SIZE; i++)
+    {
+        if (*(p_page_addr + i) != FDS_ERASED_WORD)
+        {
+            return false;
+        }
+    }
+
+    return true;
+}
+
+
+// NOTE: Must be called from within a critical section.
+static bool page_has_space(uint16_t page, uint16_t length_words)
+{
+    length_words += m_pages[page].write_offset;
+    length_words += m_pages[page].words_reserved;
+    return (length_words < FDS_PAGE_SIZE);
+}
+
+
+// Given a pointer to a record, find the index of the page on which it is stored.
+// Returns FDS_SUCCESS if the page is found, FDS_ERR_NOT_FOUND otherwise.
+static ret_code_t page_from_record(uint16_t * const p_page, uint32_t const * const p_rec)
+{
+    ret_code_t ret = FDS_ERR_NOT_FOUND;
+
+    CRITICAL_SECTION_ENTER();
+    for (uint16_t i = 0; i < FDS_MAX_PAGES; i++)
+    {
+        if ((p_rec > m_pages[i].p_addr) &&
+            (p_rec < m_pages[i].p_addr + FDS_PAGE_SIZE))
+        {
+            ret     = FDS_SUCCESS;
+            *p_page = i;
+            break;
+        }
+    }
+    CRITICAL_SECTION_EXIT();
+
+    return ret;
+}
+
+
+// Scan a page to determine how many words have been written to it.
+// This information is used to set the page write offset during initialization.
+// Additionally, this function updates the latest record ID as it proceeds.
+// If an invalid record header is found, the can_gc argument is set to true.
+static void page_scan(uint32_t const *       p_addr,
+                      uint16_t       * const words_written,
+                      bool           * const can_gc)
+{
+    uint32_t const * const p_end_addr          = p_addr + FDS_PAGE_SIZE;
+    bool                   dirty_record_found  = false;
+
+    p_addr         += FDS_PAGE_TAG_SIZE;
+    *words_written  = FDS_PAGE_TAG_SIZE;
+
+    while ((p_addr < p_end_addr) && (*p_addr != FDS_ERASED_WORD))
+    {
+        // NOTE: Skip records with a dirty key or with a missing file ID.
+        fds_header_t const * const p_header = (fds_header_t*)p_addr;
+
+        if (!header_is_valid(p_header))
+        {
+            dirty_record_found = true;
+        }
+        else
+        {
+            // Update the latest (largest) record ID.
+            if (p_header->record_id > m_latest_rec_id)
+            {
+               m_latest_rec_id = p_header->record_id;
+            }
+        }
+
+        // Jump to the next record.
+        p_addr         += (FDS_HEADER_SIZE + p_header->tl.length_words);
+        *words_written += (FDS_HEADER_SIZE + p_header->tl.length_words);
+    }
+
+    if (can_gc != NULL)
+    {
+        *can_gc = dirty_record_found;
+    }
+}
+
+
+static void page_offsets_update(fds_page_t * const p_page, uint16_t length_words)
+{
+    p_page->write_offset   += (FDS_HEADER_SIZE + length_words);
+    p_page->words_reserved -= (FDS_HEADER_SIZE + length_words);
+}
+
+
+// Tags a page as swap, i.e., reserved for GC.
+static ret_code_t page_tag_write_swap()
+{
+    // Needs to be statically allocated since it will be written to flash.
+    static uint32_t const page_tag_swap[] = {FDS_PAGE_TAG_MAGIC, FDS_PAGE_TAG_SWAP};
+    return fs_store(&fs_config, m_swap_page.p_addr, page_tag_swap, FDS_PAGE_TAG_SIZE, NULL);
+}
+
+
+// Tags a page as data, i.e, ready for storage.
+static ret_code_t page_tag_write_data(uint32_t const * const p_page_addr)
+{
+    // Needs to be statically allocated since it will be written to flash.
+    static uint32_t const page_tag_data[] = {FDS_PAGE_TAG_MAGIC, FDS_PAGE_TAG_DATA};
+    return fs_store(&fs_config, p_page_addr, page_tag_data, FDS_PAGE_TAG_SIZE, NULL);
+}
+
+
+// Reserve space on a page.
+// NOTE: this function takes into the account the space required for the record header.
+static ret_code_t write_space_reserve(uint16_t length_words, uint16_t * p_page)
+{
+    bool           space_reserved  = false;
+    uint16_t const total_len_words = length_words + FDS_HEADER_SIZE;
+
+    if (total_len_words >= FDS_PAGE_SIZE - FDS_PAGE_TAG_SIZE)
+    {
+        return FDS_ERR_RECORD_TOO_LARGE;
+    }
+
+    CRITICAL_SECTION_ENTER();
+    for (uint16_t page = 0; page < FDS_MAX_PAGES; page++)
+    {
+        if ((m_pages[page].page_type == FDS_PAGE_DATA) &&
+            (page_has_space(page, total_len_words)))
+        {
+            space_reserved = true;
+            *p_page        = page;
+
+            m_pages[page].words_reserved += total_len_words;
+            break;
+        }
+    }
+    CRITICAL_SECTION_EXIT();
+
+    return (space_reserved) ? FDS_SUCCESS : FDS_ERR_NO_SPACE_IN_FLASH;
+}
+
+
+// Undo a write_space_reserve() call.
+// NOTE: Must be called within a critical section.
+static void write_space_free(uint16_t length_words, uint16_t page)
+{
+    m_pages[page].words_reserved -= (length_words + FDS_HEADER_SIZE);
+}
+
+
+static uint32_t record_id_new(void)
+{
+    CRITICAL_SECTION_ENTER();
+    m_latest_rec_id++;
+    CRITICAL_SECTION_EXIT();
+    return m_latest_rec_id;
+}
+
+
+// Given a page and a record, finds the next valid record on that page. If p_record is NULL,
+// search from the beginning of the page, otherwise, resume searching from the address
+// pointed by p_record. Returns true if a record is found, returns false otherwise.
+// If no record is found, p_record is unchanged.
+static bool record_find_next(uint16_t page, uint32_t const ** p_record)
+{
+    fds_header_t const * p_header;
+    uint32_t     const * p_next_rec = (*p_record);
+
+    // If this is not the first invocation on this page, then jump to the next record.
+    // Otherwise, start searching from the beginning of the page.
+    if (p_next_rec != NULL)
+    {
+        p_header    = ((fds_header_t*)p_next_rec);
+        p_next_rec += (FDS_HEADER_SIZE + p_header->tl.length_words);
+    }
+    else
+    {
+        p_next_rec = m_pages[page].p_addr + FDS_PAGE_TAG_SIZE;
+    }
+
+    // Read records from the page, until a valid record is found or the end of the page is
+    // reached. The argument p_record is only updated if a valid record is found.
+    while ((p_next_rec < (m_pages[page].p_addr + FDS_PAGE_SIZE) &&
+           *p_next_rec != FDS_ERASED_WORD))
+    {
+        p_header = (fds_header_t*)p_next_rec;
+
+        if (header_is_valid(p_header))
+        {
+            *p_record = p_next_rec;
+            return true;
+        }
+        else
+        {
+            // The record is not valid, jump to the next.
+            p_next_rec += (FDS_HEADER_SIZE + (p_header->tl.length_words));
+        }
+    }
+
+    // No more valid records on this page.
+    return false;
+}
+
+
+// Find a record given its descriptor and retrive the page in which the record is stored.
+// NOTE: Do not pass NULL as an argument for p_page.
+static bool record_find_by_desc(fds_record_desc_t * const p_desc, uint16_t * const p_page)
+{
+    // If the gc_run_count field in the descriptor matches our counter, then the record has
+    // not been moved. If the address is valid, and the record ID matches, there is no need
+    // to find the record again. Only lookup the page in which the record is stored.
+
+    if ((address_is_valid(p_desc->p_record))     &&
+        (p_desc->gc_run_count == m_gc.run_count) &&
+        (p_desc->record_id    == ((fds_header_t*)p_desc->p_record)->record_id))
+    {
+        return (page_from_record(p_page, p_desc->p_record) == FDS_SUCCESS);
+    }
+
+    // Otherwise, find the record in flash.
+    for (*p_page = 0; *p_page < FDS_MAX_PAGES; (*p_page)++)
+    {
+        // Set p_record to NULL to make record_find_next() search from the beginning of the page.
+        uint32_t const * p_record = NULL;
+
+        while (record_find_next(*p_page, &p_record))
+        {
+            fds_header_t const * const p_header = (fds_header_t*)p_record;
+            if (p_header->record_id == p_desc->record_id)
+            {
+                p_desc->p_record     = p_record;
+                p_desc->gc_run_count = m_gc.run_count;
+                return true;
+            }
+        }
+    }
+
+    return false;
+}
+
+
+// Search for a record and return its descriptor.
+// If p_file_id is NULL, only the record key will be used for matching.
+// If p_record_key is NULL, only the file ID will be used for matching.
+// If both are NULL, it will iterate through all records.
+static ret_code_t record_find(uint16_t          const * const p_file_id,
+                              uint16_t          const * const p_record_key,
+                              fds_record_desc_t       * const p_desc,
+                              fds_find_token_t        * const p_token)
+{
+    if (!flag_is_set(FDS_FLAG_INITIALIZED))
+    {
+        return FDS_ERR_NOT_INITIALIZED;
+    }
+
+    if (p_desc == NULL || p_token == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    // Begin (or resume) searching for a record.
+    for (; p_token->page < FDS_MAX_PAGES; p_token->page++)
+    {
+        if (m_pages[p_token->page].page_type != FDS_PAGE_DATA)
+        {
+            // Skip this page.
+            continue;
+        }
+
+        while (record_find_next(p_token->page, &p_token->p_addr))
+        {
+            fds_header_t const * const p_header = (fds_header_t*)p_token->p_addr;
+
+            // A valid record was found, check its header for a match.
+            if ((p_file_id != NULL) &&
+                (p_header->ic.file_id != *p_file_id))
+            {
+                continue;
+            }
+
+            if ((p_record_key != NULL) &&
+                (p_header->tl.record_key != *p_record_key))
+            {
+                continue;
+            }
+
+            // Record found; update the descriptor.
+            p_desc->record_id    = p_header->record_id;
+            p_desc->p_record     = p_token->p_addr;
+            p_desc->gc_run_count = m_gc.run_count;
+
+            return FDS_SUCCESS;
+        }
+
+        // We have scanned an entire page. Set the address in the token to NULL
+        // so that it will be updated in the next iteration.
+        p_token->p_addr = NULL;
+    }
+
+    return FDS_ERR_NOT_FOUND;
+}
+
+
+// Retrieve basic statistics about dirty records on a page.
+static void dirty_records_stat(uint16_t         page,
+                               uint16_t * const p_dirty_records,
+                               uint16_t * const p_word_count)
+{
+    fds_header_t const * p_header;
+    uint32_t     const * p_rec;
+
+    p_rec = m_pages[page].p_addr + FDS_PAGE_TAG_SIZE;
+
+    while ((p_rec < (m_pages[page].p_addr + FDS_PAGE_SIZE)) &&
+           (*p_rec != FDS_ERASED_WORD))
+    {
+        p_header = (fds_header_t*)p_rec;
+
+        if (!header_is_valid(p_header))
+        {
+            (*p_dirty_records) += 1;
+            (*p_word_count)    += FDS_HEADER_SIZE + p_header->tl.length_words;
+        }
+
+        p_rec += (FDS_HEADER_SIZE + (p_header->tl.length_words));
+    }
+}
+
+
+// Advances one position in the queue.
+// Returns true if the queue is not empty.
+static bool queue_advance(void)
+{
+    // Reset the current element.
+    memset(&m_op_queue.op[m_op_queue.rp], 0x00, sizeof(fds_op_t));
+
+    if (m_op_queue.count != 0)
+    {
+        // Advance in the queue, wrapping around if necessary.
+        m_op_queue.rp = (m_op_queue.rp + 1) % FDS_OP_QUEUE_SIZE;
+        m_op_queue.count--;
+    }
+
+    return (m_op_queue.count != 0);
+}
+
+
+// Given a pointer to an element in the chunk queue, computes the pointer to
+// the next element in the queue. Handles wrap around.
+void chunk_queue_next(fds_record_chunk_t ** pp_chunk)
+{
+    if ((*pp_chunk) != &m_chunk_queue.chunk[FDS_CHUNK_QUEUE_SIZE - 1])
+    {
+        (*pp_chunk)++;
+        return;
+    }
+
+    *pp_chunk = &m_chunk_queue.chunk[0];
+}
+
+
+// Retrieve the current chunk, and advance the queue.
+static void chunk_queue_get_and_advance(fds_record_chunk_t ** pp_chunk)
+{
+    if (m_chunk_queue.count != 0)
+    {
+        // Point to the current chunk and advance the queue.
+        *pp_chunk = &m_chunk_queue.chunk[m_chunk_queue.rp];
+
+        m_chunk_queue.rp = (m_chunk_queue.rp + 1) % FDS_CHUNK_QUEUE_SIZE;
+        m_chunk_queue.count--;
+    }
+}
+
+
+static void chunk_queue_skip(fds_op_t const * const p_op)
+{
+    if ((p_op->op_code == FDS_OP_WRITE) ||
+        (p_op->op_code == FDS_OP_UPDATE))
+    {
+        m_chunk_queue.rp    += p_op->write.chunk_count;
+        m_chunk_queue.count -= p_op->write.chunk_count;
+    }
+}
+
+
+// Enqueue an operation.
+static bool op_enqueue(fds_op_t           const * const p_op,
+                       uint32_t                         num_chunks,
+                       fds_record_chunk_t const * const p_chunk)
+{
+    uint32_t idx;
+    bool     ret = false;
+
+    CRITICAL_SECTION_ENTER();
+    if  ((m_op_queue.count    <= FDS_OP_QUEUE_SIZE - 1) &&
+         (m_chunk_queue.count <= FDS_CHUNK_QUEUE_SIZE - num_chunks))
+    {
+        idx = (m_op_queue.count + m_op_queue.rp) % FDS_OP_QUEUE_SIZE;
+
+        m_op_queue.op[idx] = *p_op;
+        m_op_queue.count++;
+
+        if (num_chunks != 0)
+        {
+            idx = (m_chunk_queue.count + m_chunk_queue.rp) % FDS_CHUNK_QUEUE_SIZE;
+
+            fds_record_chunk_t * p_chunk_dst;
+            p_chunk_dst = &m_chunk_queue.chunk[idx];
+
+            for (uint32_t i = 0; i < num_chunks; i++)
+            {
+                *p_chunk_dst = p_chunk[i];
+                chunk_queue_next(&p_chunk_dst);
+            }
+
+            m_chunk_queue.count += num_chunks;
+        }
+
+        ret = true;
+    }
+    CRITICAL_SECTION_EXIT();
+
+    return ret;
+}
+
+
+// This function is called during initialization to setup the page structure (m_pages) and
+// provide additional information regarding eventual further initialization steps.
+static fds_init_opts_t pages_init()
+{
+    uint32_t ret = NO_PAGES;
+    // The index of the page being initialized in m_pages[].
+    uint16_t page = 0;
+    bool     swap_set_but_not_found  = false;
+
+    for (uint16_t i = 0; i < FDS_VIRTUAL_PAGES; i++)
+    {
+        uint32_t        const * const p_page_addr = fs_config.p_start_addr + (i * FDS_PAGE_SIZE);
+        fds_page_type_t const         page_type   = page_identify(p_page_addr);
+
+        switch (page_type)
+        {
+            case FDS_PAGE_UNDEFINED:
+                if (page_is_erased(p_page_addr))
+                {
+                    if (m_swap_page.p_addr != NULL)
+                    {
+                        // If a swap page is already set, flag the page as erased (in m_pages)
+                        // and try to tag it as data (in flash) later on during initialization.
+                        m_pages[page].page_type    = FDS_PAGE_ERASED;
+                        m_pages[page].p_addr       = p_page_addr;
+                        m_pages[page].write_offset = FDS_PAGE_TAG_SIZE;
+
+                        // This is a candidate for a potential new swap page, in case the
+                        // current swap is going to be promoted to complete a GC instance.
+                        m_gc.cur_page = page;
+                        page++;
+                    }
+                    else
+                    {
+                        // If there is no swap page yet, use this one.
+                        m_swap_page.p_addr       = p_page_addr;
+                        m_swap_page.write_offset = FDS_PAGE_TAG_SIZE;
+                        swap_set_but_not_found   = true;
+                    }
+
+                    ret |= PAGE_ERASED;
+                }
+                else
+                {
+                    // Do not initialize or use this page.
+                    m_pages[page++].page_type = FDS_PAGE_UNDEFINED;
+                }
+                break;
+
+            case FDS_PAGE_DATA:
+                m_pages[page].page_type = FDS_PAGE_DATA;
+                m_pages[page].p_addr    = p_page_addr;
+                // Scan the page to compute its write offset and determine whether or not the page
+                // can be garbage collected. Additionally, update the latest kwown record ID.
+                page_scan(p_page_addr, &m_pages[page].write_offset, &m_pages[page].can_gc);
+
+                ret |= PAGE_DATA;
+                page++;
+
+                break;
+
+            case FDS_PAGE_SWAP:
+                if (swap_set_but_not_found)
+                {
+                    m_pages[page].page_type    = FDS_PAGE_ERASED;
+                    m_pages[page].p_addr       = m_swap_page.p_addr;
+                    m_pages[page].write_offset = FDS_PAGE_TAG_SIZE;
+
+                    page++;
+                }
+
+                m_swap_page.p_addr = p_page_addr;
+                // If the swap is promoted, this offset should be kept, otherwise,
+                // it should be set to FDS_PAGE_TAG_SIZE.
+                page_scan(p_page_addr, &m_swap_page.write_offset, NULL);
+
+                ret |= (m_swap_page.write_offset == FDS_PAGE_TAG_SIZE) ?
+                        SWAP_EMPTY : SWAP_DIRTY;
+                break;
+
+            default:
+                // Shouldn't happen.
+                break;
+        }
+    }
+
+    return (fds_init_opts_t)ret;
+}
+
+
+// Write the first part of a record header (the key and length).
+static ret_code_t record_header_write_begin(fds_op_t * const p_op, uint32_t * const p_addr)
+{
+    ret_code_t ret;
+    ret = fs_store(&fs_config, p_addr + FDS_OFFSET_TL,
+                  (uint32_t*)&p_op->write.header.tl, FDS_HEADER_SIZE_TL, NULL);
+
+    // Write the record ID next.
+    p_op->write.step = FDS_OP_WRITE_RECORD_ID;
+
+    return (ret == FS_SUCCESS) ? FDS_SUCCESS : FDS_ERR_BUSY;
+}
+
+
+static ret_code_t record_header_write_id(fds_op_t * const p_op, uint32_t * const p_addr)
+{
+    ret_code_t ret;
+    ret = fs_store(&fs_config, p_addr + FDS_OFFSET_ID,
+                   (uint32_t*)&p_op->write.header.record_id, FDS_HEADER_SIZE_ID, NULL);
+
+    // If this record has zero chunk, write the last part of the header directly.
+    // Otherwise, write the record chunks next.
+    p_op->write.step = (p_op->write.chunk_count != 0) ? FDS_OP_WRITE_CHUNKS :
+                                                        FDS_OP_WRITE_HEADER_FINALIZE;
+
+    return (ret == FS_SUCCESS) ? FDS_SUCCESS : FDS_ERR_BUSY;
+}
+
+
+static ret_code_t record_header_write_finalize(fds_op_t * const p_op, uint32_t * const p_addr)
+{
+    ret_code_t ret;
+    ret = fs_store(&fs_config, p_addr + FDS_OFFSET_IC,
+                   (uint32_t*)&p_op->write.header.ic, FDS_HEADER_SIZE_IC, NULL);
+
+    // If this is a simple write operation, then this is the last step.
+    // If this is an update instead, delete the old record next.
+    p_op->write.step = (p_op->op_code == FDS_OP_UPDATE) ? FDS_OP_WRITE_FLAG_DIRTY :
+                                                          FDS_OP_WRITE_DONE;
+
+    return (ret == FS_SUCCESS) ? FDS_SUCCESS : FDS_ERR_BUSY;
+}
+
+
+static ret_code_t record_header_flag_dirty(uint32_t * const p_record, uint16_t page_to_gc)
+{
+    // Flag the record as dirty.
+    fs_ret_t ret = fs_store(&fs_config, p_record,
+                            (uint32_t*)&m_fds_tl_dirty, FDS_HEADER_SIZE_TL, NULL);
+
+    if (ret != FS_SUCCESS)
+    {
+        return FDS_ERR_BUSY;
+    }
+
+    m_pages[page_to_gc].can_gc = true;
+
+    return FDS_SUCCESS;
+}
+
+
+static ret_code_t record_find_and_delete(fds_op_t * const p_op)
+{
+    ret_code_t        ret;
+    uint16_t          page;
+    fds_record_desc_t desc = {0};
+
+    desc.record_id = p_op->del.record_to_delete;
+
+    if (record_find_by_desc(&desc, &page))
+    {
+        fds_header_t const * const p_header = (fds_header_t const *)desc.p_record;
+
+        // Copy the record key and file ID, so that they can be returned in the event.
+        // In case this function is run as part of an update, there is no need to copy
+        // the file ID and record key since they are present in the header stored
+        // in the queue element.
+
+        p_op->del.file_id    = p_header->ic.file_id;
+        p_op->del.record_key = p_header->tl.record_key;
+
+        // Flag the record as dirty.
+        ret = record_header_flag_dirty((uint32_t*)desc.p_record, page);
+    }
+    else
+    {
+        // The record never existed, or it has already been deleted.
+        ret = FDS_ERR_NOT_FOUND;
+    }
+
+    return ret;
+}
+
+
+// Finds a record within a file and flags it as dirty.
+static ret_code_t file_find_and_delete(fds_op_t * const p_op)
+{
+    ret_code_t        ret;
+    fds_record_desc_t desc;
+
+    // This token must persist across calls.
+    static fds_find_token_t tok = {0};
+
+    // Pass NULL to ignore the record key.
+    ret = record_find(&p_op->del.file_id, NULL, &desc, &tok);
+
+    if (ret == FDS_SUCCESS)
+    {
+         // A record was found: flag it as dirty.
+        ret = record_header_flag_dirty((uint32_t*)desc.p_record, tok.page);
+    }
+    else // FDS_ERR_NOT_FOUND
+    {
+        // No more records were found. Zero the token, so that it can be reused.
+        memset(&tok, 0x00, sizeof(fds_find_token_t));
+    }
+
+    return ret;
+}
+
+
+// Writes a record chunk to flash and advances the chunk queue. Additionally, decrements
+// the number of chunks left to write for this operation and accumulates the offset.
+static ret_code_t record_write_chunk(fds_op_t * const p_op, uint32_t * const p_addr)
+{
+    ret_code_t           ret;
+    fds_record_chunk_t * p_chunk = NULL;
+
+    // Retrieve the next chunk to be written.
+    chunk_queue_get_and_advance(&p_chunk);
+
+    ret = fs_store(&fs_config, p_addr + p_op->write.chunk_offset,
+                   p_chunk->p_data, p_chunk->length_words, NULL);
+
+    // Accumulate the offset.
+    p_op->write.chunk_offset += p_chunk->length_words;
+
+    // Decrement the number of chunks left to write.
+    // NOTE: If chunk_count is initially zero, this function is not called
+    // because this step is skipped entirely. See record_header_write_id().
+    p_op->write.chunk_count--;
+
+    if (p_op->write.chunk_count == 0)
+    {
+        // All record chunks have been written; write the last part of
+        // the record header to finalize the write operation.
+        p_op->write.step = FDS_OP_WRITE_HEADER_FINALIZE;
+    }
+
+    return (ret == NRF_SUCCESS) ? FDS_SUCCESS : FDS_ERR_BUSY;
+}
+
+
+#if defined(FDS_CRC_ENABLED)
+
+static bool crc_verify_success(uint16_t crc, uint16_t len_words, uint32_t const * const p_data)
+{
+    uint16_t computed_crc;
+
+    // The CRC is computed on the entire record, except the CRC field itself.
+    // The record header is 12 bytes, out of these we have to skip bytes 6 to 8 where the
+    // CRC itself is stored. Then we compute the CRC for the rest of the record, from byte 8 of
+    // the header (where the record ID begins) to the end of the record data.
+    computed_crc = crc16_compute((uint8_t const *)p_data,  6, NULL);
+    computed_crc = crc16_compute((uint8_t const *)p_data + 8,
+                                 (FDS_HEADER_SIZE_ID + len_words) * sizeof(uint32_t),
+                                 &computed_crc);
+
+    return (computed_crc == crc);
+}
+
+#endif
+
+
+static void gc_init(void)
+{
+    m_gc.run_count++;
+    m_gc.cur_page = 0;
+    m_gc.resume   = false;
+
+    // Setup which pages to GC. Defer checking for open records and the can_gc flag,
+    // as other operations might change those while GC is running.
+    for (uint16_t i = 0; i < FDS_MAX_PAGES; i++)
+    {
+        m_gc.do_gc_page[i] = (m_pages[i].page_type == FDS_PAGE_DATA);
+    }
+}
+
+
+// Obtain the next page to be garbage collected.
+// Returns true if there are pages left to garbage collect, returns false otherwise.
+static bool gc_page_next(uint16_t * const p_next_page)
+{
+    bool ret = false;
+
+    for (uint16_t i = 0; i < FDS_MAX_PAGES; i++)
+    {
+        if (m_gc.do_gc_page[i])
+        {
+            // Do not attempt to GC this page again.
+            m_gc.do_gc_page[i] = false;
+
+            // Only GC pages with no open records and with some records which have been deleted.
+            if ((m_pages[i].records_open == 0) && (m_pages[i].can_gc == true))
+            {
+                *p_next_page = i;
+                ret = true;
+                break;
+            }
+        }
+    }
+
+    return ret;
+}
+
+
+static ret_code_t gc_swap_erase(void)
+{
+    m_gc.state               = GC_DISCARD_SWAP;
+    m_swap_page.write_offset = FDS_PAGE_TAG_SIZE;
+
+    return fs_erase(&fs_config, m_swap_page.p_addr, FDS_PHY_PAGES_IN_VPAGE, NULL);
+}
+
+
+// Erase the page being garbage collected, or erase the swap in case there are any open
+// records on the page being garbage collected.
+static ret_code_t gc_page_erase(void)
+{
+    uint32_t       ret;
+    uint16_t const gc = m_gc.cur_page;
+
+    if (m_pages[gc].records_open == 0)
+    {
+        ret = fs_erase(&fs_config, m_pages[gc].p_addr, FDS_PHY_PAGES_IN_VPAGE, NULL);
+        m_gc.state = GC_ERASE_PAGE;
+    }
+    else
+    {
+        // If there are open records, stop garbage collection on this page.
+        // Discard the swap and try to garbage collect another page.
+        ret = gc_swap_erase();
+    }
+
+    return ret;
+}
+
+
+// Copy the current record to swap.
+static ret_code_t gc_record_copy(void)
+{
+    fds_header_t const * const p_header   = (fds_header_t*)m_gc.p_record_src;
+    uint32_t     const * const p_dest     = m_swap_page.p_addr + m_swap_page.write_offset;
+    uint16_t     const         record_len = FDS_HEADER_SIZE + p_header->tl.length_words;
+
+    m_gc.state = GC_COPY_RECORD;
+
+    // Copy the record to swap; it is guaranteed to fit in the destination page,
+    // so there is no need to check its size. This will either succeed or timeout.
+    return fs_store(&fs_config, p_dest, m_gc.p_record_src, record_len, NULL);
+}
+
+
+static ret_code_t gc_record_find_next(void)
+{
+    ret_code_t ret;
+
+    // Find the next valid record to copy.
+    if (record_find_next(m_gc.cur_page, &m_gc.p_record_src))
+    {
+        ret = gc_record_copy();
+    }
+    else
+    {
+        // No more records left to copy on this page; swap pages.
+        ret = gc_page_erase();
+    }
+
+    return ret;
+}
+
+
+// Promote the swap by tagging it as a data page.
+static ret_code_t gc_swap_promote(void)
+{
+    m_gc.state = GC_PROMOTE_SWAP;
+    return page_tag_write_data(m_pages[m_gc.cur_page].p_addr);
+}
+
+
+// Tag the page just garbage collected as swap.
+static ret_code_t gc_tag_new_swap(void)
+{
+    m_gc.state        = GC_TAG_NEW_SWAP;
+    m_gc.p_record_src = NULL;
+    return page_tag_write_swap();
+}
+
+
+static ret_code_t gc_next_page(void)
+{
+    if (!gc_page_next(&m_gc.cur_page))
+    {
+        // No pages left to GC; GC has terminated. Reset the state.
+        m_gc.state        = GC_BEGIN;
+        m_gc.cur_page     = 0;
+        m_gc.p_record_src = NULL;
+
+        return FDS_OP_COMPLETED;
+    }
+
+    return gc_record_find_next();
+}
+
+
+// Update the swap page offeset after a record has been successfully copied to it.
+static void gc_update_swap_offset(void)
+{
+    fds_header_t const * const p_header   = (fds_header_t*)m_gc.p_record_src;
+    uint16_t     const         record_len = FDS_HEADER_SIZE + p_header->tl.length_words;
+
+    m_swap_page.write_offset += record_len;
+}
+
+
+static void gc_swap_pages(void)
+{
+    // The page being garbage collected will be the new swap page,
+    // and the current swap will be used as a data page (promoted).
+    uint32_t const * const p_addr = m_swap_page.p_addr;
+
+    m_swap_page.p_addr            = m_pages[m_gc.cur_page].p_addr;
+    m_pages[m_gc.cur_page].p_addr = p_addr;
+
+    // Keep the offset for this page, but reset it for the swap.
+    m_pages[m_gc.cur_page].write_offset = m_swap_page.write_offset;
+    m_swap_page.write_offset            = FDS_PAGE_TAG_SIZE;
+}
+
+
+static void gc_state_advance(void)
+{
+    switch (m_gc.state)
+    {
+        case GC_BEGIN:
+            gc_init();
+            m_gc.state = GC_NEXT_PAGE;
+            break;
+
+        // A record was successfully copied.
+        case GC_COPY_RECORD:
+            gc_update_swap_offset();
+            m_gc.state = GC_FIND_NEXT_RECORD;
+            break;
+
+        // A page was successfully erased. Prepare to promote the swap.
+        case GC_ERASE_PAGE:
+            gc_swap_pages();
+            m_gc.state = GC_PROMOTE_SWAP;
+            break;
+
+        // Swap was discarded because the page being GC'ed had open records.
+        case GC_DISCARD_SWAP:
+        // Swap was sucessfully promoted.
+        case GC_PROMOTE_SWAP:
+            // Prepare to tag the page just GC'ed as swap.
+            m_gc.state = GC_TAG_NEW_SWAP;
+            break;
+
+        case GC_TAG_NEW_SWAP:
+            m_gc.state = GC_NEXT_PAGE;
+            break;
+
+        default:
+            // Should not happen.
+            break;
+    }
+}
+
+
+// Initialize the filesystem.
+static ret_code_t init_execute(uint32_t prev_ret, fds_op_t * const p_op)
+{
+    ret_code_t ret = FDS_ERR_INTERNAL;
+
+    if (prev_ret != FS_SUCCESS)
+    {
+        // A previous operation has timed out.
+        flag_clear(FDS_FLAG_INITIALIZING);
+        return FDS_ERR_OPERATION_TIMEOUT;
+    }
+
+    switch (p_op->init.step)
+    {
+        case FDS_OP_INIT_TAG_SWAP:
+            // The page write offset was determined previously by pages_init().
+            ret             = page_tag_write_swap();
+            p_op->init.step = FDS_OP_INIT_TAG_DATA;
+            break;
+
+        case FDS_OP_INIT_TAG_DATA:
+        {
+            // Tag remaining erased pages as data.
+            bool write_reqd = false;
+            for (uint16_t i = 0; i < FDS_MAX_PAGES; i++)
+            {
+                if (m_pages[i].page_type == FDS_PAGE_ERASED)
+                {
+                    ret = page_tag_write_data(m_pages[i].p_addr);
+                    m_pages[i].page_type = FDS_PAGE_DATA;
+                    write_reqd           = true;
+                    break;
+                }
+            }
+            if (!write_reqd)
+            {
+                flag_set(FDS_FLAG_INITIALIZED);
+                flag_clear(FDS_FLAG_INITIALIZING);
+                return FDS_OP_COMPLETED;
+            }
+        }
+        break;
+
+        case FDS_OP_INIT_ERASE_SWAP:
+            ret = fs_erase(&fs_config, m_swap_page.p_addr, FDS_PHY_PAGES_IN_VPAGE, NULL);
+            // If the swap is going to be discarded then reset its write_offset.
+            m_swap_page.write_offset = FDS_PAGE_TAG_SIZE;
+            p_op->init.step          = FDS_OP_INIT_TAG_SWAP;
+            break;
+
+        case FDS_OP_INIT_PROMOTE_SWAP:
+        {
+            // When promoting the swap, keep the write_offset set by pages_init().
+            ret = page_tag_write_data(m_swap_page.p_addr);
+
+            uint16_t const         gc         = m_gc.cur_page;
+            uint32_t const * const p_old_swap = m_swap_page.p_addr;
+
+            // Execute the swap.
+            m_swap_page.p_addr = m_pages[gc].p_addr;
+            m_pages[gc].p_addr = p_old_swap;
+
+            // Copy the offset from the swap to the new page.
+            m_pages[gc].write_offset = m_swap_page.write_offset;
+            m_swap_page.write_offset = FDS_PAGE_TAG_SIZE;
+
+            m_pages[gc].page_type = FDS_PAGE_DATA;
+            p_op->init.step       = FDS_OP_INIT_TAG_SWAP;
+        }
+        break;
+
+        default:
+            // Should not happen.
+            break;
+    }
+
+    if (ret != FDS_SUCCESS)
+    {
+        // fstorage queue was full.
+        flag_clear(FDS_FLAG_INITIALIZING);
+        return FDS_ERR_BUSY;
+    }
+
+    return FDS_OP_EXECUTING;
+}
+
+
+// Executes write and update operations.
+static ret_code_t write_execute(uint32_t prev_ret, fds_op_t * const p_op)
+{
+    ret_code_t         ret;
+    uint32_t   *       p_write_addr;
+    fds_page_t * const p_page = &m_pages[p_op->write.page];
+
+    // This must persist across calls.
+    static fds_record_desc_t desc = {0};
+    // When a record is updated, this variable will hold the page where the old
+    // copy was stored. This will be used to set the can_gc flag when the header is
+    // invalidated (FDS_OP_WRITE_FLAG_DIRTY).
+    static uint16_t page;
+
+    if (prev_ret != FS_SUCCESS)
+    {
+        // The previous operation has timed out, update offsets.
+        page_offsets_update(p_page, p_op->write.header.tl.length_words);
+        return FDS_ERR_OPERATION_TIMEOUT;
+    }
+
+    // Compute the address where to write data.
+    p_write_addr = (uint32_t*)(p_page->p_addr + p_page->write_offset);
+
+    // Execute the current step of the operation, and set one to be executed next.
+    switch (p_op->write.step)
+    {
+        case FDS_OP_WRITE_FIND_RECORD:
+        {
+            // The first step of updating a record constists of locating the copy to be deleted.
+            // If the old copy couldn't be found for any reason then the update should fail.
+            // This prevents duplicates when queuing multiple updates of the same record.
+            desc.p_record  = NULL;
+            desc.record_id = p_op->write.record_to_delete;
+
+            if (!record_find_by_desc(&desc, &page))
+            {
+                return FDS_ERR_NOT_FOUND;
+            }
+            // Setting the step is redundant since we are falling through.
+        }
+        // Fallthrough to FDS_OP_WRITE_HEADER_BEGIN.
+
+        case FDS_OP_WRITE_HEADER_BEGIN:
+            ret = record_header_write_begin(p_op, p_write_addr);
+            break;
+
+        case FDS_OP_WRITE_RECORD_ID:
+            ret = record_header_write_id(p_op, p_write_addr);
+            break;
+
+        case FDS_OP_WRITE_CHUNKS:
+            ret = record_write_chunk(p_op, p_write_addr);
+            break;
+
+        case FDS_OP_WRITE_HEADER_FINALIZE:
+            ret = record_header_write_finalize(p_op, p_write_addr);
+            break;
+
+        case FDS_OP_WRITE_FLAG_DIRTY:
+            ret = record_header_flag_dirty((uint32_t*)desc.p_record, page);
+            p_op->write.step = FDS_OP_WRITE_DONE;
+            break;
+
+        case FDS_OP_WRITE_DONE:
+            ret = FDS_OP_COMPLETED;
+
+#if defined(FDS_CRC_ENABLED)
+            if (flag_is_set(FDS_FLAG_VERIFY_CRC))
+            {
+                if (!crc_verify_success(p_op->write.header.ic.crc16,
+                                        p_op->write.header.tl.length_words,
+                                        p_write_addr))
+                {
+                    ret = FDS_ERR_CRC_CHECK_FAILED;
+                }
+            }
+#endif
+            break;
+
+        default:
+            ret = FDS_ERR_INTERNAL;
+            break;
+    }
+
+    // An operation has either completed or failed. It may have failed because fstorage
+    // ran out of memory, or because the user tried to delete a record which did not exist.
+    if (ret != FDS_OP_EXECUTING)
+    {
+        // There won't be another callback for this operation, so update the page offset now.
+        page_offsets_update(p_page, p_op->write.header.tl.length_words);
+    }
+
+    return ret;
+}
+
+
+static ret_code_t delete_execute(uint32_t prev_ret, fds_op_t * const p_op)
+{
+    ret_code_t ret;
+
+    if (prev_ret != FS_SUCCESS)
+    {
+        return FDS_ERR_OPERATION_TIMEOUT;
+    }
+
+    switch (p_op->del.step)
+    {
+        case FDS_OP_DEL_RECORD_FLAG_DIRTY:
+            ret = record_find_and_delete(p_op);
+            p_op->del.step = FDS_OP_DEL_DONE;
+            break;
+
+        case FDS_OP_DEL_FILE_FLAG_DIRTY:
+            ret = file_find_and_delete(p_op);
+            if (ret == FDS_ERR_NOT_FOUND)
+            {
+                // No more records could be found.
+                // There won't be another callback for this operation, so return now.
+                ret = FDS_OP_COMPLETED;
+            }
+            break;
+
+        case FDS_OP_DEL_DONE:
+            ret = FDS_OP_COMPLETED;
+            break;
+
+        default:
+            ret = FDS_ERR_INTERNAL;
+            break;
+    }
+
+    return ret;
+}
+
+
+static ret_code_t gc_execute(uint32_t prev_ret)
+{
+    ret_code_t ret;
+
+    if (prev_ret != FS_SUCCESS)
+    {
+        return FDS_ERR_OPERATION_TIMEOUT;
+    }
+
+    if (m_gc.resume)
+    {
+        m_gc.resume = false;
+    }
+    else
+    {
+        gc_state_advance();
+    }
+
+    switch (m_gc.state)
+    {
+        case GC_NEXT_PAGE:
+            ret = gc_next_page();
+            break;
+
+        case GC_FIND_NEXT_RECORD:
+            ret = gc_record_find_next();
+            break;
+
+        case GC_COPY_RECORD:
+            ret = gc_record_copy();
+            break;
+
+        case GC_ERASE_PAGE:
+            ret = gc_page_erase();
+            break;
+
+        case GC_PROMOTE_SWAP:
+            ret = gc_swap_promote();
+            break;
+
+        case GC_TAG_NEW_SWAP:
+            ret = gc_tag_new_swap();
+            break;
+
+        default:
+            // Should not happen.
+            ret = FDS_ERR_INTERNAL;
+            break;
+    }
+
+    // Either FDS_OP_EXECUTING, FDS_OP_COMPLETED, FDS_ERR_BUSY or FDS_ERR_INTERNAL.
+    return ret;
+}
+
+
+static void queue_process(fs_ret_t result)
+{
+    ret_code_t         ret;
+    fds_op_t   * const p_op = &m_op_queue.op[m_op_queue.rp];
+
+    switch (p_op->op_code)
+    {
+        case FDS_OP_INIT:
+            ret = init_execute(result, p_op);
+            break;
+
+        case FDS_OP_WRITE:
+        case FDS_OP_UPDATE:
+            ret = write_execute(result, p_op);
+            break;
+
+        case FDS_OP_DEL_RECORD:
+        case FDS_OP_DEL_FILE:
+            ret = delete_execute(result, p_op);
+            break;
+
+        case FDS_OP_GC:
+            ret = gc_execute(result);
+            break;
+
+        default:
+            ret = FDS_ERR_INTERNAL;
+            break;
+    }
+
+    if (ret != FDS_OP_EXECUTING)
+    {
+        fds_evt_t evt;
+
+        if (ret == FDS_OP_COMPLETED)
+        {
+            evt.result = FDS_SUCCESS;
+        }
+        else
+        {
+            // Either FDS_ERR_BUSY, FDS_ERR_OPERATION_TIMEOUT,
+            // FDS_ERR_CRC_CHECK_FAILED or FDS_ERR_NOT_FOUND.
+            evt.result = ret;
+
+            // If this operation had any chunks in the queue, skip them.
+            chunk_queue_skip(p_op);
+        }
+
+        event_prepare(p_op, &evt);
+        event_send(&evt);
+
+        // Advance the queue, and if there are any queued operations, process them.
+        if (queue_advance())
+        {
+            queue_process(FS_SUCCESS);
+        }
+        else
+        {
+            // No more elements in the queue. Clear the FDS_FLAG_PROCESSING flag,
+            // so that new operation can start processing the queue.
+            flag_clear(FDS_FLAG_PROCESSING);
+        }
+    }
+}
+
+
+static void queue_start(void)
+{
+    if (!flag_is_set(FDS_FLAG_PROCESSING))
+    {
+        flag_set(FDS_FLAG_PROCESSING);
+        queue_process(FS_SUCCESS);
+    }
+}
+
+
+static void fs_event_handler(fs_evt_t const * const p_evt, fs_ret_t result)
+{
+    queue_process(result);
+}
+
+
+// Enqueues write and update operations.
+static ret_code_t write_enqueue(fds_record_desc_t         * const p_desc,
+                                fds_record_t        const * const p_record,
+                                fds_reserve_token_t const * const p_tok,
+                                fds_op_code_t                     op_code)
+{
+    ret_code_t ret;
+    fds_op_t   op;
+    uint16_t   page;
+    uint16_t   crc          = 0;
+    uint16_t   length_words = 0;
+
+    if (!flag_is_set(FDS_FLAG_INITIALIZED))
+    {
+        return FDS_ERR_NOT_INITIALIZED;
+    }
+
+    if (p_record == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    if ((p_record->file_id == FDS_FILE_ID_INVALID) ||
+        (p_record->key     == FDS_RECORD_KEY_DIRTY))
+    {
+        return FDS_ERR_INVALID_ARG;
+    }
+
+    if (!chunk_is_aligned(p_record->data.p_chunks,
+                          p_record->data.num_chunks))
+    {
+        return FDS_ERR_UNALIGNED_ADDR;
+    }
+
+    // No space was previously reserved for this operation.
+    if (p_tok == NULL)
+    {
+        // Compute the total length of the record.
+        for (uint32_t i = 0; i < p_record->data.num_chunks; i++)
+        {
+            length_words += p_record->data.p_chunks[i].length_words;
+        }
+
+        // Find a page where to write data.
+        ret = write_space_reserve(length_words, &page);
+
+        if (ret != FDS_SUCCESS)
+        {
+            // There is either not enough flash space available (FDS_ERR_NO_SPACE_IN_FLASH) or
+            // the record exceeds the virtual page size (FDS_ERR_RECORD_TOO_LARGE).
+            return ret;
+        }
+    }
+    else
+    {
+        page         = p_tok->page;
+        length_words = p_tok->length_words;
+    }
+
+    // Initialize the operation.
+    op.op_code                      = op_code;
+    op.write.step                   = FDS_OP_WRITE_HEADER_BEGIN;
+    op.write.page                   = page;
+    op.write.chunk_count            = p_record->data.num_chunks;
+    op.write.chunk_offset           = FDS_OFFSET_DATA;
+    op.write.header.record_id       = record_id_new();
+    op.write.header.ic.file_id      = p_record->file_id;
+    op.write.header.tl.record_key   = p_record->key;
+    op.write.header.tl.length_words = length_words;
+
+    if (op_code == FDS_OP_UPDATE)
+    {
+        op.write.step             = FDS_OP_WRITE_FIND_RECORD;
+        // Save the record ID of the record to be updated.
+        op.write.record_to_delete = p_desc->record_id;
+    }
+
+#if defined (FDS_CRC_ENABLED)
+    // First, compute the CRC for the first 6 bytes of the header which contain the
+    // record key, length and file ID, then, compute the CRC of the record ID (4 bytes).
+    crc = crc16_compute((uint8_t*)&op.write.header,           6, NULL);
+    crc = crc16_compute((uint8_t*)&op.write.header.record_id, 4, &crc);
+
+    for (uint32_t i = 0; i < p_record->data.num_chunks; i++)
+    {
+        // Compute the CRC for the record data.
+        crc = crc16_compute((uint8_t*)p_record->data.p_chunks[i].p_data,
+                            p_record->data.p_chunks[i].length_words * sizeof(uint32_t), &crc);
+    }
+#endif
+
+    op.write.header.ic.crc16 = crc;
+
+    // Attempt to enqueue the operation.
+    if (!op_enqueue(&op, p_record->data.num_chunks, p_record->data.p_chunks))
+    {
+        // No space availble in the queues. Cancel the reservation of flash space.
+        CRITICAL_SECTION_ENTER();
+        write_space_free(length_words, page);
+        CRITICAL_SECTION_EXIT();
+
+        return FDS_ERR_NO_SPACE_IN_QUEUES;
+    }
+
+     // Initialize the record descriptor, if provided.
+    if (p_desc != NULL)
+    {
+        p_desc->p_record       = NULL;
+        // Don't invoke record_id_new() again !
+        p_desc->record_id      = op.write.header.record_id;
+        p_desc->record_is_open = false;
+        p_desc->gc_run_count   = m_gc.run_count;
+    }
+
+    // Start processing the queue, if necessary.
+    queue_start();
+
+    return FDS_SUCCESS;
+}
+
+
+ret_code_t fds_register(fds_cb_t cb)
+{
+    ret_code_t ret;
+
+    CRITICAL_SECTION_ENTER();
+    if (m_users == FDS_MAX_USERS)
+    {
+        ret = FDS_ERR_USER_LIMIT_REACHED;
+    }
+    else
+    {
+        m_cb_table[m_users] = cb;
+        m_users++;
+
+        ret = FDS_SUCCESS;
+    }
+    CRITICAL_SECTION_EXIT();
+
+    return ret;
+}
+
+
+ret_code_t fds_init(void)
+{
+    fds_evt_t const evt_success = { .id = FDS_EVT_INIT, .result = FDS_SUCCESS };
+
+    // No initialization is necessary. Notify the application immediately.
+    if (flag_is_set(FDS_FLAG_INITIALIZED))
+    {
+        event_send(&evt_success);
+        return FDS_SUCCESS;
+    }
+
+    if (flag_is_set(FDS_FLAG_INITIALIZING))
+    {
+        return FDS_SUCCESS;
+    }
+
+    flag_set(FDS_FLAG_INITIALIZING);
+
+    (void)fs_init();
+
+    // Initialize the page structure (m_pages), and determine which
+    // initialization steps are required given the current state of the filesystem.
+    fds_init_opts_t init_opts = pages_init();
+
+    if (init_opts == NO_PAGES)
+    {
+        return FDS_ERR_NO_PAGES;
+    }
+
+    if (init_opts == ALREADY_INSTALLED)
+    {
+        // No initialization is necessary. Notify the application immediately.
+        flag_set(FDS_FLAG_INITIALIZED);
+        flag_clear(FDS_FLAG_INITIALIZING);
+
+        event_send(&evt_success);
+        return FDS_SUCCESS;
+    }
+
+    fds_op_t op;
+    op.op_code = FDS_OP_INIT;
+
+    switch (init_opts)
+    {
+        case FRESH_INSTALL:
+        case TAG_SWAP:
+            op.init.step = FDS_OP_INIT_TAG_SWAP;
+            break;
+
+        case PROMOTE_SWAP:
+        case PROMOTE_SWAP_INST:
+            op.init.step = FDS_OP_INIT_PROMOTE_SWAP;
+            break;
+
+        case DISCARD_SWAP:
+            op.init.step = FDS_OP_INIT_ERASE_SWAP;
+            break;
+
+        case TAG_DATA:
+        case TAG_DATA_INST:
+            op.init.step = FDS_OP_INIT_TAG_DATA;
+            break;
+
+        default:
+            // Should not happen.
+            break;
+    }
+
+    // This cannot fail since it will be the first operation in the queue.
+    (void)op_enqueue(&op, 0, NULL);
+
+    queue_start();
+
+    return FDS_SUCCESS;
+}
+
+
+ret_code_t fds_record_open(fds_record_desc_t  * const p_desc,
+                           fds_flash_record_t * const p_flash_rec)
+{
+    uint16_t page;
+
+    if ((p_desc == NULL) || (p_flash_rec == NULL))
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    // Find the record if necessary.
+    if (record_find_by_desc(p_desc, &page))
+    {
+        fds_header_t const * const p_header = (fds_header_t*)p_desc->p_record;
+
+#if defined(FDS_CRC_ENABLED)
+        if (!crc_verify_success(p_header->ic.crc16,
+                                p_header->tl.length_words,
+                                p_desc->p_record))
+        {
+            return FDS_ERR_CRC_CHECK_FAILED;
+        }
+#endif
+
+        CRITICAL_SECTION_ENTER();
+        m_pages[page].records_open++;
+        CRITICAL_SECTION_EXIT();
+
+        // Initialize p_flash_rec.
+        p_flash_rec->p_header = p_header;
+        p_flash_rec->p_data   = (p_desc->p_record + FDS_HEADER_SIZE);
+
+        // Set the record as open in the descriptor.
+        p_desc->record_is_open = true;
+
+        return FDS_SUCCESS;
+    }
+
+    // The record could not be found.
+    // It either never existed or it has been deleted.
+    return FDS_ERR_NOT_FOUND;
+}
+
+
+ret_code_t fds_record_close(fds_record_desc_t * const p_desc)
+{
+    ret_code_t ret;
+    uint16_t   page;
+
+    if (p_desc == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    if (record_find_by_desc((fds_record_desc_t*)p_desc, &page))
+    {
+        CRITICAL_SECTION_ENTER();
+        if ((m_pages[page].records_open > 0) && (p_desc->record_is_open))
+        {
+
+            m_pages[page].records_open--;
+            p_desc->record_is_open = false;
+
+            ret = FDS_SUCCESS;
+        }
+        else
+        {
+            ret = FDS_ERR_NO_OPEN_RECORDS;
+        }
+        CRITICAL_SECTION_EXIT();
+    }
+    else
+    {
+        ret = FDS_ERR_NOT_FOUND;
+    }
+
+    return ret;
+}
+
+
+ret_code_t fds_reserve(fds_reserve_token_t * const p_tok, uint16_t length_words)
+{
+    ret_code_t ret;
+    uint16_t   page;
+
+    if (!flag_is_set(FDS_FLAG_INITIALIZED))
+    {
+        return FDS_ERR_NOT_INITIALIZED;
+    }
+
+    if (p_tok == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    ret = write_space_reserve(length_words, &page);
+
+    if (ret == FDS_SUCCESS)
+    {
+        p_tok->page         = page;
+        p_tok->length_words = length_words;
+    }
+
+    return ret;
+}
+
+
+ret_code_t fds_reserve_cancel(fds_reserve_token_t * const p_tok)
+{
+    ret_code_t ret;
+
+    if (!flag_is_set(FDS_FLAG_INITIALIZED))
+    {
+        return FDS_ERR_NOT_INITIALIZED;
+    }
+
+    if (p_tok == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    if (p_tok->page > FDS_MAX_PAGES)
+    {
+        // The page does not exist. This shouldn't happen.
+        return FDS_ERR_INVALID_ARG;
+    }
+
+    fds_page_t const * const p_page = &m_pages[p_tok->page];
+
+    CRITICAL_SECTION_ENTER();
+    if (p_page->words_reserved - (FDS_HEADER_SIZE + p_tok->length_words) >= 0)
+    {
+        // Free reserved space.
+        write_space_free(p_tok->length_words, p_tok->page);
+
+        // Clean the token.
+        p_tok->page         = 0;
+        p_tok->length_words = 0;
+        ret = FDS_SUCCESS;
+    }
+    else
+    {
+        // We are trying to cancel a reservation of more words than how many are
+        // currently reserved on the page. Clearly, this shouldn't happen.
+        ret = FDS_ERR_INVALID_ARG;
+    }
+    CRITICAL_SECTION_EXIT();
+
+    return ret;
+}
+
+
+ret_code_t fds_record_write(fds_record_desc_t       * const p_desc,
+                            fds_record_t      const * const p_record)
+{
+    return write_enqueue(p_desc, p_record, NULL, FDS_OP_WRITE);
+}
+
+
+ret_code_t fds_record_write_reserved(fds_record_desc_t         * const p_desc,
+                                     fds_record_t        const * const p_record,
+                                     fds_reserve_token_t const * const p_tok)
+{
+    // A NULL token is not allowed when writing to a reserved space.
+    if (p_tok == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    return write_enqueue(p_desc, p_record, p_tok, FDS_OP_WRITE);
+}
+
+
+ret_code_t fds_record_update(fds_record_desc_t       * const p_desc,
+                             fds_record_t      const * const p_record)
+{
+    // A NULL descriptor is not allowed when updating a record.
+    if (p_desc == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    return write_enqueue(p_desc, p_record, NULL, FDS_OP_UPDATE);
+}
+
+
+ret_code_t fds_record_delete(fds_record_desc_t * const p_desc)
+{
+    fds_op_t op;
+
+    if (!flag_is_set(FDS_FLAG_INITIALIZED))
+    {
+        return FDS_ERR_NOT_INITIALIZED;
+    }
+
+    if (p_desc == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    op.op_code              = FDS_OP_DEL_RECORD;
+    op.del.step             = FDS_OP_DEL_RECORD_FLAG_DIRTY;
+    op.del.record_to_delete = p_desc->record_id;
+
+    if (op_enqueue(&op, 0, NULL))
+    {
+        queue_start();
+        return FDS_SUCCESS;
+    }
+
+   return FDS_ERR_NO_SPACE_IN_QUEUES;
+}
+
+
+ret_code_t fds_file_delete(uint16_t file_id)
+{
+    fds_op_t op;
+
+    if (!flag_is_set(FDS_FLAG_INITIALIZED))
+    {
+        return FDS_ERR_NOT_INITIALIZED;
+    }
+
+    if (file_id == FDS_FILE_ID_INVALID)
+    {
+        return FDS_ERR_INVALID_ARG;
+    }
+
+    op.op_code      = FDS_OP_DEL_FILE;
+    op.del.step     = FDS_OP_DEL_FILE_FLAG_DIRTY;
+    op.del.file_id  = file_id;
+
+    if (op_enqueue(&op, 0, NULL))
+    {
+        queue_start();
+        return FDS_SUCCESS;
+    }
+
+    return FDS_ERR_NO_SPACE_IN_QUEUES;
+}
+
+
+ret_code_t fds_gc(void)
+{
+    fds_op_t op;
+
+    if (!flag_is_set(FDS_FLAG_INITIALIZED))
+    {
+        return FDS_ERR_NOT_INITIALIZED;
+    }
+
+    op.op_code = FDS_OP_GC;
+
+    if (op_enqueue(&op, 0, NULL))
+    {
+        if (m_gc.state != GC_BEGIN)
+        {
+            // Resume GC by retrying the last step.
+            m_gc.resume = true;
+        }
+
+        queue_start();
+        return FDS_SUCCESS;
+    }
+
+    return FDS_ERR_NO_SPACE_IN_QUEUES;
+}
+
+
+ret_code_t fds_record_iterate(fds_record_desc_t * const p_desc,
+                              fds_find_token_t  * const p_token)
+{
+    return record_find(NULL, NULL, p_desc, p_token);
+}
+
+
+ret_code_t fds_record_find(uint16_t                  file_id,
+                           uint16_t                  record_key,
+                           fds_record_desc_t * const p_desc,
+                           fds_find_token_t  * const p_token)
+{
+    return record_find(&file_id, &record_key, p_desc, p_token);
+}
+
+
+ret_code_t fds_record_find_by_key(uint16_t                  record_key,
+                                  fds_record_desc_t * const p_desc,
+                                  fds_find_token_t  * const p_token)
+{
+    return record_find(NULL, &record_key, p_desc, p_token);
+}
+
+
+ret_code_t fds_record_find_in_file(uint16_t                  file_id,
+                                   fds_record_desc_t * const p_desc,
+                                   fds_find_token_t  * const p_token)
+{
+    return record_find(&file_id, NULL, p_desc, p_token);
+}
+
+
+ret_code_t fds_descriptor_from_rec_id(fds_record_desc_t * const p_desc,
+                                      uint32_t                  record_id)
+{
+    if (p_desc == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    // Zero the descriptor and set the record_id field.
+    memset(p_desc, 0x00, sizeof(fds_record_desc_t));
+    p_desc->record_id = record_id;
+
+    return FDS_SUCCESS;
+}
+
+
+ret_code_t fds_record_id_from_desc(fds_record_desc_t const * const p_desc,
+                                   uint32_t                * const p_record_id)
+{
+    if ((p_desc == NULL) || (p_record_id == NULL))
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    *p_record_id = p_desc->record_id;
+
+    return FDS_SUCCESS;
+}
+
+
+ret_code_t fds_stat(fds_stat_t * const p_stat)
+{
+    uint16_t const words_in_page = FDS_PAGE_SIZE;
+    // The largest number of free contiguous words on any page.
+    uint16_t       contig_words  = 0;
+
+    if (!flag_is_set(FDS_FLAG_INITIALIZED))
+    {
+        return FDS_ERR_NOT_INITIALIZED;
+    }
+
+    if (p_stat == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    memset(p_stat, 0x00, sizeof(fds_stat_t));
+
+    for (uint16_t i = 0; i < FDS_MAX_PAGES; i++)
+    {
+        uint32_t const * p_record   = NULL;
+        uint16_t const   words_used = m_pages[i].write_offset + m_pages[i].words_reserved;
+
+        p_stat->open_records   += m_pages[i].records_open;
+        p_stat->words_reserved += m_pages[i].words_reserved;
+        p_stat->words_used     += words_used;
+        contig_words           =  (words_in_page - words_used);
+
+        if (contig_words > p_stat->largest_contig)
+        {
+            p_stat->largest_contig = contig_words;
+        }
+
+        while (record_find_next(i, &p_record))
+        {
+            p_stat->valid_records++;
+        }
+
+        dirty_records_stat(i, &p_stat->dirty_records, &p_stat->freeable_words);
+    }
+
+    return FDS_SUCCESS;
+}
+
+
+#if defined(FDS_CRC_ENABLED)
+
+ret_code_t fds_verify_crc_on_writes(bool enable)
+{
+    if (enable)
+    {
+        flag_set(FDS_FLAG_VERIFY_CRC);
+    }
+    else
+    {
+        flag_clear(FDS_FLAG_VERIFY_CRC);
+    }
+
+    return FDS_SUCCESS;
+}
+
+#endif
+#endif //NRF_MODULE_ENABLED(FDS)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fds/fds.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,759 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef FDS_H__
+#define FDS_H__
+
+/**
+ * @defgroup fds Flash Data Storage
+ * @ingroup app_common
+ * @{
+ *
+ * @brief   Flash Data Storage (FDS).
+ *
+ * @details Flash Data Storage is a minimalistic, record-oriented file system for the on-chip
+ *          flash. Files are stored as a collection of  records of variable length. FDS supports
+ *          synchronous read operations and asynchronous write operations (write, update,
+ *          and delete). FDS can be used from multiple threads.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "sdk_errors.h"
+#include "app_util_platform.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**@brief   Invalid file ID.
+ *
+ * This value must not be used as a file ID by the application.
+ */
+#define FDS_FILE_ID_INVALID     (0xFFFF)
+
+
+/**@brief   Record key for deleted records.
+ *
+ * This key is used to flag a record as "dirty", which means that it should be removed during
+ * the next garbage collection. This value must not be used as a record key by the application.
+ */
+#define FDS_RECORD_KEY_DIRTY    (0x0000)
+
+
+/**@brief   FDS return values.
+ */
+enum
+{
+    FDS_SUCCESS = NRF_SUCCESS,  //!< The operation completed successfully.
+    FDS_ERR_OPERATION_TIMEOUT,  //!< Error. The operation timed out.
+    FDS_ERR_NOT_INITIALIZED,    //!< Error. The module has not been initialized.
+    FDS_ERR_UNALIGNED_ADDR,     //!< Error. The input data is not aligned to a word boundary.
+    FDS_ERR_INVALID_ARG,        //!< Error. The parameter contains invalid data.
+    FDS_ERR_NULL_ARG,           //!< Error. The parameter is NULL.
+    FDS_ERR_NO_OPEN_RECORDS,    //!< Error. The record is not open, so it cannot be closed.
+    FDS_ERR_NO_SPACE_IN_FLASH,  //!< Error. There is no space in flash memory.
+    FDS_ERR_NO_SPACE_IN_QUEUES, //!< Error. There is no space in the internal queues.
+    FDS_ERR_RECORD_TOO_LARGE,   //!< Error. The record exceeds the maximum allowed size.
+    FDS_ERR_NOT_FOUND,          //!< Error. The record was not found.
+    FDS_ERR_NO_PAGES,           //!< Error. No flash pages are available.
+    FDS_ERR_USER_LIMIT_REACHED, //!< Error. The maximum number of users has been reached.
+    FDS_ERR_CRC_CHECK_FAILED,   //!< Error. The CRC check failed.
+    FDS_ERR_BUSY,               //!< Error. The underlying flash subsystem was busy.
+    FDS_ERR_INTERNAL,           //!< Error. An internal error occurred.
+};
+
+
+/**@brief   Part of the record metadata.
+ *
+ * Contains the record key and the length of the record data.
+ */
+typedef struct
+{
+    uint16_t record_key;    //!< The record key (must be in the range 0x0001 - 0xBFFF).
+    uint16_t length_words;  //!< The length of the record data (in 4-byte words).
+} fds_tl_t;
+
+
+/**@brief   Part of the record metadata.
+ *
+ * Contains the ID of the file that the record belongs to and the CRC16 check value of the record.
+ */
+typedef struct
+{
+    uint16_t file_id;   //!< The ID of the file that the record belongs to.
+
+    /**@brief   CRC16 check value.
+     *
+     * The CRC is calculated over the entire record as stored in flash (including the record
+     * metadata except the CRC field itself). The CRC standard employed is CRC-16-CCITT.
+     */
+    uint16_t crc16;
+} fds_ic_t;
+
+
+/**@brief   The record metadata as stored in flash.
+ */
+typedef struct
+{
+    fds_tl_t tl;        //!< See @ref fds_tl_t.
+    fds_ic_t ic;        //!< See @ref fds_ic_t.
+    uint32_t record_id; //!< The unique record ID (32 bits).
+} fds_header_t;
+
+
+/**@brief   The record descriptor structure that is used to manipulate records.
+ *
+ * This structure is used by the FDS module. You must provide the descriptor to the module when
+ * you manipulate existing records. However, you should never modify it or use any of its fields.
+ *
+ * @note Never reuse the same descriptor for different records.
+ */
+typedef struct
+{
+    uint32_t         record_id;         //!< The unique record ID.
+    uint32_t const * p_record;          //!< The last known location of the record in flash.
+    uint16_t         gc_run_count;      //!< Number of times garbage collection has been run.
+    bool             record_is_open;    //!< Whether the record is currently open.
+} fds_record_desc_t;
+
+
+/**@brief   Structure that can be used to read the contents of a record stored in flash.
+ *
+ * This structure does not reflect the physical layout of a record in flash, but it points
+ * to the locations where the record header (metadata) and the record data are stored.
+ */
+typedef struct
+{
+    fds_header_t const * p_header;  //!< Location of the record header in flash.
+    void         const * p_data;    //!< Location of the record data in flash.
+} fds_flash_record_t;
+
+
+/**@brief   A chunk of record data to be written to flash.
+ *
+ * @p p_data must be aligned to a word boundary. Make sure to keep it in
+ * memory until the operation has completed, which is indicated by the respective FDS event.
+ */
+typedef struct
+{
+    void     const * p_data;        //!< Pointer to the data to store. Must be word-aligned.
+    uint16_t         length_words;  //!< Length of data pointed to by @p p_data (in 4-byte words).
+} fds_record_chunk_t;
+
+
+/**@brief   A record to be written to flash.
+ */
+typedef struct
+{
+    uint16_t file_id;                           //!< The ID of the file that the record belongs to.
+    uint16_t key;                               //!< The record key.
+    struct
+    {
+        fds_record_chunk_t const * p_chunks;    //!< The chunks that make up the record data.
+        uint16_t                   num_chunks;  //!< The number of chunks that make up the data.
+    } data;
+} fds_record_t;
+
+
+/**@brief   A token to a reserved space in flash, created by @ref fds_reserve.
+ *
+ * This token can be used to write the record in the reserved space (@ref fds_record_write_reserved)
+ * or to cancel the reservation (@ref fds_reserve_cancel).
+ */
+typedef struct
+{
+    uint16_t page;           //!< The logical ID of the page where space was reserved.
+    uint16_t length_words;   //!< The amount of space reserved (in 4-byte words).
+} fds_reserve_token_t;
+
+
+/**@brief   A token to keep information about the progress of @ref fds_record_find,
+ *          @ref fds_record_find_by_key, and @ref fds_record_find_in_file.
+ *
+ * @note    Always zero-initialize the token before using it for the first time.
+ * @note    Never reuse the same token to search for different records.
+ */
+typedef struct
+{
+    uint32_t const * p_addr;
+    uint16_t         page;
+} fds_find_token_t;
+
+
+/**@brief   FDS event IDs.
+ */
+typedef enum
+{
+    FDS_EVT_INIT,       //!< Event for @ref fds_init.
+    FDS_EVT_WRITE,      //!< Event for @ref fds_record_write and @ref fds_record_write_reserved.
+    FDS_EVT_UPDATE,     //!< Event for @ref fds_record_update.
+    FDS_EVT_DEL_RECORD, //!< Event for @ref fds_record_delete.
+    FDS_EVT_DEL_FILE,   //!< Event for @ref fds_file_delete.
+    FDS_EVT_GC          //!< Event for @ref fds_gc.
+} fds_evt_id_t;
+
+
+ANON_UNIONS_ENABLE
+
+/**@brief   An FDS event.
+ */
+typedef struct
+{
+    fds_evt_id_t id;        //!< The event ID. See @ref fds_evt_id_t.
+    ret_code_t   result;    //!< The result of the operation related to this event.
+    union
+    {
+        struct
+        {
+            /* Currently not used. */
+            uint16_t pages_not_mounted;
+        } init;
+        struct
+        {
+            uint32_t record_id;
+            uint16_t file_id;
+            uint16_t record_key;
+            bool     is_record_updated;
+        } write; //!< Information for @ref FDS_EVT_WRITE and @ref FDS_EVT_UPDATE events.
+        struct
+        {
+            uint32_t record_id;
+            uint16_t file_id;
+            uint16_t record_key;
+            uint16_t records_deleted_count;
+        } del; //!< Information for @ref FDS_EVT_DEL_RECORD and @ref FDS_EVT_DEL_FILE events.
+        struct
+        {
+            /* Currently not used. */
+            uint16_t pages_skipped;
+            uint16_t space_reclaimed;
+        } gc;
+    };
+} fds_evt_t;
+
+ANON_UNIONS_DISABLE
+
+
+/**@brief   File system statistics. */
+typedef struct
+{
+    uint16_t open_records;      //!< The number of open records.
+    uint16_t valid_records;     //!< The number of valid records.
+    uint16_t dirty_records;     //!< The number of deleted ("dirty") records.
+    uint16_t words_reserved;    //!< The number of words reserved by @ref fds_reserve().
+
+    /**@brief The number of words written to flash, including those reserved for future writes.
+     */
+    uint16_t words_used;
+
+    /**@brief The largest number of free contiguous words in the file system.
+     *
+     * This number determines the largest record that can be stored by FDS.
+     * It takes into account all reservations for future writes.
+     */
+    uint16_t largest_contig;
+
+    /**@brief The largest number of words that can be reclaimed by garbage collection.
+     *
+     * The actual amount of space freed by garbage collection might be less than this value if
+     * records are open while garbage collection is run.
+     */
+    uint16_t freeable_words;
+} fds_stat_t;
+
+
+/**@brief   FDS event handler function prototype.
+ *
+ * @param   p_evt   The event.
+ */
+typedef void (*fds_cb_t)(fds_evt_t const * const p_evt);
+
+
+/**@brief   Function for registering an FDS event handler.
+ *
+ * The maximum amount of handlers that can be registered can be configured by changing the value
+ * of @ref FDS_MAX_USERS in fds_config.h.
+ *
+ * @param[in]   cb  The event handler function.
+ *
+ * @retval  FDS_SUCCESS                 If the event handler was registered successfully.
+ * @retval  FDS_ERR_USER_LIMIT_REACHED  If the maximum number of registered callbacks is reached.
+ */
+ret_code_t fds_register(fds_cb_t cb);
+
+
+/**@brief   Function for initializing the module.
+ *
+ * This function initializes the module and installs the file system (unless it is installed
+ * already).
+ *
+ * This function is asynchronous. Completion is reported through an event. Make sure to call
+ * @ref fds_register before calling @ref fds_init so that you receive the completion event.
+ *
+ * @retval  FDS_SUCCESS         If the operation was queued successfully.
+ * @retval  FDS_ERR_NO_PAGES    If there is no space available in flash memory to install the
+ *                              file system.
+ */
+ret_code_t fds_init(void);
+
+
+/**@brief   Function for writing a record to flash.
+ *
+ * There are no restrictions on the file ID and the record key, except that the record key must be
+ * different from @ref FDS_RECORD_KEY_DIRTY and the file ID must be different from
+ * @ref FDS_FILE_ID_INVALID. In particular, no restrictions are made regarding the uniqueness of
+ * the file ID or the record key. All records with the same file ID are grouped into one file.
+ * If no file with the specified ID exists, it is created. There can be multiple records with the
+ * same record key in a file.
+ *
+ * Some modules need exclusive use of certain file IDs and record keys. See @ref lib_fds_functionality_keys
+ * for details.
+ *
+ * Record data can consist of multiple chunks. The data must be aligned to a 4 byte boundary, and
+ * because it is not buffered internally, it must be kept in memory until the callback for the
+ * operation has been received. The length of the data must not exceed @ref FDS_VIRTUAL_PAGE_SIZE
+ * words minus 14 bytes.
+ *
+ * This function is asynchronous. Completion is reported through an event that is sent to
+ * the registered event handler function.
+ *
+ * @param[out]  p_desc      The descriptor of the record that was written. Pass NULL if you do not
+ *                          need the descriptor.
+ * @param[in]   p_record    The record to be written to flash.
+ *
+ * @retval  FDS_SUCCESS                 If the operation was queued successfully.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG            If @p p_record is NULL.
+ * @retval  FDS_ERR_INVALID_ARG         If the file ID or the record key is invalid.
+ * @retval  FDS_ERR_UNALIGNED_ADDR      If the record data is not aligned to a 4 byte boundary.
+ * @retval  FDS_ERR_RECORD_TOO_LARGE    If the record data exceeds the maximum length.
+ * @retval  FDS_ERR_NO_SPACE_IN_QUEUES  If the operation queue is full or there are more record
+ *                                      chunks than can be buffered.
+ * @retval  FDS_ERR_NO_SPACE_IN_FLASH   If there is not enough free space in flash to store the
+ *                                      record.
+ */
+ret_code_t fds_record_write(fds_record_desc_t       * const p_desc,
+                            fds_record_t      const * const p_record);
+
+
+/**@brief   Function for reserving space in flash.
+ *
+ * This function can be used to reserve space in flash memory. To write a record into the reserved
+ * space, use @ref fds_record_write_reserved. Alternatively, use @ref fds_reserve_cancel to cancel
+ * a reservation.
+ *
+ * Note that this function does not write any data to flash.
+ *
+ * @param[out]  p_token         A token that can be used to write a record in the reserved space or
+ *                              cancel the reservation.
+ * @param[in]   length_words    The length of the record data (in 4-byte words).
+ *
+ * @retval  FDS_SUCCESS                 If the flash space was reserved successfully.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG            If @p p_token is NULL instead of a valid token address.
+ * @retval  FDS_ERR_RECORD_TOO_LARGE    If the record length exceeds the maximum length.
+ * @retval  FDS_ERR_NO_SPACE_IN_FLASH   If there is not enough free space in flash to store the
+ *                                      record.
+ */
+ret_code_t fds_reserve(fds_reserve_token_t * const p_token, uint16_t length_words);
+
+
+/**@brief   Function for canceling an @ref fds_reserve operation.
+ *
+ * @param[in]   p_token     The token that identifies the reservation, produced by @ref fds_reserve.
+ *
+ * @retval  FDS_SUCCESS             If the reservation was canceled.
+ * @retval  FDS_ERR_NOT_INITIALIZED If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG        If @p p_token is NULL instead of a valid token address.
+ * @retval  FDS_ERR_INVALID_ARG     If @p p_token contains invalid data.
+ */
+ret_code_t fds_reserve_cancel(fds_reserve_token_t * const p_token);
+
+
+/**@brief   Function for writing a record to a space in flash that was reserved using
+ *          @ref fds_reserve.
+ *
+ * There are no restrictions on the file ID and the record key, except that the record key must be
+ * different from @ref FDS_RECORD_KEY_DIRTY and the file ID must be different from
+ * @ref FDS_FILE_ID_INVALID. In particular, no restrictions are made regarding the uniqueness of
+ * the file ID or the record key. All records with the same file ID are grouped into one file.
+ * If no file with the specified ID exists, it is created. There can be multiple records with the
+ * same record key in a file.
+ *
+ * Record data can consist of multiple chunks. The data must be aligned to a 4 byte boundary, and
+ * because it is not buffered internally, it must be kept in memory until the callback for the
+ * operation has been received. The length of the data must not exceed @ref FDS_VIRTUAL_PAGE_SIZE
+ * words minus 14 bytes.
+ *
+ * This function is asynchronous. Completion is reported through an event that is sent to the
+ * registered event handler function.
+ *
+ * @note
+ * This function behaves similarly to @ref fds_record_write, with the exception that it never
+ * fails with the error @ref FDS_ERR_NO_SPACE_IN_FLASH.
+ *
+ * @param[out]  p_desc      The descriptor of the record that was written. Pass NULL if you do not
+ *                          need the descriptor.
+ * @param[in]   p_record    The record to be written to flash.
+ * @param[in]   p_token     The token that identifies the space reserved in flash.
+ *
+ * @retval  FDS_SUCCESS                 If the operation was queued successfully.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG            If @p p_token is NULL instead of a valid token address.
+ * @retval  FDS_ERR_INVALID_ARG         If the file ID or the record key is invalid.
+ * @retval  FDS_ERR_UNALIGNED_ADDR      If the record data is not aligned to a 4 byte boundary.
+ * @retval  FDS_ERR_RECORD_TOO_LARGE    If the record data exceeds the maximum length.
+ * @retval  FDS_ERR_NO_SPACE_IN_QUEUES  If the operation queue is full or there are more record
+ *                                      chunks than can be buffered.
+ */
+ret_code_t fds_record_write_reserved(fds_record_desc_t         * const p_desc,
+                                     fds_record_t        const * const p_record,
+                                     fds_reserve_token_t const * const p_token);
+
+
+/**@brief   Function for deleting a record.
+ *
+ * Deleted records cannot be located using @ref fds_record_find, @ref fds_record_find_by_key, or
+ * @ref fds_record_find_in_file. Additionally, they can no longer be opened using
+ * @ref fds_record_open.
+ *
+ * Note that deleting a record does not free the space it occupies in flash memory.
+ * To reclaim flash space used by deleted records, call @ref fds_gc to run garbage collection.
+ *
+ * This function is asynchronous. Completion is reported through an event that is sent to the
+ * registered event handler function.
+ *
+ * @param[in]   p_desc      The descriptor of the record that should be deleted.
+ *
+ * @retval  FDS_SUCCESS                 If the operation was queued successfully.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG            If the specified record descriptor @p p_desc is NULL.
+ * @retval  FDS_ERR_NO_SPACE_IN_QUEUES  If the operation queue is full.
+ */
+ret_code_t fds_record_delete(fds_record_desc_t * const p_desc);
+
+
+/**@brief   Function for deleting all records in a file.
+ *
+ * This function deletes a file, including all its records. Deleted records cannot be located
+ * using @ref fds_record_find, @ref fds_record_find_by_key, or @ref fds_record_find_in_file.
+ * Additionally, they can no longer be opened using @ref fds_record_open.
+ *
+ * Note that deleting records does not free the space they occupy in flash memory.
+ * To reclaim flash space used by deleted records, call @ref fds_gc to run garbage collection.
+ *
+ * This function is asynchronous. Completion is reported through an event that is sent to the
+ * registered event handler function.
+ *
+ * @param[in]   file_id     The ID of the file to be deleted.
+ *
+ * @retval  FDS_SUCCESS                 If the operation was queued successfully.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_INVALID_ARG         If the specified @p file_id is invalid.
+ * @retval  FDS_ERR_NO_SPACE_IN_QUEUES  If the operation queue is full.
+ */
+ret_code_t fds_file_delete(uint16_t file_id);
+
+
+/**@brief   Function for updating a record.
+ *
+ * Updating a record first writes a new record (@p p_record) to flash and then deletes the
+ * old record (identified by @p p_desc).
+ *
+ * There are no restrictions on the file ID and the record key, except that the record key must be
+ * different from @ref FDS_RECORD_KEY_DIRTY and the file ID must be different from
+ * @ref FDS_FILE_ID_INVALID. In particular, no restrictions are made regarding the uniqueness of
+ * the file ID or the record key. All records with the same file ID are grouped into one file.
+ * If no file with the specified ID exists, it is created. There can be multiple records with the
+ * same record key in a file.
+ *
+ * Record data can consist of multiple chunks. The data must be aligned to a 4 byte boundary, and
+ * because it is not buffered internally, it must be kept in memory until the callback for the
+ * operation has been received. The length of the data must not exceed @ref FDS_VIRTUAL_PAGE_SIZE
+ * words minus 14 bytes.
+ *
+ * This function is asynchronous. Completion is reported through an event that is sent to the
+ * registered event handler function.
+ *
+ * @param[in, out]  p_desc      The descriptor of the record to update. When the function
+ *                              returns with FDS_SUCCESS, this parameter contains the
+ *                              descriptor of the newly written record.
+ * @param[in]       p_record    The updated record to be written to flash.
+ *
+ * @retval  FDS_SUCCESS                 If the operation was queued successfully.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_INVALID_ARG         If the file ID or the record key is invalid.
+ * @retval  FDS_ERR_UNALIGNED_ADDR      If the record data is not aligned to a 4 byte boundary.
+ * @retval  FDS_ERR_RECORD_TOO_LARGE    If the record data exceeds the maximum length.
+ * @retval  FDS_ERR_NO_SPACE_IN_QUEUES  If the operation queue is full or there are more record
+ *                                      chunks than can be buffered.
+ * @retval  FDS_ERR_NO_SPACE_IN_FLASH   If there is not enough free space in flash to store the
+ *                                      updated record.
+ */
+ret_code_t fds_record_update(fds_record_desc_t       * const p_desc,
+                             fds_record_t      const * const p_record);
+
+
+/**@brief   Function for iterating through all records in flash.
+ *
+ * To search for the next record, call the function again and supply the same @ref fds_find_token_t
+ * structure to resume searching from the last record that was found.
+ *
+ * Note that the order with which records are iterated is not defined.
+ *
+ * @param[out]  p_desc      The descriptor of the record that was found.
+ * @param[out]  p_token     A token containing information about the progress of the operation.
+ *
+ * @retval  FDS_SUCCESS                 If a record was found.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG            If @p p_desc or @p p_token is NULL.
+ * @retval  FDS_ERR_NOT_FOUND           If no matching record was found.
+ */
+ret_code_t fds_record_iterate(fds_record_desc_t * const p_desc,
+                              fds_find_token_t  * const p_token);
+
+
+/**@brief   Function for searching for records with a given record key in a file.
+ *
+ * This function finds the first record in a file that has the given record key. To search for the
+ * next record with the same key in the file, call the function again and supply the same
+ * @ref fds_find_token_t structure to resume searching from the last record that was found.
+ *
+ * @param[in]   file_id     The file ID.
+ * @param[in]   record_key  The record key.
+ * @param[out]  p_desc      The descriptor of the record that was found.
+ * @param[out]  p_token     A token containing information about the progress of the operation.
+ *
+ * @retval  FDS_SUCCESS                 If a record was found.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG            If @p p_desc or @p p_token is NULL.
+ * @retval  FDS_ERR_NOT_FOUND           If no matching record was found.
+ */
+ret_code_t fds_record_find(uint16_t                  file_id,
+                           uint16_t                  record_key,
+                           fds_record_desc_t * const p_desc,
+                           fds_find_token_t  * const p_token);
+
+
+/**@brief   Function for searching for records with a given record key.
+ *
+ * This function finds the first record with a given record key, independent of the file it
+ * belongs to. To search for the next record with the same key, call the function again and supply
+ * the same @ref fds_find_token_t structure to resume searching from the last record that was found.
+ *
+ * @param[in]   record_key  The record key.
+ * @param[out]  p_desc      The descriptor of the record that was found.
+ * @param[out]  p_token     A token containing information about the progress of the operation.
+ *
+ * @retval  FDS_SUCCESS                 If a record was found.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG            If @p p_desc or @p p_token is NULL.
+ * @retval  FDS_ERR_NOT_FOUND           If no record with the given key was found.
+ */
+ret_code_t fds_record_find_by_key(uint16_t                  record_key,
+                                  fds_record_desc_t * const p_desc,
+                                  fds_find_token_t  * const p_token);
+
+
+/**@brief   Function for searching for any record in a file.
+ *
+ * This function finds the first record in a file, independent of its record key.
+ * To search for the next record in the same file, call the function again and supply the same
+ * @ref fds_find_token_t structure to resume searching from the last record that was found.
+ *
+ * @param[in]   file_id     The file ID.
+ * @param[out]  p_desc      The descriptor of the record that was found.
+ * @param[out]  p_token     A token containing information about the progress of the operation.
+ *
+ * @retval  FDS_SUCCESS                 If a record was found.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG            If @p p_desc or @p p_token is NULL.
+ * @retval  FDS_ERR_NOT_FOUND           If no matching record was found.
+ */
+ret_code_t fds_record_find_in_file(uint16_t                  file_id,
+                                   fds_record_desc_t * const p_desc,
+                                   fds_find_token_t  * const p_token);
+
+
+/**@brief   Function for opening a record for reading.
+ *
+ * This function opens a record that is stored in flash, so that it can be read. The function
+ * initializes an @ref fds_flash_record_t structure, which can be used to access the record data as
+ * well as its associated metadata. The pointers provided in the @ref fds_flash_record_t structure
+ * are pointers to flash memory.
+ *
+ * Opening a record with @ref fds_record_open prevents garbage collection to run on the virtual
+ * flash page in which record is stored, so that the contents of the memory pointed by fields in
+ * @ref fds_flash_record_t are guaranteed to remain unmodified as long as the record is kept open.
+ *
+ * When you are done reading a record, call @ref fds_record_close to close it. Garbage collection
+ * can then reclaim space on the virtual page where the record is stored. Note that you must
+ * provide the same descriptor for @ref fds_record_close as you did for this function.
+ *
+ * @param[in]   p_desc          The descriptor of the record to open.
+ * @param[out]  p_flash_record  The record, as stored in flash.
+ *
+ * @retval  FDS_SUCCESS                 If the record was opened successfully.
+ * @retval  FDS_ERR_NULL_ARG            If @p p_desc or @p p_flash_record is NULL.
+ * @retval  FDS_ERR_NOT_FOUND           If the record was not found. It might have been deleted, or
+ *                                      it might not have been written yet.
+ * @retval  FDS_ERR_CRC_CHECK_FAILED    If the CRC check for the record failed.
+ */
+ret_code_t fds_record_open(fds_record_desc_t  * const p_desc,
+                           fds_flash_record_t * const p_flash_record);
+
+
+/**@brief   Function for closing a record.
+ *
+ * Closing a record allows garbage collection to run on the virtual page in which the record is
+ * stored (if no other records remain open on that page). The descriptor passed as an argument
+ * must be the same as the one used to open the record using @ref fds_record_open.
+ *
+ * Note that closing a record does not invalidate its descriptor. You can still supply the
+ * descriptor to all functions that accept a record descriptor as a parameter.
+ *
+ * @param[in]   p_desc  The descriptor of the record to close.
+ *
+ * @retval  FDS_SUCCESS             If the record was closed successfully.
+ * @retval  FDS_ERR_NULL_ARG        If @p p_desc is NULL.
+ * @retval  FDS_ERR_NO_OPEN_RECORDS If the record is not open.
+ * @retval  FDS_ERR_NOT_FOUND       If the record could not be found.
+ */
+ret_code_t fds_record_close(fds_record_desc_t * const p_desc);
+
+
+/**@brief   Function for running garbage collection.
+ *
+ * Garbage collection reclaims the flash space that is occupied by records that have been deleted,
+ * or that failed to be completely written due to, for example, a power loss.
+ *
+ * This function is asynchronous. Completion is reported through an event that is sent to the
+ * registered event handler function.
+ *
+ * @retval  FDS_SUCCESS                 If the operation was queued successfully.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NO_SPACE_IN_QUEUES  If the operation queue is full.
+ */
+ret_code_t fds_gc(void);
+
+
+/**@brief   Function for obtaining a descriptor from a record ID.
+ *
+ * This function can be used to reconstruct a descriptor from a record ID, like the one that is
+ * passed to the callback function.
+ *
+ * @note
+ * This function does not check whether a record with the given record ID exists.
+ * If a non-existing record ID is supplied, the resulting descriptor is invalid and will cause
+ * other functions to fail when it is supplied as parameter.
+ *
+ * @param[out]  p_desc      The descriptor of the record with the given record ID.
+ * @param[in]   record_id   The record ID for which a descriptor should be returned.
+ *
+ * @retval  FDS_SUCCESS         If a descriptor was returned.
+ * @retval  FDS_ERR_NULL_ARG    If @p p_desc is NULL.
+ */
+ret_code_t fds_descriptor_from_rec_id(fds_record_desc_t * const p_desc,
+                                      uint32_t                  record_id);
+
+
+/**@brief   Function for obtaining a record ID from a record descriptor.
+ *
+ * This function can be used to extract a record ID from a descriptor. For example, you could use
+ * it in the callback function to compare the record ID of an event to the record IDs of the
+ * records for which you have a descriptor.
+ *
+ * @warning
+ * This function does not check whether the record descriptor is valid. If the descriptor is not
+ * initialized or has been tampered with, the resulting record ID might be invalid.
+ *
+ * @param[in]   p_desc          The descriptor from which the record ID should be extracted.
+ * @param[out]  p_record_id     The record ID that is contained in the given descriptor.
+ *
+ * @retval  FDS_SUCCESS         If a record ID was returned.
+ * @retval  FDS_ERR_NULL_ARG    If @p p_desc or @p p_record_id is NULL.
+ */
+ret_code_t fds_record_id_from_desc(fds_record_desc_t const * const p_desc,
+                                   uint32_t                * const p_record_id);
+
+
+/**@brief   Function for retrieving file system statistics.
+ *
+ * This function retrieves file system statistics, such as the number of open records, the space
+ * that can be reclaimed by garbage collection, and others.
+ *
+ * @param[out]  p_stat      File system statistics.
+ *
+ * @retval  FDS_SUCCESS                 If the statistics were returned successfully.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG            If @p p_stat is NULL.
+ */
+ret_code_t fds_stat(fds_stat_t * const p_stat);
+
+
+#if defined(FDS_CRC_ENABLED)
+
+/**@brief   Function for enabling and disabling CRC verification for write operations.
+ *
+ * CRC verification ensures that data that is queued for writing does not change before the write
+ * actually happens. Use this function to enable or disable CRC verification. If verification is
+ * enabled, the error @ref FDS_ERR_CRC_CHECK_FAILED is returned in the event for
+ * @ref fds_record_write, @ref fds_record_write_reserved, or @ref fds_record_update if
+ * verification fails.
+ *
+ * @note
+ * CRC verification is enabled or disabled globally, thus for all users of the FDS module.
+ *
+ * @param[in]   enabled     1 to enable CRC verification. 0 to disable CRC verification.
+ *
+ * @retval  FDS_SUCCESS     If CRC verification was enabled or disabled successfully.
+ */
+ret_code_t fds_verify_crc_on_writes(bool enabled);
+
+#endif
+
+/** @} */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // FDS_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fds/fds_internal_defs.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,339 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef FDS_INTERNAL_DEFS_H__
+#define FDS_INTERNAL_DEFS_H__
+#include "sdk_config.h"
+#include <stdint.h>
+#include <stdbool.h>
+
+#if defined (FDS_THREADS)
+    #include "nrf_soc.h"
+    #include "app_util_platform.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define FDS_PAGE_TAG_SIZE       (2) // Page tag size, in 4-byte words.
+#define FDS_PAGE_TAG_WORD_0     (0) // Offset of the first word in the page tag from the page address.
+#define FDS_PAGE_TAG_WORD_1     (1) // Offset of the second word in the page tag from the page address.
+
+// Page tag constants
+#define FDS_PAGE_TAG_MAGIC      (0xDEADC0DE)
+#define FDS_PAGE_TAG_SWAP       (0xF11E01FF)
+#define FDS_PAGE_TAG_DATA       (0xF11E01FE)
+
+#define FDS_ERASED_WORD         (0xFFFFFFFF)
+
+#define FDS_OFFSET_TL           (0) // Offset of TL from the record base address, in 4-byte words.
+#define FDS_OFFSET_IC           (1) // Offset of IC from the record base address, in 4-byte words.
+#define FDS_OFFSET_ID           (2) // Offset of ID from the record base address, in 4-byte words.
+#define FDS_OFFSET_DATA         (3) // Offset of the data (chunks) from the record base address, in 4-byte words.
+
+#define FDS_HEADER_SIZE_TL      (1) // Size of the TL part of the header, in 4-byte words.
+#define FDS_HEADER_SIZE_IC      (1) // Size of the IC part of the header, in 4-byte words.
+#define FDS_HEADER_SIZE_ID      (1) // Size of the record ID in the header, in 4-byte words.
+#define FDS_HEADER_SIZE         (3) // Size of the whole header, in 4-byte words.
+
+#define FDS_OP_EXECUTING        (FS_SUCCESS)
+#define FDS_OP_COMPLETED        (0x1D1D)
+
+// The size of a physical page, in 4-byte words.
+#if     defined(NRF51)
+    #define FDS_PHY_PAGE_SIZE   (256)
+ #elif (defined(NRF52) || defined(NRF52840_XXAA))
+    #define FDS_PHY_PAGE_SIZE   (1024)
+#endif
+
+// The number of physical pages to be used. This value is configured indirectly.
+#define FDS_PHY_PAGES               ((FDS_VIRTUAL_PAGES * FDS_VIRTUAL_PAGE_SIZE) / FDS_PHY_PAGE_SIZE)
+
+// The size of a virtual page, in number of physical pages.
+#define FDS_PHY_PAGES_IN_VPAGE      (FDS_VIRTUAL_PAGE_SIZE / FDS_PHY_PAGE_SIZE)
+
+// The number of pages available to store data; which is the total minus one (the swap).
+#define FDS_MAX_PAGES               (FDS_VIRTUAL_PAGES - 1)
+
+ // Just a shorter name for the size, in words, of a virtual page.
+#define FDS_PAGE_SIZE               (FDS_VIRTUAL_PAGE_SIZE)
+
+
+#if (FDS_VIRTUAL_PAGE_SIZE % FDS_PHY_PAGE_SIZE != 0)
+    #error "FDS_VIRTUAL_PAGE_SIZE must be a multiple of the size of a physical page."
+#endif
+
+#if (FDS_VIRTUAL_PAGES < 2)
+    #error "FDS requires at least two virtual pages."
+#endif
+
+
+// FDS internal status flags.
+typedef enum
+{
+    FDS_FLAG_INITIALIZING   = (1 << 0),  // The module is initializing.
+    FDS_FLAG_INITIALIZED    = (1 << 1),  // The module is initialized.
+    FDS_FLAG_PROCESSING     = (1 << 2),  // The queue is being processed.
+    FDS_FLAG_VERIFY_CRC     = (1 << 3),  // Verify CRC upon writing a record.
+} fds_flags_t;
+
+
+// Page types.
+typedef enum
+{
+    FDS_PAGE_DATA,      // Page is ready for storage.
+    FDS_PAGE_SWAP,      // Page is reserved for garbage collection.
+    FDS_PAGE_ERASED,    // Page is erased.
+    FDS_PAGE_UNDEFINED, // Undefined page type.
+} fds_page_type_t;
+
+
+typedef struct
+{
+    fds_page_type_t         page_type;      // The page type.
+    uint32_t        const * p_addr;         // The address of the page.
+    uint16_t                write_offset;   // The page write offset, in 4-byte words.
+    uint16_t                words_reserved; // The amount of words reserved by fds_write_reserve().
+    uint16_t                records_open;   // The number of records opened using fds_open().
+    bool                    can_gc;         // Indicates that there are some records that have been deleted.
+} fds_page_t;
+
+
+typedef struct
+{
+    uint32_t const * p_addr;
+    uint16_t         write_offset;
+} fds_swap_page_t;
+
+
+// FDS op-codes.
+typedef enum
+{
+    FDS_OP_NONE,
+    FDS_OP_INIT,        // Initialize the module.
+    FDS_OP_WRITE,       // Write a record to flash.
+    FDS_OP_UPDATE,      // Update a record.
+    FDS_OP_DEL_RECORD,  // Delete a record.
+    FDS_OP_DEL_FILE,    // Delete a file.
+    FDS_OP_GC           // Run garbage collection.
+} fds_op_code_t;
+
+
+typedef enum
+{
+    FDS_OP_INIT_TAG_SWAP,
+    FDS_OP_INIT_TAG_DATA,
+    FDS_OP_INIT_ERASE_SWAP,
+    FDS_OP_INIT_PROMOTE_SWAP,
+} fds_init_step_t;
+
+
+typedef enum
+{
+    FDS_OP_WRITE_HEADER_BEGIN,      // Write the record key and length.
+    FDS_OP_WRITE_HEADER_FINALIZE,   // Write the file ID and CRC.
+    FDS_OP_WRITE_RECORD_ID,         // Write the record ID.
+    FDS_OP_WRITE_CHUNKS,            // Write the record data.
+    FDS_OP_WRITE_FIND_RECORD,
+    FDS_OP_WRITE_FLAG_DIRTY,        // Flag a record as dirty (as part of an update operation).
+    FDS_OP_WRITE_DONE,
+} fds_write_step_t;
+
+
+typedef enum
+{
+    FDS_OP_DEL_RECORD_FLAG_DIRTY,   // Flag a record as dirty.
+    FDS_OP_DEL_FILE_FLAG_DIRTY,     // Flag multiple records as dirty.
+    FDS_OP_DEL_DONE,
+} fds_delete_step_t;
+
+
+#if defined(__CC_ARM)
+    #pragma push
+    #pragma anon_unions
+#elif defined(__ICCARM__)
+    #pragma language=extended
+#elif defined(__GNUC__)
+    // anonymous unions are enabled by default
+#endif
+
+typedef struct
+{
+    fds_op_code_t op_code;                      // The opcode for the operation.
+    union
+    {
+        struct
+        {
+            fds_init_step_t step;               // The current step the operation is at.
+        } init;
+        struct
+        {
+            fds_header_t     header;
+            fds_write_step_t step;              // The current step the operation is at.
+            uint16_t         page;              // The page the flash space for this command was reserved.
+            uint16_t         chunk_offset;      // Offset used for writing record chunks, in 4-byte words.
+            uint8_t          chunk_count;       // Number of chunks to be written.
+            uint32_t         record_to_delete;  // The record to delete in case this is an update.
+        } write;
+        struct
+        {
+            fds_delete_step_t step;
+            uint16_t          file_id;
+            uint16_t          record_key;
+            uint32_t          record_to_delete;
+        } del;
+    };
+} fds_op_t;
+
+#if defined(__CC_ARM)
+    #pragma pop
+#elif defined(__ICCARM__)
+    // leave anonymous unions enabled
+#elif defined(__GNUC__)
+    // anonymous unions are enabled by default
+#endif
+
+
+typedef struct
+{
+    fds_op_t op[FDS_OP_QUEUE_SIZE];    // Queued flash operations.
+    uint32_t rp;                       // The index of the command being executed.
+    uint32_t count;                    // Number of elements in the queue.
+} fds_op_queue_t;
+
+
+typedef struct
+{
+    fds_record_chunk_t chunk[FDS_CHUNK_QUEUE_SIZE];
+    uint32_t           rp;
+    uint32_t           count;
+} fds_chunk_queue_t;
+
+
+enum
+{
+    PAGE_ERASED = 0x1,
+    PAGE_DATA   = 0x2,
+    SWAP_EMPTY  = 0x4,
+    SWAP_DIRTY  = 0x8,
+};
+
+
+typedef enum
+{
+    // This is a fatal error.
+    NO_PAGES,
+
+    // All pages are erased. Perform a fresh installation.
+    FRESH_INSTALL     = (PAGE_ERASED),
+
+    // Swap is missing. Tag an erased page as swap.
+    TAG_SWAP          = (PAGE_ERASED | PAGE_DATA),
+
+    // Swap is empty. Tag all erased pages as data.
+    TAG_DATA         = (PAGE_ERASED | SWAP_EMPTY),
+
+    // Swap is empty. Tag all remaining erased pages as data.
+    TAG_DATA_INST    = (PAGE_ERASED | PAGE_DATA | SWAP_EMPTY),
+
+    // The swap is dirty. This indicates that the device powered off during GC. However, since there
+    // is also an erased page, it is possible to assume that that page had been entirely garbage
+    // collected. Hence, tag the swap as data, one erased page as swap and any remaining pages as data.
+    PROMOTE_SWAP      = (PAGE_ERASED | SWAP_DIRTY),
+
+    // Similar to the above. Tag the swap as data, one erased page as swap, and any remain
+    // pages as data.
+    PROMOTE_SWAP_INST = (PAGE_ERASED | PAGE_DATA | SWAP_DIRTY),
+
+    // The swap is dirty (written) and there are no erased pages. This indicates that the device
+    // was powered off during GC. It is safe to discard (erase) the swap, since data that was
+    // swapped out lies in one of the valid pages.
+    DISCARD_SWAP      = (PAGE_DATA  | SWAP_DIRTY),
+
+    // Do nothing.
+    ALREADY_INSTALLED = (PAGE_DATA  | SWAP_EMPTY),
+
+} fds_init_opts_t;
+
+
+typedef enum
+{
+    GC_BEGIN,               // Begin GC.
+    GC_NEXT_PAGE,           // GC a page.
+    GC_FIND_NEXT_RECORD,    // Find a valid record to copy.
+    GC_COPY_RECORD,         // Copy a valid record to swap.
+    GC_ERASE_PAGE,          // Erase the page being garbage collected.
+    GC_DISCARD_SWAP,        // Erase (discard) the swap page.
+    GC_PROMOTE_SWAP,        // Tag the swap as valid.
+    GC_TAG_NEW_SWAP         // Tag a freshly erased (GCed) page as swap.
+} fds_gc_state_t;
+
+
+// Holds garbage collection status and related data.
+typedef struct
+{
+    fds_gc_state_t   state;                     // The current GC step.
+    uint16_t         cur_page;                  // The current page being garbage collected.
+    uint32_t const * p_record_src;              // The current record being copied to swap.
+    uint16_t         run_count;                 // Total number of times GC was run.
+    bool             do_gc_page[FDS_MAX_PAGES]; // Controls which pages to garbage collect.
+    bool             resume;                    // Whether or not GC should be resumed.
+} fds_gc_data_t;
+
+
+// Macros to enable and disable application interrupts.
+#if defined (FDS_THREADS)
+
+    #define CRITICAL_SECTION_ENTER()    CRITICAL_REGION_ENTER()
+    #define CRITICAL_SECTION_EXIT()     CRITICAL_REGION_EXIT()
+
+#else
+
+    #define CRITICAL_SECTION_ENTER()
+    #define CRITICAL_SECTION_EXIT()
+
+#endif
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // FDS_INTERNAL_DEFS_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fstorage/fstorage.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,559 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(FSTORAGE)
+#include "fstorage.h"
+#include "fstorage_internal_defs.h"
+
+#include <stdint.h>
+#include <string.h>
+#include <stdbool.h>
+#include "nrf_error.h"
+#include "nrf_soc.h"
+
+
+static uint8_t       m_flags;       // fstorage status flags.
+static fs_op_queue_t m_queue;       // Queue of requested operations.
+static uint8_t       m_retry_count; // Number of times the last flash operation was retried.
+
+// Sends events to the application.
+static void send_event(fs_op_t const * const p_op, fs_ret_t result)
+{
+    fs_evt_t evt;
+    memset(&evt, 0x00, sizeof(fs_evt_t));
+
+    switch (p_op->op_code)
+    {
+        case FS_OP_STORE:
+            evt.id                 = FS_EVT_STORE;
+            evt.store.p_data       = p_op->store.p_dest;
+            evt.store.length_words = p_op->store.length_words;
+            break;
+
+        case FS_OP_ERASE:
+            evt.id               = FS_EVT_ERASE;
+            evt.erase.first_page = p_op->erase.page - p_op->erase.pages_erased;
+            evt.erase.last_page  = p_op->erase.page;
+            break;
+
+        default:
+            // Should not happen.
+            break;
+    }
+    evt.p_context = p_op->p_context;
+
+    p_op->p_config->callback(&evt, result);
+}
+
+
+// Checks that a configuration is non-NULL and within section variable bounds.
+static bool check_config(fs_config_t const * const config)
+{
+#ifndef DFU_SUPPORT_SIGNING
+    if ((config != NULL) &&
+        (FS_SECTION_VARS_START_ADDR <= (uint32_t)config) &&
+        (FS_SECTION_VARS_END_ADDR   >  (uint32_t)config))
+    {
+        return true;
+    }
+
+    return false;
+#else
+    return true;
+#endif
+}
+
+
+// Executes a store operation.
+static uint32_t store_execute(fs_op_t const * const p_op)
+{
+    uint16_t chunk_len;
+
+    if ((p_op->store.length_words - p_op->store.offset) < FS_MAX_WRITE_SIZE_WORDS)
+    {
+        chunk_len = p_op->store.length_words - p_op->store.offset;
+    }
+    else
+    {
+        chunk_len = FS_MAX_WRITE_SIZE_WORDS;
+    }
+
+    return sd_flash_write((uint32_t*)p_op->store.p_dest + p_op->store.offset,
+                          (uint32_t*)p_op->store.p_src  + p_op->store.offset,
+                          chunk_len);
+}
+
+
+// Executes an erase operation.
+static uint32_t erase_execute(fs_op_t const * const p_op)
+{
+    return sd_flash_page_erase(p_op->erase.page);
+}
+
+
+// Advances the queue, wrapping around if necessary.
+// If no elements are left in the queue, clears the FS_FLAG_PROCESSING flag.
+static void queue_advance(void)
+{
+    if (--m_queue.count == 0)
+    {
+        m_flags &= ~FS_FLAG_PROCESSING;
+    }
+
+    if (++m_queue.rp == FS_QUEUE_SIZE)
+    {
+        m_queue.rp = 0;
+    }
+}
+
+
+// Processes the current element in the queue. If the queue is empty, does nothing.
+static void queue_process(void)
+{
+    uint32_t         ret;
+    fs_op_t  * const p_op = &m_queue.op[m_queue.rp];
+
+    if (m_queue.count > 0)
+    {
+        switch (p_op->op_code)
+        {
+            case FS_OP_STORE:
+                ret = store_execute(p_op);
+                break;
+
+            case FS_OP_ERASE:
+                ret = erase_execute(p_op);
+                break;
+
+             default:
+                ret = FS_ERR_INTERNAL;
+                break;
+        }
+
+        // There is a pending flash operation which was not initiated by this module.
+        // Stop processing the queue and wait for a system event.
+        if (ret == NRF_ERROR_BUSY)
+        {
+            m_flags &= ~FS_FLAG_PROCESSING;
+            m_flags |= FS_FLAG_FLASH_REQ_PENDING;
+        }
+        else if (ret != NRF_SUCCESS)
+        {
+            // An error has occurred.
+            send_event(p_op, FS_ERR_INTERNAL);
+        }
+        else
+        {
+            // Operation is executing.
+        }
+    }
+}
+
+
+// Starts processing the queue if there are no pending flash operations, both inside and
+// outside this module. Returns immediately otherwise.
+static void queue_start(void)
+{
+    if (!(m_flags & FS_FLAG_PROCESSING) &&
+        !(m_flags & FS_FLAG_FLASH_REQ_PENDING))
+    {
+        m_flags |= FS_FLAG_PROCESSING;
+        queue_process();
+    }
+}
+
+
+// Flash operation success callback handler. Keeps track of the progress of an operation.
+// If it has finished, advances the queue and notifies the application.
+static void on_operation_success(fs_op_t * const p_op)
+{
+    m_retry_count = 0;
+
+    switch (p_op->op_code)
+    {
+        case FS_OP_STORE:
+        {
+            uint16_t chunk_len;
+
+            if ((p_op->store.length_words - p_op->store.offset) < FS_MAX_WRITE_SIZE_WORDS)
+            {
+                chunk_len = p_op->store.length_words - p_op->store.offset;
+            }
+            else
+            {
+                chunk_len = FS_MAX_WRITE_SIZE_WORDS;
+            }
+
+            p_op->store.offset += chunk_len;
+
+            if (p_op->store.offset == p_op->store.length_words)
+            {
+                // The operation has finished.
+                send_event(p_op, FS_SUCCESS);
+                queue_advance();
+            }
+        }
+        break;
+
+        case FS_OP_ERASE:
+        {
+            p_op->erase.page++;
+            p_op->erase.pages_erased++;
+
+            if (p_op->erase.pages_erased == p_op->erase.pages_to_erase)
+            {
+                send_event(p_op, FS_SUCCESS);
+                queue_advance();
+            }
+        }
+        break;
+
+        default:
+            // Should not happen.
+            break;
+    }
+}
+
+
+// Flash operation failure callback handler. If the maximum number of retries has
+// been reached, notifies the application and advances the queue.
+static void on_operation_failure(fs_op_t const * const p_op)
+{
+    if (++m_retry_count > FS_OP_MAX_RETRIES)
+    {
+        m_retry_count = 0;
+
+        send_event(p_op, FS_ERR_OPERATION_TIMEOUT);
+        queue_advance();
+    }
+}
+
+
+// Retrieves a pointer to the next free element in the queue.
+// Additionally, increases the number of elements stored in the queue.
+static bool queue_get_next_free(fs_op_t ** p_op)
+{
+    uint32_t idx;
+
+    if (m_queue.count == FS_QUEUE_SIZE)
+    {
+        return false;
+    }
+
+    idx = ((m_queue.rp + m_queue.count) < FS_QUEUE_SIZE) ?
+           (m_queue.rp + m_queue.count) : ((m_queue.rp + m_queue.count)-FS_QUEUE_SIZE);
+
+    m_queue.count++;
+
+    // Zero the element so that unassigned fields will be zero.
+    memset(&m_queue.op[idx], 0x00, sizeof(fs_op_t));
+
+    *p_op = &m_queue.op[idx];
+
+    return true;
+}
+
+
+fs_ret_t fs_init(void)
+{
+    uint32_t const   total_users     = FS_SECTION_VARS_COUNT;
+    uint32_t         configs_to_init = FS_SECTION_VARS_COUNT;
+    uint32_t const * p_current_end   = FS_PAGE_END_ADDR;
+
+    if (m_flags & FS_FLAG_INITIALIZED)
+    {
+        return FS_SUCCESS;
+    }
+
+    // Each fstorage user has registered one configuration.
+    // The total number of users (and thus the total number of configurations) is
+    // kept in total_users. Some of these users might have specified their flash
+    // boundaries in their configurations. This function sets the flash boundaries
+    // for the remaining user configurations without further user interaction.
+
+    // First, determine how many user configurations this function has to initialize,
+    // out of the total. This number will be kept in configs_to_init.
+
+    for (uint32_t i = 0; i < total_users; i++)
+    {
+        fs_config_t const * const p_config = FS_SECTION_VARS_GET(i);
+
+        if ((p_config->p_start_addr != NULL) &&
+            (p_config->p_end_addr   != NULL))
+        {
+            configs_to_init--;
+        }
+    }
+
+    // For each configuration to initialize, assign flash space based on the priority
+    // specified. Higher priority means a higher memory address.
+
+    for (uint32_t i = 0; i < configs_to_init; i++)
+    {
+        fs_config_t * p_config_i   = FS_SECTION_VARS_GET(i);
+        uint8_t       max_priority = 0;
+        uint8_t       max_index    = i;
+
+        for (uint32_t j = 0; j < total_users; j++)
+        {
+            fs_config_t const * const p_config_j = FS_SECTION_VARS_GET(j);
+
+            #if 0
+            if (p_config_j->priority == p_config_i->priority)
+            {
+                // Duplicated priorities are not allowed.
+                return FS_ERR_INVALID_CFG;
+            }
+            #endif
+
+            if ((p_config_j->p_start_addr != NULL) &&
+                (p_config_j->p_end_addr   != NULL))
+            {
+                // When calculating the configuration with the next highest priority
+                // skip configurations which were already set during a previous iteration.
+                // This check needs to be here to prevent re-using the configurations
+                // with higher priorities which we used in previous iterations.
+                continue;
+            }
+
+            if (p_config_j->priority > max_priority)
+            {
+                max_priority = p_config_j->priority;
+                max_index    = j;
+            }
+        }
+
+        p_config_i = FS_SECTION_VARS_GET(max_index);
+
+        p_config_i->p_end_addr   = p_current_end;
+        p_config_i->p_start_addr = p_current_end - (p_config_i->num_pages * FS_PAGE_SIZE_WORDS);
+
+        p_current_end = p_config_i->p_start_addr;
+    }
+
+    m_flags |= FS_FLAG_INITIALIZED;
+
+    return FS_SUCCESS;
+}
+
+
+fs_ret_t fs_fake_init(void)
+{
+    m_flags |= FS_FLAG_INITIALIZED;
+    return FS_SUCCESS;
+}
+
+
+fs_ret_t fs_store(fs_config_t const * const p_config,
+                  uint32_t    const * const p_dest,
+                  uint32_t    const * const p_src,
+                  uint16_t    const         length_words,
+                  void *                    p_context)
+{
+    fs_op_t * p_op;
+
+    if (!(m_flags & FS_FLAG_INITIALIZED))
+    {
+        return FS_ERR_NOT_INITIALIZED;
+    }
+
+    if (!check_config(p_config))
+    {
+        return FS_ERR_INVALID_CFG;
+    }
+
+    if ((p_src == NULL) || (p_dest == NULL))
+    {
+        return FS_ERR_NULL_ARG;
+    }
+
+    // Check that both pointers are word aligned.
+    if (((uint32_t)p_src  & 0x03) ||
+        ((uint32_t)p_dest & 0x03))
+    {
+        return FS_ERR_UNALIGNED_ADDR;
+    }
+
+    // Check that the operation doesn't go outside the client's memory boundaries.
+    if ((p_config->p_start_addr > p_dest) ||
+        (p_config->p_end_addr   < (p_dest + length_words)))
+    {
+        return FS_ERR_INVALID_ADDR;
+    }
+
+    if (length_words == 0)
+    {
+        return FS_ERR_INVALID_ARG;
+    }
+
+    if (!queue_get_next_free(&p_op))
+    {
+        return FS_ERR_QUEUE_FULL;
+    }
+
+    // Initialize the operation.
+    p_op->p_context          = p_context;
+    p_op->p_config           = p_config;
+    p_op->op_code            = FS_OP_STORE;
+    p_op->store.p_src        = p_src;
+    p_op->store.p_dest       = p_dest;
+    p_op->store.length_words = length_words;
+
+    queue_start();
+
+    return FS_SUCCESS;
+}
+
+
+fs_ret_t fs_erase(fs_config_t const * const p_config,
+                  uint32_t    const * const p_page_addr,
+                  uint16_t    const         num_pages,
+                  void *                    p_context)
+{
+    fs_op_t * p_op;
+
+    if (!(m_flags & FS_FLAG_INITIALIZED))
+    {
+        return FS_ERR_NOT_INITIALIZED;
+    }
+
+    if (!check_config(p_config))
+    {
+        return FS_ERR_INVALID_CFG;
+    }
+
+    if (p_page_addr == NULL)
+    {
+        return FS_ERR_NULL_ARG;
+    }
+
+    // Check that the page is aligned to a page boundary.
+    if (((uint32_t)p_page_addr & (FS_PAGE_SIZE-1)) != 0)
+    {
+        return FS_ERR_UNALIGNED_ADDR;
+    }
+
+    // Check that the operation doesn't go outside the client's memory boundaries.
+    if ((p_page_addr < p_config->p_start_addr) ||
+        (p_page_addr + (FS_PAGE_SIZE_WORDS * num_pages) > p_config->p_end_addr))
+    {
+        return FS_ERR_INVALID_ADDR;
+    }
+
+    if (num_pages == 0)
+    {
+        return FS_ERR_INVALID_ARG;
+    }
+
+    if (!queue_get_next_free(&p_op))
+    {
+        return FS_ERR_QUEUE_FULL;
+    }
+
+    // Initialize the operation.
+    p_op->p_context            = p_context;
+    p_op->p_config             = p_config;
+    p_op->op_code              = FS_OP_ERASE;
+    p_op->erase.page           = ((uint32_t)p_page_addr / FS_PAGE_SIZE);
+    p_op->erase.pages_to_erase = num_pages;
+
+    queue_start();
+
+    return FS_SUCCESS;
+}
+
+
+fs_ret_t fs_queued_op_count_get(uint32_t * const p_op_count)
+{
+    if (p_op_count == NULL)
+    {
+        return FS_ERR_NULL_ARG;
+    }
+
+    *p_op_count = m_queue.count;
+
+    return FS_SUCCESS;
+}
+
+
+void fs_sys_event_handler(uint32_t sys_evt)
+{
+    fs_op_t * const p_op = &m_queue.op[m_queue.rp];
+
+    if (m_flags & FS_FLAG_PROCESSING)
+    {
+        // A flash operation was initiated by this module. Handle the result.
+        switch (sys_evt)
+        {
+            case NRF_EVT_FLASH_OPERATION_SUCCESS:
+                on_operation_success(p_op);
+                break;
+
+            case NRF_EVT_FLASH_OPERATION_ERROR:
+                on_operation_failure(p_op);
+                break;
+        }
+    }
+    else if ((m_flags & FS_FLAG_FLASH_REQ_PENDING))
+    {
+        // A flash operation was initiated outside this module.
+        // A callback which indicates that it has finished was received.
+        m_flags &= ~FS_FLAG_FLASH_REQ_PENDING;
+
+        // If there are any elements left in the queue, set FS_FLAG_PROCESSING.
+        if (m_queue.count > 0)
+        {
+           m_flags |= FS_FLAG_PROCESSING;
+        }
+    }
+
+    // Resume processing the queue, if necessary.
+    queue_process();
+}
+
+bool fs_queue_is_full(void)
+{
+    return (m_queue.count == FS_QUEUE_SIZE);
+}
+
+bool fs_queue_is_empty(void)
+{
+    return (m_queue.count == 0);
+}
+
+#endif //NRF_MODULE_ENABLED(FSTORAGE)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fstorage/fstorage.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,296 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef FSTORAGE_H__
+#define FSTORAGE_H__
+
+/**
+ * @defgroup fstorage fstorage
+ * @ingroup app_common
+ * @{
+ *
+ * @brief   Module which provides functionality to store data to flash and erase flash pages.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "section_vars.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**@brief   fstorage return values. */
+typedef enum
+{
+    FS_SUCCESS,
+    FS_ERR_NOT_INITIALIZED,     //!< Error. The module is not initialized.
+    FS_ERR_INVALID_CFG,         //!< Error. Invalid fstorage configuration.
+    FS_ERR_NULL_ARG,            //!< Error. Argument is NULL.
+    FS_ERR_INVALID_ARG,         //!< Error. Argument contains invalid data.
+    FS_ERR_INVALID_ADDR,        //!< Error. Address out of bounds.
+    FS_ERR_UNALIGNED_ADDR,      //!< Error. Unaligned address.
+    FS_ERR_QUEUE_FULL,          //!< Error. Queue is full.
+    FS_ERR_OPERATION_TIMEOUT,   //!< Error. The operation has timed out.
+    FS_ERR_INTERNAL,            //!< Error. Internal error.
+    FS_ERR_FAILURE_SINCE_LAST   //!< Error. Uncleared error since last call
+} fs_ret_t;
+
+
+/**@brief   fstorage event IDs. */
+typedef enum
+{
+    FS_EVT_STORE,   //!< Event for @ref fs_store.
+    FS_EVT_ERASE    //!< Event for @ref fs_erase.
+} fs_evt_id_t;
+
+
+#if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__ICCARM__)
+  #pragma language=extended
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#endif
+
+/**@brief   An fstorage event. */
+typedef struct
+{
+    fs_evt_id_t id;                         //!< The event ID.
+    void *      p_context;                  //!< User-defined context passed to the interrupt handler.
+    union
+    {
+        struct
+        {
+            uint32_t const * p_data;        //!< Pointer to the data stored in flash.
+            uint16_t         length_words;  //!< Length of the data, in 4-byte words.
+        } store;
+        struct
+        {
+            uint16_t first_page;            //!< First page erased.
+            uint16_t last_page;             //!< Last page erased.
+        } erase;
+    };
+} fs_evt_t;
+
+#if defined(__CC_ARM)
+  #pragma pop
+#elif defined(__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#endif
+
+
+/**@brief   fstorage event handler function prototype.
+ *
+ * @param[in]   evt     The event.
+ * @param[in]   result  The result of the operation.
+ */
+typedef void (*fs_cb_t)(fs_evt_t const * const evt, fs_ret_t result);
+
+
+/**@brief   fstorage application-specific configuration.
+ *
+ * @details Specifies the callback to invoke when an operation completes, the number of flash pages
+ *          requested by the application and the priority with which these are to be assigned, with
+ *          respect to other applications. Additionally, the configuration specifies the boundaries
+ *          of the flash space assigned to an application. The configuration must be provided as an
+ *          argument when invoking @ref fs_store and @ref fs_erase.
+ *
+ * @note    The fields @p p_start_addr and @p p_end_address are set by @ref fs_init, based on the
+ *          value of the field @p priority.
+ */
+typedef struct
+{
+    /**@brief   The beginning of the flash space assigned to the application which registered this
+     *          configuration. This field is set by @ref fs_init. It can also be set manually.
+     */
+    uint32_t const * p_start_addr;
+
+    /**@brief   The end of the flash space assigned to the application which registered this
+     *          configuration. This field is set by @ref fs_init. It can also be set manually.
+     */
+    uint32_t const * p_end_addr;
+
+    fs_cb_t  const   callback;    //!< Callback to run when a flash operation has completed.
+    uint8_t  const   num_pages;   //!< The number of flash pages requested.
+
+    /**@brief   The priority with which fstorage should assign flash pages to this application,
+     *          with respect to other applications. Applications with higher priority will be
+     *          assigned flash pages with a higher memory address. The highest priority is
+     *          reserved. Must be unique among configurations.
+     */
+    uint8_t  const   priority;
+} fs_config_t;
+
+
+/**@brief   Macro for registering an fstorage configuration variable.
+ *          Applications which use fstorage must register with the module using this macro.
+ *          Registering involves defining a variable which holds the configuration of fstorage
+ *          specific to the application which invokes the macro.
+ *
+ * @details This macro places the configuration variable in a section named "fs_data" that
+ *          fstorage uses during initialization and regular operation.
+ *
+ * @param[in]   cfg_var     A @e definition of a @ref fs_config_t variable.
+ */
+#define FS_REGISTER_CFG(cfg_var) NRF_SECTION_VARS_REGISTER_VAR(fs_data, cfg_var)
+
+
+/**@brief   Function for initializing the module.
+ *
+ * @details This functions assigns pages in flash according to all registered configurations.
+ *
+ * @retval  FS_SUCCESS    If the module was successfully initialized.
+ */
+fs_ret_t fs_init(void);
+
+
+fs_ret_t fs_fake_init(void);
+
+
+/**@brief   Function for storing data in flash.
+ *
+ * @details Copies @p length_words words from @p p_src to the location pointed by @p p_dest.
+ *          If the length of the data exceeds @ref FS_MAX_WRITE_SIZE_WORDS, the data will be
+ *          written down in several chunks, as necessary. Only one event will be sent to the
+ *          application upon completion. Both the source and the destination of the data must be
+ *          word aligned. This function is asynchronous, completion is reported via an event sent
+ *          the the callback function specified in the supplied configuration.
+ *
+ * @warning The data to be written to flash has to be kept in memory until the operation has
+ *          terminated, i.e., an event is received.
+ *
+ * @param[in]   p_config        fstorage configuration registered by the application.
+ * @param[in]   p_dest          The address in flash memory where to store the data.
+ * @param[in]   p_src           Pointer to the data to store in flash.
+ * @param[in]   length_words    Length of the data to store, in words.
+ * @param[in]   p_context       User-defined context passed to the interrupt handler.
+ *
+ * @retval  FS_SUCCESS              If the operation was queued successfully.
+ * @retval  FS_ERR_NOT_INITIALIZED  If the module is not initialized.
+ * @retval  FS_ERR_INVALID_CFG      If @p p_config is NULL or contains invalid data.
+ * @retval  FS_ERR_NULL_ARG         If @p p_dest or @p p_src are NULL.
+ * @retval  FS_ERR_INVALID_ARG      If @p length_words is zero.
+ * @retval  FS_ERR_INVALID_ADDR     If @p p_dest or @p p_src are outside of the flash memory
+ *                                  boundaries specified in @p p_config.
+ * @retval  FS_ERR_UNALIGNED_ADDR   If @p p_dest or @p p_src are not aligned to a word boundary.
+ * @retval  FS_ERR_QUEUE_FULL       If the internal operation queue is full.
+ */
+fs_ret_t fs_store(fs_config_t const * const p_config,
+                  uint32_t    const * const p_dest,
+                  uint32_t    const * const p_src,
+                  uint16_t                  length_words,
+                  void *                    p_context);
+
+
+/**@brief   Function for erasing flash pages.
+ *
+ * @details Starting from the page at @p p_page_addr, erases @p num_pages flash pages.
+ *          @p p_page_addr must be aligned to a page boundary. All pages to be erased must be
+ *          within the bounds specified in the supplied fstorage configuration.
+ *          This function is asynchronous. Completion is reported via an event.
+ *
+ * @param[in]   p_config        fstorage configuration registered by the application.
+ * @param[in]   p_page_addr     Address of the page to erase. Must be aligned to a page boundary.
+ * @param[in]   num_pages       Number of pages to erase. May not be zero.
+ * @param[in]   p_context       User-defined context passed to the interrupt handler.
+ *
+ * @retval  FS_SUCCESS              If the operation was queued successfully.
+ * @retval  FS_ERR_NOT_INITIALIZED  If the module is not initialized.
+ * @retval  FS_ERR_INVALID_CFG      If @p p_config is NULL or contains invalid data.
+ * @retval  FS_ERR_NULL_ARG         If @p p_page_addr is NULL.
+ * @retval  FS_ERR_INVALID_ARG      If @p num_pages is zero.
+ * @retval  FS_ERR_INVALID_ADDR     If the operation would go beyond the flash memory boundaries
+ *                                  specified in @p p_config.
+ * @retval  FS_ERR_UNALIGNED_ADDR   If @p p_page_addr is not aligned to a page boundary.
+ * @retval  FS_ERR_QUEUE_FULL       If the internal operation queue is full.
+ */
+fs_ret_t fs_erase(fs_config_t const * const p_config,
+                  uint32_t    const * const p_page_addr,
+                  uint16_t                  num_pages,
+                  void *                    p_context);
+
+
+/**@brief Function for retrieving the number of queued flash operations.
+ *
+ * @param[out]  p_op_count    The number of queued flash operations.
+ *
+ * @retval  FS_SUCCESS          If the number of queued operations was retrieved successfully.
+ * @retval  FS_ERR_NULL_ARG     If @p p_op_count is NULL.
+ */
+fs_ret_t fs_queued_op_count_get(uint32_t * const p_op_count);
+
+
+/**@brief Function for checking if the queue for flash operations is full.
+ *
+ * @retval  true    If the queue is full. 
+ * @retval  false   If there is space for more operations in the queue.
+ */
+bool fs_queue_is_full(void);
+
+
+/**@brief Function for checking if the queue for flash operations is empty.
+ *
+ * @retval  true    If the queue is empty.
+ * @retval  false   If there are flash operations in the queue.
+ */
+bool fs_queue_is_empty(void);
+
+
+/**@brief   Function for handling system events from the SoftDevice.
+ *
+ * @details If any of the modules used by the application rely on fstorage, the application should
+ *          dispatch system events to fstorage using this function.
+ *
+ * @param[in]   sys_evt     System event from the SoftDevice.
+ */
+void fs_sys_event_handler(uint32_t sys_evt);
+
+
+/** @} */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // FSTORAGE_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fstorage/fstorage_internal_defs.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,164 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef FSTORAGE_INTERNAL_DEFS_H__
+#define FSTORAGE_INTERNAL_DEFS_H__
+
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define FS_FLAG_INITIALIZED         (1 << 0)  // The module has been initialized.
+#define FS_FLAG_PROCESSING          (1 << 1)  // The module is processing flash operations.
+// The module is waiting for a flash operation initiated by another module to complete.
+#define FS_FLAG_FLASH_REQ_PENDING   (1 << 2)
+
+#define FS_ERASED_WORD              (0xFFFFFFFF)
+
+// Helper macros for section variables.
+#define FS_SECTION_VARS_GET(i)          NRF_SECTION_VARS_GET((i), fs_config_t, fs_data)
+#define FS_SECTION_VARS_COUNT           NRF_SECTION_VARS_COUNT(fs_config_t, fs_data)
+#define FS_SECTION_VARS_START_ADDR      NRF_SECTION_VARS_START_ADDR(fs_data)
+#define FS_SECTION_VARS_END_ADDR        NRF_SECTION_VARS_END_ADDR(fs_data)
+
+
+// Create section 'fs_data'.
+NRF_SECTION_VARS_CREATE_SECTION(fs_data, fs_config_t);
+
+
+// fstorage op-codes.
+typedef enum
+{
+    FS_OP_NONE,   // No operation.
+    FS_OP_STORE,  // Store data.
+    FS_OP_ERASE   // Erase one or more flash pages.
+} fs_op_code_t;
+
+
+#if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__ICCARM__)
+  #pragma language=extended
+#elif defined(__GNUC__)
+  // anonymous unions are enabled by default.
+#endif
+
+// fstorage operation.
+// Encapsulates details of a flash operation to be executed by this module.
+typedef struct
+{
+    fs_config_t  const * p_config;          // Application-specific fstorage configuration.
+    void *               p_context;         // User-defined context passed to the interrupt handler.
+    fs_op_code_t         op_code;           // ID of the operation.
+    union
+    {
+        struct
+        {
+            uint32_t const * p_src;         // Pointer to the data to be written to flash.
+            uint32_t const * p_dest;        // Destination of the data in flash.
+            uint16_t         length_words;  // Length of the data to be written, in words.
+            uint16_t         offset;        // Write offset.
+        } store;
+        struct
+        {
+            uint16_t page;
+            uint16_t pages_erased;
+            uint16_t pages_to_erase;
+        } erase;
+    };
+} fs_op_t;
+
+#if defined(__CC_ARM)
+  #pragma pop
+#elif defined(__ICCARM__)
+  // leave anonymous unions enabled.
+#elif defined(__GNUC__)
+  // anonymous unions are enabled by default.
+#endif
+
+
+// Queue of requested operations.
+// This queue holds flash operations requested to the module.
+// The data to be written to flash must be kept in memory until the write operation
+// is completed, i.e., an event indicating completion is received.
+typedef struct
+{
+    fs_op_t  op[FS_QUEUE_SIZE];  // Queue elements.
+    uint32_t rp;                 // Index of the operation being processed.
+    uint32_t count;              // Number of elements in the queue.
+} fs_op_queue_t;
+
+
+// Size of a flash page in bytes.
+#if    defined (NRF51)
+    #define FS_PAGE_SIZE    (1024)
+#elif (defined (NRF52) || defined(NRF52840_XXAA))
+    #define FS_PAGE_SIZE    (4096)
+#endif
+
+
+// Size of a flash page in words.
+#define FS_PAGE_SIZE_WORDS  (FS_PAGE_SIZE / sizeof(uint32_t))
+
+
+// Function to obtain the end of the flash space available to fstorage.
+static uint32_t const * fs_flash_page_end_addr()
+{
+    uint32_t const bootloader_addr = NRF_UICR->NRFFW[0];
+
+    return  (uint32_t*)((bootloader_addr != FS_ERASED_WORD) ? bootloader_addr :
+                                                              NRF_FICR->CODESIZE * FS_PAGE_SIZE);
+}
+
+
+// Macro to obtain the address of the last page.
+// If there is a bootloader present the bootloader address read from UICR
+// will act as the page beyond the end of the available flash storage.
+#define FS_PAGE_END_ADDR    (fs_flash_page_end_addr())
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__FSTORAGE_INTERNAL_DEFS_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/hci/hci_mem_pool.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,262 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(HCI_MEM_POOL)
+#include "hci_mem_pool.h"
+#include <stdbool.h>
+#include <stdio.h>
+
+/**@brief RX buffer element instance structure.
+ */
+typedef struct
+{
+    uint8_t  rx_buffer[HCI_RX_BUF_SIZE];                            /**< RX buffer memory array. */
+    uint32_t length;                                                /**< Length of the RX buffer memory array. */
+} rx_buffer_elem_t;
+
+/**@brief RX buffer queue element instance structure.
+ */
+typedef struct
+{
+    rx_buffer_elem_t * p_buffer;                                    /**< Pointer to RX buffer element. */
+    uint32_t           free_window_count;                           /**< Free space element count. */
+    uint32_t           free_available_count;                        /**< Free area element count. */
+    uint32_t           read_available_count;                        /**< Read area element count. */
+    uint32_t           write_index;                                 /**< Write position index. */
+    uint32_t           read_index;                                  /**< Read position index. */
+    uint32_t           free_index;                                  /**< Free position index. */
+} rx_buffer_queue_t;
+
+static bool              m_is_tx_allocated;                         /**< Boolean value to determine if the TX buffer is allocated. */
+static rx_buffer_elem_t  m_rx_buffer_elem_queue[HCI_RX_BUF_QUEUE_SIZE]; /**< RX buffer element instances. */
+static rx_buffer_queue_t m_rx_buffer_queue;                         /**< RX buffer queue element instance. */
+
+
+uint32_t hci_mem_pool_open(void)
+{
+    m_is_tx_allocated                      = false;
+    m_rx_buffer_queue.p_buffer             = m_rx_buffer_elem_queue;
+    m_rx_buffer_queue.free_window_count    = HCI_RX_BUF_QUEUE_SIZE;
+    m_rx_buffer_queue.free_available_count = 0;
+    m_rx_buffer_queue.read_available_count = 0;
+    m_rx_buffer_queue.write_index          = 0;
+    m_rx_buffer_queue.read_index           = 0;
+    m_rx_buffer_queue.free_index           = 0;
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t hci_mem_pool_close(void)
+{
+    return NRF_SUCCESS;
+}
+
+
+uint32_t hci_mem_pool_tx_alloc(void ** pp_buffer)
+{
+    static uint8_t tx_buffer[HCI_TX_BUF_SIZE];
+
+    uint32_t err_code;
+
+    if (pp_buffer == NULL)
+    {
+        return NRF_ERROR_NULL;
+    }
+
+    if (!m_is_tx_allocated)
+    {
+            m_is_tx_allocated = true;
+            *pp_buffer        = tx_buffer;
+            err_code          = NRF_SUCCESS;
+    }
+    else
+    {
+        err_code              = NRF_ERROR_NO_MEM;
+    }
+
+    return err_code;
+}
+
+
+uint32_t hci_mem_pool_tx_free(void)
+{
+    m_is_tx_allocated = false;
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t hci_mem_pool_rx_produce(uint32_t length, void ** pp_buffer)
+{
+    uint32_t err_code;
+
+    if (pp_buffer == NULL)
+    {
+        return NRF_ERROR_NULL;
+    }
+    *pp_buffer = NULL;
+
+    if (m_rx_buffer_queue.free_window_count != 0)
+    {
+        if (length <= HCI_RX_BUF_SIZE)
+        {
+            --(m_rx_buffer_queue.free_window_count);
+            ++(m_rx_buffer_queue.read_available_count);
+
+            *pp_buffer                    =
+                    m_rx_buffer_queue.p_buffer[m_rx_buffer_queue.write_index].rx_buffer;
+
+            m_rx_buffer_queue.free_index |= (1u << m_rx_buffer_queue.write_index);
+
+            // @note: Adjust the write_index making use of the fact that the buffer size is of
+            // power of two and two's complement arithmetic. For details refer example to book
+            // "Making embedded systems: Elicia White".
+            m_rx_buffer_queue.write_index =
+                    (m_rx_buffer_queue.write_index + 1u) & (HCI_RX_BUF_QUEUE_SIZE - 1u);
+
+            err_code                      = NRF_SUCCESS;
+        }
+        else
+        {
+            err_code = NRF_ERROR_DATA_SIZE;
+        }
+    }
+    else
+    {
+        err_code = NRF_ERROR_NO_MEM;
+    }
+
+    return err_code;
+}
+
+
+uint32_t hci_mem_pool_rx_consume(uint8_t * p_buffer)
+{
+    uint32_t err_code;
+    uint32_t consume_index;
+    uint32_t start_index;
+
+    if (m_rx_buffer_queue.free_available_count != 0)
+    {
+        // Find the buffer that has been freed -
+        // Start at read_index minus free_available_count and then increment until read index.
+        err_code      = NRF_ERROR_INVALID_ADDR;
+        consume_index = (m_rx_buffer_queue.read_index - m_rx_buffer_queue.free_available_count) &
+                        (HCI_RX_BUF_QUEUE_SIZE - 1u);
+        start_index   = consume_index;
+
+        do
+        {
+            if (m_rx_buffer_queue.p_buffer[consume_index].rx_buffer == p_buffer)
+            {
+                m_rx_buffer_queue.free_index ^= (1u << consume_index);
+                err_code = NRF_SUCCESS;
+                break;
+            }
+            else
+            {
+                consume_index = (consume_index + 1u) & (HCI_RX_BUF_QUEUE_SIZE - 1u);
+            }
+        }
+        while (consume_index != m_rx_buffer_queue.read_index);
+
+        while (!(m_rx_buffer_queue.free_index & (1 << start_index)) &&
+                (m_rx_buffer_queue.free_available_count != 0))
+        {
+            --(m_rx_buffer_queue.free_available_count);
+            ++(m_rx_buffer_queue.free_window_count);
+            start_index = (consume_index + 1u) & (HCI_RX_BUF_QUEUE_SIZE - 1u);
+        }
+    }
+    else
+    {
+        err_code = NRF_ERROR_NO_MEM;
+    }
+
+    return err_code;
+}
+
+
+uint32_t hci_mem_pool_rx_data_size_set(uint32_t length)
+{
+    // @note: Adjust the write_index making use of the fact that the buffer size is of power
+    // of two and two's complement arithmetic. For details refer example to book
+    // "Making embedded systems: Elicia White".
+    const uint32_t index = (m_rx_buffer_queue.write_index - 1u) & (HCI_RX_BUF_QUEUE_SIZE - 1u);
+    m_rx_buffer_queue.p_buffer[index].length = length;
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t hci_mem_pool_rx_extract(uint8_t ** pp_buffer, uint32_t * p_length)
+{
+    uint32_t err_code;
+
+    if ((pp_buffer == NULL) || (p_length == NULL))
+    {
+        return NRF_ERROR_NULL;
+    }
+
+    if (m_rx_buffer_queue.read_available_count != 0)
+    {
+        --(m_rx_buffer_queue.read_available_count);
+        ++(m_rx_buffer_queue.free_available_count);
+
+        *pp_buffer                   =
+            m_rx_buffer_queue.p_buffer[m_rx_buffer_queue.read_index].rx_buffer;
+        *p_length                    =
+            m_rx_buffer_queue.p_buffer[m_rx_buffer_queue.read_index].length;
+
+        // @note: Adjust the write_index making use of the fact that the buffer size is of power
+        // of two and two's complement arithmetic. For details refer example to book
+        // "Making embedded systems: Elicia White".
+        m_rx_buffer_queue.read_index =
+            (m_rx_buffer_queue.read_index + 1u) & (HCI_RX_BUF_QUEUE_SIZE - 1u);
+
+        err_code                     = NRF_SUCCESS;
+    }
+    else
+    {
+        err_code                     = NRF_ERROR_NO_MEM;
+    }
+
+    return err_code;
+}
+#endif //NRF_MODULE_ENABLED(HCI_MEM_POOL)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/hci/hci_mem_pool.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,167 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup hci_mem_pool Memory pool
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Memory pool implementation
+ *
+ * Memory pool implementation, based on circular buffer data structure, which supports asynchronous
+ * processing of RX data. The current default implementation supports 1 TX buffer and 4 RX buffers.
+ * The memory managed by the pool is allocated from static storage instead of heap. The internal
+ * design of the circular buffer implementing the RX memory layout is illustrated in the picture
+ * below.
+ *
+ * @image html memory_pool.svg "Circular buffer design"
+ *
+ * The expected call order for the RX APIs is as follows:
+ * - hci_mem_pool_rx_produce
+ * - hci_mem_pool_rx_data_size_set
+ * - hci_mem_pool_rx_extract
+ * - hci_mem_pool_rx_consume
+ *
+ * @warning If the above mentioned expected call order is violated the end result can be undefined.
+ *
+ * \par Component specific configuration options
+ *
+ * The following compile time configuration options are available to suit various implementations:
+ * - TX_BUF_SIZE TX buffer size in bytes.
+ * - RX_BUF_SIZE RX buffer size in bytes.
+ * - RX_BUF_QUEUE_SIZE RX buffer element size.
+ */
+
+#ifndef HCI_MEM_POOL_H__
+#define HCI_MEM_POOL_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Function for opening the module.
+ *
+ * @retval NRF_SUCCESS          Operation success.
+ */
+uint32_t hci_mem_pool_open(void);
+
+/**@brief Function for closing the module.
+ *
+ * @retval NRF_SUCCESS          Operation success.
+ */
+uint32_t hci_mem_pool_close(void);
+
+/**@brief Function for allocating requested amount of TX memory.
+ *
+ * @param[out] pp_buffer        Pointer to the allocated memory.
+ *
+ * @retval NRF_SUCCESS          Operation success. Memory was allocated.
+ * @retval NRF_ERROR_NO_MEM     Operation failure. No memory available for allocation.
+ * @retval NRF_ERROR_NULL       Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_mem_pool_tx_alloc(void ** pp_buffer);
+
+/**@brief Function for freeing previously allocated TX memory.
+ *
+ * @note Memory management follows the FIFO principle meaning that free() order must match the
+ *       alloc(...) order, which is the reason for omitting exact memory block identifier as an
+ *       input parameter.
+ *
+ * @retval NRF_SUCCESS          Operation success. Memory was freed.
+ */
+uint32_t hci_mem_pool_tx_free(void);
+
+/**@brief Function for producing a free RX memory block for usage.
+ *
+ * @note Upon produce request amount being 0, NRF_SUCCESS is returned.
+ *
+ * @param[in]  length           Amount, in bytes, of free memory to be produced.
+ * @param[out] pp_buffer        Pointer to the allocated memory.
+ *
+ * @retval NRF_SUCCESS          Operation success. Free RX memory block produced.
+ * @retval NRF_ERROR_NO_MEM     Operation failure. No suitable memory available for allocation.
+ * @retval NRF_ERROR_DATA_SIZE  Operation failure. Request size exceeds limit.
+ * @retval NRF_ERROR_NULL       Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_mem_pool_rx_produce(uint32_t length, void ** pp_buffer);
+
+/**@brief Function for setting the length of the last produced RX memory block.
+ *
+ * @warning If call to this API is omitted the end result is that the following call to
+ *          mem_pool_rx_extract will return incorrect data in the p_length output parameter.
+ *
+ * @param[in]  length           Amount, in bytes, of actual memory used.
+ *
+ * @retval NRF_SUCCESS          Operation success. Length was set.
+ */
+uint32_t hci_mem_pool_rx_data_size_set(uint32_t length);
+
+/**@brief Function for extracting a packet, which has been filled with read data, for further
+ * processing.
+ *
+ * @param[out] pp_buffer        Pointer to the packet data.
+ * @param[out] p_length         Length of packet data in bytes.
+ *
+ * @retval NRF_SUCCESS          Operation success.
+ * @retval NRF_ERROR_NO_MEM     Operation failure. No packet available to extract.
+ * @retval NRF_ERROR_NULL       Operation failure. NULL pointer supplied.
+ */
+uint32_t hci_mem_pool_rx_extract(uint8_t ** pp_buffer, uint32_t * p_length);
+
+/**@brief Function for freeing previously extracted packet, which has been filled with read data.
+ *
+ * @param[in] p_buffer             Pointer to consumed buffer.
+ *
+ * @retval NRF_SUCCESS             Operation success.
+ * @retval NRF_ERROR_NO_MEM        Operation failure. No packet available to free.
+ * @retval NRF_ERROR_INVALID_ADDR  Operation failure. Not a valid pointer.
+ */
+uint32_t hci_mem_pool_rx_consume(uint8_t * p_buffer);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // HCI_MEM_POOL_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/nrf_log.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,212 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**@file
+ *
+ * @defgroup nrf_log Logger module
+ * @{
+ * @ingroup app_common
+ *
+ * @brief The nrf_log module interface.
+ */
+
+#ifndef NRF_LOG_H_
+#define NRF_LOG_H_
+
+#include "sdk_config.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+    
+/** @brief  Default module name prefix.
+ *
+ * The prefix can be defined in a module to override the default.
+ */
+#ifndef NRF_LOG_MODULE_NAME
+    #define NRF_LOG_MODULE_NAME ""
+#endif
+
+/** @brief Severity level for the module.
+ *
+ * The severity level can be defined in a module to override the default.
+ */
+#ifndef NRF_LOG_LEVEL
+    #define NRF_LOG_LEVEL NRF_LOG_DEFAULT_LEVEL
+#endif
+
+/** @brief  Color prefix of debug logs for the module.
+ *
+ * This color prefix can be defined in a module to override the default.
+ */
+#ifndef NRF_LOG_DEBUG_COLOR
+    #define NRF_LOG_DEBUG_COLOR NRF_LOG_COLOR_DEFAULT
+#endif
+
+/** @brief  Color prefix of info logs for the module.
+ *
+ * This color prefix can be defined in a module to override the default.
+ */
+#ifndef NRF_LOG_INFO_COLOR
+    #define NRF_LOG_INFO_COLOR NRF_LOG_COLOR_DEFAULT
+#endif
+
+#include "nrf_log_internal.h"
+
+/** @def NRF_LOG_ERROR
+ *  @brief Macro for logging error messages. It takes a printf-like, formatted
+ *  string with up to seven arguments.
+ *
+ *  @details This macro is compiled only if @ref NRF_LOG_LEVEL includes error logs.
+ */
+
+/** @def NRF_LOG_WARNING
+ *  @brief Macro for logging error messages. It takes a printf-like, formatted
+ *  string with up to seven arguments.
+ *
+ *  @details This macro is compiled only if @ref NRF_LOG_LEVEL includes warning logs.
+ */
+
+/** @def NRF_LOG_INFO
+ *  @brief Macro for logging error messages. It takes a printf-like, formatted
+ *  string with up to seven arguments.
+ *
+ *  @details This macro is compiled only if @ref NRF_LOG_LEVEL includes info logs.
+ */
+
+/** @def NRF_LOG_DEBUG
+ *  @brief Macro for logging error messages. It takes a printf-like, formatted
+ *  string with up to seven arguments.
+ *
+ *  @details This macro is compiled only if @ref NRF_LOG_LEVEL includes debug logs.
+ */
+
+#define NRF_LOG_ERROR(...)                     NRF_LOG_INTERNAL_ERROR(__VA_ARGS__)
+#define NRF_LOG_WARNING(...)                   NRF_LOG_INTERNAL_WARNING( __VA_ARGS__)
+#define NRF_LOG_INFO(...)                      NRF_LOG_INTERNAL_INFO( __VA_ARGS__)
+#define NRF_LOG_DEBUG(...)                     NRF_LOG_INTERNAL_DEBUG( __VA_ARGS__)
+
+/**
+ * @brief A macro for logging a formatted string without any prefix or timestamp.
+ */
+#define NRF_LOG_RAW_INFO(...)                  NRF_LOG_INTERNAL_RAW_INFO( __VA_ARGS__)
+
+/** @def NRF_LOG_HEXDUMP_ERROR
+ *  @brief Macro for logging raw bytes.
+ *  @details It is compiled in only if @ref NRF_LOG_LEVEL includes error logs.
+ *
+ * @param p_data     Pointer to data.
+ * @param len        Data length in bytes.
+ */
+/** @def NRF_LOG_HEXDUMP_WARNING
+ *  @brief Macro for logging raw bytes.
+ *  @details This macro is compiled only if @ref NRF_LOG_LEVEL includes warning logs.
+ *
+ * @param p_data     Pointer to data.
+ * @param len        Data length in bytes.
+ */
+/** @def NRF_LOG_HEXDUMP_INFO
+ *  @brief Macro for logging raw bytes.
+ *  @details This macro is compiled only if @ref NRF_LOG_LEVEL includes info logs.
+ *
+ * @param p_data     Pointer to data.
+ * @param len        Data length in bytes.
+ */
+/** @def NRF_LOG_HEXDUMP_DEBUG
+ *  @brief Macro for logging raw bytes.
+ *  @details This macro is compiled only if @ref NRF_LOG_LEVEL includes debug logs.
+ *
+ * @param p_data     Pointer to data.
+ * @param len        Data length in bytes.
+ */
+#define NRF_LOG_HEXDUMP_ERROR(p_data, len)   NRF_LOG_INTERNAL_HEXDUMP_ERROR(p_data, len)
+#define NRF_LOG_HEXDUMP_WARNING(p_data, len) NRF_LOG_INTERNAL_HEXDUMP_WARNING(p_data, len)
+#define NRF_LOG_HEXDUMP_INFO(p_data, len)    NRF_LOG_INTERNAL_HEXDUMP_INFO(p_data, len)
+#define NRF_LOG_HEXDUMP_DEBUG(p_data, len)   NRF_LOG_INTERNAL_HEXDUMP_DEBUG(p_data, len)
+
+/**
+ * @brief Macro for logging hexdump without any prefix or timestamp.
+ */
+#define NRF_LOG_RAW_HEXDUMP_INFO(p_data, len) NRF_LOG_INTERNAL_RAW_HEXDUMP_INFO(p_data, len)
+
+/**
+ * @brief A macro for blocking reading from bidirectional backend used for logging.
+ *
+ * Macro call is blocking and returns when single byte is received.
+ */
+#define NRF_LOG_GETCHAR()                    NRF_LOG_INTERNAL_GETCHAR()
+
+/**
+ * @brief Function for copying a string to the internal logger buffer if logs are deferred.
+ *
+ * Use this function to store a string that is volatile (for example allocated
+ * on stack) or that may change before the deferred logs are processed. Such string is copied
+ * into the internal logger buffer and is persistent until the log is processed.
+ *
+ * @note If the logs are not deferred, then this function returns the input parameter.
+ *
+ * @param p_str Pointer to the user string.
+ *
+ * @return Address to the location where the string is stored in the internal logger buffer.
+ */
+uint32_t nrf_log_push(char * const p_str);
+
+/**
+ * @brief Macro to be used in a formatted string to a pass float number to the log.
+ *
+ * Macro should be used in formatted string instead of the %f specifier together with
+ * @ref NRF_LOG_FLOAT macro.
+ * Example: NRF_LOG_INFO("My float number" NRF_LOG_FLOAT_MARKER "\r\n", NRF_LOG_FLOAT(f)))
+ */
+#define NRF_LOG_FLOAT_MARKER "%d.%02d"
+
+/**
+ * @brief Macro for dissecting a float number into two numbers (integer and residuum).
+ */
+#define NRF_LOG_FLOAT(val) (int32_t)(val),                                     \
+                           (int32_t)(((val > 0) ? (val) - (int32_t)(val)       \
+                                                : (int32_t)(val) - (val))*100)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_LOG_H_
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/nrf_log_backend.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,89 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**@file
+ * @addtogroup nrf_log Logger module
+ * @ingroup    app_common
+ *
+ * @defgroup nrf_log_backend Backend of nrf_log
+ * @{
+ * @ingroup  nrf_log
+ * @brief    The nrf_log backend interface.
+ */
+
+
+#ifndef NRF_LOG_BACKEND_H__
+#define NRF_LOG_BACKEND_H__
+
+#include "nrf_log_ctrl.h"
+#include "sdk_errors.h"
+#include <stdbool.h>
+
+/**
+ * @brief Function for initializing the logger backend.
+ *
+ * param blocking Set true if handler functions should block until completion.
+ *
+ * @return NRF_SUCCESS after successful initialization, error code otherwise.
+ */
+ret_code_t nrf_log_backend_init(bool blocking);
+
+/**
+ * @brief Function for returning a pointer to a function for handling standard
+ * log entries (@ref NRF_LOG_ERROR, etc.).
+ *
+ * @return Pointer to a handler.
+ */
+nrf_log_std_handler_t nrf_log_backend_std_handler_get(void);
+
+/**
+ * @brief Function for returning a pointer to a function for handling
+ * hexdumps (@ref NRF_LOG_HEXDUMP_ERROR, etc.).
+ *
+ * @return Pointer to a handler.
+ */
+nrf_log_hexdump_handler_t nrf_log_backend_hexdump_handler_get(void);
+
+/**
+ * @brief Function for blocking reading of a byte from the backend.
+ *
+ * @return Byte.
+ */
+uint8_t nrf_log_backend_getchar(void);
+#endif // NRF_LOG_BACKEND_H__
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/nrf_log_ctrl.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,235 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef NRF_LOG_CTRL_H
+#define NRF_LOG_CTRL_H
+
+/**@file
+ * @addtogroup nrf_log Logger module
+ * @ingroup    app_common
+ *
+ * @defgroup nrf_log_ctrl Functions for controlling nrf_log
+ * @{
+ * @ingroup  nrf_log
+ * @brief    The nrf_log control interface.
+ */
+
+#include "sdk_config.h"
+#include "sdk_errors.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf_log_ctrl_internal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Timestamp function prototype.
+ *
+ * @return Timestamp value.
+ */
+typedef uint32_t (*nrf_log_timestamp_func_t)(void);
+
+/**@brief Macro for initializing the logs.
+ *
+ * @note If timestamps are disabled in the configuration, then the provided pointer
+ * can be NULL. Otherwise, it is expected that timestamp_getter is not NULL.
+ *
+ * @param timestamp_func Function that returns the timestamp.
+ *
+ * @return  NRF_SUCCESS after successful initialization, otherwise an error code.
+ */
+#define NRF_LOG_INIT(timestamp_func) NRF_LOG_INTERNAL_INIT(timestamp_func)
+
+
+/**@brief Macro for processing a single log entry from a queue of deferred logs.
+ *
+ * You can call this macro from the main context or from the error handler to process
+ * log entries one by one.
+ *
+ * @note If logs are not deferred, this call has no use and is defined as 'false'.
+ *
+ * @retval true    There are more logs to process in the buffer.
+ * @retval false   No more logs in the buffer.
+ */
+#define NRF_LOG_PROCESS()    NRF_LOG_INTERNAL_PROCESS()
+
+/** @brief Macro for processing all log entries from the buffer.
+ * It blocks until all buffered entries are processed by the backend.
+ *
+ * @note If logs are not deferred, this call has no use and is empty.
+ */
+#define NRF_LOG_FLUSH()      NRF_LOG_INTERNAL_FLUSH()
+
+/** @brief Macro for flushing log data before reset.
+ *
+ * @note If logs are not deferred, this call has no use and is empty.
+ *
+ * @note If RTT is used, then a breakpoint is hit once flushed.
+ */
+#define NRF_LOG_FINAL_FLUSH() NRF_LOG_INTERNAL_FINAL_FLUSH()
+
+/** @brief Macro for changing functions that are used to handle log entries.
+ *
+ * @param default_handler Function for handling log entries.
+ * @param bytes_handler   Function for handling hexdump entries.
+ *
+ */
+#define NRF_LOG_HANDLERS_SET(default_handler, bytes_handler) \
+    NRF_LOG_INTERNAL_HANDLERS_SET(default_handler, bytes_handler)
+
+/**
+ * @brief Function prototype for handling a log entry.
+ *
+ * The backend must implement such prototype.
+ *
+ * @param severity_level Severity level of the entry.
+ * @param p_timestamp    Pointer to the timestamp value. No timestamp if NULL.
+ * @param p_str          Pointer to a formatted string.
+ * @param p_args         Pointer to an array of arguments for a formatted string.
+ * @param nargs          Number of arguments in p_args.
+ *
+ * @retval true          If entry is successfully processed.
+ * @retval false         If entry is not processed.
+ */
+typedef bool (*nrf_log_std_handler_t)(
+    uint8_t                severity_level,
+    const uint32_t * const p_timestamp,
+    const char * const     p_str,
+    uint32_t             * p_args,
+    uint32_t               nargs);
+
+/**
+ * @brief Function prototype for handling a bytes-dumping log entry.
+ *
+ * The backend must implement such prototype. Two buffers are needed because data
+ * is stored internally in a circular buffer so it can be fragmented into up to
+ * two pieces.
+ *
+ * @param severity_level Severity level of the entry.
+ * @param p_timestamp    Pointer to a timestamp value. No timestamp if NULL.
+ * @param p_str          Prefix string for the bytes dump.
+ * @param offset         Indication of how many bytes have already been processed.
+ * @param p_buf0         Pointer to the first part of data.
+ * @param buf0_length    Number of bytes in the first part.
+ * @param p_buf1         Pointer to the second part of data. Optional.
+ * @param buf1_length    Number of bytes in the second part.
+ *
+ * @return Number of bytes processed. If all bytes are processed, it should be a sum of
+ *         buf0_length and buf1_length
+ */
+typedef uint32_t (*nrf_log_hexdump_handler_t)(
+    uint8_t                severity_level,
+    const uint32_t * const p_timestamp,
+    const char * const     p_str,
+    uint32_t               offset,
+    const uint8_t * const  p_buf0,
+    uint32_t               buf0_length,
+    const uint8_t * const  p_buf1,
+    uint32_t               buf1_length);
+
+
+/**
+ * @brief Function for initializing the frontend and the default backend.
+ *
+ * @ref NRF_LOG_INIT calls this function to initialize the frontend and the backend.
+ * If custom backend is used, then @ref NRF_LOG_INIT should not be called.
+ * Instead, frontend and user backend should be verbosely initialized.
+ *
+ * @param timestamp_func Function for getting a 32-bit timestamp.
+ *
+ * @return Error status.
+ *
+ */
+ret_code_t nrf_log_init(nrf_log_timestamp_func_t timestamp_func);
+
+/**
+ * @brief Function for reinitializing the backend in blocking mode.
+ */
+ret_code_t nrf_log_blocking_backend_set(void);
+
+/**
+ * @brief Function for initializing the logger frontend.
+ *
+ * The frontend is initialized with functions for handling log entries. Those
+ * functions are provided by the backend.
+ *
+ * @note This function needs to be called directly only if the @ref NRF_LOG_INIT macro
+ * is not used to initialize the logger.
+ *
+ * @param std_handler      Function for handling standard log entries.
+ * @param hexdump_handler  Function for handling hexdump log entries.
+ * @param timestamp_func   Function for getting a timestamp. It cannot be NULL
+ *                         unless timestamping is disabled.
+ */
+void nrf_log_frontend_init(nrf_log_std_handler_t     std_handler,
+                           nrf_log_hexdump_handler_t hexdump_handler,
+                           nrf_log_timestamp_func_t  timestamp_func);
+
+/**
+ * @brief Function for updating functions that handle log entries.
+ *
+ * @note Use this feature to change the log handling behavior in certain
+ * situations, like in a fault handler.
+ *
+ * @param std_handler      Function for handling standard log entries.
+ * @param hexdump_handler  Function for handling hexdump log entries.
+ */
+void nrf_log_handlers_set(nrf_log_std_handler_t     std_handler,
+                          nrf_log_hexdump_handler_t hexdump_handler);
+
+/**
+ * @brief Function for handling a single log entry.
+ *
+ * Use this function only if the logs are buffered. It takes a single entry from the
+ * buffer and attempts to process it.
+ *
+ * @retval true  If there are more entries to process.
+ * @retval false If there are no more entries to process.
+ */
+bool nrf_log_frontend_dequeue(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_LOG_CTRL_H
+
+/**
+ *@}
+ **/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/src/nrf_log_backend_serial.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,494 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(NRF_LOG)
+#include "nrf_log_backend.h"
+#include "nrf_error.h"
+#include <stdarg.h>
+#include <string.h>
+#include <stdio.h>
+#include <ctype.h>
+
+#if NRF_LOG_BACKEND_SERIAL_USES_RTT
+#include <SEGGER_RTT_Conf.h>
+#include <SEGGER_RTT.h>
+#endif
+
+#if NRF_LOG_BACKEND_SERIAL_USES_UART
+#include "nrf_drv_uart.h"
+#endif
+
+#if NRF_LOG_BACKEND_SERIAL_USES_UART
+static char m_uart_buffer[NRF_LOG_BACKEND_MAX_STRING_LENGTH];
+static nrf_drv_uart_t m_uart = NRF_DRV_UART_INSTANCE(NRF_LOG_BACKEND_UART_INSTANCE);
+
+#if !NRF_MODULE_ENABLED(UART)
+#error "UART driver must be enabled to use UART in nrf_log."
+#endif
+
+#endif //NRF_LOG_BACKEND_SERIAL_USES_UART
+
+#define HEXDUMP_BYTES_PER_LINE               16
+#define HEXDUMP_HEXBYTE_AREA                 3 // Two bytes for hexbyte and space to separate
+#define TIMESTAMP_STR(val) "[%0" NUM_TO_STR(val) "d]"
+
+#define RTT_RETRY_COUNTER 10 //Number of retries before skipping processing
+
+#define HEXDUMP_MAX_STR_LEN (NRF_LOG_BACKEND_MAX_STRING_LENGTH -          \
+                            (HEXDUMP_HEXBYTE_AREA*HEXDUMP_BYTES_PER_LINE +\
+                             NRF_LOG_TIMESTAMP_DIGITS +                   \
+                             4 +/* Color ANSI Escape Code */              \
+                             2)) /* Separators */
+
+static bool m_initialized   = false;
+static bool m_blocking_mode = false;
+static const char m_default_color[] = "\x1B[0m";
+
+#if (NRF_LOG_BACKEND_SERIAL_USES_UART)
+static volatile bool m_rx_done = false;
+#endif
+
+#if (NRF_LOG_BACKEND_SERIAL_USES_UART)
+static void uart_event_handler(nrf_drv_uart_event_t * p_event, void * p_context)
+{
+    // Dummy handler since is_busy feature is used for determining readiness.
+    if (p_event->type == NRF_DRV_UART_EVT_RX_DONE)
+    {
+        m_rx_done = true;
+    }
+}
+#endif //NRF_LOG_BACKEND_SERIAL_USES_UART
+
+
+ret_code_t nrf_log_backend_init(bool blocking)
+{
+
+    if (m_initialized && (blocking == m_blocking_mode))
+    {
+        return NRF_SUCCESS;
+    }
+#if (NRF_LOG_BACKEND_SERIAL_USES_RTT)
+    SEGGER_RTT_Init();
+#endif
+    
+#if (NRF_LOG_BACKEND_SERIAL_USES_UART)
+    uint32_t              ret_code;
+    nrf_drv_uart_config_t uart_config = NRF_DRV_UART_DEFAULT_CONFIG;
+    uart_config.hwfc     =
+            (nrf_uart_hwfc_t)NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL;
+    uart_config.pseltxd  = NRF_LOG_BACKEND_SERIAL_UART_TX_PIN;
+    uart_config.pselrxd  = NRF_LOG_BACKEND_SERIAL_UART_RX_PIN;
+    uart_config.pselrts  = NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN;
+    uart_config.pselcts  = NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN;
+    uart_config.baudrate =
+        (nrf_uart_baudrate_t)NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE;
+    nrf_drv_uart_uninit(&m_uart);
+    ret_code = nrf_drv_uart_init(&m_uart, &uart_config,
+                                 blocking ? NULL : uart_event_handler);
+    if (ret_code != NRF_SUCCESS)
+    {
+        return ret_code;
+    }
+#endif //NRF_LOG_BACKEND_SERIAL_USES_UART
+
+    m_initialized   = true;
+    m_blocking_mode = blocking;
+    return NRF_SUCCESS;
+}
+
+
+static bool serial_is_busy(void)
+{
+    bool res = false;
+
+#if (NRF_LOG_BACKEND_SERIAL_USES_UART)
+    res = nrf_drv_uart_tx_in_progress(&m_uart);
+#endif
+
+#if (NRF_LOG_BACKEND_SERIAL_USES_RTT)
+
+#endif
+
+    return res;
+}
+
+
+static bool serial_tx(uint8_t * p_buf, uint32_t len)
+{
+    bool ret = true;
+
+#if NRF_LOG_BACKEND_SERIAL_USES_UART
+    memcpy(m_uart_buffer, p_buf, len);
+    uint32_t ret_code = nrf_drv_uart_tx(&m_uart, (uint8_t *)m_uart_buffer, len);
+    if (ret_code != NRF_SUCCESS)
+    {
+        ret = false;
+    }
+#endif //NRF_LOG_BACKEND_SERIAL_USES_UART
+
+#if NRF_LOG_BACKEND_SERIAL_USES_RTT
+    uint32_t idx    = 0;
+    uint32_t length = len;
+    uint32_t processed;
+    uint32_t watchdog_counter = RTT_RETRY_COUNTER;
+    do
+    {
+        processed = SEGGER_RTT_WriteNoLock(0, &p_buf[idx], length);
+        idx += processed;
+        length -= processed;
+        if (processed == 0)
+        {
+            // If RTT is not connected then ensure that logger does not block
+            watchdog_counter--;
+            if (watchdog_counter == 0)
+            {
+                break;
+            }
+        }
+    } while (length);
+#endif //NRF_LOG_BACKEND_SERIAL_USES_RTT
+    return ret;
+}
+
+
+static uint8_t serial_get_byte(void)
+{
+    uint8_t data;
+#if NRF_LOG_BACKEND_SERIAL_USES_UART
+    if (m_blocking_mode)
+    {
+        (void)nrf_drv_uart_rx(&m_uart, &data, 1);
+    }
+    else
+    {
+        m_rx_done = false;
+        (void)nrf_drv_uart_rx(&m_uart, &data, 1);
+        while(!m_rx_done);
+    }
+#elif NRF_LOG_BACKEND_SERIAL_USES_RTT
+    data = (uint8_t)SEGGER_RTT_WaitKey();
+#endif //NRF_LOG_BACKEND_SERIAL_USES_RTT
+    return data;
+}
+
+
+static bool buf_len_update(uint32_t * p_buf_len, int32_t new_len)
+{
+    bool ret;
+    if (new_len < 0)
+    {
+        ret = false;
+    }
+    else
+    {
+        *p_buf_len += (uint32_t)new_len;
+        ret = true;
+    }
+    return ret;
+}
+
+
+static bool timestamp_process(const uint32_t * const p_timestamp, char * p_str, uint32_t * p_len)
+{
+    int32_t len = 0;
+    bool    ret = true;
+    if (p_timestamp)
+    {
+#if NRF_LOG_USES_COLORS
+        len = sizeof(m_default_color) - 1;
+        memcpy(p_str, m_default_color, len);
+        *p_len += len;
+#endif //NRF_LOG_USES_COLORS
+        len = snprintf(&p_str[len],NRF_LOG_BACKEND_MAX_STRING_LENGTH, TIMESTAMP_STR(NRF_LOG_TIMESTAMP_DIGITS), (int)*p_timestamp);
+        ret = buf_len_update(p_len, len);
+    }
+    else
+    {
+        *p_len = 0;
+    }
+    return ret;
+}
+
+
+static bool nrf_log_backend_serial_std_handler(
+    uint8_t                severity_level,
+    const uint32_t * const p_timestamp,
+    const char * const     p_str,
+    uint32_t             * p_args,
+    uint32_t               nargs)
+{
+    char     str[NRF_LOG_BACKEND_MAX_STRING_LENGTH];
+    int32_t  tmp_str_len     = 0;
+    uint32_t buffer_len      = 0;
+    bool     status          = true;
+
+    if (serial_is_busy())
+    {
+        return false;
+    }
+
+    if (!timestamp_process(p_timestamp, &str[buffer_len], &buffer_len))
+    {
+        return false;
+    }
+
+    switch (nargs)
+    {
+        case 0:
+        {
+            tmp_str_len = strlen(p_str);
+            if ((tmp_str_len + buffer_len) < NRF_LOG_BACKEND_MAX_STRING_LENGTH)
+            {
+                memcpy(&str[buffer_len], p_str, tmp_str_len);
+            }
+            break;
+        }
+
+        case 1:
+            tmp_str_len = snprintf(&str[buffer_len], NRF_LOG_BACKEND_MAX_STRING_LENGTH-buffer_len, p_str, p_args[0]);
+
+            break;
+
+        case 2:
+            tmp_str_len = snprintf(&str[buffer_len], NRF_LOG_BACKEND_MAX_STRING_LENGTH-buffer_len, p_str, p_args[0], p_args[1]);
+            break;
+
+        case 3:
+            tmp_str_len = snprintf(&str[buffer_len], NRF_LOG_BACKEND_MAX_STRING_LENGTH-buffer_len, p_str, p_args[0], p_args[1], p_args[2]);
+            break;
+
+        case 4:
+            tmp_str_len =
+                snprintf(&str[buffer_len], NRF_LOG_BACKEND_MAX_STRING_LENGTH-buffer_len, p_str, p_args[0], p_args[1], p_args[2], p_args[3]);
+            break;
+
+        case 5:
+            tmp_str_len =
+                snprintf(&str[buffer_len],
+                        NRF_LOG_BACKEND_MAX_STRING_LENGTH-buffer_len,
+                        p_str,
+                        p_args[0],
+                        p_args[1],
+                        p_args[2],
+                        p_args[3],
+                        p_args[4]);
+            break;
+
+        case 6:
+            tmp_str_len =
+                snprintf(&str[buffer_len],
+                        NRF_LOG_BACKEND_MAX_STRING_LENGTH-buffer_len,
+                        p_str,
+                        p_args[0],
+                        p_args[1],
+                        p_args[2],
+                        p_args[3],
+                        p_args[4],
+                        p_args[5]);
+            break;
+
+        default:
+            break;
+    }
+    status = buf_len_update(&buffer_len, tmp_str_len);
+    uint32_t full_buff_len = NRF_LOG_USES_COLORS ?
+            buffer_len + sizeof(m_default_color)-1 : buffer_len;
+    if (status && (full_buff_len <= NRF_LOG_BACKEND_MAX_STRING_LENGTH))
+    {
+        if (NRF_LOG_USES_COLORS)
+        {
+            memcpy(&str[buffer_len], m_default_color, sizeof(m_default_color)-1);
+            buffer_len = full_buff_len;
+        }
+        return serial_tx((uint8_t *)str, buffer_len);
+    }
+    else
+    {
+        // error, snprintf failed.
+        return false;
+    }
+}
+
+
+static void byte2hex(const uint8_t c, char * p_out)
+{
+    uint8_t  nibble;
+    uint32_t i = 2;
+
+    while (i-- != 0)
+    {
+        nibble       = (c >> (4 * i)) & 0x0F;
+        p_out[1 - i] = (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble);
+    }
+}
+
+
+static uint32_t nrf_log_backend_serial_hexdump_handler(
+    uint8_t                severity_level,
+    const uint32_t * const p_timestamp,
+    const char * const     p_str,
+    uint32_t               offset,
+    const uint8_t * const  p_buf0,
+    uint32_t               buf0_length,
+    const uint8_t * const  p_buf1,
+    uint32_t               buf1_length)
+{
+    char     str[NRF_LOG_BACKEND_MAX_STRING_LENGTH];
+    uint32_t slen;
+    char   * p_hex_part;
+    char   * p_char_part;
+    uint8_t  c;
+    uint32_t byte_in_line;
+    uint32_t buffer_len    = 0;
+    uint32_t byte_cnt      = offset;
+    uint32_t length        = buf0_length + buf1_length;
+    uint32_t timestamp_len = p_timestamp ?
+            NRF_LOG_TIMESTAMP_DIGITS+2 : 0; //+2 since timestamp is in brackets
+
+    if (serial_is_busy())
+    {
+        return offset;
+    }
+
+    // If it is the first part of hexdump print the header
+    if (offset == 0)
+    {
+        if (!timestamp_process(p_timestamp, &str[buffer_len], &buffer_len))
+        {
+            return offset;
+        }
+        slen = strlen(p_str);
+        // Saturate string if it's too long.
+        slen = (slen > HEXDUMP_MAX_STR_LEN) ? HEXDUMP_MAX_STR_LEN : slen;
+        memcpy(&str[buffer_len], p_str, slen);
+        buffer_len += slen;
+    }
+
+    do
+    {
+
+        uint32_t  i;
+        uint32_t hex_part_offset  = buffer_len;
+        uint32_t char_part_offset = hex_part_offset +
+                                    (HEXDUMP_BYTES_PER_LINE * HEXDUMP_HEXBYTE_AREA + 1) + // +1 - separator between hexdump and characters.
+                                    timestamp_len;
+
+        p_hex_part  = &str[hex_part_offset];
+        p_char_part = &str[char_part_offset];
+
+        // Fill the blanks to align to timestamp print
+        for (i = 0; i < timestamp_len; i++)
+        {
+            *p_hex_part = ' ';
+            ++p_hex_part;
+        }
+
+        for (byte_in_line = 0; byte_in_line < HEXDUMP_BYTES_PER_LINE; byte_in_line++)
+        {
+            if (byte_cnt >= length)
+            {
+                // file the blanks
+                *p_hex_part++  = ' ';
+                *p_hex_part++  = ' ';
+                *p_hex_part++  = ' ';
+                *p_char_part++ = ' ';
+            }
+            else
+            {
+                if (byte_cnt < buf0_length)
+                {
+                    c = p_buf0[byte_cnt];
+                }
+                else
+                {
+                    c = p_buf1[byte_cnt - buf0_length];
+                }
+                byte2hex(c, p_hex_part);
+                p_hex_part    += 2; // move the pointer since byte in hex was added.
+                *p_hex_part++  = ' ';
+                *p_char_part++ = isprint(c) ? c : '.';
+                byte_cnt++;
+            }
+        }
+        *p_char_part++ = '\r';
+        *p_char_part++ = '\n';
+        *p_hex_part++  = ' ';
+        buffer_len    += timestamp_len +
+                         (HEXDUMP_BYTES_PER_LINE * HEXDUMP_HEXBYTE_AREA + 1) + // space for hex dump and separator between hexdump and string
+                         HEXDUMP_BYTES_PER_LINE +                              // space for stringS dump
+                         2;                                                    // space for new line
+        if (NRF_LOG_USES_COLORS)
+        {
+            memcpy(&str[buffer_len], m_default_color, sizeof(m_default_color)-1);
+            buffer_len +=  sizeof(m_default_color)-1;
+        }
+
+        if (!serial_tx((uint8_t *)str, buffer_len))
+        {
+            return byte_cnt;
+        }
+
+        if (serial_is_busy())
+        {
+            return byte_cnt;
+        }
+        buffer_len = 0;
+    }
+    while (byte_cnt < length);
+    return byte_cnt;
+}
+
+
+nrf_log_std_handler_t nrf_log_backend_std_handler_get(void)
+{
+    return nrf_log_backend_serial_std_handler;
+}
+
+
+nrf_log_hexdump_handler_t nrf_log_backend_hexdump_handler_get(void)
+{
+    return nrf_log_backend_serial_hexdump_handler;
+}
+
+
+uint8_t nrf_log_backend_getchar(void)
+{
+    return serial_get_byte();
+}
+
+#endif // NRF_MODULE_ENABLED(NRF_LOG)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/src/nrf_log_ctrl_internal.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,95 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef NRF_LOG_CTRL_INTERNAL_H
+#define NRF_LOG_CTRL_INTERNAL_H
+/**
+ * @cond (NODOX)
+ * @defgroup nrf_log_ctrl_internal Auxiliary internal types declarations
+ * @{
+ * @internal
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(NRF_LOG)
+#include "app_util_platform.h"
+
+#define NRF_LOG_INTERNAL_INIT(timestamp_func) \
+    nrf_log_init(timestamp_func)
+
+#if (NRF_LOG_DEFERRED == 0)
+#define NRF_LOG_INTERNAL_PROCESS() false
+#define NRF_LOG_INTERNAL_FLUSH()
+#define NRF_LOG_INTERNAL_FINAL_FLUSH()
+#else
+#define NRF_LOG_INTERNAL_PROCESS() nrf_log_frontend_dequeue()
+#define NRF_LOG_INTERNAL_FLUSH()            \
+    do {                                    \
+        while (NRF_LOG_INTERNAL_PROCESS()); \
+    } while(0)
+
+#if NRF_LOG_BACKEND_SERIAL_USES_RTT
+#define NRF_LOG_INTERNAL_BACKEND_FINAL NRF_BREAKPOINT_COND
+#else
+#define NRF_LOG_INTERNAL_BACKEND_FINAL
+#endif
+
+#define NRF_LOG_INTERNAL_FINAL_FLUSH()      \
+    do {                                    \
+    (void)nrf_log_blocking_backend_set();   \
+        NRF_LOG_INTERNAL_FLUSH();           \
+        NRF_LOG_INTERNAL_BACKEND_FINAL;     \
+    } while(0)
+
+#endif
+
+#define NRF_LOG_INTERNAL_HANDLERS_SET(default_handler, bytes_handler) \
+    nrf_log_handlers_set(default_handler, bytes_handler)
+
+#else // NRF_MODULE_ENABLED(NRF_LOG)
+#define NRF_LOG_INTERNAL_PROCESS()            false
+#define NRF_LOG_INTERNAL_FLUSH()
+#define NRF_LOG_INTERNAL_INIT(timestamp_func) NRF_SUCCESS
+#define NRF_LOG_INTERNAL_HANDLERS_SET(default_handler, bytes_handler) \
+    UNUSED_PARAMETER(default_handler); UNUSED_PARAMETER(bytes_handler)
+#define NRF_LOG_INTERNAL_FINAL_FLUSH()
+#endif // NRF_MODULE_ENABLED(NRF_LOG)
+
+/** @}
+ * @endcond
+ */
+#endif // NRF_LOG_CTRL_INTERNAL_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/src/nrf_log_frontend.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,824 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(NRF_LOG)
+#include "app_util.h"
+#include "app_util_platform.h"
+#include "nrf_log.h"
+#include "nrf_log_internal.h"
+#include "nrf_log_backend.h"
+#include "nrf_log_ctrl.h"
+#include <string.h>
+
+#if NRF_LOG_DEFERRED
+STATIC_ASSERT((NRF_LOG_DEFERRED_BUFSIZE == 0) || IS_POWER_OF_TWO(NRF_LOG_DEFERRED_BUFSIZE));
+#else
+#define NRF_LOG_DEFERRED_BUFSIZE 1
+#endif
+
+/**
+ * brief An internal control block of the logger
+ *
+ * @note Circular buffer is using never cleared indexes and a mask. It means
+ * that logger may break when indexes overflows. However, it is quite unlikely.
+ * With rate of 1000 log entries with 2 parameters per second such situation
+ * would happen after 12 days.
+ */
+typedef struct
+{
+    uint32_t                  wr_idx;          // Current write index (never reset)
+    uint32_t                  rd_idx;          // Current read index  (never_reset)
+    uint32_t                  mask;            // Size of buffer (must be power of 2) presented as mask
+    uint32_t                  buffer[NRF_LOG_DEFERRED_BUFSIZE];
+    nrf_log_timestamp_func_t  timestamp_func;  // A pointer to function that returns timestamp
+    nrf_log_std_handler_t     std_handler;     // A handler used for processing standard log calls
+    nrf_log_hexdump_handler_t hexdump_handler; // A handler for processing hex dumps
+} log_data_t;
+
+static log_data_t   m_log_data;
+#if (NRF_LOG_DEFERRED == 1)
+static const char * m_overflow_info = NRF_LOG_ERROR_COLOR_CODE "Overflow\r\n";
+#endif //(NRF_LOG_DEFERRED == 1)
+
+/**
+ * Set of macros for encoding and decoding header for log entries.
+ * There are 3 types of entries:
+ * 1. Standard entry (STD)
+ *    An entry consists of header, pointer to string and values. Header contains
+ *    severity leveland determines number of arguments and thus size of the entry.
+ *    Since flash address space starts from 0x00000000 and is limited to kB rather
+ *    than MB 22 bits are used to store the address (4MB). It is used that way to
+ *    save one RAM memory.
+ *
+ *    --------------------------------
+ *    |TYPE|SEVERITY|NARGS|    P_STR |
+ *    |------------------------------|
+ *    |    TIMESTAMP (optional)      |
+ *    |------------------------------|
+ *    |             ARG0             |
+ *    |------------------------------|
+ *    |             ....             |
+ *    |------------------------------|
+ *    |             ARG(nargs-1)     |
+ *    --------------------------------
+ *
+ * 2. Hexdump entry (HEXDUMP) is used for dumping raw data. An entry consists of
+ *    header, optional timestamp, pointer to string and data. A header contains
+ *    length (10bit) and offset which is updated after backend processes part of
+ *    data.
+ *
+ *    --------------------------------
+ *    |TYPE|SEVERITY|NARGS|OFFSET|LEN|
+ *    |------------------------------|
+ *    |    TIMESTAMP (optional)      |
+ *    |------------------------------|
+ *    |           P_STR              |
+ *    |------------------------------|
+ *    |             data             |
+ *    |------------------------------|
+ *    |  data |       dummy          |
+ *    --------------------------------
+ *
+ * 3. Pushed string. If string is pushed into the logger internal buffer it is
+ *    stored as PUSHED entry. It consists of header, unused data (optional) and
+ *    string. Unused data is present if string does not not fit into a buffer
+ *    without wrapping (and string cannot be wrapped). In that case header
+ *    contains information about offset.
+ *
+ *    --------------------------------
+ *    |TYPE| OFFSET   |      LEN     |
+ *    |------------------------------|
+ *    |           OFFSET             |
+ *    |------------------------------|
+ * end|           OFFSET             |
+ *   0|------------------------------|
+ *    |           STRING             |
+ *    |------------------------------|
+ *    |  STRING |     dummy          |
+ *    --------------------------------
+ */
+#define HEADER_SIZE         ((NRF_LOG_USES_TIMESTAMP) ? 2 : 1)
+
+#define STD_ADDR_MASK       ((uint32_t)(1U << 22) - 1U)
+#define HEADER_TYPE_STD     1U
+#define HEADER_TYPE_HEXDUMP 2U
+#define HEADER_TYPE_PUSHED  0U
+
+typedef struct
+{
+    uint32_t type       : 2;
+    uint32_t raw        : 1;
+    uint32_t data       : 29;
+} nrf_log_generic_header_t;
+
+typedef struct
+{
+    uint32_t type       : 2;
+    uint32_t raw        : 1;
+    uint32_t severity   : 3;
+    uint32_t nargs      : 4;
+    uint32_t addr       : 22;
+} nrf_log_std_header_t;
+
+typedef struct
+{
+    uint32_t type       : 2;
+    uint32_t raw        : 1;
+    uint32_t severity   : 3;
+    uint32_t offset     : 10;
+    uint32_t reserved   : 6;
+    uint32_t len        : 10;
+} nrf_log_hexdump_header_t;
+
+typedef struct
+{
+    uint32_t type       : 2;
+    uint32_t reserved0  : 4;
+    uint32_t offset     : 10;
+    uint32_t reserved1  : 6;
+    uint32_t len        : 10;
+} nrf_log_pushed_header_t;
+
+typedef union
+{
+    nrf_log_generic_header_t generic;
+    nrf_log_std_header_t     std;
+    nrf_log_hexdump_header_t hexdump;
+    nrf_log_pushed_header_t  pushed;
+    uint32_t                 raw;
+} nrf_log_header_t;
+
+/* IAR does not support initialization with non-constant variables */
+#if defined ( __ICCARM__ )
+#define STD_HEADER_DEF(NAME, P_STR, SEVERITY, NARGS)        \
+    nrf_log_header_t NAME = {                               \
+        .std = {                                            \
+            .type     = HEADER_TYPE_STD,                    \
+        }                                                   \
+    };                                                      \
+    NAME.std.type     = HEADER_TYPE_STD;                    \
+    NAME.std.raw      = ((SEVERITY) & NRF_LOG_RAW);         \
+    NAME.std.severity = (SEVERITY) & NRF_LOG_LEVEL_MASK;    \
+    NAME.std.nargs    = (NARGS);                            \
+    NAME.std.addr     = ((uint32_t)(P_STR) & STD_ADDR_MASK)
+#else
+#define STD_HEADER_DEF(NAME, P_STR, SEVERITY, NARGS)       \
+    nrf_log_header_t NAME = {                              \
+        .std = {                                           \
+            .type     = HEADER_TYPE_STD,                   \
+            .raw      = ((SEVERITY) & NRF_LOG_RAW),        \
+            .severity = (SEVERITY) & NRF_LOG_LEVEL_MASK,   \
+            .nargs    = (NARGS),                           \
+            .addr     = ((uint32_t)(P_STR) & STD_ADDR_MASK)\
+        }                                                  \
+    }
+#endif
+
+#if defined ( __ICCARM__ )
+#define HEXDUMP_HEADER_DEF(NAME, SEVERITY, LENGTH)          \
+    nrf_log_header_t NAME = {                               \
+        .hexdump = {                                        \
+            .type     = HEADER_TYPE_HEXDUMP,                \
+            .offset   = 0,                                  \
+        }                                                   \
+    };                                                      \
+    NAME.hexdump.raw      = ((SEVERITY) & NRF_LOG_RAW);     \
+    NAME.hexdump.severity = (SEVERITY) & NRF_LOG_LEVEL_MASK;\
+    NAME.hexdump.len      = (LENGTH)
+
+#else
+#define HEXDUMP_HEADER_DEF(NAME, SEVERITY, LENGTH)          \
+    nrf_log_header_t NAME = {                               \
+        .hexdump = {                                        \
+            .type     = HEADER_TYPE_HEXDUMP,                \
+            .raw      = ((SEVERITY) & NRF_LOG_RAW),         \
+            .severity = (SEVERITY) & NRF_LOG_LEVEL_MASK,    \
+            .offset   = 0,                                  \
+            .len      = LENGTH,                             \
+        }                                                   \
+    }
+#endif
+
+#if defined ( __ICCARM__ )
+#define PUSHED_HEADER_DEF(NAME, OFFSET, LENGTH)        \
+    nrf_log_header_t NAME = {                          \
+        .pushed = {                                    \
+            .type   = HEADER_TYPE_PUSHED,              \
+        }                                              \
+    };                                                 \
+    NAME.pushed.offset = (OFFSET);                     \
+    NAME.pushed.len   = (LENGTH)
+
+#else
+#define PUSHED_HEADER_DEF(NAME, OFFSET, LENGTH)        \
+    nrf_log_header_t NAME = {                          \
+        .pushed = {                                    \
+            .type   = HEADER_TYPE_PUSHED,              \
+            .offset = (OFFSET),                        \
+            .len    = (LENGTH),                        \
+        }                                              \
+    }
+
+#endif
+
+ret_code_t nrf_log_init(nrf_log_timestamp_func_t timestamp_func)
+{
+    if (NRF_LOG_USES_TIMESTAMP && (timestamp_func == NULL))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    ret_code_t err_code = nrf_log_backend_init(NRF_LOG_DEFERRED ? false : true);
+
+    if (err_code == NRF_SUCCESS)
+    {
+        nrf_log_frontend_init(nrf_log_backend_std_handler_get(),
+                              nrf_log_backend_hexdump_handler_get(),
+                              timestamp_func);
+    }
+    return err_code;
+}
+
+
+ret_code_t nrf_log_blocking_backend_set(void)
+{
+    // Return value is ommited because
+    return nrf_log_backend_init(true);
+}
+
+
+void nrf_log_frontend_init(nrf_log_std_handler_t     std_handler,
+                           nrf_log_hexdump_handler_t hexdump_handler,
+                           nrf_log_timestamp_func_t  timestamp_func)
+{
+#if NRF_LOG_DEFERRED
+    m_log_data.mask   = NRF_LOG_DEFERRED_BUFSIZE - 1;
+    m_log_data.wr_idx = 0;
+    m_log_data.rd_idx = 0;
+#endif //NRF_LOG_DEFERRED
+#if NRF_LOG_USES_TIMESTAMP
+    m_log_data.timestamp_func = timestamp_func;
+#endif //NRF_LOG_USES_TIMESTAMP
+    nrf_log_handlers_set(std_handler, hexdump_handler);
+}
+
+
+void nrf_log_handlers_set(nrf_log_std_handler_t     std_handler,
+                          nrf_log_hexdump_handler_t hexdump_handler)
+{
+    m_log_data.std_handler     = std_handler;
+    m_log_data.hexdump_handler = hexdump_handler;
+}
+
+#if (NRF_LOG_DEFERRED == 1)
+/**
+ * @brief Allocates chunk in a buffer for one entry and injects overflow if
+ * there is no room for requested entry.
+ *
+ * @param nargs    Number of 32bit arguments. In case of allocating for hex dump it
+ * is the size of the buffer in 32bit words (ceiled).
+ * @param p_wr_idx Pointer to write index.
+ *
+ * @return True if successful allocation, false otherwise.
+ *
+ */
+static inline bool buf_prealloc(uint32_t nargs, uint32_t * p_wr_idx)
+{
+    nargs += HEADER_SIZE;
+    uint32_t ovflw_tag_size = HEADER_SIZE;
+    bool     ret            = true;
+    CRITICAL_REGION_ENTER();
+    *p_wr_idx = m_log_data.wr_idx;
+    uint32_t available_words = (m_log_data.mask + 1) - (m_log_data.wr_idx - m_log_data.rd_idx);
+    uint32_t required_words  = nargs + ovflw_tag_size; // room for current entry and overflow
+    if (required_words > available_words)
+    {
+        if (available_words >= HEADER_SIZE)
+        {
+            // Overflow entry is injected
+            STD_HEADER_DEF(header, m_overflow_info, NRF_LOG_LEVEL_INTERNAL, 0);
+            m_log_data.buffer[m_log_data.wr_idx++ & m_log_data.mask] =
+                header.raw;
+#if NRF_LOG_USES_TIMESTAMP
+            m_log_data.buffer[m_log_data.wr_idx++ & m_log_data.mask] =
+                m_log_data.timestamp_func();
+#endif //NRF_LOG_USES_TIMESTAMP
+        }
+        // overflow case
+        ret = false;
+    }
+    else
+    {
+        m_log_data.wr_idx += nargs;
+    }
+    CRITICAL_REGION_EXIT();
+    return ret;
+}
+
+
+/**
+ * @brief Function for preallocating a continuous chunk of memory from circular buffer.
+ *
+ * If buffer does not fit starting from current position it will be allocated at
+ * the beginning of the circular buffer and offset will be returned indicating
+ * how much memory has been ommited at the end of the buffer. Function is
+ * using critical section.
+ *
+ * @param len32    Length of buffer to allocate. Given in words.
+ * @param p_offset Offset of the buffer.
+ * @param p_wr_idx Pointer to write index.
+ *
+ * @return A pointer to the allocated buffer. NULL if allocation failed.
+ */
+static inline uint32_t * cont_buf_prealloc(uint32_t len32,
+                                           uint32_t * p_offset,
+                                           uint32_t * p_wr_idx)
+{
+    uint32_t * p_buf = NULL;
+
+    len32++; // Increment because 32bit header is needed to be stored.
+
+    CRITICAL_REGION_ENTER();
+    *p_wr_idx = m_log_data.wr_idx;
+    uint32_t available_words = (m_log_data.mask + 1) -
+                               (m_log_data.wr_idx & m_log_data.mask);
+    if (len32 <= available_words)
+    {
+        // buffer will fit as is
+        p_buf              = &m_log_data.buffer[(m_log_data.wr_idx + 1) & m_log_data.mask];
+        m_log_data.wr_idx += len32;
+        *p_offset          = 0;
+    }
+    else if (len32 < (m_log_data.rd_idx & m_log_data.mask))
+    {
+        // wraping to the begining of the buffer
+        m_log_data.wr_idx += (len32 + available_words - 1);
+        *p_offset          = available_words - 1;
+        p_buf              = m_log_data.buffer;
+    }
+    available_words = (m_log_data.mask + 1) - (m_log_data.wr_idx - m_log_data.rd_idx);
+    // If there is no more room for even overflow tag indicate failed allocation.
+    if (available_words < HEADER_SIZE)
+    {
+        p_buf = NULL;
+    }
+    CRITICAL_REGION_EXIT();
+
+    return p_buf;
+}
+#endif //(NRF_LOG_DEFERRED == 1)
+
+
+#if (NRF_LOG_DEFERRED == 0)
+static inline void nrf_log_direct_feed(uint8_t            type,
+                                       char const * const p_str,
+                                       uint32_t         * p_args,
+                                       uint32_t           nargs)
+{
+    uint32_t   timestamp   = 0;
+    uint32_t * p_timestamp = NRF_LOG_USES_TIMESTAMP ? &timestamp : NULL;
+
+#if NRF_LOG_USES_TIMESTAMP
+    timestamp = m_log_data.timestamp_func();
+#else //NRF_LOG_USES_TIMESTAMP
+    UNUSED_VARIABLE(timestamp);
+#endif //NRF_LOG_USES_TIMESTAMP
+
+    UNUSED_VARIABLE
+      (m_log_data.std_handler(type, p_timestamp, (char *)p_str, p_args, nargs));
+
+}
+#endif //(NRF_LOG_DEFERRED == 0)
+
+
+uint32_t nrf_log_push(char * const p_str)
+{
+#if (NRF_LOG_DEFERRED == 0)
+    return (uint32_t)p_str;
+#else //(NRF_LOG_DEFERRED == 0)
+    uint32_t mask      = m_log_data.mask;
+    uint32_t slen      = strlen(p_str) + 1;
+    uint32_t buflen    = CEIL_DIV(slen, 4);
+    uint32_t offset    = 0;
+    uint32_t wr_idx;
+    char   * p_dst_str = (char *)cont_buf_prealloc(buflen, &offset, &wr_idx);
+    if (p_dst_str)
+    {
+        PUSHED_HEADER_DEF(header, offset, buflen);
+        m_log_data.buffer[wr_idx++ & mask] = header.raw;
+        memcpy(p_dst_str, p_str, slen);
+    }
+    return (uint32_t)p_dst_str;
+#endif //(NRF_LOG_DEFERRED == 0)
+}
+
+
+void nrf_log_frontend_std_0(uint8_t severity, char const * const p_str)
+{
+#if (NRF_LOG_DEFERRED == 0)
+    nrf_log_direct_feed(severity, p_str, NULL, 0);
+#else //(NRF_LOG_DEFERRED == 0)
+    uint32_t nargs  = 0;
+    uint32_t mask   = m_log_data.mask;
+    uint32_t wr_idx;
+    if (buf_prealloc(nargs, &wr_idx))
+    {
+        // Proceed only if buffer was successfully preallocated.
+        STD_HEADER_DEF(header, p_str, severity, nargs);
+        m_log_data.buffer[wr_idx++ & mask] = header.raw;
+#if NRF_LOG_USES_TIMESTAMP
+        m_log_data.buffer[wr_idx++ & mask] = m_log_data.timestamp_func();
+#endif //NRF_LOG_USES_TIMESTAMP
+    }
+#endif //(NRF_LOG_DEFERRED == 0)
+}
+
+
+void nrf_log_frontend_std_1(uint8_t            severity,
+                            char const * const p_str,
+                            uint32_t           val0)
+{
+#if (NRF_LOG_DEFERRED == 0)
+    uint32_t args[] = {val0};
+    nrf_log_direct_feed(severity, p_str, args, ARRAY_SIZE(args));
+#else //(NRF_LOG_DEFERRED == 0)
+    uint32_t nargs  = 1;
+    uint32_t mask   = m_log_data.mask;
+    uint32_t wr_idx;
+    if (buf_prealloc(nargs, &wr_idx))
+    {
+        // Proceed only if buffer was successfully preallocated.
+        STD_HEADER_DEF(header, p_str, severity, nargs);
+        m_log_data.buffer[wr_idx++ & mask] = header.raw;
+#if NRF_LOG_USES_TIMESTAMP
+        m_log_data.buffer[wr_idx++ & mask] = m_log_data.timestamp_func();
+#endif //NRF_LOG_USES_TIMESTAMP
+        m_log_data.buffer[wr_idx & mask] = val0;
+    }
+#endif //(NRF_LOG_DEFERRED == 0)
+}
+
+
+void nrf_log_frontend_std_2(uint8_t            severity,
+                            char const * const p_str,
+                            uint32_t           val0,
+                            uint32_t           val1)
+{
+#if (NRF_LOG_DEFERRED == 0)
+    uint32_t args[] = {val0, val1};
+    nrf_log_direct_feed(severity, p_str, args, ARRAY_SIZE(args));
+#else //(NRF_LOG_DEFERRED == 0)
+    uint32_t nargs  = 2;
+    uint32_t mask   = m_log_data.mask;
+    uint32_t wr_idx;
+    if (buf_prealloc(nargs, &wr_idx))
+    {
+        // Proceed only if buffer was successfully preallocated.
+        STD_HEADER_DEF(header, p_str, severity, nargs);
+        m_log_data.buffer[wr_idx++ & mask] = header.raw;
+#if NRF_LOG_USES_TIMESTAMP
+        m_log_data.buffer[wr_idx++ & mask] = m_log_data.timestamp_func();
+#endif //NRF_LOG_USES_TIMESTAMP
+        m_log_data.buffer[wr_idx++ & mask] = val0;
+        m_log_data.buffer[wr_idx & mask]   = val1;
+    }
+#endif //(NRF_LOG_DEFERRED == 0)
+}
+
+
+void nrf_log_frontend_std_3(uint8_t            severity,
+                            char const * const p_str,
+                            uint32_t           val0,
+                            uint32_t           val1,
+                            uint32_t           val2)
+{
+#if (NRF_LOG_DEFERRED == 0)
+    uint32_t args[] = {val0, val1, val2};
+    nrf_log_direct_feed(severity, p_str, args, ARRAY_SIZE(args));
+#else //(NRF_LOG_DEFERRED == 0)
+    uint32_t nargs  = 3;
+    uint32_t mask   = m_log_data.mask;
+    uint32_t wr_idx;
+    if (buf_prealloc(nargs, &wr_idx))
+    {
+        // Proceed only if buffer was successfully preallocated.
+        STD_HEADER_DEF(header, p_str, severity, nargs);
+        m_log_data.buffer[wr_idx++ & mask] = header.raw;
+#if NRF_LOG_USES_TIMESTAMP
+        m_log_data.buffer[wr_idx++ & mask] = m_log_data.timestamp_func();
+#endif //NRF_LOG_USES_TIMESTAMP
+        m_log_data.buffer[wr_idx++ & mask] = val0;
+        m_log_data.buffer[wr_idx++ & mask] = val1;
+        m_log_data.buffer[wr_idx & mask]   = val2;
+    }
+#endif //(NRF_LOG_DEFERRED == 0)
+}
+
+
+void nrf_log_frontend_std_4(uint8_t            severity,
+                            char const * const p_str,
+                            uint32_t           val0,
+                            uint32_t           val1,
+                            uint32_t           val2,
+                            uint32_t           val3)
+{
+#if (NRF_LOG_DEFERRED == 0)
+    uint32_t args[] = {val0, val1, val2, val3};
+    nrf_log_direct_feed(severity, p_str, args, ARRAY_SIZE(args));
+#else //(NRF_LOG_DEFERRED == 0)
+    uint32_t nargs  = 4;
+    uint32_t mask   = m_log_data.mask;
+    uint32_t wr_idx;
+    if (buf_prealloc(nargs, &wr_idx))
+    {
+        // Proceed only if buffer was successfully preallocated.
+        STD_HEADER_DEF(header, p_str, severity, nargs);
+        m_log_data.buffer[wr_idx++ & mask] = header.raw;
+#if NRF_LOG_USES_TIMESTAMP
+        m_log_data.buffer[wr_idx++ & mask] = m_log_data.timestamp_func();
+#endif //NRF_LOG_USES_TIMESTAMP
+        m_log_data.buffer[wr_idx++ & mask] = val0;
+        m_log_data.buffer[wr_idx++ & mask] = val1;
+        m_log_data.buffer[wr_idx++ & mask] = val2;
+        m_log_data.buffer[wr_idx & mask]   = val3;
+    }
+#endif //(NRF_LOG_DEFERRED == 0)
+}
+
+
+void nrf_log_frontend_std_5(uint8_t            severity,
+                            char const * const p_str,
+                            uint32_t           val0,
+                            uint32_t           val1,
+                            uint32_t           val2,
+                            uint32_t           val3,
+                            uint32_t           val4)
+{
+#if (NRF_LOG_DEFERRED == 0)
+    uint32_t args[] = {val0, val1, val2, val3, val4};
+    nrf_log_direct_feed(severity, p_str, args, ARRAY_SIZE(args));
+#else //(NRF_LOG_DEFERRED == 0)
+    uint32_t nargs  = 5;
+    uint32_t mask   = m_log_data.mask;
+    uint32_t wr_idx;
+    if (buf_prealloc(nargs, &wr_idx))
+    {
+        // Proceed only if buffer was successfully preallocated.
+        STD_HEADER_DEF(header, p_str, severity, nargs);
+        m_log_data.buffer[wr_idx++ & mask] = header.raw;
+#if NRF_LOG_USES_TIMESTAMP
+        m_log_data.buffer[wr_idx++ & mask] = m_log_data.timestamp_func();
+#endif //NRF_LOG_USES_TIMESTAMP
+        m_log_data.buffer[wr_idx++ & mask] = val0;
+        m_log_data.buffer[wr_idx++ & mask] = val1;
+        m_log_data.buffer[wr_idx++ & mask] = val2;
+        m_log_data.buffer[wr_idx++ & mask] = val3;
+        m_log_data.buffer[wr_idx & mask]   = val4;
+    }
+#endif //(NRF_LOG_DEFERRED == 0)
+}
+
+
+void nrf_log_frontend_std_6(uint8_t            severity,
+                            char const * const p_str,
+                            uint32_t           val0,
+                            uint32_t           val1,
+                            uint32_t           val2,
+                            uint32_t           val3,
+                            uint32_t           val4,
+                            uint32_t           val5)
+{
+#if (NRF_LOG_DEFERRED == 0)
+    uint32_t args[] = {val0, val1, val2, val3, val4, val5};
+    nrf_log_direct_feed(severity, p_str, args, ARRAY_SIZE(args));
+#else //(NRF_LOG_DEFERRED == 0)
+    uint32_t nargs  = 6;
+    uint32_t mask   = m_log_data.mask;
+    uint32_t wr_idx;
+    if (buf_prealloc(nargs, &wr_idx))
+    {
+        // Proceed only if buffer was successfully preallocated.
+        STD_HEADER_DEF(header, p_str, severity, nargs);
+        m_log_data.buffer[wr_idx++ & mask] = header.raw;
+#if NRF_LOG_USES_TIMESTAMP
+        m_log_data.buffer[wr_idx++ & mask] = m_log_data.timestamp_func();
+#endif //NRF_LOG_USES_TIMESTAMP
+        m_log_data.buffer[wr_idx++ & mask] = val0;
+        m_log_data.buffer[wr_idx++ & mask] = val1;
+        m_log_data.buffer[wr_idx++ & mask] = val2;
+        m_log_data.buffer[wr_idx++ & mask] = val3;
+        m_log_data.buffer[wr_idx++ & mask] = val4;
+        m_log_data.buffer[wr_idx & mask]   = val5;
+    }
+#endif //(NRF_LOG_DEFERRED == 0)
+}
+
+
+void nrf_log_frontend_hexdump(uint8_t            severity,
+                              char const * const p_str,
+                              const void * const p_data,
+                              uint16_t           length)
+{
+#if (NRF_LOG_DEFERRED == 0)
+    uint32_t timestamp = 0;
+#if NRF_LOG_USES_TIMESTAMP
+    timestamp = m_log_data.timestamp_func();
+#else //NRF_LOG_USES_TIMESTAMP
+    (void) timestamp;
+#endif //NRF_LOG_USES_TIMESTAMP
+
+    uint32_t curr_offset = 0;
+
+    do
+    {
+        curr_offset = m_log_data.hexdump_handler(severity,
+                                                 NRF_LOG_USES_TIMESTAMP ? &timestamp : NULL,
+                                                 p_str,
+                                                 curr_offset,
+                                                 p_data,
+                                                 length,
+                                                 NULL,
+                                                 0);
+    }
+    while (curr_offset < length);
+#else //(NRF_LOG_DEFERRED == 0)
+    uint32_t mask   = m_log_data.mask;
+
+    uint32_t wr_idx;
+    if (buf_prealloc(CEIL_DIV(length, 4) + 1, &wr_idx))
+    {
+        HEXDUMP_HEADER_DEF(header, severity, length);
+        m_log_data.buffer[wr_idx++ & mask] = header.raw;
+#if NRF_LOG_USES_TIMESTAMP
+        m_log_data.buffer[wr_idx++ & mask] = m_log_data.timestamp_func();
+#endif //NRF_LOG_USES_TIMESTAMP
+        m_log_data.buffer[wr_idx++ & mask] = (uint32_t)p_str;
+        uint32_t space0 = sizeof(uint32_t) * (m_log_data.mask + 1 - (wr_idx & mask));
+        if (length <= space0)
+        {
+            memcpy(&m_log_data.buffer[wr_idx & mask], p_data, length);
+        }
+        else
+        {
+            memcpy(&m_log_data.buffer[wr_idx & mask], p_data, space0);
+            length -= space0;
+            memcpy(&m_log_data.buffer[0], &((uint8_t *)p_data)[space0], length);
+        }
+    }
+#endif //(NRF_LOG_DEFERRED == 0)
+}
+
+
+bool buffer_is_empty(void)
+{
+    return (m_log_data.rd_idx == m_log_data.wr_idx);
+}
+
+
+bool nrf_log_frontend_dequeue(void)
+{
+    if (buffer_is_empty())
+    {
+        return false;
+    }
+
+    uint32_t rd_idx        = m_log_data.rd_idx;
+    uint32_t mask          = m_log_data.mask;
+    uint32_t header_rd_idx = rd_idx;
+    // uint32_t header = m_log_data.buffer[rd_idx++ & mask];
+    nrf_log_header_t header;
+    header.raw = m_log_data.buffer[rd_idx++ & mask];
+
+    // Skip any string that is pushed to the circular buffer.
+    while (header.generic.type == HEADER_TYPE_PUSHED)
+    {
+        rd_idx       += (header.pushed.len + header.pushed.offset);
+        header_rd_idx = rd_idx;
+        header.raw    = m_log_data.buffer[rd_idx++ & mask];
+    }
+
+    uint32_t * p_timestamp = NRF_LOG_USES_TIMESTAMP ?
+                             &m_log_data.buffer[rd_idx++ & mask] : NULL;
+
+    if (header.generic.raw)
+    {
+        p_timestamp = NULL;
+    }
+
+    bool ret = false;
+    if (header.generic.type == HEADER_TYPE_HEXDUMP)
+    {
+        // buffer
+        char   * p_str  = (char *)m_log_data.buffer[rd_idx++ & mask];
+        uint32_t length = header.hexdump.len;
+        uint32_t offset = header.hexdump.offset;
+        uint32_t space0 = sizeof(uint32_t) * (mask + 1 - (rd_idx & mask));
+        if (length > space0)
+        {
+            uint8_t * ptr0 = space0 ?
+                             (uint8_t *)&m_log_data.buffer[rd_idx & mask] :
+                             (uint8_t *)&m_log_data.buffer[0];
+            uint8_t   len0 = space0 ? space0 : length;
+            uint8_t * ptr1 = space0 ?
+                             (uint8_t *)&m_log_data.buffer[0] : NULL;
+            uint8_t len1 = space0 ? length - space0 : 0;
+
+            offset = m_log_data.hexdump_handler(header.hexdump.severity,
+                                                p_timestamp, p_str,
+                                                offset,
+                                                ptr0, len0,
+                                                ptr1, len1);
+        }
+        else
+        {
+            offset = m_log_data.hexdump_handler(
+                header.hexdump.severity,
+                p_timestamp,
+                p_str,
+                offset,
+                (uint8_t *)&m_log_data.buffer[rd_idx & mask],
+                length,
+                NULL, 0);
+        }
+
+        if (offset == length)
+        {
+            rd_idx += CEIL_DIV(length, 4);
+            ret     = true;
+        }
+        else
+        {
+            // If there is more log to process just updated the offset but
+            // do not move rd_idx.
+            header.hexdump.offset                   = offset;
+            m_log_data.buffer[header_rd_idx & mask] = header.raw;
+        }
+    }
+    else // standard entry
+    {
+        uint32_t   args[6];
+        uint32_t * p_arg = args;
+        char     * p_str = (char *)((uint32_t)header.std.addr);
+        uint32_t   nargs = header.std.nargs;
+
+        uint32_t i;
+
+        for (i = 0; i < nargs; i++)
+        {
+            *p_arg = m_log_data.buffer[rd_idx++ & mask];
+            p_arg++;
+        }
+
+        ret = m_log_data.std_handler(header.std.severity,
+                                     p_timestamp,
+                                     p_str, args, nargs);
+    }
+    if (ret)
+    {
+        m_log_data.rd_idx = rd_idx;
+    }
+    return buffer_is_empty() ? false : true;
+
+}
+
+uint8_t nrf_log_getchar(void)
+{
+    return nrf_log_backend_getchar();
+}
+
+#endif // NRF_MODULE_ENABLED(NRF_LOG)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/src/nrf_log_internal.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,307 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef NRF_LOG_INTERNAL_H__
+#define NRF_LOG_INTERNAL_H__
+#include "sdk_common.h"
+#include "nrf.h"
+#include "nrf_error.h"
+#include "app_util.h"
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifndef NRF_LOG_DEFAULT_LEVEL
+#define NRF_LOG_DEFAULT_LEVEL 0
+#endif
+
+#ifndef NRF_LOG_USES_COLORS
+#define NRF_LOG_USES_COLORS        0
+#endif
+
+#define NRF_LOG_LEVEL_ERROR        1U
+#define NRF_LOG_LEVEL_WARNING      2U
+#define NRF_LOG_LEVEL_INFO         3U
+#define NRF_LOG_LEVEL_DEBUG        4U
+#define NRF_LOG_LEVEL_INTERNAL     5U
+#define NRF_LOG_LEVEL_MASK         0x07
+#define NRF_LOG_RAW_POS            4U
+#define NRF_LOG_RAW                (1U << NRF_LOG_RAW_POS)
+#define NRF_LOG_LEVEL_INFO_RAW     (NRF_LOG_RAW | NRF_LOG_LEVEL_INFO)
+
+
+#define NRF_LOG_COLOR_CODE_DEFAULT "\x1B[0m"
+#define NRF_LOG_COLOR_CODE_BLACK   "\x1B[1;30m"
+#define NRF_LOG_COLOR_CODE_RED     "\x1B[1;31m"
+#define NRF_LOG_COLOR_CODE_GREEN   "\x1B[1;32m"
+#define NRF_LOG_COLOR_CODE_YELLOW  "\x1B[1;33m"
+#define NRF_LOG_COLOR_CODE_BLUE    "\x1B[1;34m"
+#define NRF_LOG_COLOR_CODE_MAGENTA "\x1B[1;35m"
+#define NRF_LOG_COLOR_CODE_CYAN    "\x1B[1;36m"
+#define NRF_LOG_COLOR_CODE_WHITE   "\x1B[1;37m"
+
+#define NRF_LOG_COLOR_0            NRF_LOG_COLOR_CODE_DEFAULT
+#define NRF_LOG_COLOR_1            NRF_LOG_COLOR_CODE_BLACK
+#define NRF_LOG_COLOR_2            NRF_LOG_COLOR_CODE_RED
+#define NRF_LOG_COLOR_3            NRF_LOG_COLOR_CODE_GREEN
+#define NRF_LOG_COLOR_4            NRF_LOG_COLOR_CODE_YELLOW
+#define NRF_LOG_COLOR_5            NRF_LOG_COLOR_CODE_BLUE
+#define NRF_LOG_COLOR_6            NRF_LOG_COLOR_CODE_MAGENTA
+#define NRF_LOG_COLOR_7            NRF_LOG_COLOR_CODE_CYAN
+#define NRF_LOG_COLOR_8            NRF_LOG_COLOR_CODE_WHITE
+
+#define NRF_LOG_COLOR_DECODE(N) CONCAT_2(NRF_LOG_COLOR_, N)
+#if NRF_LOG_USES_COLORS
+#define NRF_LOG_ERROR_COLOR_CODE   NRF_LOG_COLOR_DECODE(NRF_LOG_ERROR_COLOR)
+#define NRF_LOG_WARNING_COLOR_CODE NRF_LOG_COLOR_DECODE(NRF_LOG_WARNING_COLOR)
+#define NRF_LOG_INFO_COLOR_CODE    NRF_LOG_COLOR_DECODE(NRF_LOG_INFO_COLOR)
+#define NRF_LOG_DEBUG_COLOR_CODE   NRF_LOG_COLOR_DECODE(NRF_LOG_DEBUG_COLOR)
+#else // NRF_LOG_USES_COLORS
+#define NRF_LOG_ERROR_COLOR_CODE
+#define NRF_LOG_WARNING_COLOR_CODE
+#define NRF_LOG_INFO_COLOR_CODE
+#define NRF_LOG_DEBUG_COLOR_CODE
+#endif // NRF_LOG_USES_COLORS
+
+#define LOG_INTERNAL_0(type, prefix, str) \
+    nrf_log_frontend_std_0(type, prefix str)
+#define LOG_INTERNAL_1(type, prefix, str, arg0) \
+    nrf_log_frontend_std_1(type, prefix str, arg0)
+#define LOG_INTERNAL_2(type, prefix, str, arg0, arg1) \
+    nrf_log_frontend_std_2(type, prefix str, arg0, arg1)
+#define LOG_INTERNAL_3(type, prefix, str, arg0, arg1, arg2) \
+    nrf_log_frontend_std_3(type, prefix str, arg0, arg1, arg2)
+#define LOG_INTERNAL_4(type, prefix, str, arg0, arg1, arg2, arg3) \
+    nrf_log_frontend_std_4(type, prefix str, arg0, arg1, arg2, arg3)
+#define LOG_INTERNAL_5(type, prefix, str, arg0, arg1, arg2, arg3, arg4) \
+    nrf_log_frontend_std_5(type, prefix str, arg0, arg1, arg2, arg3, arg4)
+#define LOG_INTERNAL_6(type, prefix, str, arg0, arg1, arg2, arg3, arg4, arg5) \
+    nrf_log_frontend_std_6(type, prefix str, arg0, arg1, arg2, arg3, arg4, arg5)
+
+#define LOG_INTERNAL_X(N, ...)          CONCAT_2(LOG_INTERNAL_, N) (__VA_ARGS__)
+#define LOG_INTERNAL(type, prefix, ...) LOG_INTERNAL_X(NUM_VA_ARGS_LESS_1( \
+                                                           __VA_ARGS__), type, prefix, __VA_ARGS__)
+
+#define NRF_LOG_BREAK      ":"
+
+#define LOG_ERROR_PREFIX   NRF_LOG_ERROR_COLOR_CODE NRF_LOG_MODULE_NAME NRF_LOG_BREAK "ERROR:"
+#define LOG_WARNING_PREFIX NRF_LOG_WARNING_COLOR_CODE NRF_LOG_MODULE_NAME NRF_LOG_BREAK "WARNING:"
+#define LOG_INFO_PREFIX    NRF_LOG_INFO_COLOR_CODE NRF_LOG_MODULE_NAME NRF_LOG_BREAK "INFO:"
+#define LOG_DEBUG_PREFIX   NRF_LOG_DEBUG_COLOR_CODE NRF_LOG_MODULE_NAME NRF_LOG_BREAK "DEBUG:"
+
+#define NRF_LOG_INTERNAL_ERROR(...)                                       \
+    if ((NRF_LOG_LEVEL >= NRF_LOG_LEVEL_ERROR) &&                         \
+        (NRF_LOG_LEVEL_ERROR <= NRF_LOG_DEFAULT_LEVEL))                   \
+    {                                                                     \
+        LOG_INTERNAL(NRF_LOG_LEVEL_ERROR, LOG_ERROR_PREFIX, __VA_ARGS__); \
+    }
+#define NRF_LOG_INTERNAL_HEXDUMP_ERROR(p_data, len)                                              \
+    if ((NRF_LOG_LEVEL >= NRF_LOG_LEVEL_ERROR) &&                                                \
+        (NRF_LOG_LEVEL_ERROR <= NRF_LOG_DEFAULT_LEVEL))                                          \
+    {                                                                                            \
+        nrf_log_frontend_hexdump(NRF_LOG_LEVEL_ERROR, LOG_ERROR_PREFIX "\r\n", (p_data), (len)); \
+    }
+
+#define NRF_LOG_INTERNAL_WARNING(...)                                         \
+    if ((NRF_LOG_LEVEL >= NRF_LOG_LEVEL_WARNING) &&                           \
+        (NRF_LOG_LEVEL_WARNING <= NRF_LOG_DEFAULT_LEVEL))                     \
+    {                                                                         \
+        LOG_INTERNAL(NRF_LOG_LEVEL_WARNING, LOG_WARNING_PREFIX, __VA_ARGS__); \
+    }
+#define NRF_LOG_INTERNAL_HEXDUMP_WARNING(p_data, len)                                                \
+    if ((NRF_LOG_LEVEL >= NRF_LOG_LEVEL_WARNING) &&                                                  \
+        (NRF_LOG_LEVEL_WARNING <= NRF_LOG_DEFAULT_LEVEL))                                            \
+    {                                                                                                \
+        nrf_log_frontend_hexdump(NRF_LOG_LEVEL_WARNING, LOG_WARNING_PREFIX "\r\n", (p_data), (len)); \
+    }
+
+#define NRF_LOG_INTERNAL_INFO(...)                                      \
+    if ((NRF_LOG_LEVEL >= NRF_LOG_LEVEL_INFO) &&                        \
+        (NRF_LOG_LEVEL_INFO <= NRF_LOG_DEFAULT_LEVEL))                  \
+    {                                                                   \
+        LOG_INTERNAL(NRF_LOG_LEVEL_INFO, LOG_INFO_PREFIX, __VA_ARGS__); \
+    }
+
+#define NRF_LOG_INTERNAL_RAW_INFO(...)                                  \
+    if ((NRF_LOG_LEVEL >= NRF_LOG_LEVEL_INFO) &&                        \
+        (NRF_LOG_LEVEL_INFO <= NRF_LOG_DEFAULT_LEVEL))                  \
+    {                                                                   \
+        LOG_INTERNAL(NRF_LOG_LEVEL_INFO | NRF_LOG_RAW, "", __VA_ARGS__);          \
+    }
+
+#define NRF_LOG_INTERNAL_HEXDUMP_INFO(p_data, len)                                             \
+    if ((NRF_LOG_LEVEL >= NRF_LOG_LEVEL_INFO) &&                                               \
+        (NRF_LOG_LEVEL_INFO <= NRF_LOG_DEFAULT_LEVEL))                                         \
+    {                                                                                          \
+        nrf_log_frontend_hexdump(NRF_LOG_LEVEL_INFO, LOG_INFO_PREFIX "\r\n", (p_data), (len)); \
+    }
+
+#define NRF_LOG_INTERNAL_RAW_HEXDUMP_INFO(p_data, len)                                             \
+    if ((NRF_LOG_LEVEL >= NRF_LOG_LEVEL_INFO) &&                                               \
+        (NRF_LOG_LEVEL_INFO <= NRF_LOG_DEFAULT_LEVEL))                                         \
+    {                                                                                          \
+        nrf_log_frontend_hexdump(NRF_LOG_LEVEL_INFO | NRF_LOG_RAW, "", (p_data), (len)); \
+    }
+
+#define NRF_LOG_INTERNAL_DEBUG(...)                                       \
+    if ((NRF_LOG_LEVEL >= NRF_LOG_LEVEL_DEBUG) &&                         \
+        (NRF_LOG_LEVEL_DEBUG <= NRF_LOG_DEFAULT_LEVEL))                   \
+    {                                                                     \
+        LOG_INTERNAL(NRF_LOG_LEVEL_DEBUG, LOG_DEBUG_PREFIX, __VA_ARGS__); \
+    }
+#define NRF_LOG_INTERNAL_HEXDUMP_DEBUG(p_data, len)                                              \
+    if ((NRF_LOG_LEVEL >= NRF_LOG_LEVEL_DEBUG) &&                                                \
+        (NRF_LOG_LEVEL_DEBUG <= NRF_LOG_DEFAULT_LEVEL))                                          \
+    {                                                                                            \
+        nrf_log_frontend_hexdump(NRF_LOG_LEVEL_DEBUG, LOG_DEBUG_PREFIX "\r\n", (p_data), (len)); \
+    }
+
+#if NRF_MODULE_ENABLED(NRF_LOG)
+#define NRF_LOG_INTERNAL_GETCHAR()  nrf_log_getchar()
+#else
+#define NRF_LOG_INTERNAL_GETCHAR()  (void)
+#endif
+
+/**
+ * @brief A function for logging raw string.
+ *
+ * @param severity Severity.
+ * @param p_str    A pointer to a string.
+ */
+void nrf_log_frontend_std_0(uint8_t severity, char const * const p_str);
+
+/**
+ * @brief A function for logging a formatted string with one argument.
+ *
+ * @param severity Severity.
+ * @param p_str    A pointer to a formatted string.
+ * @param val0     An argument.
+ */
+void nrf_log_frontend_std_1(uint8_t            severity,
+                            char const * const p_str,
+                            uint32_t           val0);
+
+/**
+ * @brief A function for logging a formatted string with 2 arguments.
+ *
+ * @param severity   Severity.
+ * @param p_str      A pointer to a formatted string.
+ * @param val0, val1 Arguments for formatting string.
+ */
+void nrf_log_frontend_std_2(uint8_t            severity,
+                            char const * const p_str,
+                            uint32_t           val0,
+                            uint32_t           val1);
+
+/**
+ * @brief A function for logging a formatted string with 3 arguments.
+ *
+ * @param severity         Severity.
+ * @param p_str            A pointer to a formatted string.
+ * @param val0, val1, val2 Arguments for formatting string.
+ */
+void nrf_log_frontend_std_3(uint8_t            severity,
+                            char const * const p_str,
+                            uint32_t           val0,
+                            uint32_t           val1,
+                            uint32_t           val2);
+
+/**
+ * @brief A function for logging a formatted string with 4 arguments.
+ *
+ * @param severity               Severity.
+ * @param p_str                  A pointer to a formatted string.
+ * @param val0, val1, val2, val3 Arguments for formatting string.
+ */
+void nrf_log_frontend_std_4(uint8_t            severity,
+                            char const * const p_str,
+                            uint32_t           val0,
+                            uint32_t           val1,
+                            uint32_t           val2,
+                            uint32_t           val3);
+
+/**
+ * @brief A function for logging a formatted string with 5 arguments.
+ *
+ * @param severity                     Severity.
+ * @param p_str                        A pointer to a formatted string.
+ * @param val0, val1, val2, val3, val4 Arguments for formatting string.
+ */
+void nrf_log_frontend_std_5(uint8_t            severity,
+                            char const * const p_str,
+                            uint32_t           val0,
+                            uint32_t           val1,
+                            uint32_t           val2,
+                            uint32_t           val3,
+                            uint32_t           val4);
+
+/**
+ * @brief A function for logging a formatted string with 6 arguments.
+ *
+ * @param severity                           Severity.
+ * @param p_str                              A pointer to a formatted string.
+ * @param val0, val1, val2, val3, val4, val5 Arguments for formatting string.
+ */
+void nrf_log_frontend_std_6(uint8_t            severity,
+                            char const * const p_str,
+                            uint32_t           val0,
+                            uint32_t           val1,
+                            uint32_t           val2,
+                            uint32_t           val3,
+                            uint32_t           val4,
+                            uint32_t           val5);
+
+/**
+ * @brief A function for logging raw data.
+ *
+ * @param severity Severity.
+ * @param p_str    A pointer to a string which is prefixing the data.
+ * @param p_data   A pointer to data to be dumped.
+ * @param length   Length of data (in bytes).
+ *
+ */
+void nrf_log_frontend_hexdump(uint8_t            severity,
+                              char const * const p_str,
+                              const void * const p_data,
+                              uint16_t           length);
+
+/**
+ * @brief A function for reading a byte from log backend.
+ *
+ * @return Byte.
+ */
+uint8_t nrf_log_getchar(void);
+#endif // NRF_LOG_INTERNAL_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/pwm/app_pwm.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,1008 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(APP_PWM)
+#include "app_pwm.h"
+#include "nrf_drv_timer.h"
+#include "nrf_drv_ppi.h"
+#include "nrf_drv_common.h"
+#include "nrf_drv_gpiote.h"
+#include "nrf_gpiote.h"
+#include "nrf_gpio.h"
+#include "app_util_platform.h"
+#include "nrf_assert.h"
+
+#define APP_PWM_CHANNEL_INITIALIZED                1
+#define APP_PWM_CHANNEL_UNINITIALIZED              0
+
+#define APP_PWM_CHANNEL_ENABLED                    1
+#define APP_PWM_CHANNEL_DISABLED                   0
+
+#define TIMER_PRESCALER_MAX                        9
+#define TIMER_MAX_PULSEWIDTH_US_ON_16M             4095
+
+#ifndef GPIOTE_SET_CLEAR_TASKS
+#define APP_PWM_REQUIRED_PPI_CHANNELS_PER_INSTANCE 2
+#endif
+#define APP_PWM_REQUIRED_PPI_CHANNELS_PER_CHANNEL  2
+
+#define UNALLOCATED                                0xFFFFFFFFUL
+#define BUSY_STATE_CHANGING                        0xFE
+#define BUSY_STATE_IDLE                            0xFF
+
+#define PWM_MAIN_CC_CHANNEL                        2
+#define PWM_SECONDARY_CC_CHANNEL                   3
+
+#ifdef GPIOTE_SET_CLEAR_TASKS
+static bool m_use_ppi_delay_workaround;
+#endif
+
+
+/**
+ * @brief PWM busy status
+ *
+ * Stores the number of a channel being currently updated.
+ *
+ */
+static volatile uint8_t  m_pwm_busy[TIMER_COUNT];
+
+
+/**
+ * @brief New duty cycle value
+ *
+ * When the channel duty cycle reaches this value, the update process is complete.
+ */
+static volatile uint32_t m_pwm_target_value[TIMER_COUNT];
+
+
+/**
+ * @brief PWM ready counter
+ *
+ * The value in this counter is decremented in every PWM cycle after initiating the update.
+ * If an event handler function was specified by the user, it is being called
+ * after two cycle events (at least one full PWM cycle).
+ */
+volatile uint8_t m_pwm_ready_counter[TIMER_COUNT][APP_PWM_CHANNELS_PER_INSTANCE];
+
+/**
+ * @brief Pointers to instances
+ *
+ * This array connects any active timer instance number with the pointer to the PWM instance.
+ * It is used by the interrupt runtime.
+ */
+static const app_pwm_t * m_instances[TIMER_COUNT];
+
+// Macros for getting the polarity of given instance/channel.
+#define POLARITY_ACTIVE(INST,CH)   (( ((INST)->p_cb)->channels_cb[(CH)].polarity == \
+                 APP_PWM_POLARITY_ACTIVE_LOW)?(0):(1))
+#define POLARITY_INACTIVE(INST,CH) (( ((INST)->p_cb)->channels_cb[(CH)].polarity == \
+                 APP_PWM_POLARITY_ACTIVE_LOW)?(1):(0))
+
+//lint -save -e534
+
+
+/**
+ * @brief Workaround for PAN-73.
+ *
+ * @param[in] timer     Timer.
+ * @param[in] enable    Enable or disable.
+ */
+static void pan73_workaround(NRF_TIMER_Type * p_timer, bool enable)
+{
+#ifndef GPIOTE_SET_CLEAR_TASKS
+    if (p_timer == NRF_TIMER0)
+    {
+        *(uint32_t *)0x40008C0C = (enable ? 1 : 0);
+    }
+    else if (p_timer == NRF_TIMER1)
+    {
+        *(uint32_t *)0x40009C0C = (enable ? 1 : 0);
+    }
+    else if (p_timer == NRF_TIMER2)
+    {
+        *(uint32_t *)0x4000AC0C = (enable ? 1 : 0);
+    }
+#else
+    UNUSED_PARAMETER(p_timer);
+    UNUSED_PARAMETER(enable);
+#endif
+}
+
+bool app_pwm_busy_check(app_pwm_t const * const p_instance)
+{
+    uint8_t busy_state = (m_pwm_busy[p_instance->p_timer->instance_id]);
+    bool busy = true;
+    if (busy_state != BUSY_STATE_IDLE)
+    {
+        if (busy_state != BUSY_STATE_CHANGING)
+        {
+            if (nrf_drv_timer_capture_get(p_instance->p_timer, (nrf_timer_cc_channel_t) busy_state)
+                == m_pwm_target_value[p_instance->p_timer->instance_id])
+            {
+                m_pwm_busy[p_instance->p_timer->instance_id] = BUSY_STATE_IDLE;
+                busy = false;
+            }
+        }
+    }
+    else
+    {
+        busy = false;
+    }
+    return busy;
+}
+
+
+/**
+ * @brief Function for enabling the IRQ for a given PWM instance.
+ *
+ * @param[in] p_instance  PWM instance.
+ */
+__STATIC_INLINE void pwm_irq_enable(app_pwm_t const * const p_instance)
+{
+    nrf_drv_timer_compare_int_enable(p_instance->p_timer, PWM_MAIN_CC_CHANNEL);
+}
+
+
+/**
+ * @brief Function for disabling the IRQ for a given PWM instance.
+ *
+ * @param[in] p_instance  PWM instance.
+ */
+__STATIC_INLINE void pwm_irq_disable(app_pwm_t const * const p_instance)
+{
+    nrf_drv_timer_compare_int_disable(p_instance->p_timer, PWM_MAIN_CC_CHANNEL);
+}
+
+#ifndef GPIOTE_SET_CLEAR_TASKS
+/**
+ * @brief Function for disabling PWM channel PPI.
+ *
+ * @param[in] p_instance  PWM instance.
+ */
+__STATIC_INLINE void pwm_channel_ppi_disable(app_pwm_t const * const p_instance, uint8_t channel)
+{
+    app_pwm_cb_t * p_cb = p_instance->p_cb;
+
+    nrf_drv_ppi_channel_disable(p_cb->channels_cb[channel].ppi_channels[0]);
+    nrf_drv_ppi_channel_disable(p_cb->channels_cb[channel].ppi_channels[1]);
+}
+
+
+/**
+ * @brief Function for disabling PWM PPI.
+ *
+ * @param[in] p_instance  PWM instance.
+ */
+__STATIC_INLINE void pwm_ppi_disable(app_pwm_t const * const p_instance)
+{
+    app_pwm_cb_t * p_cb = p_instance->p_cb;
+
+    nrf_drv_ppi_channel_disable(p_cb->ppi_channels[0]);
+    nrf_drv_ppi_channel_disable(p_cb->ppi_channels[1]);
+}
+#endif
+
+/**
+ * @brief This function is called on interrupt after duty set.
+ *
+ * @param[in] timer                 Timer used by PWM.
+ * @param[in] timer_instance_id     Timer index.
+ */
+void pwm_ready_tick(nrf_timer_event_t event_type, void * p_context)
+{
+    uint32_t timer_instance_id = (uint32_t)p_context;
+    uint8_t disable = 1;
+
+    for (uint8_t channel = 0; channel < APP_PWM_CHANNELS_PER_INSTANCE; ++channel)
+    {
+        if (m_pwm_ready_counter[timer_instance_id][channel])
+        {
+            --m_pwm_ready_counter[timer_instance_id][channel];
+            if (!m_pwm_ready_counter[timer_instance_id][channel])
+            {
+                app_pwm_cb_t * p_cb = m_instances[timer_instance_id]->p_cb;
+                p_cb->p_ready_callback(timer_instance_id);
+            }
+            else
+            {
+                disable = 0;
+            }
+        }
+    }
+
+    if (disable)
+    {
+        pwm_irq_disable(m_instances[timer_instance_id]);
+    }
+}
+
+
+/**
+ * @brief Function for resource de-allocation.
+ *
+ * @param[in] p_instance       PWM instance.
+ */
+//lint -e{650}
+static void pwm_dealloc(app_pwm_t const * const p_instance)
+{
+    app_pwm_cb_t * p_cb = p_instance->p_cb;
+
+#ifdef GPIOTE_SET_CLEAR_TASKS
+    nrf_drv_ppi_channel_free(p_cb->ppi_channel);
+#else
+    for (uint8_t i = 0; i < APP_PWM_REQUIRED_PPI_CHANNELS_PER_INSTANCE; ++i)
+    {
+        if (p_cb->ppi_channels[i] != (nrf_ppi_channel_t)(uint8_t)(UNALLOCATED))
+        {
+            nrf_drv_ppi_channel_free(p_cb->ppi_channels[i]);
+        }
+    }
+    if (p_cb->ppi_group != (nrf_ppi_channel_group_t)UNALLOCATED)
+    {
+        nrf_drv_ppi_group_free(p_cb->ppi_group);
+    }
+#endif //GPIOTE_SET_CLEAR_TASKS
+    for (uint8_t ch = 0; ch < APP_PWM_CHANNELS_PER_INSTANCE; ++ch)
+    {
+        for (uint8_t i = 0; i < APP_PWM_REQUIRED_PPI_CHANNELS_PER_CHANNEL; ++i)
+        {
+            if (p_cb->channels_cb[ch].ppi_channels[i] != (nrf_ppi_channel_t)UNALLOCATED)
+            {
+                nrf_drv_ppi_channel_free(p_cb->channels_cb[ch].ppi_channels[i]);
+                p_cb->channels_cb[ch].ppi_channels[i] = (nrf_ppi_channel_t)UNALLOCATED;
+            }
+        }
+        if (p_cb->channels_cb[ch].gpio_pin != UNALLOCATED)
+        {
+            nrf_drv_gpiote_out_uninit(p_cb->channels_cb[ch].gpio_pin);
+            p_cb->channels_cb[ch].gpio_pin = UNALLOCATED;
+        }
+        p_cb->channels_cb[ch].initialized = APP_PWM_CHANNEL_UNINITIALIZED;
+    }
+    nrf_drv_timer_uninit(p_instance->p_timer);
+    return;
+}
+
+#ifndef GPIOTE_SET_CLEAR_TASKS
+/**
+ * @brief PWM state transition from (0%, 100%) to 0% or 100%.
+ *
+ * @param[in] p_instance       PWM instance.
+ * @param[in] channel          PWM channel number.
+ * @param[in] ticks            Number of clock ticks.
+ */
+static void pwm_transition_n_to_0or100(app_pwm_t const * const p_instance,
+                                       uint8_t channel, uint16_t ticks)
+{
+    app_pwm_cb_t            * p_cb     = p_instance->p_cb;
+    app_pwm_channel_cb_t    * p_ch_cb  = &p_cb->channels_cb[channel];
+    nrf_ppi_channel_group_t   p_ppigrp = p_cb->ppi_group;
+
+    pwm_ppi_disable(p_instance);
+    nrf_drv_ppi_group_clear(p_ppigrp);
+    nrf_drv_ppi_channels_include_in_group(
+            nrf_drv_ppi_channel_to_mask(p_ch_cb->ppi_channels[0]) |
+            nrf_drv_ppi_channel_to_mask(p_ch_cb->ppi_channels[1]),
+            p_ppigrp);
+
+    if (!ticks)
+    {
+        nrf_drv_ppi_channel_assign(p_cb->ppi_channels[0],
+                    nrf_drv_timer_compare_event_address_get(p_instance->p_timer, channel),
+                    nrf_drv_ppi_task_addr_group_disable_get(p_ppigrp));
+        nrf_drv_timer_compare(p_instance->p_timer, (nrf_timer_cc_channel_t) PWM_SECONDARY_CC_CHANNEL, 0, false);
+        m_pwm_target_value[p_instance->p_timer->instance_id] =
+            nrf_drv_timer_capture_get(p_instance->p_timer, (nrf_timer_cc_channel_t) channel);
+        nrf_drv_ppi_channel_assign(p_cb->ppi_channels[1],
+                    nrf_drv_timer_compare_event_address_get(p_instance->p_timer, channel),
+                    nrf_drv_timer_capture_task_address_get(p_instance->p_timer, PWM_SECONDARY_CC_CHANNEL));
+    }
+    else
+    {
+        ticks = p_cb->period;
+        nrf_drv_ppi_channel_assign(p_cb->ppi_channels[0],
+                    nrf_drv_timer_compare_event_address_get(p_instance->p_timer, PWM_MAIN_CC_CHANNEL),
+                    nrf_drv_ppi_task_addr_group_disable_get(p_ppigrp));
+        // Set secondary CC channel to non-zero value:
+        nrf_drv_timer_compare(p_instance->p_timer, (nrf_timer_cc_channel_t) PWM_SECONDARY_CC_CHANNEL, 1, false);
+        m_pwm_target_value[p_instance->p_timer->instance_id] = 0;
+        // The captured value will be equal to 0, because timer clear on main PWM CC channel compare is enabled.
+        nrf_drv_ppi_channel_assign(p_cb->ppi_channels[1],
+                    nrf_drv_timer_compare_event_address_get(p_instance->p_timer, PWM_MAIN_CC_CHANNEL),
+                    nrf_drv_timer_capture_task_address_get(p_instance->p_timer, PWM_SECONDARY_CC_CHANNEL));
+    }
+
+    nrf_drv_ppi_channel_enable(p_cb->ppi_channels[0]);
+    nrf_drv_ppi_channel_enable(p_cb->ppi_channels[1]);
+
+    p_ch_cb->pulsewidth = ticks;
+    m_pwm_busy[p_instance->p_timer->instance_id] = PWM_SECONDARY_CC_CHANNEL;
+}
+
+
+/**
+ * @brief PWM state transition from (0%, 100%) to (0%, 100%).
+ *
+ * @param[in] p_instance       PWM instance.
+ * @param[in] channel          PWM channel number.
+ * @param[in] ticks            Number of clock ticks.
+ */
+static void pwm_transition_n_to_m(app_pwm_t const * const p_instance,
+                                  uint8_t channel, uint16_t ticks)
+{
+    app_pwm_cb_t            * p_cb     = p_instance->p_cb;
+    app_pwm_channel_cb_t    * p_ch_cb  = &p_cb->channels_cb[channel];
+    nrf_ppi_channel_group_t   p_ppigrp = p_cb->ppi_group;
+
+    pwm_ppi_disable(p_instance);
+    nrf_drv_ppi_group_clear(p_ppigrp);
+    nrf_drv_ppi_channels_include_in_group(
+        nrf_drv_ppi_channel_to_mask(p_cb->ppi_channels[0]) |
+        nrf_drv_ppi_channel_to_mask(p_cb->ppi_channels[1]),
+        p_ppigrp);
+
+    nrf_drv_ppi_channel_assign(p_cb->ppi_channels[0],
+                nrf_drv_timer_compare_event_address_get(p_instance->p_timer, PWM_SECONDARY_CC_CHANNEL),
+                nrf_drv_timer_capture_task_address_get(p_instance->p_timer, channel));
+
+
+    if (ticks + ((nrf_timer_frequency_get(p_instance->p_timer->p_reg) == NRF_TIMER_FREQ_16MHz) ? 1 : 0)
+        < p_ch_cb->pulsewidth)
+    {
+        // For lower value, we need one more transition. Timer task delay is included.
+        // If prescaler is disabled, one tick must be added because of 1 PCLK16M clock cycle delay.
+        nrf_drv_ppi_channel_assign(p_cb->ppi_channels[1],
+                nrf_drv_timer_compare_event_address_get(p_instance->p_timer, PWM_SECONDARY_CC_CHANNEL),
+                nrf_drv_gpiote_out_task_addr_get(p_ch_cb->gpio_pin));
+    }
+    else
+    {
+        nrf_drv_ppi_channel_remove_from_group(p_cb->ppi_channels[1], p_ppigrp);
+    }
+    p_ch_cb->pulsewidth = ticks;
+    nrf_drv_timer_compare(p_instance->p_timer, (nrf_timer_cc_channel_t) PWM_SECONDARY_CC_CHANNEL, ticks, false);
+    nrf_drv_ppi_group_enable(p_ppigrp);
+
+    m_pwm_target_value[p_instance->p_timer->instance_id] = ticks;
+    m_pwm_busy[p_instance->p_timer->instance_id] = channel;
+}
+
+
+/**
+ * @brief PWM state transition from 0% or 100% to (0%, 100%).
+ *
+ * @param[in] p_instance       PWM instance.
+ * @param[in] channel          PWM channel number.
+ * @param[in] ticks            Number of clock ticks.
+ */
+static void pwm_transition_0or100_to_n(app_pwm_t const * const p_instance,
+                                       uint8_t channel, uint16_t ticks)
+{
+    app_pwm_cb_t            * p_cb      = p_instance->p_cb;
+    app_pwm_channel_cb_t    * p_ch_cb   = &p_cb->channels_cb[channel];
+    nrf_ppi_channel_group_t   p_ppigrp  = p_cb->ppi_group;
+    nrf_timer_cc_channel_t    pwm_ch_cc = (nrf_timer_cc_channel_t)(channel);
+
+    pwm_ppi_disable(p_instance);
+    pwm_channel_ppi_disable(p_instance, channel);
+
+    nrf_drv_timer_compare(p_instance->p_timer, pwm_ch_cc, ticks, false);
+    nrf_drv_ppi_group_clear(p_ppigrp);
+    nrf_drv_ppi_channels_include_in_group(
+        nrf_drv_ppi_channel_to_mask(p_ch_cb->ppi_channels[0])|
+        nrf_drv_ppi_channel_to_mask(p_ch_cb->ppi_channels[1]),
+        p_ppigrp);
+
+    if (!p_ch_cb->pulsewidth)
+    {
+        // Channel is at 0%.
+        nrf_drv_ppi_channel_assign(p_cb->ppi_channels[0],
+                    nrf_drv_timer_compare_event_address_get(p_instance->p_timer, channel),
+                    nrf_drv_ppi_task_addr_group_enable_get(p_ppigrp));
+        nrf_drv_timer_compare(p_instance->p_timer, (nrf_timer_cc_channel_t) PWM_SECONDARY_CC_CHANNEL, 0, false);
+        m_pwm_target_value[p_instance->p_timer->instance_id] =
+            nrf_drv_timer_capture_get(p_instance->p_timer, (nrf_timer_cc_channel_t) channel);
+        nrf_drv_ppi_channel_assign(p_cb->ppi_channels[1],
+                    nrf_drv_timer_compare_event_address_get(p_instance->p_timer, channel),
+                    nrf_drv_timer_capture_task_address_get(p_instance->p_timer, PWM_SECONDARY_CC_CHANNEL));
+
+    }
+    else
+    {
+        // Channel is at 100%.
+        nrf_drv_ppi_channel_assign(p_cb->ppi_channels[0],
+                    nrf_drv_timer_compare_event_address_get(p_instance->p_timer, PWM_MAIN_CC_CHANNEL),
+                    nrf_drv_ppi_task_addr_group_enable_get(p_ppigrp));
+        // Set secondary CC channel to non-zero value:
+        nrf_drv_timer_compare(p_instance->p_timer, (nrf_timer_cc_channel_t) PWM_SECONDARY_CC_CHANNEL, 1, false);
+        m_pwm_target_value[p_instance->p_timer->instance_id] = 0;
+        // The captured value will be equal to 0, because timer clear on main PWM CC channel compare is enabled.
+        nrf_drv_ppi_channel_assign(p_cb->ppi_channels[1],
+                    nrf_drv_timer_compare_event_address_get(p_instance->p_timer, PWM_MAIN_CC_CHANNEL),
+                    nrf_drv_timer_capture_task_address_get(p_instance->p_timer, PWM_SECONDARY_CC_CHANNEL));
+    }
+    nrf_drv_ppi_channel_enable(p_cb->ppi_channels[0]);
+    nrf_drv_ppi_channel_enable(p_cb->ppi_channels[1]);
+
+    p_ch_cb->pulsewidth = ticks;
+    m_pwm_busy[p_instance->p_timer->instance_id] = PWM_SECONDARY_CC_CHANNEL;
+}
+
+
+/**
+ * @brief PWM state transition from 0% or 100% to 0% or 100%.
+ *
+ * @param[in] p_instance       PWM instance.
+ * @param[in] channel          PWM channel number.
+ * @param[in] ticks            Number of clock ticks.
+ */
+static void pwm_transition_0or100_to_0or100(app_pwm_t const * const p_instance,
+                                            uint8_t channel, uint16_t ticks)
+{
+    app_pwm_cb_t         * p_cb      = p_instance->p_cb;
+    app_pwm_channel_cb_t * p_ch_cb   = &p_cb->channels_cb[channel];
+    nrf_timer_cc_channel_t pwm_ch_cc = (nrf_timer_cc_channel_t)(channel);
+
+    pwm_ppi_disable(p_instance);
+    pwm_channel_ppi_disable(p_instance, channel);
+    if (!ticks)
+    {
+        // Set to 0%.
+        nrf_drv_gpiote_out_task_force(p_ch_cb->gpio_pin, POLARITY_INACTIVE(p_instance, channel));
+    }
+    else if (ticks >= p_cb->period)
+    {
+        // Set to 100%.
+        ticks = p_cb->period;
+        nrf_drv_gpiote_out_task_force(p_ch_cb->gpio_pin, POLARITY_ACTIVE(p_instance, channel));
+    }
+    nrf_drv_timer_compare(p_instance->p_timer, pwm_ch_cc, ticks, false);
+    p_ch_cb->pulsewidth = ticks;
+
+    m_pwm_busy[p_instance->p_timer->instance_id] = BUSY_STATE_IDLE;
+    return;
+}
+
+static void pwm_transition(app_pwm_t const * const p_instance,
+                                       uint8_t channel, uint16_t ticks)
+{
+    app_pwm_cb_t         * p_cb      = p_instance->p_cb;
+    app_pwm_channel_cb_t * p_ch_cb = &p_instance->p_cb->channels_cb[channel];
+
+    // Pulse width change sequence:
+    if (!p_ch_cb->pulsewidth || p_ch_cb->pulsewidth >= p_cb->period)
+    {
+        // Channel is disabled (0%) or at 100%.
+        if (!ticks || ticks >= p_cb->period)
+        {
+            // Set to 0 or 100%.
+            pwm_transition_0or100_to_0or100(p_instance, channel, ticks);
+        }
+        else
+        {
+            // Other value.
+            pwm_transition_0or100_to_n(p_instance, channel, ticks);
+        }
+    }
+    else
+    {
+        // Channel is at other value.
+        if (!ticks || ticks >= p_cb->period)
+        {
+            // Disable channel (set to 0%) or set to 100%.
+            pwm_transition_n_to_0or100(p_instance, channel, ticks);
+        }
+        else
+        {
+            // Set to any other value.
+            pwm_transition_n_to_m(p_instance, channel, ticks);
+        }
+    }
+}
+#else //GPIOTE_SET_CLEAR_TASKS
+/**
+ * @brief PWM state transition.
+ *
+ * @param[in] p_instance       PWM instance.
+ * @param[in] channel          PWM channel number.
+ * @param[in] ticks            Number of clock ticks.
+ */
+static void pwm_transition(app_pwm_t const * const p_instance,
+                                  uint8_t channel, uint16_t ticks)
+{
+    app_pwm_cb_t            * p_cb     = p_instance->p_cb;
+    app_pwm_channel_cb_t    * p_ch_cb  = &p_cb->channels_cb[channel];
+    nrf_timer_cc_channel_t    pwm_ch_cc = (nrf_timer_cc_channel_t)(channel);
+
+    nrf_drv_ppi_channel_disable(p_cb->ppi_channel);
+
+    if (!ticks)
+    {
+        nrf_drv_ppi_channel_disable(p_ch_cb->ppi_channels[1]);
+        nrf_drv_ppi_channel_enable(p_ch_cb->ppi_channels[0]);
+        m_pwm_busy[p_instance->p_timer->instance_id] = BUSY_STATE_IDLE;
+    }
+    else if (ticks >= p_cb->period)
+    {
+        ticks = p_cb->period;
+        nrf_drv_ppi_channel_disable(p_ch_cb->ppi_channels[0]);
+        nrf_drv_ppi_channel_enable(p_ch_cb->ppi_channels[1]);
+        m_pwm_busy[p_instance->p_timer->instance_id] = BUSY_STATE_IDLE;
+    }
+    else
+    {
+        // Set to any other value.
+        if ((p_ch_cb->pulsewidth != p_cb->period) && (p_ch_cb->pulsewidth != 0) && (ticks < p_ch_cb->pulsewidth))
+        {
+            nrf_drv_timer_compare(p_instance->p_timer, (nrf_timer_cc_channel_t)PWM_SECONDARY_CC_CHANNEL, p_ch_cb->pulsewidth, false);
+            nrf_drv_ppi_channel_assign(p_cb->ppi_channel,
+                                       nrf_drv_timer_compare_event_address_get(p_instance->p_timer, (nrf_timer_cc_channel_t)PWM_SECONDARY_CC_CHANNEL),
+                                       p_ch_cb->polarity ? nrf_drv_gpiote_clr_task_addr_get(p_ch_cb->gpio_pin) : nrf_drv_gpiote_set_task_addr_get(p_ch_cb->gpio_pin));
+            nrf_drv_ppi_channel_enable(p_cb->ppi_channel);
+            m_pwm_busy[p_instance->p_timer->instance_id] = channel;
+            m_pwm_target_value[p_instance->p_timer->instance_id] = ticks;
+        }
+        else
+        {
+            m_pwm_busy[p_instance->p_timer->instance_id] = BUSY_STATE_IDLE;
+        }
+
+        nrf_drv_timer_compare(p_instance->p_timer, pwm_ch_cc, ticks, false);
+
+        nrf_drv_ppi_channel_enable(p_ch_cb->ppi_channels[0]);
+        nrf_drv_ppi_channel_enable(p_ch_cb->ppi_channels[1]);
+    }
+    p_ch_cb->pulsewidth = ticks;
+    return;
+}
+#endif //GPIOTE_SET_CLEAR_TASKS
+
+ret_code_t app_pwm_channel_duty_ticks_set(app_pwm_t const * const p_instance,
+                                          uint8_t           channel,
+                                          uint16_t          ticks)
+{
+    app_pwm_cb_t         * p_cb    = p_instance->p_cb;
+    app_pwm_channel_cb_t * p_ch_cb = &p_cb->channels_cb[channel];
+
+    ASSERT(channel < APP_PWM_CHANNELS_PER_INSTANCE);
+    ASSERT(p_ch_cb->initialized == APP_PWM_CHANNEL_INITIALIZED);
+
+    if (p_cb->state != NRF_DRV_STATE_POWERED_ON)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+    if (ticks == p_ch_cb->pulsewidth)
+    {
+        if (p_cb->p_ready_callback)
+        {
+            p_cb->p_ready_callback(p_instance->p_timer->instance_id);
+        }
+        return NRF_SUCCESS;     // No action required.
+    }
+    if (app_pwm_busy_check(p_instance))
+    {
+        return NRF_ERROR_BUSY;  // PPI channels for synchronization are still in use.
+    }
+
+    m_pwm_busy[p_instance->p_timer->instance_id] = BUSY_STATE_CHANGING;
+
+    // Set new value.
+
+    pwm_transition(p_instance, channel, ticks);
+
+    if (p_instance->p_cb->p_ready_callback)
+    {
+        //PWM ready interrupt handler will be called after one full period.
+        m_pwm_ready_counter[p_instance->p_timer->instance_id][channel] = 2;
+        pwm_irq_enable(p_instance);
+    }
+    return NRF_SUCCESS;
+}
+
+uint16_t app_pwm_channel_duty_ticks_get(app_pwm_t const * const p_instance, uint8_t channel)
+{
+    app_pwm_cb_t         * p_cb      = p_instance->p_cb;
+    app_pwm_channel_cb_t * p_ch_cb   = &p_cb->channels_cb[channel];
+
+    return p_ch_cb->pulsewidth;
+}
+
+uint16_t app_pwm_cycle_ticks_get(app_pwm_t const * const p_instance)
+{
+    app_pwm_cb_t * p_cb = p_instance->p_cb;
+
+    return (uint16_t)p_cb->period;
+}
+
+ret_code_t app_pwm_channel_duty_set(app_pwm_t const * const p_instance,
+                                  uint8_t channel, app_pwm_duty_t duty)
+{
+    uint32_t ticks = ((uint32_t)app_pwm_cycle_ticks_get(p_instance) * (uint32_t)duty) / 100UL;
+    return app_pwm_channel_duty_ticks_set(p_instance, channel, ticks);
+}
+
+
+app_pwm_duty_t app_pwm_channel_duty_get(app_pwm_t const * const p_instance, uint8_t channel)
+{
+    uint32_t value = ((uint32_t)app_pwm_channel_duty_ticks_get(p_instance, channel) * 100UL) \
+                     / (uint32_t)app_pwm_cycle_ticks_get(p_instance);
+
+    return (app_pwm_duty_t)value;
+}
+
+
+/**
+ * @brief Function for initializing the PWM channel.
+ *
+ * @param[in] p_instance       PWM instance.
+ * @param[in] channel          Channel number.
+ * @param[in] pin              GPIO pin number.
+ *
+ * @retval    NRF_SUCCESS If initialization was successful.
+ * @retval    NRF_ERROR_NO_MEM If there were not enough free resources.
+ * @retval    NRF_ERROR_INVALID_STATE If the timer is already in use or initialization failed.
+ */
+static ret_code_t app_pwm_channel_init(app_pwm_t const * const p_instance, uint8_t channel,
+                                     uint32_t pin, app_pwm_polarity_t polarity)
+{
+    ASSERT(channel < APP_PWM_CHANNELS_PER_INSTANCE);
+    app_pwm_cb_t * p_cb = p_instance->p_cb;
+    app_pwm_channel_cb_t * p_channel_cb = &p_cb->channels_cb[channel];
+
+    if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    p_channel_cb->pulsewidth = 0;
+    p_channel_cb->polarity   = polarity;
+    ret_code_t err_code;
+
+    /* GPIOTE setup: */
+    nrf_drv_gpiote_out_config_t out_cfg = GPIOTE_CONFIG_OUT_TASK_TOGGLE( POLARITY_INACTIVE(p_instance, channel) );
+    err_code = nrf_drv_gpiote_out_init((nrf_drv_gpiote_pin_t)pin,&out_cfg);
+    if (err_code != NRF_SUCCESS)
+    {
+        return NRF_ERROR_NO_MEM;
+    }
+    p_cb->channels_cb[channel].gpio_pin = pin;
+
+    // Set output to inactive state.
+    if (polarity)
+    {
+        nrf_gpio_pin_clear(pin);
+    }
+    else
+    {
+        nrf_gpio_pin_set(pin);
+    }
+
+    /* PPI setup: */
+    for (uint8_t i = 0; i < APP_PWM_REQUIRED_PPI_CHANNELS_PER_CHANNEL; ++i)
+    {
+        if (nrf_drv_ppi_channel_alloc(&p_channel_cb->ppi_channels[i]) != NRF_SUCCESS)
+        {
+            return NRF_ERROR_NO_MEM; // Resource de-allocation is done by callee.
+        }
+    }
+
+    nrf_drv_ppi_channel_disable(p_channel_cb->ppi_channels[0]);
+    nrf_drv_ppi_channel_disable(p_channel_cb->ppi_channels[1]);
+
+#ifdef GPIOTE_SET_CLEAR_TASKS
+    uint32_t deactivate_task_addr   = polarity ? nrf_drv_gpiote_clr_task_addr_get(p_channel_cb->gpio_pin) : nrf_drv_gpiote_set_task_addr_get(p_channel_cb->gpio_pin);
+    uint32_t activate_task_addr     = polarity ? nrf_drv_gpiote_set_task_addr_get(p_channel_cb->gpio_pin) : nrf_drv_gpiote_clr_task_addr_get(p_channel_cb->gpio_pin);
+
+    nrf_drv_ppi_channel_assign(p_channel_cb->ppi_channels[0],
+                               nrf_drv_timer_compare_event_address_get(p_instance->p_timer, channel),
+                               deactivate_task_addr);
+    nrf_drv_ppi_channel_assign(p_channel_cb->ppi_channels[1],
+                               nrf_drv_timer_compare_event_address_get(p_instance->p_timer, PWM_MAIN_CC_CHANNEL),
+                               activate_task_addr);
+#else //GPIOTE_SET_CLEAR_TASKS
+    nrf_drv_ppi_channel_assign(p_channel_cb->ppi_channels[0],
+                               nrf_drv_timer_compare_event_address_get(p_instance->p_timer, channel),
+                               nrf_drv_gpiote_out_task_addr_get(p_channel_cb->gpio_pin));
+    nrf_drv_ppi_channel_assign(p_channel_cb->ppi_channels[1],
+                               nrf_drv_timer_compare_event_address_get(p_instance->p_timer, PWM_MAIN_CC_CHANNEL),
+                               nrf_drv_gpiote_out_task_addr_get(p_channel_cb->gpio_pin));
+#endif //GPIOTE_SET_CLEAR_TASKS
+    p_channel_cb->initialized = APP_PWM_CHANNEL_INITIALIZED;
+    m_pwm_ready_counter[p_instance->p_timer->instance_id][channel] = 0;
+
+    return NRF_SUCCESS;
+}
+
+
+/**
+ * @brief Function for calculating target timer frequency, which will allow to set given period length.
+ *
+ * @param[in] period_us       Desired period in microseconds.
+ *
+ * @retval    Timer frequency.
+ */
+__STATIC_INLINE nrf_timer_frequency_t pwm_calculate_timer_frequency(uint32_t period_us)
+{
+    uint32_t f   = (uint32_t) NRF_TIMER_FREQ_16MHz;
+    uint32_t min = (uint32_t) NRF_TIMER_FREQ_31250Hz;
+
+    while ((period_us > TIMER_MAX_PULSEWIDTH_US_ON_16M) && (f < min))
+    {
+        period_us >>= 1;
+        ++f;
+    }
+
+#ifdef GPIOTE_SET_CLEAR_TASKS
+    if ((m_use_ppi_delay_workaround) && (f == (uint32_t) NRF_TIMER_FREQ_16MHz))
+    {
+        f = (uint32_t) NRF_TIMER_FREQ_8MHz;
+    }
+#endif // GPIOTE_SET_CLEAR_TASKS
+
+    return (nrf_timer_frequency_t) f;
+}
+
+
+ret_code_t app_pwm_init(app_pwm_t const * const p_instance, app_pwm_config_t const * const p_config,
+                        app_pwm_callback_t p_ready_callback)
+{
+    ASSERT(p_instance);
+
+    if (!p_config)
+    {
+        return NRF_ERROR_INVALID_DATA;
+    }
+
+    app_pwm_cb_t * p_cb = p_instance->p_cb;
+
+    if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    uint32_t err_code = nrf_drv_ppi_init();
+    if ((err_code != NRF_SUCCESS) && (err_code != NRF_ERROR_MODULE_ALREADY_INITIALIZED))
+    {
+        return NRF_ERROR_NO_MEM;
+    }
+
+
+    if (!nrf_drv_gpiote_is_init())
+    {
+        err_code = nrf_drv_gpiote_init();
+        if (err_code != NRF_SUCCESS)
+        {
+            return NRF_ERROR_INTERNAL;
+        }
+    }
+
+#ifdef GPIOTE_SET_CLEAR_TASKS
+    if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
+    {
+        m_use_ppi_delay_workaround = false;
+    }
+    else
+    {
+        m_use_ppi_delay_workaround = true;
+    }
+#endif
+
+    // Innitialize resource status:
+#ifdef GPIOTE_SET_CLEAR_TASKS
+    p_cb->ppi_channel = (nrf_ppi_channel_t)UNALLOCATED;
+#else
+    p_cb->ppi_channels[0] = (nrf_ppi_channel_t)UNALLOCATED;
+    p_cb->ppi_channels[1] = (nrf_ppi_channel_t)UNALLOCATED;
+    p_cb->ppi_group       = (nrf_ppi_channel_group_t)UNALLOCATED;
+#endif //GPIOTE_SET_CLEAR_TASKS
+
+    for (uint8_t i = 0; i < APP_PWM_CHANNELS_PER_INSTANCE; ++i)
+    {
+        p_cb->channels_cb[i].initialized     = APP_PWM_CHANNEL_UNINITIALIZED;
+        p_cb->channels_cb[i].ppi_channels[0] = (nrf_ppi_channel_t)UNALLOCATED;
+        p_cb->channels_cb[i].ppi_channels[1] = (nrf_ppi_channel_t)UNALLOCATED;
+        p_cb->channels_cb[i].gpio_pin        = UNALLOCATED;
+    }
+
+    // Allocate PPI channels and groups:
+
+#ifdef GPIOTE_SET_CLEAR_TASKS
+    if (nrf_drv_ppi_channel_alloc(&p_cb->ppi_channel) != NRF_SUCCESS)
+    {
+        pwm_dealloc(p_instance);
+        return NRF_ERROR_NO_MEM;
+    }
+#else //GPIOTE_SET_CLEAR_TASKS
+    if (nrf_drv_ppi_group_alloc(&p_cb->ppi_group) != NRF_SUCCESS)
+    {
+        pwm_dealloc(p_instance);
+        return NRF_ERROR_NO_MEM;
+    }
+
+    for (uint8_t i = 0; i < APP_PWM_REQUIRED_PPI_CHANNELS_PER_INSTANCE; ++i)
+    {
+        if (nrf_drv_ppi_channel_alloc(&p_cb->ppi_channels[i]) != NRF_SUCCESS)
+        {
+            pwm_dealloc(p_instance);
+            return NRF_ERROR_NO_MEM;
+        }
+    }
+#endif //GPIOTE_SET_CLEAR_TASKS
+    // Initialize channels:
+    for (uint8_t i = 0; i < APP_PWM_CHANNELS_PER_INSTANCE; ++i)
+    {
+        if (p_config->pins[i] != APP_PWM_NOPIN)
+        {
+            err_code = app_pwm_channel_init(p_instance, i, p_config->pins[i], p_config->pin_polarity[i]);
+            if (err_code != NRF_SUCCESS)
+            {
+                pwm_dealloc(p_instance);
+                return err_code;
+            }
+            app_pwm_channel_duty_ticks_set(p_instance, i, 0);
+        }
+    }
+
+    // Initialize timer:
+    nrf_timer_frequency_t  timer_freq = pwm_calculate_timer_frequency(p_config->period_us);
+    nrf_drv_timer_config_t timer_cfg  = {
+        .frequency          = timer_freq,
+        .mode               = NRF_TIMER_MODE_TIMER,
+        .bit_width          = NRF_TIMER_BIT_WIDTH_16,
+        .interrupt_priority = APP_IRQ_PRIORITY_LOWEST,
+        .p_context          = (void *) (uint32_t) p_instance->p_timer->instance_id
+    };
+    err_code = nrf_drv_timer_init(p_instance->p_timer, &timer_cfg,
+                                  pwm_ready_tick);
+    if (err_code != NRF_SUCCESS)
+    {
+        pwm_dealloc(p_instance);
+        return err_code;
+    }
+
+    uint32_t ticks = nrf_drv_timer_us_to_ticks(p_instance->p_timer, p_config->period_us);
+    p_cb->period = ticks;
+    nrf_drv_timer_clear(p_instance->p_timer);
+    nrf_drv_timer_extended_compare(p_instance->p_timer, (nrf_timer_cc_channel_t) PWM_MAIN_CC_CHANNEL,
+                                    ticks, NRF_TIMER_SHORT_COMPARE2_CLEAR_MASK, true);
+    nrf_drv_timer_compare_int_disable(p_instance->p_timer, PWM_MAIN_CC_CHANNEL);
+
+    p_cb->p_ready_callback = p_ready_callback;
+    m_instances[p_instance->p_timer->instance_id] = p_instance;
+    m_pwm_busy[p_instance->p_timer->instance_id] = BUSY_STATE_IDLE;
+    p_cb->state = NRF_DRV_STATE_INITIALIZED;
+
+    return NRF_SUCCESS;
+}
+
+
+void app_pwm_enable(app_pwm_t const * const p_instance)
+{
+    app_pwm_cb_t * p_cb = p_instance->p_cb;
+
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+
+    for (uint32_t channel = 0; channel < APP_PWM_CHANNELS_PER_INSTANCE; ++channel)
+    {
+        app_pwm_channel_cb_t * p_ch_cb = &p_cb->channels_cb[channel];
+        m_pwm_ready_counter[p_instance->p_timer->instance_id][channel] = 0;
+        if (p_ch_cb->initialized)
+        {
+            nrf_drv_gpiote_out_task_force(p_ch_cb->gpio_pin, POLARITY_INACTIVE(p_instance, channel));
+            nrf_drv_gpiote_out_task_enable(p_ch_cb->gpio_pin);
+            p_ch_cb->pulsewidth = 0;
+        }
+    }
+    m_pwm_busy[p_instance->p_timer->instance_id] = BUSY_STATE_IDLE;
+
+    pan73_workaround(p_instance->p_timer->p_reg, true);
+
+    nrf_drv_timer_clear(p_instance->p_timer);
+    nrf_drv_timer_enable(p_instance->p_timer);
+
+    p_cb->state = NRF_DRV_STATE_POWERED_ON;
+    return;
+}
+
+
+void app_pwm_disable(app_pwm_t const * const p_instance)
+{
+    app_pwm_cb_t * p_cb = p_instance->p_cb;
+
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+
+    nrf_drv_timer_disable(p_instance->p_timer);
+    pwm_irq_disable(p_instance);
+
+#ifdef GPIOTE_SET_CLEAR_TASKS
+    nrf_drv_ppi_channel_disable(p_cb->ppi_channel);
+#else
+    for (uint8_t ppi_channel = 0; ppi_channel < APP_PWM_REQUIRED_PPI_CHANNELS_PER_INSTANCE; ++ppi_channel)
+    {
+        nrf_drv_ppi_channel_disable(p_cb->ppi_channels[ppi_channel]);
+    }
+#endif //GPIOTE_SET_CLEAR_TASKS
+
+    for (uint8_t channel = 0; channel < APP_PWM_CHANNELS_PER_INSTANCE; ++channel)
+    {
+        app_pwm_channel_cb_t * p_ch_cb = &p_cb->channels_cb[channel];
+        if (p_ch_cb->initialized)
+        {
+            uint8_t polarity = POLARITY_INACTIVE(p_instance, channel);
+            if (polarity)
+            {
+                nrf_gpio_pin_set(p_ch_cb->gpio_pin);
+            }
+            else
+            {
+                nrf_gpio_pin_clear(p_ch_cb->gpio_pin);
+            }
+            nrf_drv_gpiote_out_task_disable(p_ch_cb->gpio_pin);
+            nrf_drv_ppi_channel_disable(p_ch_cb->ppi_channels[0]);
+            nrf_drv_ppi_channel_disable(p_ch_cb->ppi_channels[1]);
+        }
+    }
+
+    pan73_workaround(p_instance->p_timer->p_reg, false);
+
+    p_cb->state = NRF_DRV_STATE_INITIALIZED;
+    return;
+}
+
+
+ret_code_t app_pwm_uninit(app_pwm_t const * const p_instance)
+{
+    app_pwm_cb_t * p_cb = p_instance->p_cb;
+
+    if (p_cb->state == NRF_DRV_STATE_POWERED_ON)
+    {
+        app_pwm_disable(p_instance);
+    }
+    else if (p_cb->state == NRF_DRV_STATE_UNINITIALIZED)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+    pwm_dealloc(p_instance);
+
+    p_cb->state = NRF_DRV_STATE_UNINITIALIZED;
+    return NRF_SUCCESS;
+}
+
+
+//lint -restore
+#endif //NRF_MODULE_ENABLED(APP_PWM)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/pwm/app_pwm.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,338 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup app_pwm Pulse-width modulation (PWM)
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Module for generating a pulse-width modulated output signal.
+ *
+ * @details This module provides a PWM implementation using timers, GPIOTE, and PPI.
+ *
+ * Resource usage:
+ * - 2 PPI channels per instance + 2 PPI channels per PWM channel.
+ * - 1 PPI group per instance.
+ * - 1 GPIOTE channel per PWM channel.
+ *
+ * For example, a PWM instance with two channels will consume 2 + 4 PPI channels, 1 PPI group, and 2 GPIOTE channels.
+ *
+ * The maximum number of PWM channels per instance is 2.
+ */
+
+#ifndef APP_PWM_H__
+#define APP_PWM_H__
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "nrf_drv_timer.h"
+#include "nrf_drv_common.h"
+#include "nrf_drv_ppi.h"
+#include "nrf_peripherals.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(GPIOTE_FEATURE_SET_PRESENT) && defined(GPIOTE_FEATURE_CLR_PRESENT)
+#define GPIOTE_SET_CLEAR_TASKS
+#endif
+
+#define APP_PWM_NOPIN                 0xFFFFFFFF
+
+/** @brief Number of channels for one timer instance (fixed to 2 due to timer properties).*/
+#define APP_PWM_CHANNELS_PER_INSTANCE 2
+
+/**@brief Macro for creating a PWM instance. */
+#define APP_PWM_INSTANCE(name, num)                                           \
+    const nrf_drv_timer_t m_pwm_##name##_timer = NRF_DRV_TIMER_INSTANCE(num); \
+    app_pwm_cb_t m_pwm_##name##_cb;                                           \
+    /*lint -e{545}*/                                                          \
+    const app_pwm_t name = {                                                  \
+        .p_cb    = &m_pwm_##name##_cb,                                        \
+        .p_timer = &m_pwm_##name##_timer,                                     \
+    }
+
+
+/**@brief PWM instance default configuration (1 channel). */
+#define APP_PWM_DEFAULT_CONFIG_1CH(period_in_us, pin)                                  \
+    {                                                                                  \
+        .pins            = {pin, APP_PWM_NOPIN},                                       \
+        .pin_polarity    = {APP_PWM_POLARITY_ACTIVE_LOW, APP_PWM_POLARITY_ACTIVE_LOW}, \
+        .num_of_channels = 1,                                                          \
+        .period_us       = period_in_us                                                \
+    }
+
+/**@brief PWM instance default configuration (2 channels). */
+#define APP_PWM_DEFAULT_CONFIG_2CH(period_in_us, pin0, pin1)                           \
+    {                                                                                  \
+        .pins            = {pin0, pin1},                                               \
+        .pin_polarity    = {APP_PWM_POLARITY_ACTIVE_LOW, APP_PWM_POLARITY_ACTIVE_LOW}, \
+        .num_of_channels = 2,                                                          \
+        .period_us       = period_in_us                                                \
+    }
+
+typedef uint16_t app_pwm_duty_t;
+
+/**
+ * @brief PWM callback that is executed when a PWM duty change has been completed.
+ *
+ * @param[in] pwm_id  PWM instance ID.
+ */
+typedef void (* app_pwm_callback_t)(uint32_t);
+
+/**
+ * @brief Channel polarity.
+ */
+typedef enum
+{
+    APP_PWM_POLARITY_ACTIVE_LOW  = 0,
+    APP_PWM_POLARITY_ACTIVE_HIGH = 1
+} app_pwm_polarity_t;
+
+/**@brief PWM configuration structure used for initialization. */
+typedef struct
+{
+    uint32_t           pins[APP_PWM_CHANNELS_PER_INSTANCE];         //!< Pins configured as PWM output.
+    app_pwm_polarity_t pin_polarity[APP_PWM_CHANNELS_PER_INSTANCE]; //!< Polarity of active state on pin.
+    uint32_t           num_of_channels;                             //!< Number of channels that can be used.
+    uint32_t           period_us;                                   //!< PWM signal output period to configure (in microseconds).
+} app_pwm_config_t;
+
+
+/**
+ * @cond (NODOX)
+ * @defgroup app_pwm_internal Auxiliary internal types declarations
+ * @{
+ * @internal
+ *
+ * @brief Module for internal usage inside the library only
+ *
+ * There are some definitions that must be included in the header file because
+ * of the way the library is set up. In this way, the are accessible to the user.
+ * However, any functions and variables defined here may change at any time
+ * without a warning, so you should not access them directly.
+ */
+
+    /**
+     * @brief PWM channel instance
+     *
+     * This structure holds all data needed by a single PWM channel.
+     */
+    typedef struct
+    {
+        uint32_t           gpio_pin;        //!< Pin that is used by this PWM channel.
+        uint32_t           pulsewidth;      //!< The copy of duty currently set (in ticks).
+        nrf_ppi_channel_t  ppi_channels[2]; //!< PPI channels used by the PWM channel to clear and set the output.
+        app_pwm_polarity_t polarity;        //!< The active state of the pin.
+        uint8_t            initialized;     //!< The internal information if the selected channel was initialized.
+    } app_pwm_channel_cb_t;
+
+    /**
+     * @brief Variable part of PWM instance
+     *
+     * This structure holds instance data that may change.
+     */
+    typedef struct
+    {
+        app_pwm_channel_cb_t    channels_cb[APP_PWM_CHANNELS_PER_INSTANCE]; //!< Channels data
+        uint32_t                period;                                     //!< Selected period in ticks
+        app_pwm_callback_t      p_ready_callback;                           //!< Callback function called on PWM readiness
+#ifdef GPIOTE_SET_CLEAR_TASKS
+        nrf_ppi_channel_t       ppi_channel;                               //!< PPI channel used temporary while changing duty
+#else
+        nrf_ppi_channel_t       ppi_channels[2];                            //!< PPI channels used temporary while changing duty
+        nrf_ppi_channel_group_t ppi_group;                                  //!< PPI group used to synchronize changes on channels
+#endif
+        nrf_drv_state_t         state;                                      //!< Current driver status
+    } app_pwm_cb_t;
+/** @}
+ * @endcond
+ */
+
+
+/**@brief PWM instance structure. */
+typedef struct
+{
+    app_pwm_cb_t *p_cb;                    //!< Pointer to control block internals.
+    nrf_drv_timer_t const * const p_timer; //!< Timer used by this PWM instance.
+} app_pwm_t;
+
+/**
+ * @brief Function for checking if the PWM instance is busy updating the duty cycle.
+ *
+ * @param[in] p_instance  PWM instance.
+ *
+ * @retval True  If the PWM instance is ready for duty cycle changes.
+ * @retval False If a change operation is in progress.
+ */
+bool app_pwm_busy_check(app_pwm_t const * const p_instance);
+
+/**
+ * @brief Function for initializing a PWM instance.
+ *
+ * @param[in] p_instance        PWM instance.
+ * @param[in] p_config          Initial configuration.
+ * @param[in] p_ready_callback  Pointer to ready callback function (or NULL to disable).
+ *
+ * @retval    NRF_SUCCESS If initialization was successful.
+ * @retval    NRF_ERROR_NO_MEM If there were not enough free resources.
+ * @retval    NRF_ERROR_INVALID_PARAM If an invalid configuration structure was passed.
+ * @retval    NRF_ERROR_INVALID_STATE If the timer/PWM is already in use or if initialization failed.
+ */
+ret_code_t app_pwm_init(app_pwm_t const * const p_instance, app_pwm_config_t const * const p_config,
+                        app_pwm_callback_t p_ready_callback);
+
+
+/**
+ * @brief Function for uninitializing a PWM instance and releasing the allocated resources.
+ *
+ * @param[in] p_instance  PWM instance.
+ *
+ * @retval    NRF_SUCCESS If uninitialization was successful.
+ * @retval    NRF_ERROR_INVALID_STATE If the given instance was not initialized.
+ */
+ret_code_t app_pwm_uninit(app_pwm_t const * const p_instance);
+
+/**
+ * @brief Function for enabling a PWM instance after initialization.
+ *
+ * @param[in] p_instance  PWM instance.
+ */
+void app_pwm_enable(app_pwm_t const * const p_instance);
+
+/**
+ * @brief Function for disabling a PWM instance after initialization.
+ *
+ * @param[in] p_instance  PWM instance.
+ */
+void app_pwm_disable(app_pwm_t const * const p_instance);
+
+/**
+ * @brief Function for setting the PWM channel duty cycle in percents.
+ *
+ * A duty cycle change requires one full PWM clock period to finish.
+ * If another change is attempted for any channel of given instance before
+ * the current change is complete, the new attempt will result in the error
+ * NRF_ERROR_BUSY.
+ *
+ * @param[in] p_instance  PWM instance.
+ * @param[in] channel     Channel number.
+ * @param[in] duty        Duty cycle (0 - 100).
+ *
+ * @retval    NRF_SUCCESS If the operation was successful.
+ * @retval    NRF_ERROR_BUSY If the PWM is not ready yet.
+ * @retval    NRF_ERROR_INVALID_STATE If the given instance was not initialized.
+ *
+ */
+ret_code_t app_pwm_channel_duty_set(app_pwm_t const * const p_instance,
+                                  uint8_t channel, app_pwm_duty_t duty);
+
+/**
+ * @brief Function for retrieving the PWM channel duty cycle in percents.
+ *
+ * @param[in] p_instance  PWM instance.
+ * @param[in] channel     Channel number.
+ *
+ * @return    Duty cycle value.
+ */
+app_pwm_duty_t app_pwm_channel_duty_get(app_pwm_t const * const p_instance, uint8_t channel);
+
+
+/**
+ * @name Functions accessing values in ticks
+ *
+ * Auxiliary functions that allow to get values in actual timer ticks.
+ * @{
+ */
+
+    /**
+     * @brief Function for setting PWM channel duty cycle in clock ticks.
+     *
+     * @note      Duty cycle changes require one full PWM clock period to finish.
+     *            Until that, the next change attempt (for any channel of given instance)
+     *            will result in an NRF_ERROR_BUSY error.
+     *
+     * @param[in] p_instance  PWM instance.
+     * @param[in] channel     Channel number.
+     * @param[in] ticks       Number of PWM clock ticks.
+     *
+     * @retval    NRF_SUCCESS If the operation was successful.
+     * @retval    NRF_ERROR_BUSY If PWM is not ready yet.
+     * @retval    NRF_ERROR_INVALID_STATE If the given instance was not initialized.
+     */
+    ret_code_t app_pwm_channel_duty_ticks_set(app_pwm_t const * const p_instance,
+                                              uint8_t           channel,
+                                              uint16_t          ticks);
+
+
+    /**
+     * @brief Function for retrieving the PWM channel duty cycle in ticks.
+     *
+     * This function retrieves the real, currently set duty cycle in ticks.
+     * For one full PWM cycle the value might be different than the value set by the last
+     * @ref app_pwm_channel_duty_ticks_set function call.
+     *
+     * @param[in] p_instance  PWM instance.
+     * @param[in] channel     Channel number.
+     *
+     * @return    Number of ticks set for selected channel.
+     *
+     */
+    uint16_t app_pwm_channel_duty_ticks_get(app_pwm_t const * const p_instance, uint8_t channel);
+
+    /**
+     * @brief Function for returning the number of ticks in a whole cycle.
+     *
+     * @param[in] p_instance  PWM instance.
+     *
+     * @return    Number of ticks that corresponds to 100% of the duty cycle.
+     */
+    uint16_t app_pwm_cycle_ticks_get(app_pwm_t const * const p_instance);
+/** @} */
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/queue/nrf_queue.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,433 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(NRF_QUEUE)
+#include "nrf_queue.h"
+#include "app_util_platform.h"
+
+/**@brief Get next element index.
+ *
+ * @param[in]   p_queue     Pointer to the queue instance.
+ * @param[in]   idx         Current index.
+ *
+ * @return      Next element index.
+ */
+__STATIC_INLINE size_t nrf_queue_next_idx(nrf_queue_t const * p_queue, size_t idx)
+{
+    ASSERT(p_queue != NULL);
+    return (idx < p_queue->size) ? (idx + 1) : 0;
+}
+
+/**@brief Get current queue utilization. This function assumes that this process will not be interrupted.
+ *
+ * @param[in]   p_queue     Pointer to the queue instance.
+ *
+ * @return      Current queue utilization.
+ */
+__STATIC_INLINE size_t queue_utilization_get(nrf_queue_t const * p_queue)
+{
+    return (p_queue->p_cb->back >= p_queue->p_cb->front) ?
+           (p_queue->p_cb->back - p_queue->p_cb->front)  :
+           (p_queue->size + 1 - p_queue->p_cb->front + p_queue->p_cb->back);
+}
+
+bool nrf_queue_is_full(nrf_queue_t const * p_queue)
+{
+    ASSERT(p_queue != NULL);
+    return (nrf_queue_next_idx(p_queue, p_queue->p_cb->back) == p_queue->p_cb->front);
+}
+
+ret_code_t nrf_queue_push(nrf_queue_t const * p_queue, void const * p_element)
+{
+    ret_code_t status = NRF_SUCCESS;
+
+    ASSERT(p_queue != NULL);
+    ASSERT(p_element != NULL);
+
+    CRITICAL_REGION_ENTER();
+    bool is_full = nrf_queue_is_full(p_queue);
+
+    if (!is_full || (p_queue->mode == NRF_QUEUE_MODE_OVERFLOW))
+    {
+        // Get write position.
+        size_t write_pos = p_queue->p_cb->back;
+        p_queue->p_cb->back = nrf_queue_next_idx(p_queue, p_queue->p_cb->back);
+        if (is_full)
+        {
+            // Overwrite the oldest element.
+            p_queue->p_cb->front = nrf_queue_next_idx(p_queue, p_queue->p_cb->front);
+        }
+
+        // Write a new element.
+        switch (p_queue->element_size)
+        {
+            case sizeof(uint8_t):
+                ((uint8_t *)p_queue->p_buffer)[write_pos] = *((uint8_t *)p_element);
+                break;
+
+            case sizeof(uint16_t):
+                ((uint16_t *)p_queue->p_buffer)[write_pos] = *((uint16_t *)p_element);
+                break;
+
+            case sizeof(uint32_t):
+                ((uint32_t *)p_queue->p_buffer)[write_pos] = *((uint32_t *)p_element);
+                break;
+
+            case sizeof(uint64_t):
+                ((uint64_t *)p_queue->p_buffer)[write_pos] = *((uint64_t *)p_element);
+                break;
+
+            default:
+                memcpy((void *)((size_t)p_queue->p_buffer + write_pos * p_queue->element_size),
+                       p_element,
+                       p_queue->element_size);
+                break;
+        }
+
+        // Update utilization.
+        size_t utilization = queue_utilization_get(p_queue);
+        if (p_queue->p_cb->max_utilization < utilization)
+        {
+            p_queue->p_cb->max_utilization = utilization;
+        }
+    }
+    else
+    {
+        status = NRF_ERROR_NO_MEM;
+    }
+
+    CRITICAL_REGION_EXIT();
+
+    return status;
+}
+
+ret_code_t nrf_queue_generic_pop(nrf_queue_t const * p_queue,
+                                 void              * p_element,
+                                 bool                just_peek)
+{
+    ret_code_t status = NRF_SUCCESS;
+
+    ASSERT(p_queue != NULL);
+    ASSERT(p_element != NULL);
+
+    CRITICAL_REGION_ENTER();
+
+    if (!nrf_queue_is_empty(p_queue))
+    {
+        // Get read position.
+        size_t read_pos = p_queue->p_cb->front;
+
+        // Update next read position.
+        if (!just_peek)
+        {
+            p_queue->p_cb->front = nrf_queue_next_idx(p_queue, p_queue->p_cb->front);
+        }
+
+        // Read element.
+        switch (p_queue->element_size)
+        {
+            case sizeof(uint8_t):
+                *((uint8_t *)p_element) = ((uint8_t *)p_queue->p_buffer)[read_pos];
+                break;
+
+            case sizeof(uint16_t):
+                *((uint16_t *)p_element) = ((uint16_t *)p_queue->p_buffer)[read_pos];
+                break;
+
+            case sizeof(uint32_t):
+                *((uint32_t *)p_element) = ((uint32_t *)p_queue->p_buffer)[read_pos];
+                break;
+
+            case sizeof(uint64_t):
+                *((uint64_t *)p_element) = ((uint64_t *)p_queue->p_buffer)[read_pos];
+                break;
+
+            default:
+                memcpy(p_element,
+                       (void const *)((size_t)p_queue->p_buffer + read_pos * p_queue->element_size),
+                       p_queue->element_size);
+                break;
+        }
+    }
+    else
+    {
+        status = NRF_ERROR_NOT_FOUND;
+    }
+
+    CRITICAL_REGION_EXIT();
+
+    return status;
+}
+
+/**@brief Write elements to the queue. This function assumes that there is enough room in the queue
+ *        to write the requested number of elements and that this process will not be interrupted.
+ *
+ * @param[in]   p_queue             Pointer to the nrf_queue_t instance.
+ * @param[in]   p_data              Pointer to the buffer with elements to write.
+ * @param[in]   element_count       Number of elements to write.
+ */
+static void queue_write(nrf_queue_t const * p_queue, void const * p_data, uint32_t element_count)
+{
+    size_t prev_available = nrf_queue_available_get(p_queue);
+    size_t continuous     = p_queue->size + 1 - p_queue->p_cb->back;
+    void * p_write_ptr    = (void *)((size_t)p_queue->p_buffer
+                          + p_queue->p_cb->back * p_queue->element_size);
+    if (element_count <= continuous)
+    {
+        memcpy(p_write_ptr,
+               p_data,
+               element_count * p_queue->element_size);
+
+        p_queue->p_cb->back = ((p_queue->p_cb->back + element_count) <= p_queue->size)
+                            ? (p_queue->p_cb->back + element_count)
+                            : 0;
+    }
+    else
+    {
+        size_t first_write_length = continuous * p_queue->element_size;
+        memcpy(p_write_ptr,
+               p_data,
+               first_write_length);
+
+        size_t elements_left = element_count - continuous;
+        memcpy(p_queue->p_buffer,
+               (void const *)((size_t)p_data + first_write_length),
+               elements_left * p_queue->element_size);
+
+        p_queue->p_cb->back = elements_left;
+        if (prev_available < element_count)
+        {
+            // Overwrite the oldest elements.
+            p_queue->p_cb->front = nrf_queue_next_idx(p_queue, p_queue->p_cb->back);
+        }
+    }
+
+    // Update utilization.
+    size_t utilization = queue_utilization_get(p_queue);
+    if (p_queue->p_cb->max_utilization < utilization)
+    {
+        p_queue->p_cb->max_utilization = utilization;
+    }
+}
+
+ret_code_t nrf_queue_write(nrf_queue_t const * p_queue,
+                           void const        * p_data,
+                           size_t              element_count)
+{
+    ret_code_t status = NRF_SUCCESS;
+
+    ASSERT(p_queue != NULL);
+    ASSERT(p_data != NULL);
+    ASSERT(element_count <= p_queue->size);
+
+    if (element_count == 0)
+    {
+        return NRF_SUCCESS;
+    }
+
+    CRITICAL_REGION_ENTER();
+
+    if ((nrf_queue_available_get(p_queue) >= element_count)
+     || (p_queue->mode == NRF_QUEUE_MODE_OVERFLOW))
+    {
+        queue_write(p_queue, p_data, element_count);
+    }
+    else
+    {
+        status = NRF_ERROR_NO_MEM;
+    }
+
+    CRITICAL_REGION_EXIT();
+
+    return status;
+}
+
+
+size_t nrf_queue_in(nrf_queue_t const * p_queue,
+                    void const        * p_data,
+                    size_t              element_count)
+{
+    ASSERT(p_queue != NULL);
+    ASSERT(p_data != NULL);
+
+    if (element_count == 0)
+    {
+        return 0;
+    }
+
+    CRITICAL_REGION_ENTER();
+
+    if (p_queue->mode == NRF_QUEUE_MODE_OVERFLOW)
+    {
+        element_count = MIN(element_count, p_queue->size);
+    }
+    else
+    {
+        size_t available = nrf_queue_available_get(p_queue);
+        element_count    = MIN(element_count, available);
+    }
+
+    queue_write(p_queue, p_data, element_count);
+
+    CRITICAL_REGION_EXIT();
+
+    return element_count;
+}
+
+/**@brief Read elements from the queue. This function assumes that there are enough elements
+ *        in the queue to read and that this process will not be interrupted.
+ *
+ * @param[in]   p_queue             Pointer to the nrf_queue_t instance.
+ * @param[out]  p_data              Pointer to the buffer where elements will be copied.
+ * @param[in]   element_count       Number of elements to read.
+ */
+static void queue_read(nrf_queue_t const * p_queue, void * p_data, uint32_t element_count)
+{
+    size_t     continuous = (p_queue->p_cb->front <= p_queue->p_cb->back)
+                          ? p_queue->p_cb->back - p_queue->p_cb->front
+                          : p_queue->size + 1 - p_queue->p_cb->front;
+    void const * p_read_ptr = (void const *)((size_t)p_queue->p_buffer
+                            + p_queue->p_cb->front * p_queue->element_size);
+
+    if (element_count <= continuous)
+    {
+        memcpy(p_data,
+               p_read_ptr,
+               element_count * p_queue->element_size);
+
+        p_queue->p_cb->front = ((p_queue->p_cb->front + element_count) <= p_queue->size)
+                             ? (p_queue->p_cb->front + element_count)
+                             : 0;
+    }
+    else
+    {
+        size_t first_read_length = continuous * p_queue->element_size;
+        memcpy(p_data,
+               p_read_ptr,
+               first_read_length);
+
+        size_t elements_left = element_count - continuous;
+        memcpy((void *)((size_t)p_data + first_read_length),
+               p_queue->p_buffer,
+               elements_left * p_queue->element_size);
+
+        p_queue->p_cb->front = elements_left;
+    }
+}
+
+ret_code_t nrf_queue_read(nrf_queue_t const * p_queue,
+                          void              * p_data,
+                          size_t              element_count)
+{
+    ret_code_t status = NRF_SUCCESS;
+
+    ASSERT(p_queue != NULL);
+    ASSERT(p_data != NULL);
+
+    if (element_count == 0)
+    {
+        return NRF_SUCCESS;
+    }
+
+    CRITICAL_REGION_ENTER();
+
+    if (element_count <= queue_utilization_get(p_queue))
+    {
+        queue_read(p_queue, p_data, element_count);
+    }
+    else
+    {
+        status = NRF_ERROR_NOT_FOUND;
+    }
+
+    CRITICAL_REGION_EXIT();
+
+    return status;
+}
+
+size_t nrf_queue_out(nrf_queue_t const * p_queue,
+                     void              * p_data,
+                     size_t              element_count)
+{
+    ASSERT(p_queue != NULL);
+    ASSERT(p_data != NULL);
+
+    if (element_count == 0)
+    {
+        return 0;
+    }
+
+    CRITICAL_REGION_ENTER();
+
+    size_t utilization = queue_utilization_get(p_queue);
+    element_count      = MIN(element_count, utilization);
+
+    queue_read(p_queue, p_data, element_count);
+
+    CRITICAL_REGION_EXIT();
+
+    return element_count;
+}
+
+void nrf_queue_reset(nrf_queue_t const * p_queue)
+{
+    ASSERT(p_queue != NULL);
+
+    CRITICAL_REGION_ENTER();
+
+    memset(p_queue->p_cb, 0, sizeof(nrf_queue_cb_t));
+
+    CRITICAL_REGION_EXIT();
+}
+
+size_t nrf_queue_utilization_get(nrf_queue_t const * p_queue)
+{
+    size_t utilization;
+    ASSERT(p_queue != NULL);
+
+    CRITICAL_REGION_ENTER();
+
+    utilization = queue_utilization_get(p_queue);
+
+    CRITICAL_REGION_EXIT();
+
+    return utilization;
+}
+
+#endif // NRF_MODULE_ENABLED(NRF_QUEUE)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/queue/nrf_queue.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,400 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+* @defgroup nrf_queue Queue module
+* @{
+* @ingroup app_common
+* @brief Functions that handle the queue instances.
+*/
+
+#ifndef NRF_QUEUE_H__
+#define NRF_QUEUE_H__
+
+#include <stdint.h>
+#include <stdint.h>
+#include <string.h>
+#include "nrf_assert.h"
+#include "sdk_errors.h"
+#include "app_util.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@brief Queue control block. */
+typedef struct
+{
+    size_t front;                   //!< Queue front index.
+    size_t back;                    //!< Queue back index.
+    size_t max_utilization;         //!< Maximum utilization of the queue.
+} nrf_queue_cb_t;
+
+/**@brief Supported queue modes. */
+typedef enum
+{
+    NRF_QUEUE_MODE_OVERFLOW,        //!< If the queue is full, new element will not be accepted.
+    NRF_QUEUE_MODE_NO_OVERFLOW,     //!< If the queue is full, new element will overwrite the oldest.
+} nrf_queue_mode_t;
+
+/**@brief Instance of the queue. */
+typedef struct
+{
+    nrf_queue_cb_t * p_cb;          //!< Pointer to the instance control block.
+    void           * p_buffer;      //!< Pointer to the memory that is used as storage.
+    size_t           size;          //!< Size of the queue.
+    size_t           element_size;  //!< Size of one element.
+    nrf_queue_mode_t mode;          //!< Mode of the queue.
+} nrf_queue_t;
+
+/**@brief Create a queue instance.
+ *
+ * @note  This macro reserves memory for the given queue instance.
+ *
+ * @param[in]   _type       Type which is stored.
+ * @param[in]   _name       Name of the queue.
+ * @param[in]   _size       Size of the queue.
+ * @param[in]   _mode       Mode of the queue.
+ */
+#define NRF_QUEUE_DEF(_type, _name, _size, _mode)                   \
+    static _type             _name##_nrf_queue_buffer[(_size) + 1]; \
+    static nrf_queue_cb_t    _name##_nrf_queue_cb;                  \
+    static const nrf_queue_t _name =                                \
+        {                                                           \
+            .p_cb           = &_name##_nrf_queue_cb,                \
+            .p_buffer       = _name##_nrf_queue_buffer,             \
+            .size           = (_size),                              \
+            .element_size   = sizeof(_type),                        \
+            .mode           = _mode,                                \
+        }
+
+/**@brief Declare a queue interface.
+ *
+ * @param[in]   _type    Type which is stored.
+ * @param[in]   _name    Name of the queue.
+ */
+#define NRF_QUEUE_INTERFACE_DEC(_type, _name)               \
+    ret_code_t  _name##_push(_type const * p_element);      \
+    ret_code_t  _name##_pop(_type * p_element);             \
+    ret_code_t  _name##_peek(_type * p_element);            \
+    ret_code_t  _name##_write(_type const * p_data,         \
+                              size_t        element_count); \
+    ret_code_t  _name##_read(_type * p_data,                \
+                             size_t  element_count);        \
+    size_t      _name##_out(_type * p_data,                 \
+                            size_t  element_count);         \
+    size_t      _name##_in(_type const * p_data,            \
+                            size_t element_count);          \
+    bool        _name##_is_full(void);                      \
+    bool        _name##_is_empty(void);                     \
+    size_t      _name##_utilization_get(void);              \
+    size_t      _name##_available_get(void);                \
+    size_t      _name##_max_utilization_get(void);          \
+    void        _name##_reset(void)
+
+/**@brief Define a custom queue interface.
+ *
+ * @param[in]   _attr    Function attribute that will be added to the queue function definition.
+ * @param[in]   _type    Type which is stored.
+ * @param[in]   _name    Name of the queue.
+ * @param[in]   _p_queue Queue instance.
+ */
+#define NRF_QUEUE_INTERFACE_CUSTOM_DEF(_attr, _type, _name, _p_queue)   \
+    _attr ret_code_t _name##_push(_type const * p_element)              \
+    {                                                                   \
+        ASSERT((_p_queue) != NULL);                                     \
+        ASSERT((_p_queue)->element_size == sizeof(_type));              \
+        return nrf_queue_push((_p_queue), p_element);                   \
+    }                                                                   \
+    _attr ret_code_t _name##_pop(_type * p_element)                     \
+    {                                                                   \
+        ASSERT((_p_queue) != NULL);                                     \
+        ASSERT((_p_queue)->element_size == sizeof(_type));              \
+        return nrf_queue_pop((_p_queue), p_element);                    \
+    }                                                                   \
+    _attr ret_code_t _name##_peek(_type * p_element)                    \
+    {                                                                   \
+        ASSERT((_p_queue) != NULL);                                     \
+        ASSERT((_p_queue)->element_size == sizeof(_type));              \
+        return nrf_queue_peek((_p_queue), p_element);                   \
+    }                                                                   \
+    ret_code_t _name##_write(_type const * p_data,                      \
+                             size_t        element_count)               \
+    {                                                                   \
+        ASSERT((_p_queue) != NULL);                                     \
+        ASSERT((_p_queue)->element_size == sizeof(_type));              \
+        return nrf_queue_write((_p_queue), p_data, element_count);      \
+    }                                                                   \
+    ret_code_t _name##_read(_type * p_data,                             \
+                            size_t  element_count)                      \
+    {                                                                   \
+        ASSERT((_p_queue) != NULL);                                     \
+        ASSERT((_p_queue)->element_size == sizeof(_type));              \
+        return nrf_queue_read((_p_queue), p_data, element_count);       \
+    }                                                                   \
+    size_t _name##_in(_type const * p_data,                             \
+                      size_t  element_count)                            \
+    {                                                                   \
+        ASSERT((_p_queue) != NULL);                                     \
+        ASSERT((_p_queue)->element_size == sizeof(_type));              \
+        return nrf_queue_in((_p_queue), p_data, element_count);         \
+    }                                                                   \
+    size_t _name##_out(_type * p_data,                                  \
+                       size_t  element_count)                           \
+    {                                                                   \
+        ASSERT((_p_queue) != NULL);                                     \
+        ASSERT((_p_queue)->element_size == sizeof(_type));              \
+        return nrf_queue_out((_p_queue), p_data, element_count);        \
+    }                                                                   \
+    bool _name##_is_full(void)                                          \
+    {                                                                   \
+        ASSERT((_p_queue) != NULL);                                     \
+        return nrf_queue_is_full(_p_queue);                             \
+    }                                                                   \
+    bool _name##_is_empty(void)                                         \
+    {                                                                   \
+        ASSERT((_p_queue) != NULL);                                     \
+        return nrf_queue_is_empty(_p_queue);                            \
+    }                                                                   \
+    size_t _name##_utilization_get(void)                                \
+    {                                                                   \
+        ASSERT((_p_queue) != NULL);                                     \
+        return nrf_queue_utilization_get(_p_queue);                     \
+    }                                                                   \
+    size_t _name##_available_get(void)                                  \
+    {                                                                   \
+        ASSERT((_p_queue) != NULL);                                     \
+        return nrf_queue_available_get(_p_queue);                       \
+    }                                                                   \
+    size_t _name##_max_utilization_get(void)                            \
+    {                                                                   \
+        ASSERT((_p_queue) != NULL);                                     \
+        return nrf_queue_max_utilization_get(_p_queue);                 \
+    }                                                                   \
+    void _name##_reset(void)                                            \
+    {                                                                   \
+        ASSERT((_p_queue) != NULL);                                     \
+        nrf_queue_reset(_p_queue);                                      \
+    }
+
+/**@brief Define a queue interface.
+ *
+ * @param[in]   _type    Type which is stored.
+ * @param[in]   _name    Name of the queue.
+ * @param[in]   _p_queue Queue instance.
+ */
+#define NRF_QUEUE_INTERFACE_DEF(_type, _name, _p_queue)                 \
+        NRF_QUEUE_INTERFACE_CUSTOM_DEF(/* empty */, _type, _name, _p_queue)
+
+/**@brief Define a local queue interface.
+ *
+ * @param[in]   _type    Type which is stored.
+ * @param[in]   _name    Name of the queue.
+ * @param[in]   _p_queue Queue instance.
+ */
+#define NRF_QUEUE_INTERFACE_LOCAL_DEF(_type, _name, _p_queue)           \
+        NRF_QUEUE_INTERFACE_CUSTOM_DEF(static, _type, _name, _p_queue)
+
+/**@brief Function for pushing an element to the end of queue.
+ *
+ * @param[in]   p_queue             Pointer to the nrf_queue_t instance.
+ * @param[in]   p_element           Pointer to the element that will be stored in the queue.
+ *
+ * @return      NRF_SUCCESS         If an element has been successfully added.
+ * @return      NRF_ERROR_NO_MEM    If the queue is full (only in @ref NRF_QUEUE_MODE_NO_OVERFLOW).
+ */
+ret_code_t nrf_queue_push(nrf_queue_t const * p_queue, void const * p_element);
+
+/**@brief Generic pop implementation.
+ *
+ * @param[in]   p_queue             Pointer to the nrf_queue_t instance.
+ * @param[out]  p_element           Pointer where the element will be copied.
+ * @param[out]  just_peek           If true, the returned element will not be removed from queue.
+ *
+ * @return      NRF_SUCCESS         If an element was returned.
+ * @return      NRF_ERROR_NOT_FOUND If there are no more elements in the queue.
+ */
+ret_code_t nrf_queue_generic_pop(nrf_queue_t const * p_queue,
+                                 void              * p_element,
+                                 bool                just_peek);
+
+/**@brief Pop element from the front of the queue.
+ *
+ * @param[in]   _p_queue            Pointer to the nrf_queue_t instance.
+ * @param[out]  _p_element          Pointer where the element will be copied.
+ *
+ * @return      NRF_SUCCESS         If an element was returned.
+ * @return      NRF_ERROR_NOT_FOUND If there are no more elements in the queue.
+ */
+#define nrf_queue_pop(_p_queue, _p_element) nrf_queue_generic_pop((_p_queue), (_p_element), false)
+
+/**@brief Peek element from the front of the queue.
+ *
+ * @param[in]   _p_queue            Pointer to the nrf_queue_t instance.
+ * @param[out]  _p_element          Pointer where the element will be copied.
+ *
+ * @return      NRF_SUCCESS         If an element was returned.
+ * @return      NRF_ERROR_NOT_FOUND If there are no more elements in the queue.
+ */
+#define nrf_queue_peek(_p_queue, _p_element) nrf_queue_generic_pop((_p_queue), (_p_element), true)
+
+/**@brief Function for writing elements to the queue.
+ *
+ * @param[in]   p_queue             Pointer to the nrf_queue_t instance.
+ * @param[in]   p_data              Pointer to the buffer with elements to write.
+ * @param[in]   element_count       Number of elements to write.
+ *
+ * @return      NRF_SUCCESS         If an element was written.
+ * @return      NRF_ERROR_NO_MEM    There is not enough space in the queue. No element was written.
+ */
+ret_code_t nrf_queue_write(nrf_queue_t const * p_queue,
+                           void const        * p_data,
+                           size_t              element_count);
+
+/**@brief Function for writing a portion of elements to the queue.
+ *
+ * @param[in]   p_queue             Pointer to the nrf_queue_t instance.
+ * @param[in]   p_data              Pointer to the buffer with elements to write.
+ * @param[in]   element_count       Number of elements to write.
+ *
+ * @return      The number of added elements.
+ */
+size_t nrf_queue_in(nrf_queue_t const * p_queue,
+                    void const        * p_data,
+                    size_t              element_count);
+
+/**@brief Function for reading elements from the queue.
+ *
+ * @param[in]   p_queue             Pointer to the nrf_queue_t instance.
+ * @param[out]  p_data              Pointer to the buffer where elements will be copied.
+ * @param[in]   element_count       Number of elements to read.
+ *
+ * @return      NRF_SUCCESS         If an element was returned.
+ * @return      NRF_ERROR_NOT_FOUND There is not enough elements in the queue.
+ */
+ret_code_t nrf_queue_read(nrf_queue_t const * p_queue,
+                          void              * p_data,
+                          size_t              element_count);
+
+/**@brief Function for reading a portion of elements from the queue.
+ *
+ * @param[in]   p_queue             Pointer to the nrf_queue_t instance.
+ * @param[out]  p_data              Pointer to the buffer where elements will be copied.
+ * @param[in]   element_count       Number of elements to read.
+ *
+ * @return      The number of read elements.
+ */
+size_t nrf_queue_out(nrf_queue_t const * p_queue,
+                    void               * p_data,
+                    size_t               element_count);
+
+/**@brief Function for checking if the queue is full. 
+ *
+ * @param[in]   p_queue     Pointer to the queue instance.
+ *
+ * @return      True if the queue is full.
+ */
+bool nrf_queue_is_full(nrf_queue_t const * p_queue);
+
+/**@brief Function for checking if the queue is empty. 
+ *
+ * @param[in]   p_queue     Pointer to the queue instance.
+ *
+ * @return      True if the queue is empty.
+ */
+__STATIC_INLINE bool nrf_queue_is_empty(nrf_queue_t const * p_queue);
+
+/**@brief Function for getting the current queue utilization. 
+ *
+ * @param[in]   p_queue     Pointer to the queue instance.
+ *
+ * @return      Current queue utilization.
+ */
+size_t nrf_queue_utilization_get(nrf_queue_t const * p_queue);
+
+/**@brief Function for getting the size of available space. 
+ *
+ * @param[in]   p_queue     Pointer to the queue instance.
+ *
+ * @return      Size of available space.
+ */
+__STATIC_INLINE size_t nrf_queue_available_get(nrf_queue_t const * p_queue);
+
+/**@brief Function for getting the maximal queue utilization. 
+ *
+ * @param[in]   p_queue     Pointer to the queue instance.
+ *
+ * @return      Maximal queue utilization.
+ */
+__STATIC_INLINE size_t nrf_queue_max_utilization_get(nrf_queue_t const * p_queue);
+
+/**@brief Function for resetting the queue state. 
+ *
+ * @param[in]   p_queue     Pointer to the queue instance.
+ */
+void nrf_queue_reset(nrf_queue_t const * p_queue);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE bool nrf_queue_is_empty(nrf_queue_t const * p_queue)
+{
+    ASSERT(p_queue != NULL);
+    return (p_queue->p_cb->front == p_queue->p_cb->back);
+}
+
+__STATIC_INLINE size_t nrf_queue_available_get(nrf_queue_t const * p_queue)
+{
+    ASSERT(p_queue != NULL);
+    return p_queue->size - nrf_queue_utilization_get(p_queue);
+}
+
+__STATIC_INLINE size_t nrf_queue_max_utilization_get(nrf_queue_t const * p_queue)
+{
+    ASSERT(p_queue != NULL);
+    return p_queue->p_cb->max_utilization;
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_QUEUE_H__
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/scheduler/app_scheduler.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,286 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(APP_SCHEDULER)
+#include "app_scheduler.h"
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include "nrf_soc.h"
+#include "nrf_assert.h"
+#include "app_util_platform.h"
+
+/**@brief Structure for holding a scheduled event header. */
+typedef struct
+{
+    app_sched_event_handler_t handler;          /**< Pointer to event handler to receive the event. */
+    uint16_t                  event_data_size;  /**< Size of event data. */
+} event_header_t;
+
+STATIC_ASSERT(sizeof(event_header_t) <= APP_SCHED_EVENT_HEADER_SIZE);
+
+static event_header_t * m_queue_event_headers;  /**< Array for holding the queue event headers. */
+static uint8_t        * m_queue_event_data;     /**< Array for holding the queue event data. */
+static volatile uint8_t m_queue_start_index;    /**< Index of queue entry at the start of the queue. */
+static volatile uint8_t m_queue_end_index;      /**< Index of queue entry at the end of the queue. */
+static uint16_t         m_queue_event_size;     /**< Maximum event size in queue. */
+static uint16_t         m_queue_size;           /**< Number of queue entries. */
+
+#if APP_SCHEDULER_WITH_PROFILER
+static uint16_t m_max_queue_utilization;    /**< Maximum observed queue utilization. */
+#endif
+
+#if APP_SCHEDULER_WITH_PAUSE
+static uint32_t m_scheduler_paused_counter = 0; /**< Counter storing the difference between pausing
+                                                     and resuming the scheduler. */
+#endif
+
+/**@brief Function for incrementing a queue index, and handle wrap-around.
+ *
+ * @param[in]   index   Old index.
+ *
+ * @return      New (incremented) index.
+ */
+static __INLINE uint8_t next_index(uint8_t index)
+{
+    return (index < m_queue_size) ? (index + 1) : 0;
+}
+
+
+static __INLINE uint8_t app_sched_queue_full()
+{
+  uint8_t tmp = m_queue_start_index;
+  return next_index(m_queue_end_index) == tmp;
+}
+
+/**@brief Macro for checking if a queue is full. */
+#define APP_SCHED_QUEUE_FULL() app_sched_queue_full()
+
+
+static __INLINE uint8_t app_sched_queue_empty()
+{
+  uint8_t tmp = m_queue_start_index;
+  return m_queue_end_index == tmp;
+}
+
+/**@brief Macro for checking if a queue is empty. */
+#define APP_SCHED_QUEUE_EMPTY() app_sched_queue_empty()
+
+
+uint32_t app_sched_init(uint16_t event_size, uint16_t queue_size, void * p_event_buffer)
+{
+    uint16_t data_start_index = (queue_size + 1) * sizeof(event_header_t);
+
+    // Check that buffer is correctly aligned
+    if (!is_word_aligned(p_event_buffer))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    // Initialize event scheduler
+    m_queue_event_headers = p_event_buffer;
+    m_queue_event_data    = &((uint8_t *)p_event_buffer)[data_start_index];
+    m_queue_end_index     = 0;
+    m_queue_start_index   = 0;
+    m_queue_event_size    = event_size;
+    m_queue_size          = queue_size;
+
+#if APP_SCHEDULER_WITH_PROFILER
+    m_max_queue_utilization = 0;
+#endif
+
+    return NRF_SUCCESS;
+}
+
+
+uint16_t app_sched_queue_space_get()
+{
+    uint16_t start = m_queue_start_index;
+    uint16_t end   = m_queue_end_index;
+    uint16_t free_space = m_queue_size - ((end >= start) ?
+                           (end - start) : (m_queue_size + 1 - start + end));
+    return free_space;
+}
+
+
+#if APP_SCHEDULER_WITH_PROFILER
+static void queue_utilization_check(void)
+{
+    uint16_t start = m_queue_start_index;
+    uint16_t end   = m_queue_end_index;
+    uint16_t queue_utilization = (end >= start) ? (end - start) :
+        (m_queue_size + 1 - start + end);
+
+    if (queue_utilization > m_max_queue_utilization)
+    {
+        m_max_queue_utilization = queue_utilization;
+    }
+}
+
+uint16_t app_sched_queue_utilization_get(void)
+{
+    return m_max_queue_utilization;
+}
+#endif // APP_SCHEDULER_WITH_PROFILER
+
+
+uint32_t app_sched_event_put(void                    * p_event_data,
+                             uint16_t                  event_data_size,
+                             app_sched_event_handler_t handler)
+{
+    uint32_t err_code;
+
+    if (event_data_size <= m_queue_event_size)
+    {
+        uint16_t event_index = 0xFFFF;
+
+        CRITICAL_REGION_ENTER();
+
+        if (!APP_SCHED_QUEUE_FULL())
+        {
+            event_index       = m_queue_end_index;
+            m_queue_end_index = next_index(m_queue_end_index);
+
+        #if APP_SCHEDULER_WITH_PROFILER
+            // This function call must be protected with critical region because
+            // it modifies 'm_max_queue_utilization'.
+            queue_utilization_check();
+        #endif
+        }
+
+        CRITICAL_REGION_EXIT();
+
+        if (event_index != 0xFFFF)
+        {
+            // NOTE: This can be done outside the critical region since the event consumer will
+            //       always be called from the main loop, and will thus never interrupt this code.
+            m_queue_event_headers[event_index].handler = handler;
+            if ((p_event_data != NULL) && (event_data_size > 0))
+            {
+                memcpy(&m_queue_event_data[event_index * m_queue_event_size],
+                       p_event_data,
+                       event_data_size);
+                m_queue_event_headers[event_index].event_data_size = event_data_size;
+            }
+            else
+            {
+                m_queue_event_headers[event_index].event_data_size = 0;
+            }
+
+            err_code = NRF_SUCCESS;
+        }
+        else
+        {
+            err_code = NRF_ERROR_NO_MEM;
+        }
+    }
+    else
+    {
+        err_code = NRF_ERROR_INVALID_LENGTH;
+    }
+
+    return err_code;
+}
+
+
+#if APP_SCHEDULER_WITH_PAUSE
+void app_sched_pause(void)
+{
+    CRITICAL_REGION_ENTER();
+
+    if (m_scheduler_paused_counter < UINT32_MAX)
+    {
+        m_scheduler_paused_counter++;
+    }
+    CRITICAL_REGION_EXIT();
+}
+
+void app_sched_resume(void)
+{
+    CRITICAL_REGION_ENTER();
+
+    if (m_scheduler_paused_counter > 0)
+    {
+        m_scheduler_paused_counter--;
+    }
+    CRITICAL_REGION_EXIT();
+}
+#endif //APP_SCHEDULER_WITH_PAUSE
+
+
+/**@brief Function for checking if scheduler is paused which means that should break processing
+ *        events.
+ *
+ * @return    Boolean value - true if scheduler is paused, false otherwise.
+ */
+static __INLINE bool is_app_sched_paused(void)
+{
+#if APP_SCHEDULER_WITH_PAUSE
+    return (m_scheduler_paused_counter > 0);
+#else
+    return false;
+#endif
+}
+
+
+void app_sched_execute(void)
+{
+    while (!is_app_sched_paused() && !APP_SCHED_QUEUE_EMPTY())
+    {
+        // Since this function is only called from the main loop, there is no
+        // need for a critical region here, however a special care must be taken
+        // regarding update of the queue start index (see the end of the loop).
+        uint16_t event_index = m_queue_start_index;
+
+        void * p_event_data;
+        uint16_t event_data_size;
+        app_sched_event_handler_t event_handler;
+
+        p_event_data = &m_queue_event_data[event_index * m_queue_event_size];
+        event_data_size = m_queue_event_headers[event_index].event_data_size;
+        event_handler   = m_queue_event_headers[event_index].handler;
+
+        event_handler(p_event_data, event_data_size);
+
+        // Event processed, now it is safe to move the queue start index,
+        // so the queue entry occupied by this event can be used to store
+        // a next one.
+        m_queue_start_index = next_index(m_queue_start_index);
+    }
+}
+#endif //NRF_MODULE_ENABLED(APP_SCHEDULER)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/scheduler/app_scheduler.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,210 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup app_scheduler Scheduler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief The scheduler is used for transferring execution from the interrupt context to the main
+ *        context.
+ *
+ * @details See @ref seq_diagrams_sched for sequence diagrams illustrating the flow of events
+ *          when using the Scheduler.
+ *
+ * @section app_scheduler_req Requirements:
+ *
+ * @subsection main_context_logic Logic in main context:
+ *
+ *   - Define an event handler for each type of event expected.
+ *   - Initialize the scheduler by calling the APP_SCHED_INIT() macro before entering the
+ *     application main loop.
+ *   - Call app_sched_execute() from the main loop each time the application wakes up because of an
+ *     event (typically when sd_app_evt_wait() returns).
+ *
+ * @subsection int_context_logic Logic in interrupt context:
+ *
+ *   - In the interrupt handler, call app_sched_event_put()
+ *     with the appropriate data and event handler. This will insert an event into the
+ *     scheduler's queue. The app_sched_execute() function will pull this event and call its
+ *     handler in the main context.
+ *
+ * @if (PERIPHERAL)
+ * For an example usage of the scheduler, see the implementations of
+ * @ref ble_sdk_app_hids_mouse and @ref ble_sdk_app_hids_keyboard.
+ * @endif
+ *
+ * @image html scheduler_working.svg The high level design of the scheduler
+ */
+
+#ifndef APP_SCHEDULER_H__
+#define APP_SCHEDULER_H__
+
+#include "sdk_config.h"
+#include <stdint.h>
+#include "app_error.h"
+#include "app_util.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define APP_SCHED_EVENT_HEADER_SIZE 8       /**< Size of app_scheduler.event_header_t (only for use inside APP_SCHED_BUF_SIZE()). */
+
+/**@brief Compute number of bytes required to hold the scheduler buffer.
+ *
+ * @param[in] EVENT_SIZE   Maximum size of events to be passed through the scheduler.
+ * @param[in] QUEUE_SIZE   Number of entries in scheduler queue (i.e. the maximum number of events
+ *                         that can be scheduled for execution).
+ *
+ * @return    Required scheduler buffer size (in bytes).
+ */
+#define APP_SCHED_BUF_SIZE(EVENT_SIZE, QUEUE_SIZE)                                                 \
+            (((EVENT_SIZE) + APP_SCHED_EVENT_HEADER_SIZE) * ((QUEUE_SIZE) + 1))
+
+/**@brief Scheduler event handler type. */
+typedef void (*app_sched_event_handler_t)(void * p_event_data, uint16_t event_size);
+
+/**@brief Macro for initializing the event scheduler.
+ *
+ * @details It will also handle dimensioning and allocation of the memory buffer required by the
+ *          scheduler, making sure the buffer is correctly aligned.
+ *
+ * @param[in] EVENT_SIZE   Maximum size of events to be passed through the scheduler.
+ * @param[in] QUEUE_SIZE   Number of entries in scheduler queue (i.e. the maximum number of events
+ *                         that can be scheduled for execution).
+ *
+ * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ *       several times as long as it is from the same location, e.g. to do a reinitialization).
+ */
+#define APP_SCHED_INIT(EVENT_SIZE, QUEUE_SIZE)                                                     \
+    do                                                                                             \
+    {                                                                                              \
+        static uint32_t APP_SCHED_BUF[CEIL_DIV(APP_SCHED_BUF_SIZE((EVENT_SIZE), (QUEUE_SIZE)),     \
+                                               sizeof(uint32_t))];                                 \
+        uint32_t ERR_CODE = app_sched_init((EVENT_SIZE), (QUEUE_SIZE), APP_SCHED_BUF);             \
+        APP_ERROR_CHECK(ERR_CODE);                                                                 \
+    } while (0)
+
+/**@brief Function for initializing the Scheduler.
+ *
+ * @details It must be called before entering the main loop.
+ *
+ * @param[in]   max_event_size   Maximum size of events to be passed through the scheduler.
+ * @param[in]   queue_size       Number of entries in scheduler queue (i.e. the maximum number of
+ *                               events that can be scheduled for execution).
+ * @param[in]   p_evt_buffer   Pointer to memory buffer for holding the scheduler queue. It must
+ *                               be dimensioned using the APP_SCHED_BUFFER_SIZE() macro. The buffer
+ *                               must be aligned to a 4 byte boundary.
+ *
+ * @note Normally initialization should be done using the APP_SCHED_INIT() macro, as that will both
+ *       allocate the scheduler buffer, and also align the buffer correctly.
+ *
+ * @retval      NRF_SUCCESS               Successful initialization.
+ * @retval      NRF_ERROR_INVALID_PARAM   Invalid parameter (buffer not aligned to a 4 byte
+ *                                        boundary).
+ */
+uint32_t app_sched_init(uint16_t max_event_size, uint16_t queue_size, void * p_evt_buffer);
+
+/**@brief Function for executing all scheduled events.
+ *
+ * @details This function must be called from within the main loop. It will execute all events
+ *          scheduled since the last time it was called.
+ */
+void app_sched_execute(void);
+
+/**@brief Function for scheduling an event.
+ *
+ * @details Puts an event into the event queue.
+ *
+ * @param[in]   p_event_data   Pointer to event data to be scheduled.
+ * @param[in]   event_size     Size of event data to be scheduled.
+ * @param[in]   handler        Event handler to receive the event.
+ *
+ * @return      NRF_SUCCESS on success, otherwise an error code.
+ */
+uint32_t app_sched_event_put(void *                    p_event_data,
+                             uint16_t                  event_size,
+                             app_sched_event_handler_t handler);
+
+/**@brief Function for getting the maximum observed queue utilization.
+ *
+ * Function for tuning the module and determining QUEUE_SIZE value and thus module RAM usage.
+ *
+ * @note @ref APP_SCHEDULER_WITH_PROFILER must be enabled to use this functionality.
+ *
+ * @return Maximum number of events in queue observed so far.
+ */
+uint16_t app_sched_queue_utilization_get(void);
+
+/**@brief Function for getting the current amount of free space in the queue.
+ *
+ * @details The real amount of free space may be less if entries are being added from an interrupt.
+ *          To get the sxact value, this function should be called from the critical section.
+ *
+ * @return Amount of free space in the queue.
+ */
+uint16_t app_sched_queue_space_get(void);
+
+/**@brief A function to pause the scheduler.
+ *
+ * @details When the scheduler is paused events are not pulled from the scheduler queue for
+ *          processing. The function can be called multiple times. To unblock the scheduler the
+ *          function @ref app_sched_resume has to be called the same number of times.
+ *
+ * @note @ref APP_SCHEDULER_WITH_PAUSE must be enabled to use this functionality.
+ */
+void app_sched_pause(void);
+
+/**@brief A function to resume a scheduler.
+ *
+ * @details To unblock the scheduler this function has to be called the same number of times as
+ *          @ref app_sched_pause function.
+ *
+ * @note @ref APP_SCHEDULER_WITH_PAUSE must be enabled to use this functionality.
+ */
+void app_sched_resume(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // APP_SCHEDULER_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/timer/app_timer.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,1079 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifndef MBED_CONF_RTOS_PRESENT
+ 
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(APP_TIMER)
+#include "app_timer.h"
+#include <stdlib.h>
+#include "nrf.h"
+#include "nrf_soc.h"
+#include "app_error.h"
+#include "nrf_delay.h"
+#include "app_util_platform.h"
+
+#define RTC1_IRQ_PRI            APP_IRQ_PRIORITY_LOWEST                        /**< Priority of the RTC1 interrupt (used for checking for timeouts and executing timeout handlers). */
+#define SWI_IRQ_PRI             APP_IRQ_PRIORITY_LOWEST                        /**< Priority of the SWI  interrupt (used for updating the timer list). */
+
+// The current design assumes that both interrupt handlers run at the same interrupt level.
+// If this is to be changed, protection must be added to prevent them from interrupting each other
+// (e.g. by using guard/trigger flags).
+STATIC_ASSERT(RTC1_IRQ_PRI == SWI_IRQ_PRI);
+
+#define MAX_RTC_COUNTER_VAL     0x00FFFFFF                                  /**< Maximum value of the RTC counter. */
+
+#define RTC_COMPARE_OFFSET_MIN  3                                           /**< Minimum offset between the current RTC counter value and the Capture Compare register. Although the nRF51 Series User Specification recommends this value to be 2, we use 3 to be safer.*/
+
+#define MAX_RTC_TASKS_DELAY     47                                          /**< Maximum delay until an RTC task is executed. */
+
+#define SWI_IRQn SWI0_IRQn
+#define SWI_IRQHandler SWI0_IRQHandler
+
+#define MODULE_INITIALIZED (m_op_queue.p_user_op_queue != NULL) /**< Macro designating whether the module has been initialized properly. */
+
+/**@brief Timer node type. The nodes will be used form a linked list of running timers. */
+typedef struct
+{
+    uint32_t                    ticks_to_expire;                            /**< Number of ticks from previous timer interrupt to timer expiry. */
+    uint32_t                    ticks_at_start;                             /**< Current RTC counter value when the timer was started. */
+    uint32_t                    ticks_first_interval;                       /**< Number of ticks in the first timer interval. */
+    uint32_t                    ticks_periodic_interval;                    /**< Timer period (for repeating timers). */
+    bool                        is_running;                                 /**< True if timer is running, False otherwise. */
+    app_timer_mode_t            mode;                                       /**< Timer mode. */
+    app_timer_timeout_handler_t p_timeout_handler;                          /**< Pointer to function to be executed when the timer expires. */
+    void *                      p_context;                                  /**< General purpose pointer. Will be passed to the timeout handler when the timer expires. */
+    void *                      next;                                       /**< Pointer to the next node. */
+} timer_node_t;
+
+STATIC_ASSERT(sizeof(timer_node_t) == APP_TIMER_NODE_SIZE);
+
+/**@brief Set of available timer operation types. */
+typedef enum
+{
+    TIMER_USER_OP_TYPE_NONE,                                                /**< Invalid timer operation type. */
+    TIMER_USER_OP_TYPE_START,                                               /**< Timer operation type Start. */
+    TIMER_USER_OP_TYPE_STOP,                                                /**< Timer operation type Stop. */
+    TIMER_USER_OP_TYPE_STOP_ALL                                             /**< Timer operation type Stop All. */
+} timer_user_op_type_t;
+
+/**@brief Structure describing a timer start operation. */
+typedef struct
+{
+    uint32_t ticks_at_start;                                                /**< Current RTC counter value when the timer was started. */
+    uint32_t ticks_first_interval;                                          /**< Number of ticks in the first timer interval. */
+    uint32_t ticks_periodic_interval;                                       /**< Timer period (for repeating timers). */
+    void *   p_context;                                                     /**< General purpose pointer. Will be passed to the timeout handler when the timer expires. */
+} timer_user_op_start_t;
+
+/**@brief Structure describing a timer operation. */
+typedef struct
+{
+    timer_user_op_type_t op_type;                                             /**< Id of timer on which the operation is to be performed. */
+    timer_node_t *       p_node;
+    union
+    {
+        timer_user_op_start_t start;                                        /**< Structure describing a timer start operation. */
+    } params;
+} timer_user_op_t;
+
+STATIC_ASSERT(sizeof(timer_user_op_t) <= APP_TIMER_USER_OP_SIZE);
+STATIC_ASSERT(sizeof(timer_user_op_t) % 4 == 0);
+
+/**@brief Structure describing a timer operations queue.
+ *
+ * @details This queue will hold timer operations issued by the application
+ *          until the timer interrupt handler processes these operations.
+ */
+typedef struct
+{
+    uint8_t           first;                                                    /**< Index of first entry to have been inserted in the queue (i.e. the next entry to be executed). */
+    uint8_t           last;                                                     /**< Index of last entry to have been inserted in the queue. */
+    uint8_t           size;                                                     /**< Queue size. */
+    timer_user_op_t * p_user_op_queue;                                          /**< Queue buffer. */
+} timer_op_queue_t;
+
+STATIC_ASSERT(sizeof(timer_op_queue_t) % 4 == 0);
+
+#define CONTEXT_QUEUE_SIZE_MAX      (2)
+
+static timer_op_queue_t              m_op_queue;                                /**< Timer operations queue. */
+static timer_node_t *                mp_timer_id_head;                          /**< First timer in list of running timers. */
+static uint32_t                      m_ticks_latest;                            /**< Last known RTC counter value. */
+static uint32_t                      m_ticks_elapsed[CONTEXT_QUEUE_SIZE_MAX];   /**< Timer internal elapsed ticks queue. */
+static uint8_t                       m_ticks_elapsed_q_read_ind;                /**< Timer internal elapsed ticks queue read index. */
+static uint8_t                       m_ticks_elapsed_q_write_ind;               /**< Timer internal elapsed ticks queue write index. */
+static app_timer_evt_schedule_func_t m_evt_schedule_func;                       /**< Pointer to function for propagating timeout events to the scheduler. */
+static bool                          m_rtc1_running;                            /**< Boolean indicating if RTC1 is running. */
+static bool                          m_rtc1_reset;                              /**< Boolean indicating if RTC1 counter has been reset due to last timer removed from timer list during the timer list handling. */
+
+#if APP_TIMER_WITH_PROFILER
+static uint8_t                       m_max_user_op_queue_utilization;           /**< Maximum observed timer user operations queue utilization. */
+#endif
+
+/**@brief Function for initializing the RTC1 counter.
+ *
+ * @param[in] prescaler   Value of the RTC1 PRESCALER register. Set to 0 for no prescaling.
+ */
+static void rtc1_init(uint32_t prescaler)
+{
+    NRF_RTC1->PRESCALER = prescaler;
+    NVIC_SetPriority(RTC1_IRQn, RTC1_IRQ_PRI);
+}
+
+
+/**@brief Function for starting the RTC1 timer.
+ */
+static void rtc1_start(void)
+{
+    NRF_RTC1->EVTENSET = RTC_EVTEN_COMPARE0_Msk;
+    NRF_RTC1->INTENSET = RTC_INTENSET_COMPARE0_Msk;
+
+    NVIC_ClearPendingIRQ(RTC1_IRQn);
+    NVIC_EnableIRQ(RTC1_IRQn);
+
+    NRF_RTC1->TASKS_START = 1;
+    nrf_delay_us(MAX_RTC_TASKS_DELAY);
+
+    m_rtc1_running = true;
+}
+
+
+/**@brief Function for stopping the RTC1 timer.
+ */
+static void rtc1_stop(void)
+{
+    NVIC_DisableIRQ(RTC1_IRQn);
+
+    NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE0_Msk;
+    NRF_RTC1->INTENCLR = RTC_INTENSET_COMPARE0_Msk;
+
+    NRF_RTC1->TASKS_STOP = 1;
+    nrf_delay_us(MAX_RTC_TASKS_DELAY);
+
+    NRF_RTC1->TASKS_CLEAR = 1;
+    m_ticks_latest        = 0;
+    nrf_delay_us(MAX_RTC_TASKS_DELAY);
+
+    m_rtc1_running = false;
+}
+
+
+/**@brief Function for returning the current value of the RTC1 counter.
+ *
+ * @return     Current value of the RTC1 counter.
+ */
+static __INLINE uint32_t rtc1_counter_get(void)
+{
+    return NRF_RTC1->COUNTER;
+}
+
+
+/**@brief Function for computing the difference between two RTC1 counter values.
+ *
+ * @return     Number of ticks elapsed from ticks_old to ticks_now.
+ */
+static __INLINE uint32_t ticks_diff_get(uint32_t ticks_now, uint32_t ticks_old)
+{
+    return ((ticks_now - ticks_old) & MAX_RTC_COUNTER_VAL);
+}
+
+
+/**@brief Function for setting the RTC1 Capture Compare register 0, and enabling the corresponding
+ *        event.
+ *
+ * @param[in] value   New value of Capture Compare register 0.
+ */
+static __INLINE void rtc1_compare0_set(uint32_t value)
+{
+    NRF_RTC1->CC[0] = value;
+}
+
+
+/**@brief Function for inserting a timer in the timer list.
+ *
+ * @param[in]  timer_id   Id of timer to insert.
+ */
+static void timer_list_insert(timer_node_t * p_timer)
+{
+    if (mp_timer_id_head == NULL)
+    {
+        mp_timer_id_head = p_timer;
+    }
+    else
+    {
+        if (p_timer->ticks_to_expire <= mp_timer_id_head->ticks_to_expire)
+        {
+            mp_timer_id_head->ticks_to_expire -= p_timer->ticks_to_expire;
+
+            p_timer->next   = mp_timer_id_head;
+            mp_timer_id_head = p_timer;
+        }
+        else
+        {
+            timer_node_t * p_previous;
+            timer_node_t * p_current;
+            uint32_t       ticks_to_expire;
+
+            ticks_to_expire   = p_timer->ticks_to_expire;
+            p_previous        = mp_timer_id_head;
+            p_current         = mp_timer_id_head;
+
+            while ((p_current != NULL) && (ticks_to_expire > p_current->ticks_to_expire))
+            {
+                ticks_to_expire   -= p_current->ticks_to_expire;
+                p_previous         = p_current;
+                p_current          = p_current->next;
+            }
+
+            if (p_current != NULL)
+            {
+                p_current->ticks_to_expire -= ticks_to_expire;
+            }
+
+            p_timer->ticks_to_expire = ticks_to_expire;
+            p_timer->next            = p_current;
+            p_previous->next         = p_timer;
+        }
+    }
+}
+
+
+/**@brief Function for removing a timer from the timer queue.
+ *
+ * @param[in]  timer_id   Id of timer to remove.
+ */
+static void timer_list_remove(timer_node_t * p_timer)
+{
+    timer_node_t * p_previous;
+    timer_node_t * p_current;
+    uint32_t       timeout;
+
+    // Find the timer's position in timer list.
+    p_previous = mp_timer_id_head;
+    p_current  = p_previous;
+
+    while (p_current != NULL)
+    {
+        if (p_current == p_timer)
+        {
+            break;
+        }
+        p_previous = p_current;
+        p_current  = p_current->next;
+    }
+
+    // Timer not in active list.
+    if (p_current == NULL)
+    {
+        return;
+    }
+
+    // Timer is the first in the list
+    if (p_previous == p_current)
+    {
+        mp_timer_id_head = mp_timer_id_head->next;
+
+        // No more timers in the list. Reset RTC1 in case Start timer operations are present in the queue.
+        if (mp_timer_id_head == NULL)
+        {
+            NRF_RTC1->TASKS_CLEAR = 1;
+            m_ticks_latest        = 0;
+            m_rtc1_reset          = true;
+        }
+    }
+
+    // Remaining timeout between next timeout.
+    timeout = p_current->ticks_to_expire;
+
+    // Link previous timer with next of this timer, i.e. removing the timer from list.
+    p_previous->next = p_current->next;
+
+    // If this is not the last timer, increment the next timer by this timer timeout.
+    p_current = p_previous->next;
+    if (p_current != NULL)
+    {
+        p_current->ticks_to_expire += timeout;
+    }
+}
+
+
+/**@brief Function for scheduling a check for timeouts by generating a RTC1 interrupt.
+ */
+static void timer_timeouts_check_sched(void)
+{
+    NVIC_SetPendingIRQ(RTC1_IRQn);
+}
+
+
+/**@brief Function for scheduling a timer list update by generating a SWI interrupt.
+ */
+static void timer_list_handler_sched(void)
+{
+    NVIC_SetPendingIRQ(SWI_IRQn);
+}
+
+
+/**@brief Function for executing an application timeout handler, either by calling it directly, or
+ *        by passing an event to the @ref app_scheduler.
+ *
+ * @param[in]  p_timer   Pointer to expired timer.
+ */
+static void timeout_handler_exec(timer_node_t * p_timer)
+{
+    if (m_evt_schedule_func != NULL)
+    {
+        uint32_t err_code = m_evt_schedule_func(p_timer->p_timeout_handler, p_timer->p_context);
+        APP_ERROR_CHECK(err_code);
+    }
+    else
+    {
+        p_timer->p_timeout_handler(p_timer->p_context);
+    }
+}
+
+
+/**@brief Function for checking for expired timers.
+ */
+static void timer_timeouts_check(void)
+{
+    // Handle expired of timer
+    if (mp_timer_id_head != NULL)
+    {
+        timer_node_t *  p_timer;
+        timer_node_t *  p_previous_timer;
+        uint32_t        ticks_elapsed;
+        uint32_t        ticks_expired;
+
+        // Initialize actual elapsed ticks being consumed to 0.
+        ticks_expired = 0;
+
+        // ticks_elapsed is collected here, job will use it.
+        ticks_elapsed = ticks_diff_get(rtc1_counter_get(), m_ticks_latest);
+
+        // Auto variable containing the head of timers expiring.
+        p_timer = mp_timer_id_head;
+
+        // Expire all timers within ticks_elapsed and collect ticks_expired.
+        while (p_timer != NULL)
+        {
+            // Do nothing if timer did not expire.
+            if (ticks_elapsed < p_timer->ticks_to_expire)
+            {
+                break;
+            }
+
+            // Decrement ticks_elapsed and collect expired ticks.
+            ticks_elapsed -= p_timer->ticks_to_expire;
+            ticks_expired += p_timer->ticks_to_expire;
+
+            // Move to next timer.
+            p_previous_timer = p_timer;
+            p_timer = p_timer->next;
+
+            // Execute Task.
+            if (p_previous_timer->is_running)
+            {
+                p_previous_timer->is_running = false;
+                timeout_handler_exec(p_previous_timer);
+            }
+        }
+
+        // Prepare to queue the ticks expired in the m_ticks_elapsed queue.
+        if (m_ticks_elapsed_q_read_ind == m_ticks_elapsed_q_write_ind)
+        {
+            // The read index of the queue is equal to the write index. This means the new
+            // value of ticks_expired should be stored at a new location in the m_ticks_elapsed
+            // queue (which is implemented as a double buffer).
+
+            // Check if there will be a queue overflow.
+            if (++m_ticks_elapsed_q_write_ind == CONTEXT_QUEUE_SIZE_MAX)
+            {
+                // There will be a queue overflow. Hence the write index should point to the start
+                // of the queue.
+                m_ticks_elapsed_q_write_ind = 0;
+            }
+        }
+
+        // Queue the ticks expired.
+        m_ticks_elapsed[m_ticks_elapsed_q_write_ind] = ticks_expired;
+
+        timer_list_handler_sched();
+    }
+}
+
+
+/**@brief Function for acquiring the number of ticks elapsed.
+ *
+ * @param[out] p_ticks_elapsed   Number of ticks elapsed.
+ *
+ * @return     TRUE if elapsed ticks was read from queue, FALSE otherwise.
+ */
+static bool elapsed_ticks_acquire(uint32_t * p_ticks_elapsed)
+{
+    // Pick the elapsed value from queue.
+    if (m_ticks_elapsed_q_read_ind != m_ticks_elapsed_q_write_ind)
+    {
+        // Dequeue elapsed value.
+        m_ticks_elapsed_q_read_ind++;
+        if (m_ticks_elapsed_q_read_ind == CONTEXT_QUEUE_SIZE_MAX)
+        {
+            m_ticks_elapsed_q_read_ind = 0;
+        }
+
+        *p_ticks_elapsed = m_ticks_elapsed[m_ticks_elapsed_q_read_ind];
+
+        m_ticks_latest += *p_ticks_elapsed;
+        m_ticks_latest &= MAX_RTC_COUNTER_VAL;
+
+        return true;
+    }
+    else
+    {
+        // No elapsed value in queue.
+        *p_ticks_elapsed = 0;
+        return false;
+    }
+}
+
+
+/**@brief Function for handling the timer list deletions.
+ *
+ * @return     TRUE if Capture Compare register must be updated, FALSE otherwise.
+ */
+static bool list_deletions_handler(void)
+{
+    timer_node_t * p_timer_old_head;
+    uint8_t        user_ops_first = m_op_queue.first;
+
+    // Remember the old head, so as to decide if new compare needs to be set.
+    p_timer_old_head = mp_timer_id_head;
+
+    while (user_ops_first != m_op_queue.last)
+    {
+        timer_user_op_t * p_user_op = &m_op_queue.p_user_op_queue[user_ops_first];
+
+        // Traverse to next operation in queue.
+        user_ops_first++;
+        if (user_ops_first == m_op_queue.size)
+        {
+            user_ops_first = 0;
+        }
+
+        switch (p_user_op->op_type)
+        {
+            case TIMER_USER_OP_TYPE_STOP:
+                // Delete node if timer is running.
+                timer_list_remove(p_user_op->p_node);
+                break;
+
+            case TIMER_USER_OP_TYPE_STOP_ALL:
+                // Delete list of running timers, and mark all timers as not running.
+                while (mp_timer_id_head != NULL)
+                {
+                    timer_node_t * p_head = mp_timer_id_head;
+
+                    p_head->is_running = false;
+                    mp_timer_id_head    = p_head->next;
+                }
+                break;
+
+            default:
+                // No implementation needed.
+                break;
+        }
+    }
+
+    // Detect change in head of the list.
+    return (mp_timer_id_head != p_timer_old_head);
+}
+
+
+/**@brief Function for updating the timer list for expired timers.
+ *
+ * @param[in]  ticks_elapsed         Number of elapsed ticks.
+ * @param[in]  ticks_previous        Previous known value of the RTC counter.
+ * @param[out] p_restart_list_head   List of repeating timers to be restarted.
+ */
+static void expired_timers_handler(uint32_t         ticks_elapsed,
+                                   uint32_t         ticks_previous,
+                                   timer_node_t **  p_restart_list_head)
+{
+    uint32_t ticks_expired = 0;
+
+    while (mp_timer_id_head != NULL)
+    {
+        timer_node_t * p_timer;
+        timer_node_t * p_timer_expired;
+
+        // Auto variable for current timer node.
+        p_timer = mp_timer_id_head;
+
+        // Do nothing if timer did not expire
+        if (ticks_elapsed < p_timer->ticks_to_expire)
+        {
+            p_timer->ticks_to_expire -= ticks_elapsed;
+            break;
+        }
+
+        // Decrement ticks_elapsed and collect expired ticks.
+        ticks_elapsed -= p_timer->ticks_to_expire;
+        ticks_expired += p_timer->ticks_to_expire;
+
+        // Timer expired, set ticks_to_expire zero.
+        p_timer->ticks_to_expire = 0;
+
+        // Remove the expired timer from head.
+        p_timer_expired  = mp_timer_id_head;
+        mp_timer_id_head = p_timer->next;
+
+        // Timer will be restarted if periodic.
+        if (p_timer->ticks_periodic_interval != 0)
+        {
+            p_timer->ticks_at_start       = (ticks_previous + ticks_expired) & MAX_RTC_COUNTER_VAL;
+            p_timer->ticks_first_interval = p_timer->ticks_periodic_interval;
+            p_timer->next                 = *p_restart_list_head;
+            *p_restart_list_head          = p_timer_expired;
+        }
+    }
+}
+
+
+/**@brief Function for handling timer list insertions.
+ *
+ * @param[in]  p_restart_list_head   List of repeating timers to be restarted.
+ *
+ * @return     TRUE if Capture Compare register must be updated, FALSE otherwise.
+ */
+static bool list_insertions_handler(timer_node_t * p_restart_list_head)
+{
+    timer_node_t * p_timer_id_old_head;
+
+    // Remember the old head, so as to decide if new compare needs to be set.
+    p_timer_id_old_head = mp_timer_id_head;
+
+    // Handle insertions of timers.
+    while ((p_restart_list_head != NULL) || (m_op_queue.first != m_op_queue.last))
+    {
+        timer_node_t * p_timer;
+
+        if (p_restart_list_head != NULL)
+        {
+            p_timer           = p_restart_list_head;
+            p_restart_list_head = p_timer->next;
+        }
+        else
+        {
+            timer_user_op_t * p_user_op = &m_op_queue.p_user_op_queue[m_op_queue.first];
+
+            m_op_queue.first++;
+            if (m_op_queue.first == m_op_queue.size)
+            {
+                m_op_queue.first = 0;
+            }
+
+            p_timer = p_user_op->p_node;
+
+            if ((p_user_op->op_type != TIMER_USER_OP_TYPE_START) || p_timer->is_running)
+            {
+                continue;
+            }
+
+            p_timer->ticks_at_start          = p_user_op->params.start.ticks_at_start;
+            p_timer->ticks_first_interval    = p_user_op->params.start.ticks_first_interval;
+            p_timer->ticks_periodic_interval = p_user_op->params.start.ticks_periodic_interval;
+            p_timer->p_context               = p_user_op->params.start.p_context;
+
+            if (m_rtc1_reset)
+            {
+                p_timer->ticks_at_start = 0;
+            }
+        }
+
+        // Prepare the node to be inserted.
+        if (
+             ((p_timer->ticks_at_start - m_ticks_latest) & MAX_RTC_COUNTER_VAL)
+             <
+             (MAX_RTC_COUNTER_VAL / 2)
+            )
+        {
+            p_timer->ticks_to_expire = ticks_diff_get(p_timer->ticks_at_start, m_ticks_latest) +
+                                       p_timer->ticks_first_interval;
+        }
+        else
+        {
+            uint32_t delta_current_start;
+
+            delta_current_start = ticks_diff_get(m_ticks_latest, p_timer->ticks_at_start);
+            if (p_timer->ticks_first_interval > delta_current_start)
+            {
+                p_timer->ticks_to_expire = p_timer->ticks_first_interval - delta_current_start;
+            }
+            else
+            {
+                p_timer->ticks_to_expire = 0;
+            }
+        }
+
+        p_timer->ticks_at_start       = 0;
+        p_timer->ticks_first_interval = 0;
+        p_timer->is_running           = true;
+        p_timer->next                 = NULL;
+
+        // Insert into list
+        timer_list_insert(p_timer);
+    }
+
+    return (mp_timer_id_head != p_timer_id_old_head);
+}
+
+
+/**@brief Function for updating the Capture Compare register.
+ */
+static void compare_reg_update(timer_node_t * p_timer_id_head_old)
+{
+    // Setup the timeout for timers on the head of the list
+    if (mp_timer_id_head != NULL)
+    {
+        uint32_t ticks_to_expire = mp_timer_id_head->ticks_to_expire;
+        uint32_t pre_counter_val = rtc1_counter_get();
+        uint32_t cc              = m_ticks_latest;
+        uint32_t ticks_elapsed   = ticks_diff_get(pre_counter_val, cc) + RTC_COMPARE_OFFSET_MIN;
+
+        if (!m_rtc1_running)
+        {
+            // No timers were already running, start RTC
+            rtc1_start();
+        }
+
+        cc += (ticks_elapsed < ticks_to_expire) ? ticks_to_expire : ticks_elapsed;
+        cc &= MAX_RTC_COUNTER_VAL;
+
+        rtc1_compare0_set(cc);
+
+        uint32_t post_counter_val = rtc1_counter_get();
+
+        if (
+            (ticks_diff_get(post_counter_val, pre_counter_val) + RTC_COMPARE_OFFSET_MIN)
+            >
+            ticks_diff_get(cc, pre_counter_val)
+           )
+        {
+            // When this happens the COMPARE event may not be triggered by the RTC.
+            // The nRF51 Series User Specification states that if the COUNTER value is N
+            // (i.e post_counter_val = N), writing N or N + 1 to a CC register may not trigger a
+            // COMPARE event. Hence the RTC interrupt is forcefully pended by calling the following
+            // function.
+            rtc1_compare0_set(rtc1_counter_get());  // this should prevent CC to fire again in the background while the code is in RTC-ISR
+            nrf_delay_us(MAX_RTC_TASKS_DELAY);
+            timer_timeouts_check_sched();
+        }
+    }
+    else
+    {
+#if (APP_TIMER_KEEPS_RTC_ACTIVE == 0)
+        // No timers are running, stop RTC
+        rtc1_stop();
+#endif //(APP_TIMER_KEEPS_RTC_ACTIVE == 0)
+    }
+}
+
+
+/**@brief Function for handling changes to the timer list.
+ */
+static void timer_list_handler(void)
+{
+    timer_node_t * p_restart_list_head = NULL;
+
+    uint32_t       ticks_elapsed;
+    uint32_t       ticks_previous;
+    bool           ticks_have_elapsed;
+    bool           compare_update;
+    timer_node_t * p_timer_id_head_old;
+
+#if APP_TIMER_WITH_PROFILER
+    {
+        uint8_t size = m_op_queue.size;
+        uint8_t first = m_op_queue.first;
+        uint8_t last = m_op_queue.last;
+        uint8_t utilization = (first <= last) ? (last - first) : (size + 1 - first + last);
+
+        if (utilization > m_max_user_op_queue_utilization)
+        {
+            m_max_user_op_queue_utilization = utilization;
+        }
+    }
+#endif
+
+    // Back up the previous known tick and previous list head
+    ticks_previous    = m_ticks_latest;
+    p_timer_id_head_old = mp_timer_id_head;
+
+    // Get number of elapsed ticks
+    ticks_have_elapsed = elapsed_ticks_acquire(&ticks_elapsed);
+
+    // Handle list deletions
+    compare_update = list_deletions_handler();
+
+    // Handle expired timers
+    if (ticks_have_elapsed)
+    {
+        expired_timers_handler(ticks_elapsed, ticks_previous, &p_restart_list_head);
+        compare_update = true;
+    }
+
+    // Handle list insertions
+    if (list_insertions_handler(p_restart_list_head))
+    {
+        compare_update = true;
+    }
+
+    // Update compare register if necessary
+    if (compare_update)
+    {
+        compare_reg_update(p_timer_id_head_old);
+    }
+    m_rtc1_reset = false;
+}
+
+
+/**@brief Function for enqueueing a new operations queue entry.
+ *
+ * @param[in]  last_index Index of the next last index to be enqueued.
+ */
+static void user_op_enque(uint8_t last_index)
+{
+    m_op_queue.last = last_index;
+}
+
+
+/**@brief Function for allocating a new operations queue entry.
+ *
+ * @param[out] p_last_index Index of the next last index to be enqueued.
+ *
+ * @return     Pointer to allocated queue entry, or NULL if queue is full.
+ */
+static timer_user_op_t * user_op_alloc( uint8_t * p_last_index)
+{
+    uint8_t           last;
+    timer_user_op_t * p_user_op;
+
+    last = m_op_queue.last + 1;
+    if (last == m_op_queue.size)
+    {
+        // Overflow case.
+        last = 0;
+    }
+    if (last == m_op_queue.first)
+    {
+        // Queue is full.
+        return NULL;
+    }
+
+    *p_last_index = last;
+    p_user_op     = &m_op_queue.p_user_op_queue[m_op_queue.last];
+
+    return p_user_op;
+}
+
+
+/**@brief Function for scheduling a Timer Start operation.
+ *
+ * @param[in]  timer_id          Id of timer to start.
+ * @param[in]  timeout_initial   Time (in ticks) to first timer expiry.
+ * @param[in]  timeout_periodic  Time (in ticks) between periodic expiries.
+ * @param[in]  p_context         General purpose pointer. Will be passed to the timeout handler when
+ *                               the timer expires.
+ * @return     NRF_SUCCESS on success, otherwise an error code.
+ */
+
+static uint32_t timer_start_op_schedule(timer_node_t * p_node,
+                                        uint32_t        timeout_initial,
+                                        uint32_t        timeout_periodic,
+                                        void *          p_context)
+{
+    uint8_t last_index;
+    uint32_t err_code = NRF_SUCCESS;
+
+    CRITICAL_REGION_ENTER();
+    timer_user_op_t * p_user_op = user_op_alloc(&last_index);
+    if (p_user_op == NULL)
+    {
+        err_code = NRF_ERROR_NO_MEM;
+    }
+    else
+    {
+
+        p_user_op->op_type                              = TIMER_USER_OP_TYPE_START;
+        p_user_op->p_node                               = p_node;
+        p_user_op->params.start.ticks_at_start          = rtc1_counter_get();
+        p_user_op->params.start.ticks_first_interval    = timeout_initial;
+        p_user_op->params.start.ticks_periodic_interval = timeout_periodic;
+        p_user_op->params.start.p_context               = p_context;
+
+        user_op_enque(last_index);
+    }
+    CRITICAL_REGION_EXIT();
+
+    if (err_code == NRF_SUCCESS)
+    {
+        timer_list_handler_sched();
+    }
+
+    return err_code;
+}
+
+
+/**@brief Function for scheduling a Timer Stop operation.
+ *
+ * @param[in]  timer_id   Id of timer to stop.
+ * @param[in]  op_type    Type of stop operation
+ *
+ * @return NRF_SUCCESS on successful scheduling a timer stop operation. NRF_ERROR_NO_MEM when there
+ *         is no memory left to schedule the timer stop operation.
+ */
+static uint32_t timer_stop_op_schedule(timer_node_t * p_node,
+                                       timer_user_op_type_t op_type)
+{
+    uint8_t last_index;
+    uint32_t err_code = NRF_SUCCESS;
+
+    CRITICAL_REGION_ENTER();
+    timer_user_op_t * p_user_op = user_op_alloc(&last_index);
+    if (p_user_op == NULL)
+    {
+        err_code = NRF_ERROR_NO_MEM;
+    }
+    else
+    {
+        p_user_op->op_type  = op_type;
+        p_user_op->p_node = p_node;
+
+        user_op_enque(last_index);
+    }
+    CRITICAL_REGION_EXIT();
+
+    if (err_code == NRF_SUCCESS)
+    {
+        timer_list_handler_sched();
+    }
+
+    return err_code;
+}
+
+/**@brief Function for handling the RTC1 interrupt.
+ *
+ * @details Checks for timeouts, and executes timeout handlers for expired timers.
+ */
+void RTC1_IRQHandler(void)
+{
+    // Clear all events (also unexpected ones)
+    NRF_RTC1->EVENTS_COMPARE[0] = 0;
+    NRF_RTC1->EVENTS_COMPARE[1] = 0;
+    NRF_RTC1->EVENTS_COMPARE[2] = 0;
+    NRF_RTC1->EVENTS_COMPARE[3] = 0;
+    NRF_RTC1->EVENTS_TICK       = 0;
+    NRF_RTC1->EVENTS_OVRFLW     = 0;
+
+    // Check for expired timers
+    timer_timeouts_check();
+}
+
+
+/**@brief Function for handling the SWI interrupt.
+ *
+ * @details Performs all updates to the timer list.
+ */
+void SWI_IRQHandler(void)
+{
+    timer_list_handler();
+}
+
+
+uint32_t app_timer_init(uint32_t                      prescaler,
+                        uint8_t                       op_queue_size,
+                        void *                        p_buffer,
+                        app_timer_evt_schedule_func_t evt_schedule_func)
+{
+    // Check that buffer is correctly aligned
+    if (!is_word_aligned(p_buffer))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    // Check for NULL buffer
+    if (p_buffer == NULL)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    // Stop RTC to prevent any running timers from expiring (in case of reinitialization)
+    rtc1_stop();
+
+    m_evt_schedule_func = evt_schedule_func;
+
+    // Initialize operation queue
+    m_op_queue.first           = 0;
+    m_op_queue.last            = 0;
+    m_op_queue.size            = op_queue_size;
+    m_op_queue.p_user_op_queue = p_buffer;
+
+    mp_timer_id_head            = NULL;
+    m_ticks_elapsed_q_read_ind  = 0;
+    m_ticks_elapsed_q_write_ind = 0;
+
+#if APP_TIMER_WITH_PROFILER
+    m_max_user_op_queue_utilization   = 0;
+#endif
+
+    NVIC_ClearPendingIRQ(SWI_IRQn);
+    NVIC_SetPriority(SWI_IRQn, SWI_IRQ_PRI);
+    NVIC_EnableIRQ(SWI_IRQn);
+
+    rtc1_init(prescaler);
+
+    m_ticks_latest = rtc1_counter_get();
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t app_timer_create(app_timer_id_t const *      p_timer_id,
+                          app_timer_mode_t            mode,
+                          app_timer_timeout_handler_t timeout_handler)
+{
+    // Check state and parameters
+    VERIFY_MODULE_INITIALIZED();
+
+    if (timeout_handler == NULL)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    if (p_timer_id == NULL)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    if (((timer_node_t*)*p_timer_id)->is_running)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    timer_node_t * p_node     = (timer_node_t *)*p_timer_id;
+    p_node->is_running        = false;
+    p_node->mode              = mode;
+    p_node->p_timeout_handler = timeout_handler;
+    return NRF_SUCCESS;
+}
+
+uint32_t app_timer_start(app_timer_id_t timer_id, uint32_t timeout_ticks, void * p_context)
+{
+    uint32_t timeout_periodic;
+    timer_node_t * p_node = (timer_node_t*)timer_id;
+
+    // Check state and parameters
+    VERIFY_MODULE_INITIALIZED();
+
+    if (timer_id == 0)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+    if (timeout_ticks < APP_TIMER_MIN_TIMEOUT_TICKS)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    if (p_node->p_timeout_handler == NULL)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    // Schedule timer start operation
+    timeout_periodic = (p_node->mode == APP_TIMER_MODE_REPEATED) ? timeout_ticks : 0;
+
+    return timer_start_op_schedule(p_node,
+                                   timeout_ticks,
+                                   timeout_periodic,
+                                   p_context);
+}
+
+
+uint32_t app_timer_stop(app_timer_id_t timer_id)
+{
+    timer_node_t * p_node = (timer_node_t*)timer_id;
+    // Check state and parameters
+    VERIFY_MODULE_INITIALIZED();
+
+    if ((timer_id == NULL) || (p_node->p_timeout_handler == NULL))
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    p_node->is_running = false;
+    // Schedule timer stop operation
+    return timer_stop_op_schedule(p_node, TIMER_USER_OP_TYPE_STOP);
+}
+
+
+uint32_t app_timer_stop_all(void)
+{
+    // Check state
+    VERIFY_MODULE_INITIALIZED();
+
+    return timer_stop_op_schedule(NULL, TIMER_USER_OP_TYPE_STOP_ALL);
+}
+
+
+uint32_t app_timer_cnt_get(void)
+{
+    return rtc1_counter_get();
+}
+
+
+uint32_t app_timer_cnt_diff_compute(uint32_t   ticks_to,
+                                    uint32_t   ticks_from,
+                                    uint32_t * p_ticks_diff)
+{
+    *p_ticks_diff = ticks_diff_get(ticks_to, ticks_from);
+    return NRF_SUCCESS;
+}
+
+#if APP_TIMER_WITH_PROFILER
+uint8_t app_timer_op_queue_utilization_get(void)
+{
+    return m_max_user_op_queue_utilization;
+}
+#endif
+#endif //NRF_MODULE_ENABLED(APP_TIMER)
+#endif // MBED_CONF_RTOS_PRESENT

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/timer/app_timer.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,321 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup app_timer Application Timer
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Application timer functionality.
+ *
+ * @details This module enables the application to create multiple timer instances based on the RTC1
+ *          peripheral. Checking for time-outs and invocation of user time-out handlers is performed
+ *          in the RTC1 interrupt handler. List handling is done using a software interrupt (SWI0).
+ *          Both interrupt handlers are running in APP_LOW priority level.
+ *
+ * @details When calling app_timer_start() or app_timer_stop(), the timer operation is just queued,
+ *          and the software interrupt is triggered. The actual timer start/stop operation is
+ *          executed by the SWI0 interrupt handler. Since the SWI0 interrupt is running in APP_LOW,
+ *          if the application code calling the timer function is running in APP_LOW or APP_HIGH,
+ *          the timer operation will not be performed until the application handler has returned.
+ *          This will be the case, for example, when stopping a timer from a time-out handler when not using
+ *          the scheduler.
+ *
+ * @details Use the USE_SCHEDULER parameter of the APP_TIMER_INIT() macro to select if the
+ *          @ref app_scheduler should be used or not. Even if the scheduler is
+ *          not used, app_timer.h will include app_scheduler.h, so when
+ *          compiling, app_scheduler.h must be available in one of the compiler include paths.
+ */
+
+#ifndef APP_TIMER_H__
+#define APP_TIMER_H__
+#include "sdk_config.h"
+#include "app_error.h"
+#include "app_util.h"
+#include "compiler_abstraction.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define APP_TIMER_CLOCK_FREQ         32768                      /**< Clock frequency of the RTC timer used to implement the app timer module. */
+#define APP_TIMER_MIN_TIMEOUT_TICKS  5                          /**< Minimum value of the timeout_ticks parameter of app_timer_start(). */
+
+#ifdef RTX
+#define APP_TIMER_NODE_SIZE          40                         /**< Size of app_timer.timer_node_t (used to allocate data). */
+#else
+#define APP_TIMER_NODE_SIZE          32                         /**< Size of app_timer.timer_node_t (used to allocate data). */
+#endif // RTX
+#define APP_TIMER_USER_OP_SIZE       24                         /**< Size of app_timer.timer_user_op_t (only for use inside APP_TIMER_BUF_SIZE()). */
+
+/**@brief Compute number of bytes required to hold the application timer data structures.
+ *
+ * @param[in]  OP_QUEUE_SIZE   Size of the queue holding timer operations that are pending execution.
+ *                             Note that due to the queue implementation, this size must be one more
+ *                             than the size that is actually needed.
+ *
+ * @return     Required application timer buffer size (in bytes).
+ */
+#define APP_TIMER_BUF_SIZE(OP_QUEUE_SIZE)                                  \
+    (                                                                      \
+        (                                                                  \
+            (((OP_QUEUE_SIZE) + 1) * APP_TIMER_USER_OP_SIZE)               \
+        )                                                                  \
+    )
+
+/**@brief Convert milliseconds to timer ticks.
+ *
+ * This macro uses 64-bit integer arithmetic, but as long as the macro parameters are
+ *       constants (i.e. defines), the computation will be done by the preprocessor.
+ *
+ * When using this macro, ensure that the
+ *         values provided as input result in an output value that is supported by the
+ *         @ref app_timer_start function. For example, when the ticks for 1 ms is needed, the
+ *         maximum possible value of PRESCALER must be 6, when @ref APP_TIMER_CLOCK_FREQ is 32768.
+ *         This will result in a ticks value as 5. Any higher value for PRESCALER will result in a
+ *         ticks value that is not supported by this module.
+ *
+ * @param[in]  MS          Milliseconds.
+ * @param[in]  PRESCALER   Value of the RTC1 PRESCALER register (must be the same value that was
+ *                         passed to APP_TIMER_INIT()).
+ *
+ * @return     Number of timer ticks.
+ */
+#define APP_TIMER_TICKS(MS, PRESCALER)\
+            ((uint32_t)ROUNDED_DIV((MS) * (uint64_t)APP_TIMER_CLOCK_FREQ, ((PRESCALER) + 1) * 1000))
+
+typedef struct app_timer_t { uint32_t data[CEIL_DIV(APP_TIMER_NODE_SIZE, sizeof(uint32_t))]; } app_timer_t;
+
+/**@brief Timer ID type.
+ * Never declare a variable of this type, but use the macro @ref APP_TIMER_DEF instead.*/
+typedef app_timer_t * app_timer_id_t;
+
+/**
+ * @brief Create a timer identifier and statically allocate memory for the timer.
+ *
+ * @param timer_id Name of the timer identifier variable that will be used to control the timer.
+ */
+#define APP_TIMER_DEF(timer_id)                                  \
+    static app_timer_t timer_id##_data = { {0} };                  \
+    static const app_timer_id_t timer_id = &timer_id##_data
+
+
+/**@brief Application time-out handler type. */
+typedef void (*app_timer_timeout_handler_t)(void * p_context);
+
+/**@brief Type of function for passing events from the timer module to the scheduler. */
+typedef uint32_t (*app_timer_evt_schedule_func_t) (app_timer_timeout_handler_t timeout_handler,
+                                                   void *                      p_context);
+
+/**@brief Timer modes. */
+typedef enum
+{
+    APP_TIMER_MODE_SINGLE_SHOT,                 /**< The timer will expire only once. */
+    APP_TIMER_MODE_REPEATED                     /**< The timer will restart each time it expires. */
+} app_timer_mode_t;
+
+/**@brief Initialize the application timer module.
+ *
+ * @details This macro handles dimensioning and allocation of the memory buffer required by the timer,
+ *          making sure that the buffer is correctly aligned. It will also connect the timer module
+ *          to the scheduler (if specified).
+ *
+ * @note    This module assumes that the LFCLK is already running. If it is not, the module will
+ *          be non-functional, since the RTC will not run. If you do not use a SoftDevice, you
+ *          must start the LFCLK manually. See the rtc_example's lfclk_config() function
+ *          for an example of how to do this. If you use a SoftDevice, the LFCLK is started on
+ *          SoftDevice init.
+ *
+ *
+ * @param[in]  PRESCALER        Value of the RTC1 PRESCALER register. This will decide the
+ *                              timer tick rate. Set to 0 for no prescaling.
+ * @param[in]  OP_QUEUE_SIZE    Size of the queue holding timer operations that are pending execution.
+ * @param[in]  SCHEDULER_FUNC   Pointer to scheduler event handler
+ *
+ * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ *       several times as long as it is from the same location, for example, to do a re-initialization).
+ */
+/*lint -emacro(506, APP_TIMER_INIT) */ /* Suppress "Constant value Boolean */
+#define APP_TIMER_INIT(PRESCALER, OP_QUEUE_SIZE, SCHEDULER_FUNC)                  \
+    do                                                                            \
+    {                                                                             \
+        static uint32_t APP_TIMER_BUF[CEIL_DIV(APP_TIMER_BUF_SIZE(OP_QUEUE_SIZE), \
+                                               sizeof(uint32_t))];                \
+        uint32_t ERR_CODE = app_timer_init((PRESCALER),                           \
+                                           (OP_QUEUE_SIZE) + 1,                   \
+                                           APP_TIMER_BUF,                         \
+                                           SCHEDULER_FUNC);                       \
+        APP_ERROR_CHECK(ERR_CODE);                                                \
+    } while (0)
+
+
+
+/**@brief Function for initializing the timer module.
+ *
+ * Normally, initialization should be done using the APP_TIMER_INIT() macro, because that macro will both
+ *       allocate the buffers needed by the timer module (including aligning the buffers correctly)
+ *       and take care of connecting the timer module to the scheduler (if specified).
+ *
+ * @param[in]  prescaler           Value of the RTC1 PRESCALER register. Set to 0 for no prescaling.
+ * @param[in]  op_queue_size       Size of the queue holding timer operations that are pending
+ *                                 execution. Note that due to the queue implementation, this size must
+ *                                 be one more than the size that is actually needed.
+ * @param[in]  p_buffer            Pointer to memory buffer for internal use in the app_timer
+ *                                 module. The size of the buffer can be computed using the
+ *                                 APP_TIMER_BUF_SIZE() macro. The buffer must be aligned to a
+ *                                 4 byte boundary.
+ * @param[in]  evt_schedule_func   Function for passing time-out events to the scheduler. Point to
+ *                                 app_timer_evt_schedule() to connect to the scheduler. Set to NULL
+ *                                 to make the timer module call the time-out handler directly from
+ *                                 the timer interrupt handler.
+ *
+ * @retval     NRF_SUCCESS               If the module was initialized successfully.
+ * @retval     NRF_ERROR_INVALID_PARAM   If a parameter was invalid (buffer not aligned to a 4 byte
+ *                                       boundary or NULL).
+ */
+uint32_t app_timer_init(uint32_t                      prescaler,
+                        uint8_t                       op_queue_size,
+                        void *                        p_buffer,
+                        app_timer_evt_schedule_func_t evt_schedule_func);
+
+/**@brief Function for creating a timer instance.
+ *
+ * @param[in]  p_timer_id        Pointer to timer identifier.
+ * @param[in]  mode              Timer mode.
+ * @param[in]  timeout_handler   Function to be executed when the timer expires.
+ *
+ * @retval     NRF_SUCCESS               If the timer was successfully created.
+ * @retval     NRF_ERROR_INVALID_PARAM   If a parameter was invalid.
+ * @retval     NRF_ERROR_INVALID_STATE   If the application timer module has not been initialized or
+ *                                       the timer is running.
+ *
+ * @note This function does the timer allocation in the caller's context. It is also not protected
+ *       by a critical region. Therefore care must be taken not to call it from several interrupt
+ *       levels simultaneously.
+ * @note The function can be called again on the timer instance and will re-initialize the instance if
+ *       the timer is not running.
+ * @attention The FreeRTOS and RTX app_timer implementation does not allow app_timer_create to
+ *       be called on the previously initialized instance.
+ */
+uint32_t app_timer_create(app_timer_id_t const *      p_timer_id,
+                          app_timer_mode_t            mode,
+                          app_timer_timeout_handler_t timeout_handler);
+
+/**@brief Function for starting a timer.
+ *
+ * @param[in]       timer_id      Timer identifier.
+ * @param[in]       timeout_ticks Number of ticks (of RTC1, including prescaling) to time-out event
+ *                                (minimum 5 ticks).
+ * @param[in]       p_context     General purpose pointer. Will be passed to the time-out handler when
+ *                                the timer expires.
+ *
+ * @retval     NRF_SUCCESS               If the timer was successfully started.
+ * @retval     NRF_ERROR_INVALID_PARAM   If a parameter was invalid.
+ * @retval     NRF_ERROR_INVALID_STATE   If the application timer module has not been initialized or the timer
+ *                                       has not been created.
+ * @retval     NRF_ERROR_NO_MEM          If the timer operations queue was full.
+ *
+ * @note The minimum timeout_ticks value is 5.
+ * @note For multiple active timers, time-outs occurring in close proximity to each other (in the
+ *       range of 1 to 3 ticks) will have a positive jitter of maximum 3 ticks.
+ * @note When calling this method on a timer that is already running, the second start operation
+ *       is ignored.
+ */
+uint32_t app_timer_start(app_timer_id_t timer_id, uint32_t timeout_ticks, void * p_context);
+
+/**@brief Function for stopping the specified timer.
+ *
+ * @param[in]  timer_id                  Timer identifier.
+ *
+ * @retval     NRF_SUCCESS               If the timer was successfully stopped.
+ * @retval     NRF_ERROR_INVALID_PARAM   If a parameter was invalid.
+ * @retval     NRF_ERROR_INVALID_STATE   If the application timer module has not been initialized or the timer
+ *                                       has not been created.
+ * @retval     NRF_ERROR_NO_MEM          If the timer operations queue was full.
+ */
+uint32_t app_timer_stop(app_timer_id_t timer_id);
+
+/**@brief Function for stopping all running timers.
+ *
+ * @retval     NRF_SUCCESS               If all timers were successfully stopped.
+ * @retval     NRF_ERROR_INVALID_STATE   If the application timer module has not been initialized.
+ * @retval     NRF_ERROR_NO_MEM          If the timer operations queue was full.
+ */
+uint32_t app_timer_stop_all(void);
+
+/**@brief Function for returning the current value of the RTC1 counter.
+ *
+ * @return    Current value of the RTC1 counter.
+ */
+uint32_t app_timer_cnt_get(void);
+
+/**@brief Function for computing the difference between two RTC1 counter values.
+ *
+ * @param[in]  ticks_to       Value returned by app_timer_cnt_get().
+ * @param[in]  ticks_from     Value returned by app_timer_cnt_get().
+ * @param[out] p_ticks_diff   Number of ticks from ticks_from to ticks_to.
+ *
+ * @retval     NRF_SUCCESS   If the counter difference was successfully computed.
+ */
+uint32_t app_timer_cnt_diff_compute(uint32_t   ticks_to,
+                                    uint32_t   ticks_from,
+                                    uint32_t * p_ticks_diff);
+
+
+/**@brief Function for getting the maximum observed operation queue utilization.
+ *
+ * Function for tuning the module and determining OP_QUEUE_SIZE value and thus module RAM usage.
+ *
+ * @note APP_TIMER_WITH_PROFILER must be enabled to use this functionality.
+ *
+ * @return Maximum number of events in queue observed so far.
+ */
+uint8_t app_timer_op_queue_utilization_get(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // APP_TIMER_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/timer/app_timer_appsh.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,60 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "app_timer_appsh.h"
+#include "app_scheduler.h"
+
+static void app_timer_evt_get(void * p_event_data, uint16_t event_size)
+{
+    app_timer_event_t * p_timer_event = (app_timer_event_t *)p_event_data;
+
+    APP_ERROR_CHECK_BOOL(event_size == sizeof(app_timer_event_t));
+    p_timer_event->timeout_handler(p_timer_event->p_context);
+}
+
+uint32_t app_timer_evt_schedule(app_timer_timeout_handler_t timeout_handler,
+                                void *                      p_context)
+{
+    app_timer_event_t timer_event;
+
+    timer_event.timeout_handler = timeout_handler;
+    timer_event.p_context       = p_context;
+
+    return app_sched_event_put(&timer_event, sizeof(timer_event), app_timer_evt_get);
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/timer/app_timer_appsh.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,79 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ #ifndef APP_TIMER_APPSH_H
+ #define APP_TIMER_APPSH_H
+
+#include "app_timer.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define APP_TIMER_SCHED_EVT_SIZE     sizeof(app_timer_event_t)  /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). */
+
+/**@brief Macro for initializing the application timer module to use with app_scheduler.
+ *
+ * @param[in]  PRESCALER        Value of the RTC1 PRESCALER register. This will decide the
+ *                              timer tick rate. Set to 0 for no prescaling.
+ * @param[in]  OP_QUEUES_SIZE   Size of queues holding timer operations that are pending execution.
+ * @param[in]  USE_SCHEDULER    TRUE if the application is using the app_scheduler,
+ *                              FALSE otherwise.
+ *
+ * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ *       several times as long as it is from the same location, e.g. to do a reinitialization).
+ */
+#define APP_TIMER_APPSH_INIT(PRESCALER, OP_QUEUES_SIZE, USE_SCHEDULER)                 \
+    APP_TIMER_INIT(PRESCALER, OP_QUEUES_SIZE,                                          \
+                                (USE_SCHEDULER) ? app_timer_evt_schedule : NULL)
+
+typedef struct
+{
+    app_timer_timeout_handler_t timeout_handler;
+    void *                      p_context;
+} app_timer_event_t;
+
+uint32_t app_timer_evt_schedule(app_timer_timeout_handler_t timeout_handler,
+                                void *                      p_context);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // APP_TIMER_APPSH_H
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/timer/app_timer_dox_config.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,37 @@
+/**
+ *
+ * @defgroup app_timer_config Application timer functionality configuration
+ * @{
+ * @ingroup app_timer
+ */
+/** @brief Enabling app_timer module
+ *
+ *  Set to 1 to activate.
+ *
+ * @note This is an NRF_CONFIG macro.
+ */
+#define APP_TIMER_ENABLED
+
+/** @brief Enable app_timer profiling
+ *
+ *  Set to 1 to activate.
+ *
+ * @note This is an NRF_CONFIG macro.
+ */
+#define APP_TIMER_WITH_PROFILER
+
+
+/** @brief Enable RTC always on
+ *
+ * If option is enabled RTC is kept running even if there is no active timers.
+ * This option can be used when app_timer is used for timestamping.
+ *
+ *  Set to 1 to activate.
+ *
+ * @note This is an NRF_CONFIG macro.
+ */
+#define APP_TIMER_KEEPS_RTC_ACTIVE
+
+
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/timer/app_timer_rtx.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,285 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#ifdef MBED_CONF_RTOS_PRESENT
+ 
+#include "sdk_common.h"
+#if NRF_MODULE_ENABLED(APP_TIMER)
+#include "app_timer.h"
+#include <stdlib.h>
+#include "nrf.h"
+#include "nrf_soc.h"
+#include "app_error.h"
+#include "cmsis_os.h"
+#include "app_util_platform.h"
+
+#define RTC1_IRQ_PRI        APP_IRQ_PRIORITY_LOWEST    /**< Priority of the RTC1 interrupt. */
+
+#define MAX_RTC_COUNTER_VAL 0x00FFFFFF /**< Maximum value of the RTC counter. */
+
+/**@brief This structure keeps information about osTimer.*/
+typedef struct
+{
+    osTimerDef_t timerDef;
+    uint32_t     buffer[6];
+    osTimerId    id;
+}app_timer_info_t;
+
+/**@brief Store an array of timers with configuration. */
+typedef struct
+{
+    uint8_t             max_timers;         /**< The maximum number of timers*/
+    uint32_t            prescaler;
+    app_timer_info_t *  app_timers;         /**< Pointer to table of timers*/
+}app_timer_control_t;
+app_timer_control_t     app_timer_control;
+
+/**@brief This structure is defined by RTX. It keeps information about created osTimers. It is used in app_timer_start(). */
+typedef struct os_timer_cb_ 
+{                   
+    struct os_timer_cb_ *   next;               /**< Pointer to next active Timer */
+    uint8_t                 state;              /**< Timer State */
+    uint8_t                 type;               /**< Timer Type (Periodic/One-shot). */
+    uint16_t                reserved;           /**< Reserved. */
+    uint32_t                tcnt;               /**< Timer Delay Count. */
+    uint32_t                icnt;               /**< Timer Initial Count. */ 
+    void *                  arg;                /**< Timer Function Argument. */
+    const osTimerDef_t *    timer;              /**< Pointer to Timer definition. */
+} os_timer_cb;
+
+/**@brief This functions are defined by RTX.*/
+//lint --save -e10 -e19 -e526
+extern osStatus svcTimerStop(osTimerId timer_id);                        /**< Used in app_timer_stop(). */
+extern osStatus svcTimerStart(osTimerId timer_id, uint32_t millisec);    /**< Used in app_timer_start(). */
+// lint --restore
+static void * rt_id2obj (void *id)          /**< Used in app_timer_start(). This function gives information if osTimerID is valid */
+{
+    if ((uint32_t)id & 3U)
+    { 
+        return NULL; 
+    }
+
+#ifdef OS_SECTIONS_LINK_INFO
+  
+    if ((os_section_id$$Base != 0U) && (os_section_id$$Limit != 0U)) 
+    {
+        if (id  < (void *)os_section_id$$Base)  
+        { 
+            return NULL; 
+        }
+        
+        if (id >= (void *)os_section_id$$Limit) 
+        { 
+            return NULL; 
+        }
+    }
+#endif
+
+    return id;
+}
+
+
+
+uint32_t app_timer_init(uint32_t                      prescaler,
+                        uint8_t                       op_queues_size,
+                        void                        * p_buffer,
+                        app_timer_evt_schedule_func_t evt_schedule_func)
+{
+    if (p_buffer == NULL)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    app_timer_control.prescaler  = prescaler;
+    app_timer_control.app_timers = p_buffer;
+    NVIC_SetPriority(RTC1_IRQn, RTC1_IRQ_PRI);
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t app_timer_create(app_timer_id_t const      * p_timer_id,
+                          app_timer_mode_t            mode,
+                          app_timer_timeout_handler_t timeout_handler)
+{
+
+    if ((timeout_handler == NULL) || (p_timer_id == NULL))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    app_timer_info_t * p_timer_info = (app_timer_info_t *)*p_timer_id;
+    p_timer_info->timerDef.timer = p_timer_info->buffer;
+    p_timer_info->timerDef.ptimer = (os_ptimer)timeout_handler;
+
+    p_timer_info->id = osTimerCreate(&(p_timer_info->timerDef), (os_timer_type)mode, NULL);
+
+    if (p_timer_info->id)
+        return NRF_SUCCESS;
+    else
+    {
+        return NRF_ERROR_INVALID_PARAM; // This error is unspecified by rtx
+    }
+}
+
+#define osTimerRunning  2
+uint32_t app_timer_start(app_timer_id_t timer_id, uint32_t timeout_ticks, void * p_context)
+{
+    if ((timeout_ticks < APP_TIMER_MIN_TIMEOUT_TICKS))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    uint32_t timeout_ms =
+        ((uint32_t)ROUNDED_DIV(timeout_ticks * 1000 * (app_timer_control.prescaler + 1),
+                               (uint32_t)APP_TIMER_CLOCK_FREQ));
+
+    app_timer_info_t * p_timer_info = (app_timer_info_t *)timer_id;
+    if (rt_id2obj((void *)p_timer_info->id) == NULL)
+        return NRF_ERROR_INVALID_PARAM;
+
+    // Pass p_context to timer_timeout_handler
+    ((os_timer_cb *)(p_timer_info->id))->arg = p_context;
+
+    if (((os_timer_cb *)(p_timer_info->id))->state == osTimerRunning)
+    {
+        return NRF_SUCCESS;
+    }
+    // osTimerStart() returns osErrorISR if it is called in interrupt routine.
+    switch (osTimerStart((osTimerId)p_timer_info->id, timeout_ms) )
+    {
+        case osOK:
+            return NRF_SUCCESS;
+
+        case osErrorISR:
+            break;
+
+        case osErrorParameter:
+            return NRF_ERROR_INVALID_PARAM;
+
+        default:
+            return NRF_ERROR_INVALID_PARAM;
+    }
+
+    // Start timer without svcCall
+    switch (svcTimerStart((osTimerId)p_timer_info->id, timeout_ms))
+    {
+        case osOK:
+            return NRF_SUCCESS;
+
+        case osErrorISR:
+            return NRF_ERROR_INVALID_STATE;
+
+        case osErrorParameter:
+            return NRF_ERROR_INVALID_PARAM;
+
+        default:
+            return NRF_ERROR_INVALID_PARAM;
+    }
+}
+
+uint32_t app_timer_stop(app_timer_id_t timer_id)
+{
+    app_timer_info_t * p_timer_info = (app_timer_info_t *)timer_id;
+    switch (osTimerStop((osTimerId)p_timer_info->id) )
+    {
+        case osOK:
+            return NRF_SUCCESS;
+
+        case osErrorISR:
+            break;
+
+        case osErrorParameter:
+            return NRF_ERROR_INVALID_PARAM;
+
+        case osErrorResource:
+            return NRF_SUCCESS;
+
+        default:
+            return NRF_ERROR_INVALID_PARAM;
+    }
+
+    // Stop timer without svcCall
+    switch (svcTimerStop((osTimerId)p_timer_info->id))
+    {
+        case osOK:
+            return NRF_SUCCESS;
+
+        case osErrorISR:
+            return NRF_ERROR_INVALID_STATE;
+
+        case osErrorParameter:
+            return NRF_ERROR_INVALID_PARAM;
+
+        case osErrorResource:
+            return NRF_SUCCESS;
+
+        default:
+            return NRF_ERROR_INVALID_PARAM;
+    }
+}
+
+
+uint32_t app_timer_stop_all(void)
+{
+    for (int i = 0; i < app_timer_control.max_timers; i++)
+    {
+        if (app_timer_control.app_timers[i].id)
+        {
+            (void)app_timer_stop((app_timer_id_t)app_timer_control.app_timers[i].id);
+        }
+    }
+    return 0;
+}
+
+
+extern uint32_t os_tick_val(void);
+uint32_t app_timer_cnt_get(void)
+{
+    return os_tick_val();
+}
+
+
+uint32_t app_timer_cnt_diff_compute(uint32_t   ticks_to,
+                                    uint32_t   ticks_from,
+                                    uint32_t * p_ticks_diff)
+{
+    *p_ticks_diff = ((ticks_to - ticks_from) & MAX_RTC_COUNTER_VAL);
+    return NRF_SUCCESS;
+}
+#endif //NRF_MODULE_ENABLED(APP_TIMER)
+
+#endif // MBED_CONF_RTOS_PRESENT

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_error.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,146 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup app_error Common application error handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Common application error handler.
+ */
+
+#include "nrf.h"
+#include <stdio.h>
+#include "app_error.h"
+#include "nordic_common.h"
+#include "sdk_errors.h"
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+/**@brief Function for error handling, which is called when an error has occurred.
+ *
+ * @warning This handler is an example only and does not fit a final product. You need to analyze
+ *          how your product is supposed to react in case of error.
+ *
+ * @param[in] error_code  Error code supplied to the handler.
+ * @param[in] line_num    Line number where the handler is called.
+ * @param[in] p_file_name Pointer to the file name.
+ */
+
+/*lint -save -e14 */
+#if (!defined(FEATURE_BLE) && defined(__MBED__)) || !defined(__MBED__) // remove implementation for mbed-os BLE
+void app_error_handler(ret_code_t error_code, uint32_t line_num, const uint8_t * p_file_name)
+{
+    error_info_t error_info =
+    {
+        .line_num    = line_num,
+        .p_file_name = p_file_name,
+        .err_code    = error_code,
+    };
+    app_error_fault_handler(NRF_FAULT_ID_SDK_ERROR, 0, (uint32_t)(&error_info));
+
+    UNUSED_VARIABLE(error_info);
+}
+#endif
+
+/*lint -save -e14 */
+void app_error_handler_bare(ret_code_t error_code)
+{
+    error_info_t error_info =
+    {
+        .line_num    = 0,
+        .p_file_name = NULL,
+        .err_code    = error_code,
+    };
+
+    app_error_fault_handler(NRF_FAULT_ID_SDK_ERROR, 0, (uint32_t)(&error_info));
+
+    UNUSED_VARIABLE(error_info);
+}
+
+
+void app_error_save_and_stop(uint32_t id, uint32_t pc, uint32_t info)
+{
+    /* static error variables - in order to prevent removal by optimizers */
+    static volatile struct
+    {
+        uint32_t        fault_id;
+        uint32_t        pc;
+        uint32_t        error_info;
+        assert_info_t * p_assert_info;
+        error_info_t  * p_error_info;
+        ret_code_t      err_code;
+        uint32_t        line_num;
+        const uint8_t * p_file_name;
+    } m_error_data = {0};
+
+    // The following variable helps Keil keep the call stack visible, in addition, it can be set to
+    // 0 in the debugger to continue executing code after the error check.
+    volatile bool loop = true;
+    UNUSED_VARIABLE(loop);
+
+    m_error_data.fault_id   = id;
+    m_error_data.pc         = pc;
+    m_error_data.error_info = info;
+
+    switch (id)
+    {
+        case NRF_FAULT_ID_SDK_ASSERT:
+            m_error_data.p_assert_info = (assert_info_t *)info;
+            m_error_data.line_num      = m_error_data.p_assert_info->line_num;
+            m_error_data.p_file_name   = m_error_data.p_assert_info->p_file_name;
+            break;
+
+        case NRF_FAULT_ID_SDK_ERROR:
+            m_error_data.p_error_info = (error_info_t *)info;
+            m_error_data.err_code     = m_error_data.p_error_info->err_code;
+            m_error_data.line_num     = m_error_data.p_error_info->line_num;
+            m_error_data.p_file_name  = m_error_data.p_error_info->p_file_name;
+            break;
+    }
+
+    UNUSED_VARIABLE(m_error_data);
+
+    // If printing is disrupted, remove the irq calls, or set the loop variable to 0 in the debugger.
+    __disable_irq();
+    while (loop);
+
+    __enable_irq();
+}
+
+/*lint -restore */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_error.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,238 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup app_error Common application error handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Common application error handler and macros for utilizing a common error handler.
+ */
+
+#ifndef APP_ERROR_H__
+#define APP_ERROR_H__
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdbool.h>
+#include "nrf.h"
+#include "sdk_errors.h"
+#include "nordic_common.h"
+#include "app_error_weak.h"
+#ifdef ANT_STACK_SUPPORT_REQD
+#include "ant_error.h"
+#endif // ANT_STACK_SUPPORT_REQD
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NRF_FAULT_ID_SDK_RANGE_START 0x00004000 /**< The start of the range of error IDs defined in the SDK. */
+
+/**@defgroup APP_ERROR_FAULT_IDS Fault ID types
+ * @{ */
+#define NRF_FAULT_ID_SDK_ERROR       NRF_FAULT_ID_SDK_RANGE_START + 1 /**< An error stemming from a call to @ref APP_ERROR_CHECK or @ref APP_ERROR_CHECK_BOOL. The info parameter is a pointer to an @ref error_info_t variable. */
+#define NRF_FAULT_ID_SDK_ASSERT      NRF_FAULT_ID_SDK_RANGE_START + 2 /**< An error stemming from a call to ASSERT (nrf_assert.h). The info parameter is a pointer to an @ref assert_info_t variable. */
+/**@} */
+
+/**@brief Structure containing info about an error of the type @ref NRF_FAULT_ID_SDK_ERROR.
+ */
+typedef struct
+{
+    uint16_t        line_num;    /**< The line number where the error occurred. */
+    uint8_t const * p_file_name; /**< The file in which the error occurred. */
+    uint32_t        err_code;    /**< The error code representing the error that occurred. */
+} error_info_t;
+
+/**@brief Structure containing info about an error of the type @ref NRF_FAULT_ID_SDK_ASSERT.
+ */
+typedef struct
+{
+    uint16_t        line_num;    /**< The line number where the error occurred. */
+    uint8_t const * p_file_name; /**< The file in which the error occurred. */
+} assert_info_t;
+
+/**@brief Function for error handling, which is called when an error has occurred.
+ *
+ * @param[in] error_code  Error code supplied to the handler.
+ * @param[in] line_num    Line number where the handler is called.
+ * @param[in] p_file_name Pointer to the file name.
+ */
+void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name);
+
+/**@brief Function for error handling, which is called when an error has occurred.
+ *
+ * @param[in] error_code  Error code supplied to the handler.
+ */
+void app_error_handler_bare(ret_code_t error_code);
+
+/**@brief       Function for saving the parameters and entering an eternal loop, for debug purposes.
+ *
+ * @param[in] id    Fault identifier. See @ref NRF_FAULT_IDS.
+ * @param[in] pc    The program counter of the instruction that triggered the fault, or 0 if
+ *                  unavailable.
+ * @param[in] info  Optional additional information regarding the fault. Refer to each fault
+ *                  identifier for details.
+ */
+void app_error_save_and_stop(uint32_t id, uint32_t pc, uint32_t info);
+
+/**@brief       Function for printing all error info (using nrf_log).
+ *
+ * @details     Nrf_log library must be initialized using NRF_LOG_INIT macro before calling
+ *              this function.
+ *
+ * @param[in] id    Fault identifier. See @ref NRF_FAULT_IDS.
+ * @param[in] pc    The program counter of the instruction that triggered the fault, or 0 if
+ *                  unavailable.
+ * @param[in] info  Optional additional information regarding the fault. Refer to each fault
+ *                  identifier for details.
+ */
+static __INLINE void app_error_log(uint32_t id, uint32_t pc, uint32_t info)
+{
+    switch (id)
+    {
+        case NRF_FAULT_ID_SDK_ASSERT:
+            //NRF_LOG_INFO(NRF_LOG_COLOR_RED "\r\n*** ASSERTION FAILED ***\r\n");
+            if (((assert_info_t *)(info))->p_file_name)
+            {
+               // NRF_LOG_INFO(NRF_LOG_COLOR_WHITE "Line Number: %u\r\n", (unsigned int) ((assert_info_t *)(info))->line_num);
+                //NRF_LOG_INFO("File Name:   %s\r\n", ((assert_info_t *)(info))->p_file_name);
+            }
+            //NRF_LOG_INFO(NRF_LOG_COLOR_DEFAULT "\r\n");
+            break;
+
+        case NRF_FAULT_ID_SDK_ERROR:
+            //NRF_LOG_INFO(NRF_LOG_COLOR_RED "\r\n*** APPLICATION ERROR *** \r\n" NRF_LOG_COLOR_WHITE);
+            if (((error_info_t *)(info))->p_file_name)
+            {
+                //NRF_LOG_INFO("Line Number: %u\r\n", (unsigned int) ((error_info_t *)(info))->line_num);
+                //NRF_LOG_INFO("File Name:   %s\r\n", ((error_info_t *)(info))->p_file_name);
+            }
+            //NRF_LOG_INFO("Error Code:  0x%X\r\n" NRF_LOG_COLOR_DEFAULT "\r\n", (unsigned int) ((error_info_t *)(info))->err_code);
+            break;
+    }
+}
+
+/**@brief       Function for printing all error info (using printf).
+ *
+ * @param[in] id    Fault identifier. See @ref NRF_FAULT_IDS.
+ * @param[in] pc    The program counter of the instruction that triggered the fault, or 0 if
+ *                  unavailable.
+ * @param[in] info  Optional additional information regarding the fault. Refer to each fault
+ *                  identifier for details.
+ */
+//lint -save -e438
+static __INLINE void app_error_print(uint32_t id, uint32_t pc, uint32_t info)
+{
+    unsigned int tmp = id;
+    printf("app_error_print():\r\n");
+    printf("Fault identifier:  0x%X\r\n", tmp);
+    printf("Program counter:   0x%X\r\n", tmp = pc);
+    printf("Fault information: 0x%X\r\n", tmp = info);
+
+    switch (id)
+    {
+        case NRF_FAULT_ID_SDK_ASSERT:
+            printf("Line Number: %u\r\n", tmp = ((assert_info_t *)(info))->line_num);
+            printf("File Name:   %s\r\n",       ((assert_info_t *)(info))->p_file_name);
+            break;
+
+        case NRF_FAULT_ID_SDK_ERROR:
+            printf("Line Number: %u\r\n",   tmp = ((error_info_t *)(info))->line_num);
+            printf("File Name:   %s\r\n",         ((error_info_t *)(info))->p_file_name);
+            printf("Error Code:  0x%X\r\n", tmp = ((error_info_t *)(info))->err_code);
+            break;
+    }
+}
+//lint -restore
+
+
+/**@brief Macro for calling error handler function.
+ *
+ * @param[in] ERR_CODE Error code supplied to the error handler.
+ */
+#ifdef DEBUG
+#define APP_ERROR_HANDLER(ERR_CODE)                                    \
+    do                                                                 \
+    {                                                                  \
+        app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__);  \
+    } while (0)
+#else
+#define APP_ERROR_HANDLER(ERR_CODE)                                    \
+    do                                                                 \
+    {                                                                  \
+        app_error_handler_bare((ERR_CODE));                            \
+    } while (0)
+#endif
+/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS.
+ *
+ * @param[in] ERR_CODE Error code supplied to the error handler.
+ */
+#define APP_ERROR_CHECK(ERR_CODE)                           \
+    do                                                      \
+    {                                                       \
+        const uint32_t LOCAL_ERR_CODE = (ERR_CODE);         \
+        if (LOCAL_ERR_CODE != NRF_SUCCESS)                  \
+        {                                                   \
+            APP_ERROR_HANDLER(LOCAL_ERR_CODE);              \
+        }                                                   \
+    } while (0)
+
+/**@brief Macro for calling error handler function if supplied boolean value is false.
+ *
+ * @param[in] BOOLEAN_VALUE Boolean value to be evaluated.
+ */
+#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE)                   \
+    do                                                        \
+    {                                                         \
+        const uint32_t LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \
+        if (!LOCAL_BOOLEAN_VALUE)                             \
+        {                                                     \
+            APP_ERROR_HANDLER(0);                             \
+        }                                                     \
+    } while (0)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // APP_ERROR_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_error_weak.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,65 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "app_error.h"
+
+//#define NRF_LOG_MODULE_NAME "APP_ERROR"
+#include "nrf_log.h"
+#include "nrf_log_ctrl.h"
+/*lint -save -e14 */
+
+/**
+ * Function is implemented as weak so that it can be overwritten by custom application error handler
+ * when needed.
+ */
+__WEAK void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info)
+{
+    NRF_LOG_ERROR("Fatal\r\n");
+    NRF_LOG_FINAL_FLUSH();
+    // On assert, the system can only recover with a reset.
+#ifndef DEBUG
+    NRF_LOG_INFO("Hit weak handler\r\n");
+    NVIC_SystemReset();
+#else
+    app_error_save_and_stop(id, pc, info);
+#endif // DEBUG
+}
+
+/*lint -restore */
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_error_weak.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,84 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef APP_ERROR_WEAK_H__
+#define APP_ERROR_WEAK_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @file
+ *
+ * @defgroup app_error Common application error handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Common application error handler.
+ */
+
+/**@brief       Callback function for errors, asserts, and faults.
+ *
+ * @details     This function is called every time an error is raised in app_error, nrf_assert, or
+ *              in the SoftDevice. Information about the error can be found in the @p info
+ *              parameter.
+ *
+ *              See also @ref nrf_fault_handler_t for more details.
+ *
+ * @note        The function is implemented as weak so that it can be redefined by a custom error
+ *              handler when needed.
+ *
+ * @param[in] id    Fault identifier. See @ref NRF_FAULT_IDS.
+ * @param[in] pc    The program counter of the instruction that triggered the fault, or 0 if
+ *                  unavailable.
+ * @param[in] info  Optional additional information regarding the fault. The value of the @p id
+ *                  parameter dictates how to interpret this parameter. Refer to the documentation
+ *                  for each fault identifier (@ref NRF_FAULT_IDS and @ref APP_ERROR_FAULT_IDS) for
+ *                  details about interpreting @p info.
+ */
+void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info);
+
+
+/** @} */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // APP_ERROR_WEAK_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_util.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,1016 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup app_util Utility Functions and Definitions
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Various types and definitions available to all applications.
+ */
+
+#ifndef APP_UTIL_H__
+#define APP_UTIL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "compiler_abstraction.h"
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//lint -save -e27 -e10 -e19
+#if defined ( __CC_ARM )
+extern char STACK$$Base;
+extern char STACK$$Length;
+#define STACK_BASE    &STACK$$Base
+#define STACK_TOP    ((void*)((uint32_t)STACK_BASE + (uint32_t)&STACK$$Length))
+#elif defined ( __ICCARM__ )
+extern char CSTACK$$Base;
+extern char CSTACK$$Length;
+#define STACK_BASE    &CSTACK$$Base
+#define STACK_TOP    ((void*)((uint32_t)STACK_BASE + (uint32_t)&CSTACK$$Length))
+#elif defined   ( __GNUC__ )
+extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
+#define STACK_BASE    &__StackLimit
+#define STACK_TOP     &__StackTop
+#endif
+//lint -restore
+
+enum
+{
+    UNIT_0_625_MS = 625,                                /**< Number of microseconds in 0.625 milliseconds. */
+    UNIT_1_25_MS  = 1250,                               /**< Number of microseconds in 1.25 milliseconds. */
+    UNIT_10_MS    = 10000                               /**< Number of microseconds in 10 milliseconds. */
+};
+
+
+/**@brief Implementation specific macro for delayed macro expansion used in string concatenation
+*
+* @param[in]   lhs   Left hand side in concatenation
+* @param[in]   rhs   Right hand side in concatenation
+*/
+#define STRING_CONCATENATE_IMPL(lhs, rhs) lhs ## rhs
+
+
+/**@brief Macro used to concatenate string using delayed macro expansion
+*
+* @note This macro will delay concatenation until the expressions have been resolved
+*
+* @param[in]   lhs   Left hand side in concatenation
+* @param[in]   rhs   Right hand side in concatenation
+*/
+#define STRING_CONCATENATE(lhs, rhs) STRING_CONCATENATE_IMPL(lhs, rhs)
+
+
+// Disable lint-warnings/errors for STATIC_ASSERT_MSG
+//lint --emacro(10, STATIC_ASSERT_MSG)
+//lint --emacro(18, STATIC_ASSERT_MSG)
+//lint --emacro(19, STATIC_ASSERT_MSG)
+//lint --emacro(30, STATIC_ASSERT_MSG)
+//lint --emacro(37, STATIC_ASSERT_MSG)
+//lint --emacro(42, STATIC_ASSERT_MSG)
+//lint --emacro(26, STATIC_ASSERT_MSG)
+//lint --emacro(102,STATIC_ASSERT_MSG)
+//lint --emacro(533,STATIC_ASSERT_MSG)
+//lint --emacro(534,STATIC_ASSERT_MSG)
+//lint --emacro(132,STATIC_ASSERT_MSG)
+//lint --emacro(414,STATIC_ASSERT_MSG)
+//lint --emacro(578,STATIC_ASSERT_MSG)
+//lint --emacro(628,STATIC_ASSERT_MSG)
+//lint --emacro(648,STATIC_ASSERT_MSG)
+//lint --emacro(830,STATIC_ASSERT_MSG)
+
+
+/**@brief Macro for doing static (i.e. compile time) assertion.
+*
+* @note If the EXPR isn't resolvable, then the error message won't be shown.
+*
+* @note The output of STATIC_ASSERT_MSG will be different across different compilers.
+*
+* @param[in] EXPR Constant expression to be verified.
+* @param[in] MSG  Name of the static assert.
+*/
+#if defined(__COUNTER__)
+
+    #define STATIC_ASSERT_MSG(EXPR, MSG) \
+        ;enum { STRING_CONCATENATE(MSG, __COUNTER__) = 1 / (!!(EXPR)) }
+
+#else
+
+    #define STATIC_ASSERT_MSG(EXPR, MSG) \
+        ;enum { STRING_CONCATENATE(MSG, __LINE__) = 1 / (!!(EXPR)) }
+
+#endif
+
+
+/**@brief Macro for doing static (i.e. compile time) assertion.
+*
+* @note If the EXPR isn't resolvable, then the error message won't be shown.
+*
+* @note The output of STATIC_ASSERT will be different across different compilers.
+*
+* @param[in] EXPR Constant expression to be verified.
+*/
+#define STATIC_ASSERT(EXPR) STATIC_ASSERT_MSG((EXPR), static_assert_)
+
+
+/**@brief Implementation details for NUM_VAR_ARGS */
+#define NUM_VA_ARGS_IMPL(                              \
+    _0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10,       \
+    _11, _12, _13, _14, _15, _16, _17, _18, _19, _20,  \
+    _21, _22, _23, _24, _25, _26, _27, _28, _29, _30,  \
+    _31, _32, _33, _34, _35, _36, _37, _38, _39, _40,  \
+    _41, _42, _43, _44, _45, _46, _47, _48, _49, _50,  \
+    _51, _52, _53, _54, _55, _56, _57, _58, _59, _60,  \
+    _61, _62, N, ...) N
+
+
+/**@brief Macro to get the number of arguments in a call variadic macro call
+ *
+ * param[in]    ...     List of arguments
+ *
+ * @retval  Number of variadic arguments in the argument list
+ */
+#define NUM_VA_ARGS(...) NUM_VA_ARGS_IMPL(__VA_ARGS__, 63, 62, 61,  \
+    60, 59, 58, 57, 56, 55, 54, 53, 52, 51,                         \
+    50, 49, 48, 47, 46, 45, 44, 43, 42, 41,                         \
+    40, 39, 38, 37, 36, 35, 34, 33, 32, 31,                         \
+    30, 29, 28, 27, 26, 25, 24, 23, 22, 21,                         \
+    20, 19, 18, 17, 16, 15, 14, 13, 12, 11,                         \
+    10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
+
+/**@brief Implementation details for NUM_VAR_ARGS */
+#define NUM_VA_ARGS_LESS_1_IMPL(                       \
+    _ignored,                                          \
+    _0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10,       \
+    _11, _12, _13, _14, _15, _16, _17, _18, _19, _20,  \
+    _21, _22, _23, _24, _25, _26, _27, _28, _29, _30,  \
+    _31, _32, _33, _34, _35, _36, _37, _38, _39, _40,  \
+    _41, _42, _43, _44, _45, _46, _47, _48, _49, _50,  \
+    _51, _52, _53, _54, _55, _56, _57, _58, _59, _60,  \
+    _61, _62, N, ...) N
+
+/**@brief Macro to get the number of arguments in a call variadic macro call.
+ * First argument is not counted.
+ *
+ * param[in]    ...     List of arguments
+ *
+ * @retval  Number of variadic arguments in the argument list
+ */
+#define NUM_VA_ARGS_LESS_1(...) NUM_VA_ARGS_LESS_1_IMPL(__VA_ARGS__, 63, 62, 61,  \
+    60, 59, 58, 57, 56, 55, 54, 53, 52, 51,                         \
+    50, 49, 48, 47, 46, 45, 44, 43, 42, 41,                         \
+    40, 39, 38, 37, 36, 35, 34, 33, 32, 31,                         \
+    30, 29, 28, 27, 26, 25, 24, 23, 22, 21,                         \
+    20, 19, 18, 17, 16, 15, 14, 13, 12, 11,                         \
+    10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, ~)
+
+
+/**@brief type for holding an encoded (i.e. little endian) 16 bit unsigned integer. */
+typedef uint8_t uint16_le_t[2];
+
+/**@brief Type for holding an encoded (i.e. little endian) 32 bit unsigned integer. */
+typedef uint8_t uint32_le_t[4];
+
+/**@brief Byte array type. */
+typedef struct
+{
+    uint16_t  size;                 /**< Number of array entries. */
+    uint8_t * p_data;               /**< Pointer to array entries. */
+} uint8_array_t;
+
+
+/**@brief Macro for performing rounded integer division (as opposed to truncating the result).
+ *
+ * @param[in]   A   Numerator.
+ * @param[in]   B   Denominator.
+ *
+ * @return      Rounded (integer) result of dividing A by B.
+ */
+#define ROUNDED_DIV(A, B) (((A) + ((B) / 2)) / (B))
+
+
+/**@brief Macro for checking if an integer is a power of two.
+ *
+ * @param[in]   A   Number to be tested.
+ *
+ * @return      true if value is power of two.
+ * @return      false if value not power of two.
+ */
+#define IS_POWER_OF_TWO(A) ( ((A) != 0) && ((((A) - 1) & (A)) == 0) )
+
+
+/**@brief Macro for converting milliseconds to ticks.
+ *
+ * @param[in] TIME          Number of milliseconds to convert.
+ * @param[in] RESOLUTION    Unit to be converted to in [us/ticks].
+ */
+#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION))
+
+
+/**@brief Macro for performing integer division, making sure the result is rounded up.
+ *
+ * @details One typical use for this is to compute the number of objects with size B is needed to
+ *          hold A number of bytes.
+ *
+ * @param[in]   A   Numerator.
+ * @param[in]   B   Denominator.
+ *
+ * @return      Integer result of dividing A by B, rounded up.
+ */
+#define CEIL_DIV(A, B)      \
+    (((A) + (B) - 1) / (B))
+
+
+/**@brief Macro for creating a buffer aligned to 4 bytes.
+ *
+ * @param[in]   NAME        Name of the buffor.
+ * @param[in]   MIN_SIZE    Size of this buffor (it will be rounded up to multiples of 4 bytes).
+ */
+#define WORD_ALIGNED_MEM_BUFF(NAME, MIN_SIZE) static uint32_t NAME[CEIL_DIV(MIN_SIZE, sizeof(uint32_t))]
+
+
+/**@brief Macro for calculating the number of words that are needed to hold a number of bytes.
+ *
+ * @details Adds 3 and divides by 4.
+ *
+ * @param[in]  n_bytes  The number of bytes.
+ *
+ * @return The number of words that @p n_bytes take up (rounded up).
+ */
+#define BYTES_TO_WORDS(n_bytes) (((n_bytes) + 3) >> 2)
+
+
+/**@brief The number of bytes in a word.
+ */
+#define BYTES_PER_WORD (4)
+
+
+/**@brief Macro for increasing a number to the nearest (larger) multiple of another number.
+ *
+ * @param[in]  alignment  The number to align to.
+ * @param[in]  number     The number to align (increase).
+ *
+ * @return The aligned (increased) @p number.
+ */
+#define ALIGN_NUM(alignment, number) ((number - 1) + alignment - ((number - 1) % alignment))
+
+/**@brief Macro for getting first of 2 parameters.
+ *
+ * @param[in] a1    First parameter.
+ * @param[in] a2    Second parameter.
+ */
+#define GET_ARG_1(a1, a2) a1
+
+/**@brief Macro for getting second of 2 parameters.
+ *
+ * @param[in] a1    First parameter.
+ * @param[in] a2    Second parameter.
+ */
+#define GET_ARG_2(a1, a2) a2
+
+
+/**@brief Container of macro (borrowed from Linux kernel).
+ *
+ * This macro returns parent structure address basing on child member address.
+ *
+ * @param ptr       Address of child type.
+ * @param type      Type of parent structure.
+ * @param member    Name of child field in parent structure.
+ *
+ * @return Parent structure address.
+ * */
+#define CONTAINER_OF(ptr, type, member)                 \
+        (type *)((char *)ptr - offsetof(type, member))
+
+
+/**
+ * @brief Define Bit-field mask
+ *
+ * Macro that defined the mask with selected number of bits set, starting from
+ * provided bit number.
+ *
+ * @param[in] bcnt Number of bits in the bit-field
+ * @param[in] boff Lowest bit number
+ */
+#define BF_MASK(bcnt, boff) ( ((1U << (bcnt)) - 1U) << (boff) )
+
+/**
+ * @brief Get bit-field
+ *
+ * Macro that extracts selected bit-field from provided value
+ *
+ * @param[in] val  Value from witch selected bit-field would be extracted
+ * @param[in] bcnt Number of bits in the bit-field
+ * @param[in] boff Lowest bit number
+ *
+ * @return Value of the selected bits
+ */
+#define BF_GET(val, bcnt, boff) ( ( (val) & BF_MASK((bcnt), (boff)) ) >> (boff) )
+
+/**
+ * @brief Create bit-field value
+ *
+ * Value is masked and shifted to match given bit-field
+ *
+ * @param[in] val  Value to set on bit-field
+ * @param[in] bcnt Number of bits for bit-field
+ * @param[in] boff Offset of bit-field
+ *
+ * @return Value positioned of given bit-field.
+ */
+#define BF_VAL(val, bcnt, boff) ( (((uint32_t)(val)) << (boff)) & BF_MASK(bcnt, boff) )
+
+/**
+ * @name Configuration of complex bit-field
+ *
+ * @sa BF_CX
+ * @{
+ */
+/** @brief Position of bit count in complex bit-field value */
+#define BF_CX_BCNT_POS  0U
+/** @brief Mask of bit count in complex bit-field value */
+#define BF_CX_BCNT_MASK (0xffU << BF_CX_BCNT_POS)
+/** @brief Position of bit position in complex bit-field value */
+#define BF_CX_BOFF_POS  8U
+/** @brief Mask of bit position in complex bit-field value */
+#define BF_CX_BOFF_MASK (0xffU << BF_CX_BOFF_POS)
+/** @} */
+
+/**
+ * @brief Define complex bit-field
+ *
+ * Complex bit-field would contain its position and size in one number.
+ * @sa BF_CX_MASK
+ * @sa BF_CX_POS
+ * @sa BF_CX_GET
+ *
+ * @param[in] bcnt Number of bits in the bit-field
+ * @param[in] boff Lowest bit number
+ *
+ * @return The single number that describes the bit-field completely.
+ */
+#define BF_CX(bcnt, boff) ( ((((uint32_t)(bcnt)) << BF_CX_BCNT_POS) & BF_CX_BCNT_MASK) | ((((uint32_t)(boff)) << BF_CX_BOFF_POS) & BF_CX_BOFF_MASK) )
+
+/**
+ * @brief Get number of bits in bit-field
+ *
+ * @sa BF_CX
+ *
+ * @param bf_cx Complex bit-field
+ *
+ * @return Number of bits in given bit-field
+ */
+#define BF_CX_BCNT(bf_cx) ( ((bf_cx) & BF_CX_BCNT_MASK) >> BF_CX_BCNT_POS )
+
+/**
+ * @brief Get lowest bit number in the field
+ *
+ * @sa BF_CX
+ *
+ * @param[in] bf_cx Complex bit-field
+ *
+ * @return Lowest bit number in given bit-field
+ */
+#define BF_CX_BOFF(bf_cx) ( ((bf_cx) & BF_CX_BOFF_MASK) >> BF_CX_BOFF_POS )
+
+/**
+ * @brief Get bit mask of the selected field
+ *
+ * @sa BF_CX
+ *
+ * @param[in] bf_cx Complex bit-field
+ *
+ * @return Mask of given bit-field
+ */
+#define BF_CX_MASK(bf_cx) BF_MASK(BF_CX_BCNT(bf_cx), BF_CX_BOFF(bf_cx))
+
+/**
+ * @brief Get bit-field
+ *
+ * Macro that extracts selected bit-field from provided value.
+ * Bit-field is given as a complex value.
+ *
+ * @sa BF_CX
+ * @sa BF_GET
+ *
+ * @param[in] val   Value from witch selected bit-field would be extracted
+ * @param[in] bf_cx Complex bit-field
+ *
+ * @return Value of the selected bits.
+ */
+#define BF_CX_GET(val, bf_cx) BF_GET(val, BF_CX_BCNT(bf_cx), BF_CX_BOFF(bf_cx))
+
+/**
+ * @brief Create bit-field value
+ *
+ * Value is masked and shifted to match given bit-field.
+ *
+ * @param[in] val  Value to set on bit-field
+ * @param[in] bf_cx Complex bit-field
+ *
+ * @return Value positioned of given bit-field.
+ */
+#define BF_CX_VAL(val, bf_cx) BF_VAL(val, BF_CX_BCNT(bf_cx), BF_CX_BOFF(bf_cx))
+
+/**
+ * @brief Extracting data from the brackets
+ *
+ * This macro get rid of brackets around the argument.
+ * It can be used to pass multiple arguments in logical one argument to a macro.
+ * Call it with arguments inside brackets:
+ * @code
+ * #define ARGUMENTS (a, b, c)
+ * BRACKET_EXTRACT(ARGUMENTS)
+ * @endcode
+ * It would produce:
+ * @code
+ * a, b, c
+ * @endcode
+ *
+ * @param a Argument with anything inside brackets
+ * @return Anything that appears inside the brackets of the argument
+ *
+ * @note
+ * The argument of the macro have to be inside brackets.
+ * In other case the compilation would fail.
+ */
+#define BRACKET_EXTRACT(a)  BRACKET_EXTRACT_(a)
+#define BRACKET_EXTRACT_(a) BRACKET_EXTRACT__ a
+#define BRACKET_EXTRACT__(...) __VA_ARGS__
+
+
+/**
+ * @brief Check if number of parameters is more than 1
+ *
+ * @param ... Arguments to count
+ *
+ * @return 0 If argument count is <= 1
+ * @return 1 If argument count is > 1
+ *
+ * @sa NUM_VA_ARGS
+ * @sa NUM_IS_MORE_THAN_1
+ */
+#define NUM_VA_ARGS_IS_MORE_THAN_1(...) NUM_IS_MORE_THAN_1(NUM_VA_ARGS(__VA_ARGS__))
+
+/**
+ * @brief Check if given numeric value is bigger than 1
+ *
+ * This macro accepts numeric value, that may be the result of argument expansion.
+ * This numeric value is then converted to 0 if it is lover than 1 or to 1 if
+ * its value is higher than 1.
+ * The generated result can be used to glue it into other macro mnemonic name.
+ *
+ * @param N Numeric value to check
+ *
+ * @return 0 If argument is <= 1
+ * @return 1 If argument is > 1
+ *
+ * @note Any existing definition of a form NUM_IS_MORE_THAN_1_PROBE_[N] can
+ *       broke the result of this macro
+ */
+#define NUM_IS_MORE_THAN_1(N) NUM_IS_MORE_THAN_1_(N)
+#define NUM_IS_MORE_THAN_1_(N)  NUM_IS_MORE_THAN_1_PROBE_(NUM_IS_MORE_THAN_1_PROBE_ ## N, 1)
+#define NUM_IS_MORE_THAN_1_PROBE_(...) GET_VA_ARG_1(GET_ARGS_AFTER_1(__VA_ARGS__))
+#define NUM_IS_MORE_THAN_1_PROBE_0 ~, 0
+#define NUM_IS_MORE_THAN_1_PROBE_1 ~, 0
+
+/**
+ * @brief Get the first argument
+ *
+ * @param ... Arguments to select
+ *
+ * @return First argument or empty if no arguments are provided
+ */
+#define GET_VA_ARG_1(...) GET_VA_ARG_1_(__VA_ARGS__, ) // Make sure that also for 1 argument it works
+#define GET_VA_ARG_1_(a1, ...) a1
+
+/**
+ * @brief Get all the arguments but the first one
+ *
+ * @param ... Arguments to select
+ *
+ * @return All arguments after the first one or empty if less than 2 arguments are provided
+ */
+#define GET_ARGS_AFTER_1(...) GET_ARGS_AFTER_1_(__VA_ARGS__, ) // Make sure that also for 1 argument it works
+#define GET_ARGS_AFTER_1_(a1, ...) __VA_ARGS__
+
+/**
+ * @brief Size of a field in declared structure
+ *
+ * Macro that returns the size of the structure field.
+ * @param struct_type Variable type to get the field size from
+ * @param field Field name to analyze. It can be even field inside field (field.somethingelse.and_another).
+ *
+ * @return Size of the field
+ */
+#define FIELD_SIZE(struct_type, field) sizeof(((struct struct_type*)NULL)->field)
+
+/**
+ * @brief Number of elements in field array in declared structure
+ *
+ * Macro that returns number of elementy in structure field.
+ * @param struct_type Variable type to get the field size from
+ * @param field Field name to analyze.
+ *
+ * @return Number of elements in field array
+ *
+ * @sa FIELD_SIZE
+ */
+#define FIELD_ARRAY_SIZE(struct_type, field) (FIELD_SIZE(struct_type, field) / FIELD_SIZE(struct_type, field[0]))
+
+/**
+ * @brief Mapping macro
+ *
+ * Macro that process all arguments using given macro
+ *
+ * @param ... Macro name to be used for argument processing followed by arguments to process.
+ *            Macro should have following form: MACRO(argument)
+ *
+ * @return All arguments processed by given macro
+ */
+#define MACRO_MAP(...) MACRO_MAP_(__VA_ARGS__)
+#define MACRO_MAP_(...) MACRO_MAP_N(NUM_VA_ARGS_LESS_1(__VA_ARGS__), __VA_ARGS__) // To make sure it works also for 2 arguments in total
+
+/**
+ * @brief Mapping macro, recursive version
+ *
+ *  Can be used in @ref MACRO_MAP macro
+ */
+#define MACRO_MAP_REC(...) MACRO_MAP_REC_(__VA_ARGS__)
+#define MACRO_MAP_REC_(...) MACRO_MAP_REC_N(NUM_VA_ARGS_LESS_1(__VA_ARGS__), __VA_ARGS__) // To make sure it works also for 2 arguments in total
+/**
+ * @brief Mapping N arguments macro
+ *
+ * Macro similar to @ref MACRO_MAP but maps exact number of arguments.
+ * If there is more arguments given, the rest would be ignored.
+ *
+ * @param N   Number of arguments to map
+ * @param ... Macro name to be used for argument processing followed by arguments to process.
+ *            Macro should have following form: MACRO(argument)
+ *
+ * @return Selected number of arguments processed by given macro
+ */
+#define MACRO_MAP_N(N, ...) MACRO_MAP_N_(N, __VA_ARGS__)
+#define MACRO_MAP_N_(N, ...) CONCAT_2(MACRO_MAP_, N)(__VA_ARGS__, )
+
+/**
+ * @brief Mapping N arguments macro, recursive version
+ *
+ *  Can be used in @ref MACRO_MAP_N macro
+ */
+#define MACRO_MAP_REC_N(N, ...) MACRO_MAP_REC_N_(N, __VA_ARGS__)
+#define MACRO_MAP_REC_N_(N, ...) CONCAT_2(MACRO_MAP_REC_, N)(__VA_ARGS__, )
+
+#define MACRO_MAP_0(           ...)
+#define MACRO_MAP_1( macro, a, ...) macro(a)
+#define MACRO_MAP_2( macro, a, ...) macro(a) MACRO_MAP_1 (macro, __VA_ARGS__, )
+#define MACRO_MAP_3( macro, a, ...) macro(a) MACRO_MAP_2 (macro, __VA_ARGS__, )
+#define MACRO_MAP_4( macro, a, ...) macro(a) MACRO_MAP_3 (macro, __VA_ARGS__, )
+#define MACRO_MAP_5( macro, a, ...) macro(a) MACRO_MAP_4 (macro, __VA_ARGS__, )
+#define MACRO_MAP_6( macro, a, ...) macro(a) MACRO_MAP_5 (macro, __VA_ARGS__, )
+#define MACRO_MAP_7( macro, a, ...) macro(a) MACRO_MAP_6 (macro, __VA_ARGS__, )
+#define MACRO_MAP_8( macro, a, ...) macro(a) MACRO_MAP_7 (macro, __VA_ARGS__, )
+#define MACRO_MAP_9( macro, a, ...) macro(a) MACRO_MAP_8 (macro, __VA_ARGS__, )
+#define MACRO_MAP_10(macro, a, ...) macro(a) MACRO_MAP_9 (macro, __VA_ARGS__, )
+#define MACRO_MAP_11(macro, a, ...) macro(a) MACRO_MAP_10(macro, __VA_ARGS__, )
+#define MACRO_MAP_12(macro, a, ...) macro(a) MACRO_MAP_11(macro, __VA_ARGS__, )
+#define MACRO_MAP_13(macro, a, ...) macro(a) MACRO_MAP_12(macro, __VA_ARGS__, )
+#define MACRO_MAP_14(macro, a, ...) macro(a) MACRO_MAP_13(macro, __VA_ARGS__, )
+#define MACRO_MAP_15(macro, a, ...) macro(a) MACRO_MAP_14(macro, __VA_ARGS__, )
+
+#define MACRO_MAP_REC_0(           ...)
+#define MACRO_MAP_REC_1( macro, a, ...) macro(a)
+#define MACRO_MAP_REC_2( macro, a, ...) macro(a) MACRO_MAP_REC_1 (macro, __VA_ARGS__, )
+#define MACRO_MAP_REC_3( macro, a, ...) macro(a) MACRO_MAP_REC_2 (macro, __VA_ARGS__, )
+#define MACRO_MAP_REC_4( macro, a, ...) macro(a) MACRO_MAP_REC_3 (macro, __VA_ARGS__, )
+#define MACRO_MAP_REC_5( macro, a, ...) macro(a) MACRO_MAP_REC_4 (macro, __VA_ARGS__, )
+#define MACRO_MAP_REC_6( macro, a, ...) macro(a) MACRO_MAP_REC_5 (macro, __VA_ARGS__, )
+#define MACRO_MAP_REC_7( macro, a, ...) macro(a) MACRO_MAP_REC_6 (macro, __VA_ARGS__, )
+#define MACRO_MAP_REC_8( macro, a, ...) macro(a) MACRO_MAP_REC_7 (macro, __VA_ARGS__, )
+#define MACRO_MAP_REC_9( macro, a, ...) macro(a) MACRO_MAP_REC_8 (macro, __VA_ARGS__, )
+#define MACRO_MAP_REC_10(macro, a, ...) macro(a) MACRO_MAP_REC_9 (macro, __VA_ARGS__, )
+#define MACRO_MAP_REC_11(macro, a, ...) macro(a) MACRO_MAP_REC_10(macro, __VA_ARGS__, )
+#define MACRO_MAP_REC_12(macro, a, ...) macro(a) MACRO_MAP_REC_11(macro, __VA_ARGS__, )
+#define MACRO_MAP_REC_13(macro, a, ...) macro(a) MACRO_MAP_REC_12(macro, __VA_ARGS__, )
+#define MACRO_MAP_REC_14(macro, a, ...) macro(a) MACRO_MAP_REC_13(macro, __VA_ARGS__, )
+#define MACRO_MAP_REC_15(macro, a, ...) macro(a) MACRO_MAP_REC_14(macro, __VA_ARGS__, )
+
+/**
+ * @brief Mapping macro with current index
+ *
+ * Basically macro similar to @ref MACRO_MAP, but the processing function would get an argument
+ * and current argument index (beginning from 0).
+ *
+ * @param ... Macro name to be used for argument processing followed by arguments to process.
+ *            Macro should have following form: MACRO(argument, index)
+ * @return All arguments processed by given macro
+ */
+#define MACRO_MAP_FOR(...) MACRO_MAP_FOR_(__VA_ARGS__)
+#define MACRO_MAP_FOR_N_LIST 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#define MACRO_MAP_FOR_(...) MACRO_MAP_FOR_N(NUM_VA_ARGS_LESS_1(__VA_ARGS__), __VA_ARGS__)
+
+/**
+ * @brief Mapping N arguments macro with current index
+ *
+ * Macro is similar to @ref MACRO_MAP_FOR but maps exact number of arguments.
+ * If there is more arguments given, the rest would be ignored.
+ *
+ * @param N   Number of arguments to map
+ * @param ... Macro name to be used for argument processing followed by arguments to process.
+ *            Macro should have following form: MACRO(argument, index)
+ *
+ * @return Selected number of arguments processed by given macro
+ */
+#define MACRO_MAP_FOR_N(N, ...) MACRO_MAP_FOR_N_(N, __VA_ARGS__)
+#define MACRO_MAP_FOR_N_(N, ...) CONCAT_2(MACRO_MAP_FOR_, N)((MACRO_MAP_FOR_N_LIST), __VA_ARGS__, )
+
+#define MACRO_MAP_FOR_0( n_list,           ...)
+#define MACRO_MAP_FOR_1( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)))
+#define MACRO_MAP_FOR_2( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_1 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_3( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_2 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_4( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_3 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_5( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_4 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_6( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_5 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_7( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_6 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_8( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_7 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_9( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_8 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_10(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_9 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_11(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_10((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_12(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_11((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_13(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_12((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_14(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_13((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_15(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_14((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, )
+
+
+/**
+ * @brief Mapping macro with current index and parameter
+ *
+ * Version of @ref MACRO_MAP_FOR that passes also the same parameter to all macros.
+ *
+ * @param param Parameter that would be passed to each macro call during mapping.
+ * @param ...   Macro name to be used for argument processing followed by arguments to process.
+ *              Macro should have following form: MACRO(argument, index, param)
+ *
+ * @return All arguments processed by given macro
+ */
+#define MACRO_MAP_FOR_PARAM(param, ...) MACRO_MAP_FOR_PARAM_(param, __VA_ARGS__)
+#define MACRO_MAP_FOR_PARAM_(param, ...) MACRO_MAP_FOR_PARAM_N(NUM_VA_ARGS_LESS_1(__VA_ARGS__), param, __VA_ARGS__)
+
+/**
+ * @brief Mapping N arguments macro with with current index and parameter
+ *
+ * @param N     Number of arguments to map
+ * @param param Parameter that would be passed to each macro call during mapping.
+ * @param ...   Macro name to be used for argument processing followed by arguments to process.
+ *              Macro should have following form: MACRO(argument, index, param)
+ *
+ * @return All arguments processed by given macro
+ */
+#define MACRO_MAP_FOR_PARAM_N(N, param, ...) MACRO_MAP_FOR_PARAM_N_(N, param, __VA_ARGS__)
+#define MACRO_MAP_FOR_PARAM_N_(N, param, ...) CONCAT_2(MACRO_MAP_FOR_PARAM_, N)((MACRO_MAP_FOR_N_LIST), param, __VA_ARGS__, )
+
+
+#define MACRO_MAP_FOR_PARAM_0( n_list, param, ...)
+#define MACRO_MAP_FOR_PARAM_1( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param)
+#define MACRO_MAP_FOR_PARAM_2( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_1 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_PARAM_3( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_2 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_PARAM_4( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_3 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_PARAM_5( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_4 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_PARAM_6( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_5 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_PARAM_7( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_6 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_PARAM_8( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_7 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_PARAM_9( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_8 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_PARAM_10(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_9 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_PARAM_11(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_10((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_PARAM_12(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_11((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_PARAM_13(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_12((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_PARAM_14(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_13((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, )
+#define MACRO_MAP_FOR_PARAM_15(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_14((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, )
+
+
+/**@brief Adding curly brace to macro parameter
+ *
+ * Useful in array of structures initialization.
+ *
+ * @param p parameter to put into the curly brace*/
+#define PARAM_CBRACE(p) { p },
+
+
+/**@brief Function for changing the value unit.
+ *
+ * @param[in]   value               Value to be rescaled.
+ * @param[in]   old_unit_reversal   Reversal of the incoming unit.
+ * @param[in]   new_unit_reversal   Reversal of the desired unit.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint64_t value_rescale(uint32_t value, uint32_t old_unit_reversal, uint16_t new_unit_reversal)
+{
+    return (uint64_t)ROUNDED_DIV((uint64_t)value * new_unit_reversal, old_unit_reversal);
+}
+
+/**@brief Function for encoding a uint16 value.
+ *
+ * @param[in]   value            Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t uint16_encode(uint16_t value, uint8_t * p_encoded_data)
+{
+    p_encoded_data[0] = (uint8_t) ((value & 0x00FF) >> 0);
+    p_encoded_data[1] = (uint8_t) ((value & 0xFF00) >> 8);
+    return sizeof(uint16_t);
+}
+
+/**@brief Function for encoding a three-byte value.
+ *
+ * @param[in]   value            Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t uint24_encode(uint32_t value, uint8_t * p_encoded_data)
+{
+    p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0);
+    p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8);
+    p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16);
+    return 3;
+}
+
+/**@brief Function for encoding a uint32 value.
+ *
+ * @param[in]   value            Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t uint32_encode(uint32_t value, uint8_t * p_encoded_data)
+{
+    p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0);
+    p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8);
+    p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16);
+    p_encoded_data[3] = (uint8_t) ((value & 0xFF000000) >> 24);
+    return sizeof(uint32_t);
+}
+
+/**@brief Function for encoding a uint48 value.
+ *
+ * @param[in]   value            Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t uint48_encode(uint64_t value, uint8_t * p_encoded_data)
+{
+    p_encoded_data[0] = (uint8_t) ((value & 0x0000000000FF) >> 0);
+    p_encoded_data[1] = (uint8_t) ((value & 0x00000000FF00) >> 8);
+    p_encoded_data[2] = (uint8_t) ((value & 0x000000FF0000) >> 16);
+    p_encoded_data[3] = (uint8_t) ((value & 0x0000FF000000) >> 24);
+    p_encoded_data[4] = (uint8_t) ((value & 0x00FF00000000) >> 32);
+    p_encoded_data[5] = (uint8_t) ((value & 0xFF0000000000) >> 40);
+    return 6;
+}
+
+/**@brief Function for decoding a uint16 value.
+ *
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ *
+ * @return      Decoded value.
+ */
+static __INLINE uint16_t uint16_decode(const uint8_t * p_encoded_data)
+{
+        return ( (((uint16_t)((uint8_t *)p_encoded_data)[0])) |
+                 (((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 ));
+}
+
+/**@brief Function for decoding a uint16 value in big-endian format.
+ *
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ *
+ * @return      Decoded value.
+ */
+static __INLINE uint16_t uint16_big_decode(const uint8_t * p_encoded_data)
+{
+        return ( (((uint16_t)((uint8_t *)p_encoded_data)[0]) << 8 ) |
+                 (((uint16_t)((uint8_t *)p_encoded_data)[1])) );
+}
+
+/**@brief Function for decoding a three-byte value.
+ *
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ *
+ * @return      Decoded value (uint32_t).
+ */
+static __INLINE uint32_t uint24_decode(const uint8_t * p_encoded_data)
+{
+    return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0)  |
+             (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8)  |
+             (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16));
+}
+
+/**@brief Function for decoding a uint32 value.
+ *
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ *
+ * @return      Decoded value.
+ */
+static __INLINE uint32_t uint32_decode(const uint8_t * p_encoded_data)
+{
+    return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0)  |
+             (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8)  |
+             (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) |
+             (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 ));
+}
+
+/**@brief Function for decoding a uint32 value in big-endian format.
+ *
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ *
+ * @return      Decoded value.
+ */
+static __INLINE uint32_t uint32_big_decode(const uint8_t * p_encoded_data)
+{
+    return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 24) |
+             (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 16) |
+             (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 8)  |
+             (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 0) );
+}
+
+/**
+ * @brief Function for encoding an uint16 value in big-endian format.
+ *
+ * @param[in]   value            Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data will be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t uint16_big_encode(uint16_t value, uint8_t * p_encoded_data)
+{
+    p_encoded_data[0] = (uint8_t) (value >> 8);
+    p_encoded_data[1] = (uint8_t) (value & 0xFF);
+
+    return sizeof(uint16_t);
+}
+
+/**@brief Function for encoding a uint32 value in big-endian format.
+ *
+ * @param[in]   value            Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data will be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t uint32_big_encode(uint32_t value, uint8_t * p_encoded_data)
+{
+    *(uint32_t *)p_encoded_data = __REV(value);
+    return sizeof(uint32_t);
+}
+
+/**@brief Function for decoding a uint48 value.
+ *
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ *
+ * @return      Decoded value. (uint64_t)
+ */
+static __INLINE uint64_t uint48_decode(const uint8_t * p_encoded_data)
+{
+    return ( (((uint64_t)((uint8_t *)p_encoded_data)[0]) << 0)  |
+             (((uint64_t)((uint8_t *)p_encoded_data)[1]) << 8)  |
+             (((uint64_t)((uint8_t *)p_encoded_data)[2]) << 16) |
+             (((uint64_t)((uint8_t *)p_encoded_data)[3]) << 24) |
+             (((uint64_t)((uint8_t *)p_encoded_data)[4]) << 32) |
+             (((uint64_t)((uint8_t *)p_encoded_data)[5]) << 40 ));
+}
+
+/** @brief Function for converting the input voltage (in milli volts) into percentage of 3.0 Volts.
+ *
+ *  @details The calculation is based on a linearized version of the battery's discharge
+ *           curve. 3.0V returns 100% battery level. The limit for power failure is 2.1V and
+ *           is considered to be the lower boundary.
+ *
+ *           The discharge curve for CR2032 is non-linear. In this model it is split into
+ *           4 linear sections:
+ *           - Section 1: 3.0V - 2.9V = 100% - 42% (58% drop on 100 mV)
+ *           - Section 2: 2.9V - 2.74V = 42% - 18% (24% drop on 160 mV)
+ *           - Section 3: 2.74V - 2.44V = 18% - 6% (12% drop on 300 mV)
+ *           - Section 4: 2.44V - 2.1V = 6% - 0% (6% drop on 340 mV)
+ *
+ *           These numbers are by no means accurate. Temperature and
+ *           load in the actual application is not accounted for!
+ *
+ *  @param[in] mvolts The voltage in mV
+ *
+ *  @return    Battery level in percent.
+*/
+static __INLINE uint8_t battery_level_in_percent(const uint16_t mvolts)
+{
+    uint8_t battery_level;
+
+    if (mvolts >= 3000)
+    {
+        battery_level = 100;
+    }
+    else if (mvolts > 2900)
+    {
+        battery_level = 100 - ((3000 - mvolts) * 58) / 100;
+    }
+    else if (mvolts > 2740)
+    {
+        battery_level = 42 - ((2900 - mvolts) * 24) / 160;
+    }
+    else if (mvolts > 2440)
+    {
+        battery_level = 18 - ((2740 - mvolts) * 12) / 300;
+    }
+    else if (mvolts > 2100)
+    {
+        battery_level = 6 - ((2440 - mvolts) * 6) / 340;
+    }
+    else
+    {
+        battery_level = 0;
+    }
+
+    return battery_level;
+}
+
+/**@brief Function for checking if a pointer value is aligned to a 4 byte boundary.
+ *
+ * @param[in]   p   Pointer value to be checked.
+ *
+ * @return      TRUE if pointer is aligned to a 4 byte boundary, FALSE otherwise.
+ */
+static __INLINE bool is_word_aligned(void const* p)
+{
+    return (((uintptr_t)p & 0x03) == 0);
+}
+
+/**
+ * @brief Function for checking if provided address is located in stack space.
+ *
+ * @param[in]   ptr Pointer to be checked.
+ *
+ * @return      true if address is in stack space, false otherwise.
+ */
+static __INLINE bool is_address_from_stack(void * ptr)
+{
+    if (((uint32_t)ptr >= (uint32_t)STACK_BASE) &&
+        ((uint32_t)ptr <  (uint32_t)STACK_TOP) )
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // APP_UTIL_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_util_bds.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,448 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup app_util Utility Functions and Definitions
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Various types and definitions available to all applications.
+ */
+
+#ifndef APP_UTIL_BDS_H__
+#define APP_UTIL_BDS_H__
+
+#include <stdint.h>
+#include <string.h>
+#include <stdbool.h>
+#include "compiler_abstraction.h"
+#include "app_util.h"
+#include "ble_srv_common.h"
+#include "nordic_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef uint8_t nibble_t;
+typedef uint32_t uint24_t;
+typedef uint64_t uint40_t;
+
+/**@brief IEEE 11073-20601 Regulatory Certification Data List Structure */
+typedef struct
+{
+    uint8_t *  p_list;                                          /**< Pointer the byte array containing the encoded opaque structure based on IEEE 11073-20601 specification. */
+    uint8_t    list_len;                                        /**< Length of the byte array. */
+} regcertdatalist_t;
+
+/**@brief SFLOAT format (IEEE-11073 16-bit FLOAT, meaning 4 bits for exponent (base 10) and 12 bits mantissa) */
+typedef struct
+{
+  int8_t exponent;                                             /**< Base 10 exponent, should be using only 4 bits */
+  int16_t mantissa;                                            /**< Mantissa, should be using only 12 bits */
+} sfloat_t;
+
+/**@brief Date and Time structure. */
+typedef struct
+{
+    uint16_t year;
+    uint8_t  month;
+    uint8_t  day;
+    uint8_t  hours;
+    uint8_t  minutes;
+    uint8_t  seconds;
+} ble_date_time_t;
+
+
+/**@brief Function for encoding a uint16 value.
+ *
+ * @param[in]   p_value          Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t bds_uint16_encode(const uint16_t * p_value, uint8_t * p_encoded_data)
+{
+    p_encoded_data[0] = (uint8_t) ((*p_value & 0x00FF) >> 0);
+    p_encoded_data[1] = (uint8_t) ((*p_value & 0xFF00) >> 8);
+    return sizeof(uint16_t);
+}
+
+static __INLINE uint8_t bds_int16_encode(const int16_t * p_value, uint8_t * p_encoded_data)
+{
+    uint16_t tmp = *p_value;
+    return bds_uint16_encode(&tmp, p_encoded_data);
+}
+
+/**@brief Function for encoding a uint24 value.
+ *
+ * @param[in]   p_value          Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t bds_uint24_encode(const uint32_t * p_value, uint8_t * p_encoded_data)
+{
+    p_encoded_data[0] = (uint8_t) ((*p_value & 0x000000FF) >> 0);
+    p_encoded_data[1] = (uint8_t) ((*p_value & 0x0000FF00) >> 8);
+    p_encoded_data[2] = (uint8_t) ((*p_value & 0x00FF0000) >> 16);
+    return (3);
+}
+
+
+/**@brief Function for encoding a uint32 value.
+ *
+ * @param[in]   p_value          Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t bds_uint32_encode(const uint32_t * p_value, uint8_t * p_encoded_data)
+{
+    p_encoded_data[0] = (uint8_t) ((*p_value & 0x000000FF) >> 0);
+    p_encoded_data[1] = (uint8_t) ((*p_value & 0x0000FF00) >> 8);
+    p_encoded_data[2] = (uint8_t) ((*p_value & 0x00FF0000) >> 16);
+    p_encoded_data[3] = (uint8_t) ((*p_value & 0xFF000000) >> 24);
+    return sizeof(uint32_t);
+}
+
+
+/**@brief Function for encoding a uint40 value.
+ *
+ * @param[in]   p_value          Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t bds_uint40_encode(const uint64_t * p_value, uint8_t * p_encoded_data)
+{
+    p_encoded_data[0] = (uint8_t) ((*p_value & 0x00000000000000FF) >> 0);
+    p_encoded_data[1] = (uint8_t) ((*p_value & 0x000000000000FF00) >> 8);
+    p_encoded_data[2] = (uint8_t) ((*p_value & 0x0000000000FF0000) >> 16);
+    p_encoded_data[3] = (uint8_t) ((*p_value & 0x00000000FF000000) >> 24);
+    p_encoded_data[4] = (uint8_t) ((*p_value & 0x000000FF00000000) >> 32);
+    return 5;
+}
+
+/**@brief Function for encoding a sfloat value.
+ *
+ * @param[in]   p_value          Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t bds_sfloat_encode(const sfloat_t * p_value, uint8_t * p_encoded_data)
+{
+    uint16_t encoded_val;
+
+    encoded_val = ((p_value->exponent << 12) & 0xF000) |
+                            ((p_value->mantissa <<  0) & 0x0FFF);
+
+    return(bds_uint16_encode(&encoded_val, p_encoded_data));
+}
+
+
+/**@brief Function for encoding a uint8_array value.
+ *
+ * @param[in]   p_value          Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ */
+static __INLINE uint8_t bds_uint8_array_encode(const uint8_array_t * p_value,
+                                               uint8_t             * p_encoded_data)
+{
+    memcpy(p_encoded_data, p_value->p_data, p_value->size);
+    return p_value->size;
+}
+
+
+/**@brief Function for encoding a utf8_str value.
+ *
+ * @param[in]   p_value          Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+
+ */
+static __INLINE uint8_t bds_ble_srv_utf8_str_encode(const ble_srv_utf8_str_t * p_value,
+                                                    uint8_t                  * p_encoded_data)
+{
+    memcpy(p_encoded_data, p_value->p_str, p_value->length);
+    return p_value->length;
+}
+
+/**@brief Function for encoding a regcertdatalist value.
+ *
+ * @param[in]   p_value          Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+
+ */
+static __INLINE uint8_t bds_regcertdatalist_encode(const regcertdatalist_t * p_value,
+                                                   uint8_t                 * p_encoded_data)
+{
+    memcpy(p_encoded_data, p_value->p_list, p_value->list_len);
+    return p_value->list_len;
+}
+
+
+/**@brief Function for decoding a date_time value.
+ *
+ * @param[in]   p_date_time    pointer to the date_time structure to encode.
+ * @param[in]   p_encoded_data pointer to the encoded data
+ * @return      length of the encoded field.
+ */
+static __INLINE uint8_t bds_ble_date_time_encode(const ble_date_time_t * p_date_time,
+                                                 uint8_t               * p_encoded_data)
+{
+    uint8_t len = bds_uint16_encode(&p_date_time->year, &p_encoded_data[0]);
+
+    p_encoded_data[len++] = p_date_time->month;
+    p_encoded_data[len++] = p_date_time->day;
+    p_encoded_data[len++] = p_date_time->hours;
+    p_encoded_data[len++] = p_date_time->minutes;
+    p_encoded_data[len++] = p_date_time->seconds;
+
+    return len;
+}
+
+
+/**@brief Function for decoding a uint16 value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_decoded_val    pointer to the decoded value
+ * @return      length of the decoded field.
+ */
+static __INLINE uint8_t bds_uint16_decode(const uint8_t len,
+                                          const uint8_t * p_encoded_data,
+                                          uint16_t      * p_decoded_val)
+{
+    UNUSED_VARIABLE(len);
+    *p_decoded_val = (((uint16_t)((uint8_t *)p_encoded_data)[0])) |
+                     (((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 );
+    return (sizeof(uint16_t));
+}
+
+
+/**@brief Function for decoding a int16 value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_decoded_val    pointer to the decoded value
+ * @return      length of the decoded field.
+ */
+static __INLINE uint8_t bds_int16_decode(const uint8_t len,
+                                         const uint8_t * p_encoded_data,
+                                         int16_t       * p_decoded_val)
+{
+    UNUSED_VARIABLE(len);
+    uint16_t tmp = 0;
+    uint8_t retval = bds_uint16_decode(len, p_encoded_data, &tmp);
+    *p_decoded_val = (int16_t)tmp;
+    return retval;
+}
+
+
+/**@brief Function for decoding a uint24 value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_decoded_val    pointer to the decoded value
+ *
+ * @return      length of the decoded field.
+ */
+static __INLINE uint8_t bds_uint24_decode(const uint8_t len,
+                                          const uint8_t * p_encoded_data,
+                                          uint32_t      * p_decoded_val)
+{
+    UNUSED_VARIABLE(len);
+    *p_decoded_val = (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0)  |
+                     (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8)  |
+                     (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16);
+    return (3);
+}
+
+
+/**@brief Function for decoding a uint32 value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_decoded_val    pointer to the decoded value
+ *
+ * @return      length of the decoded field.
+ */
+static __INLINE uint8_t bds_uint32_decode(const uint8_t len,
+                                          const uint8_t * p_encoded_data,
+                                          uint32_t      * p_decoded_val)
+{
+    UNUSED_VARIABLE(len);
+    *p_decoded_val = (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0)  |
+                     (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8)  |
+                     (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) |
+                     (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 );
+    return (sizeof(uint32_t));
+}
+
+
+/**@brief Function for decoding a uint40 value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_decoded_val    pointer to the decoded value
+ *
+ * @return      length of the decoded field.
+ */
+static __INLINE uint8_t bds_uint40_decode(const uint8_t len,
+                                          const uint8_t * p_encoded_data,
+                                          uint64_t      * p_decoded_val)
+{
+    UNUSED_VARIABLE(len);
+    *p_decoded_val = (((uint64_t)((uint8_t *)p_encoded_data)[0]) << 0)  |
+                     (((uint64_t)((uint8_t *)p_encoded_data)[1]) << 8)  |
+                     (((uint64_t)((uint8_t *)p_encoded_data)[2]) << 16) |
+                     (((uint64_t)((uint8_t *)p_encoded_data)[3]) << 24 )|
+                     (((uint64_t)((uint8_t *)p_encoded_data)[4]) << 32 );
+    return (40);
+}
+
+
+/**@brief Function for decoding a sfloat value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_decoded_val    pointer to the decoded value
+ *
+ * @return      length of the decoded field.
+
+ */
+static __INLINE uint8_t bds_sfloat_decode(const uint8_t len,
+                                          const uint8_t * p_encoded_data,
+                                          sfloat_t      * p_decoded_val)
+{
+
+    p_decoded_val->exponent = 0;
+    bds_uint16_decode(len, p_encoded_data, (uint16_t*)&p_decoded_val->mantissa);
+    p_decoded_val->exponent = (uint8_t)((p_decoded_val->mantissa & 0xF000) >> 12);
+    p_decoded_val->mantissa &= 0x0FFF;
+    return len;
+}
+
+
+/**@brief Function for decoding a uint8_array value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_decoded_val    pointer to the decoded value
+ *
+ * @return      length of the decoded field.
+ */
+static __INLINE uint8_t bds_uint8_array_decode(const uint8_t len,
+                                               const uint8_t * p_encoded_data,
+                                               uint8_array_t * p_decoded_val)
+{
+    memcpy(p_decoded_val->p_data, p_encoded_data, len);
+    p_decoded_val->size = len;
+    return p_decoded_val->size;
+}
+
+
+/**@brief Function for decoding a utf8_str value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_decoded_val    pointer to the decoded value
+ *
+ * @return      length of the decoded field.
+ */
+static __INLINE uint8_t bds_ble_srv_utf8_str_decode(const uint8_t      len,
+                                                    const uint8_t      * p_encoded_data,
+                                                    ble_srv_utf8_str_t * p_decoded_val)
+{
+    p_decoded_val->p_str = (uint8_t*)p_encoded_data;
+    p_decoded_val->length = len;
+    return p_decoded_val->length;
+}
+
+
+/**@brief Function for decoding a regcertdatalist value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_decoded_val    pointer to the decoded value
+ *
+ * @return      length of the decoded field.
+ */
+static __INLINE uint8_t bds_regcertdatalist_decode(const uint8_t     len,
+                                                   const uint8_t     * p_encoded_data,
+                                                   regcertdatalist_t * p_decoded_val)
+{
+    memcpy(p_decoded_val->p_list, p_encoded_data, len);
+    p_decoded_val->list_len = len;
+    return p_decoded_val->list_len;
+}
+
+
+/**@brief Function for decoding a date_time value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_date_time      pointer to the decoded value
+ *
+ * @return      length of the decoded field.
+ */
+static __INLINE uint8_t bds_ble_date_time_decode(const uint8_t   len,
+                                                 const uint8_t   * p_encoded_data,
+                                                 ble_date_time_t * p_date_time)
+{
+    UNUSED_VARIABLE(len);
+    uint8_t pos          = bds_uint16_decode(len, &p_encoded_data[0], &p_date_time->year);
+    p_date_time->month   = p_encoded_data[pos++];
+    p_date_time->day     = p_encoded_data[pos++];
+    p_date_time->hours   = p_encoded_data[pos++];
+    p_date_time->minutes = p_encoded_data[pos++];
+    p_date_time->seconds = p_encoded_data[pos++];
+
+    return pos;
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // APP_UTIL_BDS_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_util_platform.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,126 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "app_util_platform.h"
+
+#ifdef SOFTDEVICE_PRESENT
+/* Global nvic state instance, required by nrf_nvic.h */
+nrf_nvic_state_t nrf_nvic_state;
+#endif
+
+static uint32_t m_in_critical_region = 0;
+
+void app_util_disable_irq(void)
+{
+    __disable_irq();
+    m_in_critical_region++;
+}
+
+void app_util_enable_irq(void)
+{
+    m_in_critical_region--;
+    if (m_in_critical_region == 0)
+    {
+        __enable_irq();
+    }
+}
+
+void app_util_critical_region_enter(uint8_t *p_nested)
+{
+#if __CORTEX_M == (0x04U)
+    ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get())
+#endif
+
+#if defined(SOFTDEVICE_PRESENT)
+    /* return value can be safely ignored */
+    (void) sd_nvic_critical_region_enter(p_nested);
+#else
+    app_util_disable_irq();
+#endif
+}
+
+void app_util_critical_region_exit(uint8_t nested)
+{
+#if __CORTEX_M == (0x04U)
+    ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get())
+#endif
+
+#if defined(SOFTDEVICE_PRESENT)
+    /* return value can be safely ignored */
+    (void) sd_nvic_critical_region_exit(nested);
+#else
+    app_util_enable_irq();
+#endif
+}
+
+
+uint8_t privilege_level_get(void)
+{
+#if __CORTEX_M == (0x00U) || defined(_WIN32) || defined(__unix) || defined(__APPLE__)
+    /* the Cortex-M0 has no concept of privilege */
+    return APP_LEVEL_PRIVILEGED;
+#elif __CORTEX_M == (0x04U)
+    uint32_t isr_vector_num = __get_IPSR() & IPSR_ISR_Msk ;
+    if (0 == isr_vector_num)
+    {
+        /* Thread Mode, check nPRIV */
+        int32_t control = __get_CONTROL();
+        return control & CONTROL_nPRIV_Msk ? APP_LEVEL_UNPRIVILEGED : APP_LEVEL_PRIVILEGED;
+    }
+    else
+    {
+        /* Handler Mode, always privileged */
+        return APP_LEVEL_PRIVILEGED;
+    }
+#endif
+}
+
+
+uint8_t current_int_priority_get(void)
+{
+    uint32_t isr_vector_num = __get_IPSR() & IPSR_ISR_Msk ;
+    if (isr_vector_num > 0)
+    {
+        int32_t irq_type = ((int32_t)isr_vector_num - EXTERNAL_INT_VECTOR_OFFSET);
+        return (NVIC_GetPriority((IRQn_Type)irq_type) & 0xFF);
+    }
+    else
+    {
+        return APP_IRQ_PRIORITY_THREAD;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_util_platform.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,252 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**@file
+ *
+ * @defgroup app_util_platform Utility Functions and Definitions (Platform)
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Various types and definitions available to all applications when using SoftDevice.
+ */
+
+#ifndef APP_UTIL_PLATFORM_H__
+#define APP_UTIL_PLATFORM_H__
+
+#include <stdint.h>
+#include "compiler_abstraction.h"
+#include "nrf.h"
+#ifdef SOFTDEVICE_PRESENT
+#include "nrf_soc.h"
+#include "nrf_nvic.h"
+#endif
+#include "nrf_assert.h"
+#include "app_error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if __CORTEX_M == (0x00U)
+#define _PRIO_SD_HIGH       0
+#define _PRIO_APP_HIGH      1
+#define _PRIO_APP_MID       1
+#define _PRIO_SD_LOW        2
+#define _PRIO_APP_LOW       3
+#define _PRIO_APP_LOWEST    3
+#define _PRIO_THREAD        4
+#elif __CORTEX_M == (0x04U)
+#define _PRIO_SD_HIGH       0
+#define _PRIO_SD_MID        1
+#define _PRIO_APP_HIGH      2
+#define _PRIO_APP_MID       3
+#define _PRIO_SD_LOW        4
+#define _PRIO_SD_LOWEST     5
+#define _PRIO_APP_LOW       6
+#define _PRIO_APP_LOWEST    7
+#define _PRIO_THREAD        15
+#else
+    #error "No platform defined"
+#endif
+
+
+//lint -save -e113 -e452
+/**@brief The interrupt priorities available to the application while the SoftDevice is active. */
+typedef enum
+{
+#ifndef SOFTDEVICE_PRESENT
+    APP_IRQ_PRIORITY_HIGHEST = _PRIO_SD_HIGH,
+#else
+    APP_IRQ_PRIORITY_HIGHEST = _PRIO_APP_HIGH,
+#endif
+    APP_IRQ_PRIORITY_HIGH    = _PRIO_APP_HIGH,
+#ifndef SOFTDEVICE_PRESENT
+    APP_IRQ_PRIORITY_MID     = _PRIO_SD_LOW,
+#else
+    APP_IRQ_PRIORITY_MID     = _PRIO_APP_MID,
+#endif
+    APP_IRQ_PRIORITY_LOW     = _PRIO_APP_LOW,
+    APP_IRQ_PRIORITY_LOWEST  = _PRIO_APP_LOWEST,
+    APP_IRQ_PRIORITY_THREAD  = _PRIO_THREAD     /**< "Interrupt level" when running in Thread Mode. */
+} app_irq_priority_t;
+//lint -restore
+
+
+/*@brief The privilege levels available to applications in Thread Mode */
+typedef enum
+{
+    APP_LEVEL_UNPRIVILEGED,
+    APP_LEVEL_PRIVILEGED
+} app_level_t;
+
+/**@cond NO_DOXYGEN */
+#define EXTERNAL_INT_VECTOR_OFFSET 16
+/**@endcond */
+
+/**@brief Macro for setting a breakpoint.
+ */
+#if defined(__GNUC__)
+#define NRF_BREAKPOINT __builtin_trap()
+#else
+#define NRF_BREAKPOINT __BKPT(0)
+#endif
+
+/** @brief Macro for setting a breakpoint.
+ *
+ * If it is possible to detect debugger presence then it is set only in that case.
+ *
+ */
+#if __CORTEX_M == 0x04
+#define NRF_BREAKPOINT_COND do {                            \
+    /* C_DEBUGEN == 1 -> Debugger Connected */              \
+    if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk)   \
+    {                                                       \
+       /* Generate breakpoint if debugger is connected */   \
+            NRF_BREAKPOINT;                                 \
+    } \
+    }while (0)
+#else
+#define NRF_BREAKPOINT_COND NRF_BREAKPOINT
+#endif // __CORTEX_M == 0x04
+
+// #if defined ( __CC_ARM )
+// #define PACKED(TYPE) __packed TYPE
+// #define PACKED_STRUCT PACKED(struct)
+// #elif defined   ( __GNUC__ )
+// #define PACKED __attribute__((packed))
+// #define PACKED_STRUCT struct PACKED
+// #endif
+
+void app_util_critical_region_enter (uint8_t *p_nested);
+void app_util_critical_region_exit (uint8_t nested);
+
+/**@brief Macro for entering a critical region.
+ *
+ * @note Due to implementation details, there must exist one and only one call to
+ *       CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located
+ *       in the same scope.
+ */
+#ifdef SOFTDEVICE_PRESENT
+#define CRITICAL_REGION_ENTER()                                                             \
+    {                                                                                       \
+        uint8_t __CR_NESTED = 0;                                                            \
+        app_util_critical_region_enter(&__CR_NESTED);
+#else
+#define CRITICAL_REGION_ENTER() app_util_critical_region_enter(NULL)
+#endif
+
+/**@brief Macro for leaving a critical region.
+ *
+ * @note Due to implementation details, there must exist one and only one call to
+ *       CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located
+ *       in the same scope.
+ */
+#ifdef SOFTDEVICE_PRESENT
+#define CRITICAL_REGION_EXIT()                                                              \
+        app_util_critical_region_exit(__CR_NESTED);                                         \
+    }
+#else
+#define CRITICAL_REGION_EXIT() app_util_critical_region_exit(0)
+#endif
+
+/* Workaround for Keil 4 */
+#ifndef IPSR_ISR_Msk
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+#endif
+
+
+
+/**@brief Macro to enable anonymous unions from a certain point in the code.
+ */
+#if defined(__CC_ARM)
+    #define ANON_UNIONS_ENABLE _Pragma("push") \
+                               _Pragma("anon_unions")
+#elif defined(__ICCARM__)
+    #define ANON_UNIONS_ENABLE _Pragma("language=extended")
+#else
+    #define ANON_UNIONS_ENABLE
+    // No action will be taken.
+    // For GCC anonymous unions are enabled by default.
+#endif
+
+/**@brief Macro to disable anonymous unions from a certain point in the code.
+ * @note Call only after first calling @ref ANON_UNIONS_ENABLE.
+ */
+#if defined(__CC_ARM)
+    #define ANON_UNIONS_DISABLE _Pragma("pop")
+#elif defined(__ICCARM__)
+    #define ANON_UNIONS_DISABLE
+    // for IAR leave anonymous unions enabled
+#else
+    #define ANON_UNIONS_DISABLE
+    // No action will be taken.
+    // For GCC anonymous unions are enabled by default.
+#endif
+
+/* Workaround for Keil 4 */
+#ifndef CONTROL_nPRIV_Msk
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+#endif
+
+
+/**@brief Function for finding the current interrupt level.
+ *
+ * @return   Current interrupt level.
+ * @retval   APP_IRQ_PRIORITY_HIGH    We are running in Application High interrupt level.
+ * @retval   APP_IRQ_PRIORITY_LOW     We are running in Application Low interrupt level.
+ * @retval   APP_IRQ_PRIORITY_THREAD  We are running in Thread Mode.
+ */
+uint8_t current_int_priority_get(void);
+
+
+/**@brief Function for finding out the current privilege level.
+ *
+ * @return   Current privilege level.
+ * @retval   APP_LEVEL_UNPRIVILEGED    We are running in unprivileged level.
+ * @retval   APP_LEVEL_PRIVILEGED    We are running in privileged level.
+ */
+uint8_t privilege_level_get(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // APP_UTIL_PLATFORM_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/nordic_common.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,210 @@
+/* 
+ * Copyright (c) 2008 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ * @brief Common defines and macros for firmware developed by Nordic Semiconductor.
+ */
+
+#ifndef NORDIC_COMMON_H__
+#define NORDIC_COMMON_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Check if selected module is enabled
+ *
+ * This is save function for driver enable checking.
+ * Correct from Lint point of view (not using default of undefined value).
+ *
+ * Usage:
+ * @code
+   #if NRF_MODULE_ENABLED(UART)
+   ...
+   #endif
+ * @endcode
+ *
+ * @param module The module name.
+ *
+ * @retval 1 The macro <module>_ENABLE is defined and is non-zero.
+ * @retval 0 The macro <module>_ENABLE is not defined or it equals zero.
+ *
+ * @note
+ * This macro intentionally does not implement second expansion level.
+ * The name of the module to be checked has to be given directly as a parameter.
+ * And given parameter would be connected with @c _ENABLED postfix directly
+ * without evaluating its value.
+ */
+//lint -e491 // Suppers warning 491 "non-standard use of 'defined' preprocessor operator"
+#define NRF_MODULE_ENABLED(module) \
+    ((defined(module ## _ENABLED) && (module ## _ENABLED)) ? 1 : 0)
+
+/** The upper 8 bits of a 32 bit value */
+//lint -emacro(572,MSB) // Suppress warning 572 "Excessive shift value"
+#define MSB_32(a) (((a) & 0xFF000000) >> 24)
+/** The lower 8 bits (of a 32 bit value) */
+#define LSB_32(a) ((a) & 0x000000FF)
+
+/** The upper 8 bits of a 16 bit value */
+//lint -emacro(572,MSB_16) // Suppress warning 572 "Excessive shift value"
+#define MSB_16(a) (((a) & 0xFF00) >> 8)
+/** The lower 8 bits (of a 16 bit value) */
+#define LSB_16(a) ((a) & 0x00FF)
+
+/** Leaves the minimum of the two 32-bit arguments */
+/*lint -emacro(506, MIN) */ /* Suppress "Constant value Boolean */
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+/** Leaves the maximum of the two 32-bit arguments */
+/*lint -emacro(506, MAX) */ /* Suppress "Constant value Boolean */
+#define MAX(a, b) ((a) < (b) ? (b) : (a))
+
+/**@brief Concatenates two parameters.
+ *
+ * It realizes two level expansion to make it sure that all the parameters
+ * are actually expanded before gluing them together.
+ *
+ * @param p1 First parameter to concatenating
+ * @param p2 Second parameter to concatenating
+ *
+ * @return Two parameters glued together.
+ *         They have to create correct C mnemonic in other case
+ *         preprocessor error would be generated.
+ *
+ * @sa CONCAT_3
+ */
+#define CONCAT_2(p1, p2)      CONCAT_2_(p1, p2)
+/** Auxiliary macro used by @ref CONCAT_2 */
+#define CONCAT_2_(p1, p2)     p1##p2
+
+/**@brief Concatenates three parameters.
+ *
+ * It realizes two level expansion to make it sure that all the parameters
+ * are actually expanded before gluing them together.
+ *
+ * @param p1 First parameter to concatenating
+ * @param p2 Second parameter to concatenating
+ * @param p3 Third parameter to concatenating
+ *
+ * @return Three parameters glued together.
+ *         They have to create correct C mnemonic in other case
+ *         preprocessor error would be generated.
+ *
+ * @sa CONCAT_2
+ */
+#define CONCAT_3(p1, p2, p3)  CONCAT_3_(p1, p2, p3)
+/** Auxiliary macro used by @ref CONCAT_3 */
+#define CONCAT_3_(p1, p2, p3) p1##p2##p3
+
+#define NUM_TO_STR_INTERNAL(val) #val
+/** Converts numeric value to string.
+ */
+#define NUM_TO_STR(val) NUM_TO_STR_INTERNAL(val)
+
+/** Counts number of elements inside the array
+ */
+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
+
+/**@brief Set a bit in the uint32 word.
+ *
+ * @param[in] W  Word whose bit is being set.
+ * @param[in] B  Bit number in the word to be set.
+ */
+#define SET_BIT(W,B)  ((W) |= (uint32_t)(1U << (B)))
+
+
+/**@brief Clears a bit in the uint32 word.
+ *
+ * @param[in] W   Word whose bit is to be cleared.
+ * @param[in] B   Bit number in the word to be cleared.
+ */
+#define CLR_BIT(W, B) ((W) &= (~((uint32_t)1 << (B))))
+
+
+/**@brief Checks if a bit is set.
+ *
+ * @param[in] W   Word whose bit is to be checked.
+ * @param[in] B   Bit number in the word to be checked.
+ *
+ * @retval 1 if bit is set.
+ * @retval 0 if bit is not set.
+ */
+#define IS_SET(W,B) (((W) >> (B)) & 1)
+
+#define BIT_0 0x01 /**< The value of bit 0 */
+#define BIT_1 0x02 /**< The value of bit 1 */
+#define BIT_2 0x04 /**< The value of bit 2 */
+#define BIT_3 0x08 /**< The value of bit 3 */
+#define BIT_4 0x10 /**< The value of bit 4 */
+#define BIT_5 0x20 /**< The value of bit 5 */
+#define BIT_6 0x40 /**< The value of bit 6 */
+#define BIT_7 0x80 /**< The value of bit 7 */
+#define BIT_8 0x0100 /**< The value of bit 8 */
+#define BIT_9 0x0200 /**< The value of bit 9 */
+#define BIT_10 0x0400 /**< The value of bit 10 */
+#define BIT_11 0x0800 /**< The value of bit 11 */
+#define BIT_12 0x1000 /**< The value of bit 12 */
+#define BIT_13 0x2000 /**< The value of bit 13 */
+#define BIT_14 0x4000 /**< The value of bit 14 */
+#define BIT_15 0x8000 /**< The value of bit 15 */
+#define BIT_16 0x00010000 /**< The value of bit 16 */
+#define BIT_17 0x00020000 /**< The value of bit 17 */
+#define BIT_18 0x00040000 /**< The value of bit 18 */
+#define BIT_19 0x00080000 /**< The value of bit 19 */
+#define BIT_20 0x00100000 /**< The value of bit 20 */
+#define BIT_21 0x00200000 /**< The value of bit 21 */
+#define BIT_22 0x00400000 /**< The value of bit 22 */
+#define BIT_23 0x00800000 /**< The value of bit 23 */
+#define BIT_24 0x01000000 /**< The value of bit 24 */
+#define BIT_25 0x02000000 /**< The value of bit 25 */
+#define BIT_26 0x04000000 /**< The value of bit 26 */
+#define BIT_27 0x08000000 /**< The value of bit 27 */
+#define BIT_28 0x10000000 /**< The value of bit 28 */
+#define BIT_29 0x20000000 /**< The value of bit 29 */
+#define BIT_30 0x40000000 /**< The value of bit 30 */
+#define BIT_31 0x80000000 /**< The value of bit 31 */
+
+#define UNUSED_VARIABLE(X)  ((void)(X))
+#define UNUSED_PARAMETER(X) UNUSED_VARIABLE(X)
+#define UNUSED_RETURN_VALUE(X) UNUSED_VARIABLE(X)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NORDIC_COMMON_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/nrf_assert.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,52 @@
+/* 
+ * Copyright (c) 2006 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "nrf_assert.h"
+#include "app_error.h"
+#include "nordic_common.h"
+
+__WEAK void assert_nrf_callback(uint16_t line_num, const uint8_t * file_name)
+{
+    assert_info_t assert_info =
+    {
+        .line_num    = line_num,
+        .p_file_name = file_name,
+    };
+    app_error_fault_handler(NRF_FAULT_ID_SDK_ASSERT, 0, (uint32_t)(&assert_info));
+
+    UNUSED_VARIABLE(assert_info);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/nrf_assert.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,121 @@
+/* 
+ * Copyright (c) 2006 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ * @brief Utilities for verifying program logic
+ */
+
+#ifndef NRF_ASSERT_H_
+#define NRF_ASSERT_H_
+
+#include <stdint.h>
+#include "nrf.h"
+#include "app_error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @brief Function for handling assertions.
+ *
+ *
+ * @note
+ * This function is called when an assertion has triggered.
+ *
+ * @note
+ * This function is deprecated and will be removed in future releases.
+ * Use app_error_fault_handler instead.
+ *
+ *
+ * @post
+ * All hardware is put into an idle non-emitting state (in particular the radio is highly
+ * important to switch off since the radio might be in a state that makes it send
+ * packets continiously while a typical final infinit ASSERT loop is executing).
+ *
+ *
+ * @param line_num The line number where the assertion is called
+ * @param file_name Pointer to the file name
+ */
+//lint -save -esym(14, assert_nrf_callback)
+void assert_nrf_callback(uint16_t line_num, const uint8_t *file_name);
+//lint -restore
+
+#if (defined(DEBUG_NRF) || defined(DEBUG_NRF_USER))
+#define NRF_ASSERT_PRESENT 1
+#else
+#define NRF_ASSERT_PRESENT 0
+#endif
+
+//#if defined(DEBUG_NRF) || defined(DEBUG_NRF_USER)
+
+/*lint -emacro(506, ASSERT) */ /* Suppress "Constant value Boolean */
+/*lint -emacro(774, ASSERT) */ /* Suppress "Boolean within 'if' always evaluates to True" */ \
+
+/** @brief Function for checking intended for production code.
+ *
+ * Check passes if "expr" evaluates to true. */
+
+#ifdef _lint
+#define ASSERT(expr) \
+if (expr)                                                                     \
+{                                                                             \
+}                                                                             \
+else                                                                          \
+{                                                                             \
+    while(1);             \
+}
+#else //_lint
+#define ASSERT(expr) \
+if (NRF_ASSERT_PRESENT)                                                       \
+{                                                                             \
+    if (expr)                                                                 \
+    {                                                                         \
+    }                                                                         \
+    else                                                                      \
+    {                                                                         \
+        assert_nrf_callback((uint16_t)__LINE__, (uint8_t *)__FILE__);         \
+    }                                                                         \
+}
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF_ASSERT_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/nrf_bitmask.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,147 @@
+/* 
+ * Copyright (c) 2006 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_BITMASK_H
+#define NRF_BITMASK_H
+
+#include "compiler_abstraction.h"
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BITMASK_BYTE_GET(abs_bit) ((abs_bit)/8)
+#define BITMASK_RELBIT_GET(abs_bit) ((abs_bit) & 0x00000007)
+
+/**
+ * Function for checking if bit in the multi-byte bit mask is set.
+ *
+ * @param bit    Bit index.
+ * @param p_mask A pointer to mask with bit fields.
+ *
+ * @return 0 if bit is not set, positive value otherwise.
+ */
+__STATIC_INLINE uint32_t nrf_bitmask_bit_is_set(uint32_t bit, void const * p_mask)
+{
+    uint8_t const * p_mask8 = (uint8_t const *)p_mask;
+    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
+    bit = BITMASK_RELBIT_GET(bit);
+    return (1 << bit) & p_mask8[byte_idx];
+}
+
+/**
+ * Function for setting a bit in the multi-byte bit mask.
+ *
+ * @param bit    Bit index.
+ * @param p_mask A pointer to mask with bit fields.
+ */
+__STATIC_INLINE void nrf_bitmask_bit_set(uint32_t bit, void * p_mask)
+{
+    uint8_t * p_mask8 = (uint8_t *)p_mask;
+    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
+    bit = BITMASK_RELBIT_GET(bit);
+    p_mask8[byte_idx] |= (1 << bit);
+}
+
+/**
+ * Function for clearing a bit in the multi-byte bit mask.
+ *
+ * @param bit    Bit index.
+ * @param p_mask A pointer to mask with bit fields.
+ */
+__STATIC_INLINE void nrf_bitmask_bit_clear(uint32_t bit, void * p_mask)
+{
+    uint8_t * p_mask8 = (uint8_t *)p_mask;
+    uint32_t byte_idx = BITMASK_BYTE_GET(bit);
+    bit = BITMASK_RELBIT_GET(bit);
+    p_mask8[byte_idx] &= ~(1 << bit);
+}
+
+/**
+ * Function for performing bitwise OR operation on two multi-byte bit masks.
+ *
+ * @param p_mask1    A pointer to the first bit mask.
+ * @param p_mask2    A pointer to the second bit mask.
+ * @param p_mask_out A pointer to the output bit mask.
+ * @param length     Length of output mask in bytes.
+ */
+__STATIC_INLINE void nrf_bitmask_masks_or(void const *   p_mask1,
+                                          void const *   p_mask2,
+                                          void *         p_out_mask,
+                                          uint32_t       length)
+{
+    uint8_t const * p_mask8_1 = (uint8_t const *)p_mask1;
+    uint8_t const * p_mask8_2 = (uint8_t const *)p_mask2;
+    uint8_t * p_mask8_out = (uint8_t *)p_out_mask;
+    uint32_t i;
+    for (i = 0; i < length; i++)
+    {
+        p_mask8_out[i] = p_mask8_1[i] | p_mask8_2[i];
+    }
+}
+
+/**
+ * Function for performing bitwise AND operation on two multi-byte bit masks.
+ *
+ * @param p_mask1    A pointer to the first bit mask.
+ * @param p_mask2    A pointer to the second bit mask.
+ * @param p_mask_out A pointer to the output bit mask.
+ * @param length     Length of output mask in bytes.
+ */
+__STATIC_INLINE void nrf_bitmask_masks_and(void const *   p_mask1,
+                                           void const *   p_mask2,
+                                           void *         p_out_mask,
+                                           uint32_t       length)
+{
+    uint8_t const * p_mask8_1 = (uint8_t const *)p_mask1;
+    uint8_t const * p_mask8_2 = (uint8_t const *)p_mask2;
+    uint8_t * p_mask8_out = (uint8_t *)p_out_mask;
+    uint32_t i;
+    for (i = 0; i < length; i++)
+    {
+        p_mask8_out[i] = p_mask8_1[i] & p_mask8_2[i];
+    }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //NRF_BITMASK_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_common.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,76 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @cond */
+/**@file
+ *
+ * @ingroup experimental_api
+ * @defgroup sdk_common SDK Common Header
+ * @brief All common headers needed for SDK examples will be included here so that application
+ *       developer does not have to include headers on him/herself.
+ * @{
+ */
+
+#ifndef SDK_COMMON_H__
+#define SDK_COMMON_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+#include "sdk_config.h"
+#include "nordic_common.h"
+#include "compiler_abstraction.h"
+#include "sdk_os.h"
+#include "sdk_errors.h"
+#include "app_util.h"
+#include "sdk_macros.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @} */
+/** @endcond */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // SDK_COMMON_H__
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_errors.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,180 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**@file
+ *
+ * @defgroup sdk_error SDK Error codes
+ * @{
+ * @ingroup app_common
+ * @{
+ * @details Error codes are 32-bit unsigned integers with the most significant 16-bit reserved for
+ *          identifying the module where the error occurred while the least least significant LSB
+ *          are used to provide the cause or nature of error. Each module is assigned a 16-bit
+ *          unsigned integer. Which it will use to identify all errors that occurred in it. 16-bit
+ *          LSB range is with module id as the MSB in the 32-bit error code is reserved for the
+ *          module. As an example, if 0x8800 identifies a certain SDK module, all values from
+ *          0x88000000 - 0x8800FFFF are reserved for this module.
+ *          It should be noted that common error reasons have been assigned values to make it
+ *          possible to decode error reason easily. As an example, lets module uninitialized has
+ *          been assigned an error code 0x000A0. Then, if application encounters an error code
+ *          0xZZZZ00A0, it knows that it accessing a certain module without initializing it.
+ *          Apart from this, each module is allowed to define error codes that are not covered by
+ *          the common ones, however, these values are defined in a range that does not conflict
+ *          with common error values. For module, specific error however, it is possible that the
+ *          same error value is used by two different modules to indicated errors of very different
+ *          nature. If error is already defined by the NRF common error codes, these are reused.
+ *          A range is reserved for application as well, it can use this range for defining
+ *          application specific errors.
+ *
+ * @note Success code, NRF_SUCCESS, does not include any module identifier.
+
+ */
+
+#ifndef SDK_ERRORS_H__
+#define SDK_ERRORS_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+#include "sdk_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup sdk_err_base Base defined for SDK Modules
+ * @{
+ */
+#define NRF_ERROR_SDK_ERROR_BASE         (NRF_ERROR_BASE_NUM + 0x8000)   /**< Base value defined for SDK module identifiers. */
+#define NRF_ERROR_SDK_COMMON_ERROR_BASE  (NRF_ERROR_BASE_NUM + 0x0080)   /**< Base error value to be used for SDK error values. */
+/* @} */
+
+/**
+ * @defgroup sdk_module_codes Codes reserved as identification for module where the error occurred.
+ * @{
+ */
+#define NRF_ERROR_MEMORY_MANAGER_ERR_BASE   (0x8100)
+#define NRF_ERROR_PERIPH_DRIVERS_ERR_BASE   (0x8200)
+#define NRF_ERROR_GAZELLE_ERR_BASE          (0x8300)
+/* @} */
+
+
+/**
+ * @defgroup sdk_iot_errors Codes reserved as identification for IoT errors.
+ * @{
+ */
+#define NRF_ERROR_IOT_ERR_BASE_START        (0xA000)
+#define NRF_ERROR_IOT_ERR_BASE_STOP         (0xAFFF)
+/* @} */
+
+
+/**
+ * @defgroup sdk_common_errors Codes reserved as identification for common errors.
+ * @{
+ */
+#define NRF_ERROR_MODULE_NOT_INITIALZED      (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0000)
+#define NRF_ERROR_MUTEX_INIT_FAILED          (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0001)
+#define NRF_ERROR_MUTEX_LOCK_FAILED          (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0002)
+#define NRF_ERROR_MUTEX_UNLOCK_FAILED        (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0003)
+#define NRF_ERROR_MUTEX_COND_INIT_FAILED     (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0004)
+#define NRF_ERROR_MODULE_ALREADY_INITIALIZED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0005)
+#define NRF_ERROR_STORAGE_FULL               (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0006)
+#define NRF_ERROR_API_NOT_IMPLEMENTED        (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0010)
+#define NRF_ERROR_FEATURE_NOT_ENABLED        (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0011)
+/* @} */
+
+
+/**
+ * @defgroup drv_specific_errors Error / status codes specific to drivers.
+ * @{
+ */
+#define NRF_ERROR_DRV_TWI_ERR_OVERRUN              (NRF_ERROR_PERIPH_DRIVERS_ERR_BASE + 0x0000)
+#define NRF_ERROR_DRV_TWI_ERR_ANACK                (NRF_ERROR_PERIPH_DRIVERS_ERR_BASE + 0x0001)
+#define NRF_ERROR_DRV_TWI_ERR_DNACK                (NRF_ERROR_PERIPH_DRIVERS_ERR_BASE + 0x0002)
+/* @} */
+
+/**
+ * @brief API Result.
+ *
+ * @details Indicates success or failure of an API procedure. In case of failure, a comprehensive
+ *          error code indicating cause or reason for failure is provided.
+ *
+ *          Though called an API result, it could used in Asynchronous notifications callback along
+ *          with asynchronous callback as event result. This mechanism is employed when an event
+ *          marks the end of procedure initiated using API. API result, in this case, will only be
+ *          an indicative of whether the procedure has been requested successfully.
+ */
+typedef uint32_t ret_code_t;
+
+#if defined(NRF_LOG_ENABLED) && NRF_LOG_ENABLED
+/**
+ * @defgroup err_sizes Sizes of error code arrays.
+ * @{
+ */
+#define ERR_NAMES_SIZE          18
+#define ERR_NAMES_COMMON_SIZE   9
+#define ERR_NAMES_TWI_SIZE      3
+/* @} */
+
+extern const char * m_sdk_errors_name[ERR_NAMES_SIZE];
+extern const char * m_sdk_errors_name_common[ERR_NAMES_COMMON_SIZE];
+extern const char * m_sdk_errors_name_twi[ERR_NAMES_TWI_SIZE];
+
+/**
+ * @defgroup err_to_string Macros for converting error codes to strings.
+ * @{
+ */
+#define ERR_TO_STR(err_code)            m_sdk_errors_name[err_code]
+#define ERR_TO_STR_COMMON(err_code)     m_sdk_errors_name_common[err_code - NRF_ERROR_SDK_COMMON_ERROR_BASE]
+#define ERR_TO_STR_TWI(err_code)        m_sdk_errors_name_twi[err_code - NRF_ERROR_PERIPH_DRIVERS_ERR_BASE]
+#else
+#define ERR_TO_STR(err_code)            ""
+#define ERR_TO_STR_COMMON(err_code)     ""
+#define ERR_TO_STR_TWI(err_code)        ""
+#endif // NRF_LOG_ENABLED
+
+/* @} */
+/** @} */
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // SDK_ERRORS_H__
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_macros.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,190 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**@file
+ *
+
+ * @defgroup sdk_common_macros SDK Common Header
+ * @ingroup app_common
+ * @brief Macros for parameter checking and similar tasks
+ * @{
+ */
+
+#ifndef SDK_MACROS_H__
+#define SDK_MACROS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**@brief Macro for verifying statement to be true. It will cause the exterior function to return
+ *        err_code if the statement is not true.
+ *
+ * @param[in]   statement   Statement to test.
+ * @param[in]   err_code    Error value to return if test was invalid.
+ *
+ * @retval      nothing, but will cause the exterior function to return @p err_code if @p statement
+ *              is false.
+ */
+#define VERIFY_TRUE(statement, err_code)    \
+do                                          \
+{                                           \
+    if (!(statement))                       \
+    {                                       \
+        return err_code;                    \
+    }                                       \
+} while (0)
+
+
+/**@brief Macro for verifying statement to be true. It will cause the exterior function to return
+ *        if the statement is not true.
+ *
+ * @param[in]   statement   Statement to test.
+ */
+#define VERIFY_TRUE_VOID(statement) VERIFY_TRUE((statement), )
+
+
+/**@brief Macro for verifying statement to be false. It will cause the exterior function to return
+ *        err_code if the statement is not false.
+ *
+ * @param[in]   statement   Statement to test.
+ * @param[in]   err_code    Error value to return if test was invalid.
+ *
+ * @retval      nothing, but will cause the exterior function to return @p err_code if @p statement
+ *              is true.
+ */
+#define VERIFY_FALSE(statement, err_code)   \
+do                                          \
+{                                           \
+    if ((statement))                        \
+    {                                       \
+        return err_code;                    \
+    }                                       \
+} while (0)
+
+
+/**@brief Macro for verifying statement to be false. It will cause the exterior function to return
+ *        if the statement is not false.
+ *
+ * @param[in]   statement    Statement to test.
+ */
+#define VERIFY_FALSE_VOID(statement) VERIFY_FALSE((statement), )
+
+
+/**@brief Macro for verifying that a function returned NRF_SUCCESS. It will cause the exterior
+ *        function to return err_code if the err_code is not @ref NRF_SUCCESS.
+ *
+ * @param[in] err_code The error code to check.
+ */
+#ifdef DISABLE_PARAM_CHECK
+#define VERIFY_SUCCESS()
+#else
+#define VERIFY_SUCCESS(err_code) VERIFY_TRUE((err_code) == NRF_SUCCESS, (err_code))
+#endif /* DISABLE_PARAM_CHECK */
+
+
+/**@brief Macro for verifying that a function returned NRF_SUCCESS. It will cause the exterior
+ *        function to return if the err_code is not @ref NRF_SUCCESS.
+ *
+ * @param[in] err_code The error code to check.
+ */
+#ifdef DISABLE_PARAM_CHECK
+#define VERIFY_SUCCESS_VOID()
+#else
+#define VERIFY_SUCCESS_VOID(err_code) VERIFY_TRUE_VOID((err_code) == NRF_SUCCESS)
+#endif /* DISABLE_PARAM_CHECK */
+
+
+/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to
+ *        return @ref NRF_ERROR_INVALID_STATE if not.
+ *
+ * @note MODULE_INITIALIZED must be defined in each module using this macro. MODULE_INITIALIZED
+ *       should be true if the module is initialized, false if not.
+ */
+#ifdef DISABLE_PARAM_CHECK
+#define VERIFY_MODULE_INITIALIZED()
+#else
+#define VERIFY_MODULE_INITIALIZED() VERIFY_TRUE((MODULE_INITIALIZED), NRF_ERROR_INVALID_STATE)
+#endif /* DISABLE_PARAM_CHECK */
+
+
+/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to
+ *        return if not.
+ *
+ * @note MODULE_INITIALIZED must be defined in each module using this macro. MODULE_INITIALIZED
+ *       should be true if the module is initialized, false if not.
+ */
+#ifdef DISABLE_PARAM_CHECK
+#define VERIFY_MODULE_INITIALIZED_VOID()
+#else
+#define VERIFY_MODULE_INITIALIZED_VOID() VERIFY_TRUE_VOID((MODULE_INITIALIZED))
+#endif /* DISABLE_PARAM_CHECK */
+
+
+/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to
+ *        return if not.
+ *
+ * @param[in] param  The variable to check if is NULL.
+ */
+#ifdef DISABLE_PARAM_CHECK
+#define VERIFY_PARAM_NOT_NULL()
+#else
+#define VERIFY_PARAM_NOT_NULL(param) VERIFY_FALSE(((param) == NULL), NRF_ERROR_NULL)
+#endif /* DISABLE_PARAM_CHECK */
+
+
+/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to
+ *        return if not.
+ *
+ * @param[in] param  The variable to check if is NULL.
+ */
+#ifdef DISABLE_PARAM_CHECK
+#define VERIFY_PARAM_NOT_NULL_VOID()
+#else
+#define VERIFY_PARAM_NOT_NULL_VOID(param) VERIFY_FALSE_VOID(((param) == NULL))
+#endif /* DISABLE_PARAM_CHECK */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // SDK_MACROS_H__
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_mapped_flags.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,187 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "sdk_mapped_flags.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include "compiler_abstraction.h"
+
+
+/**@brief Function for setting the state of a flag to true.
+ *
+ * @note This function does not check whether the index is valid.
+ *
+ * @param[in]  p_flags  The collection of flags to modify.
+ * @param[in]  index    The index of the flag to modify.
+ */
+static __INLINE void sdk_mapped_flags_set_by_index(sdk_mapped_flags_t * p_flags, uint16_t index)
+{
+    *p_flags |= (1U << index);
+}
+
+
+/**@brief Function for setting the state of a flag to false.
+ *
+ * @note This function does not check whether the index is valid.
+ *
+ * @param[in]  p_flags  The collection of flags to modify.
+ * @param[in]  index    The index of the flag to modify.
+ */
+static __INLINE void sdk_mapped_flags_clear_by_index(sdk_mapped_flags_t * p_flags, uint16_t index)
+{
+    *p_flags &= ~(1U << index);
+}
+
+
+/**@brief Function for getting the state of a flag.
+ *
+ * @note This function does not check whether the index is valid.
+ *
+ * @param[in]  p_flags  The collection of flags to read.
+ * @param[in]  index    The index of the flag to get.
+ */
+static __INLINE bool sdk_mapped_flags_get_by_index(sdk_mapped_flags_t flags, uint16_t index)
+{
+    return ((flags & (1 << index)) != 0);
+}
+
+
+
+uint16_t sdk_mapped_flags_first_key_index_get(sdk_mapped_flags_t flags)
+{
+    for (uint16_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++)
+    {
+        if (sdk_mapped_flags_get_by_index(flags, i))
+        {
+            return i;
+        }
+    }
+    return SDK_MAPPED_FLAGS_INVALID_INDEX;
+}
+
+
+void sdk_mapped_flags_update_by_key(uint16_t           * p_keys,
+                                    sdk_mapped_flags_t * p_flags,
+                                    uint16_t             key,
+                                    bool                 value)
+{
+    sdk_mapped_flags_bulk_update_by_key(p_keys, p_flags, 1, key, value);
+}
+
+
+void sdk_mapped_flags_bulk_update_by_key(uint16_t           * p_keys,
+                                         sdk_mapped_flags_t * p_flags,
+                                         uint32_t             n_flag_collections,
+                                         uint16_t             key,
+                                         bool                 value)
+{
+    if ((p_keys != NULL) && (p_flags != NULL) && (n_flag_collections > 0))
+    {
+        for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++)
+        {
+            if (p_keys[i] == key)
+            {
+                for (uint32_t j = 0; j < n_flag_collections; j++)
+                {
+                    if (value)
+                    {
+                        sdk_mapped_flags_set_by_index(&p_flags[j], i);
+                    }
+                    else
+                    {
+                        sdk_mapped_flags_clear_by_index(&p_flags[j], i);
+                    }
+                }
+                return;
+            }
+        }
+    }
+}
+
+
+bool sdk_mapped_flags_get_by_key(uint16_t * p_keys, sdk_mapped_flags_t flags, uint16_t key)
+{
+    if (p_keys != NULL)
+    {
+        for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++)
+        {
+            if (p_keys[i] == key)
+            {
+                return sdk_mapped_flags_get_by_index(flags, i);
+            }
+        }
+    }
+    return false;
+}
+
+
+sdk_mapped_flags_key_list_t sdk_mapped_flags_key_list_get(uint16_t           * p_keys,
+                                                          sdk_mapped_flags_t   flags)
+{
+    sdk_mapped_flags_key_list_t key_list;
+    key_list.len = 0;
+
+    if (p_keys != NULL)
+    {
+        for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++)
+        {
+            if (sdk_mapped_flags_get_by_index(flags, i))
+            {
+                key_list.flag_keys[key_list.len++] = p_keys[i];
+            }
+        }
+    }
+
+    return key_list;
+}
+
+
+uint32_t sdk_mapped_flags_n_flags_set(sdk_mapped_flags_t flags)
+{
+    uint32_t n_flags_set = 0;
+
+    for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++)
+    {
+        if (sdk_mapped_flags_get_by_index(flags, i))
+        {
+            n_flags_set += 1;
+        }
+    }
+    return n_flags_set;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_mapped_flags.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,188 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef SDK_MAPPED_FLAGS_H__
+#define SDK_MAPPED_FLAGS_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "app_util.h"
+#include "compiler_abstraction.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @file
+ * @defgroup sdk_mapped_flags Mapped flags
+ * @ingroup app_common
+ * @{
+ * @brief Module for writing and reading flags that are associated
+ *        with keys.
+ *
+ * @details The flags are represented as bits in a bitmap called a <i>flag collection</i>. The keys
+ *          are uint16_t. Each flag collection contains all flags of the same type, one flag for
+ *          each key.
+ *
+ *          The mapped flags module does not keep the flag states, nor the list of keys. These are
+ *          provided in the API calls. A key's index in the key list determines which bit in the
+ *          flag collection is associated with it. This module does not ever edit the key list, and
+ *          does not edit flags except in function calls that take the flag collection as a pointer.
+ *
+ */
+
+#define SDK_MAPPED_FLAGS_N_KEYS          8       /**< The number of keys to keep flags for. This is also the number of flags in a flag collection. If changing this value, you might also need change the width of the sdk_mapped_flags_t type. */
+#define SDK_MAPPED_FLAGS_N_KEYS_PER_BYTE 8       /**< The number of flags that fit in one byte. */
+#define SDK_MAPPED_FLAGS_INVALID_INDEX   0xFFFF  /**< A flag index guaranteed to be invalid. */
+
+typedef uint8_t sdk_mapped_flags_t; /**< The bitmap to hold flags. Each flag is one bit, and each bit represents the flag state associated with one key. */
+
+
+// Test whether the flag collection type is large enough to hold all the flags. If this fails,
+// reduce SDK_MAPPED_FLAGS_N_KEYS or increase the size of sdk_mapped_flags_t.
+STATIC_ASSERT((
+    sizeof(sdk_mapped_flags_t) * SDK_MAPPED_FLAGS_N_KEYS_PER_BYTE) >= SDK_MAPPED_FLAGS_N_KEYS);
+
+
+/**@brief Type used to present a subset of the registered keys.
+ */
+typedef struct
+{
+    uint32_t len;                                 /**< The length of the list. */
+    uint16_t flag_keys[SDK_MAPPED_FLAGS_N_KEYS];  /**< The list of keys. */
+} sdk_mapped_flags_key_list_t;
+
+
+/**@brief Function for getting the first index at which the flag is true in the provided
+ *        collection.
+ *
+ * @param[in]  flags   The flag collection to search for a flag set to true.
+ *
+ * @return  The first index that has its flag set to true. If none were found, the
+ *          function returns @ref SDK_MAPPED_FLAGS_INVALID_INDEX.
+ */
+uint16_t sdk_mapped_flags_first_key_index_get(sdk_mapped_flags_t flags);
+
+
+/**@brief Function for updating the state of a flag.
+ *
+ * @param[in]  p_keys   The list of associated keys (assumed to have a length of
+ *                      @ref SDK_MAPPED_FLAGS_N_KEYS).
+ * @param[out] p_flags  The flag collection to modify.
+ * @param[in]  key      The key to modify the flag of.
+ * @param[in]  value    The state to set the flag to.
+ */
+void sdk_mapped_flags_update_by_key(uint16_t           * p_keys,
+                                    sdk_mapped_flags_t * p_flags,
+                                    uint16_t             key,
+                                    bool                 value);
+
+
+/**@brief Function for updating the state of the same flag in multiple flag collections.
+ *
+ * @details The key and value are the same for all flag collections in the p_flags array.
+ *
+ * @param[in]  p_keys              The list of associated keys (assumed to have a length of
+ *                                 @ref SDK_MAPPED_FLAGS_N_KEYS).
+ * @param[out] p_flags             The flag collections to modify.
+ * @param[out] n_flag_collections  The number of flag collections in p_flags.
+ * @param[in]  key                 The key to modify the flag of.
+ * @param[in]  value               The state to set the flag to.
+ */
+void sdk_mapped_flags_bulk_update_by_key(uint16_t           * p_keys,
+                                         sdk_mapped_flags_t * p_flags,
+                                         uint32_t             n_flag_collections,
+                                         uint16_t             key,
+                                         bool                 value);
+
+
+/**@brief Function for getting the state of a specific flag.
+ *
+ * @param[in]  p_keys  The list of associated keys (assumed to have a length of
+ *                     @ref SDK_MAPPED_FLAGS_N_KEYS).
+ * @param[in]  flags   The flag collection to read from.
+ * @param[in]  key     The key to get the flag for.
+ *
+ * @return  The state of the flag.
+ */
+bool sdk_mapped_flags_get_by_key(uint16_t * p_keys, sdk_mapped_flags_t flags, uint16_t key);
+
+
+/**@brief Function for getting a list of all keys that have a specific flag set to true.
+ *
+ * @param[in]  p_keys  The list of associated keys (assumed to have a length of
+ *                     @ref SDK_MAPPED_FLAGS_N_KEYS).
+ * @param[in]  flags   The flag collection to search.
+ *
+ * @return  The list of keys.
+ */
+sdk_mapped_flags_key_list_t sdk_mapped_flags_key_list_get(uint16_t           * p_keys,
+                                                          sdk_mapped_flags_t   flags);
+
+
+/**@brief Function for getting the number of keys that have a specific flag set to true.
+ *
+ * @param[in]  flags  The flag collection to search.
+ *
+ * @return  The number of keys.
+ */
+uint32_t sdk_mapped_flags_n_flags_set(sdk_mapped_flags_t flags);
+
+
+/**@brief Function for querying whether any flags in the collection are set.
+ *
+ * @param[in]  flags  The flag collection to query.
+ *
+ * @retval  true If one or more flags are set to true.
+ * @retval  false Otherwise.
+ */
+static __INLINE bool sdk_mapped_flags_any_set(sdk_mapped_flags_t flags)
+{
+    return (flags != 0);
+}
+
+
+/** @} */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SDK_MAPPED_FLAGS_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_os.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,75 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ /** @cond */
+/**@file
+ *
+ * @defgroup sdk_os SDK OS Abstraction
+ * @ingroup experimental_api
+ * @details In order to made SDK modules independent of use of an embedded OS, and permit
+ *          application with varied task architecture, SDK abstracts the OS specific
+ *          elements here in order to make all other modules agnostic to the OS or task
+ *          architecture.
+ * @{
+ */
+
+#ifndef SDK_OS_H__
+#define SDK_OS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SDK_MUTEX_DEFINE(X)
+#define SDK_MUTEX_INIT(X)
+#define SDK_MUTEX_LOCK(X)
+#define SDK_MUTEX_UNLOCK(X)
+
+/**
+ * @defgroup os_data_type Data types.
+ */
+
+/** @} */
+/** @endcond */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // SDK_OS_H__
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_resources.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,86 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ * @brief Definition file for resource usage by SoftDevice, ESB and Gazell.
+ */
+
+#ifndef APP_RESOURCES_H__
+#define APP_RESOURCES_H__
+
+#ifdef SOFTDEVICE_PRESENT
+    #include "nrf_sd_def.h"
+#else
+    #define SD_PPI_RESTRICTED         0uL /**< 1 if PPI peripheral is restricted, 0 otherwise. */
+    #define SD_PPI_CHANNELS_USED      0uL /**< PPI channels utilized by SotfDevice (not available to th spplication). */
+    #define SD_PPI_GROUPS_USED        0uL /**< PPI groups utilized by SotfDevice (not available to th spplication). */
+    #define SD_TIMERS_USED            0uL /**< Timers used by SoftDevice. */
+    #define SD_SWI_USED               0uL /**< Software interrupts used by SoftDevice. */
+#endif
+
+#ifdef GAZELL_PRESENT
+    #include "nrf_gzll_resources.h"
+#else
+    #define GZLL_PPI_CHANNELS_USED    0uL /**< PPI channels utilized by Gazell (not available to th spplication). */
+    #define GZLL_TIMERS_USED          0uL /**< Timers used by Gazell. */
+    #define GZLL_SWI_USED             0uL /**< Software interrupts used by Gazell */
+#endif
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifdef ESB_PRESENT
+    #include "nrf_esb_resources.h"
+#else
+    #define ESB_PPI_CHANNELS_USED    0uL /**< PPI channels utilized by ESB (not available to th spplication). */
+    #define ESB_TIMERS_USED          0uL /**< Timers used by ESB. */
+    #define ESB_SWI_USED             0uL /**< Software interrupts used by ESB */
+#endif
+
+#define NRF_PPI_CHANNELS_USED (SD_PPI_CHANNELS_USED | GZLL_PPI_CHANNELS_USED | ESB_PPI_CHANNELS_USED)
+#define NRF_PPI_GROUPS_USED   (SD_PPI_GROUPS_USED)
+#define NRF_SWI_USED          (SD_SWI_USED | GZLL_SWI_USED | ESB_SWI_USED)
+#define NRF_TIMERS_USED       (SD_TIMERS_USED | GZLL_TIMERS_USED | ESB_TIMERS_USED)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // APP_RESOURCES_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/sdk_validation.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,304 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef SDK_VALIDATION_H
+#define SDK_VALIDATION_H
+
+#include "nrf_peripherals.h"
+#include "sdk_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Validate peripheral availibility
+
+#if ((defined(SAADC_ENABLED)) && (SAADC_ENABLED > 0) && (!defined(SAADC_PRESENT)))
+#error "SAADC not present in selected MCU."
+#endif
+
+#if ((defined(ADC_ENABLED)) && (ADC_ENABLED > 0) && (!defined(ADC_PRESENT)))
+#error "SAADC not present in selected MCU."
+#endif
+
+#if ((defined(I2S_ENABLED)) && (I2S_ENABLED > 0) && (!defined(I2S_PRESENT)))
+#error "I2S not present in selected MCU."
+#endif
+
+#if ((defined(COMP_ENABLED)) && (COMP_ENABLED > 0) && (!defined(COMP_PRESENT)))
+#error "COMP not present in selected MCU."
+#endif
+
+#if ((defined(LPCOMP_ENABLED)) && (LPCOMP_ENABLED > 0) && (!defined(LPCOMP_PRESENT)))
+#error "LPCOMP not present in selected MCU."
+#endif
+
+#if ((defined(SPIS0_ENABLED)) && (SPIS0_ENABLED > 0) && (!defined(SPIS_PRESENT)))
+#error "SPIS0 instance not present in selected MCU."
+#endif
+
+#if ((defined(EGU_ENABLED)) && (EGU_ENABLED > 0) && (!defined(EGU_PRESENT)))
+#error "EGU instance not present in selected MCU."
+#endif
+
+#if ((defined(NFC_HAL_ENABLED)) && (NFC_HAL_ENABLED > 0) && (!defined(NFCT_PRESENT)))
+#error "NFC TAG not present in selected MCU."
+#endif
+
+// Validate count of instances
+
+#if ((defined(RTC2_ENABLED)) && (RTC2_ENABLED > 0) && (RTC_COUNT < 2))
+#error "RTC2 not present in selected MCU."
+#endif
+
+#if ((defined(TWIS0_ENABLED) || defined(TWIS1_ENABLED)) &&\
+    ((TWIS0_ENABLED + TWIS1_ENABLED) > 0) &&\
+    (!defined(TWIS_PRESENT)))
+#error "TWIS not present in selected MCU."
+#endif
+
+#if ((defined(SPIS2_ENABLED)) && (SPIS2_ENABLED > 0) && (SPIS_COUNT < 2))
+#error "SPI2/SPIS2 instance not present in selected MCU."
+#endif
+
+#if ((defined(TIMER3_ENABLED) || defined(TIMER4_ENABLED)) &&\
+    ((TIMER3_ENABLED + TIMER4_ENABLED ) > 0) &&\
+    (TIMER_COUNT < 5))
+#error "TIMER3 and TIMER4 not present in selected MCU."
+#endif
+
+// Validate peripheral sharing feature
+#if ((defined(PERIPHERAL_RESOURCE_SHARING_ENABLED)) && (!PERIPHERAL_RESOURCE_SHARING_ENABLED))
+
+#if ((defined(TWIM0_ENABLED) && defined(TWIS0_ENABLED)) &&\
+    ((TWIM0_ENABLED + TWIS0_ENABLED) > 1))
+#error "Peripherals overlap. TWIM0, TWIS0 - only one of these can be enabled."
+#endif
+
+#if ((defined(TWIM0_ENABLED) && defined(SPIM0_ENABLED)) &&\
+    ((TWIM0_ENABLED + SPIM0_ENABLED) > 1))
+#error "Peripherals overlap. TWIM0, SPIM0 - only one of these can be enabled."
+#endif
+
+#if ((defined(TWIM0_ENABLED) && defined(SPIS0_ENABLED)) &&\
+    ((TWIM0_ENABLED + SPIS0_ENABLED) > 1))
+#error "Peripherals overlap. TWIM0, SPIS0 - only one of these can be enabled."
+#endif
+
+#if ((defined(TWIM0_ENABLED) && defined(SPI0_ENABLED)) &&\
+    ((TWIM0_ENABLED + SPI0_ENABLED) > 1))
+#error "Peripherals overlap. TWIM0, SPI0 - only one of these can be enabled."
+#endif
+
+#if ((defined(TWIM0_ENABLED) && defined(TWI0_ENABLED)) &&\
+    ((TWIM0_ENABLED + TWI0_ENABLED) > 1))
+#error "Peripherals overlap. TWIM0, TWI0 - only one of these can be enabled."
+#endif
+
+#if ((defined(TWIS0_ENABLED) && defined(SPIM0_ENABLED)) &&\
+    ((TWIS0_ENABLED + SPIM0_ENABLED) > 1))
+#error "Peripherals overlap. TWIS0, SPIM0 - only one of these can be enabled."
+#endif
+
+#if ((defined(TWIS0_ENABLED) && defined(SPIS0_ENABLED)) &&\
+    ((TWIS0_ENABLED + SPIS0_ENABLED) > 1))
+#error "Peripherals overlap. TWIS0, SPIS0 - only one of these can be enabled."
+#endif
+
+#if ((defined(TWIS0_ENABLED) && defined(SPI0_ENABLED)) &&\
+    ((TWIS0_ENABLED + SPI0_ENABLED) > 1))
+#error "Peripherals overlap. TWIS0, SPI0 - only one of these can be enabled."
+#endif
+
+#if ((defined(TWIS0_ENABLED) && defined(TWI0_ENABLED)) &&\
+    ((TWIS0_ENABLED + TWI0_ENABLED) > 1))
+#error "Peripherals overlap. TWIS0, TWI0 - only one of these can be enabled."
+#endif
+
+#if ((defined(SPIM0_ENABLED) && defined(SPIS0_ENABLED)) &&\
+    ((SPIM0_ENABLED + SPIS0_ENABLED) > 1))
+#error "Peripherals overlap. SPIM0, SPIS0 - only one of these can be enabled."
+#endif
+
+#if ((defined(SPIM0_ENABLED) && defined(SPI0_ENABLED)) &&\
+    ((SPIM0_ENABLED + SPI0_ENABLED) > 1))
+#error "Peripherals overlap. SPIM0, SPI0 - only one of these can be enabled."
+#endif
+
+#if ((defined(SPIM0_ENABLED) && defined(TWI0_ENABLED)) &&\
+    ((SPIM0_ENABLED + TWI0_ENABLED) > 1))
+#error "Peripherals overlap. SPIM0, TWI0 - only one of these can be enabled."
+#endif
+
+#if ((defined(SPIS0_ENABLED) && defined(SPI0_ENABLED)) &&\
+    ((SPIS0_ENABLED + SPI0_ENABLED) > 1))
+#error "Peripherals overlap. SPIS0, SPI0 - only one of these can be enabled."
+#endif
+
+#if ((defined(SPIS0_ENABLED) && defined(TWI0_ENABLED)) &&\
+    ((SPIS0_ENABLED + TWI0_ENABLED) > 1))
+#error "Peripherals overlap. SPIS0, TWI0 - only one of these can be enabled."
+#endif
+
+#if ((defined(SPI0_ENABLED) && defined(TWI0_ENABLED)) &&\
+    ((SPI0_ENABLED + TWI0_ENABLED) > 1))
+#error "Peripherals overlap. SPI0, TWI0 - only one of these can be enabled."
+#endif
+
+#if ((defined(TWIM1_ENABLED) && defined(TWIS1_ENABLED)) &&\
+    ((TWIM1_ENABLED + TWIS1_ENABLED) > 1))
+#error "Peripherals overlap. TWIM1, TWIS1 - only one of these can be enabled."
+#endif
+
+#if ((defined(TWIM1_ENABLED) && defined(SPIM1_ENABLED)) &&\
+    ((TWIM1_ENABLED + SPIM1_ENABLED) > 1))
+#error "Peripherals overlap. TWIM1, SPIM1 - only one of these can be enabled."
+#endif
+
+#if ((defined(TWIM1_ENABLED) && defined(SPIS1_ENABLED)) &&\
+    ((TWIM1_ENABLED + SPIS1_ENABLED) > 1))
+#error "Peripherals overlap. TWIM1, SPIS1 - only one of these can be enabled."
+#endif
+
+#if ((defined(TWIM1_ENABLED) && defined(SPI1_ENABLED)) &&\
+    ((TWIM1_ENABLED + SPI1_ENABLED) > 1))
+#error "Peripherals overlap. TWIM1, SPI1 - only one of these can be enabled."
+#endif
+
+#if ((defined(TWIM1_ENABLED) && defined(TWI1_ENABLED)) &&\
+    ((TWIM1_ENABLED + TWI1_ENABLED) > 1))
+#error "Peripherals overlap. TWIM1, TWI1 - only one of these can be enabled."
+#endif
+
+#if ((defined(TWIS1_ENABLED) && defined(SPIM1_ENABLED)) &&\
+    ((TWIS1_ENABLED + SPIM1_ENABLED) > 1))
+#error "Peripherals overlap. TWIS1, SPIM1 - only one of these can be enabled."
+#endif
+
+#if ((defined(TWIS1_ENABLED) && defined(SPIS1_ENABLED)) &&\
+    ((TWIS1_ENABLED + SPIS1_ENABLED) > 1))
+#error "Peripherals overlap. TWIS1, SPIS1 - only one of these can be enabled."
+#endif
+
+#if ((defined(TWIS1_ENABLED) && defined(SPI1_ENABLED)) &&\
+    ((TWIS1_ENABLED + SPI1_ENABLED) > 1))
+#error "Peripherals overlap. TWIS1, SPI1 - only one of these can be enabled."
+#endif
+
+#if ((defined(TWIS1_ENABLED) && defined(TWI1_ENABLED)) &&\
+    ((TWIS1_ENABLED + TWI1_ENABLED) > 1))
+#error "Peripherals overlap. TWIS1, TWI1 - only one of these can be enabled."
+#endif
+
+#if ((defined(SPIM1_ENABLED) && defined(SPIS1_ENABLED)) &&\
+    ((SPIM1_ENABLED + SPIS1_ENABLED) > 1))
+#error "Peripherals overlap. SPIM1, SPIS1 - only one of these can be enabled."
+#endif
+
+#if ((defined(SPIM1_ENABLED) && defined(SPI1_ENABLED)) &&\
+    ((SPIM1_ENABLED + SPI1_ENABLED) > 1))
+#error "Peripherals overlap. SPIM1, SPI1 - only one of these can be enabled."
+#endif
+
+#if ((defined(SPIM1_ENABLED) && defined(TWI1_ENABLED)) &&\
+    ((SPIM1_ENABLED + TWI1_ENABLED) > 1))
+#error "Peripherals overlap. SPIM1, TWI1 - only one of these can be enabled."
+#endif
+
+#if ((defined(SPIS1_ENABLED) && defined(SPI1_ENABLED)) &&\
+    ((SPIS1_ENABLED + SPI1_ENABLED) > 1))
+#error "Peripherals overlap. SPIS1, SPI1 - only one of these can be enabled."
+#endif
+
+#if ((defined(SPIS1_ENABLED) && defined(TWI1_ENABLED)) &&\
+    ((SPIS1_ENABLED + TWI1_ENABLED) > 1))
+#error "Peripherals overlap. SPIS1, TWI1 - only one of these can be enabled."
+#endif
+
+#if ((defined(SPI1_ENABLED) && defined(TWI1_ENABLED)) &&\
+    ((SPI1_ENABLED + TWI1_ENABLED) > 1))
+#error "Peripherals overlap. SPI1, TWI1 - only one of these can be enabled."
+#endif
+
+#if ((defined(SPI2_ENABLED) && defined(SPIS2_ENABLED)) &&\
+    ((SPI2_ENABLED + SPIS2_ENABLED) > 1))
+#error "Peripherals overlap. SPI2, SPIS2 - only one of these can be enabled."
+#endif
+
+#if ((defined(SPIM2_ENABLED) && defined(SPIS2_ENABLED)) &&\
+    ((SPI2_ENABLED + SPIS2_ENABLED) > 1))
+#error "Peripherals overlap. SPIM2, SPIS2 - only one of these can be enabled."
+#endif
+
+#if ((defined(SPIM2_ENABLED) && defined(SPI2_ENABLED)) &&\
+    ((SPI2_ENABLED + SPIS2_ENABLED) > 1))
+#error "Peripherals overlap. SPIM2, SPI2 - only one of these can be enabled."
+#endif
+
+#endif
+
+#ifdef NFCT_PRESENT
+
+#if ((defined(NFC_HAL_ENABLED) && defined(CLOCK_ENABLED)) &&\
+    ((NFC_HAL_ENABLED) && (!CLOCK_ENABLED)))
+#error "NFC_HAL requires CLOCK to work. NFC_HAL can not be enabled without CLOCK."
+#endif
+
+#if ((defined(NFC_HAL_ENABLED) && defined(TIMER4_ENABLED)) &&\
+    ((NFC_HAL_ENABLED + TIMER4_ENABLED) > 1))
+#error "TIMER4 is used by NFC_HAL. NFC_HAL, TIMER4 - only one of these can be enabled."
+#endif
+
+#endif
+// Complex driver validation
+#ifdef LPCOMP_PRESENT
+
+#if ((defined(COMP_ENABLED) && defined(LPCOMP_ENABLED)) &&\
+    (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \
+    ((COMP_ENABLED + LPCOMP_ENABLED) > 1))
+#error "Peripherals overlap. SPIM2, SPI2 - only one of these can be enabled."
+#endif
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // SDK_VALIDATION_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/ant_stack_handler_types.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,109 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**@file
+ *
+ * @defgroup ant_stack_handler_types Types definitions for ANT support in SoftDevice handler.
+ * @{
+ * @ingroup  softdevice_handler
+ * @brief    This file contains the declarations of types required for ANT stack support. These
+ *           types will be defined when the preprocessor define ANT_STACK_SUPPORT_REQD is defined.
+ */
+
+#ifndef ANT_STACK_HANDLER_TYPES_H__
+#define ANT_STACK_HANDLER_TYPES_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef ANT_STACK_SUPPORT_REQD
+
+#include <stdlib.h>
+#include <stdint.h>
+
+#define ANT_STACK_EVT_MSG_BUF_SIZE      32                                                /**< Size of ANT event message buffer. This will be provided to the SoftDevice while fetching an event. */
+#define ANT_STACK_EVT_STRUCT_SIZE       (sizeof(ant_evt_t))                               /**< Size of the @ref ant_evt_t structure. This will be used by the @ref softdevice_handler to internal event buffer size needed. */
+
+/**@brief ANT stack event type. */
+typedef struct
+{
+    union
+    {
+        uint32_t ulForceAlign;                           ///< force the evt_buffer to be 4-byte aligned, required for some casting to ANT_MESSAGE.
+        uint8_t  evt_buffer[ANT_STACK_EVT_MSG_BUF_SIZE]; ///< Event message buffer.
+    } msg;
+    uint8_t channel;                                     ///< Channel number.
+    uint8_t event;                                       ///< Event code.
+} ant_evt_t;
+
+/**@brief Application ANT stack event handler type. */
+typedef void (*ant_evt_handler_t) (ant_evt_t * p_ant_evt);
+
+/**@brief     Function for registering for ANT events.
+ *
+ * @details   The application should use this function to register for receiving ANT events from
+ *            the SoftDevice. If the application does not call this function, then any ANT event
+ *            that may be generated by the SoftDevice will NOT be fetched. Once the application has
+ *            registered for the events, it is not possible to  possible to cancel the registration.
+ *            However, it is possible to register a different function for handling the events at
+ *            any point of time.
+ *
+ * @param[in] ant_evt_handler Function to be called for each received ANT event.
+ *
+ * @retval    NRF_SUCCESS     Successful registration.
+ * @retval    NRF_ERROR_NULL  Null pointer provided as input.
+ */
+uint32_t softdevice_ant_evt_handler_set(ant_evt_handler_t ant_evt_handler);
+
+#else
+
+// The ANT Stack support is not required.
+
+#define ANT_STACK_EVT_STRUCT_SIZE       0                                                 /**< Since the ANT stack support is not required, this is equated to 0, so that the @ref softdevice_handler.h can compute the internal event buffer size without having to care for ANT events.*/
+
+#endif // ANT_STACK_SUPPORT_REQD
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // ANT_STACK_HANDLER_TYPES_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/app_ram_base.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,186 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+// ble_enable param app_ram_base
+
+#ifndef APP_RAM_BASE_H__
+#define APP_RAM_BASE_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef S130
+    #define APP_RAM_BASE_CENTRAL_LINKS_0_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20001870
+    #define APP_RAM_BASE_CENTRAL_LINKS_0_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20001900
+    #define APP_RAM_BASE_CENTRAL_LINKS_0_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20001fe8
+    #define APP_RAM_BASE_CENTRAL_LINKS_0_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20002078
+    #define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20001ce0
+    #define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20001d70
+    #define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20001eb0
+    #define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20001f40
+    #define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20002418
+    #define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x200024a8
+    #define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x200025e0
+    #define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20002670
+    #define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20002110
+    #define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x200021a0
+    #define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x200022d8
+    #define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20002368
+    #define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20002840
+    #define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x200028d0
+    #define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20002a10
+    #define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20002aa0
+    #define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20002538
+    #define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x200025c8
+    #define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20002708
+    #define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20002798
+    #define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20002c70
+    #define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20002d00
+    #define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20002e40
+    #define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20002ed0
+    #define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20002968
+    #define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x200029f8
+    #define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20002b30
+    #define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20002bc0
+    #define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x200030a0
+    #define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20003130
+    #define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20003268
+    #define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x200032f8
+    #define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20002d98
+    #define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20002e28
+    #define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20002f60
+    #define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20002ff0
+    #define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x200034c8
+    #define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20003558
+    #define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20003698
+    #define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20003728
+    #define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x200031c0
+    #define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20003250
+    #define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20003390
+    #define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20003420
+    #define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x200038f8
+    #define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20003988
+    #define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20003ac0
+    #define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20003b50
+    #define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x200035f0
+    #define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20003680
+    #define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x200037b8
+    #define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20003848
+    #define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20003d28
+    #define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20003db8
+    #define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20003ef0
+    #define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20003f80
+    #define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20003a18
+    #define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20003aa8
+    #define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20003be8
+    #define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20003c78
+#elif defined(S132) || defined(S332)
+    #define APP_RAM_BASE_CENTRAL_LINKS_0_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20001930
+    #define APP_RAM_BASE_CENTRAL_LINKS_0_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x200019c0
+    #define APP_RAM_BASE_CENTRAL_LINKS_0_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20002128
+    #define APP_RAM_BASE_CENTRAL_LINKS_0_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x200021b8
+    #define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20001e18
+    #define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20001ea8
+    #define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20001fe8
+    #define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20002078
+    #define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x200025d0
+    #define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20002660
+    #define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20002798
+    #define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20002828
+    #define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x200022c0
+    #define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20002350
+    #define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20002490
+    #define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20002520
+    #define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20002a78
+    #define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20002b08
+    #define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20002c40
+    #define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20002cd0
+    #define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20002768
+    #define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x200027f8
+    #define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20002938
+    #define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x200029c8
+    #define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20002f20
+    #define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20002fb0
+    #define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x200030e8
+    #define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20003178
+    #define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20002c10
+    #define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20002ca0
+    #define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20002de0
+    #define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20002e70
+    #define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x200033c8
+    #define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20003458
+    #define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20003590
+    #define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20003620
+    #define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x200030b8
+    #define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20003148
+    #define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20003288
+    #define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20003318
+    #define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20003870
+    #define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20003900
+    #define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20003a38
+    #define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20003ac8
+    #define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20003560
+    #define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x200035f0
+    #define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20003730
+    #define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x200037c0
+    #define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20003d18
+    #define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20003da8
+    #define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20003ee0
+    #define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20003f70
+    #define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20003a08
+    #define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20003a98
+    #define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20003bd8
+    #define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20003c68
+    #define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x200041c0
+    #define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20004250
+    #define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20004388
+    #define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20004418
+    #define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_1_MID_BW 0x20003eb0
+    #define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_0_VS_UUID_COUNT_10_MID_BW 0x20003f40
+    #define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_1_MID_BW 0x20004080
+    #define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_1_VS_UUID_COUNT_10_MID_BW 0x20004110
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // APP_RAM_BASE_H__

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/ble_stack_handler_types.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,112 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**@file
+ *
+ * @defgroup ble_stack_handler_types Types definitions for BLE support in SoftDevice handler.
+ * @{
+ * @ingroup  softdevice_handler
+ * @brief    This file contains the declarations of types required for BLE stack support. These
+ *           types will be defined when the preprocessor define BLE_STACK_SUPPORT_REQD is defined.
+ */
+
+#ifndef BLE_STACK_HANDLER_TYPES_H__
+#define BLE_STACK_HANDLER_TYPES_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BLE_STACK_SUPPORT_REQD
+
+#include <stdlib.h>
+#include "headers/ble.h"
+#include "nrf_sdm.h"
+#include "app_error.h"
+#include "app_util.h"
+#include "sdk_config.h"
+
+/** @brief  Default Maximum ATT MTU size.
+ *
+ * This define should be defined in the sdk_config.h file to override the default.
+ */
+#ifndef NRF_BLE_GATT_MAX_MTU_SIZE
+    #if ((NRF_SD_BLE_API_VERSION == 2) || (NRF_SD_BLE_API_VERSION == 3))
+        #define NRF_BLE_GATT_MAX_MTU_SIZE GATT_MTU_SIZE_DEFAULT
+    #else
+        #define NRF_BLE_GATT_MAX_MTU_SIZE BLE_GATT_MTU_SIZE_DEFAULT
+    #endif
+#endif
+
+#define BLE_STACK_EVT_MSG_BUF_SIZE       (sizeof(ble_evt_t) + (NRF_BLE_GATT_MAX_MTU_SIZE))     /**< Size of BLE event message buffer. This will be provided to the SoftDevice while fetching an event. */
+#define BLE_STACK_HANDLER_SCHED_EVT_SIZE 0                                                     /**< The size of the scheduler event used by SoftDevice handler when passing BLE events using the @ref app_scheduler. */
+
+/**@brief Application stack event handler type. */
+typedef void (*ble_evt_handler_t) (ble_evt_t * p_ble_evt);
+
+/**@brief     Function for registering for BLE events.
+ *
+ * @details   The application should use this function to register for receiving BLE events from
+ *            the SoftDevice. If the application does not call this function, then any BLE event
+ *            that may be generated by the SoftDevice will NOT be fetched. Once the application has
+ *            registered for the events, it is not possible to cancel the registration.
+ *            However, it is possible to register a different function for handling the events at
+ *            any point of time.
+ *
+ * @param[in] ble_evt_handler Function to be called for each received BLE event.
+ *
+ * @retval    NRF_SUCCESS     Successful registration.
+ * @retval    NRF_ERROR_NULL  Null pointer provided as input.
+ */
+uint32_t softdevice_ble_evt_handler_set(ble_evt_handler_t ble_evt_handler);
+
+#else
+
+#define BLE_STACK_EVT_MSG_BUF_SIZE        0                                                /**< Since the BLE stack support is not required, this is equated to 0, so that the @ref softdevice_handler.h can compute the internal event buffer size without having to care for BLE events.*/
+#define BLE_STACK_HANDLER_SCHED_EVT_SIZE  0
+
+#endif // BLE_STACK_SUPPORT_REQD
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // BLE_STACK_HANDLER_TYPES_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/softdevice_handler.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,559 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+#include "softdevice_handler.h"
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include "nrf.h"
+#include "nrf_assert.h"
+#include "nrf_soc.h"
+#include "nrf_nvic.h"
+#include "sdk_common.h"
+
+#if NRF_MODULE_ENABLED(CLOCK)
+#include "nrf_drv_clock.h"
+#endif // NRF_MODULE_ENABLED(CLOCK)
+#include "app_error.h"
+
+#if NRF_MODULE_ENABLED(RNG)
+#include "nrf_drv_rng.h"
+#endif // NRF_MODULE_ENABLED(RNG)
+
+#define NRF_LOG_MODULE_NAME "SDH"
+#include "nrf_log.h"
+#if defined(ANT_STACK_SUPPORT_REQD) && defined(BLE_STACK_SUPPORT_REQD)
+    #include "ant_interface.h"
+#elif defined(ANT_STACK_SUPPORT_REQD)
+    #include "ant_interface.h"
+#elif defined(BLE_STACK_SUPPORT_REQD)
+    #include "headers/ble.h"
+#endif
+
+#define RAM_START_ADDRESS         0x20000000
+#define SOFTDEVICE_EVT_IRQ        SD_EVT_IRQn       /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */
+#define SOFTDEVICE_EVT_IRQHandler SD_EVT_IRQHandler
+#define RAM_TOTAL_SIZE            ((NRF_FICR->INFO.RAM) * 1024)
+#define RAM_END_ADDRESS           (RAM_START_ADDRESS + RAM_TOTAL_SIZE)
+
+
+#define SOFTDEVICE_VS_UUID_COUNT       0
+#define SOFTDEVICE_GATTS_ATTR_TAB_SIZE BLE_GATTS_ATTR_TAB_SIZE_DEFAULT
+#define SOFTDEVICE_GATTS_SRV_CHANGED   0
+#define SOFTDEVICE_PERIPH_CONN_COUNT   1
+#define SOFTDEVICE_CENTRAL_CONN_COUNT  4
+#define SOFTDEVICE_CENTRAL_SEC_COUNT   1
+
+static softdevice_evt_schedule_func_t m_evt_schedule_func;              /**< Pointer to function for propagating SoftDevice events to the scheduler. */
+
+static volatile bool                  m_softdevice_enabled = false;     /**< Variable to indicate whether the SoftDevice is enabled. */
+static volatile bool                  m_suspended;                      /**< Current state of the event handler. */
+#ifdef BLE_STACK_SUPPORT_REQD
+// The following three definitions is needed only if BLE events are needed to be pulled from the stack.
+static uint8_t                      * mp_ble_evt_buffer;                /**< Buffer for receiving BLE events from the SoftDevice. */
+static uint16_t                       m_ble_evt_buffer_size;            /**< Size of BLE event buffer. */
+static ble_evt_handler_t              m_ble_evt_handler;                /**< Application event handler for handling BLE events. */
+#endif
+
+#ifdef ANT_STACK_SUPPORT_REQD
+// The following two definitions are needed only if ANT events are needed to be pulled from the stack.
+static ant_evt_t                      m_ant_evt_buffer;                 /**< Buffer for receiving ANT events from the SoftDevice. */
+static ant_evt_handler_t              m_ant_evt_handler;                /**< Application event handler for handling ANT events.  */
+#endif
+
+static sys_evt_handler_t              m_sys_evt_handler;                /**< Application event handler for handling System (SOC) events.  */
+
+/**@brief       Callback function for asserts in the SoftDevice.
+ *
+ * @details     A pointer to this function will be passed to the SoftDevice. This function will be
+ *              called by the SoftDevice if certain unrecoverable errors occur within the
+ *              application or SoftDevice.
+ *
+ *              See @ref nrf_fault_handler_t for more details.
+ *
+ * @param[in] id    Fault identifier. See @ref NRF_FAULT_IDS.
+ * @param[in] pc    The program counter of the instruction that triggered the fault.
+ * @param[in] info  Optional additional information regarding the fault. Refer to each fault
+ *                  identifier for details.
+ */
+void softdevice_fault_handler(uint32_t id, uint32_t pc, uint32_t info)
+{
+    app_error_fault_handler(id, pc, info);
+}
+
+void intern_softdevice_events_execute(void)
+{
+    if (!m_softdevice_enabled)
+    {
+        // SoftDevice not enabled. This can be possible if the SoftDevice was enabled by the
+        // application without using this module's API (i.e softdevice_handler_init)
+
+        return;
+    }
+#if NRF_MODULE_ENABLED(CLOCK)
+    bool no_more_soc_evts = false;
+#else
+    bool no_more_soc_evts = (m_sys_evt_handler == NULL);
+#endif
+#ifdef BLE_STACK_SUPPORT_REQD
+    bool no_more_ble_evts = (m_ble_evt_handler == NULL);
+#endif
+#ifdef ANT_STACK_SUPPORT_REQD
+    bool no_more_ant_evts = (m_ant_evt_handler == NULL);
+#endif
+
+    for (;;)
+    {
+        uint32_t err_code;
+
+        if (!no_more_soc_evts)
+        {
+            if (m_suspended)
+            {
+                // Cancel pulling next event if event handler was suspended by user.
+                return;
+            }
+
+            uint32_t evt_id;
+
+            // Pull event from SOC.
+            err_code = sd_evt_get(&evt_id);
+
+            if (err_code == NRF_ERROR_NOT_FOUND)
+            {
+                no_more_soc_evts = true;
+            }
+            else if (err_code != NRF_SUCCESS)
+            {
+                APP_ERROR_HANDLER(err_code);
+            }
+            else
+            {
+                // Call application's SOC event handler.
+#if (NRF_MODULE_ENABLED(CLOCK) && defined(SOFTDEVICE_PRESENT))
+                nrf_drv_clock_on_soc_event(evt_id);
+                if (m_sys_evt_handler)
+                {
+                    m_sys_evt_handler(evt_id);
+                }
+#else
+                m_sys_evt_handler(evt_id);
+#endif
+            }
+        }
+
+#ifdef BLE_STACK_SUPPORT_REQD
+        // Fetch BLE Events.
+        if (!no_more_ble_evts)
+        {
+            if (m_suspended)
+            {
+                // Cancel pulling next event if event handler was suspended by user.
+                return;
+            }
+
+            // Pull event from stack
+            uint16_t evt_len = m_ble_evt_buffer_size;
+
+            err_code = sd_ble_evt_get(mp_ble_evt_buffer, &evt_len);
+            if (err_code == NRF_ERROR_NOT_FOUND)
+            {
+                no_more_ble_evts = true;
+            }
+            else if (err_code != NRF_SUCCESS)
+            {
+                APP_ERROR_HANDLER(err_code);
+            }
+            else
+            {
+                // Call application's BLE stack event handler.
+                m_ble_evt_handler((ble_evt_t *)mp_ble_evt_buffer);
+            }
+        }
+#endif
+
+#ifdef ANT_STACK_SUPPORT_REQD
+        // Fetch ANT Events.
+        if (!no_more_ant_evts)
+        {
+            if (m_suspended)
+            {
+                // Cancel pulling next event if event handler was suspended by user.
+                return;
+            }
+
+            // Pull event from stack
+            err_code = sd_ant_event_get(&m_ant_evt_buffer.channel,
+                                        &m_ant_evt_buffer.event,
+                                        m_ant_evt_buffer.msg.evt_buffer);
+            if (err_code == NRF_ERROR_NOT_FOUND)
+            {
+                no_more_ant_evts = true;
+            }
+            else if (err_code != NRF_SUCCESS)
+            {
+                APP_ERROR_HANDLER(err_code);
+            }
+            else
+            {
+                // Call application's ANT stack event handler.
+                m_ant_evt_handler(&m_ant_evt_buffer);
+            }
+        }
+#endif
+
+        if (no_more_soc_evts)
+        {
+            // There are no remaining System (SOC) events to be fetched from the SoftDevice.
+#if defined(ANT_STACK_SUPPORT_REQD) && defined(BLE_STACK_SUPPORT_REQD)
+            // Check if there are any remaining BLE and ANT events.
+            if (no_more_ble_evts && no_more_ant_evts)
+            {
+                break;
+            }
+#elif defined(BLE_STACK_SUPPORT_REQD)
+            // Check if there are any remaining BLE events.
+            if (no_more_ble_evts)
+            {
+                break;
+            }
+#elif defined(ANT_STACK_SUPPORT_REQD)
+            // Check if there are any remaining ANT events.
+            if (no_more_ant_evts)
+            {
+                break;
+            }
+#else
+            // No need to check for BLE or ANT events since there is no support for BLE and ANT
+            // required.
+            break;
+#endif
+        }
+    }
+}
+
+bool softdevice_handler_is_enabled(void)
+{
+    return m_softdevice_enabled;
+}
+
+uint32_t softdevice_handler_init(nrf_clock_lf_cfg_t *           p_clock_lf_cfg,
+                                 void *                         p_ble_evt_buffer,
+                                 uint16_t                       ble_evt_buffer_size,
+                                 softdevice_evt_schedule_func_t evt_schedule_func)
+{
+    uint32_t err_code;
+
+    // Save configuration.
+#if defined (BLE_STACK_SUPPORT_REQD)
+    // Check that buffer is not NULL.
+    if (p_ble_evt_buffer == NULL)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    // Check that buffer is correctly aligned.
+    if (!is_word_aligned(p_ble_evt_buffer))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    mp_ble_evt_buffer     = (uint8_t *)p_ble_evt_buffer;
+    m_ble_evt_buffer_size = ble_evt_buffer_size;
+#else
+    // The variables p_ble_evt_buffer and ble_evt_buffer_size is not needed if BLE Stack support
+    // is not required.
+    UNUSED_PARAMETER(p_ble_evt_buffer);
+    UNUSED_PARAMETER(ble_evt_buffer_size);
+#endif
+
+    m_evt_schedule_func = evt_schedule_func;
+
+    // Initialize SoftDevice.
+#if (NRF_MODULE_ENABLED(CLOCK) && defined(SOFTDEVICE_PRESENT))
+    bool power_clock_isr_enabled = nrf_drv_common_irq_enable_check(POWER_CLOCK_IRQn);
+    if (power_clock_isr_enabled)
+    {
+        NVIC_DisableIRQ(POWER_CLOCK_IRQn);
+    }
+#endif
+
+#if (NRF_MODULE_ENABLED(RNG) && defined(SOFTDEVICE_PRESENT))
+    bool rng_isr_enabled = nrf_drv_common_irq_enable_check(RNG_IRQn);
+    if (rng_isr_enabled)
+    {
+        NVIC_DisableIRQ(RNG_IRQn);
+    }
+#endif
+#if defined(S212) || defined(S332)
+    err_code = sd_softdevice_enable(p_clock_lf_cfg, softdevice_fault_handler, ANT_LICENSE_KEY);
+#else
+    err_code = sd_softdevice_enable(p_clock_lf_cfg, softdevice_fault_handler);
+#endif
+
+    if (err_code != NRF_SUCCESS)
+    {
+#if (NRF_MODULE_ENABLED(RNG) && defined(SOFTDEVICE_PRESENT))
+        if (rng_isr_enabled)
+        {
+            NVIC_EnableIRQ(RNG_IRQn);
+        }
+#endif
+#if (NRF_MODULE_ENABLED(CLOCK) && defined(SOFTDEVICE_PRESENT))
+        if (power_clock_isr_enabled)
+        {
+            NVIC_EnableIRQ(POWER_CLOCK_IRQn);
+        }
+#endif
+        return err_code;
+    }
+
+    m_softdevice_enabled = true;
+#if (NRF_MODULE_ENABLED(CLOCK) && defined(SOFTDEVICE_PRESENT))
+        nrf_drv_clock_on_sd_enable();
+#endif
+
+    // Enable BLE event interrupt (interrupt priority has already been set by the stack).
+#ifdef SOFTDEVICE_PRESENT
+    err_code = sd_nvic_EnableIRQ((IRQn_Type)SOFTDEVICE_EVT_IRQ);
+		return err_code;
+
+#else
+    //In case of Serialization NVIC must be accessed directly.
+    NVIC_EnableIRQ(SOFTDEVICE_EVT_IRQ);
+    return NRF_SUCCESS;
+#endif
+}
+
+
+uint32_t softdevice_handler_sd_disable(void)
+{
+    uint32_t err_code = sd_softdevice_disable();
+    if (err_code == NRF_SUCCESS)
+    {
+        m_softdevice_enabled = false;
+
+#if (NRF_MODULE_ENABLED(CLOCK) && defined(SOFTDEVICE_PRESENT))
+        nrf_drv_clock_on_sd_disable();
+#endif
+
+#if (NRF_MODULE_ENABLED(RNG) && defined(SOFTDEVICE_PRESENT))
+        nrf_drv_rng_on_sd_disable();
+#endif
+    }
+    return err_code;
+}
+
+#ifdef BLE_STACK_SUPPORT_REQD
+uint32_t softdevice_ble_evt_handler_set(ble_evt_handler_t ble_evt_handler)
+{
+    VERIFY_PARAM_NOT_NULL(ble_evt_handler);
+
+    m_ble_evt_handler = ble_evt_handler;
+
+    return NRF_SUCCESS;
+}
+#endif
+
+
+#ifdef ANT_STACK_SUPPORT_REQD
+uint32_t softdevice_ant_evt_handler_set(ant_evt_handler_t ant_evt_handler)
+{
+    VERIFY_PARAM_NOT_NULL(ant_evt_handler);
+
+    m_ant_evt_handler = ant_evt_handler;
+
+    return NRF_SUCCESS;
+}
+#endif
+
+
+uint32_t softdevice_sys_evt_handler_set(sys_evt_handler_t sys_evt_handler)
+{
+    VERIFY_PARAM_NOT_NULL(sys_evt_handler);
+
+    m_sys_evt_handler = sys_evt_handler;
+
+    return NRF_SUCCESS;
+}
+
+
+/**@brief   Function for handling the Application's BLE Stack events interrupt.
+ *
+ * @details This function is called whenever an event is ready to be pulled.
+ */
+void SOFTDEVICE_EVT_IRQHandler(void)
+{
+    if (m_evt_schedule_func != NULL)
+    {
+        uint32_t err_code = m_evt_schedule_func();
+        APP_ERROR_CHECK(err_code);
+    }
+    else
+    {
+        intern_softdevice_events_execute();
+    }
+}
+
+void softdevice_handler_suspend()
+{
+#ifdef SOFTDEVICE_PRESENT
+    ret_code_t err_code = sd_nvic_DisableIRQ((IRQn_Type)SOFTDEVICE_EVT_IRQ);
+    APP_ERROR_CHECK(err_code);
+#else
+    NVIC_DisableIRQ(SOFTDEVICE_EVT_IRQ);
+#endif
+    m_suspended = true;
+    return;
+}
+
+void softdevice_handler_resume()
+{
+    if (!m_suspended) return;
+    m_suspended = false;
+
+#ifdef SOFTDEVICE_PRESENT
+    ret_code_t err_code;
+
+    // Force calling ISR again to make sure that events not pulled previously
+    // has been processed.
+    err_code = sd_nvic_SetPendingIRQ((IRQn_Type)SOFTDEVICE_EVT_IRQ);
+    APP_ERROR_CHECK(err_code);
+    err_code = sd_nvic_EnableIRQ((IRQn_Type)SOFTDEVICE_EVT_IRQ);
+    APP_ERROR_CHECK(err_code);
+#else
+    NVIC_SetPendingIRQ((IRQn_Type)SOFTDEVICE_EVT_IRQ);
+    NVIC_EnableIRQ(SOFTDEVICE_EVT_IRQ);
+#endif
+
+    return;
+}
+
+bool softdevice_handler_is_suspended()
+{
+    return m_suspended;
+}
+
+#if defined(BLE_STACK_SUPPORT_REQD)
+uint32_t softdevice_enable_get_default_config(uint8_t central_links_count,
+                                              uint8_t periph_links_count,
+                                              ble_enable_params_t * p_ble_enable_params)
+{
+    memset(p_ble_enable_params, 0, sizeof(ble_enable_params_t));
+    p_ble_enable_params->common_enable_params.vs_uuid_count   = 1;
+    p_ble_enable_params->gatts_enable_params.attr_tab_size    = SOFTDEVICE_GATTS_ATTR_TAB_SIZE;
+    p_ble_enable_params->gatts_enable_params.service_changed  = SOFTDEVICE_GATTS_SRV_CHANGED;
+    p_ble_enable_params->gap_enable_params.periph_conn_count  = periph_links_count;
+    p_ble_enable_params->gap_enable_params.central_conn_count = central_links_count;
+    if (p_ble_enable_params->gap_enable_params.central_conn_count != 0)
+    {
+        p_ble_enable_params->gap_enable_params.central_sec_count  = SOFTDEVICE_CENTRAL_SEC_COUNT;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+static inline uint32_t ram_total_size_get(void)
+{
+#ifdef NRF51
+    uint32_t size_ram_blocks = (uint32_t)NRF_FICR->SIZERAMBLOCKS;
+    uint32_t total_ram_size = size_ram_blocks;
+    total_ram_size = total_ram_size * (NRF_FICR->NUMRAMBLOCK);
+    return total_ram_size;
+#elif (defined (NRF52) || defined(NRF52840_XXAA))
+    return RAM_TOTAL_SIZE;
+#endif /* NRF51 */
+}
+
+
+/*lint --e{528} -save suppress 528: symbol not referenced */
+/**@brief   Function for finding the end address of the RAM.
+ *
+ * @retval  ram_end_address  Address of the end of the RAM.
+ */
+static inline uint32_t ram_end_address_get(void)
+{
+    uint32_t ram_end_address = (uint32_t)RAM_START_ADDRESS;
+    ram_end_address += ram_total_size_get();
+    return ram_end_address;
+}
+/*lint -restore*/
+
+/*lint --e{10} --e{27} --e{40} --e{529} -save */
+uint32_t softdevice_enable(ble_enable_params_t * p_ble_enable_params)
+{
+#if (defined(S130) || defined(S132) || defined(S332) || defined(S140))
+    uint32_t err_code;
+    uint32_t app_ram_base;
+
+#if defined ( __CC_ARM )
+    extern uint32_t Image$$RW_IRAM1$$Base;
+    const volatile uint32_t ram_start = (uint32_t) &Image$$RW_IRAM1$$Base;
+#elif defined ( __ICCARM__ )
+    extern uint32_t __ICFEDIT_region_RAM_start__;
+    volatile uint32_t ram_start = (uint32_t) &__ICFEDIT_region_RAM_start__;
+#elif defined   ( __GNUC__ )
+    extern uint32_t __data_start__;
+    volatile uint32_t ram_start = (uint32_t) &__data_start__;
+#endif
+
+    app_ram_base = ram_start;
+    NRF_LOG_DEBUG("sd_ble_enable: RAM start at 0x%x\r\n",
+                    app_ram_base);
+    err_code = sd_ble_enable(p_ble_enable_params, &app_ram_base);
+
+    if (app_ram_base != ram_start)
+    {
+        NRF_LOG_WARNING("sd_ble_enable: RAM start should be adjusted to 0x%x\r\n",
+                app_ram_base);
+        NRF_LOG_WARNING("RAM size should be adjusted to 0x%x \r\n",
+                ram_end_address_get() - app_ram_base);
+    }
+    else if (err_code != NRF_SUCCESS)
+    {
+        NRF_LOG_ERROR("sd_ble_enable: error 0x%x\r\n", err_code);
+    }
+    return err_code;
+#else
+    return NRF_SUCCESS;
+#endif   //defined(S130) || defined(S132) || defined(S332) || defined(S140)
+}
+/*lint -restore*/
+
+#endif //BLE_STACK_SUPPORT_REQD

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/softdevice_handler.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,262 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/** @file
+ *
+ * @defgroup softdevice_handler SoftDevice Event Handler
+ * @{
+ * @ingroup  app_common
+ * @brief    API for initializing and disabling the SoftDevice
+ *
+ * @details  This API contains the functions and defines exposed by the @ref lib_softdevice_handler.
+ *           For more information on the library and how the application should use it, please refer
+ *           @ref lib_softdevice_handler.
+ *
+ * @note     Use the USE_SCHEDULER parameter of the SOFTDEVICE_HANDLER_INIT() macro to select if
+ *           the @ref app_scheduler is to be used or not.
+ *
+ * @note     Even if the scheduler is not used, softdevice_handler.h will include app_scheduler.h.
+ *           So when compiling, app_scheduler.h must be available in one of the compiler include
+ *           paths.
+ */
+
+#ifndef SOFTDEVICE_HANDLER_H__
+#define SOFTDEVICE_HANDLER_H__
+
+#include <stdlib.h>
+#include "nordic_common.h"
+#include "nrf_sdm.h"
+#include "app_error.h"
+#include "app_util.h"
+#include "ble_stack_handler_types.h"
+#include "ant_stack_handler_types.h"
+#if defined(BLE_STACK_SUPPORT_REQD)
+    #include "headers/ble.h"
+#endif
+#include "app_ram_base.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#define SOFTDEVICE_SCHED_EVT_SIZE       0                                                 /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). For SoftDevice events, this size is 0, since the events are being pulled in the event handler. */
+#define SYS_EVT_MSG_BUF_SIZE            sizeof(uint32_t)                                  /**< Size of System (SOC) event message buffer. */
+
+#if  defined(BLE_GATT_MTU_SIZE_DEFAULT) && !defined(GATT_MTU_SIZE_DEFAULT)
+#define GATT_MTU_SIZE_DEFAULT BLE_GATT_MTU_SIZE_DEFAULT
+#endif
+
+/** @brief Macro for checking the RAM requirement of the SoftDevice.  */
+#define CHECK_RAM_START_ADDR(C_LINK_CNT, P_LINK_CNT)
+
+
+/**@brief     Function for checking the RAM requirement of the SoftDevice.
+ *
+ * @details   Call this function to check if the project settings have the correct RAM start address in respect to what the SoftDevice requires.
+ *
+ * @note      This function is called using the CHECK_RAM_START_ADDR_INTERN macro and should not be called directly.
+ */
+uint32_t sd_check_ram_start(uint32_t sd_req_ram_start);
+
+/**@brief Type of function for passing events from the stack handler module to the scheduler. */
+typedef uint32_t (*softdevice_evt_schedule_func_t) (void);
+
+/**@brief Application System (SOC) event handler type. */
+typedef void (*sys_evt_handler_t) (uint32_t evt_id);
+
+
+/**@brief     Macro for initializing the stack event handler.
+ *
+ * @details   It will handle dimensioning and allocation of the memory buffer required for reading
+ *            events from the stack, making sure the buffer is correctly aligned. It will also
+ *            connect the stack event handler to the scheduler/RTOS (if specified).
+ *
+ * @param[in] CLOCK_SOURCE     Low frequency clock source and accuracy (type nrf_clock_lf_cfg_t_t,
+ *                             see sd_softdevice_enable() for details).
+ * @param[in] EVT_HANDLER      scheduler/RTOS event handler function.
+ *
+ * @note      Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ *            several times as long as it is from the same location, that is to do a
+ *            reinitialization).
+ */
+/*lint -emacro(506, SOFTDEVICE_HANDLER_INIT) */ /* Suppress "Constant value Boolean */
+#define SOFTDEVICE_HANDLER_INIT(CLOCK_SOURCE,                                                      \
+                                EVT_HANDLER)                                                       \
+    do                                                                                             \
+    {                                                                                              \
+        static uint32_t BLE_EVT_BUFFER[CEIL_DIV(BLE_STACK_EVT_MSG_BUF_SIZE, sizeof(uint32_t))];    \
+        uint32_t ERR_CODE;                                                                         \
+        ERR_CODE = softdevice_handler_init((CLOCK_SOURCE),                                         \
+                                           BLE_EVT_BUFFER,                                         \
+                                           sizeof(BLE_EVT_BUFFER),                                 \
+                                           EVT_HANDLER);                                           \
+        APP_ERROR_CHECK(ERR_CODE);                                                                 \
+    } while (0)
+
+/**
+ * @brief Function for retrieving the information about SD state
+ *
+ * The information about current state of softdevice.
+ * @retval false SD is not initialized and SD commands should not be called.
+ * @retval true  SD is already initialized
+ */
+bool softdevice_handler_is_enabled(void);
+
+/**@brief      Function for initializing the stack handler module.
+ *
+ * @details    Enables the SoftDevice and the stack event interrupt handler.
+ *
+ * @note       This function must be called before calling any function in the SoftDevice API.
+ *
+ * @note       Normally initialization should be done using the SOFTDEVICE_HANDLER_INIT() macro,
+ *             as that will both allocate the event buffer, and also align the buffer correctly.
+ *
+ * @param[in]  p_clock_lf_cfg      Low frequency clock source to be used by the SoftDevice.
+ * @param[in]  p_ble_evt_buffer    Buffer for holding one BLE stack event. Since heap is not being
+ *                                 used, this buffer must be provided by the application. The
+ *                                 buffer must be large enough to hold the biggest stack event the
+ *                                 application is supposed to handle. The buffer must be aligned to
+ *                                 a 4 byte boundary. This parameter is unused if BLE stack support
+ *                                 is not required.
+ * @param[in]  ble_evt_buffer_size Size of SoftDevice BLE event buffer. This parameter is unused if
+ *                                 BLE stack support is not required.
+ * @param[in]  evt_schedule_func   Function for passing events to the scheduler. Point to
+ *                                 ble_ant_stack_evt_schedule() to connect to the scheduler.
+ *                                 Set to NULL to make the stack handler module call the event
+ *                                 handler directly from the stack event interrupt handler.
+ *
+ * @retval     NRF_SUCCESS               Successful initialization.
+ * @retval     NRF_ERROR_INVALID_PARAM   Invalid parameter (buffer not aligned to a 4 byte
+ *                                       boundary) or NULL.
+ */
+uint32_t softdevice_handler_init(nrf_clock_lf_cfg_t *              p_clock_lf_cfg,
+                                 void *                            p_ble_evt_buffer,
+                                 uint16_t                          ble_evt_buffer_size,
+                                 softdevice_evt_schedule_func_t    evt_schedule_func);
+
+
+/**@brief     Function for disabling the SoftDevice.
+ *
+ * @details   This function will disable the SoftDevice. It will also update the internal state
+ *            of this module.
+ */
+uint32_t softdevice_handler_sd_disable(void);
+
+/**@brief     Function for suspending the event handler.
+ *
+ * @details   When event handler is disabled, no new events are pulled from SoftDevice.
+ *            Application can suspend pulling incoming events when its event queue is full.
+ */
+void softdevice_handler_suspend(void);
+
+/**@brief     Function for re-enabling the event handler after suspending.
+ */
+void softdevice_handler_resume(void);
+
+/**@brief Function for retrieving the information about the event handler state
+ *
+ * @retval false Event handler is active.
+ * @retval true  Event handler is suspended and events from SD will not be pulled.
+ */
+bool softdevice_handler_is_suspended(void);
+
+
+/**@brief     Function for registering for System (SOC) events.
+ *
+ * @details   The application should use this function to register for receiving System (SOC)
+ *            events from the SoftDevice. If the application does not call this function, then any
+ *            System (SOC) events that may be generated by the SoftDevice will NOT be fetched. Once
+ *            the application has registered for the events, it is not possible to  possible to
+ *            cancel the registration. However, it is possible to register a different function for
+ *            handling the events at any point of time.
+ *
+ * @param[in] sys_evt_handler Function to be called for each received System (SOC) event.
+ *
+ * @retval    NRF_SUCCESS     Successful registration.
+ * @retval    NRF_ERROR_NULL  Null pointer provided as input.
+ */
+uint32_t softdevice_sys_evt_handler_set(sys_evt_handler_t sys_evt_handler);
+
+#if defined(BLE_STACK_SUPPORT_REQD)
+/**@brief     Function for fetching the default enable parameters for the SoftDevice.
+ *
+ * @details   The default enable parameters will work for most projects in the SDK.
+ *            They are not optimized with regards to RAM use. This function is meant as a way to abstract the
+ *            details of p_ble_enable_params needed by @ref softdevice_enable. You might want to tweak
+ *            the struct returned by this function or fill in the entire ble_enable_params_t
+ *            instead of fetching it from this function.
+ *
+ * @param[in]  central_links_count Number of central links used by the application.
+ * @param[in]  periph_links_count Number of peripheral links used by the application.
+ * @param[out] p_ble_enable_params Default ble_enable_params_t to be used by @ref softdevice_enable.
+ *
+ * @retval    NRF_SUCCESS     If the operation was successful.
+ */
+uint32_t softdevice_enable_get_default_config(uint8_t central_links_count,
+                                              uint8_t periph_links_count,
+                                              ble_enable_params_t * p_ble_enable_params);
+
+/**@brief     Function for enabling the SoftDevice.
+ *
+ * @details   This function calls the @ref sd_ble_enable SVC call. It has been abstracted to give
+ *            feedback on the app_ram_base. If the app_ram_base is too low, this function will
+ *            return an error. Using a app_ram_base that is too high will not fail, but will
+ *            result in RAM that is never used. If the DEBUG macro is enabled, this
+ *            function will provide the correct app_ram_base as mandated by the SoftDevice.
+ *            This is useful to tweak the RAM use of your application.
+ *
+ * @param[in]  p_ble_enable_params Parameters for configuring links and bandwidths.
+ *
+ * @retval    NRF_SUCCESS     If the operation was successful.
+ */
+uint32_t softdevice_enable(ble_enable_params_t * p_ble_enable_params);
+#endif //BLE_STACK_SUPPORT_REQD
+// Functions for connecting the Stack Event Handler to the scheduler:
+/**@cond NO_DOXYGEN */
+void intern_softdevice_events_execute(void);
+
+
+/**@endcond */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // SOFTDEVICE_HANDLER_H__
+
+/** @} */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/softdevice_handler_appsh.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,52 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "softdevice_handler_appsh.h"
+#include "app_scheduler.h"
+#include <string.h>
+
+void softdevice_evt_get(void * p_event_data, uint16_t event_size)
+{
+    APP_ERROR_CHECK_BOOL(event_size == 0);
+    intern_softdevice_events_execute();
+}
+
+uint32_t softdevice_evt_schedule(void)
+{
+    return app_sched_event_put(NULL, 0, softdevice_evt_get);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/softdevice_handler_appsh.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,59 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef SOFTDEVICE_HANDLER_APPSH_H
+#define SOFTDEVICE_HANDLER_APPSH_H
+
+#include "softdevice_handler.h"
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SOFTDEVICE_HANDLER_APPSH_INIT(CLOCK_SOURCE,USE_SCHEDULER) \
+    SOFTDEVICE_HANDLER_INIT(CLOCK_SOURCE,(USE_SCHEDULER) ? softdevice_evt_schedule : NULL)
+
+uint32_t softdevice_evt_schedule(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //SOFTDEVICE_HANDLER_APPSH_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/serial_api.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,723 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "serial_api.h"
+
+#if DEVICE_SERIAL
+
+#include <string.h>
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "nrf_uart.h"
+#include "nrf_drv_common.h"
+#include "app_util_platform.h"
+#include "nrf_gpio.h"
+
+#define UART_INSTANCE_COUNT 1
+#define UART_INSTANCE       NRF_UART0
+#define UART_IRQn           UART0_IRQn
+#define UART_IRQ_HANDLER    UART0_IRQHandler
+#define UART_INSTANCE_ID    0
+#define UART_CB uart_cb[UART_INSTANCE_ID]
+
+#define UART_DEFAULT_BAUDRATE   UART_DEFAULT_CONFIG_BAUDRATE
+#define UART_DEFAULT_PARITY     UART_DEFAULT_CONFIG_PARITY
+
+// expected the macro from mbed configuration system
+#ifndef MBED_CONF_NORDIC_UART_HWFC
+    #define MBED_CONF_NORDIC_UART_HWFC 1
+    #warning None of UART flow control configuration (expected macro MBED_CONF_NORDIC_UART_HWFC). The RTSCTS flow control is used by default .
+#endif
+
+#if MBED_CONF_NORDIC_UART_HWFC == 1
+    #define UART_DEFAULT_HWFC       UART_DEFAULT_CONFIG_HWFC
+#else
+    #define UART_DEFAULT_HWFC  NRF_UART_HWFC_DISABLED
+#endif
+
+#define UART_DEFAULT_CTS        CTS_PIN_NUMBER
+#define UART_DEFAULT_RTS        RTS_PIN_NUMBER
+
+#ifdef NRF51
+    #define NRFx_MBED_UART_IRQ_PRIORITY  APP_IRQ_PRIORITY_LOW
+#elif defined(NRF52) || defined(NRF52840_XXAA)
+    #define NRFx_MBED_UART_IRQ_PRIORITY  APP_IRQ_PRIORITY_LOWEST
+#endif
+
+// Required by "retarget.cpp".
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+typedef struct
+{
+    bool initialized;
+    uint32_t irq_context;
+    uart_irq_handler irq_handler;
+
+    uint32_t pselrxd;
+    uint32_t pseltxd;
+    uint32_t pselcts;
+    uint32_t pselrts;
+    nrf_uart_hwfc_t hwfc;
+    nrf_uart_parity_t parity;
+    nrf_uart_baudrate_t baudrate;
+
+#if DEVICE_SERIAL_ASYNCH
+    bool volatile rx_active;
+    uint8_t            *rx_buffer;
+    size_t rx_length;
+    size_t rx_pos;
+    void (*rx_asynch_handler)();
+    uint8_t char_match;
+
+    bool volatile tx_active;
+    const uint8_t      *tx_buffer;
+    size_t tx_length;
+    size_t tx_pos;
+    void (*tx_asynch_handler)();
+
+    uint32_t events_wanted;
+    uint32_t events_occured;
+
+#define UART_IRQ_TX 1
+#define UART_IRQ_RX 2
+    uint8_t irq_enabled;
+#endif // DEVICE_SERIAL_ASYNCH
+} uart_ctlblock_t;
+
+static uart_ctlblock_t uart_cb[UART_INSTANCE_COUNT];
+
+static void internal_set_hwfc(FlowControl type,
+                             PinName rxflow, PinName txflow);
+
+
+#if DEVICE_SERIAL_ASYNCH
+static void end_asynch_rx(void)
+{
+    // If RX interrupt is activated for synchronous operations,
+    // don't disable it, just stop handling it here.
+    if (!(UART_CB.irq_enabled & UART_IRQ_RX))
+    {
+        nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY);
+    }
+    UART_CB.rx_active = false;
+}
+static void end_asynch_tx(void)
+{
+    // If TX interrupt is activated for synchronous operations,
+    // don't disable it, just stop handling it here.
+    if (!(UART_CB.irq_enabled & UART_IRQ_TX))
+    {
+        nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY);
+    }
+    UART_CB.tx_active = false;
+}
+#endif // DEVICE_SERIAL_ASYNCH
+
+void UART_IRQ_HANDLER(void)
+{
+    if (nrf_uart_int_enable_check(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY) &&
+        nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_RXDRDY))
+    {
+
+#if DEVICE_SERIAL_ASYNCH
+        if (UART_CB.rx_active)
+        {
+            nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_RXDRDY);
+
+            uint8_t rx_data = nrf_uart_rxd_get(UART_INSTANCE);
+            UART_CB.rx_buffer[UART_CB.rx_pos] = rx_data;
+
+            bool end_rx = false;
+            // If character matching should be performed, check if the current
+            // data matches the given one.
+            if (UART_CB.char_match != SERIAL_RESERVED_CHAR_MATCH &&
+                rx_data == UART_CB.char_match)
+            {
+                // If it does, report the match and abort further receiving.
+                UART_CB.events_occured |= SERIAL_EVENT_RX_CHARACTER_MATCH;
+                if (UART_CB.events_wanted & SERIAL_EVENT_RX_CHARACTER_MATCH)
+                {
+                    end_rx = true;
+                }
+            }
+            if (++UART_CB.rx_pos >= UART_CB.rx_length)
+            {
+                UART_CB.events_occured |= SERIAL_EVENT_RX_COMPLETE;
+                end_rx = true;
+            }
+            if (end_rx)
+            {
+                end_asynch_rx();
+
+                if (UART_CB.rx_asynch_handler)
+                {
+                    // Use local variable to make it possible to start a next
+                    // transfer from callback routine.
+                    void (*handler)() = UART_CB.rx_asynch_handler;
+                    UART_CB.rx_asynch_handler = NULL;
+                    handler();
+                }
+            }
+        }
+        else
+#endif
+
+        if (UART_CB.irq_handler)
+        {
+            UART_CB.irq_handler(UART_CB.irq_context, RxIrq);
+        }
+    }
+
+    if (nrf_uart_int_enable_check(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY) &&
+        nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_TXDRDY))
+    {
+
+#if DEVICE_SERIAL_ASYNCH
+        if (UART_CB.tx_active)
+        {
+            if (++UART_CB.tx_pos <= UART_CB.tx_length)
+            {
+                // When there is still something to send, clear the TXDRDY event
+                // and put next byte to transmitter.
+                nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_TXDRDY);
+                nrf_uart_txd_set(UART_INSTANCE,
+                    UART_CB.tx_buffer[UART_CB.tx_pos]);
+            }
+            else
+            {
+                // When the TXDRDY event is set after the last byte to be sent
+                // has been passed to the transmitter, the job is done and TX
+                // complete can be indicated.
+                // Don't clear the TXDRDY event, it needs to remain set for the
+                // 'serial_writable' function to work properly.
+                end_asynch_tx();
+
+                UART_CB.events_occured |= SERIAL_EVENT_TX_COMPLETE;
+                if (UART_CB.tx_asynch_handler)
+                {
+                    // Use local variable to make it possible to start a next
+                    // transfer from callback routine.
+                    void (*handler)() = UART_CB.tx_asynch_handler;
+                    UART_CB.tx_asynch_handler = NULL;
+                    handler();
+                }
+            }
+        }
+        else
+#endif
+
+        if (UART_CB.irq_handler)
+        {
+            UART_CB.irq_handler(UART_CB.irq_context, TxIrq);
+        }
+    }
+
+#if DEVICE_SERIAL_ASYNCH
+    if (nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_ERROR))
+    {
+        nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_ERROR);
+
+        uint8_t errorsrc = nrf_uart_errorsrc_get_and_clear(UART_INSTANCE);
+        if (UART_CB.rx_asynch_handler)
+        {
+            UART_CB.events_occured |= SERIAL_EVENT_ERROR;
+            if (errorsrc & NRF_UART_ERROR_PARITY_MASK)
+            {
+                UART_CB.events_occured |= SERIAL_EVENT_RX_PARITY_ERROR;
+            }
+            if (errorsrc & NRF_UART_ERROR_FRAMING_MASK)
+            {
+                UART_CB.events_occured |= SERIAL_EVENT_RX_FRAMING_ERROR;
+            }
+            if (errorsrc & NRF_UART_ERROR_OVERRUN_MASK)
+            {
+                UART_CB.events_occured |= SERIAL_EVENT_RX_OVERRUN_ERROR;
+            }
+            UART_CB.rx_asynch_handler();
+        }
+    }
+#endif // DEVICE_SERIAL_ASYNCH
+}
+
+
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+
+    NVIC_SetVector(UART0_IRQn, (uint32_t) UART0_IRQHandler);
+
+    
+    UART_CB.pseltxd =
+        (tx == NC) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)tx;
+    UART_CB.pselrxd =
+        (rx == NC) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)rx;
+    if (UART_CB.pseltxd != NRF_UART_PSEL_DISCONNECTED)
+    {
+        nrf_gpio_pin_set(UART_CB.pseltxd);
+        nrf_gpio_cfg_output(UART_CB.pseltxd);
+    }
+    if (UART_CB.pselrxd != NRF_UART_PSEL_DISCONNECTED)
+    {
+        nrf_gpio_cfg_input(UART_CB.pselrxd, NRF_GPIO_PIN_NOPULL);
+    }
+
+    if (UART_CB.initialized)
+    {
+        // For already initialized peripheral it is sufficient to reconfigure
+        // RX/TX pins only.
+
+        // Ensure that there is no unfinished TX transfer.
+        while (!serial_writable(obj))
+        {
+        }
+        // UART pins can be configured only when the peripheral is disabled.
+        nrf_uart_disable(UART_INSTANCE);
+        nrf_uart_txrx_pins_set(UART_INSTANCE, UART_CB.pseltxd, UART_CB.pselrxd);
+        nrf_uart_enable(UART_INSTANCE);
+    }
+    else
+    {
+        UART_CB.baudrate = (nrf_uart_baudrate_t)UART_DEFAULT_BAUDRATE;
+        UART_CB.parity   = (nrf_uart_parity_t)UART_DEFAULT_PARITY;
+        UART_CB.hwfc     = (nrf_uart_hwfc_t)UART_DEFAULT_HWFC;
+        UART_CB.pselcts  = UART_DEFAULT_CTS;
+        UART_CB.pselrts  = UART_DEFAULT_RTS;
+
+        nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_RXDRDY);
+        nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_TXDRDY);
+        nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_STARTRX);
+        nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_STARTTX);
+
+        nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY |
+                             NRF_UART_INT_MASK_TXDRDY);
+#if DEVICE_SERIAL_ASYNCH
+        nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_ERROR);
+#endif
+        nrf_drv_common_irq_enable(UART_IRQn, NRFx_MBED_UART_IRQ_PRIORITY);
+
+        // TX interrupt needs to be signaled when transmitter buffer is empty,
+        // so a dummy transmission is needed to get the TXDRDY event initially
+        // set.
+        nrf_uart_configure(UART_INSTANCE,
+            NRF_UART_PARITY_EXCLUDED, NRF_UART_HWFC_DISABLED);
+        // Use maximum baud rate, so this dummy transmission takes as little
+        // time as possible.
+        nrf_uart_baudrate_set(UART_INSTANCE, NRF_UART_BAUDRATE_1000000);
+        // Perform it with disconnected TX pin, so nothing actually comes out
+        // of the device.
+        nrf_uart_txrx_pins_disconnect(UART_INSTANCE);
+        nrf_uart_hwfc_pins_disconnect(UART_INSTANCE);
+        nrf_uart_enable(UART_INSTANCE);
+        nrf_uart_txd_set(UART_INSTANCE, 0);
+
+        while (!nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_TXDRDY))
+        {
+        }
+        nrf_uart_disable(UART_INSTANCE);
+
+        // Now everything is prepared to set the default configuration and
+        // connect the peripheral to actual pins.
+        nrf_uart_txrx_pins_set(UART_INSTANCE, UART_CB.pseltxd, UART_CB.pselrxd);
+        nrf_uart_baudrate_set(UART_INSTANCE, UART_CB.baudrate);
+        nrf_uart_configure(UART_INSTANCE, UART_CB.parity, UART_CB.hwfc);
+        if (UART_CB.hwfc == NRF_UART_HWFC_ENABLED)
+        {
+            internal_set_hwfc(FlowControlRTSCTS,
+                (PinName) UART_CB.pselrts, (PinName) UART_CB.pselcts);
+        }
+        
+        nrf_uart_enable(UART_INSTANCE);
+
+        UART_CB.initialized = true;
+    }
+
+    if (tx == STDIO_UART_TX && rx == STDIO_UART_RX)
+    {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+    else
+    {
+        stdio_uart_inited = 0;
+    }
+}
+
+void serial_free(serial_t *obj)
+{
+    (void)obj;
+
+    if (UART_CB.initialized)
+    {
+        nrf_uart_disable(UART_INSTANCE);
+        nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY |
+                                            NRF_UART_INT_MASK_TXDRDY |
+                                            NRF_UART_INT_MASK_ERROR);
+        nrf_drv_common_irq_disable(UART_IRQn);
+        UART_CB.initialized = false;
+
+        // There is only one UART instance, thus at this point the stdio UART
+        // can no longer be initialized.
+        stdio_uart_inited = 0;
+    }
+}
+
+void serial_baud(serial_t *obj, int baudrate)
+{
+    // nrf_uart_baudrate_set() is not used here (registers are accessed
+    // directly) to make it possible to set special baud rates like 56000
+    // or 31250.
+
+    static uint32_t const acceptedSpeeds[][2] = {
+        { 1200,    UART_BAUDRATE_BAUDRATE_Baud1200   },
+        { 2400,    UART_BAUDRATE_BAUDRATE_Baud2400   },
+        { 4800,    UART_BAUDRATE_BAUDRATE_Baud4800   },
+        { 9600,    UART_BAUDRATE_BAUDRATE_Baud9600   },
+        { 14400,   UART_BAUDRATE_BAUDRATE_Baud14400  },
+        { 19200,   UART_BAUDRATE_BAUDRATE_Baud19200  },
+        { 28800,   UART_BAUDRATE_BAUDRATE_Baud28800  },
+        { 31250,   (0x00800000UL) /* 31250 baud */   },
+        { 38400,   UART_BAUDRATE_BAUDRATE_Baud38400  },
+        { 56000,   (0x00E51000UL) /* 56000 baud */   },
+        { 57600,   UART_BAUDRATE_BAUDRATE_Baud57600  },
+        { 76800,   UART_BAUDRATE_BAUDRATE_Baud76800  },
+        { 115200,  UART_BAUDRATE_BAUDRATE_Baud115200 },
+        { 230400,  UART_BAUDRATE_BAUDRATE_Baud230400 },
+        { 250000,  UART_BAUDRATE_BAUDRATE_Baud250000 },
+        { 460800,  UART_BAUDRATE_BAUDRATE_Baud460800 },
+        { 921600,  UART_BAUDRATE_BAUDRATE_Baud921600 },
+        { 1000000, UART_BAUDRATE_BAUDRATE_Baud1M     }
+    };
+
+    if (baudrate <= 1200)
+    {
+        UART_INSTANCE->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud1200;
+        return;
+    }
+
+    int const item_cnt = sizeof(acceptedSpeeds)/sizeof(acceptedSpeeds[0]);
+
+    for (int i = 1; i < item_cnt; i++)
+    {
+        if ((uint32_t)baudrate < acceptedSpeeds[i][0])
+        {
+            UART_INSTANCE->BAUDRATE = acceptedSpeeds[i - 1][1];
+            return;
+        }
+    }
+
+    UART_INSTANCE->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud1M;
+}
+
+void serial_format(serial_t *obj,
+                   int data_bits, SerialParity parity, int stop_bits)
+{
+    (void)obj;
+
+    if (data_bits != 8)
+    {
+        error("UART supports only 8 data bits.\r\n");
+    }
+    if (stop_bits != 1)
+    {
+        error("UART supports only 1 stop bits.\r\n");
+    }
+    if (parity == ParityNone)
+    {
+        UART_CB.parity = NRF_UART_PARITY_EXCLUDED;
+    }
+    else if (parity == ParityEven)
+    {
+        UART_CB.parity = NRF_UART_PARITY_INCLUDED;
+    }
+    else
+    {
+        error("UART supports only even parity.\r\n");
+    }
+
+    // Reconfigure UART peripheral.
+    nrf_uart_configure(UART_INSTANCE, UART_CB.parity, UART_CB.hwfc);
+}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+    (void)obj;
+    UART_CB.irq_handler = handler;
+    UART_CB.irq_context = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+    (void)obj;
+    if (enable)
+    {
+        switch (irq)
+        {
+            case RxIrq:
+#if DEVICE_SERIAL_ASYNCH
+                UART_CB.irq_enabled |= UART_IRQ_RX;
+#endif
+                nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY);
+                break;
+
+            case TxIrq:
+#if DEVICE_SERIAL_ASYNCH
+                UART_CB.irq_enabled |= UART_IRQ_TX;
+#endif
+                nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY);
+                break;
+        }
+    }
+    else
+    {
+        switch (irq)
+        {
+            case RxIrq:
+#if DEVICE_SERIAL_ASYNCH
+                UART_CB.irq_enabled &= ~UART_IRQ_RX;
+                if (!UART_CB.rx_active)
+#endif
+                {
+                    nrf_uart_int_disable(UART_INSTANCE,
+                        NRF_UART_INT_MASK_RXDRDY);
+                }
+                break;
+
+            case TxIrq:
+#if DEVICE_SERIAL_ASYNCH
+                UART_CB.irq_enabled &= ~UART_IRQ_TX;
+                if (!UART_CB.tx_active)
+#endif
+                {
+                    nrf_uart_int_disable(UART_INSTANCE,
+                        NRF_UART_INT_MASK_TXDRDY);
+                }
+                break;
+        }
+    }
+}
+
+int serial_getc(serial_t *obj)
+{
+    while (!serial_readable(obj))
+    {
+    }
+
+    nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_RXDRDY);
+    return nrf_uart_rxd_get(UART_INSTANCE);
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+    while (!serial_writable(obj))
+    {
+    }
+
+    nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_TXDRDY);
+    nrf_uart_txd_set(UART_INSTANCE, (uint8_t)c);
+}
+
+int serial_readable(serial_t *obj)
+{
+    (void)obj;
+#if DEVICE_SERIAL_ASYNCH
+    if (UART_CB.rx_active)
+    {
+        return 0;
+    }
+#endif
+    return (nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_RXDRDY));
+}
+
+int serial_writable(serial_t *obj)
+{
+    (void)obj;
+#if DEVICE_SERIAL_ASYNCH
+    if (UART_CB.tx_active)
+    {
+        return 0;
+    }
+#endif
+    return (nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_TXDRDY));
+}
+
+void serial_break_set(serial_t *obj)
+{
+    (void)obj;
+    nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_SUSPEND);
+    nrf_uart_txrx_pins_disconnect(UART_INSTANCE);
+    nrf_gpio_pin_clear(UART_CB.pseltxd);
+}
+
+void serial_break_clear(serial_t *obj)
+{
+    (void)obj;
+    nrf_gpio_pin_set(UART_CB.pseltxd);
+    nrf_uart_txrx_pins_set(UART_INSTANCE, UART_CB.pseltxd, UART_CB.pselrxd);
+    nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_STARTRX);
+    nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_STARTTX);
+}
+
+
+static void internal_set_hwfc(FlowControl type,
+                             PinName rxflow, PinName txflow)
+{
+    UART_CB.pselrts =
+        ((rxflow == NC) || (type == FlowControlCTS)) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)rxflow;
+    UART_CB.pselcts =
+        ((txflow == NC) || (type == FlowControlRTS)) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)txflow;
+
+    if (UART_CB.pselrts != NRF_UART_PSEL_DISCONNECTED)
+    {
+        nrf_gpio_pin_set(UART_CB.pselrts);
+        nrf_gpio_cfg_output(UART_CB.pselrts);
+    }
+    if (UART_CB.pselcts != NRF_UART_PSEL_DISCONNECTED)
+    {
+        nrf_gpio_cfg_input(UART_CB.pselcts, NRF_GPIO_PIN_NOPULL);
+    }
+    
+    UART_CB.hwfc = (nrf_uart_hwfc_t)((type == FlowControlNone)? NRF_UART_HWFC_DISABLED  : UART_DEFAULT_CONFIG_HWFC);
+    
+    nrf_uart_configure(UART_INSTANCE, UART_CB.parity, UART_CB.hwfc);
+    nrf_uart_hwfc_pins_set(UART_INSTANCE, UART_CB.pselrts, UART_CB.pselcts);
+}
+
+void serial_set_flow_control(serial_t *obj, FlowControl type,
+                             PinName rxflow, PinName txflow)
+{
+    (void)obj;
+    
+    nrf_uart_disable(UART_INSTANCE);
+    internal_set_hwfc(type, rxflow, txflow);
+    nrf_uart_enable(UART_INSTANCE);
+}
+
+
+void serial_clear(serial_t *obj)
+{
+    (void)obj;
+}
+
+#if DEVICE_SERIAL_ASYNCH
+
+int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length,
+                     uint8_t tx_width, uint32_t handler, uint32_t event,
+                     DMAUsage hint)
+{
+    (void)obj;
+    (void)tx_width;
+    (void)hint;
+    if (UART_CB.tx_active || !tx_length)
+    {
+        return 0;
+    }
+
+    UART_CB.tx_buffer = tx;
+    UART_CB.tx_length = tx_length;
+    UART_CB.tx_pos    = 0;
+    UART_CB.tx_asynch_handler = (void(*)())handler;
+    UART_CB.events_wanted &= ~SERIAL_EVENT_TX_ALL;
+    UART_CB.events_wanted |= event;
+
+    UART_CB.tx_active = true;
+    nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY);
+
+    return 0;
+}
+
+void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length,
+                      uint8_t rx_width, uint32_t handler, uint32_t event,
+                      uint8_t char_match, DMAUsage hint)
+{
+    (void)obj;
+    (void)rx_width;
+    (void)hint;
+    if (UART_CB.rx_active || !rx_length)
+    {
+        return;
+    }
+
+    UART_CB.rx_buffer = rx;
+    UART_CB.rx_length = rx_length;
+    UART_CB.rx_pos    = 0;
+    UART_CB.rx_asynch_handler = (void(*)())handler;
+    UART_CB.events_wanted &= ~SERIAL_EVENT_RX_ALL;
+    UART_CB.events_wanted |= event;
+    UART_CB.char_match = char_match;
+
+    UART_CB.rx_active = true;
+    nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY);
+}
+
+uint8_t serial_tx_active(serial_t *obj)
+{
+    (void)obj;
+    return UART_CB.tx_active;
+}
+
+uint8_t serial_rx_active(serial_t *obj)
+{
+    (void)obj;
+    return UART_CB.rx_active;
+}
+
+int serial_irq_handler_asynch(serial_t *obj)
+{
+    (void)obj;
+    uint32_t events_to_report = UART_CB.events_wanted & UART_CB.events_occured;
+    UART_CB.events_occured &= (~events_to_report);
+    return events_to_report;
+}
+
+void serial_tx_abort_asynch(serial_t *obj)
+{
+    (void)obj;
+    end_asynch_tx();
+    UART_CB.tx_asynch_handler = NULL;
+}
+
+void serial_rx_abort_asynch(serial_t *obj)
+{
+    (void)obj;
+    end_asynch_rx();
+    UART_CB.rx_asynch_handler = NULL;
+}
+
+#endif // DEVICE_SERIAL_ASYNCH
+
+#endif // DEVICE_SERIAL

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sleep.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,85 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "sleep_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+#include "softdevice_handler.h"
+#include "nrf_soc.h"
+
+// Mask of reserved bits of the register ICSR in the System Control Block peripheral
+// In this case, bits which are equal to 0 are the bits reserved in this register
+#define SCB_ICSR_RESERVED_BITS_MASK     0x9E43F03F
+
+#define FPU_EXCEPTION_MASK 0x0000009F
+
+void hal_sleep(void)
+{
+    // ensure debug is disconnected if semihost is enabled....
+
+    // Trigger an event when an interrupt is pending. This allows to wake up
+    // the processor from disabled interrupts.
+    SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
+
+#if defined(NRF52)  || defined(NRF52840_XXAA)
+    /* Clear exceptions and PendingIRQ from the FPU unit */
+    __set_FPSCR(__get_FPSCR()  & ~(FPU_EXCEPTION_MASK));
+    (void) __get_FPSCR();
+    NVIC_ClearPendingIRQ(FPU_IRQn);
+#endif
+
+    // If the SoftDevice is enabled, its API must be used to go to sleep.
+    if (softdevice_handler_is_enabled())
+    {
+        sd_power_mode_set(NRF_POWER_MODE_LOWPWR);
+        sd_app_evt_wait();
+    }
+    else
+    {
+        NRF_POWER->TASKS_LOWPWR = 1;
+
+        // Note: it is not sufficient to just use WFE here, since the internal
+        // event register may be already set from an event that occurred in the
+        // past (like an SVC call to the SoftDevice) and in such case WFE will
+        // just clear the register and continue execution.
+        // Therefore, the strategy here is to first clear the event register
+        // by using SEV/WFE pair, and then execute WFE again, unless there is
+        // a pending interrupt.
+
+        // Set an event and wake up whatsoever, this will clear the event
+        // register from all previous events set (SVC call included)
+        __SEV();
+        __WFE();
+
+        // Test if there is an interrupt pending (mask reserved regions)
+        if (SCB->ICSR & (SCB_ICSR_RESERVED_BITS_MASK))
+        {
+            // Ok, there is an interrut pending, no need to go to sleep
+            return;
+        }
+        else
+        {
+            // next event will wakeup the CPU
+            // If an interrupt occured between the test of SCB->ICSR and this
+            // instruction, WFE will just not put the CPU to sleep
+            __WFE();
+        }
+    }
+}
+
+void hal_deepsleep(void)
+{
+    hal_sleep();
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/spi_api.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,600 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "spi_api.h"
+
+#if DEVICE_SPI
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "nrf_drv_spi.h"
+#include "nrf_drv_spis.h"
+#include "app_util_platform.h"
+
+#if DEVICE_SPI_ASYNCH
+    #define SPI_IDX(obj)    ((obj)->spi.spi_idx)
+#else
+    #define SPI_IDX(obj)    ((obj)->spi_idx)
+#endif
+#define SPI_INFO(obj)       (&m_spi_info[SPI_IDX(obj)])
+#define MASTER_INST(obj)    (&m_instances[SPI_IDX(obj)].master)
+#define SLAVE_INST(obj)     (&m_instances[SPI_IDX(obj)].slave)
+
+typedef struct
+{
+    bool initialized;
+    bool master;
+    uint8_t sck_pin;
+    uint8_t mosi_pin;
+    uint8_t miso_pin;
+    uint8_t ss_pin;
+    uint8_t spi_mode;
+    nrf_drv_spi_frequency_t frequency;
+    volatile union
+    {
+        bool busy;     // master
+        bool readable; // slave
+    } flag;
+    volatile uint8_t tx_buf;
+    volatile uint8_t rx_buf;
+
+#if DEVICE_SPI_ASYNCH
+    uint32_t handler;
+    uint32_t event;
+#endif
+} spi_info_t;
+static spi_info_t m_spi_info[SPI_COUNT];
+
+typedef struct
+{
+    nrf_drv_spi_t master;
+    nrf_drv_spis_t slave;
+} sdk_driver_instances_t;
+
+void SPI0_TWI0_IRQHandler(void);
+void SPI1_TWI1_IRQHandler(void);
+void SPIM2_SPIS2_SPI2_IRQHandler(void);
+
+static const peripheral_handler_desc_t spi_handler_desc[SPI_COUNT] = {
+#if SPI0_ENABLED
+    {
+        SPI0_IRQ,
+        (uint32_t) SPI0_TWI0_IRQHandler
+    },
+#endif
+#if SPI1_ENABLED
+    {
+        SPI1_IRQ,
+        (uint32_t) SPI1_TWI1_IRQHandler
+    },
+#endif
+#if SPI2_ENABLED
+    {
+        SPI2_IRQ,
+        (uint32_t) SPIM2_SPIS2_SPI2_IRQHandler
+    },
+#endif
+};
+
+
+static sdk_driver_instances_t m_instances[SPI_COUNT] = {
+#if SPI0_ENABLED
+    {
+        NRF_DRV_SPI_INSTANCE(0),
+        NRF_DRV_SPIS_INSTANCE(0)
+    },
+#endif
+#if SPI1_ENABLED
+    {
+        NRF_DRV_SPI_INSTANCE(1),
+        NRF_DRV_SPIS_INSTANCE(1)
+    },
+#endif
+#if SPI2_ENABLED
+    {
+        NRF_DRV_SPI_INSTANCE(2),
+        NRF_DRV_SPIS_INSTANCE(2)
+    },
+#endif
+};
+
+static void master_event_handler(uint8_t spi_idx,
+                                 nrf_drv_spi_evt_t const *p_event)
+{
+    spi_info_t *p_spi_info = &m_spi_info[spi_idx];
+
+    if (p_event->type == NRF_DRV_SPI_EVENT_DONE)
+    {
+        p_spi_info->flag.busy = false;
+        if (p_spi_info->handler)
+        {
+            void (*handler)(void) = (void (*)(void))p_spi_info->handler;
+            p_spi_info->handler = 0;
+            handler();
+        }
+    }
+}
+#define MASTER_EVENT_HANDLER(idx) \
+    static void master_event_handler_##idx(nrf_drv_spi_evt_t const *p_event) { \
+        master_event_handler(SPI##idx##_INSTANCE_INDEX, p_event); \
+    }
+#if SPI0_ENABLED
+    MASTER_EVENT_HANDLER(0)
+#endif
+#if SPI1_ENABLED
+    MASTER_EVENT_HANDLER(1)
+#endif
+#if SPI2_ENABLED
+    MASTER_EVENT_HANDLER(2)
+#endif
+
+static nrf_drv_spi_handler_t const m_master_event_handlers[SPI_COUNT] = {
+#if SPI0_ENABLED
+    master_event_handler_0,
+#endif
+#if SPI1_ENABLED
+    master_event_handler_1,
+#endif
+#if SPI2_ENABLED
+    master_event_handler_2,
+#endif
+};
+
+
+static void slave_event_handler(uint8_t spi_idx,
+                                nrf_drv_spis_event_t event)
+{
+    spi_info_t *p_spi_info = &m_spi_info[spi_idx];
+
+    if (event.evt_type == NRF_DRV_SPIS_XFER_DONE)
+    {
+        // Signal that there is some data received that could be read.
+        p_spi_info->flag.readable = true;
+
+        // And prepare for the next transfer.
+        // Previous data set in 'spi_slave_write' (if any) has been transmitted,
+        // now use the default one, until some new is set by 'spi_slave_write'.
+        p_spi_info->tx_buf = SPIS_DEFAULT_ORC;
+        nrf_drv_spis_buffers_set(&m_instances[spi_idx].slave,
+            (uint8_t const *)&p_spi_info->tx_buf, 1,
+            (uint8_t *)&p_spi_info->rx_buf, 1);
+    }
+}
+#define SLAVE_EVENT_HANDLER(idx) \
+    static void slave_event_handler_##idx(nrf_drv_spis_event_t event) { \
+        slave_event_handler(SPIS##idx##_INSTANCE_INDEX, event); \
+    }
+#if SPIS0_ENABLED
+    SLAVE_EVENT_HANDLER(0)
+#endif
+#if SPIS1_ENABLED
+    SLAVE_EVENT_HANDLER(1)
+#endif
+#if SPIS2_ENABLED
+    SLAVE_EVENT_HANDLER(2)
+#endif
+
+static nrf_drv_spis_event_handler_t const m_slave_event_handlers[SPIS_COUNT] = {
+#if SPIS0_ENABLED
+    slave_event_handler_0,
+#endif
+#if SPIS1_ENABLED
+    slave_event_handler_1,
+#endif
+#if SPIS2_ENABLED
+    slave_event_handler_2,
+#endif
+};
+
+static void prepare_master_config(nrf_drv_spi_config_t *p_config,
+                                  spi_info_t const *p_spi_info)
+{
+    p_config->sck_pin   = p_spi_info->sck_pin;
+    p_config->mosi_pin  = p_spi_info->mosi_pin;
+    p_config->miso_pin  = p_spi_info->miso_pin;
+    p_config->ss_pin    = p_spi_info->ss_pin;
+    p_config->frequency = p_spi_info->frequency;
+    p_config->mode      = (nrf_drv_spi_mode_t)p_spi_info->spi_mode;
+
+    p_config->irq_priority = SPI_DEFAULT_CONFIG_IRQ_PRIORITY;
+    p_config->orc          = 0xFF;
+    p_config->bit_order    = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST;
+}
+
+static void prepare_slave_config(nrf_drv_spis_config_t *p_config,
+                                 spi_info_t const *p_spi_info)
+{
+    p_config->sck_pin   = p_spi_info->sck_pin;
+    p_config->mosi_pin  = p_spi_info->mosi_pin;
+    p_config->miso_pin  = p_spi_info->miso_pin;
+    p_config->csn_pin   = p_spi_info->ss_pin;
+    p_config->mode      = (nrf_drv_spis_mode_t)p_spi_info->spi_mode;
+
+    p_config->irq_priority = SPIS_DEFAULT_CONFIG_IRQ_PRIORITY;
+    p_config->orc          = SPIS_DEFAULT_ORC;
+    p_config->def          = SPIS_DEFAULT_DEF;
+    p_config->bit_order    = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST;
+    p_config->csn_pullup   = NRF_DRV_SPIS_DEFAULT_CSN_PULLUP;
+    p_config->miso_drive   = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE;
+}
+
+void spi_init(spi_t *obj,
+              PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+    int i;
+
+    // This block is only a workaround that allows to create SPI object several
+    // times, what would be otherwise impossible in the current implementation
+    // of mbed driver that does not call spi_free() from SPI destructor.
+    // Once this mbed's imperfection is corrected, this block should be removed.
+    for (i = 0; i < SPI_COUNT; ++i)
+    {
+        spi_info_t *p_spi_info = &m_spi_info[i];
+        
+        if (p_spi_info->initialized &&
+            p_spi_info->mosi_pin == (uint8_t)mosi &&
+            p_spi_info->miso_pin == (uint8_t)miso &&
+            p_spi_info->sck_pin  == (uint8_t)sclk &&
+            p_spi_info->ss_pin   == (uint8_t)ssel)
+        {
+            // Reuse the already allocated SPI instance (instead of allocating
+            // a new one), if it appears to be initialized with exactly the same
+            // pin assignments.
+            SPI_IDX(obj) = i;
+            return;
+        }
+    }
+
+    for (i = 0; i < SPI_COUNT; ++i)
+    {
+        spi_info_t *p_spi_info = &m_spi_info[i];
+        
+        if (!p_spi_info->initialized)
+        {
+            p_spi_info->sck_pin   = (uint8_t)sclk;
+            p_spi_info->mosi_pin  = (mosi != NC) ?
+                (uint8_t)mosi : NRF_DRV_SPI_PIN_NOT_USED;
+            p_spi_info->miso_pin  = (miso != NC) ?
+                (uint8_t)miso : NRF_DRV_SPI_PIN_NOT_USED;
+            p_spi_info->ss_pin    = (ssel != NC) ?
+                (uint8_t)ssel : NRF_DRV_SPI_PIN_NOT_USED;
+            p_spi_info->spi_mode  = (uint8_t)NRF_DRV_SPI_MODE_0;
+            p_spi_info->frequency = NRF_DRV_SPI_FREQ_1M;
+
+            NVIC_SetVector(spi_handler_desc[i].IRQn, spi_handler_desc[i].vector);
+
+            // By default each SPI instance is initialized to work as a master.
+            // Should the slave mode be used, the instance will be reconfigured
+            // appropriately in 'spi_format'.
+            nrf_drv_spi_config_t config;
+            prepare_master_config(&config, p_spi_info);
+
+            nrf_drv_spi_t const *p_spi    = &m_instances[i].master;
+            ret_code_t           ret_code = nrf_drv_spi_init(p_spi,
+                                                             &config, m_master_event_handlers[i]);
+            if (ret_code == NRF_SUCCESS)
+            {
+                p_spi_info->initialized = true;
+                p_spi_info->master      = true;
+                p_spi_info->flag.busy   = false;
+#if DEVICE_SPI_ASYNCH
+                p_spi_info->handler = 0;
+#endif
+                SPI_IDX(obj) = i;
+
+                return;
+            }
+        }
+    }
+
+    // No available peripheral
+    error("No available SPI peripheral\r\n");
+}
+
+void spi_free(spi_t *obj)
+{
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+
+    if (p_spi_info->master)
+    {
+        nrf_drv_spi_uninit(MASTER_INST(obj));
+    }
+    else
+    {
+        nrf_drv_spis_uninit(SLAVE_INST(obj));
+    }
+    p_spi_info->initialized = false;
+}
+
+int spi_busy(spi_t *obj)
+{
+    return (int)(SPI_INFO(obj)->flag.busy);
+}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+    if (bits != 8)
+    {
+        error("Only 8-bits SPI is supported\r\n");
+    }
+    if (mode > 3)
+    {
+        error("SPI format error\r\n");
+    }
+
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+
+    if (slave)
+    {
+        nrf_drv_spis_mode_t spi_modes[4] = {
+            NRF_DRV_SPIS_MODE_0,
+            NRF_DRV_SPIS_MODE_1,
+            NRF_DRV_SPIS_MODE_2,
+            NRF_DRV_SPIS_MODE_3,
+        };
+        nrf_drv_spis_mode_t new_mode = spi_modes[mode];
+
+        // If the peripheral is currently working as a master, the SDK driver
+        // it uses needs to be switched from SPI to SPIS.
+        if (p_spi_info->master)
+        {
+            nrf_drv_spi_uninit(MASTER_INST(obj));
+        }
+        // I the SPI mode has to be changed, the SDK's SPIS driver needs to be
+        // re-initialized (there is no other way to change its configuration).
+        else if (p_spi_info->spi_mode != (uint8_t)new_mode)
+        {
+            nrf_drv_spis_uninit(SLAVE_INST(obj));
+        }
+        else
+        {
+            return;
+        }
+
+        p_spi_info->spi_mode = (uint8_t)new_mode;
+        p_spi_info->master = false;
+        p_spi_info->flag.readable = false;
+
+        // Initialize SDK's SPIS driver with the new configuration.
+        nrf_drv_spis_config_t config;
+        prepare_slave_config(&config, p_spi_info);
+        (void)nrf_drv_spis_init(SLAVE_INST(obj), &config,
+            m_slave_event_handlers[SPI_IDX(obj)]);
+
+        // Prepare the slave for transfer.
+        p_spi_info->tx_buf = SPIS_DEFAULT_ORC;
+        nrf_drv_spis_buffers_set(SLAVE_INST(obj),
+            (uint8_t const *)&p_spi_info->tx_buf, 1,
+            (uint8_t *)&p_spi_info->rx_buf, 1);
+    }
+    else // master
+    {
+        nrf_drv_spi_mode_t spi_modes[4] = {
+            NRF_DRV_SPI_MODE_0,
+            NRF_DRV_SPI_MODE_1,
+            NRF_DRV_SPI_MODE_2,
+            NRF_DRV_SPI_MODE_3,
+        };
+        nrf_drv_spi_mode_t new_mode = spi_modes[mode];
+
+        // If the peripheral is currently working as a slave, the SDK driver
+        // it uses needs to be switched from SPIS to SPI.
+        if (!p_spi_info->master)
+        {
+            nrf_drv_spis_uninit(SLAVE_INST(obj));
+        }
+        // I the SPI mode has to be changed, the SDK's SPI driver needs to be
+        // re-initialized (there is no other way to change its configuration).
+        else if (p_spi_info->spi_mode != (uint8_t)new_mode)
+        {
+            nrf_drv_spi_uninit(MASTER_INST(obj));
+        }
+        else
+        {
+            return;
+        }
+
+        p_spi_info->spi_mode = (uint8_t)new_mode;
+        p_spi_info->master = true;
+        p_spi_info->flag.busy = false;
+
+        // Initialize SDK's SPI driver with the new configuration.
+        nrf_drv_spi_config_t config;
+        prepare_master_config(&config, p_spi_info);
+        (void)nrf_drv_spi_init(MASTER_INST(obj), &config,
+            m_master_event_handlers[SPI_IDX(obj)]);
+    }
+}
+
+static nrf_drv_spi_frequency_t freq_translate(int hz)
+{
+    nrf_drv_spi_frequency_t frequency;
+
+    if (hz<250000)   //125Kbps
+    {
+        frequency = NRF_DRV_SPI_FREQ_125K;
+    }
+    else if (hz<500000)     //250Kbps
+    {
+        frequency = NRF_DRV_SPI_FREQ_250K;
+    }
+    else if (hz<1000000)     //500Kbps
+    {
+        frequency = NRF_DRV_SPI_FREQ_500K;
+    }
+    else if (hz<2000000)     //1Mbps
+    {
+        frequency = NRF_DRV_SPI_FREQ_1M;
+    }
+    else if (hz<4000000)     //2Mbps
+    {
+        frequency = NRF_DRV_SPI_FREQ_2M;
+    }
+    else if (hz<8000000)     //4Mbps
+    {
+        frequency = NRF_DRV_SPI_FREQ_4M;
+    }
+    else     //8Mbps
+    {
+        frequency = NRF_DRV_SPI_FREQ_8M;
+    }
+    return frequency;
+}
+
+void spi_frequency(spi_t *obj, int hz)
+{
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+    nrf_drv_spi_frequency_t new_frequency = freq_translate(hz);
+
+    if (p_spi_info->master)
+    {
+        if (p_spi_info->frequency != new_frequency)
+        {
+            p_spi_info->frequency = new_frequency;
+
+            nrf_drv_spi_config_t config;
+            prepare_master_config(&config, p_spi_info);
+
+            nrf_drv_spi_t const *p_spi = MASTER_INST(obj);
+            nrf_drv_spi_uninit(p_spi);
+            (void)nrf_drv_spi_init(p_spi, &config,
+                m_master_event_handlers[SPI_IDX(obj)]);
+        }
+    }
+    // There is no need to set anything in slaves when it comes to frequency,
+    // since slaves just synchronize with the clock provided by a master.
+}
+
+int spi_master_write(spi_t *obj, int value)
+{
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+
+#if DEVICE_SPI_ASYNCH
+
+    while (p_spi_info->flag.busy)
+    {
+    }
+#endif
+
+    p_spi_info->tx_buf = value;
+    p_spi_info->flag.busy = true;
+    (void)nrf_drv_spi_transfer(MASTER_INST(obj),
+        (uint8_t const *)&p_spi_info->tx_buf, 1,
+        (uint8_t *)&p_spi_info->rx_buf, 1);
+
+    while (p_spi_info->flag.busy)
+    {
+    }
+
+    return p_spi_info->rx_buf;
+}
+
+int spi_slave_receive(spi_t *obj)
+{
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+    MBED_ASSERT(!p_spi_info->master);
+    return p_spi_info->flag.readable;
+}
+
+int spi_slave_read(spi_t *obj)
+{
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+    MBED_ASSERT(!p_spi_info->master);
+
+    while (!p_spi_info->flag.readable)
+    {
+    }
+    p_spi_info->flag.readable = false;
+    return p_spi_info->rx_buf;
+}
+
+void spi_slave_write(spi_t *obj, int value)
+{
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+    MBED_ASSERT(!p_spi_info->master);
+
+    p_spi_info->tx_buf = (uint8_t)value;
+}
+
+#if DEVICE_SPI_ASYNCH
+
+void spi_master_transfer(spi_t *obj,
+                         const void *tx, size_t tx_length,
+                         void *rx, size_t rx_length, uint8_t bit_width,
+                         uint32_t handler, uint32_t event, DMAUsage hint)
+{
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+    MBED_ASSERT(p_spi_info->master);
+    (void)hint;
+    (void)bit_width;
+
+    p_spi_info->handler = handler;
+    p_spi_info->event   = event;
+
+    p_spi_info->flag.busy = true;
+    (void)nrf_drv_spi_transfer(MASTER_INST(obj),
+        (uint8_t const *)tx, tx_length,
+        (uint8_t *)rx, rx_length);
+}
+
+uint32_t spi_irq_handler_asynch(spi_t *obj)
+{
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+    MBED_ASSERT(p_spi_info->master);
+    return p_spi_info->event & SPI_EVENT_COMPLETE;
+}
+
+uint8_t spi_active(spi_t *obj)
+{
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+    MBED_ASSERT(p_spi_info->master);
+    return p_spi_info->flag.busy;
+}
+
+void spi_abort_asynch(spi_t *obj)
+{
+    MBED_ASSERT(SPI_INFO(obj)->master);
+    nrf_drv_spi_abort(MASTER_INST(obj));
+}
+
+#endif // DEVICE_SPI_ASYNCH
+
+#endif // DEVICE_SPI

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/us_ticker.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,637 @@
+/*
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ *   1. Redistributions of source code must retain the above copyright notice, this list
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
+ *      integrated circuit in a product or a software update for such product, must reproduce
+ *      the above copyright notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
+ *      used to endorse or promote products derived from this software without specific prior
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse
+ *      engineered, decompiled, modified and/or disassembled.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "us_ticker_api.h"
+#include "common_rtc.h"
+#include "app_util.h"
+#include "nrf_drv_common.h"
+#include "lp_ticker_api.h"
+#include "mbed_critical.h"
+
+#if defined(NRF52_ERRATA_20)
+    #include "softdevice_handler.h"
+#endif
+
+//------------------------------------------------------------------------------
+// Common stuff used also by lp_ticker and rtc_api (see "common_rtc.h").
+//
+#include "app_util_platform.h"
+
+bool              m_common_rtc_enabled   = false;
+uint32_t volatile m_common_rtc_overflows = 0;
+
+#if defined(TARGET_MCU_NRF51822)
+void common_rtc_irq_handler(void)
+#else
+void COMMON_RTC_IRQ_HANDLER(void)
+#endif
+{
+    if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, US_TICKER_EVENT))
+    {
+        us_ticker_irq_handler();
+    }
+
+#if DEVICE_LOWPOWERTIMER
+    if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, LP_TICKER_EVENT))
+    {
+
+        lp_ticker_irq_handler();
+    }
+#endif
+
+    if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW))
+    {
+        nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW);
+        // Don't disable this event. It shall occur periodically.
+
+        ++m_common_rtc_overflows;
+    }
+}
+
+// Function for fix errata 20: RTC Register values are invalid
+__STATIC_INLINE void errata_20(void)
+{
+#if defined(NRF52_ERRATA_20)
+    if (!softdevice_handler_is_enabled())
+    {
+        NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
+        NRF_CLOCK->TASKS_LFCLKSTART    = 1;
+
+        while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0)
+        {
+        }
+    }
+    NRF_RTC1->TASKS_STOP = 0;
+#endif
+}
+
+#if (defined (__ICCARM__)) && defined(TARGET_MCU_NRF51822)//IAR
+__stackless __task
+#endif
+void RTC1_IRQHandler(void);
+
+void common_rtc_init(void)
+{
+    if (m_common_rtc_enabled)
+    {
+        return;
+    }
+
+    errata_20();
+
+    NVIC_SetVector(RTC1_IRQn, (uint32_t)RTC1_IRQHandler);
+
+    // RTC is driven by the low frequency (32.768 kHz) clock, a proper request
+    // must be made to have it running.
+    // Currently this clock is started in 'SystemInit' (see "system_nrf51.c"
+    // or "system_nrf52.c", respectively).
+
+    nrf_rtc_prescaler_set(COMMON_RTC_INSTANCE, 0);
+
+    nrf_rtc_event_clear(COMMON_RTC_INSTANCE, US_TICKER_EVENT);
+#if defined(TARGET_MCU_NRF51822)
+    nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT);
+#endif
+#if DEVICE_LOWPOWERTIMER
+    nrf_rtc_event_clear(COMMON_RTC_INSTANCE, LP_TICKER_EVENT);
+#endif
+    nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW);
+
+    // Interrupts on all related events are enabled permanently. Particular
+    // events will be enabled or disabled as needed (such approach is more
+    // energy efficient).
+    nrf_rtc_int_enable(COMMON_RTC_INSTANCE,
+#if DEVICE_LOWPOWERTIMER
+                       LP_TICKER_INT_MASK |
+#endif
+                       US_TICKER_INT_MASK |
+                       NRF_RTC_INT_OVERFLOW_MASK);
+
+    // This event is enabled permanently, since overflow indications are needed
+    // continuously.
+    nrf_rtc_event_enable(COMMON_RTC_INSTANCE, NRF_RTC_INT_OVERFLOW_MASK);
+    // All other relevant events are initially disabled.
+    nrf_rtc_event_disable(COMMON_RTC_INSTANCE,
+#if defined(TARGET_MCU_NRF51822)
+                          OS_TICK_INT_MASK |
+#endif
+#if DEVICE_LOWPOWERTIMER
+                          LP_TICKER_INT_MASK |
+#endif
+                          US_TICKER_INT_MASK);
+
+    nrf_drv_common_irq_enable(nrf_drv_get_IRQn(COMMON_RTC_INSTANCE),
+#ifdef NRF51
+                              APP_IRQ_PRIORITY_LOW
+#elif defined(NRF52) || defined(NRF52840_XXAA)
+                              APP_IRQ_PRIORITY_LOWEST
+#endif
+                             );
+
+    nrf_rtc_task_trigger(COMMON_RTC_INSTANCE, NRF_RTC_TASK_START);
+
+    m_common_rtc_enabled = true;
+}
+
+uint32_t common_rtc_32bit_ticks_get(void)
+{
+    uint32_t ticks = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
+    // The counter used for time measurements is less than 32 bit wide,
+    // so its value is complemented with the number of registered overflows
+    // of the counter.
+    ticks += (m_common_rtc_overflows << RTC_COUNTER_BITS);
+    return ticks;
+}
+
+uint64_t common_rtc_64bit_us_get(void)
+{
+    uint32_t ticks = common_rtc_32bit_ticks_get();
+    // [ticks -> microseconds]
+    return ROUNDED_DIV(((uint64_t)ticks) * 1000000, RTC_INPUT_FREQ);
+}
+
+void common_rtc_set_interrupt(uint32_t us_timestamp, uint32_t cc_channel,
+                              uint32_t int_mask)
+{
+    // The internal counter is clocked with a frequency that cannot be easily
+    // multiplied to 1 MHz, therefore besides the translation of values
+    // (microsecond <-> ticks) a special care of overflows handling must be
+    // taken. Here the 32-bit timestamp value is complemented with information
+    // about current the system up time of (ticks + number of overflows of tick
+    // counter on upper bits, converted to microseconds), and such 64-bit value
+    // is then translated to counter ticks. Finally, the lower 24 bits of thus
+    // calculated value is written to the counter compare register to prepare
+    // the interrupt generation.
+    uint64_t current_time64 = common_rtc_64bit_us_get();
+    // [add upper 32 bits from the current time to the timestamp value]
+    uint64_t timestamp64 = us_timestamp +
+                           (current_time64 & ~(uint64_t)0xFFFFFFFF);
+
+    // [if the original timestamp value happens to be after the 32 bit counter
+    //  of microsends overflows, correct the upper 32 bits accordingly]
+    if (us_timestamp < (uint32_t)(current_time64 & 0xFFFFFFFF))
+    {
+        timestamp64 += ((uint64_t)1 << 32);
+    }
+    // [microseconds -> ticks, always round the result up to avoid too early
+    //  interrupt generation]
+    uint32_t compare_value =
+        (uint32_t)CEIL_DIV((timestamp64) * RTC_INPUT_FREQ, 1000000);
+
+    // The COMPARE event occurs when the value in compare register is N and
+    // the counter value changes from N-1 to N. Therefore, the minimal safe
+    // difference between the compare value to be set and the current counter
+    // value is 2 ticks. This guarantees that the compare trigger is properly
+    // setup before the compare condition occurs.
+    uint32_t closest_safe_compare = common_rtc_32bit_ticks_get() + 2;
+    if ((int)(compare_value - closest_safe_compare) <= 0)
+    {
+        compare_value = closest_safe_compare;
+    }
+
+    nrf_rtc_cc_set(COMMON_RTC_INSTANCE, cc_channel, RTC_WRAP(compare_value));
+    nrf_rtc_event_enable(COMMON_RTC_INSTANCE, int_mask);
+}
+//------------------------------------------------------------------------------
+
+
+void us_ticker_init(void)
+{
+    common_rtc_init();
+}
+
+uint32_t us_ticker_read()
+{
+    us_ticker_init();
+    return (uint32_t)common_rtc_64bit_us_get();
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+    common_rtc_set_interrupt(timestamp,
+        US_TICKER_CC_CHANNEL, US_TICKER_INT_MASK);
+}
+
+void us_ticker_disable_interrupt(void)
+{
+    nrf_rtc_event_disable(COMMON_RTC_INSTANCE, US_TICKER_INT_MASK);
+}
+
+void us_ticker_clear_interrupt(void)
+{
+    nrf_rtc_event_clear(COMMON_RTC_INSTANCE, US_TICKER_EVENT);
+}
+
+
+// Since there is no SysTick on NRF51, the RTC1 channel 1 is used as an
+// alternative source of RTOS ticks.
+#if defined(TARGET_MCU_NRF51822)
+
+#include "mbed_toolchain.h"
+
+
+#define MAX_RTC_COUNTER_VAL     ((1uL << RTC_COUNTER_BITS) - 1)
+
+/**
+ * The value previously set in the capture compare register of channel 1
+ */
+static uint32_t previous_tick_cc_value = 0;
+
+/*
+ RTX provide the following definitions which are used by the tick code:
+   * os_trv: The number (minus 1) of clock cycle between two tick.
+   * os_clockrate: Time duration between two ticks (in us).
+   * OS_Tick_Handler: The function which handle a tick event.
+     This function is special because it never returns.
+ Those definitions are used by the code which handle the os tick.
+ To allow compilation of us_ticker programs without RTOS, those symbols are
+ exported from this module as weak ones.
+ */
+MBED_WEAK uint32_t const os_trv;
+MBED_WEAK uint32_t const os_clockrate;
+MBED_WEAK void OS_Tick_Handler()
+{
+}
+
+
+#if defined (__CC_ARM)         /* ARMCC Compiler */
+
+__asm void COMMON_RTC_IRQ_HANDLER(void)
+{
+    IMPORT  OS_Tick_Handler
+    IMPORT  common_rtc_irq_handler
+
+    /**
+     * Chanel 1 of RTC1 is used by RTX as a systick.
+     * If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
+     * Otherwise, just execute common_rtc_irq_handler.
+     * This function has to be written in assembly and tagged as naked because OS_Tick_Handler
+     * will never return.
+     * A c function would put lr on the stack before calling OS_Tick_Handler and this value
+     * would never been dequeued.
+     *
+     * \code
+     * void COMMON_RTC_IRQ_HANDLER(void) {
+         if(NRF_RTC1->EVENTS_COMPARE[1]) {
+             // never return...
+             OS_Tick_Handler();
+         } else {
+             common_rtc_irq_handler();
+         }
+       }
+     * \endcode
+     */
+    ldr r0,=0x40011144
+    ldr r1, [r0, #0]
+    cmp r1, #0
+    beq US_TICKER_HANDLER
+    bl OS_Tick_Handler
+US_TICKER_HANDLER
+    push {r3, lr}
+    bl common_rtc_irq_handler
+    pop {r3, pc}
+    ; ALIGN ;
+}
+
+#elif defined (__GNUC__)        /* GNU Compiler */
+
+__attribute__((naked)) void COMMON_RTC_IRQ_HANDLER(void)
+{
+    /**
+     * Chanel 1 of RTC1 is used by RTX as a systick.
+     * If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
+     * Otherwise, just execute common_rtc_irq_handler.
+     * This function has to be written in assembly and tagged as naked because OS_Tick_Handler
+     * will never return.
+     * A c function would put lr on the stack before calling OS_Tick_Handler and this value
+     * would never been dequeued.
+     *
+     * \code
+     * void COMMON_RTC_IRQ_HANDLER(void) {
+         if(NRF_RTC1->EVENTS_COMPARE[1]) {
+             // never return...
+             OS_Tick_Handler();
+         } else {
+             common_rtc_irq_handler();
+         }
+       }
+     * \endcode
+     */
+    __asm__ (
+        "ldr r0,=0x40011144\n"
+        "ldr r1, [r0, #0]\n"
+        "cmp r1, #0\n"
+        "beq US_TICKER_HANDLER\n"
+        "bl OS_Tick_Handler\n"
+    "US_TICKER_HANDLER:\n"
+        "push {r3, lr}\n"
+        "bl common_rtc_irq_handler\n"
+        "pop {r3, pc}\n"
+        "nop"
+    );
+}
+
+#elif defined (__ICCARM__)//IAR
+void common_rtc_irq_handler(void);
+
+__stackless __task void COMMON_RTC_IRQ_HANDLER(void)
+{
+    uint32_t temp;
+
+    __asm volatile(
+    "   ldr  %[temp], [%[reg2check]] \n"
+    "   cmp  %[temp], #0             \n"
+    "   beq  1f                      \n"
+    "   bl.w OS_Tick_Handler            \n"
+    "1:                             \n"
+    "   push {r3, lr}\n"
+    "   blx %[rtc_irq] \n"
+    "   pop {r3, pc}\n"
+
+    : /* Outputs */
+    [temp] "=&r"(temp)
+    : /* Inputs */
+    [reg2check] "r"(0x40011144),
+    [rtc_irq] "r"(common_rtc_irq_handler)
+    : /* Clobbers */
+    "cc"
+    );
+    (void)temp;
+}
+
+
+#else
+
+#error Compiler not supported.
+#error Provide a definition of COMMON_RTC_IRQ_HANDLER.
+
+/*
+ * Chanel 1 of RTC1 is used by RTX as a systick.
+ * If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
+ * Otherwise, just execute common_rtc_irq_handler.
+ * This function has to be written in assembly and tagged as naked because OS_Tick_Handler
+ * will never return.
+ * A c function would put lr on the stack before calling OS_Tick_Handler and this value
+ * will never been dequeued. After a certain time a stack overflow will happen.
+ *
+ * \code
+ * void COMMON_RTC_IRQ_HANDLER(void) {
+     if(NRF_RTC1->EVENTS_COMPARE[1]) {
+         // never return...
+         OS_Tick_Handler();
+     } else {
+         common_rtc_irq_handler();
+     }
+   }
+ * \endcode
+ */
+
+#endif
+
+/**
+ * Return the next number of clock cycle needed for the next tick.
+ * @note This function has been carrefuly optimized for a systick occuring every 1000us.
+ */
+static uint32_t get_next_tick_cc_delta()
+{
+    uint32_t delta = 0;
+
+    if (os_clockrate != 1000)
+    {
+        // In RTX, by default SYSTICK is is used.
+        // A tick event is generated  every os_trv + 1 clock cycles of the system timer.
+        delta = os_trv + 1;
+    }
+    else
+    {
+        // If the clockrate is set to 1000us then 1000 tick should happen every second.
+        // Unfortunatelly, when clockrate is set to 1000, os_trv is equal to 31.
+        // If (os_trv + 1) is used as the delta value between two ticks, 1000 ticks will be
+        // generated in 32000 clock cycle instead of 32768 clock cycles.
+        // As a result, if a user schedule an OS timer to start in 100s, the timer will start
+        // instead after 97.656s
+        // The code below fix this issue, a clock rate of 1000s will generate 1000 ticks in 32768
+        // clock cycles.
+        // The strategy is simple, for 1000 ticks:
+        //   * 768 ticks will occur 33 clock cycles after the previous tick
+        //   * 232 ticks will occur 32 clock cycles after the previous tick
+        // By default every delta is equal to 33.
+        // Every five ticks (20%, 200 delta in one second), the delta is equal to 32
+        // The remaining (32) deltas equal to 32 are distributed using primes numbers.
+        static uint32_t counter = 0;
+        if ((counter % 5) == 0 || (counter % 31) == 0 || (counter % 139) == 0 || (counter == 503))
+        {
+            delta = 32;
+        }
+        else
+        {
+            delta = 33;
+        }
+        ++counter;
+        if (counter == 1000)
+        {
+            counter = 0;
+        }
+    }
+    return delta;
+}
+
+
+static inline void clear_tick_interrupt()
+{
+    nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT);
+    nrf_rtc_event_disable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
+}
+
+/**
+ * Indicate if a value is included in a range which can be wrapped.
+ * @param  begin start of the range
+ * @param  end   end of the range
+ * @param  val   value to check
+ * @return       true if the value is included in the range and false otherwise.
+ */
+static inline bool is_in_wrapped_range(uint32_t begin, uint32_t end, uint32_t val)
+{
+    // regular case, begin < end
+    // return true if  begin <= val < end
+    if (begin < end)
+    {
+        if (begin <= val && val < end)
+        {
+            return true;
+        }
+        else
+        {
+            return false;
+        }
+    }
+    else
+    {
+        // In this case end < begin because it has wrap around the limits
+        // return false if end < val < begin
+        if (end < val && val < begin)
+        {
+            return false;
+        }
+        else
+        {
+            return true;
+        }
+    }
+
+}
+
+/**
+ * Register the next tick.
+ */
+static void register_next_tick()
+{
+    previous_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL);
+    uint32_t delta = get_next_tick_cc_delta();
+    uint32_t new_compare_value = (previous_tick_cc_value + delta) & MAX_RTC_COUNTER_VAL;
+
+    // Disable irq directly for few cycles,
+    // Validation of the new CC value against the COUNTER,
+    // Setting the new CC value and enabling CC IRQ should be an atomic operation
+    // Otherwise, there is a possibility to set an invalid CC value because
+    // the RTC1 keeps running.
+    // This code is very short 20-38 cycles in the worst case, it shouldn't
+    // disturb softdevice.
+    core_util_critical_section_enter();
+    uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
+
+    // If an overflow occur, set the next tick in COUNTER + delta clock cycles
+    if (is_in_wrapped_range(previous_tick_cc_value, new_compare_value, current_counter + 1) == false)
+    {
+        new_compare_value = current_counter + delta;
+    }
+    nrf_rtc_cc_set(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL, new_compare_value);
+    // Enable generation of the compare event for the value set above (this
+    // event will trigger the interrupt).
+    nrf_rtc_event_enable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
+    core_util_critical_section_exit();
+}
+
+/**
+ * Initialize alternative hardware timer as RTX kernel timer
+ * This function is directly called by RTX.
+ * @note this function shouldn't be called directly.
+ * @return  IRQ number of the alternative hardware timer
+ */
+int os_tick_init (void)
+{
+    common_rtc_init();
+    nrf_rtc_int_enable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
+
+    nrf_rtc_cc_set(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL, 0);
+    register_next_tick();
+
+    return nrf_drv_get_IRQn(COMMON_RTC_INSTANCE);
+}
+
+/**
+ * Acknowledge the tick interrupt.
+ * This function is called by the function OS_Tick_Handler of RTX.
+ * @note this function shouldn't be called directly.
+ */
+void os_tick_irqack(void)
+{
+    clear_tick_interrupt();
+    register_next_tick();
+}
+
+/**
+ * Returns the overflow flag of the alternative hardware timer.
+ * @note This function is exposed by RTX kernel.
+ * @return 1 if the timer has overflowed and 0 otherwise.
+ */
+uint32_t os_tick_ovf(void)
+{
+    uint32_t current_counter    = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
+    uint32_t next_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL);
+
+    return is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter) ? 0 : 1;
+}
+
+/**
+ * Return the value of the alternative hardware timer.
+ * @note The documentation is not very clear about what is expected as a result,
+ * is it an ascending counter, a descending one ?
+ * None of this is specified.
+ * The default systick is a descending counter and this function return values in
+ * descending order, even if the internal counter used is an ascending one.
+ * @return the value of the alternative hardware timer.
+ */
+uint32_t os_tick_val(void)
+{
+    uint32_t current_counter    = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
+    uint32_t next_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL);
+
+    // do not use os_tick_ovf because its counter value can be different
+    if (is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter))
+    {
+        if (next_tick_cc_value > previous_tick_cc_value)
+        {
+            return next_tick_cc_value - current_counter;
+        }
+        else if (current_counter <= next_tick_cc_value)
+        {
+            return next_tick_cc_value - current_counter;
+        }
+        else
+        {
+            return next_tick_cc_value + (MAX_RTC_COUNTER_VAL - current_counter);
+        }
+    }
+    else
+    {
+        // use (os_trv + 1) has the base step, can be totally inacurate ...
+        uint32_t clock_cycles_by_tick = os_trv + 1;
+
+        // if current counter has wrap arround, add the limit to it.
+        if (current_counter < next_tick_cc_value)
+        {
+            current_counter = current_counter + MAX_RTC_COUNTER_VAL;
+        }
+
+        return clock_cycles_by_tick - ((current_counter - next_tick_cc_value) % clock_cycles_by_tick);
+    }
+
+}
+
+#endif // defined(TARGET_MCU_NRF51822)

--- a/targets/TARGET_NORDIC/mbed_rtx.h	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_NORDIC/mbed_rtx.h	Wed Apr 12 16:21:43 2017 +0100
@@ -55,6 +55,21 @@
 #define OS_CLOCK                64000000
 #endif
 
+#elif defined(TARGET_MCU_NRF52840)
+
+#ifndef INITIAL_SP
+#define INITIAL_SP              (0x20040000UL)
+#endif
+#ifndef OS_TASKCNT
+#define OS_TASKCNT              24
+#endif
+#ifndef OS_MAINSTKSIZE
+#define OS_MAINSTKSIZE          2048
+#endif
+#ifndef OS_CLOCK
+#define OS_CLOCK                64000000
 #endif
 
-#endif
+#endif // defined(TARGET_MCU_NRF51822)...
+
+#endif // #ifndef MBED_MBED_RTX_H

--- a/targets/TARGET_NXP/TARGET_LPC176X/TARGET_UBLOX_C027/C027_api.c	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC176X/TARGET_UBLOX_C027/C027_api.c	Wed Apr 12 16:21:43 2017 +0100
@@ -16,6 +16,7 @@
 #include "gpio_api.h"
 #include "mbed_wait_api.h"
 #include "C027_api.h"
+#include "us_ticker_api.h"
 
 static gpio_t mdmEn, mdmLvlOe, mdmILvlOe, mdmUsbDet;
 static gpio_t gpsEn;
@@ -36,7 +37,10 @@
     // led should be off
     gpio_init_out_ex(&led,       LED,       0);
     
-    wait_ms(50); // when USB cable is inserted the interface chip issues 
+    // Can't use wait_ms() as RTOS isn't initialised yet
+    // so this is the correct way to wait for 50 ms
+    uint32_t start = us_ticker_read();
+    while ((us_ticker_read() - start) < 50000);
 }
 
 void c027_mdm_powerOn(int usb) {

--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h	Wed Apr 12 16:21:43 2017 +0100
@@ -178,11 +178,11 @@
     A0          = PA_3,
     A1          = PC_0,
     A2          = PC_3,
-    A3          = PC_1,
-    A4          = PC_4,
-    A5          = PC_5,
-    D0          = PG_9,
-    D1          = PG_14,
+    A3          = PD_11,
+    A4          = PD_12,
+    A5          = PD_13,
+    D0          = PC_5,
+    D1          = PC_14,
     D2          = PF_15,
     D3          = PE_13,
     D4          = PF_14,

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralNames.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE,
+    ADC_2 = (int) ADC2_BASE,
+    ADC_3 = (int) ADC3_BASE
+} ADCName;
+
+
+typedef enum {
+    UART_1 = (int)USART1_BASE,
+    UART_2 = (int)USART2_BASE,
+    UART_3 = (int)USART3_BASE,
+    UART_4 = (int)UART4_BASE,
+    UART_5 = (int)UART5_BASE,
+    UART_6 = (int)USART6_BASE,
+    UART_7 = (int)UART7_BASE,
+    UART_8 = (int)UART8_BASE
+} UARTName;
+
+#define STDIO_UART_TX  PA_9
+#define STDIO_UART_RX  PA_10
+#define STDIO_UART     UART_1
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE,
+    SPI_3 = (int)SPI3_BASE,
+    SPI_4 = (int)SPI4_BASE,
+    SPI_5 = (int)SPI5_BASE,
+    SPI_6 = (int)SPI6_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE,
+    I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1  = (int)TIM1_BASE,
+    PWM_2  = (int)TIM2_BASE,
+    PWM_3  = (int)TIM3_BASE,
+    PWM_4  = (int)TIM4_BASE,
+    PWM_5  = (int)TIM5_BASE,
+    PWM_8  = (int)TIM8_BASE,
+    PWM_9  = (int)TIM9_BASE,
+    PWM_10 = (int)TIM10_BASE,
+    PWM_11 = (int)TIM11_BASE,
+    PWM_12 = (int)TIM12_BASE,
+    PWM_13 = (int)TIM13_BASE,
+    PWM_14 = (int)TIM14_BASE
+} PWMName;
+
+typedef enum {
+    DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+    CAN_1 = (int)CAN1_BASE,
+    CAN_2 = (int)CAN2_BASE
+} CANName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,120 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+//       If you change them, you will have also to modify the corresponding xxx_api.c file
+//       for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3,  0)}, // ADC1_IN3
+    {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4,  0)}, // ADC1_IN4
+    {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6,  0)}, // ADC1_IN6
+    {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8,  0)}, // ADC1_IN8
+    {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+    {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+
+const PinMap PinMap_I2C_SDA[] = {
+    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PC_9,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PA_8,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_DAC[] = {
+    {PA_5,  DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 - ARDUINO D13
+    {NC,   NC,    0}
+};
+
+//*** PWM ***
+
+const PinMap PinMap_PWM[] = {
+    {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+    {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)},  // TIM1_CH1N
+    {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
+    {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)},  // TIM4_CH1
+    {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)},  // TIM10_CH1
+    {PB_15, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)},  // TIM12_CH2
+    {NC,    NC,    0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PD_5,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PD_9,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_6,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA_10,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PD_6,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PD_8,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_7,  UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+    {NC,    NC,     0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+    {NC,    NC,    0}
+};

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PinNames.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,144 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PA_0  = 0x00, PA_1  = 0x01, PA_2  = 0x02, PA_3  = 0x03,
+    PA_4  = 0x04, PA_5  = 0x05, PA_6  = 0x06, PA_7  = 0x07,
+    PA_8  = 0x08, PA_9  = 0x09, PA_10 = 0x0A, PA_11 = 0x0B,
+    PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F,
+
+    PB_0  = 0x10, PB_1  = 0x11, PB_2  = 0x12, PB_3  = 0x13,
+    PB_4  = 0x14, PB_5  = 0x15, PB_6  = 0x16, PB_7  = 0x17,
+    PB_8  = 0x18, PB_9  = 0x19, PB_10 = 0x1A, PB_11 = 0x1B,
+    PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F,
+
+    PC_0  = 0x20, PC_1  = 0x21, PC_2  = 0x22, PC_3  = 0x23,
+    PC_4  = 0x24, PC_5  = 0x25, PC_6  = 0x26, PC_7  = 0x27,
+    PC_8  = 0x28, PC_9  = 0x29, PC_10 = 0x2A, PC_11 = 0x2B,
+    PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, PC_15 = 0x2F,
+
+    PD_0  = 0x30, PD_1  = 0x31, PD_2  = 0x32, PD_3  = 0x33,
+    PD_4  = 0x34, PD_5  = 0x35, PD_6  = 0x36, PD_7  = 0x37,
+    PD_8  = 0x38, PD_9  = 0x39, PD_10 = 0x3A, PD_11 = 0x3B,
+    PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F,
+    
+    PE_0  = 0x40, PE_1  = 0x41, PE_2  = 0x42, PE_3  = 0x43,
+    PE_4  = 0x44, PE_5  = 0x45, PE_6  = 0x46, PE_7  = 0x47,
+    PE_8  = 0x48, PE_9  = 0x49, PE_10 = 0x4A, PE_11 = 0x4B,
+    PE_12 = 0x4C, PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F,
+
+
+    PH_0  = 0x70, PH_1  = 0x71,
+    
+    // Not connected
+    NC = -1,
+
+    GNSSTXD = PC_6,
+    GNSSRXD = PC_7,
+    // Control
+    GNSSRST = PC_10, // Reset (input to GPS, active low)
+    GNSSPWR = PE_0,  // 2.8V rail, should be set to open drain output
+    GNSSEN = PA_15,  // VCC_IO to GNSS, should be set to push-pull, no pull-up, output
+    // u-blox LISA/SARA cellular modem
+    // http://www.u-blox.com/wireless-modules.html
+    // -----------------------------------------------------------
+    // UART (LISA/SARA = DCE)
+    MDMTXD = PD_5, // Transmit Data
+    MDMRXD = PD_6, // Receive Data
+    MDMCTS = PD_3, // Clear to Send
+    MDMRTS = PD_4, // Request to Send (set high or use handshake)
+    MDMDCD = NC,   // DCD line not connecetd
+    
+    // USB
+    // Control 
+    MDMEN     = PC_2,  // Supply Control (high = enabled)
+    MDMPWRON  = PE_14,  // 
+    MDMGPIO2  = PD_1,  // 
+    MDMGPIO3  = PB_4,  //
+    MDMRST    = PB_5,  // Reset (active low, set as open drain!)
+
+    // Board Pins
+    // A0-A5
+    A0      = PA_3,  
+    A1      = PC_0,
+    A2      = PC_3,
+    A3      = PA_4,  
+    A4      = PA_6,  
+    A5      = PB_0,  
+    // D0-D15
+    D0      = PD_9,   // UART3-RX
+    D1      = PD_8,   // UART3-TX
+    D2      = PD_11,  // UART3-CTS
+    D3      = PB_14,  // UART3-RTS
+    D4      = PB_1,
+    D5      = PA_5,
+    D6      = PB_8,   // UART3-CTS
+    D7      = PB_15,  // UART3-RTS
+    D8      = PD_15,  // UART1-TX
+    D9      = PD_12,  // SDCard-CS
+    D10     = PE_11,  // SSEL
+    D11     = PE_6,   // MOSI
+    D12     = PE_5,   // MISO
+    D13     = PE_2,   // SCK
+    D14     = PB_7,   // SDA
+    D15     = PB_6,   // SCL
+    // Internal
+    LED1    = PE_3,   // Red / Mode
+    LED2    = PE_4,   // Green / Switch-1
+    LED3    = PE_1,   // Blue
+    LED4    = PE_7,   // A definition is required by the mbed platform RTC test code, this is the Ethernet connector yellow LED
+    LED_RED = LED1,
+    SW0     = PC_13,  // Switch-0
+
+    // ST-Link
+    USBRX   = PA_10,
+    USBTX   = PA_9,
+    SWDIO   = PA_13, 
+    SWCLK   = PA_14, 
+    NTRST   = PB_4,  
+} PinName;
+
+#define GNSSBAUD    9600    // Default GNSS Baud Rate
+#define MDMBAUD     115200  // Default Modem Baud Rate
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/system_stm32f4xx.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,872 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.c
+  * @author  MCD Application Team
+  * @version V2.5.0
+  * @date    22-April-2016
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f4xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * This file configures the system clock as follows:
+  *--------------------------------------------------------------------------------------
+  * System clock source                | PLL_HSE_XTAL           | PLL_HSE_XTAL           
+  *                                    | (external 8 MHz clock) | (external 8 MHz clock) 
+  *--------------------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 168                    | 84                    
+  *--------------------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 168                    | 84                   
+  *--------------------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 42                     | 42                     
+  *--------------------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 84                     | 84                     
+  *--------------------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | YES                    | YES                     
+  *--------------------------------------------------------------------------------------
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F4xx_System_Private_Includes
+  * @{
+  */
+
+
+#include "stm32f4xx.h"
+#include "hal_tick.h"
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+          STM32F412Zx || STM32F412Vx */
+ 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/* #define DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+          STM32F479xx */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+  * @{
+  */
+
+/* Select the SYSCLOCK  to start with (0=OFF, 1=ON) */
+#define USE_SYSCLOCK_168 (1) /* Use external 8MHz xtal and sets SYSCLK to 168MHz */
+#define USE_SYSCLOCK_84 (0) /* Use external 8MHz xtal and sets SYSCLK to 84MHz */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 168000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+void SetSysClock(void);
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and External memory 
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+  /* Configure the Cube driver */
+  SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
+  HAL_Init();
+
+  /* Configure the System clock source, PLL Multiplier and Divider factors,
+     AHB/APBx prescalers and Flash settings */
+  SetSysClock();
+  SystemCoreClockUpdate();
+  
+  /* Reset the timer to avoid issues after the RAM initialization */
+  TIM_MST_RESET_ON;
+  TIM_MST_RESET_OFF;  
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
+  *              depends on the application requirements), user has to ensure that HSE_VALUE
+  *              is same as the real frequency of the crystal used. Otherwise, this function
+  *              may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f4xx.s before jump to main.
+  *         This function configures the external memories (SRAM/SDRAM)
+  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+  __IO uint32_t tmp = 0x00;
+
+  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register __IO uint32_t index;
+
+  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
+  RCC->AHB1ENR |= 0x000001F8;
+
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+  
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CCC0CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A8A;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0FCF;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00CC0CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA828A;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC3CF;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+  
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0xCCCCCCCC;
+  GPIOF->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA800AAA;
+  /* Configure PFx pins speed to 50 MHz */ 
+  GPIOF->OSPEEDR = 0xAA800AAA;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0xCCCCCCCC;
+  GPIOG->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0xAAAAAAAA;
+  /* Configure PGx pins speed to 50 MHz */ 
+  GPIOG->OSPEEDR = 0xAAAAAAAA;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+  /* Connect PHx pins to FMC Alternate function */
+  GPIOH->AFR[0]  = 0x00C0CC00;
+  GPIOH->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PHx pins in Alternate function mode */ 
+  GPIOH->MODER   = 0xAAAA08A0;
+  /* Configure PHx pins speed to 50 MHz */ 
+  GPIOH->OSPEEDR = 0xAAAA08A0;
+  /* Configure PHx pins Output type to push-pull */  
+  GPIOH->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PHx pins */ 
+  GPIOH->PUPDR   = 0x00000000;
+  
+  /* Connect PIx pins to FMC Alternate function */
+  GPIOI->AFR[0]  = 0xCCCCCCCC;
+  GPIOI->AFR[1]  = 0x00000CC0;
+  /* Configure PIx pins in Alternate function mode */ 
+  GPIOI->MODER   = 0x0028AAAA;
+  /* Configure PIx pins speed to 50 MHz */ 
+  GPIOI->OSPEEDR = 0x0028AAAA;
+  /* Configure PIx pins Output type to push-pull */  
+  GPIOI->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PIx pins */ 
+  GPIOI->PUPDR   = 0x00000000;
+  
+/*-- FMC Configuration -------------------------------------------------------*/
+  /* Enable the FMC interface clock */
+  RCC->AHB3ENR |= 0x00000001;
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+  FMC_Bank5_6->SDCR[0] = 0x000019E4;
+  FMC_Bank5_6->SDTR[0] = 0x01115351;      
+  
+  /* SDRAM initialization sequence */
+  /* Clock enable command */
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+
+  /* Delay */
+  for (index = 0; index<1000; index++);
+  
+  /* PALL command */
+  FMC_Bank5_6->SDCMR = 0x00000012;           
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+  
+  /* Auto refresh command */
+  FMC_Bank5_6->SDCMR = 0x00000073;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+ 
+  /* MRD register program */
+  FMC_Bank5_6->SDCMR = 0x00046014;
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
+  /* Set refresh count */
+  tmpreg = FMC_Bank5_6->SDRTR;
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+  
+  /* Disable write protection */
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
+  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001011;
+  FMC_Bank1->BTCR[3]  = 0x00000201;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
+#if defined(STM32F469xx) || defined(STM32F479xx)
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001091;
+  FMC_Bank1->BTCR[3]  = 0x00110212;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F469xx || STM32F479xx */
+
+  (void)(tmp); 
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f4xx.s before jump to main.
+  *         This function configures the external memories (SRAM/SDRAM)
+  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+  __IO uint32_t tmp = 0x00;
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined (DATA_IN_ExtSDRAM)
+  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register __IO uint32_t index;
+
+#if defined(STM32F446xx)
+  /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
+      clock */
+  RCC->AHB1ENR |= 0x0000007D;
+#else
+  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface 
+      clock */
+  RCC->AHB1ENR |= 0x000001F8;
+#endif /* STM32F446xx */  
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+  
+#if defined(STM32F446xx)
+  /* Connect PAx pins to FMC Alternate function */
+  GPIOA->AFR[0]  |= 0xC0000000;
+  GPIOA->AFR[1]  |= 0x00000000;
+  /* Configure PDx pins in Alternate function mode */
+  GPIOA->MODER   |= 0x00008000;
+  /* Configure PDx pins speed to 50 MHz */
+  GPIOA->OSPEEDR |= 0x00008000;
+  /* Configure PDx pins Output type to push-pull */
+  GPIOA->OTYPER  |= 0x00000000;
+  /* No pull-up, pull-down for PDx pins */
+  GPIOA->PUPDR   |= 0x00000000;
+
+  /* Connect PCx pins to FMC Alternate function */
+  GPIOC->AFR[0]  |= 0x00CC0000;
+  GPIOC->AFR[1]  |= 0x00000000;
+  /* Configure PDx pins in Alternate function mode */
+  GPIOC->MODER   |= 0x00000A00;
+  /* Configure PDx pins speed to 50 MHz */
+  GPIOC->OSPEEDR |= 0x00000A00;
+  /* Configure PDx pins Output type to push-pull */
+  GPIOC->OTYPER  |= 0x00000000;
+  /* No pull-up, pull-down for PDx pins */
+  GPIOC->PUPDR   |= 0x00000000;
+#endif /* STM32F446xx */
+
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x000000CC;
+  GPIOD->AFR[1]  = 0xCC000CCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xA02A000A;
+  /* Configure PDx pins speed to 50 MHz */  
+  GPIOD->OSPEEDR = 0xA02A000A;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00000CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA800A;
+  /* Configure PEx pins speed to 50 MHz */ 
+  GPIOE->OSPEEDR = 0xAAAA800A;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0xCCCCCCCC;
+  GPIOF->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA800AAA;
+  /* Configure PFx pins speed to 50 MHz */ 
+  GPIOF->OSPEEDR = 0xAA800AAA;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0xCCCCCCCC;
+  GPIOG->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0xAAAAAAAA;
+  /* Configure PGx pins speed to 50 MHz */ 
+  GPIOG->OSPEEDR = 0xAAAAAAAA;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx)  
+  /* Connect PHx pins to FMC Alternate function */
+  GPIOH->AFR[0]  = 0x00C0CC00;
+  GPIOH->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PHx pins in Alternate function mode */ 
+  GPIOH->MODER   = 0xAAAA08A0;
+  /* Configure PHx pins speed to 50 MHz */ 
+  GPIOH->OSPEEDR = 0xAAAA08A0;
+  /* Configure PHx pins Output type to push-pull */  
+  GPIOH->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PHx pins */ 
+  GPIOH->PUPDR   = 0x00000000;
+  
+  /* Connect PIx pins to FMC Alternate function */
+  GPIOI->AFR[0]  = 0xCCCCCCCC;
+  GPIOI->AFR[1]  = 0x00000CC0;
+  /* Configure PIx pins in Alternate function mode */ 
+  GPIOI->MODER   = 0x0028AAAA;
+  /* Configure PIx pins speed to 50 MHz */ 
+  GPIOI->OSPEEDR = 0x0028AAAA;
+  /* Configure PIx pins Output type to push-pull */  
+  GPIOI->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PIx pins */ 
+  GPIOI->PUPDR   = 0x00000000;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+  
+/*-- FMC Configuration -------------------------------------------------------*/
+  /* Enable the FMC interface clock */
+  RCC->AHB3ENR |= 0x00000001;
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+  /* Configure and enable SDRAM bank1 */
+#if defined(STM32F446xx)
+  FMC_Bank5_6->SDCR[0] = 0x00001954;
+#else  
+  FMC_Bank5_6->SDCR[0] = 0x000019E4;
+#endif /* STM32F446xx */
+  FMC_Bank5_6->SDTR[0] = 0x01115351;      
+  
+  /* SDRAM initialization sequence */
+  /* Clock enable command */
+  FMC_Bank5_6->SDCMR = 0x00000011; 
+  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+
+  /* Delay */
+  for (index = 0; index<1000; index++);
+  
+  /* PALL command */
+  FMC_Bank5_6->SDCMR = 0x00000012;           
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+  
+  /* Auto refresh command */
+#if defined(STM32F446xx)
+  FMC_Bank5_6->SDCMR = 0x000000F3;
+#else  
+  FMC_Bank5_6->SDCMR = 0x00000073;
+#endif /* STM32F446xx */
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  }
+ 
+  /* MRD register program */
+#if defined(STM32F446xx)
+  FMC_Bank5_6->SDCMR = 0x00044014;
+#else  
+  FMC_Bank5_6->SDCMR = 0x00046014;
+#endif /* STM32F446xx */
+  timeout = 0xFFFF;
+  while((tmpreg != 0) && (timeout-- > 0))
+  {
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; 
+  } 
+  
+  /* Set refresh count */
+  tmpreg = FMC_Bank5_6->SDRTR;
+#if defined(STM32F446xx)
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
+#else    
+  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+#endif /* STM32F446xx */
+  
+  /* Disable write protection */
+  tmpreg = FMC_Bank5_6->SDCR[0]; 
+  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+#endif /* DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
+
+#if defined(DATA_IN_ExtSRAM)
+/*-- GPIOs Configuration -----------------------------------------------------*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   |= 0x00000078;
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
+  
+  /* Connect PDx pins to FMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CCC0CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A8A;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0FCF;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00CC0CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA828A;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC3CF;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x000000C0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00085AAA;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000CAFFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FMC/FSMC Configuration --------------------------------------------------*/                                                                               
+  /* Enable the FMC/FSMC interface clock */
+  RCC->AHB3ENR         |= 0x00000001;
+  
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) 
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001011;
+  FMC_Bank1->BTCR[3]  = 0x00000201;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ 
+#if defined(STM32F469xx) || defined(STM32F479xx)
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+  /* Configure and enable Bank1_SRAM2 */
+  FMC_Bank1->BTCR[2]  = 0x00001091;
+  FMC_Bank1->BTCR[3]  = 0x00110212;
+  FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F469xx || STM32F479xx */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+   || defined(STM32F412Zx) || defined(STM32F412Vx)
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001011;
+  FSMC_Bank1->BTCR[3]  = 0x00000201;
+  FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
+
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ 
+  (void)(tmp); 
+}
+#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
+
+/** System Clock Configuration
+*/
+#if USE_SYSCLOCK_168 != 0
+/*
+ * Set SYSCLK=168MHZ
+ */
+void SetSysClock(void)
+{
+
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+  __PWR_CLK_ENABLE();
+
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 8;
+  RCC_OscInitStruct.PLL.PLLN = 336;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 7;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
+                              |RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
+  
+  // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
+
+
+}
+
+#elif USE_SYSCLOCK_84 != 0
+/*
+Set SYSCLK=84MHZ
+ */
+void SetSysClock(void)
+{
+
+  RCC_OscInitTypeDef RCC_OscInitStruct;
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+  __PWR_CLK_ENABLE();
+
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 8;
+  RCC_OscInitStruct.PLL.PLLN = 336;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+  RCC_OscInitStruct.PLL.PLLQ = 7;
+  HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
+                              |RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
+
+  // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
+
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_ARM_STD/startup_stm32f437xx.S	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,414 @@
+;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
+;* File Name          : startup_stm32f437xx.s
+;* Author             : MCD Application Team
+;* Version            : V2.4.0
+;* Date               : 14-August-2015
+;* Description        : STM32F437x devices vector table for MDK-ARM_STD toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+;
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+
+__initial_sp    EQU     0x20030000 ; Top of RAM
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9
+                DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDIO_IRQHandler                   ; SDIO
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
+                DCD     ETH_IRQHandler                    ; Ethernet
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
+                DCD     USART6_IRQHandler                 ; USART6
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS
+                DCD     DCMI_IRQHandler                   ; DCMI
+                DCD     CRYP_IRQHandler                   ; CRYPTO
+                DCD     HASH_RNG_IRQHandler               ; Hash and Rng
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     UART7_IRQHandler                  ; UART7
+                DCD     UART8_IRQHandler                  ; UART8
+                DCD     SPI4_IRQHandler                   ; SPI4
+                DCD     SPI5_IRQHandler                   ; SPI5
+                DCD     SPI6_IRQHandler                   ; SPI6
+                DCD     SAI1_IRQHandler                   ; SAI1
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     DMA2D_IRQHandler                  ; DMA2D
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_IRQHandler                    [WEAK]
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]
+                EXPORT  ADC_IRQHandler                    [WEAK]
+                EXPORT  CAN1_TX_IRQHandler                [WEAK]
+                EXPORT  CAN1_RX0_IRQHandler               [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_TIM9_IRQHandler          [WEAK]
+                EXPORT  TIM1_UP_TIM10_IRQHandler          [WEAK]
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler     [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  TIM3_IRQHandler                   [WEAK]
+                EXPORT  TIM4_IRQHandler                   [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  USART2_IRQHandler                 [WEAK]
+                EXPORT  USART3_IRQHandler                 [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK]
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]
+                EXPORT  FMC_IRQHandler                    [WEAK]
+                EXPORT  SDIO_IRQHandler                   [WEAK]
+                EXPORT  TIM5_IRQHandler                   [WEAK]
+                EXPORT  SPI3_IRQHandler                   [WEAK]
+                EXPORT  UART4_IRQHandler                  [WEAK]
+                EXPORT  UART5_IRQHandler                  [WEAK]
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]
+                EXPORT  TIM7_IRQHandler                   [WEAK]
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]
+                EXPORT  ETH_IRQHandler                    [WEAK]
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]
+                EXPORT  CAN2_TX_IRQHandler                [WEAK]
+                EXPORT  CAN2_RX0_IRQHandler               [WEAK]
+                EXPORT  CAN2_RX1_IRQHandler               [WEAK]
+                EXPORT  CAN2_SCE_IRQHandler               [WEAK]
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]
+                EXPORT  USART6_IRQHandler                 [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]
+                EXPORT  DCMI_IRQHandler                   [WEAK]
+                EXPORT  CRYP_IRQHandler                   [WEAK]
+                EXPORT  HASH_RNG_IRQHandler               [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  UART7_IRQHandler                  [WEAK]
+                EXPORT  UART8_IRQHandler                  [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+                EXPORT  SPI5_IRQHandler                   [WEAK]
+                EXPORT  SPI6_IRQHandler                   [WEAK]
+                EXPORT  SAI1_IRQHandler                   [WEAK]
+                EXPORT  DMA2D_IRQHandler                  [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_TIM9_IRQHandler
+TIM1_UP_TIM10_IRQHandler
+TIM1_TRG_COM_TIM11_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+OTG_FS_WKUP_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDIO_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+CAN2_TX_IRQHandler
+CAN2_RX0_IRQHandler
+CAN2_RX1_IRQHandler
+CAN2_SCE_IRQHandler
+OTG_FS_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+DMA2D_IRQHandler
+                B       .
+
+                ENDP
+
+                ALIGN
+                END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_ARM_STD/stm32f437xx.sct	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,52 @@
+#! armcc -E
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; 1 MB FLASH (0x100000) + 192 KB SRAM (0x30000) + 64 KB CCBRAM (0x10000)+ 4 KB BKPSRAM
+LR_IROM1 0x08000000 0x100000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0x1AC) (0x30000-0x1AC)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  
+  RW_IRAM2 (0x10000000) (0x10000)  {  ; RW data
+   .ANY (CCMRAM)
+  }
+  
+  RW_IRAM3 0x40024000 4096  {  ; 4 kbytes of Backup SRAM
+   .ANY (BKPSRAM)
+  }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_ARM_STD/sys.cpp	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model, 
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_GCC_ARM/STM32F437xx.ld	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,174 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{ 
+RAM (xrw)        : ORIGIN = 0x200001AC, LENGTH = 192K - 0x1AC /* 0x1AC is to leave room for vectors */
+CCM_RAM (rw)     : ORIGIN = 0x10000000, LENGTH = 64K
+BACKUP_SRAM (rw) : ORIGIN = 0x40024000, LENGTH = 4096
+FLASH (rx)       : ORIGIN = 0x08000000, LENGTH = 1024K
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+    _sidata = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        _sdata = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+        _edata = .;
+
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        _sbss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+        _ebss = .;
+    } > RAM
+
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+    /* Code can explicitly ask for data to be 
+       placed into CCMRAM which will be left
+       uninitialized. 
+    */
+    .CCMRAM (NOLOAD):
+    {
+        Image$$RW_IRAM2$$Base = . ;
+        *(CCMRAM)
+        Image$$RW_IRAM2$$ZI$$Limit = .;
+    } > CCM_RAM
+
+    /* Backup SRAM, requires unlocking before access */
+    .BKPSRAM (NOLOAD):
+    {
+        Image$$RW_IRAM3$$Base = . ;
+        *(BKPSRAM)
+        Image$$RW_IRAM3$$ZI$$Limit = .;
+    } > BACKUP_SRAM
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f437xx.s	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,554 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f437xx.s
+  * @author    MCD Application Team
+  * @version   V2.6.0
+  * @date      04-November-2016
+  * @brief     STM32F437xx Devices vector table for GCC based toolchains.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack     /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+  //bl __libc_init_array
+/* Call the application's entry point.*/
+  //bl  main
+  // Calling the crt0 'cold-start' entry point. There __libc_init_array is called
+  // and when existing hardware_init_hook() and software_init_hook() before
+  // starting main(). software_init_hook() is available and has to be called due
+  // to initializsation when using rtos.
+  bl _start
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */
+  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
+  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */
+  .word     FLASH_IRQHandler                  /* FLASH                        */
+  .word     RCC_IRQHandler                    /* RCC                          */
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */
+  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */
+  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */
+  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */
+  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */
+  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */
+  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */
+  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
+  .word     TIM2_IRQHandler                   /* TIM2                         */
+  .word     TIM3_IRQHandler                   /* TIM3                         */
+  .word     TIM4_IRQHandler                   /* TIM4                         */
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */
+  .word     SPI1_IRQHandler                   /* SPI1                         */
+  .word     SPI2_IRQHandler                   /* SPI2                         */
+  .word     USART1_IRQHandler                 /* USART1                       */
+  .word     USART2_IRQHandler                 /* USART2                       */
+  .word     USART3_IRQHandler                 /* USART3                       */
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */
+  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */
+  .word     FMC_IRQHandler                    /* FMC                          */
+  .word     SDIO_IRQHandler                   /* SDIO                         */
+  .word     TIM5_IRQHandler                   /* TIM5                         */
+  .word     SPI3_IRQHandler                   /* SPI3                         */
+  .word     UART4_IRQHandler                  /* UART4                        */
+  .word     UART5_IRQHandler                  /* UART5                        */
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */
+  .word     TIM7_IRQHandler                   /* TIM7                         */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */
+  .word     ETH_IRQHandler                    /* Ethernet                     */
+  .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */
+  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */
+  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */
+  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */
+  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */
+  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */
+  .word     USART6_IRQHandler                 /* USART6                       */
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */
+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */
+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */
+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */
+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */
+  .word     DCMI_IRQHandler                   /* DCMI                         */
+  .word     CRYP_IRQHandler                   /* CRYP crypto                  */
+  .word     HASH_RNG_IRQHandler               /* Hash and Rng                 */
+  .word     FPU_IRQHandler                    /* FPU                          */
+  .word     UART7_IRQHandler                  /* UART7                        */
+  .word     UART8_IRQHandler                  /* UART8                        */
+  .word     SPI4_IRQHandler                   /* SPI4                         */
+  .word     SPI5_IRQHandler                   /* SPI5                         */
+  .word     SPI6_IRQHandler                   /* SPI6                         */
+  .word     SAI1_IRQHandler                   /* SAI1                         */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     DMA2D_IRQHandler                  /* DMA2D                        */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler
+
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      TAMP_STAMP_IRQHandler
+   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+   .weak      RTC_WKUP_IRQHandler
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream0_IRQHandler
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream1_IRQHandler
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream2_IRQHandler
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream3_IRQHandler
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream4_IRQHandler
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream5_IRQHandler
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream6_IRQHandler
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+   .weak      ADC_IRQHandler
+   .thumb_set ADC_IRQHandler,Default_Handler
+
+   .weak      CAN1_TX_IRQHandler
+   .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX0_IRQHandler
+   .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN1_RX1_IRQHandler
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN1_SCE_IRQHandler
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TIM1_BRK_TIM9_IRQHandler
+   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+
+   .weak      TIM1_UP_TIM10_IRQHandler
+   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+
+   .weak      TIM1_TRG_COM_TIM11_IRQHandler
+   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+
+   .weak      TIM1_CC_IRQHandler
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+   .weak      TIM2_IRQHandler
+   .thumb_set TIM2_IRQHandler,Default_Handler
+
+   .weak      TIM3_IRQHandler
+   .thumb_set TIM3_IRQHandler,Default_Handler
+
+   .weak      TIM4_IRQHandler
+   .thumb_set TIM4_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTC_Alarm_IRQHandler
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+   .weak      OTG_FS_WKUP_IRQHandler
+   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+   .weak      TIM8_BRK_TIM12_IRQHandler
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+   .weak      TIM8_UP_TIM13_IRQHandler
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+   .weak      TIM8_CC_IRQHandler
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream7_IRQHandler
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+   .weak      FMC_IRQHandler
+   .thumb_set FMC_IRQHandler,Default_Handler
+
+   .weak      SDIO_IRQHandler
+   .thumb_set SDIO_IRQHandler,Default_Handler
+
+   .weak      TIM5_IRQHandler
+   .thumb_set TIM5_IRQHandler,Default_Handler
+
+   .weak      SPI3_IRQHandler
+   .thumb_set SPI3_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TIM6_DAC_IRQHandler
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+   .weak      TIM7_IRQHandler
+   .thumb_set TIM7_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream0_IRQHandler
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream1_IRQHandler
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream2_IRQHandler
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream3_IRQHandler
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream4_IRQHandler
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+   .weak      ETH_IRQHandler
+   .thumb_set ETH_IRQHandler,Default_Handler
+
+   .weak      ETH_WKUP_IRQHandler
+   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+   .weak      CAN2_TX_IRQHandler
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX0_IRQHandler
+   .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+
+   .weak      CAN2_RX1_IRQHandler
+   .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+
+   .weak      CAN2_SCE_IRQHandler
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+   .weak      OTG_FS_IRQHandler
+   .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream5_IRQHandler
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream6_IRQHandler
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream7_IRQHandler
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_EP1_OUT_IRQHandler
+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_EP1_IN_IRQHandler
+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_WKUP_IRQHandler
+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_IRQHandler
+   .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+   .weak      DCMI_IRQHandler
+   .thumb_set DCMI_IRQHandler,Default_Handler
+
+   .weak      CRYP_IRQHandler
+   .thumb_set CRYP_IRQHandler,Default_Handler
+
+   .weak      HASH_RNG_IRQHandler
+   .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+   .weak      FPU_IRQHandler
+   .thumb_set FPU_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      SPI5_IRQHandler
+   .thumb_set SPI5_IRQHandler,Default_Handler
+
+   .weak      SPI6_IRQHandler
+   .thumb_set SPI6_IRQHandler,Default_Handler
+
+   .weak      SAI1_IRQHandler
+   .thumb_set SAI1_IRQHandler,Default_Handler
+
+   .weak      DMA2D_IRQHandler
+   .thumb_set DMA2D_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_IAR/startup_stm32f437xx.S	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,688 @@
+;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;* File Name          : startup_stm32f437xx.s
+;* Author             : MCD Application Team
+;* Version            : V2.1.0
+;* Date               : 19-June-2014
+;* Description        : STM32F437xx devices vector table for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* 
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;* 
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog
+        DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
+        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
+        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
+        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
+        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
+        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
+        DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9
+        DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10
+        DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line
+        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12
+        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13
+        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare
+        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     SDIO_IRQHandler                   ; SDIO
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
+        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
+        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
+        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
+        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
+        DCD     ETH_IRQHandler                    ; Ethernet
+        DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line
+        DCD     CAN2_TX_IRQHandler                ; CAN2 TX
+        DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0
+        DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1
+        DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE
+        DCD     OTG_FS_IRQHandler                 ; USB OTG FS
+        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
+        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
+        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
+        DCD     USART6_IRQHandler                 ; USART6
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out
+        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In
+        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI
+        DCD     OTG_HS_IRQHandler                 ; USB OTG HS
+        DCD     DCMI_IRQHandler                   ; DCMI
+        DCD     CRYP_IRQHandler                   ; CRYP crypto
+        DCD     HASH_RNG_IRQHandler               ; Hash and Rng
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     UART7_IRQHandler                  ; UART7
+        DCD     UART8_IRQHandler                  ; UART8
+        DCD     SPI4_IRQHandler                   ; SPI4
+        DCD     SPI5_IRQHandler                   ; SPI5
+        DCD     SPI6_IRQHandler                   ; SPI6
+        DCD     SAI1_IRQHandler                   ; SAI1
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     DMA2D_IRQHandler                  ; DMA2D
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+WWDG_IRQHandler  
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PVD_IRQHandler  
+        B PVD_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TAMP_STAMP_IRQHandler  
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_WKUP_IRQHandler  
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+FLASH_IRQHandler  
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RCC_IRQHandler  
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI0_IRQHandler  
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI1_IRQHandler  
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI2_IRQHandler  
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI4_IRQHandler  
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Stream0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream0_IRQHandler  
+        B DMA1_Stream0_IRQHandler
+
+        PUBWEAK DMA1_Stream1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream1_IRQHandler  
+        B DMA1_Stream1_IRQHandler
+
+        PUBWEAK DMA1_Stream2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream2_IRQHandler  
+        B DMA1_Stream2_IRQHandler
+
+        PUBWEAK DMA1_Stream3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream3_IRQHandler  
+        B DMA1_Stream3_IRQHandler
+
+        PUBWEAK DMA1_Stream4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream4_IRQHandler  
+        B DMA1_Stream4_IRQHandler
+
+        PUBWEAK DMA1_Stream5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream5_IRQHandler  
+        B DMA1_Stream5_IRQHandler
+
+        PUBWEAK DMA1_Stream6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream6_IRQHandler  
+        B DMA1_Stream6_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ADC_IRQHandler  
+        B ADC_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_TX_IRQHandler  
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_RX0_IRQHandler  
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_RX1_IRQHandler  
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_SCE_IRQHandler  
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI9_5_IRQHandler  
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM9_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_BRK_TIM9_IRQHandler  
+        B TIM1_BRK_TIM9_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM10_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_UP_TIM10_IRQHandler  
+        B TIM1_UP_TIM10_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_TRG_COM_TIM11_IRQHandler  
+        B TIM1_TRG_COM_TIM11_IRQHandler
+        
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM1_CC_IRQHandler  
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM2_IRQHandler  
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM3_IRQHandler  
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM4_IRQHandler  
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_EV_IRQHandler  
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_ER_IRQHandler  
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_EV_IRQHandler  
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_ER_IRQHandler  
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler  
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler  
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_IRQHandler  
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART2_IRQHandler  
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART3_IRQHandler  
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI15_10_IRQHandler  
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_Alarm_IRQHandler  
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK OTG_FS_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_FS_WKUP_IRQHandler  
+        B OTG_FS_WKUP_IRQHandler
+      
+        PUBWEAK TIM8_BRK_TIM12_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_BRK_TIM12_IRQHandler  
+        B TIM8_BRK_TIM12_IRQHandler
+
+        PUBWEAK TIM8_UP_TIM13_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_UP_TIM13_IRQHandler  
+        B TIM8_UP_TIM13_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_TRG_COM_TIM14_IRQHandler  
+        B TIM8_TRG_COM_TIM14_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM8_CC_IRQHandler  
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK DMA1_Stream7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Stream7_IRQHandler  
+        B DMA1_Stream7_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+FMC_IRQHandler  
+        B FMC_IRQHandler
+
+        PUBWEAK SDIO_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SDIO_IRQHandler  
+        B SDIO_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM5_IRQHandler  
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI3_IRQHandler  
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART4_IRQHandler  
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART5_IRQHandler  
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM6_DAC_IRQHandler  
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM7_IRQHandler  
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Stream0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream0_IRQHandler  
+        B DMA2_Stream0_IRQHandler
+
+        PUBWEAK DMA2_Stream1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream1_IRQHandler  
+        B DMA2_Stream1_IRQHandler
+
+        PUBWEAK DMA2_Stream2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream2_IRQHandler  
+        B DMA2_Stream2_IRQHandler
+
+        PUBWEAK DMA2_Stream3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream3_IRQHandler  
+        B DMA2_Stream3_IRQHandler
+
+        PUBWEAK DMA2_Stream4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream4_IRQHandler  
+        B DMA2_Stream4_IRQHandler
+
+        PUBWEAK ETH_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ETH_IRQHandler  
+        B ETH_IRQHandler
+
+        PUBWEAK ETH_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ETH_WKUP_IRQHandler  
+        B ETH_WKUP_IRQHandler
+
+        PUBWEAK CAN2_TX_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_TX_IRQHandler  
+        B CAN2_TX_IRQHandler
+
+        PUBWEAK CAN2_RX0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_RX0_IRQHandler  
+        B CAN2_RX0_IRQHandler
+
+        PUBWEAK CAN2_RX1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_RX1_IRQHandler  
+        B CAN2_RX1_IRQHandler
+
+        PUBWEAK CAN2_SCE_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_SCE_IRQHandler  
+        B CAN2_SCE_IRQHandler
+
+        PUBWEAK OTG_FS_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_FS_IRQHandler  
+        B OTG_FS_IRQHandler
+
+        PUBWEAK DMA2_Stream5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream5_IRQHandler  
+        B DMA2_Stream5_IRQHandler
+
+        PUBWEAK DMA2_Stream6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream6_IRQHandler  
+        B DMA2_Stream6_IRQHandler
+
+        PUBWEAK DMA2_Stream7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Stream7_IRQHandler  
+        B DMA2_Stream7_IRQHandler
+
+        PUBWEAK USART6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART6_IRQHandler  
+        B USART6_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C3_EV_IRQHandler  
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C3_ER_IRQHandler  
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_HS_EP1_OUT_IRQHandler  
+        B OTG_HS_EP1_OUT_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_IN_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_HS_EP1_IN_IRQHandler  
+        B OTG_HS_EP1_IN_IRQHandler
+
+        PUBWEAK OTG_HS_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_HS_WKUP_IRQHandler  
+        B OTG_HS_WKUP_IRQHandler
+
+        PUBWEAK OTG_HS_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+OTG_HS_IRQHandler  
+        B OTG_HS_IRQHandler
+
+        PUBWEAK DCMI_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DCMI_IRQHandler  
+        B DCMI_IRQHandler
+
+        PUBWEAK CRYP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CRYP_IRQHandler  
+        B CRYP_IRQHandler
+
+        PUBWEAK HASH_RNG_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HASH_RNG_IRQHandler  
+        B HASH_RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+FPU_IRQHandler  
+        B FPU_IRQHandler
+
+        PUBWEAK UART7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART7_IRQHandler 
+        B UART7_IRQHandler  
+
+        PUBWEAK UART8_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART8_IRQHandler
+        B UART8_IRQHandler
+
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI4_IRQHandler
+        B SPI4_IRQHandler
+
+        PUBWEAK SPI5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI5_IRQHandler
+        B SPI5_IRQHandler
+
+        PUBWEAK SPI6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI6_IRQHandler 
+        B SPI6_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SAI1_IRQHandler  
+        B SAI1_IRQHandler
+
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2D_IRQHandler 
+        B DMA2D_IRQHandler
+
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_IAR/stm32f437xx.icf	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,44 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x080FFFFF;
+define symbol __ICFEDIT_region_NVIC_start__    = 0x20000000;
+define symbol __ICFEDIT_region_NVIC_end__      = 0x200001AF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x200001B0;
+define symbol __ICFEDIT_region_RAM_end__       = 0x2002FFFF;
+define symbol __ICFEDIT_region_CCMRAM_start__  = 0x10000000;
+define symbol __ICFEDIT_region_CCMRAM_end__    = 0x1000FFFF;
+define symbol __ICFEDIT_region_BKPSRAM_start__ = 0x40024000;
+define symbol __ICFEDIT_region_BKPSRAM_end__   = 0x40024FFF;
+/*-Sizes-*/
+/*Heap 1/2 of ram and ISR stack 4 kbytes*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x18000;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region CCMRAM_region   = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
+define region BKPSRAM_region  = mem:[from __ICFEDIT_region_BKPSRAM_start__ to __ICFEDIT_region_BKPSRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+do not initialize  { section CCMRAM };
+do not initialize  { section BKPSRAM };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+place in CCMRAM_region    { section CCMRAM };
+place in BKPSRAM_region    { section BKPSRAM };

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/cmsis.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32f4xx.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/cmsis_nvic.c	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */ 
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS   (0x20000000)  // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000)  // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    uint32_t *vectors = (uint32_t *)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+        for (i=0; i<NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/cmsis_nvic.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */ 
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32F437VG
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 91 vectors = 364 bytes from 0x40 to 0x1AB
+// Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
+#define NVIC_NUM_VECTORS      107
+#define NVIC_USER_IRQ_OFFSET  16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/hal_tick.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,66 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.h
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32f4xx.h"
+#include "cmsis_nvic.h"
+   
+#define TIM_MST      TIM5
+#define TIM_MST_IRQ  TIM5_IRQn
+#define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+
+#define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
+
+#define TIM_MST_16BIT  0 // 1=16-bit timer, 0=32-bit timer
+
+#define TIM_MST_PCLK  1 // Select the peripheral clock number (1 or 2)
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+void HAL_SuspendTick(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f437xx.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,16964 @@
+/**
+  ******************************************************************************
+  * @file    stm32f437xx.h
+  * @author  MCD Application Team
+  * @version V2.6.0
+  * @date    04-November-2016
+  * @brief   CMSIS STM32F437xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - peripherals registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32f437xx
+  * @{
+  */
+    
+#ifndef __STM32F437xx_H
+#define __STM32F437xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
+  */
+#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
+#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#endif /* __FPU_PRESENT */
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+typedef enum
+{
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
+  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
+  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
+  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
+  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
+  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
+  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
+  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
+  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
+  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
+  DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
+  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
+  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
+  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
+  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
+  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
+  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
+  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
+  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
+  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
+  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
+  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
+  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
+  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
+  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
+  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
+  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
+                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/** 
+  * @brief Controller Area Network TxMailBox 
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FIFOMailBox 
+  */
+  
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FilterRegister 
+  */
+  
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/** 
+  * @brief Controller Area Network 
+  */
+  
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
+  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
+  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
+  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
+} CRC_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
+  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
+  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
+  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DCMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/** 
+  * @brief DMA2D Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/** 
+  * @brief Ethernet MAC
+  */
+
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACFFR;
+  __IO uint32_t MACHTHR;
+  __IO uint32_t MACHTLR;
+  __IO uint32_t MACMIIAR;
+  __IO uint32_t MACMIIDR;
+  __IO uint32_t MACFCR;
+  __IO uint32_t MACVLANTR;             /*    8 */
+  uint32_t      RESERVED0[2];
+  __IO uint32_t MACRWUFFR;             /*   11 */
+  __IO uint32_t MACPMTCSR;
+  uint32_t      RESERVED1;
+  __IO uint32_t MACDBGR;
+  __IO uint32_t MACSR;                 /*   15 */
+  __IO uint32_t MACIMR;
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;               /*   24 */
+  uint32_t      RESERVED2[40];
+  __IO uint32_t MMCCR;                 /*   65 */
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;               /*   69 */
+  uint32_t      RESERVED3[14];
+  __IO uint32_t MMCTGFSCCR;            /*   84 */
+  __IO uint32_t MMCTGFMSCCR;
+  uint32_t      RESERVED4[5];
+  __IO uint32_t MMCTGFCR;
+  uint32_t      RESERVED5[10];
+  __IO uint32_t MMCRFCECR;
+  __IO uint32_t MMCRFAECR;
+  uint32_t      RESERVED6[10];
+  __IO uint32_t MMCRGUFCR;
+  uint32_t      RESERVED7[334];
+  __IO uint32_t PTPTSCR;
+  __IO uint32_t PTPSSIR;
+  __IO uint32_t PTPTSHR;
+  __IO uint32_t PTPTSLR;
+  __IO uint32_t PTPTSHUR;
+  __IO uint32_t PTPTSLUR;
+  __IO uint32_t PTPTSAR;
+  __IO uint32_t PTPTTHR;
+  __IO uint32_t PTPTTLR;
+  __IO uint32_t RESERVED8;
+  __IO uint32_t PTPTSSR;
+  uint32_t      RESERVED9[565];
+  __IO uint32_t DMABMR;
+  __IO uint32_t DMATPDR;
+  __IO uint32_t DMARPDR;
+  __IO uint32_t DMARDLAR;
+  __IO uint32_t DMATDLAR;
+  __IO uint32_t DMASR;
+  __IO uint32_t DMAOMR;
+  __IO uint32_t DMAIER;
+  __IO uint32_t DMAMFBOCR;
+  __IO uint32_t DMARSWTR;
+  uint32_t      RESERVED10[8];
+  __IO uint32_t DMACHTDR;
+  __IO uint32_t DMACHRDR;
+  __IO uint32_t DMACHTBAR;
+  __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
+  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
+  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
+  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
+  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
+  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
+  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
+  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
+  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+/** 
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef; 
+
+/** 
+  * @brief Flexible Memory Controller Bank1E
+  */
+  
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+/** 
+  * @brief Flexible Memory Controller Bank2
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
+  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */
+  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */
+  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
+  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
+  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
+  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
+} FMC_Bank2_3_TypeDef;
+
+/** 
+  * @brief Flexible Memory Controller Bank4
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
+  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
+  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
+  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
+  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
+} FMC_Bank4_TypeDef;
+
+/** 
+  * @brief Flexible Memory Controller Bank5_6
+  */
+  
+typedef struct
+{
+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
+  __IO uint32_t SDCMR;          /*!< SDRAM Command Mode register,   Address offset: 0x150        */
+  __IO uint32_t SDRTR;          /*!< SDRAM Refresh Timer register,  Address offset: 0x154        */
+  __IO uint32_t SDSR;           /*!< SDRAM Status register,         Address offset: 0x158        */
+} FMC_Bank5_6_TypeDef;
+
+/** 
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/** 
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */
+  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
+} SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
+  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
+  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
+  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
+  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
+  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
+  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
+  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
+  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */
+} I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/** 
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
+  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
+  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
+  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
+  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
+  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
+  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
+  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
+  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
+  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
+  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
+  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
+  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
+  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
+  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
+  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
+  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
+  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
+  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
+  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
+  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
+  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */
+  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
+  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
+  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
+  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
+  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
+  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
+  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
+  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
+  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
+  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
+  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
+  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
+  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
+  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
+  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
+  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
+  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
+  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
+  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
+  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
+  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
+  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
+  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
+  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
+  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
+  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
+  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
+  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
+  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
+  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
+  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
+  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
+  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
+  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
+  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
+  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
+  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
+  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
+} RTC_TypeDef;
+
+/** 
+  * @brief Serial Audio Interface
+  */
+  
+typedef struct
+{
+  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/** 
+  * @brief SD host Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */
+  __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */
+  __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
+  __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
+  __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
+  __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
+  __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */
+  __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
+  __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */
+  __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
+  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
+  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
+  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
+  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
+  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/** 
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
+} TIM_TypeDef;
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+ 
+typedef struct
+{
+  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
+  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
+  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
+  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
+  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
+  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/** 
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/** 
+  * @brief Crypto Processor
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */
+  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */
+  __IO uint32_t DR;         /*!< CRYP data input register,                                 Address offset: 0x08 */
+  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */
+  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */
+  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */
+  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */
+  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */
+  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */
+  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */
+  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */
+  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */
+  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */
+  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */
+  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */
+  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */
+  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */
+  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */
+  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */
+  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */
+  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */
+  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */
+  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */
+  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */
+  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */
+  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */
+  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */
+  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */
+  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */
+  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */
+  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */
+  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */
+  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */
+  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */
+  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */
+  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */
+} CRYP_TypeDef;
+
+/** 
+  * @brief HASH
+  */
+  
+typedef struct 
+{
+  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
+  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
+  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
+  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
+  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
+  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
+       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
+  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
+} HASH_TypeDef;
+
+/** 
+  * @brief HASH_DIGEST
+  */
+
+typedef struct 
+{
+  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */ 
+} HASH_DIGEST_TypeDef;
+
+/** 
+  * @brief RNG
+  */
+  
+typedef struct 
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/** 
+  * @brief USB_OTG_Core_Registers
+  */
+typedef struct
+{
+  __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */
+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
+  uint32_t  Reserved40[48];           /*!< Reserved                                0x40-0xFF */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */
+} USB_OTG_GlobalTypeDef;
+
+/** 
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
+  uint32_t  Reserved20;          /*!< Reserved                     820h */
+  uint32_t Reserved9;            /*!< Reserved                     824h */
+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
+} USB_OTG_DeviceTypeDef;
+
+/** 
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct 
+{
+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/** 
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct 
+{
+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
+} USB_OTG_HostTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
+  uint32_t Reserved[2];           /*!< Reserved                                      */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define FLASH_BASE            0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region                         */
+#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
+#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                              */
+#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */
+#define SRAM3_BASE            0x20020000U /*!< SRAM3(64 KB) base address in the alias region                              */
+#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define FMC_R_BASE            0xA0000000U /*!< FMC registers base address                                                 */
+#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                          */
+#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                           */
+#define SRAM3_BB_BASE         0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region                           */
+#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */
+#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
+#define FLASH_END             0x081FFFFFU /*!< FLASH end address                                                          */
+#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address                                                   */
+
+/* Legacy defines */
+#define SRAM_BASE             SRAM1_BASE
+#define SRAM_BB_BASE          SRAM1_BB_BASE
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
+#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
+#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
+#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)
+#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)
+#define ADC_BASE              (APB2PERIPH_BASE + 0x2300U)
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
+#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)
+#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)
+#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)
+#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)
+#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)
+#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)
+#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)
+#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)
+#define ETH_MAC_BASE          (ETH_BASE)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)
+#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)
+#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000U)
+#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400U)
+#define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710U)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
+#define FMC_Bank2_3_R_BASE    (FMC_R_BASE + 0x0060U)
+#define FMC_Bank4_R_BASE      (FMC_R_BASE + 0x00A0U)
+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)
+
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE           0xE0042000U
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE               0x40040000U
+#define USB_OTG_FS_PERIPH_BASE               0x50000000U
+
+#define USB_OTG_GLOBAL_BASE                  0x000U
+#define USB_OTG_DEVICE_BASE                  0x800U
+#define USB_OTG_IN_ENDPOINT_BASE             0x900U
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U
+#define USB_OTG_EP_REG_SIZE                  0x20U
+#define USB_OTG_HOST_BASE                    0x400U
+#define USB_OTG_HOST_PORT_BASE               0x440U
+#define USB_OTG_HOST_CHANNEL_BASE            0x500U
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20U
+#define USB_OTG_PCGCCTL_BASE                 0xE00U
+#define USB_OTG_FIFO_BASE                    0x1000U
+#define USB_OTG_FIFO_SIZE                    0x1000U
+
+#define UID_BASE                     0x1FFF7A10U           /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE               0x1FFF7A22U           /*!< FLASH Size register base address       */
+#define PACKAGE_BASE                 0x1FFF7BF0U           /*!< Package size register base address     */
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
+#define UART7               ((USART_TypeDef *) UART7_BASE)
+#define UART8               ((USART_TypeDef *) UART8_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
+#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
+#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
+#define HASH                ((HASH_TypeDef *) HASH_BASE)
+#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_3         ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
+#define FMC_Bank4           ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
+#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+  
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for ADC_SR register  ********************/
+#define ADC_SR_AWD_Pos            (0U)                                         
+#define ADC_SR_AWD_Msk            (0x1U << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */
+#define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos            (1U)                                         
+#define ADC_SR_EOC_Msk            (0x1U << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */
+#define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */
+#define ADC_SR_JEOC_Pos           (2U)                                         
+#define ADC_SR_JEOC_Msk           (0x1U << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */
+#define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos          (3U)                                         
+#define ADC_SR_JSTRT_Msk          (0x1U << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */
+#define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos           (4U)                                         
+#define ADC_SR_STRT_Msk           (0x1U << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */
+#define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos            (5U)                                         
+#define ADC_SR_OVR_Msk            (0x1U << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */
+#define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */
+
+/*******************  Bit definition for ADC_CR1 register  ********************/
+#define ADC_CR1_AWDCH_Pos         (0U)                                         
+#define ADC_CR1_AWDCH_Msk         (0x1FU << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */
+#define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0           (0x01U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1           (0x02U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2           (0x04U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3           (0x08U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4           (0x10U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos         (5U)                                         
+#define ADC_CR1_EOCIE_Msk         (0x1U << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */
+#define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos         (6U)                                         
+#define ADC_CR1_AWDIE_Msk         (0x1U << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */
+#define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos        (7U)                                         
+#define ADC_CR1_JEOCIE_Msk        (0x1U << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos          (8U)                                         
+#define ADC_CR1_SCAN_Msk          (0x1U << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */
+#define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos        (9U)                                         
+#define ADC_CR1_AWDSGL_Msk        (0x1U << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos         (10U)                                        
+#define ADC_CR1_JAUTO_Msk         (0x1U << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */
+#define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos        (11U)                                        
+#define ADC_CR1_DISCEN_Msk        (0x1U << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */
+#define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos       (12U)                                        
+#define ADC_CR1_JDISCEN_Msk       (0x1U << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos       (13U)                                        
+#define ADC_CR1_DISCNUM_Msk       (0x7U << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0         (0x1U << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1         (0x2U << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2         (0x4U << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos        (22U)                                        
+#define ADC_CR1_JAWDEN_Msk        (0x1U << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos         (23U)                                        
+#define ADC_CR1_AWDEN_Msk         (0x1U << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */
+#define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos           (24U)                                        
+#define ADC_CR1_RES_Msk           (0x3U << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */
+#define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0             (0x1U << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */
+#define ADC_CR1_RES_1             (0x2U << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos         (26U)                                        
+#define ADC_CR1_OVRIE_Msk         (0x1U << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */
+#define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */
+  
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define ADC_CR2_ADON_Pos          (0U)                                         
+#define ADC_CR2_ADON_Msk          (0x1U << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */
+#define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos          (1U)                                         
+#define ADC_CR2_CONT_Msk          (0x1U << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */
+#define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos           (8U)                                         
+#define ADC_CR2_DMA_Msk           (0x1U << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */
+#define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos           (9U)                                         
+#define ADC_CR2_DDS_Msk           (0x1U << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */
+#define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos          (10U)                                        
+#define ADC_CR2_EOCS_Msk          (0x1U << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */
+#define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos         (11U)                                        
+#define ADC_CR2_ALIGN_Msk         (0x1U << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */
+#define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos       (16U)                                        
+#define ADC_CR2_JEXTSEL_Msk       (0xFU << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0         (0x1U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1         (0x2U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2         (0x4U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3         (0x8U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos        (20U)                                        
+#define ADC_CR2_JEXTEN_Msk        (0x3U << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0          (0x1U << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1          (0x2U << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos      (22U)                                        
+#define ADC_CR2_JSWSTART_Msk      (0x1U << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos        (24U)                                        
+#define ADC_CR2_EXTSEL_Msk        (0xFU << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0          (0x1U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1          (0x2U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2          (0x4U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3          (0x8U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos         (28U)                                        
+#define ADC_CR2_EXTEN_Msk         (0x3U << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */
+#define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0           (0x1U << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1           (0x2U << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos       (30U)                                        
+#define ADC_CR2_SWSTART_Msk       (0x1U << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */
+#define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */
+
+/******************  Bit definition for ADC_SMPR1 register  *******************/
+#define ADC_SMPR1_SMP10_Pos       (0U)                                         
+#define ADC_SMPR1_SMP10_Msk       (0x7U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0         (0x1U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1         (0x2U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2         (0x4U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos       (3U)                                         
+#define ADC_SMPR1_SMP11_Msk       (0x7U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0         (0x1U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1         (0x2U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2         (0x4U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos       (6U)                                         
+#define ADC_SMPR1_SMP12_Msk       (0x7U << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0         (0x1U << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1         (0x2U << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2         (0x4U << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos       (9U)                                         
+#define ADC_SMPR1_SMP13_Msk       (0x7U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0         (0x1U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1         (0x2U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2         (0x4U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos       (12U)                                        
+#define ADC_SMPR1_SMP14_Msk       (0x7U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0         (0x1U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1         (0x2U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2         (0x4U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos       (15U)                                        
+#define ADC_SMPR1_SMP15_Msk       (0x7U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0         (0x1U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1         (0x2U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2         (0x4U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos       (18U)                                        
+#define ADC_SMPR1_SMP16_Msk       (0x7U << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0         (0x1U << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1         (0x2U << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2         (0x4U << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos       (21U)                                        
+#define ADC_SMPR1_SMP17_Msk       (0x7U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0         (0x1U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1         (0x2U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2         (0x4U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos       (24U)                                        
+#define ADC_SMPR1_SMP18_Msk       (0x7U << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0         (0x1U << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1         (0x2U << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2         (0x4U << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */
+
+/******************  Bit definition for ADC_SMPR2 register  *******************/
+#define ADC_SMPR2_SMP0_Pos        (0U)                                         
+#define ADC_SMPR2_SMP0_Msk        (0x7U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0          (0x1U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1          (0x2U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2          (0x4U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos        (3U)                                         
+#define ADC_SMPR2_SMP1_Msk        (0x7U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0          (0x1U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1          (0x2U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2          (0x4U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos        (6U)                                         
+#define ADC_SMPR2_SMP2_Msk        (0x7U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0          (0x1U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1          (0x2U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2          (0x4U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos        (9U)                                         
+#define ADC_SMPR2_SMP3_Msk        (0x7U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0          (0x1U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1          (0x2U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2          (0x4U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos        (12U)                                        
+#define ADC_SMPR2_SMP4_Msk        (0x7U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0          (0x1U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1          (0x2U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2          (0x4U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos        (15U)                                        
+#define ADC_SMPR2_SMP5_Msk        (0x7U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0          (0x1U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1          (0x2U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2          (0x4U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos        (18U)                                        
+#define ADC_SMPR2_SMP6_Msk        (0x7U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0          (0x1U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1          (0x2U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2          (0x4U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos        (21U)                                        
+#define ADC_SMPR2_SMP7_Msk        (0x7U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0          (0x1U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1          (0x2U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2          (0x4U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos        (24U)                                        
+#define ADC_SMPR2_SMP8_Msk        (0x7U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0          (0x1U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1          (0x2U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2          (0x4U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos        (27U)                                        
+#define ADC_SMPR2_SMP9_Msk        (0x7U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0          (0x1U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1          (0x2U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2          (0x4U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */
+
+/******************  Bit definition for ADC_JOFR1 register  *******************/
+#define ADC_JOFR1_JOFFSET1_Pos    (0U)                                         
+#define ADC_JOFR1_JOFFSET1_Msk    (0xFFFU << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFR2 register  *******************/
+#define ADC_JOFR2_JOFFSET2_Pos    (0U)                                         
+#define ADC_JOFR2_JOFFSET2_Msk    (0xFFFU << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFR3 register  *******************/
+#define ADC_JOFR3_JOFFSET3_Pos    (0U)                                         
+#define ADC_JOFR3_JOFFSET3_Msk    (0xFFFU << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFR4 register  *******************/
+#define ADC_JOFR4_JOFFSET4_Pos    (0U)                                         
+#define ADC_JOFR4_JOFFSET4_Msk    (0xFFFU << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define ADC_HTR_HT_Pos            (0U)                                         
+#define ADC_HTR_HT_Msk            (0xFFFU << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */
+#define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define ADC_LTR_LT_Pos            (0U)                                         
+#define ADC_LTR_LT_Msk            (0xFFFU << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */
+#define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_SQR1 register  *******************/
+#define ADC_SQR1_SQ13_Pos         (0U)                                         
+#define ADC_SQR1_SQ13_Msk         (0x1FU << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */
+#define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0           (0x01U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1           (0x02U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2           (0x04U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3           (0x08U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4           (0x10U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos         (5U)                                         
+#define ADC_SQR1_SQ14_Msk         (0x1FU << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0           (0x01U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1           (0x02U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2           (0x04U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3           (0x08U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4           (0x10U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos         (10U)                                        
+#define ADC_SQR1_SQ15_Msk         (0x1FU << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0           (0x01U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1           (0x02U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2           (0x04U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3           (0x08U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4           (0x10U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos         (15U)                                        
+#define ADC_SQR1_SQ16_Msk         (0x1FU << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0           (0x01U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1           (0x02U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2           (0x04U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3           (0x08U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4           (0x10U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos            (20U)                                        
+#define ADC_SQR1_L_Msk            (0xFU << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */
+#define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0              (0x1U << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */
+#define ADC_SQR1_L_1              (0x2U << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */
+#define ADC_SQR1_L_2              (0x4U << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */
+#define ADC_SQR1_L_3              (0x8U << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */
+
+/*******************  Bit definition for ADC_SQR2 register  *******************/
+#define ADC_SQR2_SQ7_Pos          (0U)                                         
+#define ADC_SQR2_SQ7_Msk          (0x1FU << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */
+#define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0            (0x01U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1            (0x02U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2            (0x04U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3            (0x08U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4            (0x10U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos          (5U)                                         
+#define ADC_SQR2_SQ8_Msk          (0x1FU << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0            (0x01U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1            (0x02U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2            (0x04U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3            (0x08U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4            (0x10U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos          (10U)                                        
+#define ADC_SQR2_SQ9_Msk          (0x1FU << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0            (0x01U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1            (0x02U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2            (0x04U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3            (0x08U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4            (0x10U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos         (15U)                                        
+#define ADC_SQR2_SQ10_Msk         (0x1FU << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0           (0x01U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1           (0x02U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2           (0x04U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3           (0x08U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4           (0x10U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos         (20U)                                        
+#define ADC_SQR2_SQ11_Msk         (0x1FU << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0           (0x01U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1           (0x02U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2           (0x04U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3           (0x08U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4           (0x10U << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos         (25U)                                        
+#define ADC_SQR2_SQ12_Msk         (0x1FU << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0           (0x01U << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1           (0x02U << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2           (0x04U << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3           (0x08U << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4           (0x10U << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */
+
+/*******************  Bit definition for ADC_SQR3 register  *******************/
+#define ADC_SQR3_SQ1_Pos          (0U)                                         
+#define ADC_SQR3_SQ1_Msk          (0x1FU << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */
+#define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0            (0x01U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1            (0x02U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2            (0x04U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3            (0x08U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4            (0x10U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos          (5U)                                         
+#define ADC_SQR3_SQ2_Msk          (0x1FU << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0            (0x01U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1            (0x02U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2            (0x04U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3            (0x08U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4            (0x10U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos          (10U)                                        
+#define ADC_SQR3_SQ3_Msk          (0x1FU << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0            (0x01U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1            (0x02U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2            (0x04U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3            (0x08U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4            (0x10U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos          (15U)                                        
+#define ADC_SQR3_SQ4_Msk          (0x1FU << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0            (0x01U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1            (0x02U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2            (0x04U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3            (0x08U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4            (0x10U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos          (20U)                                        
+#define ADC_SQR3_SQ5_Msk          (0x1FU << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0            (0x01U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1            (0x02U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2            (0x04U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3            (0x08U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4            (0x10U << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos          (25U)                                        
+#define ADC_SQR3_SQ6_Msk          (0x1FU << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0            (0x01U << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1            (0x02U << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2            (0x04U << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3            (0x08U << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4            (0x10U << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */
+
+/*******************  Bit definition for ADC_JSQR register  *******************/
+#define ADC_JSQR_JSQ1_Pos         (0U)                                         
+#define ADC_JSQR_JSQ1_Msk         (0x1FU << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define ADC_JSQR_JSQ1_0           (0x01U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1           (0x02U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2           (0x04U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3           (0x08U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4           (0x10U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos         (5U)                                         
+#define ADC_JSQR_JSQ2_Msk         (0x1FU << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0           (0x01U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1           (0x02U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2           (0x04U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3           (0x08U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4           (0x10U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos         (10U)                                        
+#define ADC_JSQR_JSQ3_Msk         (0x1FU << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0           (0x01U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1           (0x02U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2           (0x04U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3           (0x08U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4           (0x10U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos         (15U)                                        
+#define ADC_JSQR_JSQ4_Msk         (0x1FU << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0           (0x01U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1           (0x02U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2           (0x04U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3           (0x08U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4           (0x10U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos           (20U)                                        
+#define ADC_JSQR_JL_Msk           (0x3U << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */
+#define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0             (0x1U << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */
+#define ADC_JSQR_JL_1             (0x2U << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */
+
+/*******************  Bit definition for ADC_JDR1 register  *******************/
+#define ADC_JDR1_JDATA_Pos        (0U)                                         
+#define ADC_JDR1_JDATA_Msk        (0xFFFFU << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR2 register  *******************/
+#define ADC_JDR2_JDATA_Pos        (0U)                                         
+#define ADC_JDR2_JDATA_Msk        (0xFFFFU << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR3 register  *******************/
+#define ADC_JDR3_JDATA_Pos        (0U)                                         
+#define ADC_JDR3_JDATA_Msk        (0xFFFFU << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR4 register  *******************/
+#define ADC_JDR4_JDATA_Pos        (0U)                                         
+#define ADC_JDR4_JDATA_Msk        (0xFFFFU << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_DATA_Pos           (0U)                                         
+#define ADC_DR_DATA_Msk           (0xFFFFU << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */
+#define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos       (16U)                                        
+#define ADC_DR_ADC2DATA_Msk       (0xFFFFU << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */
+
+/*******************  Bit definition for ADC_CSR register  ********************/
+#define ADC_CSR_AWD1_Pos          (0U)                                         
+#define ADC_CSR_AWD1_Msk          (0x1U << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */
+#define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos          (1U)                                         
+#define ADC_CSR_EOC1_Msk          (0x1U << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */
+#define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos         (2U)                                         
+#define ADC_CSR_JEOC1_Msk         (0x1U << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */
+#define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos        (3U)                                         
+#define ADC_CSR_JSTRT1_Msk        (0x1U << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos         (4U)                                         
+#define ADC_CSR_STRT1_Msk         (0x1U << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */
+#define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos          (5U)                                         
+#define ADC_CSR_OVR1_Msk          (0x1U << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */
+#define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */
+#define ADC_CSR_AWD2_Pos          (8U)                                         
+#define ADC_CSR_AWD2_Msk          (0x1U << ADC_CSR_AWD2_Pos)                   /*!< 0x00000100 */
+#define ADC_CSR_AWD2              ADC_CSR_AWD2_Msk                             /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2_Pos          (9U)                                         
+#define ADC_CSR_EOC2_Msk          (0x1U << ADC_CSR_EOC2_Pos)                   /*!< 0x00000200 */
+#define ADC_CSR_EOC2              ADC_CSR_EOC2_Msk                             /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2_Pos         (10U)                                        
+#define ADC_CSR_JEOC2_Msk         (0x1U << ADC_CSR_JEOC2_Pos)                  /*!< 0x00000400 */
+#define ADC_CSR_JEOC2             ADC_CSR_JEOC2_Msk                            /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2_Pos        (11U)                                        
+#define ADC_CSR_JSTRT2_Msk        (0x1U << ADC_CSR_JSTRT2_Pos)                 /*!< 0x00000800 */
+#define ADC_CSR_JSTRT2            ADC_CSR_JSTRT2_Msk                           /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2_Pos         (12U)                                        
+#define ADC_CSR_STRT2_Msk         (0x1U << ADC_CSR_STRT2_Pos)                  /*!< 0x00001000 */
+#define ADC_CSR_STRT2             ADC_CSR_STRT2_Msk                            /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2_Pos          (13U)                                        
+#define ADC_CSR_OVR2_Msk          (0x1U << ADC_CSR_OVR2_Pos)                   /*!< 0x00002000 */
+#define ADC_CSR_OVR2              ADC_CSR_OVR2_Msk                             /*!<ADC2 DMA overrun  flag */
+#define ADC_CSR_AWD3_Pos          (16U)                                        
+#define ADC_CSR_AWD3_Msk          (0x1U << ADC_CSR_AWD3_Pos)                   /*!< 0x00010000 */
+#define ADC_CSR_AWD3              ADC_CSR_AWD3_Msk                             /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3_Pos          (17U)                                        
+#define ADC_CSR_EOC3_Msk          (0x1U << ADC_CSR_EOC3_Pos)                   /*!< 0x00020000 */
+#define ADC_CSR_EOC3              ADC_CSR_EOC3_Msk                             /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3_Pos         (18U)                                        
+#define ADC_CSR_JEOC3_Msk         (0x1U << ADC_CSR_JEOC3_Pos)                  /*!< 0x00040000 */
+#define ADC_CSR_JEOC3             ADC_CSR_JEOC3_Msk                            /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3_Pos        (19U)                                        
+#define ADC_CSR_JSTRT3_Msk        (0x1U << ADC_CSR_JSTRT3_Pos)                 /*!< 0x00080000 */
+#define ADC_CSR_JSTRT3            ADC_CSR_JSTRT3_Msk                           /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3_Pos         (20U)                                        
+#define ADC_CSR_STRT3_Msk         (0x1U << ADC_CSR_STRT3_Pos)                  /*!< 0x00100000 */
+#define ADC_CSR_STRT3             ADC_CSR_STRT3_Msk                            /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3_Pos          (21U)                                        
+#define ADC_CSR_OVR3_Msk          (0x1U << ADC_CSR_OVR3_Pos)                   /*!< 0x00200000 */
+#define ADC_CSR_OVR3              ADC_CSR_OVR3_Msk                             /*!<ADC3 DMA overrun  flag */
+
+/* Legacy defines */
+#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
+#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
+#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define ADC_CCR_MULTI_Pos         (0U)                                         
+#define ADC_CCR_MULTI_Msk         (0x1FU << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */
+#define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define ADC_CCR_MULTI_0           (0x01U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1           (0x02U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2           (0x04U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3           (0x08U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4           (0x10U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos         (8U)                                         
+#define ADC_CCR_DELAY_Msk         (0xFU << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */
+#define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define ADC_CCR_DELAY_0           (0x1U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1           (0x2U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2           (0x4U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3           (0x8U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos           (13U)                                        
+#define ADC_CCR_DDS_Msk           (0x1U << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */
+#define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos           (14U)                                        
+#define ADC_CCR_DMA_Msk           (0x3U << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */
+#define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define ADC_CCR_DMA_0             (0x1U << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */
+#define ADC_CCR_DMA_1             (0x2U << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos        (16U)                                        
+#define ADC_CCR_ADCPRE_Msk        (0x3U << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define ADC_CCR_ADCPRE_0          (0x1U << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1          (0x2U << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos         (22U)                                        
+#define ADC_CCR_VBATE_Msk         (0x1U << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */
+#define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos       (23U)                                        
+#define ADC_CCR_TSVREFE_Msk       (0x1U << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */
+
+/*******************  Bit definition for ADC_CDR register  ********************/
+#define ADC_CDR_DATA1_Pos         (0U)                                         
+#define ADC_CDR_DATA1_Msk         (0xFFFFU << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos         (16U)                                        
+#define ADC_CDR_DATA2_Msk         (0xFFFFU << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define CAN_MCR_INRQ_Pos       (0U)                                            
+#define CAN_MCR_INRQ_Msk       (0x1U << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
+#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos      (1U)                                            
+#define CAN_MCR_SLEEP_Msk      (0x1U << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
+#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos       (2U)                                            
+#define CAN_MCR_TXFP_Msk       (0x1U << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
+#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos       (3U)                                            
+#define CAN_MCR_RFLM_Msk       (0x1U << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
+#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos       (4U)                                            
+#define CAN_MCR_NART_Msk       (0x1U << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
+#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos       (5U)                                            
+#define CAN_MCR_AWUM_Msk       (0x1U << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
+#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos       (6U)                                            
+#define CAN_MCR_ABOM_Msk       (0x1U << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
+#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos       (7U)                                            
+#define CAN_MCR_TTCM_Msk       (0x1U << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
+#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos      (15U)                                           
+#define CAN_MCR_RESET_Msk      (0x1U << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
+#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
+#define CAN_MCR_DBF_Pos        (16U)                                           
+#define CAN_MCR_DBF_Msk        (0x1U << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */
+#define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define CAN_MSR_INAK_Pos       (0U)                                            
+#define CAN_MSR_INAK_Msk       (0x1U << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
+#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos       (1U)                                            
+#define CAN_MSR_SLAK_Msk       (0x1U << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
+#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos       (2U)                                            
+#define CAN_MSR_ERRI_Msk       (0x1U << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
+#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos       (3U)                                            
+#define CAN_MSR_WKUI_Msk       (0x1U << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
+#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos      (4U)                                            
+#define CAN_MSR_SLAKI_Msk      (0x1U << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
+#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos        (8U)                                            
+#define CAN_MSR_TXM_Msk        (0x1U << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
+#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos        (9U)                                            
+#define CAN_MSR_RXM_Msk        (0x1U << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
+#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos       (10U)                                           
+#define CAN_MSR_SAMP_Msk       (0x1U << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
+#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos         (11U)                                           
+#define CAN_MSR_RX_Msk         (0x1U << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
+#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define CAN_TSR_RQCP0_Pos      (0U)                                            
+#define CAN_TSR_RQCP0_Msk      (0x1U << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
+#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos      (1U)                                            
+#define CAN_TSR_TXOK0_Msk      (0x1U << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
+#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos      (2U)                                            
+#define CAN_TSR_ALST0_Msk      (0x1U << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
+#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos      (3U)                                            
+#define CAN_TSR_TERR0_Msk      (0x1U << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
+#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos      (7U)                                            
+#define CAN_TSR_ABRQ0_Msk      (0x1U << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos      (8U)                                            
+#define CAN_TSR_RQCP1_Msk      (0x1U << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
+#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos      (9U)                                            
+#define CAN_TSR_TXOK1_Msk      (0x1U << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
+#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos      (10U)                                           
+#define CAN_TSR_ALST1_Msk      (0x1U << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
+#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos      (11U)                                           
+#define CAN_TSR_TERR1_Msk      (0x1U << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
+#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos      (15U)                                           
+#define CAN_TSR_ABRQ1_Msk      (0x1U << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos      (16U)                                           
+#define CAN_TSR_RQCP2_Msk      (0x1U << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
+#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos      (17U)                                           
+#define CAN_TSR_TXOK2_Msk      (0x1U << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
+#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos      (18U)                                           
+#define CAN_TSR_ALST2_Msk      (0x1U << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
+#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos      (19U)                                           
+#define CAN_TSR_TERR2_Msk      (0x1U << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
+#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos      (23U)                                           
+#define CAN_TSR_ABRQ2_Msk      (0x1U << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos       (24U)                                           
+#define CAN_TSR_CODE_Msk       (0x3U << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
+#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos        (26U)                                           
+#define CAN_TSR_TME_Msk        (0x7U << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
+#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos       (26U)                                           
+#define CAN_TSR_TME0_Msk       (0x1U << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
+#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos       (27U)                                           
+#define CAN_TSR_TME1_Msk       (0x1U << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
+#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos       (28U)                                           
+#define CAN_TSR_TME2_Msk       (0x1U << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
+#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos        (29U)                                           
+#define CAN_TSR_LOW_Msk        (0x7U << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
+#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos       (29U)                                           
+#define CAN_TSR_LOW0_Msk       (0x1U << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
+#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos       (30U)                                           
+#define CAN_TSR_LOW1_Msk       (0x1U << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
+#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos       (31U)                                           
+#define CAN_TSR_LOW2_Msk       (0x1U << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
+#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define CAN_RF0R_FMP0_Pos      (0U)                                            
+#define CAN_RF0R_FMP0_Msk      (0x3U << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
+#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos     (3U)                                            
+#define CAN_RF0R_FULL0_Msk     (0x1U << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
+#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos     (4U)                                            
+#define CAN_RF0R_FOVR0_Msk     (0x1U << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos     (5U)                                            
+#define CAN_RF0R_RFOM0_Msk     (0x1U << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define CAN_RF1R_FMP1_Pos      (0U)                                            
+#define CAN_RF1R_FMP1_Msk      (0x3U << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
+#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos     (3U)                                            
+#define CAN_RF1R_FULL1_Msk     (0x1U << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
+#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos     (4U)                                            
+#define CAN_RF1R_FOVR1_Msk     (0x1U << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos     (5U)                                            
+#define CAN_RF1R_RFOM1_Msk     (0x1U << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define CAN_IER_TMEIE_Pos      (0U)                                            
+#define CAN_IER_TMEIE_Msk      (0x1U << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
+#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos     (1U)                                            
+#define CAN_IER_FMPIE0_Msk     (0x1U << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
+#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos      (2U)                                            
+#define CAN_IER_FFIE0_Msk      (0x1U << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
+#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos     (3U)                                            
+#define CAN_IER_FOVIE0_Msk     (0x1U << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
+#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos     (4U)                                            
+#define CAN_IER_FMPIE1_Msk     (0x1U << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
+#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos      (5U)                                            
+#define CAN_IER_FFIE1_Msk      (0x1U << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
+#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos     (6U)                                            
+#define CAN_IER_FOVIE1_Msk     (0x1U << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
+#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos      (8U)                                            
+#define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
+#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos      (9U)                                            
+#define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
+#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos      (10U)                                           
+#define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
+#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos      (11U)                                           
+#define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
+#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos      (15U)                                           
+#define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
+#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos      (16U)                                           
+#define CAN_IER_WKUIE_Msk      (0x1U << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
+#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos      (17U)                                           
+#define CAN_IER_SLKIE_Msk      (0x1U << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
+#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE_Pos      (8U)                                            
+#define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
+#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error warning interrupt enable */
+#define CAN_IER_EPVIE_Pos      (9U)                                            
+#define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
+#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error passive interrupt enable */
+#define CAN_IER_BOFIE_Pos      (10U)                                           
+#define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
+#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-off interrupt enable */
+#define CAN_IER_LECIE_Pos      (11U)                                           
+#define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
+#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last error code interrupt enable */
+#define CAN_IER_ERRIE_Pos      (15U)                                           
+#define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
+#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error interrupt enable */
+
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define CAN_ESR_EWGF_Pos       (0U)                                            
+#define CAN_ESR_EWGF_Msk       (0x1U << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
+#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos       (1U)                                            
+#define CAN_ESR_EPVF_Msk       (0x1U << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
+#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos       (2U)                                            
+#define CAN_ESR_BOFF_Msk       (0x1U << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
+#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos        (4U)                                            
+#define CAN_ESR_LEC_Msk        (0x7U << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
+#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0          (0x1U << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
+#define CAN_ESR_LEC_1          (0x2U << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
+#define CAN_ESR_LEC_2          (0x4U << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos        (16U)                                           
+#define CAN_ESR_TEC_Msk        (0xFFU << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
+#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos        (24U)                                           
+#define CAN_ESR_REC_Msk        (0xFFU << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
+#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define CAN_BTR_BRP_Pos        (0U)                                            
+#define CAN_BTR_BRP_Msk        (0x3FFU << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
+#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos        (16U)                                           
+#define CAN_BTR_TS1_Msk        (0xFU << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
+#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0          (0x1U << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
+#define CAN_BTR_TS1_1          (0x2U << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
+#define CAN_BTR_TS1_2          (0x4U << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
+#define CAN_BTR_TS1_3          (0x8U << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos        (20U)                                           
+#define CAN_BTR_TS2_Msk        (0x7U << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
+#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0          (0x1U << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
+#define CAN_BTR_TS2_1          (0x2U << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
+#define CAN_BTR_TS2_2          (0x4U << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos        (24U)                                           
+#define CAN_BTR_SJW_Msk        (0x3U << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
+#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0          (0x1U << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
+#define CAN_BTR_SJW_1          (0x2U << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos       (30U)                                           
+#define CAN_BTR_LBKM_Msk       (0x1U << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
+#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos       (31U)                                           
+#define CAN_BTR_SILM_Msk       (0x1U << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
+#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define CAN_TI0R_TXRQ_Pos      (0U)                                            
+#define CAN_TI0R_TXRQ_Msk      (0x1U << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos       (1U)                                            
+#define CAN_TI0R_RTR_Msk       (0x1U << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos       (2U)                                            
+#define CAN_TI0R_IDE_Msk       (0x1U << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos      (3U)                                            
+#define CAN_TI0R_EXID_Msk      (0x3FFFFU << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos      (21U)                                           
+#define CAN_TI0R_STID_Msk      (0x7FFU << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define CAN_TDT0R_DLC_Pos      (0U)                                            
+#define CAN_TDT0R_DLC_Msk      (0xFU << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos      (8U)                                            
+#define CAN_TDT0R_TGT_Msk      (0x1U << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos     (16U)                                           
+#define CAN_TDT0R_TIME_Msk     (0xFFFFU << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define CAN_TDL0R_DATA0_Pos    (0U)                                            
+#define CAN_TDL0R_DATA0_Msk    (0xFFU << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos    (8U)                                            
+#define CAN_TDL0R_DATA1_Msk    (0xFFU << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos    (16U)                                           
+#define CAN_TDL0R_DATA2_Msk    (0xFFU << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos    (24U)                                           
+#define CAN_TDL0R_DATA3_Msk    (0xFFU << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define CAN_TDH0R_DATA4_Pos    (0U)                                            
+#define CAN_TDH0R_DATA4_Msk    (0xFFU << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos    (8U)                                            
+#define CAN_TDH0R_DATA5_Msk    (0xFFU << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos    (16U)                                           
+#define CAN_TDH0R_DATA6_Msk    (0xFFU << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos    (24U)                                           
+#define CAN_TDH0R_DATA7_Msk    (0xFFU << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define CAN_TI1R_TXRQ_Pos      (0U)                                            
+#define CAN_TI1R_TXRQ_Msk      (0x1U << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos       (1U)                                            
+#define CAN_TI1R_RTR_Msk       (0x1U << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos       (2U)                                            
+#define CAN_TI1R_IDE_Msk       (0x1U << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos      (3U)                                            
+#define CAN_TI1R_EXID_Msk      (0x3FFFFU << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos      (21U)                                           
+#define CAN_TI1R_STID_Msk      (0x7FFU << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define CAN_TDT1R_DLC_Pos      (0U)                                            
+#define CAN_TDT1R_DLC_Msk      (0xFU << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos      (8U)                                            
+#define CAN_TDT1R_TGT_Msk      (0x1U << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos     (16U)                                           
+#define CAN_TDT1R_TIME_Msk     (0xFFFFU << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define CAN_TDL1R_DATA0_Pos    (0U)                                            
+#define CAN_TDL1R_DATA0_Msk    (0xFFU << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos    (8U)                                            
+#define CAN_TDL1R_DATA1_Msk    (0xFFU << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos    (16U)                                           
+#define CAN_TDL1R_DATA2_Msk    (0xFFU << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos    (24U)                                           
+#define CAN_TDL1R_DATA3_Msk    (0xFFU << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define CAN_TDH1R_DATA4_Pos    (0U)                                            
+#define CAN_TDH1R_DATA4_Msk    (0xFFU << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos    (8U)                                            
+#define CAN_TDH1R_DATA5_Msk    (0xFFU << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos    (16U)                                           
+#define CAN_TDH1R_DATA6_Msk    (0xFFU << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos    (24U)                                           
+#define CAN_TDH1R_DATA7_Msk    (0xFFU << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define CAN_TI2R_TXRQ_Pos      (0U)                                            
+#define CAN_TI2R_TXRQ_Msk      (0x1U << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos       (1U)                                            
+#define CAN_TI2R_RTR_Msk       (0x1U << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos       (2U)                                            
+#define CAN_TI2R_IDE_Msk       (0x1U << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos      (3U)                                            
+#define CAN_TI2R_EXID_Msk      (0x3FFFFU << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos      (21U)                                           
+#define CAN_TI2R_STID_Msk      (0x7FFU << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/  
+#define CAN_TDT2R_DLC_Pos      (0U)                                            
+#define CAN_TDT2R_DLC_Msk      (0xFU << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos      (8U)                                            
+#define CAN_TDT2R_TGT_Msk      (0x1U << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos     (16U)                                           
+#define CAN_TDT2R_TIME_Msk     (0xFFFFU << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define CAN_TDL2R_DATA0_Pos    (0U)                                            
+#define CAN_TDL2R_DATA0_Msk    (0xFFU << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos    (8U)                                            
+#define CAN_TDL2R_DATA1_Msk    (0xFFU << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos    (16U)                                           
+#define CAN_TDL2R_DATA2_Msk    (0xFFU << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos    (24U)                                           
+#define CAN_TDL2R_DATA3_Msk    (0xFFU << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define CAN_TDH2R_DATA4_Pos    (0U)                                            
+#define CAN_TDH2R_DATA4_Msk    (0xFFU << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos    (8U)                                            
+#define CAN_TDH2R_DATA5_Msk    (0xFFU << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos    (16U)                                           
+#define CAN_TDH2R_DATA6_Msk    (0xFFU << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos    (24U)                                           
+#define CAN_TDH2R_DATA7_Msk    (0xFFU << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define CAN_RI0R_RTR_Pos       (1U)                                            
+#define CAN_RI0R_RTR_Msk       (0x1U << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos       (2U)                                            
+#define CAN_RI0R_IDE_Msk       (0x1U << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos      (3U)                                            
+#define CAN_RI0R_EXID_Msk      (0x3FFFFU << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos      (21U)                                           
+#define CAN_RI0R_STID_Msk      (0x7FFU << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define CAN_RDT0R_DLC_Pos      (0U)                                            
+#define CAN_RDT0R_DLC_Msk      (0xFU << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos      (8U)                                            
+#define CAN_RDT0R_FMI_Msk      (0xFFU << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos     (16U)                                           
+#define CAN_RDT0R_TIME_Msk     (0xFFFFU << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define CAN_RDL0R_DATA0_Pos    (0U)                                            
+#define CAN_RDL0R_DATA0_Msk    (0xFFU << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos    (8U)                                            
+#define CAN_RDL0R_DATA1_Msk    (0xFFU << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos    (16U)                                           
+#define CAN_RDL0R_DATA2_Msk    (0xFFU << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos    (24U)                                           
+#define CAN_RDL0R_DATA3_Msk    (0xFFU << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define CAN_RDH0R_DATA4_Pos    (0U)                                            
+#define CAN_RDH0R_DATA4_Msk    (0xFFU << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos    (8U)                                            
+#define CAN_RDH0R_DATA5_Msk    (0xFFU << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos    (16U)                                           
+#define CAN_RDH0R_DATA6_Msk    (0xFFU << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos    (24U)                                           
+#define CAN_RDH0R_DATA7_Msk    (0xFFU << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define CAN_RI1R_RTR_Pos       (1U)                                            
+#define CAN_RI1R_RTR_Msk       (0x1U << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos       (2U)                                            
+#define CAN_RI1R_IDE_Msk       (0x1U << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos      (3U)                                            
+#define CAN_RI1R_EXID_Msk      (0x3FFFFU << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos      (21U)                                           
+#define CAN_RI1R_STID_Msk      (0x7FFU << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define CAN_RDT1R_DLC_Pos      (0U)                                            
+#define CAN_RDT1R_DLC_Msk      (0xFU << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos      (8U)                                            
+#define CAN_RDT1R_FMI_Msk      (0xFFU << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos     (16U)                                           
+#define CAN_RDT1R_TIME_Msk     (0xFFFFU << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define CAN_RDL1R_DATA0_Pos    (0U)                                            
+#define CAN_RDL1R_DATA0_Msk    (0xFFU << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos    (8U)                                            
+#define CAN_RDL1R_DATA1_Msk    (0xFFU << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos    (16U)                                           
+#define CAN_RDL1R_DATA2_Msk    (0xFFU << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos    (24U)                                           
+#define CAN_RDL1R_DATA3_Msk    (0xFFU << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define CAN_RDH1R_DATA4_Pos    (0U)                                            
+#define CAN_RDH1R_DATA4_Msk    (0xFFU << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos    (8U)                                            
+#define CAN_RDH1R_DATA5_Msk    (0xFFU << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos    (16U)                                           
+#define CAN_RDH1R_DATA6_Msk    (0xFFU << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos    (24U)                                           
+#define CAN_RDH1R_DATA7_Msk    (0xFFU << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define CAN_FMR_FINIT_Pos      (0U)                                            
+#define CAN_FMR_FINIT_Msk      (0x1U << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
+#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos     (8U)                                            
+#define CAN_FMR_CAN2SB_Msk     (0x3FU << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define CAN_FM1R_FBM_Pos       (0U)                                            
+#define CAN_FM1R_FBM_Msk       (0xFFFFFFFU << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */
+#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos      (0U)                                            
+#define CAN_FM1R_FBM0_Msk      (0x1U << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
+#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos      (1U)                                            
+#define CAN_FM1R_FBM1_Msk      (0x1U << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
+#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos      (2U)                                            
+#define CAN_FM1R_FBM2_Msk      (0x1U << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
+#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos      (3U)                                            
+#define CAN_FM1R_FBM3_Msk      (0x1U << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
+#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos      (4U)                                            
+#define CAN_FM1R_FBM4_Msk      (0x1U << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
+#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos      (5U)                                            
+#define CAN_FM1R_FBM5_Msk      (0x1U << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
+#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos      (6U)                                            
+#define CAN_FM1R_FBM6_Msk      (0x1U << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
+#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos      (7U)                                            
+#define CAN_FM1R_FBM7_Msk      (0x1U << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
+#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos      (8U)                                            
+#define CAN_FM1R_FBM8_Msk      (0x1U << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
+#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos      (9U)                                            
+#define CAN_FM1R_FBM9_Msk      (0x1U << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
+#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos     (10U)                                           
+#define CAN_FM1R_FBM10_Msk     (0x1U << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
+#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos     (11U)                                           
+#define CAN_FM1R_FBM11_Msk     (0x1U << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
+#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos     (12U)                                           
+#define CAN_FM1R_FBM12_Msk     (0x1U << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
+#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos     (13U)                                           
+#define CAN_FM1R_FBM13_Msk     (0x1U << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
+#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14_Pos     (14U)                                           
+#define CAN_FM1R_FBM14_Msk     (0x1U << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */
+#define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15_Pos     (15U)                                           
+#define CAN_FM1R_FBM15_Msk     (0x1U << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */
+#define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16_Pos     (16U)                                           
+#define CAN_FM1R_FBM16_Msk     (0x1U << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */
+#define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17_Pos     (17U)                                           
+#define CAN_FM1R_FBM17_Msk     (0x1U << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */
+#define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18_Pos     (18U)                                           
+#define CAN_FM1R_FBM18_Msk     (0x1U << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */
+#define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19_Pos     (19U)                                           
+#define CAN_FM1R_FBM19_Msk     (0x1U << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */
+#define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20_Pos     (20U)                                           
+#define CAN_FM1R_FBM20_Msk     (0x1U << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */
+#define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21_Pos     (21U)                                           
+#define CAN_FM1R_FBM21_Msk     (0x1U << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */
+#define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22_Pos     (22U)                                           
+#define CAN_FM1R_FBM22_Msk     (0x1U << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */
+#define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23_Pos     (23U)                                           
+#define CAN_FM1R_FBM23_Msk     (0x1U << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */
+#define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24_Pos     (24U)                                           
+#define CAN_FM1R_FBM24_Msk     (0x1U << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */
+#define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25_Pos     (25U)                                           
+#define CAN_FM1R_FBM25_Msk     (0x1U << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */
+#define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26_Pos     (26U)                                           
+#define CAN_FM1R_FBM26_Msk     (0x1U << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */
+#define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27_Pos     (27U)                                           
+#define CAN_FM1R_FBM27_Msk     (0x1U << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */
+#define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define CAN_FS1R_FSC_Pos       (0U)                                            
+#define CAN_FS1R_FSC_Msk       (0xFFFFFFFU << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */
+#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos      (0U)                                            
+#define CAN_FS1R_FSC0_Msk      (0x1U << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
+#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos      (1U)                                            
+#define CAN_FS1R_FSC1_Msk      (0x1U << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
+#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos      (2U)                                            
+#define CAN_FS1R_FSC2_Msk      (0x1U << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
+#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos      (3U)                                            
+#define CAN_FS1R_FSC3_Msk      (0x1U << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
+#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos      (4U)                                            
+#define CAN_FS1R_FSC4_Msk      (0x1U << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
+#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos      (5U)                                            
+#define CAN_FS1R_FSC5_Msk      (0x1U << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
+#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos      (6U)                                            
+#define CAN_FS1R_FSC6_Msk      (0x1U << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
+#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos      (7U)                                            
+#define CAN_FS1R_FSC7_Msk      (0x1U << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
+#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos      (8U)                                            
+#define CAN_FS1R_FSC8_Msk      (0x1U << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
+#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos      (9U)                                            
+#define CAN_FS1R_FSC9_Msk      (0x1U << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
+#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos     (10U)                                           
+#define CAN_FS1R_FSC10_Msk     (0x1U << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
+#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos     (11U)                                           
+#define CAN_FS1R_FSC11_Msk     (0x1U << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
+#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos     (12U)                                           
+#define CAN_FS1R_FSC12_Msk     (0x1U << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
+#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos     (13U)                                           
+#define CAN_FS1R_FSC13_Msk     (0x1U << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
+#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14_Pos     (14U)                                           
+#define CAN_FS1R_FSC14_Msk     (0x1U << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */
+#define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15_Pos     (15U)                                           
+#define CAN_FS1R_FSC15_Msk     (0x1U << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */
+#define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16_Pos     (16U)                                           
+#define CAN_FS1R_FSC16_Msk     (0x1U << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */
+#define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17_Pos     (17U)                                           
+#define CAN_FS1R_FSC17_Msk     (0x1U << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */
+#define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18_Pos     (18U)                                           
+#define CAN_FS1R_FSC18_Msk     (0x1U << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */
+#define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19_Pos     (19U)                                           
+#define CAN_FS1R_FSC19_Msk     (0x1U << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */
+#define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20_Pos     (20U)                                           
+#define CAN_FS1R_FSC20_Msk     (0x1U << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */
+#define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21_Pos     (21U)                                           
+#define CAN_FS1R_FSC21_Msk     (0x1U << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */
+#define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22_Pos     (22U)                                           
+#define CAN_FS1R_FSC22_Msk     (0x1U << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */
+#define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23_Pos     (23U)                                           
+#define CAN_FS1R_FSC23_Msk     (0x1U << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */
+#define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24_Pos     (24U)                                           
+#define CAN_FS1R_FSC24_Msk     (0x1U << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */
+#define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25_Pos     (25U)                                           
+#define CAN_FS1R_FSC25_Msk     (0x1U << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */
+#define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26_Pos     (26U)                                           
+#define CAN_FS1R_FSC26_Msk     (0x1U << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */
+#define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27_Pos     (27U)                                           
+#define CAN_FS1R_FSC27_Msk     (0x1U << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */
+#define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define CAN_FFA1R_FFA_Pos      (0U)                                            
+#define CAN_FFA1R_FFA_Msk      (0xFFFFFFFU << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */
+#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos     (0U)                                            
+#define CAN_FFA1R_FFA0_Msk     (0x1U << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1_Pos     (1U)                                            
+#define CAN_FFA1R_FFA1_Msk     (0x1U << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2_Pos     (2U)                                            
+#define CAN_FFA1R_FFA2_Msk     (0x1U << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3_Pos     (3U)                                            
+#define CAN_FFA1R_FFA3_Msk     (0x1U << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4_Pos     (4U)                                            
+#define CAN_FFA1R_FFA4_Msk     (0x1U << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5_Pos     (5U)                                            
+#define CAN_FFA1R_FFA5_Msk     (0x1U << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6_Pos     (6U)                                            
+#define CAN_FFA1R_FFA6_Msk     (0x1U << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7_Pos     (7U)                                            
+#define CAN_FFA1R_FFA7_Msk     (0x1U << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8_Pos     (8U)                                            
+#define CAN_FFA1R_FFA8_Msk     (0x1U << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9_Pos     (9U)                                            
+#define CAN_FFA1R_FFA9_Msk     (0x1U << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10_Pos    (10U)                                           
+#define CAN_FFA1R_FFA10_Msk    (0x1U << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11_Pos    (11U)                                           
+#define CAN_FFA1R_FFA11_Msk    (0x1U << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12_Pos    (12U)                                           
+#define CAN_FFA1R_FFA12_Msk    (0x1U << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13_Pos    (13U)                                           
+#define CAN_FFA1R_FFA13_Msk    (0x1U << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14_Pos    (14U)                                           
+#define CAN_FFA1R_FFA14_Msk    (0x1U << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */
+#define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15_Pos    (15U)                                           
+#define CAN_FFA1R_FFA15_Msk    (0x1U << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */
+#define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16_Pos    (16U)                                           
+#define CAN_FFA1R_FFA16_Msk    (0x1U << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */
+#define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17_Pos    (17U)                                           
+#define CAN_FFA1R_FFA17_Msk    (0x1U << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */
+#define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18_Pos    (18U)                                           
+#define CAN_FFA1R_FFA18_Msk    (0x1U << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */
+#define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19_Pos    (19U)                                           
+#define CAN_FFA1R_FFA19_Msk    (0x1U << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */
+#define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20_Pos    (20U)                                           
+#define CAN_FFA1R_FFA20_Msk    (0x1U << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */
+#define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21_Pos    (21U)                                           
+#define CAN_FFA1R_FFA21_Msk    (0x1U << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */
+#define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22_Pos    (22U)                                           
+#define CAN_FFA1R_FFA22_Msk    (0x1U << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */
+#define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23_Pos    (23U)                                           
+#define CAN_FFA1R_FFA23_Msk    (0x1U << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */
+#define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24_Pos    (24U)                                           
+#define CAN_FFA1R_FFA24_Msk    (0x1U << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */
+#define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25_Pos    (25U)                                           
+#define CAN_FFA1R_FFA25_Msk    (0x1U << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */
+#define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26_Pos    (26U)                                           
+#define CAN_FFA1R_FFA26_Msk    (0x1U << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */
+#define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27_Pos    (27U)                                           
+#define CAN_FFA1R_FFA27_Msk    (0x1U << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */
+#define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define CAN_FA1R_FACT_Pos      (0U)                                            
+#define CAN_FA1R_FACT_Msk      (0xFFFFFFFU << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */
+#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos     (0U)                                            
+#define CAN_FA1R_FACT0_Msk     (0x1U << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
+#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1_Pos     (1U)                                            
+#define CAN_FA1R_FACT1_Msk     (0x1U << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
+#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2_Pos     (2U)                                            
+#define CAN_FA1R_FACT2_Msk     (0x1U << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
+#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3_Pos     (3U)                                            
+#define CAN_FA1R_FACT3_Msk     (0x1U << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
+#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4_Pos     (4U)                                            
+#define CAN_FA1R_FACT4_Msk     (0x1U << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
+#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5_Pos     (5U)                                            
+#define CAN_FA1R_FACT5_Msk     (0x1U << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
+#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6_Pos     (6U)                                            
+#define CAN_FA1R_FACT6_Msk     (0x1U << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
+#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7_Pos     (7U)                                            
+#define CAN_FA1R_FACT7_Msk     (0x1U << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
+#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8_Pos     (8U)                                            
+#define CAN_FA1R_FACT8_Msk     (0x1U << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
+#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9_Pos     (9U)                                            
+#define CAN_FA1R_FACT9_Msk     (0x1U << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
+#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10_Pos    (10U)                                           
+#define CAN_FA1R_FACT10_Msk    (0x1U << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
+#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11_Pos    (11U)                                           
+#define CAN_FA1R_FACT11_Msk    (0x1U << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
+#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12_Pos    (12U)                                           
+#define CAN_FA1R_FACT12_Msk    (0x1U << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
+#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13_Pos    (13U)                                           
+#define CAN_FA1R_FACT13_Msk    (0x1U << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
+#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14_Pos    (14U)                                           
+#define CAN_FA1R_FACT14_Msk    (0x1U << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */
+#define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15_Pos    (15U)                                           
+#define CAN_FA1R_FACT15_Msk    (0x1U << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */
+#define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16_Pos    (16U)                                           
+#define CAN_FA1R_FACT16_Msk    (0x1U << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */
+#define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17_Pos    (17U)                                           
+#define CAN_FA1R_FACT17_Msk    (0x1U << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */
+#define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18_Pos    (18U)                                           
+#define CAN_FA1R_FACT18_Msk    (0x1U << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */
+#define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19_Pos    (19U)                                           
+#define CAN_FA1R_FACT19_Msk    (0x1U << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */
+#define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20_Pos    (20U)                                           
+#define CAN_FA1R_FACT20_Msk    (0x1U << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */
+#define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21_Pos    (21U)                                           
+#define CAN_FA1R_FACT21_Msk    (0x1U << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */
+#define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22_Pos    (22U)                                           
+#define CAN_FA1R_FACT22_Msk    (0x1U << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */
+#define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23_Pos    (23U)                                           
+#define CAN_FA1R_FACT23_Msk    (0x1U << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */
+#define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24_Pos    (24U)                                           
+#define CAN_FA1R_FACT24_Msk    (0x1U << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */
+#define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25_Pos    (25U)                                           
+#define CAN_FA1R_FACT25_Msk    (0x1U << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */
+#define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26_Pos    (26U)                                           
+#define CAN_FA1R_FACT26_Msk    (0x1U << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */
+#define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27_Pos    (27U)                                           
+#define CAN_FA1R_FACT27_Msk    (0x1U << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */
+#define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */
+
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define CAN_F0R1_FB0_Pos       (0U)                                            
+#define CAN_F0R1_FB0_Msk       (0x1U << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos       (1U)                                            
+#define CAN_F0R1_FB1_Msk       (0x1U << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos       (2U)                                            
+#define CAN_F0R1_FB2_Msk       (0x1U << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos       (3U)                                            
+#define CAN_F0R1_FB3_Msk       (0x1U << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos       (4U)                                            
+#define CAN_F0R1_FB4_Msk       (0x1U << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos       (5U)                                            
+#define CAN_F0R1_FB5_Msk       (0x1U << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos       (6U)                                            
+#define CAN_F0R1_FB6_Msk       (0x1U << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos       (7U)                                            
+#define CAN_F0R1_FB7_Msk       (0x1U << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos       (8U)                                            
+#define CAN_F0R1_FB8_Msk       (0x1U << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos       (9U)                                            
+#define CAN_F0R1_FB9_Msk       (0x1U << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos      (10U)                                           
+#define CAN_F0R1_FB10_Msk      (0x1U << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos      (11U)                                           
+#define CAN_F0R1_FB11_Msk      (0x1U << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos      (12U)                                           
+#define CAN_F0R1_FB12_Msk      (0x1U << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos      (13U)                                           
+#define CAN_F0R1_FB13_Msk      (0x1U << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos      (14U)                                           
+#define CAN_F0R1_FB14_Msk      (0x1U << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos      (15U)                                           
+#define CAN_F0R1_FB15_Msk      (0x1U << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos      (16U)                                           
+#define CAN_F0R1_FB16_Msk      (0x1U << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos      (17U)                                           
+#define CAN_F0R1_FB17_Msk      (0x1U << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos      (18U)                                           
+#define CAN_F0R1_FB18_Msk      (0x1U << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos      (19U)                                           
+#define CAN_F0R1_FB19_Msk      (0x1U << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos      (20U)                                           
+#define CAN_F0R1_FB20_Msk      (0x1U << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos      (21U)                                           
+#define CAN_F0R1_FB21_Msk      (0x1U << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos      (22U)                                           
+#define CAN_F0R1_FB22_Msk      (0x1U << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos      (23U)                                           
+#define CAN_F0R1_FB23_Msk      (0x1U << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos      (24U)                                           
+#define CAN_F0R1_FB24_Msk      (0x1U << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos      (25U)                                           
+#define CAN_F0R1_FB25_Msk      (0x1U << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos      (26U)                                           
+#define CAN_F0R1_FB26_Msk      (0x1U << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos      (27U)                                           
+#define CAN_F0R1_FB27_Msk      (0x1U << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos      (28U)                                           
+#define CAN_F0R1_FB28_Msk      (0x1U << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos      (29U)                                           
+#define CAN_F0R1_FB29_Msk      (0x1U << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos      (30U)                                           
+#define CAN_F0R1_FB30_Msk      (0x1U << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos      (31U)                                           
+#define CAN_F0R1_FB31_Msk      (0x1U << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define CAN_F1R1_FB0_Pos       (0U)                                            
+#define CAN_F1R1_FB0_Msk       (0x1U << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos       (1U)                                            
+#define CAN_F1R1_FB1_Msk       (0x1U << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos       (2U)                                            
+#define CAN_F1R1_FB2_Msk       (0x1U << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos       (3U)                                            
+#define CAN_F1R1_FB3_Msk       (0x1U << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos       (4U)                                            
+#define CAN_F1R1_FB4_Msk       (0x1U << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos       (5U)                                            
+#define CAN_F1R1_FB5_Msk       (0x1U << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos       (6U)                                            
+#define CAN_F1R1_FB6_Msk       (0x1U << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos       (7U)                                            
+#define CAN_F1R1_FB7_Msk       (0x1U << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos       (8U)                                            
+#define CAN_F1R1_FB8_Msk       (0x1U << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos       (9U)                                            
+#define CAN_F1R1_FB9_Msk       (0x1U << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos      (10U)                                           
+#define CAN_F1R1_FB10_Msk      (0x1U << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos      (11U)                                           
+#define CAN_F1R1_FB11_Msk      (0x1U << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos      (12U)                                           
+#define CAN_F1R1_FB12_Msk      (0x1U << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos      (13U)                                           
+#define CAN_F1R1_FB13_Msk      (0x1U << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos      (14U)                                           
+#define CAN_F1R1_FB14_Msk      (0x1U << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos      (15U)                                           
+#define CAN_F1R1_FB15_Msk      (0x1U << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos      (16U)                                           
+#define CAN_F1R1_FB16_Msk      (0x1U << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos      (17U)                                           
+#define CAN_F1R1_FB17_Msk      (0x1U << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos      (18U)                                           
+#define CAN_F1R1_FB18_Msk      (0x1U << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos      (19U)                                           
+#define CAN_F1R1_FB19_Msk      (0x1U << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos      (20U)                                           
+#define CAN_F1R1_FB20_Msk      (0x1U << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos      (21U)                                           
+#define CAN_F1R1_FB21_Msk      (0x1U << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos      (22U)                                           
+#define CAN_F1R1_FB22_Msk      (0x1U << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos      (23U)                                           
+#define CAN_F1R1_FB23_Msk      (0x1U << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos      (24U)                                           
+#define CAN_F1R1_FB24_Msk      (0x1U << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos      (25U)                                           
+#define CAN_F1R1_FB25_Msk      (0x1U << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos      (26U)                                           
+#define CAN_F1R1_FB26_Msk      (0x1U << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos      (27U)                                           
+#define CAN_F1R1_FB27_Msk      (0x1U << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos      (28U)                                           
+#define CAN_F1R1_FB28_Msk      (0x1U << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos      (29U)                                           
+#define CAN_F1R1_FB29_Msk      (0x1U << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos      (30U)                                           
+#define CAN_F1R1_FB30_Msk      (0x1U << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos      (31U)                                           
+#define CAN_F1R1_FB31_Msk      (0x1U << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define CAN_F2R1_FB0_Pos       (0U)                                            
+#define CAN_F2R1_FB0_Msk       (0x1U << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos       (1U)                                            
+#define CAN_F2R1_FB1_Msk       (0x1U << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos       (2U)                                            
+#define CAN_F2R1_FB2_Msk       (0x1U << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos       (3U)                                            
+#define CAN_F2R1_FB3_Msk       (0x1U << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos       (4U)                                            
+#define CAN_F2R1_FB4_Msk       (0x1U << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos       (5U)                                            
+#define CAN_F2R1_FB5_Msk       (0x1U << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos       (6U)                                            
+#define CAN_F2R1_FB6_Msk       (0x1U << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos       (7U)                                            
+#define CAN_F2R1_FB7_Msk       (0x1U << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos       (8U)                                            
+#define CAN_F2R1_FB8_Msk       (0x1U << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos       (9U)                                            
+#define CAN_F2R1_FB9_Msk       (0x1U << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos      (10U)                                           
+#define CAN_F2R1_FB10_Msk      (0x1U << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos      (11U)                                           
+#define CAN_F2R1_FB11_Msk      (0x1U << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos      (12U)                                           
+#define CAN_F2R1_FB12_Msk      (0x1U << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos      (13U)                                           
+#define CAN_F2R1_FB13_Msk      (0x1U << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos      (14U)                                           
+#define CAN_F2R1_FB14_Msk      (0x1U << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos      (15U)                                           
+#define CAN_F2R1_FB15_Msk      (0x1U << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos      (16U)                                           
+#define CAN_F2R1_FB16_Msk      (0x1U << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos      (17U)                                           
+#define CAN_F2R1_FB17_Msk      (0x1U << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos      (18U)                                           
+#define CAN_F2R1_FB18_Msk      (0x1U << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos      (19U)                                           
+#define CAN_F2R1_FB19_Msk      (0x1U << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos      (20U)                                           
+#define CAN_F2R1_FB20_Msk      (0x1U << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos      (21U)                                           
+#define CAN_F2R1_FB21_Msk      (0x1U << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos      (22U)                                           
+#define CAN_F2R1_FB22_Msk      (0x1U << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos      (23U)                                           
+#define CAN_F2R1_FB23_Msk      (0x1U << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos      (24U)                                           
+#define CAN_F2R1_FB24_Msk      (0x1U << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos      (25U)                                           
+#define CAN_F2R1_FB25_Msk      (0x1U << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos      (26U)                                           
+#define CAN_F2R1_FB26_Msk      (0x1U << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos      (27U)                                           
+#define CAN_F2R1_FB27_Msk      (0x1U << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos      (28U)                                           
+#define CAN_F2R1_FB28_Msk      (0x1U << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos      (29U)                                           
+#define CAN_F2R1_FB29_Msk      (0x1U << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos      (30U)                                           
+#define CAN_F2R1_FB30_Msk      (0x1U << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos      (31U)                                           
+#define CAN_F2R1_FB31_Msk      (0x1U << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define CAN_F3R1_FB0_Pos       (0U)                                            
+#define CAN_F3R1_FB0_Msk       (0x1U << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos       (1U)                                            
+#define CAN_F3R1_FB1_Msk       (0x1U << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos       (2U)                                            
+#define CAN_F3R1_FB2_Msk       (0x1U << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos       (3U)                                            
+#define CAN_F3R1_FB3_Msk       (0x1U << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos       (4U)                                            
+#define CAN_F3R1_FB4_Msk       (0x1U << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos       (5U)                                            
+#define CAN_F3R1_FB5_Msk       (0x1U << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos       (6U)                                            
+#define CAN_F3R1_FB6_Msk       (0x1U << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos       (7U)                                            
+#define CAN_F3R1_FB7_Msk       (0x1U << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos       (8U)                                            
+#define CAN_F3R1_FB8_Msk       (0x1U << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos       (9U)                                            
+#define CAN_F3R1_FB9_Msk       (0x1U << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos      (10U)                                           
+#define CAN_F3R1_FB10_Msk      (0x1U << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos      (11U)                                           
+#define CAN_F3R1_FB11_Msk      (0x1U << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos      (12U)                                           
+#define CAN_F3R1_FB12_Msk      (0x1U << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos      (13U)                                           
+#define CAN_F3R1_FB13_Msk      (0x1U << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos      (14U)                                           
+#define CAN_F3R1_FB14_Msk      (0x1U << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos      (15U)                                           
+#define CAN_F3R1_FB15_Msk      (0x1U << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos      (16U)                                           
+#define CAN_F3R1_FB16_Msk      (0x1U << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos      (17U)                                           
+#define CAN_F3R1_FB17_Msk      (0x1U << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos      (18U)                                           
+#define CAN_F3R1_FB18_Msk      (0x1U << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos      (19U)                                           
+#define CAN_F3R1_FB19_Msk      (0x1U << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos      (20U)                                           
+#define CAN_F3R1_FB20_Msk      (0x1U << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos      (21U)                                           
+#define CAN_F3R1_FB21_Msk      (0x1U << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos      (22U)                                           
+#define CAN_F3R1_FB22_Msk      (0x1U << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos      (23U)                                           
+#define CAN_F3R1_FB23_Msk      (0x1U << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos      (24U)                                           
+#define CAN_F3R1_FB24_Msk      (0x1U << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos      (25U)                                           
+#define CAN_F3R1_FB25_Msk      (0x1U << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos      (26U)                                           
+#define CAN_F3R1_FB26_Msk      (0x1U << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos      (27U)                                           
+#define CAN_F3R1_FB27_Msk      (0x1U << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos      (28U)                                           
+#define CAN_F3R1_FB28_Msk      (0x1U << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos      (29U)                                           
+#define CAN_F3R1_FB29_Msk      (0x1U << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos      (30U)                                           
+#define CAN_F3R1_FB30_Msk      (0x1U << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos      (31U)                                           
+#define CAN_F3R1_FB31_Msk      (0x1U << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define CAN_F4R1_FB0_Pos       (0U)                                            
+#define CAN_F4R1_FB0_Msk       (0x1U << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos       (1U)                                            
+#define CAN_F4R1_FB1_Msk       (0x1U << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos       (2U)                                            
+#define CAN_F4R1_FB2_Msk       (0x1U << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos       (3U)                                            
+#define CAN_F4R1_FB3_Msk       (0x1U << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos       (4U)                                            
+#define CAN_F4R1_FB4_Msk       (0x1U << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos       (5U)                                            
+#define CAN_F4R1_FB5_Msk       (0x1U << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos       (6U)                                            
+#define CAN_F4R1_FB6_Msk       (0x1U << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos       (7U)                                            
+#define CAN_F4R1_FB7_Msk       (0x1U << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos       (8U)                                            
+#define CAN_F4R1_FB8_Msk       (0x1U << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos       (9U)                                            
+#define CAN_F4R1_FB9_Msk       (0x1U << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos      (10U)                                           
+#define CAN_F4R1_FB10_Msk      (0x1U << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos      (11U)                                           
+#define CAN_F4R1_FB11_Msk      (0x1U << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos      (12U)                                           
+#define CAN_F4R1_FB12_Msk      (0x1U << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos      (13U)                                           
+#define CAN_F4R1_FB13_Msk      (0x1U << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos      (14U)                                           
+#define CAN_F4R1_FB14_Msk      (0x1U << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos      (15U)                                           
+#define CAN_F4R1_FB15_Msk      (0x1U << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos      (16U)                                           
+#define CAN_F4R1_FB16_Msk      (0x1U << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos      (17U)                                           
+#define CAN_F4R1_FB17_Msk      (0x1U << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos      (18U)                                           
+#define CAN_F4R1_FB18_Msk      (0x1U << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos      (19U)                                           
+#define CAN_F4R1_FB19_Msk      (0x1U << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos      (20U)                                           
+#define CAN_F4R1_FB20_Msk      (0x1U << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos      (21U)                                           
+#define CAN_F4R1_FB21_Msk      (0x1U << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos      (22U)                                           
+#define CAN_F4R1_FB22_Msk      (0x1U << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos      (23U)                                           
+#define CAN_F4R1_FB23_Msk      (0x1U << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos      (24U)                                           
+#define CAN_F4R1_FB24_Msk      (0x1U << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos      (25U)                                           
+#define CAN_F4R1_FB25_Msk      (0x1U << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos      (26U)                                           
+#define CAN_F4R1_FB26_Msk      (0x1U << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos      (27U)                                           
+#define CAN_F4R1_FB27_Msk      (0x1U << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos      (28U)                                           
+#define CAN_F4R1_FB28_Msk      (0x1U << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos      (29U)                                           
+#define CAN_F4R1_FB29_Msk      (0x1U << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos      (30U)                                           
+#define CAN_F4R1_FB30_Msk      (0x1U << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos      (31U)                                           
+#define CAN_F4R1_FB31_Msk      (0x1U << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define CAN_F5R1_FB0_Pos       (0U)                                            
+#define CAN_F5R1_FB0_Msk       (0x1U << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos       (1U)                                            
+#define CAN_F5R1_FB1_Msk       (0x1U << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos       (2U)                                            
+#define CAN_F5R1_FB2_Msk       (0x1U << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos       (3U)                                            
+#define CAN_F5R1_FB3_Msk       (0x1U << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos       (4U)                                            
+#define CAN_F5R1_FB4_Msk       (0x1U << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos       (5U)                                            
+#define CAN_F5R1_FB5_Msk       (0x1U << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos       (6U)                                            
+#define CAN_F5R1_FB6_Msk       (0x1U << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos       (7U)                                            
+#define CAN_F5R1_FB7_Msk       (0x1U << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos       (8U)                                            
+#define CAN_F5R1_FB8_Msk       (0x1U << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos       (9U)                                            
+#define CAN_F5R1_FB9_Msk       (0x1U << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos      (10U)                                           
+#define CAN_F5R1_FB10_Msk      (0x1U << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos      (11U)                                           
+#define CAN_F5R1_FB11_Msk      (0x1U << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos      (12U)                                           
+#define CAN_F5R1_FB12_Msk      (0x1U << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos      (13U)                                           
+#define CAN_F5R1_FB13_Msk      (0x1U << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos      (14U)                                           
+#define CAN_F5R1_FB14_Msk      (0x1U << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos      (15U)                                           
+#define CAN_F5R1_FB15_Msk      (0x1U << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos      (16U)                                           
+#define CAN_F5R1_FB16_Msk      (0x1U << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos      (17U)                                           
+#define CAN_F5R1_FB17_Msk      (0x1U << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos      (18U)                                           
+#define CAN_F5R1_FB18_Msk      (0x1U << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos      (19U)                                           
+#define CAN_F5R1_FB19_Msk      (0x1U << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos      (20U)                                           
+#define CAN_F5R1_FB20_Msk      (0x1U << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos      (21U)                                           
+#define CAN_F5R1_FB21_Msk      (0x1U << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos      (22U)                                           
+#define CAN_F5R1_FB22_Msk      (0x1U << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos      (23U)                                           
+#define CAN_F5R1_FB23_Msk      (0x1U << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos      (24U)                                           
+#define CAN_F5R1_FB24_Msk      (0x1U << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos      (25U)                                           
+#define CAN_F5R1_FB25_Msk      (0x1U << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos      (26U)                                           
+#define CAN_F5R1_FB26_Msk      (0x1U << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos      (27U)                                           
+#define CAN_F5R1_FB27_Msk      (0x1U << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos      (28U)                                           
+#define CAN_F5R1_FB28_Msk      (0x1U << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos      (29U)                                           
+#define CAN_F5R1_FB29_Msk      (0x1U << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos      (30U)                                           
+#define CAN_F5R1_FB30_Msk      (0x1U << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos      (31U)                                           
+#define CAN_F5R1_FB31_Msk      (0x1U << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define CAN_F6R1_FB0_Pos       (0U)                                            
+#define CAN_F6R1_FB0_Msk       (0x1U << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos       (1U)                                            
+#define CAN_F6R1_FB1_Msk       (0x1U << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos       (2U)                                            
+#define CAN_F6R1_FB2_Msk       (0x1U << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos       (3U)                                            
+#define CAN_F6R1_FB3_Msk       (0x1U << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos       (4U)                                            
+#define CAN_F6R1_FB4_Msk       (0x1U << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos       (5U)                                            
+#define CAN_F6R1_FB5_Msk       (0x1U << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos       (6U)                                            
+#define CAN_F6R1_FB6_Msk       (0x1U << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos       (7U)                                            
+#define CAN_F6R1_FB7_Msk       (0x1U << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos       (8U)                                            
+#define CAN_F6R1_FB8_Msk       (0x1U << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos       (9U)                                            
+#define CAN_F6R1_FB9_Msk       (0x1U << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos      (10U)                                           
+#define CAN_F6R1_FB10_Msk      (0x1U << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos      (11U)                                           
+#define CAN_F6R1_FB11_Msk      (0x1U << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos      (12U)                                           
+#define CAN_F6R1_FB12_Msk      (0x1U << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos      (13U)                                           
+#define CAN_F6R1_FB13_Msk      (0x1U << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos      (14U)                                           
+#define CAN_F6R1_FB14_Msk      (0x1U << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos      (15U)                                           
+#define CAN_F6R1_FB15_Msk      (0x1U << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos      (16U)                                           
+#define CAN_F6R1_FB16_Msk      (0x1U << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos      (17U)                                           
+#define CAN_F6R1_FB17_Msk      (0x1U << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos      (18U)                                           
+#define CAN_F6R1_FB18_Msk      (0x1U << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos      (19U)                                           
+#define CAN_F6R1_FB19_Msk      (0x1U << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos      (20U)                                           
+#define CAN_F6R1_FB20_Msk      (0x1U << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos      (21U)                                           
+#define CAN_F6R1_FB21_Msk      (0x1U << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos      (22U)                                           
+#define CAN_F6R1_FB22_Msk      (0x1U << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos      (23U)                                           
+#define CAN_F6R1_FB23_Msk      (0x1U << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos      (24U)                                           
+#define CAN_F6R1_FB24_Msk      (0x1U << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos      (25U)                                           
+#define CAN_F6R1_FB25_Msk      (0x1U << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos      (26U)                                           
+#define CAN_F6R1_FB26_Msk      (0x1U << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos      (27U)                                           
+#define CAN_F6R1_FB27_Msk      (0x1U << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos      (28U)                                           
+#define CAN_F6R1_FB28_Msk      (0x1U << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos      (29U)                                           
+#define CAN_F6R1_FB29_Msk      (0x1U << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos      (30U)                                           
+#define CAN_F6R1_FB30_Msk      (0x1U << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos      (31U)                                           
+#define CAN_F6R1_FB31_Msk      (0x1U << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define CAN_F7R1_FB0_Pos       (0U)                                            
+#define CAN_F7R1_FB0_Msk       (0x1U << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos       (1U)                                            
+#define CAN_F7R1_FB1_Msk       (0x1U << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos       (2U)                                            
+#define CAN_F7R1_FB2_Msk       (0x1U << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos       (3U)                                            
+#define CAN_F7R1_FB3_Msk       (0x1U << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos       (4U)                                            
+#define CAN_F7R1_FB4_Msk       (0x1U << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos       (5U)                                            
+#define CAN_F7R1_FB5_Msk       (0x1U << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos       (6U)                                            
+#define CAN_F7R1_FB6_Msk       (0x1U << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos       (7U)                                            
+#define CAN_F7R1_FB7_Msk       (0x1U << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos       (8U)                                            
+#define CAN_F7R1_FB8_Msk       (0x1U << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos       (9U)                                            
+#define CAN_F7R1_FB9_Msk       (0x1U << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos      (10U)                                           
+#define CAN_F7R1_FB10_Msk      (0x1U << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos      (11U)                                           
+#define CAN_F7R1_FB11_Msk      (0x1U << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos      (12U)                                           
+#define CAN_F7R1_FB12_Msk      (0x1U << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos      (13U)                                           
+#define CAN_F7R1_FB13_Msk      (0x1U << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos      (14U)                                           
+#define CAN_F7R1_FB14_Msk      (0x1U << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos      (15U)                                           
+#define CAN_F7R1_FB15_Msk      (0x1U << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos      (16U)                                           
+#define CAN_F7R1_FB16_Msk      (0x1U << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos      (17U)                                           
+#define CAN_F7R1_FB17_Msk      (0x1U << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos      (18U)                                           
+#define CAN_F7R1_FB18_Msk      (0x1U << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos      (19U)                                           
+#define CAN_F7R1_FB19_Msk      (0x1U << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos      (20U)                                           
+#define CAN_F7R1_FB20_Msk      (0x1U << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos      (21U)                                           
+#define CAN_F7R1_FB21_Msk      (0x1U << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos      (22U)                                           
+#define CAN_F7R1_FB22_Msk      (0x1U << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos      (23U)                                           
+#define CAN_F7R1_FB23_Msk      (0x1U << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos      (24U)                                           
+#define CAN_F7R1_FB24_Msk      (0x1U << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos      (25U)                                           
+#define CAN_F7R1_FB25_Msk      (0x1U << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos      (26U)                                           
+#define CAN_F7R1_FB26_Msk      (0x1U << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos      (27U)                                           
+#define CAN_F7R1_FB27_Msk      (0x1U << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos      (28U)                                           
+#define CAN_F7R1_FB28_Msk      (0x1U << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos      (29U)                                           
+#define CAN_F7R1_FB29_Msk      (0x1U << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos      (30U)                                           
+#define CAN_F7R1_FB30_Msk      (0x1U << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos      (31U)                                           
+#define CAN_F7R1_FB31_Msk      (0x1U << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define CAN_F8R1_FB0_Pos       (0U)                                            
+#define CAN_F8R1_FB0_Msk       (0x1U << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos       (1U)                                            
+#define CAN_F8R1_FB1_Msk       (0x1U << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos       (2U)                                            
+#define CAN_F8R1_FB2_Msk       (0x1U << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos       (3U)                                            
+#define CAN_F8R1_FB3_Msk       (0x1U << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos       (4U)                                            
+#define CAN_F8R1_FB4_Msk       (0x1U << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos       (5U)                                            
+#define CAN_F8R1_FB5_Msk       (0x1U << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos       (6U)                                            
+#define CAN_F8R1_FB6_Msk       (0x1U << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos       (7U)                                            
+#define CAN_F8R1_FB7_Msk       (0x1U << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos       (8U)                                            
+#define CAN_F8R1_FB8_Msk       (0x1U << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos       (9U)                                            
+#define CAN_F8R1_FB9_Msk       (0x1U << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos      (10U)                                           
+#define CAN_F8R1_FB10_Msk      (0x1U << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos      (11U)                                           
+#define CAN_F8R1_FB11_Msk      (0x1U << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos      (12U)                                           
+#define CAN_F8R1_FB12_Msk      (0x1U << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos      (13U)                                           
+#define CAN_F8R1_FB13_Msk      (0x1U << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos      (14U)                                           
+#define CAN_F8R1_FB14_Msk      (0x1U << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos      (15U)                                           
+#define CAN_F8R1_FB15_Msk      (0x1U << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos      (16U)                                           
+#define CAN_F8R1_FB16_Msk      (0x1U << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos      (17U)                                           
+#define CAN_F8R1_FB17_Msk      (0x1U << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos      (18U)                                           
+#define CAN_F8R1_FB18_Msk      (0x1U << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos      (19U)                                           
+#define CAN_F8R1_FB19_Msk      (0x1U << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos      (20U)                                           
+#define CAN_F8R1_FB20_Msk      (0x1U << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos      (21U)                                           
+#define CAN_F8R1_FB21_Msk      (0x1U << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos      (22U)                                           
+#define CAN_F8R1_FB22_Msk      (0x1U << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos      (23U)                                           
+#define CAN_F8R1_FB23_Msk      (0x1U << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos      (24U)                                           
+#define CAN_F8R1_FB24_Msk      (0x1U << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos      (25U)                                           
+#define CAN_F8R1_FB25_Msk      (0x1U << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos      (26U)                                           
+#define CAN_F8R1_FB26_Msk      (0x1U << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos      (27U)                                           
+#define CAN_F8R1_FB27_Msk      (0x1U << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos      (28U)                                           
+#define CAN_F8R1_FB28_Msk      (0x1U << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos      (29U)                                           
+#define CAN_F8R1_FB29_Msk      (0x1U << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos      (30U)                                           
+#define CAN_F8R1_FB30_Msk      (0x1U << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos      (31U)                                           
+#define CAN_F8R1_FB31_Msk      (0x1U << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define CAN_F9R1_FB0_Pos       (0U)                                            
+#define CAN_F9R1_FB0_Msk       (0x1U << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos       (1U)                                            
+#define CAN_F9R1_FB1_Msk       (0x1U << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos       (2U)                                            
+#define CAN_F9R1_FB2_Msk       (0x1U << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos       (3U)                                            
+#define CAN_F9R1_FB3_Msk       (0x1U << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos       (4U)                                            
+#define CAN_F9R1_FB4_Msk       (0x1U << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos       (5U)                                            
+#define CAN_F9R1_FB5_Msk       (0x1U << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos       (6U)                                            
+#define CAN_F9R1_FB6_Msk       (0x1U << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos       (7U)                                            
+#define CAN_F9R1_FB7_Msk       (0x1U << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos       (8U)                                            
+#define CAN_F9R1_FB8_Msk       (0x1U << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos       (9U)                                            
+#define CAN_F9R1_FB9_Msk       (0x1U << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos      (10U)                                           
+#define CAN_F9R1_FB10_Msk      (0x1U << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos      (11U)                                           
+#define CAN_F9R1_FB11_Msk      (0x1U << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos      (12U)                                           
+#define CAN_F9R1_FB12_Msk      (0x1U << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos      (13U)                                           
+#define CAN_F9R1_FB13_Msk      (0x1U << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos      (14U)                                           
+#define CAN_F9R1_FB14_Msk      (0x1U << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos      (15U)                                           
+#define CAN_F9R1_FB15_Msk      (0x1U << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos      (16U)                                           
+#define CAN_F9R1_FB16_Msk      (0x1U << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos      (17U)                                           
+#define CAN_F9R1_FB17_Msk      (0x1U << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos      (18U)                                           
+#define CAN_F9R1_FB18_Msk      (0x1U << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos      (19U)                                           
+#define CAN_F9R1_FB19_Msk      (0x1U << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos      (20U)                                           
+#define CAN_F9R1_FB20_Msk      (0x1U << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos      (21U)                                           
+#define CAN_F9R1_FB21_Msk      (0x1U << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos      (22U)                                           
+#define CAN_F9R1_FB22_Msk      (0x1U << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos      (23U)                                           
+#define CAN_F9R1_FB23_Msk      (0x1U << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos      (24U)                                           
+#define CAN_F9R1_FB24_Msk      (0x1U << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos      (25U)                                           
+#define CAN_F9R1_FB25_Msk      (0x1U << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos      (26U)                                           
+#define CAN_F9R1_FB26_Msk      (0x1U << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos      (27U)                                           
+#define CAN_F9R1_FB27_Msk      (0x1U << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos      (28U)                                           
+#define CAN_F9R1_FB28_Msk      (0x1U << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos      (29U)                                           
+#define CAN_F9R1_FB29_Msk      (0x1U << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos      (30U)                                           
+#define CAN_F9R1_FB30_Msk      (0x1U << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos      (31U)                                           
+#define CAN_F9R1_FB31_Msk      (0x1U << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define CAN_F10R1_FB0_Pos      (0U)                                            
+#define CAN_F10R1_FB0_Msk      (0x1U << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos      (1U)                                            
+#define CAN_F10R1_FB1_Msk      (0x1U << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos      (2U)                                            
+#define CAN_F10R1_FB2_Msk      (0x1U << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos      (3U)                                            
+#define CAN_F10R1_FB3_Msk      (0x1U << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos      (4U)                                            
+#define CAN_F10R1_FB4_Msk      (0x1U << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos      (5U)                                            
+#define CAN_F10R1_FB5_Msk      (0x1U << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos      (6U)                                            
+#define CAN_F10R1_FB6_Msk      (0x1U << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos      (7U)                                            
+#define CAN_F10R1_FB7_Msk      (0x1U << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos      (8U)                                            
+#define CAN_F10R1_FB8_Msk      (0x1U << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos      (9U)                                            
+#define CAN_F10R1_FB9_Msk      (0x1U << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos     (10U)                                           
+#define CAN_F10R1_FB10_Msk     (0x1U << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos     (11U)                                           
+#define CAN_F10R1_FB11_Msk     (0x1U << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos     (12U)                                           
+#define CAN_F10R1_FB12_Msk     (0x1U << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos     (13U)                                           
+#define CAN_F10R1_FB13_Msk     (0x1U << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos     (14U)                                           
+#define CAN_F10R1_FB14_Msk     (0x1U << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos     (15U)                                           
+#define CAN_F10R1_FB15_Msk     (0x1U << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos     (16U)                                           
+#define CAN_F10R1_FB16_Msk     (0x1U << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos     (17U)                                           
+#define CAN_F10R1_FB17_Msk     (0x1U << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos     (18U)                                           
+#define CAN_F10R1_FB18_Msk     (0x1U << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos     (19U)                                           
+#define CAN_F10R1_FB19_Msk     (0x1U << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos     (20U)                                           
+#define CAN_F10R1_FB20_Msk     (0x1U << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos     (21U)                                           
+#define CAN_F10R1_FB21_Msk     (0x1U << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos     (22U)                                           
+#define CAN_F10R1_FB22_Msk     (0x1U << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos     (23U)                                           
+#define CAN_F10R1_FB23_Msk     (0x1U << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos     (24U)                                           
+#define CAN_F10R1_FB24_Msk     (0x1U << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos     (25U)                                           
+#define CAN_F10R1_FB25_Msk     (0x1U << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos     (26U)                                           
+#define CAN_F10R1_FB26_Msk     (0x1U << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos     (27U)                                           
+#define CAN_F10R1_FB27_Msk     (0x1U << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos     (28U)                                           
+#define CAN_F10R1_FB28_Msk     (0x1U << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos     (29U)                                           
+#define CAN_F10R1_FB29_Msk     (0x1U << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos     (30U)                                           
+#define CAN_F10R1_FB30_Msk     (0x1U << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos     (31U)                                           
+#define CAN_F10R1_FB31_Msk     (0x1U << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define CAN_F11R1_FB0_Pos      (0U)                                            
+#define CAN_F11R1_FB0_Msk      (0x1U << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos      (1U)                                            
+#define CAN_F11R1_FB1_Msk      (0x1U << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos      (2U)                                            
+#define CAN_F11R1_FB2_Msk      (0x1U << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos      (3U)                                            
+#define CAN_F11R1_FB3_Msk      (0x1U << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos      (4U)                                            
+#define CAN_F11R1_FB4_Msk      (0x1U << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos      (5U)                                            
+#define CAN_F11R1_FB5_Msk      (0x1U << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos      (6U)                                            
+#define CAN_F11R1_FB6_Msk      (0x1U << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos      (7U)                                            
+#define CAN_F11R1_FB7_Msk      (0x1U << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos      (8U)                                            
+#define CAN_F11R1_FB8_Msk      (0x1U << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos      (9U)                                            
+#define CAN_F11R1_FB9_Msk      (0x1U << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos     (10U)                                           
+#define CAN_F11R1_FB10_Msk     (0x1U << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos     (11U)                                           
+#define CAN_F11R1_FB11_Msk     (0x1U << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos     (12U)                                           
+#define CAN_F11R1_FB12_Msk     (0x1U << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos     (13U)                                           
+#define CAN_F11R1_FB13_Msk     (0x1U << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos     (14U)                                           
+#define CAN_F11R1_FB14_Msk     (0x1U << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos     (15U)                                           
+#define CAN_F11R1_FB15_Msk     (0x1U << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos     (16U)                                           
+#define CAN_F11R1_FB16_Msk     (0x1U << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos     (17U)                                           
+#define CAN_F11R1_FB17_Msk     (0x1U << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos     (18U)                                           
+#define CAN_F11R1_FB18_Msk     (0x1U << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos     (19U)                                           
+#define CAN_F11R1_FB19_Msk     (0x1U << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos     (20U)                                           
+#define CAN_F11R1_FB20_Msk     (0x1U << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos     (21U)                                           
+#define CAN_F11R1_FB21_Msk     (0x1U << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos     (22U)                                           
+#define CAN_F11R1_FB22_Msk     (0x1U << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos     (23U)                                           
+#define CAN_F11R1_FB23_Msk     (0x1U << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos     (24U)                                           
+#define CAN_F11R1_FB24_Msk     (0x1U << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos     (25U)                                           
+#define CAN_F11R1_FB25_Msk     (0x1U << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos     (26U)                                           
+#define CAN_F11R1_FB26_Msk     (0x1U << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos     (27U)                                           
+#define CAN_F11R1_FB27_Msk     (0x1U << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos     (28U)                                           
+#define CAN_F11R1_FB28_Msk     (0x1U << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos     (29U)                                           
+#define CAN_F11R1_FB29_Msk     (0x1U << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos     (30U)                                           
+#define CAN_F11R1_FB30_Msk     (0x1U << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos     (31U)                                           
+#define CAN_F11R1_FB31_Msk     (0x1U << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define CAN_F12R1_FB0_Pos      (0U)                                            
+#define CAN_F12R1_FB0_Msk      (0x1U << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos      (1U)                                            
+#define CAN_F12R1_FB1_Msk      (0x1U << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos      (2U)                                            
+#define CAN_F12R1_FB2_Msk      (0x1U << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos      (3U)                                            
+#define CAN_F12R1_FB3_Msk      (0x1U << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos      (4U)                                            
+#define CAN_F12R1_FB4_Msk      (0x1U << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos      (5U)                                            
+#define CAN_F12R1_FB5_Msk      (0x1U << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos      (6U)                                            
+#define CAN_F12R1_FB6_Msk      (0x1U << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos      (7U)                                            
+#define CAN_F12R1_FB7_Msk      (0x1U << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos      (8U)                                            
+#define CAN_F12R1_FB8_Msk      (0x1U << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos      (9U)                                            
+#define CAN_F12R1_FB9_Msk      (0x1U << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos     (10U)                                           
+#define CAN_F12R1_FB10_Msk     (0x1U << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos     (11U)                                           
+#define CAN_F12R1_FB11_Msk     (0x1U << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos     (12U)                                           
+#define CAN_F12R1_FB12_Msk     (0x1U << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos     (13U)                                           
+#define CAN_F12R1_FB13_Msk     (0x1U << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos     (14U)                                           
+#define CAN_F12R1_FB14_Msk     (0x1U << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos     (15U)                                           
+#define CAN_F12R1_FB15_Msk     (0x1U << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos     (16U)                                           
+#define CAN_F12R1_FB16_Msk     (0x1U << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos     (17U)                                           
+#define CAN_F12R1_FB17_Msk     (0x1U << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos     (18U)                                           
+#define CAN_F12R1_FB18_Msk     (0x1U << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos     (19U)                                           
+#define CAN_F12R1_FB19_Msk     (0x1U << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos     (20U)                                           
+#define CAN_F12R1_FB20_Msk     (0x1U << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos     (21U)                                           
+#define CAN_F12R1_FB21_Msk     (0x1U << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos     (22U)                                           
+#define CAN_F12R1_FB22_Msk     (0x1U << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos     (23U)                                           
+#define CAN_F12R1_FB23_Msk     (0x1U << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos     (24U)                                           
+#define CAN_F12R1_FB24_Msk     (0x1U << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos     (25U)                                           
+#define CAN_F12R1_FB25_Msk     (0x1U << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos     (26U)                                           
+#define CAN_F12R1_FB26_Msk     (0x1U << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos     (27U)                                           
+#define CAN_F12R1_FB27_Msk     (0x1U << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos     (28U)                                           
+#define CAN_F12R1_FB28_Msk     (0x1U << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos     (29U)                                           
+#define CAN_F12R1_FB29_Msk     (0x1U << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos     (30U)                                           
+#define CAN_F12R1_FB30_Msk     (0x1U << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos     (31U)                                           
+#define CAN_F12R1_FB31_Msk     (0x1U << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define CAN_F13R1_FB0_Pos      (0U)                                            
+#define CAN_F13R1_FB0_Msk      (0x1U << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos      (1U)                                            
+#define CAN_F13R1_FB1_Msk      (0x1U << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos      (2U)                                            
+#define CAN_F13R1_FB2_Msk      (0x1U << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos      (3U)                                            
+#define CAN_F13R1_FB3_Msk      (0x1U << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos      (4U)                                            
+#define CAN_F13R1_FB4_Msk      (0x1U << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos      (5U)                                            
+#define CAN_F13R1_FB5_Msk      (0x1U << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos      (6U)                                            
+#define CAN_F13R1_FB6_Msk      (0x1U << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos      (7U)                                            
+#define CAN_F13R1_FB7_Msk      (0x1U << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos      (8U)                                            
+#define CAN_F13R1_FB8_Msk      (0x1U << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos      (9U)                                            
+#define CAN_F13R1_FB9_Msk      (0x1U << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos     (10U)                                           
+#define CAN_F13R1_FB10_Msk     (0x1U << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos     (11U)                                           
+#define CAN_F13R1_FB11_Msk     (0x1U << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos     (12U)                                           
+#define CAN_F13R1_FB12_Msk     (0x1U << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos     (13U)                                           
+#define CAN_F13R1_FB13_Msk     (0x1U << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos     (14U)                                           
+#define CAN_F13R1_FB14_Msk     (0x1U << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos     (15U)                                           
+#define CAN_F13R1_FB15_Msk     (0x1U << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos     (16U)                                           
+#define CAN_F13R1_FB16_Msk     (0x1U << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos     (17U)                                           
+#define CAN_F13R1_FB17_Msk     (0x1U << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos     (18U)                                           
+#define CAN_F13R1_FB18_Msk     (0x1U << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos     (19U)                                           
+#define CAN_F13R1_FB19_Msk     (0x1U << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos     (20U)                                           
+#define CAN_F13R1_FB20_Msk     (0x1U << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos     (21U)                                           
+#define CAN_F13R1_FB21_Msk     (0x1U << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos     (22U)                                           
+#define CAN_F13R1_FB22_Msk     (0x1U << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos     (23U)                                           
+#define CAN_F13R1_FB23_Msk     (0x1U << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos     (24U)                                           
+#define CAN_F13R1_FB24_Msk     (0x1U << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos     (25U)                                           
+#define CAN_F13R1_FB25_Msk     (0x1U << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos     (26U)                                           
+#define CAN_F13R1_FB26_Msk     (0x1U << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos     (27U)                                           
+#define CAN_F13R1_FB27_Msk     (0x1U << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos     (28U)                                           
+#define CAN_F13R1_FB28_Msk     (0x1U << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos     (29U)                                           
+#define CAN_F13R1_FB29_Msk     (0x1U << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos     (30U)                                           
+#define CAN_F13R1_FB30_Msk     (0x1U << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos     (31U)                                           
+#define CAN_F13R1_FB31_Msk     (0x1U << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define CAN_F0R2_FB0_Pos       (0U)                                            
+#define CAN_F0R2_FB0_Msk       (0x1U << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos       (1U)                                            
+#define CAN_F0R2_FB1_Msk       (0x1U << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos       (2U)                                            
+#define CAN_F0R2_FB2_Msk       (0x1U << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos       (3U)                                            
+#define CAN_F0R2_FB3_Msk       (0x1U << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos       (4U)                                            
+#define CAN_F0R2_FB4_Msk       (0x1U << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos       (5U)                                            
+#define CAN_F0R2_FB5_Msk       (0x1U << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos       (6U)                                            
+#define CAN_F0R2_FB6_Msk       (0x1U << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos       (7U)                                            
+#define CAN_F0R2_FB7_Msk       (0x1U << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos       (8U)                                            
+#define CAN_F0R2_FB8_Msk       (0x1U << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos       (9U)                                            
+#define CAN_F0R2_FB9_Msk       (0x1U << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos      (10U)                                           
+#define CAN_F0R2_FB10_Msk      (0x1U << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos      (11U)                                           
+#define CAN_F0R2_FB11_Msk      (0x1U << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos      (12U)                                           
+#define CAN_F0R2_FB12_Msk      (0x1U << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos      (13U)                                           
+#define CAN_F0R2_FB13_Msk      (0x1U << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos      (14U)                                           
+#define CAN_F0R2_FB14_Msk      (0x1U << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos      (15U)                                           
+#define CAN_F0R2_FB15_Msk      (0x1U << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos      (16U)                                           
+#define CAN_F0R2_FB16_Msk      (0x1U << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos      (17U)                                           
+#define CAN_F0R2_FB17_Msk      (0x1U << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos      (18U)                                           
+#define CAN_F0R2_FB18_Msk      (0x1U << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos      (19U)                                           
+#define CAN_F0R2_FB19_Msk      (0x1U << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos      (20U)                                           
+#define CAN_F0R2_FB20_Msk      (0x1U << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos      (21U)                                           
+#define CAN_F0R2_FB21_Msk      (0x1U << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos      (22U)                                           
+#define CAN_F0R2_FB22_Msk      (0x1U << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos      (23U)                                           
+#define CAN_F0R2_FB23_Msk      (0x1U << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos      (24U)                                           
+#define CAN_F0R2_FB24_Msk      (0x1U << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos      (25U)                                           
+#define CAN_F0R2_FB25_Msk      (0x1U << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos      (26U)                                           
+#define CAN_F0R2_FB26_Msk      (0x1U << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos      (27U)                                           
+#define CAN_F0R2_FB27_Msk      (0x1U << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos      (28U)                                           
+#define CAN_F0R2_FB28_Msk      (0x1U << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos      (29U)                                           
+#define CAN_F0R2_FB29_Msk      (0x1U << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos      (30U)                                           
+#define CAN_F0R2_FB30_Msk      (0x1U << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos      (31U)                                           
+#define CAN_F0R2_FB31_Msk      (0x1U << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define CAN_F1R2_FB0_Pos       (0U)                                            
+#define CAN_F1R2_FB0_Msk       (0x1U << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos       (1U)                                            
+#define CAN_F1R2_FB1_Msk       (0x1U << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos       (2U)                                            
+#define CAN_F1R2_FB2_Msk       (0x1U << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos       (3U)                                            
+#define CAN_F1R2_FB3_Msk       (0x1U << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos       (4U)                                            
+#define CAN_F1R2_FB4_Msk       (0x1U << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos       (5U)                                            
+#define CAN_F1R2_FB5_Msk       (0x1U << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos       (6U)                                            
+#define CAN_F1R2_FB6_Msk       (0x1U << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos       (7U)                                            
+#define CAN_F1R2_FB7_Msk       (0x1U << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos       (8U)                                            
+#define CAN_F1R2_FB8_Msk       (0x1U << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos       (9U)                                            
+#define CAN_F1R2_FB9_Msk       (0x1U << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos      (10U)                                           
+#define CAN_F1R2_FB10_Msk      (0x1U << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos      (11U)                                           
+#define CAN_F1R2_FB11_Msk      (0x1U << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos      (12U)                                           
+#define CAN_F1R2_FB12_Msk      (0x1U << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos      (13U)                                           
+#define CAN_F1R2_FB13_Msk      (0x1U << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos      (14U)                                           
+#define CAN_F1R2_FB14_Msk      (0x1U << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos      (15U)                                           
+#define CAN_F1R2_FB15_Msk      (0x1U << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos      (16U)                                           
+#define CAN_F1R2_FB16_Msk      (0x1U << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos      (17U)                                           
+#define CAN_F1R2_FB17_Msk      (0x1U << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos      (18U)                                           
+#define CAN_F1R2_FB18_Msk      (0x1U << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos      (19U)                                           
+#define CAN_F1R2_FB19_Msk      (0x1U << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos      (20U)                                           
+#define CAN_F1R2_FB20_Msk      (0x1U << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos      (21U)                                           
+#define CAN_F1R2_FB21_Msk      (0x1U << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos      (22U)                                           
+#define CAN_F1R2_FB22_Msk      (0x1U << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos      (23U)                                           
+#define CAN_F1R2_FB23_Msk      (0x1U << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos      (24U)                                           
+#define CAN_F1R2_FB24_Msk      (0x1U << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos      (25U)                                           
+#define CAN_F1R2_FB25_Msk      (0x1U << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos      (26U)                                           
+#define CAN_F1R2_FB26_Msk      (0x1U << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos      (27U)                                           
+#define CAN_F1R2_FB27_Msk      (0x1U << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos      (28U)                                           
+#define CAN_F1R2_FB28_Msk      (0x1U << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos      (29U)                                           
+#define CAN_F1R2_FB29_Msk      (0x1U << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos      (30U)                                           
+#define CAN_F1R2_FB30_Msk      (0x1U << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos      (31U)                                           
+#define CAN_F1R2_FB31_Msk      (0x1U << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define CAN_F2R2_FB0_Pos       (0U)                                            
+#define CAN_F2R2_FB0_Msk       (0x1U << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos       (1U)                                            
+#define CAN_F2R2_FB1_Msk       (0x1U << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos       (2U)                                            
+#define CAN_F2R2_FB2_Msk       (0x1U << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos       (3U)                                            
+#define CAN_F2R2_FB3_Msk       (0x1U << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos       (4U)                                            
+#define CAN_F2R2_FB4_Msk       (0x1U << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos       (5U)                                            
+#define CAN_F2R2_FB5_Msk       (0x1U << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos       (6U)                                            
+#define CAN_F2R2_FB6_Msk       (0x1U << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos       (7U)                                            
+#define CAN_F2R2_FB7_Msk       (0x1U << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos       (8U)                                            
+#define CAN_F2R2_FB8_Msk       (0x1U << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos       (9U)                                            
+#define CAN_F2R2_FB9_Msk       (0x1U << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos      (10U)                                           
+#define CAN_F2R2_FB10_Msk      (0x1U << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos      (11U)                                           
+#define CAN_F2R2_FB11_Msk      (0x1U << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos      (12U)                                           
+#define CAN_F2R2_FB12_Msk      (0x1U << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos      (13U)                                           
+#define CAN_F2R2_FB13_Msk      (0x1U << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos      (14U)                                           
+#define CAN_F2R2_FB14_Msk      (0x1U << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos      (15U)                                           
+#define CAN_F2R2_FB15_Msk      (0x1U << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos      (16U)                                           
+#define CAN_F2R2_FB16_Msk      (0x1U << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos      (17U)                                           
+#define CAN_F2R2_FB17_Msk      (0x1U << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos      (18U)                                           
+#define CAN_F2R2_FB18_Msk      (0x1U << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos      (19U)                                           
+#define CAN_F2R2_FB19_Msk      (0x1U << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos      (20U)                                           
+#define CAN_F2R2_FB20_Msk      (0x1U << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos      (21U)                                           
+#define CAN_F2R2_FB21_Msk      (0x1U << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos      (22U)                                           
+#define CAN_F2R2_FB22_Msk      (0x1U << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos      (23U)                                           
+#define CAN_F2R2_FB23_Msk      (0x1U << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos      (24U)                                           
+#define CAN_F2R2_FB24_Msk      (0x1U << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos      (25U)                                           
+#define CAN_F2R2_FB25_Msk      (0x1U << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos      (26U)                                           
+#define CAN_F2R2_FB26_Msk      (0x1U << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos      (27U)                                           
+#define CAN_F2R2_FB27_Msk      (0x1U << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos      (28U)                                           
+#define CAN_F2R2_FB28_Msk      (0x1U << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos      (29U)                                           
+#define CAN_F2R2_FB29_Msk      (0x1U << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos      (30U)                                           
+#define CAN_F2R2_FB30_Msk      (0x1U << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos      (31U)                                           
+#define CAN_F2R2_FB31_Msk      (0x1U << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define CAN_F3R2_FB0_Pos       (0U)                                            
+#define CAN_F3R2_FB0_Msk       (0x1U << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos       (1U)                                            
+#define CAN_F3R2_FB1_Msk       (0x1U << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos       (2U)                                            
+#define CAN_F3R2_FB2_Msk       (0x1U << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos       (3U)                                            
+#define CAN_F3R2_FB3_Msk       (0x1U << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos       (4U)                                            
+#define CAN_F3R2_FB4_Msk       (0x1U << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos       (5U)                                            
+#define CAN_F3R2_FB5_Msk       (0x1U << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos       (6U)                                            
+#define CAN_F3R2_FB6_Msk       (0x1U << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos       (7U)                                            
+#define CAN_F3R2_FB7_Msk       (0x1U << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos       (8U)                                            
+#define CAN_F3R2_FB8_Msk       (0x1U << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos       (9U)                                            
+#define CAN_F3R2_FB9_Msk       (0x1U << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos      (10U)                                           
+#define CAN_F3R2_FB10_Msk      (0x1U << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos      (11U)                                           
+#define CAN_F3R2_FB11_Msk      (0x1U << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos      (12U)                                           
+#define CAN_F3R2_FB12_Msk      (0x1U << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos      (13U)                                           
+#define CAN_F3R2_FB13_Msk      (0x1U << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos      (14U)                                           
+#define CAN_F3R2_FB14_Msk      (0x1U << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos      (15U)                                           
+#define CAN_F3R2_FB15_Msk      (0x1U << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos      (16U)                                           
+#define CAN_F3R2_FB16_Msk      (0x1U << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos      (17U)                                           
+#define CAN_F3R2_FB17_Msk      (0x1U << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos      (18U)                                           
+#define CAN_F3R2_FB18_Msk      (0x1U << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos      (19U)                                           
+#define CAN_F3R2_FB19_Msk      (0x1U << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos      (20U)                                           
+#define CAN_F3R2_FB20_Msk      (0x1U << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos      (21U)                                           
+#define CAN_F3R2_FB21_Msk      (0x1U << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos      (22U)                                           
+#define CAN_F3R2_FB22_Msk      (0x1U << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos      (23U)                                           
+#define CAN_F3R2_FB23_Msk      (0x1U << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos      (24U)                                           
+#define CAN_F3R2_FB24_Msk      (0x1U << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos      (25U)                                           
+#define CAN_F3R2_FB25_Msk      (0x1U << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos      (26U)                                           
+#define CAN_F3R2_FB26_Msk      (0x1U << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos      (27U)                                           
+#define CAN_F3R2_FB27_Msk      (0x1U << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos      (28U)                                           
+#define CAN_F3R2_FB28_Msk      (0x1U << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos      (29U)                                           
+#define CAN_F3R2_FB29_Msk      (0x1U << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos      (30U)                                           
+#define CAN_F3R2_FB30_Msk      (0x1U << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos      (31U)                                           
+#define CAN_F3R2_FB31_Msk      (0x1U << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define CAN_F4R2_FB0_Pos       (0U)                                            
+#define CAN_F4R2_FB0_Msk       (0x1U << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos       (1U)                                            
+#define CAN_F4R2_FB1_Msk       (0x1U << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos       (2U)                                            
+#define CAN_F4R2_FB2_Msk       (0x1U << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos       (3U)                                            
+#define CAN_F4R2_FB3_Msk       (0x1U << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos       (4U)                                            
+#define CAN_F4R2_FB4_Msk       (0x1U << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos       (5U)                                            
+#define CAN_F4R2_FB5_Msk       (0x1U << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos       (6U)                                            
+#define CAN_F4R2_FB6_Msk       (0x1U << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos       (7U)                                            
+#define CAN_F4R2_FB7_Msk       (0x1U << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos       (8U)                                            
+#define CAN_F4R2_FB8_Msk       (0x1U << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos       (9U)                                            
+#define CAN_F4R2_FB9_Msk       (0x1U << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos      (10U)                                           
+#define CAN_F4R2_FB10_Msk      (0x1U << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos      (11U)                                           
+#define CAN_F4R2_FB11_Msk      (0x1U << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos      (12U)                                           
+#define CAN_F4R2_FB12_Msk      (0x1U << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos      (13U)                                           
+#define CAN_F4R2_FB13_Msk      (0x1U << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos      (14U)                                           
+#define CAN_F4R2_FB14_Msk      (0x1U << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos      (15U)                                           
+#define CAN_F4R2_FB15_Msk      (0x1U << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos      (16U)                                           
+#define CAN_F4R2_FB16_Msk      (0x1U << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos      (17U)                                           
+#define CAN_F4R2_FB17_Msk      (0x1U << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos      (18U)                                           
+#define CAN_F4R2_FB18_Msk      (0x1U << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos      (19U)                                           
+#define CAN_F4R2_FB19_Msk      (0x1U << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos      (20U)                                           
+#define CAN_F4R2_FB20_Msk      (0x1U << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos      (21U)                                           
+#define CAN_F4R2_FB21_Msk      (0x1U << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos      (22U)                                           
+#define CAN_F4R2_FB22_Msk      (0x1U << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos      (23U)                                           
+#define CAN_F4R2_FB23_Msk      (0x1U << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos      (24U)                                           
+#define CAN_F4R2_FB24_Msk      (0x1U << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos      (25U)                                           
+#define CAN_F4R2_FB25_Msk      (0x1U << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos      (26U)                                           
+#define CAN_F4R2_FB26_Msk      (0x1U << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos      (27U)                                           
+#define CAN_F4R2_FB27_Msk      (0x1U << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos      (28U)                                           
+#define CAN_F4R2_FB28_Msk      (0x1U << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos      (29U)                                           
+#define CAN_F4R2_FB29_Msk      (0x1U << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos      (30U)                                           
+#define CAN_F4R2_FB30_Msk      (0x1U << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos      (31U)                                           
+#define CAN_F4R2_FB31_Msk      (0x1U << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define CAN_F5R2_FB0_Pos       (0U)                                            
+#define CAN_F5R2_FB0_Msk       (0x1U << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos       (1U)                                            
+#define CAN_F5R2_FB1_Msk       (0x1U << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos       (2U)                                            
+#define CAN_F5R2_FB2_Msk       (0x1U << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos       (3U)                                            
+#define CAN_F5R2_FB3_Msk       (0x1U << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos       (4U)                                            
+#define CAN_F5R2_FB4_Msk       (0x1U << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos       (5U)                                            
+#define CAN_F5R2_FB5_Msk       (0x1U << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos       (6U)                                            
+#define CAN_F5R2_FB6_Msk       (0x1U << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos       (7U)                                            
+#define CAN_F5R2_FB7_Msk       (0x1U << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos       (8U)                                            
+#define CAN_F5R2_FB8_Msk       (0x1U << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos       (9U)                                            
+#define CAN_F5R2_FB9_Msk       (0x1U << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos      (10U)                                           
+#define CAN_F5R2_FB10_Msk      (0x1U << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos      (11U)                                           
+#define CAN_F5R2_FB11_Msk      (0x1U << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos      (12U)                                           
+#define CAN_F5R2_FB12_Msk      (0x1U << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos      (13U)                                           
+#define CAN_F5R2_FB13_Msk      (0x1U << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos      (14U)                                           
+#define CAN_F5R2_FB14_Msk      (0x1U << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos      (15U)                                           
+#define CAN_F5R2_FB15_Msk      (0x1U << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos      (16U)                                           
+#define CAN_F5R2_FB16_Msk      (0x1U << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos      (17U)                                           
+#define CAN_F5R2_FB17_Msk      (0x1U << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos      (18U)                                           
+#define CAN_F5R2_FB18_Msk      (0x1U << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos      (19U)                                           
+#define CAN_F5R2_FB19_Msk      (0x1U << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos      (20U)                                           
+#define CAN_F5R2_FB20_Msk      (0x1U << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos      (21U)                                           
+#define CAN_F5R2_FB21_Msk      (0x1U << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos      (22U)                                           
+#define CAN_F5R2_FB22_Msk      (0x1U << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos      (23U)                                           
+#define CAN_F5R2_FB23_Msk      (0x1U << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos      (24U)                                           
+#define CAN_F5R2_FB24_Msk      (0x1U << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos      (25U)                                           
+#define CAN_F5R2_FB25_Msk      (0x1U << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos      (26U)                                           
+#define CAN_F5R2_FB26_Msk      (0x1U << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos      (27U)                                           
+#define CAN_F5R2_FB27_Msk      (0x1U << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos      (28U)                                           
+#define CAN_F5R2_FB28_Msk      (0x1U << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos      (29U)                                           
+#define CAN_F5R2_FB29_Msk      (0x1U << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos      (30U)                                           
+#define CAN_F5R2_FB30_Msk      (0x1U << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos      (31U)                                           
+#define CAN_F5R2_FB31_Msk      (0x1U << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define CAN_F6R2_FB0_Pos       (0U)                                            
+#define CAN_F6R2_FB0_Msk       (0x1U << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos       (1U)                                            
+#define CAN_F6R2_FB1_Msk       (0x1U << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos       (2U)                                            
+#define CAN_F6R2_FB2_Msk       (0x1U << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos       (3U)                                            
+#define CAN_F6R2_FB3_Msk       (0x1U << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos       (4U)                                            
+#define CAN_F6R2_FB4_Msk       (0x1U << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos       (5U)                                            
+#define CAN_F6R2_FB5_Msk       (0x1U << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos       (6U)                                            
+#define CAN_F6R2_FB6_Msk       (0x1U << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos       (7U)                                            
+#define CAN_F6R2_FB7_Msk       (0x1U << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos       (8U)                                            
+#define CAN_F6R2_FB8_Msk       (0x1U << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos       (9U)                                            
+#define CAN_F6R2_FB9_Msk       (0x1U << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos      (10U)                                           
+#define CAN_F6R2_FB10_Msk      (0x1U << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos      (11U)                                           
+#define CAN_F6R2_FB11_Msk      (0x1U << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos      (12U)                                           
+#define CAN_F6R2_FB12_Msk      (0x1U << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos      (13U)                                           
+#define CAN_F6R2_FB13_Msk      (0x1U << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos      (14U)                                           
+#define CAN_F6R2_FB14_Msk      (0x1U << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos      (15U)                                           
+#define CAN_F6R2_FB15_Msk      (0x1U << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos      (16U)                                           
+#define CAN_F6R2_FB16_Msk      (0x1U << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos      (17U)                                           
+#define CAN_F6R2_FB17_Msk      (0x1U << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos      (18U)                                           
+#define CAN_F6R2_FB18_Msk      (0x1U << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos      (19U)                                           
+#define CAN_F6R2_FB19_Msk      (0x1U << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos      (20U)                                           
+#define CAN_F6R2_FB20_Msk      (0x1U << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos      (21U)                                           
+#define CAN_F6R2_FB21_Msk      (0x1U << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos      (22U)                                           
+#define CAN_F6R2_FB22_Msk      (0x1U << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos      (23U)                                           
+#define CAN_F6R2_FB23_Msk      (0x1U << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos      (24U)                                           
+#define CAN_F6R2_FB24_Msk      (0x1U << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos      (25U)                                           
+#define CAN_F6R2_FB25_Msk      (0x1U << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos      (26U)                                           
+#define CAN_F6R2_FB26_Msk      (0x1U << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos      (27U)                                           
+#define CAN_F6R2_FB27_Msk      (0x1U << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos      (28U)                                           
+#define CAN_F6R2_FB28_Msk      (0x1U << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos      (29U)                                           
+#define CAN_F6R2_FB29_Msk      (0x1U << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos      (30U)                                           
+#define CAN_F6R2_FB30_Msk      (0x1U << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos      (31U)                                           
+#define CAN_F6R2_FB31_Msk      (0x1U << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define CAN_F7R2_FB0_Pos       (0U)                                            
+#define CAN_F7R2_FB0_Msk       (0x1U << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos       (1U)                                            
+#define CAN_F7R2_FB1_Msk       (0x1U << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos       (2U)                                            
+#define CAN_F7R2_FB2_Msk       (0x1U << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos       (3U)                                            
+#define CAN_F7R2_FB3_Msk       (0x1U << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos       (4U)                                            
+#define CAN_F7R2_FB4_Msk       (0x1U << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos       (5U)                                            
+#define CAN_F7R2_FB5_Msk       (0x1U << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos       (6U)                                            
+#define CAN_F7R2_FB6_Msk       (0x1U << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos       (7U)                                            
+#define CAN_F7R2_FB7_Msk       (0x1U << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos       (8U)                                            
+#define CAN_F7R2_FB8_Msk       (0x1U << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos       (9U)                                            
+#define CAN_F7R2_FB9_Msk       (0x1U << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos      (10U)                                           
+#define CAN_F7R2_FB10_Msk      (0x1U << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos      (11U)                                           
+#define CAN_F7R2_FB11_Msk      (0x1U << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos      (12U)                                           
+#define CAN_F7R2_FB12_Msk      (0x1U << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos      (13U)                                           
+#define CAN_F7R2_FB13_Msk      (0x1U << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos      (14U)                                           
+#define CAN_F7R2_FB14_Msk      (0x1U << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos      (15U)                                           
+#define CAN_F7R2_FB15_Msk      (0x1U << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos      (16U)                                           
+#define CAN_F7R2_FB16_Msk      (0x1U << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos      (17U)                                           
+#define CAN_F7R2_FB17_Msk      (0x1U << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos      (18U)                                           
+#define CAN_F7R2_FB18_Msk      (0x1U << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos      (19U)                                           
+#define CAN_F7R2_FB19_Msk      (0x1U << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos      (20U)                                           
+#define CAN_F7R2_FB20_Msk      (0x1U << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos      (21U)                                           
+#define CAN_F7R2_FB21_Msk      (0x1U << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos      (22U)                                           
+#define CAN_F7R2_FB22_Msk      (0x1U << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos      (23U)                                           
+#define CAN_F7R2_FB23_Msk      (0x1U << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos      (24U)                                           
+#define CAN_F7R2_FB24_Msk      (0x1U << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos      (25U)                                           
+#define CAN_F7R2_FB25_Msk      (0x1U << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos      (26U)                                           
+#define CAN_F7R2_FB26_Msk      (0x1U << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos      (27U)                                           
+#define CAN_F7R2_FB27_Msk      (0x1U << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos      (28U)                                           
+#define CAN_F7R2_FB28_Msk      (0x1U << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos      (29U)                                           
+#define CAN_F7R2_FB29_Msk      (0x1U << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos      (30U)                                           
+#define CAN_F7R2_FB30_Msk      (0x1U << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos      (31U)                                           
+#define CAN_F7R2_FB31_Msk      (0x1U << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define CAN_F8R2_FB0_Pos       (0U)                                            
+#define CAN_F8R2_FB0_Msk       (0x1U << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos       (1U)                                            
+#define CAN_F8R2_FB1_Msk       (0x1U << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos       (2U)                                            
+#define CAN_F8R2_FB2_Msk       (0x1U << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos       (3U)                                            
+#define CAN_F8R2_FB3_Msk       (0x1U << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos       (4U)                                            
+#define CAN_F8R2_FB4_Msk       (0x1U << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos       (5U)                                            
+#define CAN_F8R2_FB5_Msk       (0x1U << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos       (6U)                                            
+#define CAN_F8R2_FB6_Msk       (0x1U << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos       (7U)                                            
+#define CAN_F8R2_FB7_Msk       (0x1U << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos       (8U)                                            
+#define CAN_F8R2_FB8_Msk       (0x1U << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos       (9U)                                            
+#define CAN_F8R2_FB9_Msk       (0x1U << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos      (10U)                                           
+#define CAN_F8R2_FB10_Msk      (0x1U << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos      (11U)                                           
+#define CAN_F8R2_FB11_Msk      (0x1U << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos      (12U)                                           
+#define CAN_F8R2_FB12_Msk      (0x1U << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos      (13U)                                           
+#define CAN_F8R2_FB13_Msk      (0x1U << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos      (14U)                                           
+#define CAN_F8R2_FB14_Msk      (0x1U << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos      (15U)                                           
+#define CAN_F8R2_FB15_Msk      (0x1U << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos      (16U)                                           
+#define CAN_F8R2_FB16_Msk      (0x1U << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos      (17U)                                           
+#define CAN_F8R2_FB17_Msk      (0x1U << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos      (18U)                                           
+#define CAN_F8R2_FB18_Msk      (0x1U << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos      (19U)                                           
+#define CAN_F8R2_FB19_Msk      (0x1U << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos      (20U)                                           
+#define CAN_F8R2_FB20_Msk      (0x1U << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos      (21U)                                           
+#define CAN_F8R2_FB21_Msk      (0x1U << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos      (22U)                                           
+#define CAN_F8R2_FB22_Msk      (0x1U << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos      (23U)                                           
+#define CAN_F8R2_FB23_Msk      (0x1U << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos      (24U)                                           
+#define CAN_F8R2_FB24_Msk      (0x1U << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos      (25U)                                           
+#define CAN_F8R2_FB25_Msk      (0x1U << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos      (26U)                                           
+#define CAN_F8R2_FB26_Msk      (0x1U << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos      (27U)                                           
+#define CAN_F8R2_FB27_Msk      (0x1U << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos      (28U)                                           
+#define CAN_F8R2_FB28_Msk      (0x1U << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos      (29U)                                           
+#define CAN_F8R2_FB29_Msk      (0x1U << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos      (30U)                                           
+#define CAN_F8R2_FB30_Msk      (0x1U << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos      (31U)                                           
+#define CAN_F8R2_FB31_Msk      (0x1U << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define CAN_F9R2_FB0_Pos       (0U)                                            
+#define CAN_F9R2_FB0_Msk       (0x1U << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos       (1U)                                            
+#define CAN_F9R2_FB1_Msk       (0x1U << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos       (2U)                                            
+#define CAN_F9R2_FB2_Msk       (0x1U << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos       (3U)                                            
+#define CAN_F9R2_FB3_Msk       (0x1U << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos       (4U)                                            
+#define CAN_F9R2_FB4_Msk       (0x1U << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos       (5U)                                            
+#define CAN_F9R2_FB5_Msk       (0x1U << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos       (6U)                                            
+#define CAN_F9R2_FB6_Msk       (0x1U << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos       (7U)                                            
+#define CAN_F9R2_FB7_Msk       (0x1U << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos       (8U)                                            
+#define CAN_F9R2_FB8_Msk       (0x1U << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos       (9U)                                            
+#define CAN_F9R2_FB9_Msk       (0x1U << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos      (10U)                                           
+#define CAN_F9R2_FB10_Msk      (0x1U << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos      (11U)                                           
+#define CAN_F9R2_FB11_Msk      (0x1U << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos      (12U)                                           
+#define CAN_F9R2_FB12_Msk      (0x1U << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos      (13U)                                           
+#define CAN_F9R2_FB13_Msk      (0x1U << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos      (14U)                                           
+#define CAN_F9R2_FB14_Msk      (0x1U << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos      (15U)                                           
+#define CAN_F9R2_FB15_Msk      (0x1U << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos      (16U)                                           
+#define CAN_F9R2_FB16_Msk      (0x1U << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos      (17U)                                           
+#define CAN_F9R2_FB17_Msk      (0x1U << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos      (18U)                                           
+#define CAN_F9R2_FB18_Msk      (0x1U << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos      (19U)                                           
+#define CAN_F9R2_FB19_Msk      (0x1U << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos      (20U)                                           
+#define CAN_F9R2_FB20_Msk      (0x1U << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos      (21U)                                           
+#define CAN_F9R2_FB21_Msk      (0x1U << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos      (22U)                                           
+#define CAN_F9R2_FB22_Msk      (0x1U << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos      (23U)                                           
+#define CAN_F9R2_FB23_Msk      (0x1U << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos      (24U)                                           
+#define CAN_F9R2_FB24_Msk      (0x1U << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos      (25U)                                           
+#define CAN_F9R2_FB25_Msk      (0x1U << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos      (26U)                                           
+#define CAN_F9R2_FB26_Msk      (0x1U << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos      (27U)                                           
+#define CAN_F9R2_FB27_Msk      (0x1U << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos      (28U)                                           
+#define CAN_F9R2_FB28_Msk      (0x1U << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos      (29U)                                           
+#define CAN_F9R2_FB29_Msk      (0x1U << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos      (30U)                                           
+#define CAN_F9R2_FB30_Msk      (0x1U << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos      (31U)                                           
+#define CAN_F9R2_FB31_Msk      (0x1U << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define CAN_F10R2_FB0_Pos      (0U)                                            
+#define CAN_F10R2_FB0_Msk      (0x1U << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos      (1U)                                            
+#define CAN_F10R2_FB1_Msk      (0x1U << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos      (2U)                                            
+#define CAN_F10R2_FB2_Msk      (0x1U << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos      (3U)                                            
+#define CAN_F10R2_FB3_Msk      (0x1U << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos      (4U)                                            
+#define CAN_F10R2_FB4_Msk      (0x1U << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos      (5U)                                            
+#define CAN_F10R2_FB5_Msk      (0x1U << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos      (6U)                                            
+#define CAN_F10R2_FB6_Msk      (0x1U << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos      (7U)                                            
+#define CAN_F10R2_FB7_Msk      (0x1U << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos      (8U)                                            
+#define CAN_F10R2_FB8_Msk      (0x1U << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos      (9U)                                            
+#define CAN_F10R2_FB9_Msk      (0x1U << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos     (10U)                                           
+#define CAN_F10R2_FB10_Msk     (0x1U << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos     (11U)                                           
+#define CAN_F10R2_FB11_Msk     (0x1U << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos     (12U)                                           
+#define CAN_F10R2_FB12_Msk     (0x1U << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos     (13U)                                           
+#define CAN_F10R2_FB13_Msk     (0x1U << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos     (14U)                                           
+#define CAN_F10R2_FB14_Msk     (0x1U << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos     (15U)                                           
+#define CAN_F10R2_FB15_Msk     (0x1U << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos     (16U)                                           
+#define CAN_F10R2_FB16_Msk     (0x1U << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos     (17U)                                           
+#define CAN_F10R2_FB17_Msk     (0x1U << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos     (18U)                                           
+#define CAN_F10R2_FB18_Msk     (0x1U << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos     (19U)                                           
+#define CAN_F10R2_FB19_Msk     (0x1U << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos     (20U)                                           
+#define CAN_F10R2_FB20_Msk     (0x1U << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos     (21U)                                           
+#define CAN_F10R2_FB21_Msk     (0x1U << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos     (22U)                                           
+#define CAN_F10R2_FB22_Msk     (0x1U << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos     (23U)                                           
+#define CAN_F10R2_FB23_Msk     (0x1U << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos     (24U)                                           
+#define CAN_F10R2_FB24_Msk     (0x1U << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos     (25U)                                           
+#define CAN_F10R2_FB25_Msk     (0x1U << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos     (26U)                                           
+#define CAN_F10R2_FB26_Msk     (0x1U << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos     (27U)                                           
+#define CAN_F10R2_FB27_Msk     (0x1U << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos     (28U)                                           
+#define CAN_F10R2_FB28_Msk     (0x1U << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos     (29U)                                           
+#define CAN_F10R2_FB29_Msk     (0x1U << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos     (30U)                                           
+#define CAN_F10R2_FB30_Msk     (0x1U << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos     (31U)                                           
+#define CAN_F10R2_FB31_Msk     (0x1U << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define CAN_F11R2_FB0_Pos      (0U)                                            
+#define CAN_F11R2_FB0_Msk      (0x1U << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos      (1U)                                            
+#define CAN_F11R2_FB1_Msk      (0x1U << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos      (2U)                                            
+#define CAN_F11R2_FB2_Msk      (0x1U << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos      (3U)                                            
+#define CAN_F11R2_FB3_Msk      (0x1U << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos      (4U)                                            
+#define CAN_F11R2_FB4_Msk      (0x1U << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos      (5U)                                            
+#define CAN_F11R2_FB5_Msk      (0x1U << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos      (6U)                                            
+#define CAN_F11R2_FB6_Msk      (0x1U << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos      (7U)                                            
+#define CAN_F11R2_FB7_Msk      (0x1U << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos      (8U)                                            
+#define CAN_F11R2_FB8_Msk      (0x1U << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos      (9U)                                            
+#define CAN_F11R2_FB9_Msk      (0x1U << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos     (10U)                                           
+#define CAN_F11R2_FB10_Msk     (0x1U << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos     (11U)                                           
+#define CAN_F11R2_FB11_Msk     (0x1U << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos     (12U)                                           
+#define CAN_F11R2_FB12_Msk     (0x1U << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos     (13U)                                           
+#define CAN_F11R2_FB13_Msk     (0x1U << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos     (14U)                                           
+#define CAN_F11R2_FB14_Msk     (0x1U << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos     (15U)                                           
+#define CAN_F11R2_FB15_Msk     (0x1U << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos     (16U)                                           
+#define CAN_F11R2_FB16_Msk     (0x1U << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos     (17U)                                           
+#define CAN_F11R2_FB17_Msk     (0x1U << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos     (18U)                                           
+#define CAN_F11R2_FB18_Msk     (0x1U << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos     (19U)                                           
+#define CAN_F11R2_FB19_Msk     (0x1U << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos     (20U)                                           
+#define CAN_F11R2_FB20_Msk     (0x1U << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos     (21U)                                           
+#define CAN_F11R2_FB21_Msk     (0x1U << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos     (22U)                                           
+#define CAN_F11R2_FB22_Msk     (0x1U << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos     (23U)                                           
+#define CAN_F11R2_FB23_Msk     (0x1U << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos     (24U)                                           
+#define CAN_F11R2_FB24_Msk     (0x1U << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos     (25U)                                           
+#define CAN_F11R2_FB25_Msk     (0x1U << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos     (26U)                                           
+#define CAN_F11R2_FB26_Msk     (0x1U << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos     (27U)                                           
+#define CAN_F11R2_FB27_Msk     (0x1U << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos     (28U)                                           
+#define CAN_F11R2_FB28_Msk     (0x1U << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos     (29U)                                           
+#define CAN_F11R2_FB29_Msk     (0x1U << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos     (30U)                                           
+#define CAN_F11R2_FB30_Msk     (0x1U << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos     (31U)                                           
+#define CAN_F11R2_FB31_Msk     (0x1U << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define CAN_F12R2_FB0_Pos      (0U)                                            
+#define CAN_F12R2_FB0_Msk      (0x1U << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos      (1U)                                            
+#define CAN_F12R2_FB1_Msk      (0x1U << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos      (2U)                                            
+#define CAN_F12R2_FB2_Msk      (0x1U << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos      (3U)                                            
+#define CAN_F12R2_FB3_Msk      (0x1U << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos      (4U)                                            
+#define CAN_F12R2_FB4_Msk      (0x1U << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos      (5U)                                            
+#define CAN_F12R2_FB5_Msk      (0x1U << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos      (6U)                                            
+#define CAN_F12R2_FB6_Msk      (0x1U << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos      (7U)                                            
+#define CAN_F12R2_FB7_Msk      (0x1U << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos      (8U)                                            
+#define CAN_F12R2_FB8_Msk      (0x1U << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos      (9U)                                            
+#define CAN_F12R2_FB9_Msk      (0x1U << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos     (10U)                                           
+#define CAN_F12R2_FB10_Msk     (0x1U << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos     (11U)                                           
+#define CAN_F12R2_FB11_Msk     (0x1U << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos     (12U)                                           
+#define CAN_F12R2_FB12_Msk     (0x1U << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos     (13U)                                           
+#define CAN_F12R2_FB13_Msk     (0x1U << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos     (14U)                                           
+#define CAN_F12R2_FB14_Msk     (0x1U << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos     (15U)                                           
+#define CAN_F12R2_FB15_Msk     (0x1U << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos     (16U)                                           
+#define CAN_F12R2_FB16_Msk     (0x1U << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos     (17U)                                           
+#define CAN_F12R2_FB17_Msk     (0x1U << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos     (18U)                                           
+#define CAN_F12R2_FB18_Msk     (0x1U << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos     (19U)                                           
+#define CAN_F12R2_FB19_Msk     (0x1U << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos     (20U)                                           
+#define CAN_F12R2_FB20_Msk     (0x1U << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos     (21U)                                           
+#define CAN_F12R2_FB21_Msk     (0x1U << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos     (22U)                                           
+#define CAN_F12R2_FB22_Msk     (0x1U << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos     (23U)                                           
+#define CAN_F12R2_FB23_Msk     (0x1U << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos     (24U)                                           
+#define CAN_F12R2_FB24_Msk     (0x1U << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos     (25U)                                           
+#define CAN_F12R2_FB25_Msk     (0x1U << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos     (26U)                                           
+#define CAN_F12R2_FB26_Msk     (0x1U << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos     (27U)                                           
+#define CAN_F12R2_FB27_Msk     (0x1U << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos     (28U)                                           
+#define CAN_F12R2_FB28_Msk     (0x1U << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos     (29U)                                           
+#define CAN_F12R2_FB29_Msk     (0x1U << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos     (30U)                                           
+#define CAN_F12R2_FB30_Msk     (0x1U << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos     (31U)                                           
+#define CAN_F12R2_FB31_Msk     (0x1U << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define CAN_F13R2_FB0_Pos      (0U)                                            
+#define CAN_F13R2_FB0_Msk      (0x1U << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos      (1U)                                            
+#define CAN_F13R2_FB1_Msk      (0x1U << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos      (2U)                                            
+#define CAN_F13R2_FB2_Msk      (0x1U << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos      (3U)                                            
+#define CAN_F13R2_FB3_Msk      (0x1U << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos      (4U)                                            
+#define CAN_F13R2_FB4_Msk      (0x1U << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos      (5U)                                            
+#define CAN_F13R2_FB5_Msk      (0x1U << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos      (6U)                                            
+#define CAN_F13R2_FB6_Msk      (0x1U << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos      (7U)                                            
+#define CAN_F13R2_FB7_Msk      (0x1U << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos      (8U)                                            
+#define CAN_F13R2_FB8_Msk      (0x1U << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos      (9U)                                            
+#define CAN_F13R2_FB9_Msk      (0x1U << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos     (10U)                                           
+#define CAN_F13R2_FB10_Msk     (0x1U << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos     (11U)                                           
+#define CAN_F13R2_FB11_Msk     (0x1U << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos     (12U)                                           
+#define CAN_F13R2_FB12_Msk     (0x1U << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos     (13U)                                           
+#define CAN_F13R2_FB13_Msk     (0x1U << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos     (14U)                                           
+#define CAN_F13R2_FB14_Msk     (0x1U << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos     (15U)                                           
+#define CAN_F13R2_FB15_Msk     (0x1U << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos     (16U)                                           
+#define CAN_F13R2_FB16_Msk     (0x1U << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos     (17U)                                           
+#define CAN_F13R2_FB17_Msk     (0x1U << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos     (18U)                                           
+#define CAN_F13R2_FB18_Msk     (0x1U << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos     (19U)                                           
+#define CAN_F13R2_FB19_Msk     (0x1U << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos     (20U)                                           
+#define CAN_F13R2_FB20_Msk     (0x1U << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos     (21U)                                           
+#define CAN_F13R2_FB21_Msk     (0x1U << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos     (22U)                                           
+#define CAN_F13R2_FB22_Msk     (0x1U << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos     (23U)                                           
+#define CAN_F13R2_FB23_Msk     (0x1U << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos     (24U)                                           
+#define CAN_F13R2_FB24_Msk     (0x1U << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos     (25U)                                           
+#define CAN_F13R2_FB25_Msk     (0x1U << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos     (26U)                                           
+#define CAN_F13R2_FB26_Msk     (0x1U << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos     (27U)                                           
+#define CAN_F13R2_FB27_Msk     (0x1U << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos     (28U)                                           
+#define CAN_F13R2_FB28_Msk     (0x1U << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos     (29U)                                           
+#define CAN_F13R2_FB29_Msk     (0x1U << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos     (30U)                                           
+#define CAN_F13R2_FB30_Msk     (0x1U << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos     (31U)                                           
+#define CAN_F13R2_FB31_Msk     (0x1U << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos       (0U)                                               
+#define CRC_DR_DR_Msk       (0xFFFFFFFFU << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */
+#define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */
+
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos     (0U)                                               
+#define CRC_IDR_IDR_Msk     (0xFFU << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */
+#define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */
+
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos    (0U)                                               
+#define CRC_CR_RESET_Msk    (0x1U << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */
+#define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Crypto Processor                                */
+/*                                                                            */
+/******************************************************************************/
+/******************* Bits definition for CRYP_CR register  ********************/
+#define CRYP_CR_ALGODIR_Pos              (2U)                                  
+#define CRYP_CR_ALGODIR_Msk              (0x1U << CRYP_CR_ALGODIR_Pos)         /*!< 0x00000004 */
+#define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk                   
+
+#define CRYP_CR_ALGOMODE_Pos             (3U)                                  
+#define CRYP_CR_ALGOMODE_Msk             (0x10007U << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00080038 */
+#define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk                  
+#define CRYP_CR_ALGOMODE_0               (0x00001U << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */
+#define CRYP_CR_ALGOMODE_1               (0x00002U << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */
+#define CRYP_CR_ALGOMODE_2               (0x00004U << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */
+#define CRYP_CR_ALGOMODE_TDES_ECB        0x00000000U                           
+#define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)                                  
+#define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1U << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
+#define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk         
+#define CRYP_CR_ALGOMODE_DES_ECB_Pos     (4U)                                  
+#define CRYP_CR_ALGOMODE_DES_ECB_Msk     (0x1U << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
+#define CRYP_CR_ALGOMODE_DES_ECB         CRYP_CR_ALGOMODE_DES_ECB_Msk          
+#define CRYP_CR_ALGOMODE_DES_CBC_Pos     (3U)                                  
+#define CRYP_CR_ALGOMODE_DES_CBC_Msk     (0x3U << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
+#define CRYP_CR_ALGOMODE_DES_CBC         CRYP_CR_ALGOMODE_DES_CBC_Msk          
+#define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)                                  
+#define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1U << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
+#define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk          
+#define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)                                  
+#define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5U << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
+#define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk          
+#define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)                                  
+#define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3U << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
+#define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk          
+#define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)                                  
+#define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7U << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
+#define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk          
+
+#define CRYP_CR_DATATYPE_Pos             (6U)                                  
+#define CRYP_CR_DATATYPE_Msk             (0x3U << CRYP_CR_DATATYPE_Pos)        /*!< 0x000000C0 */
+#define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk                  
+#define CRYP_CR_DATATYPE_0               (0x1U << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000040 */
+#define CRYP_CR_DATATYPE_1               (0x2U << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000080 */
+#define CRYP_CR_KEYSIZE_Pos              (8U)                                  
+#define CRYP_CR_KEYSIZE_Msk              (0x3U << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000300 */
+#define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk                   
+#define CRYP_CR_KEYSIZE_0                (0x1U << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000100 */
+#define CRYP_CR_KEYSIZE_1                (0x2U << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000200 */
+#define CRYP_CR_FFLUSH_Pos               (14U)                                 
+#define CRYP_CR_FFLUSH_Msk               (0x1U << CRYP_CR_FFLUSH_Pos)          /*!< 0x00004000 */
+#define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk                    
+#define CRYP_CR_CRYPEN_Pos               (15U)                                 
+#define CRYP_CR_CRYPEN_Msk               (0x1U << CRYP_CR_CRYPEN_Pos)          /*!< 0x00008000 */
+#define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk                    
+
+#define CRYP_CR_GCM_CCMPH_Pos            (16U)                                 
+#define CRYP_CR_GCM_CCMPH_Msk            (0x3U << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00030000 */
+#define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk                 
+#define CRYP_CR_GCM_CCMPH_0              (0x1U << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */
+#define CRYP_CR_GCM_CCMPH_1              (0x2U << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */
+#define CRYP_CR_ALGOMODE_3               0x00080000U                           
+
+/****************** Bits definition for CRYP_SR register  *********************/
+#define CRYP_SR_IFEM_Pos                 (0U)                                  
+#define CRYP_SR_IFEM_Msk                 (0x1U << CRYP_SR_IFEM_Pos)            /*!< 0x00000001 */
+#define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk                      
+#define CRYP_SR_IFNF_Pos                 (1U)                                  
+#define CRYP_SR_IFNF_Msk                 (0x1U << CRYP_SR_IFNF_Pos)            /*!< 0x00000002 */
+#define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk                      
+#define CRYP_SR_OFNE_Pos                 (2U)                                  
+#define CRYP_SR_OFNE_Msk                 (0x1U << CRYP_SR_OFNE_Pos)            /*!< 0x00000004 */
+#define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk                      
+#define CRYP_SR_OFFU_Pos                 (3U)                                  
+#define CRYP_SR_OFFU_Msk                 (0x1U << CRYP_SR_OFFU_Pos)            /*!< 0x00000008 */
+#define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk                      
+#define CRYP_SR_BUSY_Pos                 (4U)                                  
+#define CRYP_SR_BUSY_Msk                 (0x1U << CRYP_SR_BUSY_Pos)            /*!< 0x00000010 */
+#define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk                      
+/****************** Bits definition for CRYP_DMACR register  ******************/
+#define CRYP_DMACR_DIEN_Pos              (0U)                                  
+#define CRYP_DMACR_DIEN_Msk              (0x1U << CRYP_DMACR_DIEN_Pos)         /*!< 0x00000001 */
+#define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk                   
+#define CRYP_DMACR_DOEN_Pos              (1U)                                  
+#define CRYP_DMACR_DOEN_Msk              (0x1U << CRYP_DMACR_DOEN_Pos)         /*!< 0x00000002 */
+#define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk                   
+/*****************  Bits definition for CRYP_IMSCR register  ******************/
+#define CRYP_IMSCR_INIM_Pos              (0U)                                  
+#define CRYP_IMSCR_INIM_Msk              (0x1U << CRYP_IMSCR_INIM_Pos)         /*!< 0x00000001 */
+#define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk                   
+#define CRYP_IMSCR_OUTIM_Pos             (1U)                                  
+#define CRYP_IMSCR_OUTIM_Msk             (0x1U << CRYP_IMSCR_OUTIM_Pos)        /*!< 0x00000002 */
+#define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk                  
+/****************** Bits definition for CRYP_RISR register  *******************/
+#define CRYP_RISR_OUTRIS_Pos             (0U)                                  
+#define CRYP_RISR_OUTRIS_Msk             (0x1U << CRYP_RISR_OUTRIS_Pos)        /*!< 0x00000001 */
+#define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk                  
+#define CRYP_RISR_INRIS_Pos              (1U)                                  
+#define CRYP_RISR_INRIS_Msk              (0x1U << CRYP_RISR_INRIS_Pos)         /*!< 0x00000002 */
+#define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk                   
+/****************** Bits definition for CRYP_MISR register  *******************/
+#define CRYP_MISR_INMIS_Pos              (0U)                                  
+#define CRYP_MISR_INMIS_Msk              (0x1U << CRYP_MISR_INMIS_Pos)         /*!< 0x00000001 */
+#define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk                   
+#define CRYP_MISR_OUTMIS_Pos             (1U)                                  
+#define CRYP_MISR_OUTMIS_Msk             (0x1U << CRYP_MISR_OUTMIS_Pos)        /*!< 0x00000002 */
+#define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk                  
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT                                    /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos              (0U)                                       
+#define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos            (1U)                                       
+#define DAC_CR_BOFF1_Msk            (0x1U << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
+#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos             (2U)                                       
+#define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (3U)                                       
+#define DAC_CR_TSEL1_Msk            (0x7U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos            (6U)                                       
+#define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)                                       
+#define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)                                      
+#define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos        (13U)                                      
+#define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2_Pos              (16U)                                      
+#define DAC_CR_EN2_Msk              (0x1U << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos            (17U)                                      
+#define DAC_CR_BOFF2_Msk            (0x1U << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
+#define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos             (18U)                                      
+#define DAC_CR_TEN2_Msk             (0x1U << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos            (19U)                                      
+#define DAC_CR_TSEL2_Msk            (0x7U << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0              (0x1U << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1              (0x2U << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2              (0x4U << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos            (22U)                                      
+#define DAC_CR_WAVE2_Msk            (0x3U << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0              (0x1U << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1              (0x2U << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos            (24U)                                      
+#define DAC_CR_MAMP2_Msk            (0xFU << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0              (0x1U << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1              (0x2U << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2              (0x4U << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3              (0x8U << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos           (28U)                                      
+#define DAC_CR_DMAEN2_Msk           (0x1U << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos        (29U)                                      
+#define DAC_CR_DMAUDRIE2_Msk        (0x1U << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)                                       
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)                                       
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)                                       
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)                                       
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)                                       
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)                                      
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)                                      
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)                                       
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos       (0U)                                       
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFU << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos       (0U)                                       
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFU << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos          (13U)                                      
+#define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_Pos          (29U)                                      
+#define DAC_SR_DMAUDR2_Msk          (0x1U << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE_Pos        (0U)                                        
+#define DCMI_CR_CAPTURE_Msk        (0x1U << DCMI_CR_CAPTURE_Pos)               /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk                         
+#define DCMI_CR_CM_Pos             (1U)                                        
+#define DCMI_CR_CM_Msk             (0x1U << DCMI_CR_CM_Pos)                    /*!< 0x00000002 */
+#define DCMI_CR_CM                 DCMI_CR_CM_Msk                              
+#define DCMI_CR_CROP_Pos           (2U)                                        
+#define DCMI_CR_CROP_Msk           (0x1U << DCMI_CR_CROP_Pos)                  /*!< 0x00000004 */
+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk                            
+#define DCMI_CR_JPEG_Pos           (3U)                                        
+#define DCMI_CR_JPEG_Msk           (0x1U << DCMI_CR_JPEG_Pos)                  /*!< 0x00000008 */
+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk                            
+#define DCMI_CR_ESS_Pos            (4U)                                        
+#define DCMI_CR_ESS_Msk            (0x1U << DCMI_CR_ESS_Pos)                   /*!< 0x00000010 */
+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk                             
+#define DCMI_CR_PCKPOL_Pos         (5U)                                        
+#define DCMI_CR_PCKPOL_Msk         (0x1U << DCMI_CR_PCKPOL_Pos)                /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk                          
+#define DCMI_CR_HSPOL_Pos          (6U)                                        
+#define DCMI_CR_HSPOL_Msk          (0x1U << DCMI_CR_HSPOL_Pos)                 /*!< 0x00000040 */
+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk                           
+#define DCMI_CR_VSPOL_Pos          (7U)                                        
+#define DCMI_CR_VSPOL_Msk          (0x1U << DCMI_CR_VSPOL_Pos)                 /*!< 0x00000080 */
+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk                           
+#define DCMI_CR_FCRC_0             0x00000100U                                 
+#define DCMI_CR_FCRC_1             0x00000200U                                 
+#define DCMI_CR_EDM_0              0x00000400U                                 
+#define DCMI_CR_EDM_1              0x00000800U                                 
+#define DCMI_CR_ENABLE_Pos         (14U)                                       
+#define DCMI_CR_ENABLE_Msk         (0x1U << DCMI_CR_ENABLE_Pos)                /*!< 0x00004000 */
+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk                          
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC_Pos          (0U)                                        
+#define DCMI_SR_HSYNC_Msk          (0x1U << DCMI_SR_HSYNC_Pos)                 /*!< 0x00000001 */
+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk                           
+#define DCMI_SR_VSYNC_Pos          (1U)                                        
+#define DCMI_SR_VSYNC_Msk          (0x1U << DCMI_SR_VSYNC_Pos)                 /*!< 0x00000002 */
+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk                           
+#define DCMI_SR_FNE_Pos            (2U)                                        
+#define DCMI_SR_FNE_Msk            (0x1U << DCMI_SR_FNE_Pos)                   /*!< 0x00000004 */
+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk                             
+
+/********************  Bits definition for DCMI_RIS register  *****************/
+#define DCMI_RIS_FRAME_RIS_Pos     (0U)                                        
+#define DCMI_RIS_FRAME_RIS_Msk     (0x1U << DCMI_RIS_FRAME_RIS_Pos)            /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk                      
+#define DCMI_RIS_OVR_RIS_Pos       (1U)                                        
+#define DCMI_RIS_OVR_RIS_Msk       (0x1U << DCMI_RIS_OVR_RIS_Pos)              /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk                        
+#define DCMI_RIS_ERR_RIS_Pos       (2U)                                        
+#define DCMI_RIS_ERR_RIS_Msk       (0x1U << DCMI_RIS_ERR_RIS_Pos)              /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk                        
+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)                                        
+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1U << DCMI_RIS_VSYNC_RIS_Pos)            /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk                      
+#define DCMI_RIS_LINE_RIS_Pos      (4U)                                        
+#define DCMI_RIS_LINE_RIS_Msk      (0x1U << DCMI_RIS_LINE_RIS_Pos)             /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk                       
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE_Pos      (0U)                                        
+#define DCMI_IER_FRAME_IE_Msk      (0x1U << DCMI_IER_FRAME_IE_Pos)             /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk                       
+#define DCMI_IER_OVR_IE_Pos        (1U)                                        
+#define DCMI_IER_OVR_IE_Msk        (0x1U << DCMI_IER_OVR_IE_Pos)               /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk                         
+#define DCMI_IER_ERR_IE_Pos        (2U)                                        
+#define DCMI_IER_ERR_IE_Msk        (0x1U << DCMI_IER_ERR_IE_Pos)               /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk                         
+#define DCMI_IER_VSYNC_IE_Pos      (3U)                                        
+#define DCMI_IER_VSYNC_IE_Msk      (0x1U << DCMI_IER_VSYNC_IE_Pos)             /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk                       
+#define DCMI_IER_LINE_IE_Pos       (4U)                                        
+#define DCMI_IER_LINE_IE_Msk       (0x1U << DCMI_IER_LINE_IE_Pos)              /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk                        
+/* Legacy defines */
+#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
+
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS_Pos     (0U)                                        
+#define DCMI_MIS_FRAME_MIS_Msk     (0x1U << DCMI_MIS_FRAME_MIS_Pos)            /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk                      
+#define DCMI_MIS_OVR_MIS_Pos       (1U)                                        
+#define DCMI_MIS_OVR_MIS_Msk       (0x1U << DCMI_MIS_OVR_MIS_Pos)              /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk                        
+#define DCMI_MIS_ERR_MIS_Pos       (2U)                                        
+#define DCMI_MIS_ERR_MIS_Msk       (0x1U << DCMI_MIS_ERR_MIS_Pos)              /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk                        
+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)                                        
+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1U << DCMI_MIS_VSYNC_MIS_Pos)            /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk                      
+#define DCMI_MIS_LINE_MIS_Pos      (4U)                                        
+#define DCMI_MIS_LINE_MIS_Msk      (0x1U << DCMI_MIS_LINE_MIS_Pos)             /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk                       
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC_Pos     (0U)                                        
+#define DCMI_ICR_FRAME_ISC_Msk     (0x1U << DCMI_ICR_FRAME_ISC_Pos)            /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk                      
+#define DCMI_ICR_OVR_ISC_Pos       (1U)                                        
+#define DCMI_ICR_OVR_ISC_Msk       (0x1U << DCMI_ICR_OVR_ISC_Pos)              /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk                        
+#define DCMI_ICR_ERR_ISC_Pos       (2U)                                        
+#define DCMI_ICR_ERR_ISC_Msk       (0x1U << DCMI_ICR_ERR_ISC_Pos)              /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk                        
+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)                                        
+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1U << DCMI_ICR_VSYNC_ISC_Pos)            /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk                      
+#define DCMI_ICR_LINE_ISC_Pos      (4U)                                        
+#define DCMI_ICR_LINE_ISC_Msk      (0x1U << DCMI_ICR_LINE_ISC_Pos)             /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk                       
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
+
+/********************  Bits definition for DCMI_ESCR register  ******************/
+#define DCMI_ESCR_FSC_Pos          (0U)                                        
+#define DCMI_ESCR_FSC_Msk          (0xFFU << DCMI_ESCR_FSC_Pos)                /*!< 0x000000FF */
+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk                           
+#define DCMI_ESCR_LSC_Pos          (8U)                                        
+#define DCMI_ESCR_LSC_Msk          (0xFFU << DCMI_ESCR_LSC_Pos)                /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk                           
+#define DCMI_ESCR_LEC_Pos          (16U)                                       
+#define DCMI_ESCR_LEC_Msk          (0xFFU << DCMI_ESCR_LEC_Pos)                /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk                           
+#define DCMI_ESCR_FEC_Pos          (24U)                                       
+#define DCMI_ESCR_FEC_Msk          (0xFFU << DCMI_ESCR_FEC_Pos)                /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk                           
+
+/********************  Bits definition for DCMI_ESUR register  ******************/
+#define DCMI_ESUR_FSU_Pos          (0U)                                        
+#define DCMI_ESUR_FSU_Msk          (0xFFU << DCMI_ESUR_FSU_Pos)                /*!< 0x000000FF */
+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk                           
+#define DCMI_ESUR_LSU_Pos          (8U)                                        
+#define DCMI_ESUR_LSU_Msk          (0xFFU << DCMI_ESUR_LSU_Pos)                /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk                           
+#define DCMI_ESUR_LEU_Pos          (16U)                                       
+#define DCMI_ESUR_LEU_Msk          (0xFFU << DCMI_ESUR_LEU_Pos)                /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk                           
+#define DCMI_ESUR_FEU_Pos          (24U)                                       
+#define DCMI_ESUR_FEU_Msk          (0xFFU << DCMI_ESUR_FEU_Pos)                /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk                           
+
+/********************  Bits definition for DCMI_CWSTRT register  ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)                                        
+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos)        /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk                     
+#define DCMI_CWSTRT_VST_Pos        (16U)                                       
+#define DCMI_CWSTRT_VST_Msk        (0x1FFFU << DCMI_CWSTRT_VST_Pos)            /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk                         
+
+/********************  Bits definition for DCMI_CWSIZE register  ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)                                        
+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos)         /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk                      
+#define DCMI_CWSIZE_VLINE_Pos      (16U)                                       
+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFU << DCMI_CWSIZE_VLINE_Pos)          /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk                       
+
+/********************  Bits definition for DCMI_DR register  *********************/
+#define DCMI_DR_BYTE0_Pos          (0U)                                        
+#define DCMI_DR_BYTE0_Msk          (0xFFU << DCMI_DR_BYTE0_Pos)                /*!< 0x000000FF */
+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk                           
+#define DCMI_DR_BYTE1_Pos          (8U)                                        
+#define DCMI_DR_BYTE1_Msk          (0xFFU << DCMI_DR_BYTE1_Pos)                /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk                           
+#define DCMI_DR_BYTE2_Pos          (16U)                                       
+#define DCMI_DR_BYTE2_Msk          (0xFFU << DCMI_DR_BYTE2_Pos)                /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk                           
+#define DCMI_DR_BYTE3_Pos          (24U)                                       
+#define DCMI_DR_BYTE3_Msk          (0xFFU << DCMI_DR_BYTE3_Pos)                /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk                           
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMA_SxCR register  *****************/
+#define DMA_SxCR_CHSEL_Pos       (25U)                                         
+#define DMA_SxCR_CHSEL_Msk       (0x7U << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */
+#define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk                            
+#define DMA_SxCR_CHSEL_0         0x02000000U                                   
+#define DMA_SxCR_CHSEL_1         0x04000000U                                   
+#define DMA_SxCR_CHSEL_2         0x08000000U                                   
+#define DMA_SxCR_MBURST_Pos      (23U)                                         
+#define DMA_SxCR_MBURST_Msk      (0x3U << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */
+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           
+#define DMA_SxCR_MBURST_0        (0x1U << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1        (0x2U << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos      (21U)                                         
+#define DMA_SxCR_PBURST_Msk      (0x3U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */
+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           
+#define DMA_SxCR_PBURST_0        (0x1U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1        (0x2U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos          (19U)                                         
+#define DMA_SxCR_CT_Msk          (0x1U << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */
+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               
+#define DMA_SxCR_DBM_Pos         (18U)                                         
+#define DMA_SxCR_DBM_Msk         (0x1U << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */
+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              
+#define DMA_SxCR_PL_Pos          (16U)                                         
+#define DMA_SxCR_PL_Msk          (0x3U << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */
+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               
+#define DMA_SxCR_PL_0            (0x1U << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
+#define DMA_SxCR_PL_1            (0x2U << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos      (15U)                                         
+#define DMA_SxCR_PINCOS_Msk      (0x1U << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           
+#define DMA_SxCR_MSIZE_Pos       (13U)                                         
+#define DMA_SxCR_MSIZE_Msk       (0x3U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            
+#define DMA_SxCR_MSIZE_0         (0x1U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1         (0x2U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos       (11U)                                         
+#define DMA_SxCR_PSIZE_Msk       (0x3U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            
+#define DMA_SxCR_PSIZE_0         (0x1U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1         (0x2U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos        (10U)                                         
+#define DMA_SxCR_MINC_Msk        (0x1U << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */
+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             
+#define DMA_SxCR_PINC_Pos        (9U)                                          
+#define DMA_SxCR_PINC_Msk        (0x1U << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */
+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             
+#define DMA_SxCR_CIRC_Pos        (8U)                                          
+#define DMA_SxCR_CIRC_Msk        (0x1U << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */
+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             
+#define DMA_SxCR_DIR_Pos         (6U)                                          
+#define DMA_SxCR_DIR_Msk         (0x3U << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */
+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              
+#define DMA_SxCR_DIR_0           (0x1U << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1           (0x2U << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos      (5U)                                          
+#define DMA_SxCR_PFCTRL_Msk      (0x1U << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           
+#define DMA_SxCR_TCIE_Pos        (4U)                                          
+#define DMA_SxCR_TCIE_Msk        (0x1U << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */
+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             
+#define DMA_SxCR_HTIE_Pos        (3U)                                          
+#define DMA_SxCR_HTIE_Msk        (0x1U << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */
+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             
+#define DMA_SxCR_TEIE_Pos        (2U)                                          
+#define DMA_SxCR_TEIE_Msk        (0x1U << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */
+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             
+#define DMA_SxCR_DMEIE_Pos       (1U)                                          
+#define DMA_SxCR_DMEIE_Msk       (0x1U << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            
+#define DMA_SxCR_EN_Pos          (0U)                                          
+#define DMA_SxCR_EN_Msk          (0x1U << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */
+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos         (20U)                                         
+#define DMA_SxCR_ACK_Msk         (0x1U << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */
+#define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk                              
+
+/********************  Bits definition for DMA_SxCNDTR register  **************/
+#define DMA_SxNDT_Pos            (0U)                                          
+#define DMA_SxNDT_Msk            (0xFFFFU << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */
+#define DMA_SxNDT                DMA_SxNDT_Msk                                 
+#define DMA_SxNDT_0              (0x0001U << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
+#define DMA_SxNDT_1              (0x0002U << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
+#define DMA_SxNDT_2              (0x0004U << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
+#define DMA_SxNDT_3              (0x0008U << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
+#define DMA_SxNDT_4              (0x0010U << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
+#define DMA_SxNDT_5              (0x0020U << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
+#define DMA_SxNDT_6              (0x0040U << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
+#define DMA_SxNDT_7              (0x0080U << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
+#define DMA_SxNDT_8              (0x0100U << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
+#define DMA_SxNDT_9              (0x0200U << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
+#define DMA_SxNDT_10             (0x0400U << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
+#define DMA_SxNDT_11             (0x0800U << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
+#define DMA_SxNDT_12             (0x1000U << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
+#define DMA_SxNDT_13             (0x2000U << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
+#define DMA_SxNDT_14             (0x4000U << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
+#define DMA_SxNDT_15             (0x8000U << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
+
+/********************  Bits definition for DMA_SxFCR register  ****************/ 
+#define DMA_SxFCR_FEIE_Pos       (7U)                                          
+#define DMA_SxFCR_FEIE_Msk       (0x1U << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            
+#define DMA_SxFCR_FS_Pos         (3U)                                          
+#define DMA_SxFCR_FS_Msk         (0x7U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */
+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              
+#define DMA_SxFCR_FS_0           (0x1U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1           (0x2U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2           (0x4U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos      (2U)                                          
+#define DMA_SxFCR_DMDIS_Msk      (0x1U << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           
+#define DMA_SxFCR_FTH_Pos        (0U)                                          
+#define DMA_SxFCR_FTH_Msk        (0x3U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */
+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             
+#define DMA_SxFCR_FTH_0          (0x1U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1          (0x2U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
+
+/********************  Bits definition for DMA_LISR register  *****************/ 
+#define DMA_LISR_TCIF3_Pos       (27U)                                         
+#define DMA_LISR_TCIF3_Msk       (0x1U << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */
+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            
+#define DMA_LISR_HTIF3_Pos       (26U)                                         
+#define DMA_LISR_HTIF3_Msk       (0x1U << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */
+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            
+#define DMA_LISR_TEIF3_Pos       (25U)                                         
+#define DMA_LISR_TEIF3_Msk       (0x1U << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */
+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            
+#define DMA_LISR_DMEIF3_Pos      (24U)                                         
+#define DMA_LISR_DMEIF3_Msk      (0x1U << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           
+#define DMA_LISR_FEIF3_Pos       (22U)                                         
+#define DMA_LISR_FEIF3_Msk       (0x1U << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */
+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            
+#define DMA_LISR_TCIF2_Pos       (21U)                                         
+#define DMA_LISR_TCIF2_Msk       (0x1U << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */
+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            
+#define DMA_LISR_HTIF2_Pos       (20U)                                         
+#define DMA_LISR_HTIF2_Msk       (0x1U << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */
+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            
+#define DMA_LISR_TEIF2_Pos       (19U)                                         
+#define DMA_LISR_TEIF2_Msk       (0x1U << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */
+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            
+#define DMA_LISR_DMEIF2_Pos      (18U)                                         
+#define DMA_LISR_DMEIF2_Msk      (0x1U << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           
+#define DMA_LISR_FEIF2_Pos       (16U)                                         
+#define DMA_LISR_FEIF2_Msk       (0x1U << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */
+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            
+#define DMA_LISR_TCIF1_Pos       (11U)                                         
+#define DMA_LISR_TCIF1_Msk       (0x1U << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */
+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            
+#define DMA_LISR_HTIF1_Pos       (10U)                                         
+#define DMA_LISR_HTIF1_Msk       (0x1U << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */
+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            
+#define DMA_LISR_TEIF1_Pos       (9U)                                          
+#define DMA_LISR_TEIF1_Msk       (0x1U << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */
+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            
+#define DMA_LISR_DMEIF1_Pos      (8U)                                          
+#define DMA_LISR_DMEIF1_Msk      (0x1U << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           
+#define DMA_LISR_FEIF1_Pos       (6U)                                          
+#define DMA_LISR_FEIF1_Msk       (0x1U << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */
+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            
+#define DMA_LISR_TCIF0_Pos       (5U)                                          
+#define DMA_LISR_TCIF0_Msk       (0x1U << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */
+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            
+#define DMA_LISR_HTIF0_Pos       (4U)                                          
+#define DMA_LISR_HTIF0_Msk       (0x1U << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */
+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            
+#define DMA_LISR_TEIF0_Pos       (3U)                                          
+#define DMA_LISR_TEIF0_Msk       (0x1U << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */
+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            
+#define DMA_LISR_DMEIF0_Pos      (2U)                                          
+#define DMA_LISR_DMEIF0_Msk      (0x1U << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           
+#define DMA_LISR_FEIF0_Pos       (0U)                                          
+#define DMA_LISR_FEIF0_Msk       (0x1U << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */
+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            
+
+/********************  Bits definition for DMA_HISR register  *****************/ 
+#define DMA_HISR_TCIF7_Pos       (27U)                                         
+#define DMA_HISR_TCIF7_Msk       (0x1U << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */
+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            
+#define DMA_HISR_HTIF7_Pos       (26U)                                         
+#define DMA_HISR_HTIF7_Msk       (0x1U << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */
+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            
+#define DMA_HISR_TEIF7_Pos       (25U)                                         
+#define DMA_HISR_TEIF7_Msk       (0x1U << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */
+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            
+#define DMA_HISR_DMEIF7_Pos      (24U)                                         
+#define DMA_HISR_DMEIF7_Msk      (0x1U << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           
+#define DMA_HISR_FEIF7_Pos       (22U)                                         
+#define DMA_HISR_FEIF7_Msk       (0x1U << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */
+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            
+#define DMA_HISR_TCIF6_Pos       (21U)                                         
+#define DMA_HISR_TCIF6_Msk       (0x1U << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */
+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            
+#define DMA_HISR_HTIF6_Pos       (20U)                                         
+#define DMA_HISR_HTIF6_Msk       (0x1U << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */
+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            
+#define DMA_HISR_TEIF6_Pos       (19U)                                         
+#define DMA_HISR_TEIF6_Msk       (0x1U << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */
+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            
+#define DMA_HISR_DMEIF6_Pos      (18U)                                         
+#define DMA_HISR_DMEIF6_Msk      (0x1U << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           
+#define DMA_HISR_FEIF6_Pos       (16U)                                         
+#define DMA_HISR_FEIF6_Msk       (0x1U << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */
+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            
+#define DMA_HISR_TCIF5_Pos       (11U)                                         
+#define DMA_HISR_TCIF5_Msk       (0x1U << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */
+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            
+#define DMA_HISR_HTIF5_Pos       (10U)                                         
+#define DMA_HISR_HTIF5_Msk       (0x1U << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */
+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            
+#define DMA_HISR_TEIF5_Pos       (9U)                                          
+#define DMA_HISR_TEIF5_Msk       (0x1U << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */
+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            
+#define DMA_HISR_DMEIF5_Pos      (8U)                                          
+#define DMA_HISR_DMEIF5_Msk      (0x1U << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           
+#define DMA_HISR_FEIF5_Pos       (6U)                                          
+#define DMA_HISR_FEIF5_Msk       (0x1U << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */
+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            
+#define DMA_HISR_TCIF4_Pos       (5U)                                          
+#define DMA_HISR_TCIF4_Msk       (0x1U << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */
+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            
+#define DMA_HISR_HTIF4_Pos       (4U)                                          
+#define DMA_HISR_HTIF4_Msk       (0x1U << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */
+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            
+#define DMA_HISR_TEIF4_Pos       (3U)                                          
+#define DMA_HISR_TEIF4_Msk       (0x1U << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */
+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            
+#define DMA_HISR_DMEIF4_Pos      (2U)                                          
+#define DMA_HISR_DMEIF4_Msk      (0x1U << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           
+#define DMA_HISR_FEIF4_Pos       (0U)                                          
+#define DMA_HISR_FEIF4_Msk       (0x1U << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */
+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            
+
+/********************  Bits definition for DMA_LIFCR register  ****************/ 
+#define DMA_LIFCR_CTCIF3_Pos     (27U)                                         
+#define DMA_LIFCR_CTCIF3_Msk     (0x1U << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          
+#define DMA_LIFCR_CHTIF3_Pos     (26U)                                         
+#define DMA_LIFCR_CHTIF3_Msk     (0x1U << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          
+#define DMA_LIFCR_CTEIF3_Pos     (25U)                                         
+#define DMA_LIFCR_CTEIF3_Msk     (0x1U << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          
+#define DMA_LIFCR_CDMEIF3_Pos    (24U)                                         
+#define DMA_LIFCR_CDMEIF3_Msk    (0x1U << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         
+#define DMA_LIFCR_CFEIF3_Pos     (22U)                                         
+#define DMA_LIFCR_CFEIF3_Msk     (0x1U << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          
+#define DMA_LIFCR_CTCIF2_Pos     (21U)                                         
+#define DMA_LIFCR_CTCIF2_Msk     (0x1U << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          
+#define DMA_LIFCR_CHTIF2_Pos     (20U)                                         
+#define DMA_LIFCR_CHTIF2_Msk     (0x1U << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          
+#define DMA_LIFCR_CTEIF2_Pos     (19U)                                         
+#define DMA_LIFCR_CTEIF2_Msk     (0x1U << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          
+#define DMA_LIFCR_CDMEIF2_Pos    (18U)                                         
+#define DMA_LIFCR_CDMEIF2_Msk    (0x1U << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         
+#define DMA_LIFCR_CFEIF2_Pos     (16U)                                         
+#define DMA_LIFCR_CFEIF2_Msk     (0x1U << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          
+#define DMA_LIFCR_CTCIF1_Pos     (11U)                                         
+#define DMA_LIFCR_CTCIF1_Msk     (0x1U << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          
+#define DMA_LIFCR_CHTIF1_Pos     (10U)                                         
+#define DMA_LIFCR_CHTIF1_Msk     (0x1U << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          
+#define DMA_LIFCR_CTEIF1_Pos     (9U)                                          
+#define DMA_LIFCR_CTEIF1_Msk     (0x1U << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          
+#define DMA_LIFCR_CDMEIF1_Pos    (8U)                                          
+#define DMA_LIFCR_CDMEIF1_Msk    (0x1U << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         
+#define DMA_LIFCR_CFEIF1_Pos     (6U)                                          
+#define DMA_LIFCR_CFEIF1_Msk     (0x1U << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          
+#define DMA_LIFCR_CTCIF0_Pos     (5U)                                          
+#define DMA_LIFCR_CTCIF0_Msk     (0x1U << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          
+#define DMA_LIFCR_CHTIF0_Pos     (4U)                                          
+#define DMA_LIFCR_CHTIF0_Msk     (0x1U << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          
+#define DMA_LIFCR_CTEIF0_Pos     (3U)                                          
+#define DMA_LIFCR_CTEIF0_Msk     (0x1U << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          
+#define DMA_LIFCR_CDMEIF0_Pos    (2U)                                          
+#define DMA_LIFCR_CDMEIF0_Msk    (0x1U << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         
+#define DMA_LIFCR_CFEIF0_Pos     (0U)                                          
+#define DMA_LIFCR_CFEIF0_Msk     (0x1U << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          
+
+/********************  Bits definition for DMA_HIFCR  register  ****************/ 
+#define DMA_HIFCR_CTCIF7_Pos     (27U)                                         
+#define DMA_HIFCR_CTCIF7_Msk     (0x1U << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          
+#define DMA_HIFCR_CHTIF7_Pos     (26U)                                         
+#define DMA_HIFCR_CHTIF7_Msk     (0x1U << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          
+#define DMA_HIFCR_CTEIF7_Pos     (25U)                                         
+#define DMA_HIFCR_CTEIF7_Msk     (0x1U << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          
+#define DMA_HIFCR_CDMEIF7_Pos    (24U)                                         
+#define DMA_HIFCR_CDMEIF7_Msk    (0x1U << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         
+#define DMA_HIFCR_CFEIF7_Pos     (22U)                                         
+#define DMA_HIFCR_CFEIF7_Msk     (0x1U << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          
+#define DMA_HIFCR_CTCIF6_Pos     (21U)                                         
+#define DMA_HIFCR_CTCIF6_Msk     (0x1U << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          
+#define DMA_HIFCR_CHTIF6_Pos     (20U)                                         
+#define DMA_HIFCR_CHTIF6_Msk     (0x1U << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          
+#define DMA_HIFCR_CTEIF6_Pos     (19U)                                         
+#define DMA_HIFCR_CTEIF6_Msk     (0x1U << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          
+#define DMA_HIFCR_CDMEIF6_Pos    (18U)                                         
+#define DMA_HIFCR_CDMEIF6_Msk    (0x1U << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         
+#define DMA_HIFCR_CFEIF6_Pos     (16U)                                         
+#define DMA_HIFCR_CFEIF6_Msk     (0x1U << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          
+#define DMA_HIFCR_CTCIF5_Pos     (11U)                                         
+#define DMA_HIFCR_CTCIF5_Msk     (0x1U << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          
+#define DMA_HIFCR_CHTIF5_Pos     (10U)                                         
+#define DMA_HIFCR_CHTIF5_Msk     (0x1U << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          
+#define DMA_HIFCR_CTEIF5_Pos     (9U)                                          
+#define DMA_HIFCR_CTEIF5_Msk     (0x1U << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          
+#define DMA_HIFCR_CDMEIF5_Pos    (8U)                                          
+#define DMA_HIFCR_CDMEIF5_Msk    (0x1U << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         
+#define DMA_HIFCR_CFEIF5_Pos     (6U)                                          
+#define DMA_HIFCR_CFEIF5_Msk     (0x1U << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          
+#define DMA_HIFCR_CTCIF4_Pos     (5U)                                          
+#define DMA_HIFCR_CTCIF4_Msk     (0x1U << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          
+#define DMA_HIFCR_CHTIF4_Pos     (4U)                                          
+#define DMA_HIFCR_CHTIF4_Msk     (0x1U << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          
+#define DMA_HIFCR_CTEIF4_Pos     (3U)                                          
+#define DMA_HIFCR_CTEIF4_Msk     (0x1U << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          
+#define DMA_HIFCR_CDMEIF4_Pos    (2U)                                          
+#define DMA_HIFCR_CDMEIF4_Msk    (0x1U << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         
+#define DMA_HIFCR_CFEIF4_Pos     (0U)                                          
+#define DMA_HIFCR_CFEIF4_Msk     (0x1U << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          
+
+/******************  Bit definition for DMA_SxPAR register  ********************/
+#define DMA_SxPAR_PA_Pos         (0U)                                          
+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFU << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_SxM0AR register  ********************/
+#define DMA_SxM0AR_M0A_Pos       (0U)                                          
+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */
+
+/******************  Bit definition for DMA_SxM1AR register  ********************/
+#define DMA_SxM1AR_M1A_Pos       (0U)                                          
+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                         AHB Master DMA2D Controller (DMA2D)                */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DMA2D_CR register  ******************/
+
+#define DMA2D_CR_START_Pos         (0U)                                        
+#define DMA2D_CR_START_Msk         (0x1U << DMA2D_CR_START_Pos)                /*!< 0x00000001 */
+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer */
+#define DMA2D_CR_SUSP_Pos          (1U)                                        
+#define DMA2D_CR_SUSP_Msk          (0x1U << DMA2D_CR_SUSP_Pos)                 /*!< 0x00000002 */
+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer */
+#define DMA2D_CR_ABORT_Pos         (2U)                                        
+#define DMA2D_CR_ABORT_Msk         (0x1U << DMA2D_CR_ABORT_Pos)                /*!< 0x00000004 */
+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer */
+#define DMA2D_CR_TEIE_Pos          (8U)                                        
+#define DMA2D_CR_TEIE_Msk          (0x1U << DMA2D_CR_TEIE_Pos)                 /*!< 0x00000100 */
+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable */
+#define DMA2D_CR_TCIE_Pos          (9U)                                        
+#define DMA2D_CR_TCIE_Msk          (0x1U << DMA2D_CR_TCIE_Pos)                 /*!< 0x00000200 */
+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable */
+#define DMA2D_CR_TWIE_Pos          (10U)                                       
+#define DMA2D_CR_TWIE_Msk          (0x1U << DMA2D_CR_TWIE_Pos)                 /*!< 0x00000400 */
+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable */
+#define DMA2D_CR_CAEIE_Pos         (11U)                                       
+#define DMA2D_CR_CAEIE_Msk         (0x1U << DMA2D_CR_CAEIE_Pos)                /*!< 0x00000800 */
+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable */
+#define DMA2D_CR_CTCIE_Pos         (12U)                                       
+#define DMA2D_CR_CTCIE_Msk         (0x1U << DMA2D_CR_CTCIE_Pos)                /*!< 0x00001000 */
+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_Pos          (13U)                                       
+#define DMA2D_CR_CEIE_Msk          (0x1U << DMA2D_CR_CEIE_Pos)                 /*!< 0x00002000 */
+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable */
+#define DMA2D_CR_MODE_Pos          (16U)                                       
+#define DMA2D_CR_MODE_Msk          (0x3U << DMA2D_CR_MODE_Pos)                 /*!< 0x00030000 */
+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[1:0] */
+#define DMA2D_CR_MODE_0            (0x1U << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */
+#define DMA2D_CR_MODE_1            (0x2U << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */
+
+/********************  Bit definition for DMA2D_ISR register  *****************/
+
+#define DMA2D_ISR_TEIF_Pos         (0U)                                        
+#define DMA2D_ISR_TEIF_Msk         (0x1U << DMA2D_ISR_TEIF_Pos)                /*!< 0x00000001 */
+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag */
+#define DMA2D_ISR_TCIF_Pos         (1U)                                        
+#define DMA2D_ISR_TCIF_Msk         (0x1U << DMA2D_ISR_TCIF_Pos)                /*!< 0x00000002 */
+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_TWIF_Pos         (2U)                                        
+#define DMA2D_ISR_TWIF_Msk         (0x1U << DMA2D_ISR_TWIF_Pos)                /*!< 0x00000004 */
+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag */
+#define DMA2D_ISR_CAEIF_Pos        (3U)                                        
+#define DMA2D_ISR_CAEIF_Msk        (0x1U << DMA2D_ISR_CAEIF_Pos)               /*!< 0x00000008 */
+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag */
+#define DMA2D_ISR_CTCIF_Pos        (4U)                                        
+#define DMA2D_ISR_CTCIF_Msk        (0x1U << DMA2D_ISR_CTCIF_Pos)               /*!< 0x00000010 */
+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_Pos         (5U)                                        
+#define DMA2D_ISR_CEIF_Msk         (0x1U << DMA2D_ISR_CEIF_Pos)                /*!< 0x00000020 */
+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag */
+
+/********************  Bit definition for DMA2D_IFCR register  ****************/
+
+#define DMA2D_IFCR_CTEIF_Pos       (0U)                                        
+#define DMA2D_IFCR_CTEIF_Msk       (0x1U << DMA2D_IFCR_CTEIF_Pos)              /*!< 0x00000001 */
+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFCR_CTCIF_Pos       (1U)                                        
+#define DMA2D_IFCR_CTCIF_Msk       (0x1U << DMA2D_IFCR_CTCIF_Pos)              /*!< 0x00000002 */
+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFCR_CTWIF_Pos       (2U)                                        
+#define DMA2D_IFCR_CTWIF_Msk       (0x1U << DMA2D_IFCR_CTWIF_Pos)              /*!< 0x00000004 */
+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFCR_CAECIF_Pos      (3U)                                        
+#define DMA2D_IFCR_CAECIF_Msk      (0x1U << DMA2D_IFCR_CAECIF_Pos)             /*!< 0x00000008 */
+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFCR_CCTCIF_Pos      (4U)                                        
+#define DMA2D_IFCR_CCTCIF_Msk      (0x1U << DMA2D_IFCR_CCTCIF_Pos)             /*!< 0x00000010 */
+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_Pos       (5U)                                        
+#define DMA2D_IFCR_CCEIF_Msk       (0x1U << DMA2D_IFCR_CCEIF_Pos)              /*!< 0x00000020 */
+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */
+
+/* Legacy defines */
+#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_FGMAR register  ***************/
+
+#define DMA2D_FGMAR_MA_Pos         (0U)                                        
+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos)         /*!< 0xFFFFFFFF */
+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_FGOR register  ****************/
+
+#define DMA2D_FGOR_LO_Pos          (0U)                                        
+#define DMA2D_FGOR_LO_Msk          (0x3FFFU << DMA2D_FGOR_LO_Pos)              /*!< 0x00003FFF */
+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_BGMAR register  ***************/
+
+#define DMA2D_BGMAR_MA_Pos         (0U)                                        
+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos)         /*!< 0xFFFFFFFF */
+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGOR register  ****************/
+
+#define DMA2D_BGOR_LO_Pos          (0U)                                        
+#define DMA2D_BGOR_LO_Msk          (0x3FFFU << DMA2D_BGOR_LO_Pos)              /*!< 0x00003FFF */
+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/
+
+#define DMA2D_FGPFCCR_CM_Pos       (0U)                                        
+#define DMA2D_FGPFCCR_CM_Msk       (0xFU << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x0000000F */
+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0         (0x1U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_FGPFCCR_CM_1         (0x2U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_FGPFCCR_CM_2         (0x4U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_FGPFCCR_CM_3         (0x8U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */
+#define DMA2D_FGPFCCR_CCM_Pos      (4U)                                        
+#define DMA2D_FGPFCCR_CCM_Msk      (0x1U << DMA2D_FGPFCCR_CCM_Pos)             /*!< 0x00000010 */
+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_Pos    (5U)                                        
+#define DMA2D_FGPFCCR_START_Msk    (0x1U << DMA2D_FGPFCCR_START_Pos)           /*!< 0x00000020 */
+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_FGPFCCR_CS_Pos       (8U)                                        
+#define DMA2D_FGPFCCR_CS_Msk       (0xFFU << DMA2D_FGPFCCR_CS_Pos)             /*!< 0x0000FF00 */
+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_Pos       (16U)                                       
+#define DMA2D_FGPFCCR_AM_Msk       (0x3U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00030000 */
+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0         (0x1U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */
+#define DMA2D_FGPFCCR_AM_1         (0x2U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */
+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)                                       
+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */
+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_FGCOLR register  **************/
+
+#define DMA2D_FGCOLR_BLUE_Pos      (0U)                                        
+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFU << DMA2D_FGCOLR_BLUE_Pos)            /*!< 0x000000FF */
+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Blue Value */
+#define DMA2D_FGCOLR_GREEN_Pos     (8U)                                        
+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFU << DMA2D_FGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */
+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Green Value */
+#define DMA2D_FGCOLR_RED_Pos       (16U)                                       
+#define DMA2D_FGCOLR_RED_Msk       (0xFFU << DMA2D_FGCOLR_RED_Pos)             /*!< 0x00FF0000 */
+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Red Value */   
+
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/
+
+#define DMA2D_BGPFCCR_CM_Pos       (0U)                                        
+#define DMA2D_BGPFCCR_CM_Msk       (0xFU << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x0000000F */
+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0         (0x1U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_BGPFCCR_CM_1         (0x2U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_BGPFCCR_CM_2         (0x4U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_BGPFCCR_CM_3         0x00000008U                                 /*!< Input color mode CM bit 3 */
+#define DMA2D_BGPFCCR_CCM_Pos      (4U)                                        
+#define DMA2D_BGPFCCR_CCM_Msk      (0x1U << DMA2D_BGPFCCR_CCM_Pos)             /*!< 0x00000010 */
+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_Pos    (5U)                                        
+#define DMA2D_BGPFCCR_START_Msk    (0x1U << DMA2D_BGPFCCR_START_Pos)           /*!< 0x00000020 */
+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_BGPFCCR_CS_Pos       (8U)                                        
+#define DMA2D_BGPFCCR_CS_Msk       (0xFFU << DMA2D_BGPFCCR_CS_Pos)             /*!< 0x0000FF00 */
+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_Pos       (16U)                                       
+#define DMA2D_BGPFCCR_AM_Msk       (0x3U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00030000 */
+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0         (0x1U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */
+#define DMA2D_BGPFCCR_AM_1         (0x2U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */
+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)                                       
+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */
+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */
+
+/********************  Bit definition for DMA2D_BGCOLR register  **************/
+
+#define DMA2D_BGCOLR_BLUE_Pos      (0U)                                        
+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFU << DMA2D_BGCOLR_BLUE_Pos)            /*!< 0x000000FF */
+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Blue Value */
+#define DMA2D_BGCOLR_GREEN_Pos     (8U)                                        
+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFU << DMA2D_BGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */
+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Green Value */
+#define DMA2D_BGCOLR_RED_Pos       (16U)                                       
+#define DMA2D_BGCOLR_RED_Msk       (0xFFU << DMA2D_BGCOLR_RED_Pos)             /*!< 0x00FF0000 */
+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Red Value */
+
+/********************  Bit definition for DMA2D_FGCMAR register  **************/
+
+#define DMA2D_FGCMAR_MA_Pos        (0U)                                        
+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_BGCMAR register  **************/
+
+#define DMA2D_BGCMAR_MA_Pos        (0U)                                        
+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OPFCCR register  **************/
+
+#define DMA2D_OPFCCR_CM_Pos        (0U)                                        
+#define DMA2D_OPFCCR_CM_Msk        (0x7U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000007 */
+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0          (0x1U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000001 */
+#define DMA2D_OPFCCR_CM_1          (0x2U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000002 */
+#define DMA2D_OPFCCR_CM_2          (0x4U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000004 */
+
+/********************  Bit definition for DMA2D_OCOLR register  ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1         0x000000FFU                                 /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_1        0x0000FF00U                                 /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_1          0x00FF0000U                                 /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_1        0xFF000000U                                 /*!< Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2         0x0000001FU                                 /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_2        0x000007E0U                                 /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_2          0x0000F800U                                 /*!< Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3         0x0000001FU                                 /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_3        0x000003E0U                                 /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_3          0x00007C00U                                 /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_3        0x00008000U                                 /*!< Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4         0x0000000FU                                 /*!< BLUE Value */
+#define DMA2D_OCOLR_GREEN_4        0x000000F0U                                 /*!< GREEN Value  */
+#define DMA2D_OCOLR_RED_4          0x00000F00U                                 /*!< Red Value */
+#define DMA2D_OCOLR_ALPHA_4        0x0000F000U                                 /*!< Alpha Channel Value */
+
+/********************  Bit definition for DMA2D_OMAR register  ****************/
+
+#define DMA2D_OMAR_MA_Pos          (0U)                                        
+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos)          /*!< 0xFFFFFFFF */
+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Memory Address */
+
+/********************  Bit definition for DMA2D_OOR register  *****************/
+
+#define DMA2D_OOR_LO_Pos           (0U)                                        
+#define DMA2D_OOR_LO_Msk           (0x3FFFU << DMA2D_OOR_LO_Pos)               /*!< 0x00003FFF */
+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_NLR register  *****************/
+
+#define DMA2D_NLR_NL_Pos           (0U)                                        
+#define DMA2D_NLR_NL_Msk           (0xFFFFU << DMA2D_NLR_NL_Pos)               /*!< 0x0000FFFF */
+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
+#define DMA2D_NLR_PL_Pos           (16U)                                       
+#define DMA2D_NLR_PL_Msk           (0x3FFFU << DMA2D_NLR_PL_Pos)               /*!< 0x3FFF0000 */
+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
+
+/********************  Bit definition for DMA2D_LWR register  *****************/
+
+#define DMA2D_LWR_LW_Pos           (0U)                                        
+#define DMA2D_LWR_LW_Msk           (0xFFFFU << DMA2D_LWR_LW_Pos)               /*!< 0x0000FFFF */
+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
+
+/********************  Bit definition for DMA2D_AMTCR register  ***************/
+
+#define DMA2D_AMTCR_EN_Pos         (0U)                                        
+#define DMA2D_AMTCR_EN_Msk         (0x1U << DMA2D_AMTCR_EN_Pos)                /*!< 0x00000001 */
+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
+#define DMA2D_AMTCR_DT_Pos         (8U)                                        
+#define DMA2D_AMTCR_DT_Msk         (0xFFU << DMA2D_AMTCR_DT_Pos)               /*!< 0x0000FF00 */
+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
+
+/********************  Bit definition for DMA2D_FGCLUT register  **************/
+                                                                     
+/********************  Bit definition for DMA2D_BGCLUT register  **************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define EXTI_IMR_MR0_Pos          (0U)                                         
+#define EXTI_IMR_MR0_Msk          (0x1U << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */
+#define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos          (1U)                                         
+#define EXTI_IMR_MR1_Msk          (0x1U << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */
+#define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos          (2U)                                         
+#define EXTI_IMR_MR2_Msk          (0x1U << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */
+#define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos          (3U)                                         
+#define EXTI_IMR_MR3_Msk          (0x1U << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */
+#define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos          (4U)                                         
+#define EXTI_IMR_MR4_Msk          (0x1U << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */
+#define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos          (5U)                                         
+#define EXTI_IMR_MR5_Msk          (0x1U << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */
+#define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos          (6U)                                         
+#define EXTI_IMR_MR6_Msk          (0x1U << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */
+#define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos          (7U)                                         
+#define EXTI_IMR_MR7_Msk          (0x1U << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */
+#define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos          (8U)                                         
+#define EXTI_IMR_MR8_Msk          (0x1U << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */
+#define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos          (9U)                                         
+#define EXTI_IMR_MR9_Msk          (0x1U << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */
+#define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos         (10U)                                        
+#define EXTI_IMR_MR10_Msk         (0x1U << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */
+#define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos         (11U)                                        
+#define EXTI_IMR_MR11_Msk         (0x1U << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */
+#define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos         (12U)                                        
+#define EXTI_IMR_MR12_Msk         (0x1U << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */
+#define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos         (13U)                                        
+#define EXTI_IMR_MR13_Msk         (0x1U << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */
+#define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos         (14U)                                        
+#define EXTI_IMR_MR14_Msk         (0x1U << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */
+#define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos         (15U)                                        
+#define EXTI_IMR_MR15_Msk         (0x1U << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */
+#define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos         (16U)                                        
+#define EXTI_IMR_MR16_Msk         (0x1U << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */
+#define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos         (17U)                                        
+#define EXTI_IMR_MR17_Msk         (0x1U << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */
+#define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos         (18U)                                        
+#define EXTI_IMR_MR18_Msk         (0x1U << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */
+#define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos         (19U)                                        
+#define EXTI_IMR_MR19_Msk         (0x1U << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */
+#define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos         (20U)                                        
+#define EXTI_IMR_MR20_Msk         (0x1U << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */
+#define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos         (21U)                                        
+#define EXTI_IMR_MR21_Msk         (0x1U << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */
+#define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos         (22U)                                        
+#define EXTI_IMR_MR22_Msk         (0x1U << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */
+#define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */
+
+/* Reference Defines */
+#define  EXTI_IMR_IM0                        EXTI_IMR_MR0
+#define  EXTI_IMR_IM1                        EXTI_IMR_MR1
+#define  EXTI_IMR_IM2                        EXTI_IMR_MR2
+#define  EXTI_IMR_IM3                        EXTI_IMR_MR3
+#define  EXTI_IMR_IM4                        EXTI_IMR_MR4
+#define  EXTI_IMR_IM5                        EXTI_IMR_MR5
+#define  EXTI_IMR_IM6                        EXTI_IMR_MR6
+#define  EXTI_IMR_IM7                        EXTI_IMR_MR7
+#define  EXTI_IMR_IM8                        EXTI_IMR_MR8
+#define  EXTI_IMR_IM9                        EXTI_IMR_MR9
+#define  EXTI_IMR_IM10                       EXTI_IMR_MR10
+#define  EXTI_IMR_IM11                       EXTI_IMR_MR11
+#define  EXTI_IMR_IM12                       EXTI_IMR_MR12
+#define  EXTI_IMR_IM13                       EXTI_IMR_MR13
+#define  EXTI_IMR_IM14                       EXTI_IMR_MR14
+#define  EXTI_IMR_IM15                       EXTI_IMR_MR15
+#define  EXTI_IMR_IM16                       EXTI_IMR_MR16
+#define  EXTI_IMR_IM17                       EXTI_IMR_MR17
+#define  EXTI_IMR_IM18                       EXTI_IMR_MR18
+#define  EXTI_IMR_IM19                       EXTI_IMR_MR19
+#define  EXTI_IMR_IM20                       EXTI_IMR_MR20
+#define  EXTI_IMR_IM21                       EXTI_IMR_MR21
+#define  EXTI_IMR_IM22                       EXTI_IMR_MR22
+#define EXTI_IMR_IM_Pos           (0U)                                         
+#define EXTI_IMR_IM_Msk           (0x7FFFFFU << EXTI_IMR_IM_Pos)               /*!< 0x007FFFFF */
+#define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define EXTI_EMR_MR0_Pos          (0U)                                         
+#define EXTI_EMR_MR0_Msk          (0x1U << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */
+#define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos          (1U)                                         
+#define EXTI_EMR_MR1_Msk          (0x1U << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */
+#define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos          (2U)                                         
+#define EXTI_EMR_MR2_Msk          (0x1U << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */
+#define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos          (3U)                                         
+#define EXTI_EMR_MR3_Msk          (0x1U << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */
+#define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos          (4U)                                         
+#define EXTI_EMR_MR4_Msk          (0x1U << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */
+#define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos          (5U)                                         
+#define EXTI_EMR_MR5_Msk          (0x1U << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */
+#define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos          (6U)                                         
+#define EXTI_EMR_MR6_Msk          (0x1U << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */
+#define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos          (7U)                                         
+#define EXTI_EMR_MR7_Msk          (0x1U << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */
+#define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos          (8U)                                         
+#define EXTI_EMR_MR8_Msk          (0x1U << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */
+#define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos          (9U)                                         
+#define EXTI_EMR_MR9_Msk          (0x1U << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */
+#define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos         (10U)                                        
+#define EXTI_EMR_MR10_Msk         (0x1U << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */
+#define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos         (11U)                                        
+#define EXTI_EMR_MR11_Msk         (0x1U << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */
+#define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos         (12U)                                        
+#define EXTI_EMR_MR12_Msk         (0x1U << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */
+#define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos         (13U)                                        
+#define EXTI_EMR_MR13_Msk         (0x1U << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */
+#define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos         (14U)                                        
+#define EXTI_EMR_MR14_Msk         (0x1U << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */
+#define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos         (15U)                                        
+#define EXTI_EMR_MR15_Msk         (0x1U << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */
+#define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos         (16U)                                        
+#define EXTI_EMR_MR16_Msk         (0x1U << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */
+#define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos         (17U)                                        
+#define EXTI_EMR_MR17_Msk         (0x1U << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */
+#define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos         (18U)                                        
+#define EXTI_EMR_MR18_Msk         (0x1U << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */
+#define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos         (19U)                                        
+#define EXTI_EMR_MR19_Msk         (0x1U << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */
+#define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos         (20U)                                        
+#define EXTI_EMR_MR20_Msk         (0x1U << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */
+#define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos         (21U)                                        
+#define EXTI_EMR_MR21_Msk         (0x1U << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */
+#define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos         (22U)                                        
+#define EXTI_EMR_MR22_Msk         (0x1U << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */
+#define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */
+
+/* Reference Defines */
+#define  EXTI_EMR_EM0                        EXTI_EMR_MR0
+#define  EXTI_EMR_EM1                        EXTI_EMR_MR1
+#define  EXTI_EMR_EM2                        EXTI_EMR_MR2
+#define  EXTI_EMR_EM3                        EXTI_EMR_MR3
+#define  EXTI_EMR_EM4                        EXTI_EMR_MR4
+#define  EXTI_EMR_EM5                        EXTI_EMR_MR5
+#define  EXTI_EMR_EM6                        EXTI_EMR_MR6
+#define  EXTI_EMR_EM7                        EXTI_EMR_MR7
+#define  EXTI_EMR_EM8                        EXTI_EMR_MR8
+#define  EXTI_EMR_EM9                        EXTI_EMR_MR9
+#define  EXTI_EMR_EM10                       EXTI_EMR_MR10
+#define  EXTI_EMR_EM11                       EXTI_EMR_MR11
+#define  EXTI_EMR_EM12                       EXTI_EMR_MR12
+#define  EXTI_EMR_EM13                       EXTI_EMR_MR13
+#define  EXTI_EMR_EM14                       EXTI_EMR_MR14
+#define  EXTI_EMR_EM15                       EXTI_EMR_MR15
+#define  EXTI_EMR_EM16                       EXTI_EMR_MR16
+#define  EXTI_EMR_EM17                       EXTI_EMR_MR17
+#define  EXTI_EMR_EM18                       EXTI_EMR_MR18
+#define  EXTI_EMR_EM19                       EXTI_EMR_MR19
+#define  EXTI_EMR_EM20                       EXTI_EMR_MR20
+#define  EXTI_EMR_EM21                       EXTI_EMR_MR21
+#define  EXTI_EMR_EM22                       EXTI_EMR_MR22
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define EXTI_RTSR_TR0_Pos         (0U)                                         
+#define EXTI_RTSR_TR0_Msk         (0x1U << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */
+#define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos         (1U)                                         
+#define EXTI_RTSR_TR1_Msk         (0x1U << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */
+#define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos         (2U)                                         
+#define EXTI_RTSR_TR2_Msk         (0x1U << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */
+#define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos         (3U)                                         
+#define EXTI_RTSR_TR3_Msk         (0x1U << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */
+#define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos         (4U)                                         
+#define EXTI_RTSR_TR4_Msk         (0x1U << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */
+#define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos         (5U)                                         
+#define EXTI_RTSR_TR5_Msk         (0x1U << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */
+#define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos         (6U)                                         
+#define EXTI_RTSR_TR6_Msk         (0x1U << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */
+#define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos         (7U)                                         
+#define EXTI_RTSR_TR7_Msk         (0x1U << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */
+#define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos         (8U)                                         
+#define EXTI_RTSR_TR8_Msk         (0x1U << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */
+#define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos         (9U)                                         
+#define EXTI_RTSR_TR9_Msk         (0x1U << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */
+#define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos        (10U)                                        
+#define EXTI_RTSR_TR10_Msk        (0x1U << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */
+#define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos        (11U)                                        
+#define EXTI_RTSR_TR11_Msk        (0x1U << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */
+#define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos        (12U)                                        
+#define EXTI_RTSR_TR12_Msk        (0x1U << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */
+#define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos        (13U)                                        
+#define EXTI_RTSR_TR13_Msk        (0x1U << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */
+#define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos        (14U)                                        
+#define EXTI_RTSR_TR14_Msk        (0x1U << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */
+#define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos        (15U)                                        
+#define EXTI_RTSR_TR15_Msk        (0x1U << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */
+#define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos        (16U)                                        
+#define EXTI_RTSR_TR16_Msk        (0x1U << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */
+#define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos        (17U)                                        
+#define EXTI_RTSR_TR17_Msk        (0x1U << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */
+#define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos        (18U)                                        
+#define EXTI_RTSR_TR18_Msk        (0x1U << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */
+#define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos        (19U)                                        
+#define EXTI_RTSR_TR19_Msk        (0x1U << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */
+#define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos        (20U)                                        
+#define EXTI_RTSR_TR20_Msk        (0x1U << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */
+#define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos        (21U)                                        
+#define EXTI_RTSR_TR21_Msk        (0x1U << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */
+#define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos        (22U)                                        
+#define EXTI_RTSR_TR22_Msk        (0x1U << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */
+#define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define EXTI_FTSR_TR0_Pos         (0U)                                         
+#define EXTI_FTSR_TR0_Msk         (0x1U << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */
+#define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos         (1U)                                         
+#define EXTI_FTSR_TR1_Msk         (0x1U << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */
+#define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos         (2U)                                         
+#define EXTI_FTSR_TR2_Msk         (0x1U << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */
+#define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos         (3U)                                         
+#define EXTI_FTSR_TR3_Msk         (0x1U << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */
+#define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos         (4U)                                         
+#define EXTI_FTSR_TR4_Msk         (0x1U << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */
+#define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos         (5U)                                         
+#define EXTI_FTSR_TR5_Msk         (0x1U << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */
+#define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos         (6U)                                         
+#define EXTI_FTSR_TR6_Msk         (0x1U << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */
+#define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos         (7U)                                         
+#define EXTI_FTSR_TR7_Msk         (0x1U << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */
+#define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos         (8U)                                         
+#define EXTI_FTSR_TR8_Msk         (0x1U << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */
+#define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos         (9U)                                         
+#define EXTI_FTSR_TR9_Msk         (0x1U << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */
+#define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos        (10U)                                        
+#define EXTI_FTSR_TR10_Msk        (0x1U << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */
+#define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos        (11U)                                        
+#define EXTI_FTSR_TR11_Msk        (0x1U << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */
+#define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos        (12U)                                        
+#define EXTI_FTSR_TR12_Msk        (0x1U << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */
+#define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos        (13U)                                        
+#define EXTI_FTSR_TR13_Msk        (0x1U << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */
+#define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos        (14U)                                        
+#define EXTI_FTSR_TR14_Msk        (0x1U << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */
+#define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos        (15U)                                        
+#define EXTI_FTSR_TR15_Msk        (0x1U << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */
+#define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos        (16U)                                        
+#define EXTI_FTSR_TR16_Msk        (0x1U << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */
+#define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos        (17U)                                        
+#define EXTI_FTSR_TR17_Msk        (0x1U << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */
+#define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos        (18U)                                        
+#define EXTI_FTSR_TR18_Msk        (0x1U << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */
+#define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos        (19U)                                        
+#define EXTI_FTSR_TR19_Msk        (0x1U << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */
+#define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos        (20U)                                        
+#define EXTI_FTSR_TR20_Msk        (0x1U << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */
+#define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos        (21U)                                        
+#define EXTI_FTSR_TR21_Msk        (0x1U << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */
+#define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos        (22U)                                        
+#define EXTI_FTSR_TR22_Msk        (0x1U << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */
+#define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define EXTI_SWIER_SWIER0_Pos     (0U)                                         
+#define EXTI_SWIER_SWIER0_Msk     (0x1U << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos     (1U)                                         
+#define EXTI_SWIER_SWIER1_Msk     (0x1U << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos     (2U)                                         
+#define EXTI_SWIER_SWIER2_Msk     (0x1U << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos     (3U)                                         
+#define EXTI_SWIER_SWIER3_Msk     (0x1U << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos     (4U)                                         
+#define EXTI_SWIER_SWIER4_Msk     (0x1U << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos     (5U)                                         
+#define EXTI_SWIER_SWIER5_Msk     (0x1U << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos     (6U)                                         
+#define EXTI_SWIER_SWIER6_Msk     (0x1U << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos     (7U)                                         
+#define EXTI_SWIER_SWIER7_Msk     (0x1U << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos     (8U)                                         
+#define EXTI_SWIER_SWIER8_Msk     (0x1U << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos     (9U)                                         
+#define EXTI_SWIER_SWIER9_Msk     (0x1U << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos    (10U)                                        
+#define EXTI_SWIER_SWIER10_Msk    (0x1U << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos    (11U)                                        
+#define EXTI_SWIER_SWIER11_Msk    (0x1U << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos    (12U)                                        
+#define EXTI_SWIER_SWIER12_Msk    (0x1U << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos    (13U)                                        
+#define EXTI_SWIER_SWIER13_Msk    (0x1U << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos    (14U)                                        
+#define EXTI_SWIER_SWIER14_Msk    (0x1U << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos    (15U)                                        
+#define EXTI_SWIER_SWIER15_Msk    (0x1U << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos    (16U)                                        
+#define EXTI_SWIER_SWIER16_Msk    (0x1U << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos    (17U)                                        
+#define EXTI_SWIER_SWIER17_Msk    (0x1U << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos    (18U)                                        
+#define EXTI_SWIER_SWIER18_Msk    (0x1U << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos    (19U)                                        
+#define EXTI_SWIER_SWIER19_Msk    (0x1U << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos    (20U)                                        
+#define EXTI_SWIER_SWIER20_Msk    (0x1U << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos    (21U)                                        
+#define EXTI_SWIER_SWIER21_Msk    (0x1U << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos    (22U)                                        
+#define EXTI_SWIER_SWIER22_Msk    (0x1U << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define EXTI_PR_PR0_Pos           (0U)                                         
+#define EXTI_PR_PR0_Msk           (0x1U << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */
+#define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos           (1U)                                         
+#define EXTI_PR_PR1_Msk           (0x1U << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */
+#define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos           (2U)                                         
+#define EXTI_PR_PR2_Msk           (0x1U << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */
+#define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos           (3U)                                         
+#define EXTI_PR_PR3_Msk           (0x1U << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */
+#define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos           (4U)                                         
+#define EXTI_PR_PR4_Msk           (0x1U << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */
+#define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos           (5U)                                         
+#define EXTI_PR_PR5_Msk           (0x1U << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */
+#define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos           (6U)                                         
+#define EXTI_PR_PR6_Msk           (0x1U << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */
+#define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos           (7U)                                         
+#define EXTI_PR_PR7_Msk           (0x1U << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */
+#define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos           (8U)                                         
+#define EXTI_PR_PR8_Msk           (0x1U << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */
+#define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos           (9U)                                         
+#define EXTI_PR_PR9_Msk           (0x1U << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */
+#define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos          (10U)                                        
+#define EXTI_PR_PR10_Msk          (0x1U << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */
+#define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos          (11U)                                        
+#define EXTI_PR_PR11_Msk          (0x1U << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */
+#define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos          (12U)                                        
+#define EXTI_PR_PR12_Msk          (0x1U << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */
+#define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos          (13U)                                        
+#define EXTI_PR_PR13_Msk          (0x1U << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */
+#define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos          (14U)                                        
+#define EXTI_PR_PR14_Msk          (0x1U << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */
+#define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos          (15U)                                        
+#define EXTI_PR_PR15_Msk          (0x1U << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */
+#define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos          (16U)                                        
+#define EXTI_PR_PR16_Msk          (0x1U << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */
+#define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos          (17U)                                        
+#define EXTI_PR_PR17_Msk          (0x1U << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */
+#define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos          (18U)                                        
+#define EXTI_PR_PR18_Msk          (0x1U << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */
+#define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos          (19U)                                        
+#define EXTI_PR_PR19_Msk          (0x1U << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */
+#define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos          (20U)                                        
+#define EXTI_PR_PR20_Msk          (0x1U << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */
+#define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos          (21U)                                        
+#define EXTI_PR_PR21_Msk          (0x1U << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */
+#define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos          (22U)                                        
+#define EXTI_PR_PR22_Msk          (0x1U << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */
+#define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for FLASH_ACR register  *****************/
+#define FLASH_ACR_LATENCY_Pos          (0U)                                    
+#define FLASH_ACR_LATENCY_Msk          (0xFU << FLASH_ACR_LATENCY_Pos)         /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk                   
+#define FLASH_ACR_LATENCY_0WS          0x00000000U                             
+#define FLASH_ACR_LATENCY_1WS          0x00000001U                             
+#define FLASH_ACR_LATENCY_2WS          0x00000002U                             
+#define FLASH_ACR_LATENCY_3WS          0x00000003U                             
+#define FLASH_ACR_LATENCY_4WS          0x00000004U                             
+#define FLASH_ACR_LATENCY_5WS          0x00000005U                             
+#define FLASH_ACR_LATENCY_6WS          0x00000006U                             
+#define FLASH_ACR_LATENCY_7WS          0x00000007U                             
+
+#define FLASH_ACR_LATENCY_8WS          0x00000008U                             
+#define FLASH_ACR_LATENCY_9WS          0x00000009U                             
+#define FLASH_ACR_LATENCY_10WS         0x0000000AU                             
+#define FLASH_ACR_LATENCY_11WS         0x0000000BU                             
+#define FLASH_ACR_LATENCY_12WS         0x0000000CU                             
+#define FLASH_ACR_LATENCY_13WS         0x0000000DU                             
+#define FLASH_ACR_LATENCY_14WS         0x0000000EU                             
+#define FLASH_ACR_LATENCY_15WS         0x0000000FU                             
+#define FLASH_ACR_PRFTEN_Pos           (8U)                                    
+#define FLASH_ACR_PRFTEN_Msk           (0x1U << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk                    
+#define FLASH_ACR_ICEN_Pos             (9U)                                    
+#define FLASH_ACR_ICEN_Msk             (0x1U << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */
+#define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk                      
+#define FLASH_ACR_DCEN_Pos             (10U)                                   
+#define FLASH_ACR_DCEN_Msk             (0x1U << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */
+#define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk                      
+#define FLASH_ACR_ICRST_Pos            (11U)                                   
+#define FLASH_ACR_ICRST_Msk            (0x1U << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */
+#define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk                     
+#define FLASH_ACR_DCRST_Pos            (12U)                                   
+#define FLASH_ACR_DCRST_Msk            (0x1U << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */
+#define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk                     
+#define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)                                   
+#define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk             
+#define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)                                    
+#define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk             
+
+/*******************  Bits definition for FLASH_SR register  ******************/
+#define FLASH_SR_EOP_Pos               (0U)                                    
+#define FLASH_SR_EOP_Msk               (0x1U << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */
+#define FLASH_SR_EOP                   FLASH_SR_EOP_Msk                        
+#define FLASH_SR_SOP_Pos               (1U)                                    
+#define FLASH_SR_SOP_Msk               (0x1U << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */
+#define FLASH_SR_SOP                   FLASH_SR_SOP_Msk                        
+#define FLASH_SR_WRPERR_Pos            (4U)                                    
+#define FLASH_SR_WRPERR_Msk            (0x1U << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */
+#define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk                     
+#define FLASH_SR_PGAERR_Pos            (5U)                                    
+#define FLASH_SR_PGAERR_Msk            (0x1U << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */
+#define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk                     
+#define FLASH_SR_PGPERR_Pos            (6U)                                    
+#define FLASH_SR_PGPERR_Msk            (0x1U << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */
+#define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk                     
+#define FLASH_SR_PGSERR_Pos            (7U)                                    
+#define FLASH_SR_PGSERR_Msk            (0x1U << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */
+#define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk                     
+#define FLASH_SR_BSY_Pos               (16U)                                   
+#define FLASH_SR_BSY_Msk               (0x1U << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */
+#define FLASH_SR_BSY                   FLASH_SR_BSY_Msk                        
+
+/*******************  Bits definition for FLASH_CR register  ******************/
+#define FLASH_CR_PG_Pos                (0U)                                    
+#define FLASH_CR_PG_Msk                (0x1U << FLASH_CR_PG_Pos)               /*!< 0x00000001 */
+#define FLASH_CR_PG                    FLASH_CR_PG_Msk                         
+#define FLASH_CR_SER_Pos               (1U)                                    
+#define FLASH_CR_SER_Msk               (0x1U << FLASH_CR_SER_Pos)              /*!< 0x00000002 */
+#define FLASH_CR_SER                   FLASH_CR_SER_Msk                        
+#define FLASH_CR_MER_Pos               (2U)                                    
+#define FLASH_CR_MER_Msk               (0x1U << FLASH_CR_MER_Pos)              /*!< 0x00000004 */
+#define FLASH_CR_MER                   FLASH_CR_MER_Msk                        
+#define FLASH_CR_MER1                        FLASH_CR_MER
+#define FLASH_CR_SNB_Pos               (3U)                                    
+#define FLASH_CR_SNB_Msk               (0x1FU << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */
+#define FLASH_CR_SNB                   FLASH_CR_SNB_Msk                        
+#define FLASH_CR_SNB_0                 (0x01U << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */
+#define FLASH_CR_SNB_1                 (0x02U << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */
+#define FLASH_CR_SNB_2                 (0x04U << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */
+#define FLASH_CR_SNB_3                 (0x08U << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */
+#define FLASH_CR_SNB_4                 (0x10U << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos             (8U)                                    
+#define FLASH_CR_PSIZE_Msk             (0x3U << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */
+#define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk                      
+#define FLASH_CR_PSIZE_0               (0x1U << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1               (0x2U << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */
+#define FLASH_CR_MER2_Pos              (15U)                                   
+#define FLASH_CR_MER2_Msk              (0x1U << FLASH_CR_MER2_Pos)             /*!< 0x00008000 */
+#define FLASH_CR_MER2                  FLASH_CR_MER2_Msk                       
+#define FLASH_CR_STRT_Pos              (16U)                                   
+#define FLASH_CR_STRT_Msk              (0x1U << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */
+#define FLASH_CR_STRT                  FLASH_CR_STRT_Msk                       
+#define FLASH_CR_EOPIE_Pos             (24U)                                   
+#define FLASH_CR_EOPIE_Msk             (0x1U << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */
+#define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk                      
+#define FLASH_CR_LOCK_Pos              (31U)                                   
+#define FLASH_CR_LOCK_Msk              (0x1U << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */
+#define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk                       
+
+/*******************  Bits definition for FLASH_OPTCR register  ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos        (0U)                                    
+#define FLASH_OPTCR_OPTLOCK_Msk        (0x1U << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk                 
+#define FLASH_OPTCR_OPTSTRT_Pos        (1U)                                    
+#define FLASH_OPTCR_OPTSTRT_Msk        (0x1U << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk                 
+
+#define FLASH_OPTCR_BOR_LEV_0          0x00000004U                             
+#define FLASH_OPTCR_BOR_LEV_1          0x00000008U                             
+#define FLASH_OPTCR_BOR_LEV_Pos        (2U)                                    
+#define FLASH_OPTCR_BOR_LEV_Msk        (0x3U << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk                 
+#define FLASH_OPTCR_BFB2_Pos           (4U)                                    
+#define FLASH_OPTCR_BFB2_Msk           (0x1U << FLASH_OPTCR_BFB2_Pos)          /*!< 0x00000010 */
+#define FLASH_OPTCR_BFB2               FLASH_OPTCR_BFB2_Msk                    
+#define FLASH_OPTCR_WDG_SW_Pos         (5U)                                    
+#define FLASH_OPTCR_WDG_SW_Msk         (0x1U << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk                  
+#define FLASH_OPTCR_nRST_STOP_Pos      (6U)                                    
+#define FLASH_OPTCR_nRST_STOP_Msk      (0x1U << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk               
+#define FLASH_OPTCR_nRST_STDBY_Pos     (7U)                                    
+#define FLASH_OPTCR_nRST_STDBY_Msk     (0x1U << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk              
+#define FLASH_OPTCR_RDP_Pos            (8U)                                    
+#define FLASH_OPTCR_RDP_Msk            (0xFFU << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk                     
+#define FLASH_OPTCR_RDP_0              (0x01U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1              (0x02U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2              (0x04U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3              (0x08U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4              (0x10U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5              (0x20U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6              (0x40U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7              (0x80U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos           (16U)                                   
+#define FLASH_OPTCR_nWRP_Msk           (0xFFFU << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */
+#define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk                    
+#define FLASH_OPTCR_nWRP_0             0x00010000U                             
+#define FLASH_OPTCR_nWRP_1             0x00020000U                             
+#define FLASH_OPTCR_nWRP_2             0x00040000U                             
+#define FLASH_OPTCR_nWRP_3             0x00080000U                             
+#define FLASH_OPTCR_nWRP_4             0x00100000U                             
+#define FLASH_OPTCR_nWRP_5             0x00200000U                             
+#define FLASH_OPTCR_nWRP_6             0x00400000U                             
+#define FLASH_OPTCR_nWRP_7             0x00800000U                             
+#define FLASH_OPTCR_nWRP_8             0x01000000U                             
+#define FLASH_OPTCR_nWRP_9             0x02000000U                             
+#define FLASH_OPTCR_nWRP_10            0x04000000U                             
+#define FLASH_OPTCR_nWRP_11            0x08000000U                             
+#define FLASH_OPTCR_DB1M_Pos           (30U)                                   
+#define FLASH_OPTCR_DB1M_Msk           (0x1U << FLASH_OPTCR_DB1M_Pos)          /*!< 0x40000000 */
+#define FLASH_OPTCR_DB1M               FLASH_OPTCR_DB1M_Msk                    
+#define FLASH_OPTCR_SPRMOD_Pos         (31U)                                   
+#define FLASH_OPTCR_SPRMOD_Msk         (0x1U << FLASH_OPTCR_SPRMOD_Pos)        /*!< 0x80000000 */
+#define FLASH_OPTCR_SPRMOD             FLASH_OPTCR_SPRMOD_Msk                  
+                                             
+/******************  Bits definition for FLASH_OPTCR1 register  ***************/
+#define FLASH_OPTCR1_nWRP_Pos          (16U)                                   
+#define FLASH_OPTCR1_nWRP_Msk          (0xFFFU << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk                   
+#define FLASH_OPTCR1_nWRP_0            (0x001U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1            (0x002U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2            (0x004U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3            (0x008U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4            (0x010U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5            (0x020U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6            (0x040U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7            (0x080U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8            (0x100U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9            (0x200U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10           (0x400U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11           (0x800U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define FMC_BCR1_MBKEN_Pos          (0U)                                       
+#define FMC_BCR1_MBKEN_Msk          (0x1U << FMC_BCR1_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCR1_MBKEN              FMC_BCR1_MBKEN_Msk                         /*!<Memory bank enable bit                 */
+#define FMC_BCR1_MUXEN_Pos          (1U)                                       
+#define FMC_BCR1_MUXEN_Msk          (0x1U << FMC_BCR1_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCR1_MUXEN              FMC_BCR1_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCR1_MTYP_Pos           (2U)                                       
+#define FMC_BCR1_MTYP_Msk           (0x3U << FMC_BCR1_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCR1_MTYP               FMC_BCR1_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCR1_MTYP_0             (0x1U << FMC_BCR1_MTYP_Pos)                /*!< 0x00000004 */
+#define FMC_BCR1_MTYP_1             (0x2U << FMC_BCR1_MTYP_Pos)                /*!< 0x00000008 */
+
+#define FMC_BCR1_MWID_Pos           (4U)                                       
+#define FMC_BCR1_MWID_Msk           (0x3U << FMC_BCR1_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCR1_MWID               FMC_BCR1_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0             (0x1U << FMC_BCR1_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_BCR1_MWID_1             (0x2U << FMC_BCR1_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_BCR1_FACCEN_Pos         (6U)                                       
+#define FMC_BCR1_FACCEN_Msk         (0x1U << FMC_BCR1_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCR1_FACCEN             FMC_BCR1_FACCEN_Msk                        /*!<Flash access enable        */
+#define FMC_BCR1_BURSTEN_Pos        (8U)                                       
+#define FMC_BCR1_BURSTEN_Msk        (0x1U << FMC_BCR1_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCR1_BURSTEN            FMC_BCR1_BURSTEN_Msk                       /*!<Burst enable bit           */
+#define FMC_BCR1_WAITPOL_Pos        (9U)                                       
+#define FMC_BCR1_WAITPOL_Msk        (0x1U << FMC_BCR1_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCR1_WAITPOL            FMC_BCR1_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
+#define FMC_BCR1_WRAPMOD_Pos        (10U)                                      
+#define FMC_BCR1_WRAPMOD_Msk        (0x1U << FMC_BCR1_WRAPMOD_Pos)             /*!< 0x00000400 */
+#define FMC_BCR1_WRAPMOD            FMC_BCR1_WRAPMOD_Msk                       /*!<Wrapped burst mode support */
+#define FMC_BCR1_WAITCFG_Pos        (11U)                                      
+#define FMC_BCR1_WAITCFG_Msk        (0x1U << FMC_BCR1_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCR1_WAITCFG            FMC_BCR1_WAITCFG_Msk                       /*!<Wait timing configuration  */
+#define FMC_BCR1_WREN_Pos           (12U)                                      
+#define FMC_BCR1_WREN_Msk           (0x1U << FMC_BCR1_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCR1_WREN               FMC_BCR1_WREN_Msk                          /*!<Write enable bit           */
+#define FMC_BCR1_WAITEN_Pos         (13U)                                      
+#define FMC_BCR1_WAITEN_Msk         (0x1U << FMC_BCR1_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCR1_WAITEN             FMC_BCR1_WAITEN_Msk                        /*!<Wait enable bit            */
+#define FMC_BCR1_EXTMOD_Pos         (14U)                                      
+#define FMC_BCR1_EXTMOD_Msk         (0x1U << FMC_BCR1_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCR1_EXTMOD             FMC_BCR1_EXTMOD_Msk                        /*!<Extended mode enable       */
+#define FMC_BCR1_ASYNCWAIT_Pos      (15U)                                      
+#define FMC_BCR1_ASYNCWAIT_Msk      (0x1U << FMC_BCR1_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCR1_ASYNCWAIT          FMC_BCR1_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
+#define FMC_BCR1_CPSIZE_Pos         (16U)                                      
+#define FMC_BCR1_CPSIZE_Msk         (0x7U << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00070000 */
+#define FMC_BCR1_CPSIZE             FMC_BCR1_CPSIZE_Msk                        /*!<CRAM page size             */
+#define FMC_BCR1_CPSIZE_0           (0x1U << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00010000 */
+#define FMC_BCR1_CPSIZE_1           (0x2U << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00020000 */
+#define FMC_BCR1_CPSIZE_2           (0x4U << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00040000 */
+#define FMC_BCR1_CBURSTRW_Pos       (19U)                                      
+#define FMC_BCR1_CBURSTRW_Msk       (0x1U << FMC_BCR1_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCR1_CBURSTRW           FMC_BCR1_CBURSTRW_Msk                      /*!<Write burst enable         */
+#define FMC_BCR1_CCLKEN_Pos         (20U)                                      
+#define FMC_BCR1_CCLKEN_Msk         (0x1U << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN             FMC_BCR1_CCLKEN_Msk                        /*!<Continous clock enable     */
+
+/******************  Bit definition for FMC_BCR2 register  *******************/
+#define FMC_BCR2_MBKEN_Pos          (0U)                                       
+#define FMC_BCR2_MBKEN_Msk          (0x1U << FMC_BCR2_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCR2_MBKEN              FMC_BCR2_MBKEN_Msk                         /*!<Memory bank enable bit                 */
+#define FMC_BCR2_MUXEN_Pos          (1U)                                       
+#define FMC_BCR2_MUXEN_Msk          (0x1U << FMC_BCR2_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCR2_MUXEN              FMC_BCR2_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCR2_MTYP_Pos           (2U)                                       
+#define FMC_BCR2_MTYP_Msk           (0x3U << FMC_BCR2_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCR2_MTYP               FMC_BCR2_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCR2_MTYP_0             (0x1U << FMC_BCR2_MTYP_Pos)                /*!< 0x00000004 */
+#define FMC_BCR2_MTYP_1             (0x2U << FMC_BCR2_MTYP_Pos)                /*!< 0x00000008 */
+
+#define FMC_BCR2_MWID_Pos           (4U)                                       
+#define FMC_BCR2_MWID_Msk           (0x3U << FMC_BCR2_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCR2_MWID               FMC_BCR2_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0             (0x1U << FMC_BCR2_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_BCR2_MWID_1             (0x2U << FMC_BCR2_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_BCR2_FACCEN_Pos         (6U)                                       
+#define FMC_BCR2_FACCEN_Msk         (0x1U << FMC_BCR2_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCR2_FACCEN             FMC_BCR2_FACCEN_Msk                        /*!<Flash access enable        */
+#define FMC_BCR2_BURSTEN_Pos        (8U)                                       
+#define FMC_BCR2_BURSTEN_Msk        (0x1U << FMC_BCR2_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCR2_BURSTEN            FMC_BCR2_BURSTEN_Msk                       /*!<Burst enable bit           */
+#define FMC_BCR2_WAITPOL_Pos        (9U)                                       
+#define FMC_BCR2_WAITPOL_Msk        (0x1U << FMC_BCR2_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCR2_WAITPOL            FMC_BCR2_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
+#define FMC_BCR2_WRAPMOD_Pos        (10U)                                      
+#define FMC_BCR2_WRAPMOD_Msk        (0x1U << FMC_BCR2_WRAPMOD_Pos)             /*!< 0x00000400 */
+#define FMC_BCR2_WRAPMOD            FMC_BCR2_WRAPMOD_Msk                       /*!<Wrapped burst mode support */
+#define FMC_BCR2_WAITCFG_Pos        (11U)                                      
+#define FMC_BCR2_WAITCFG_Msk        (0x1U << FMC_BCR2_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCR2_WAITCFG            FMC_BCR2_WAITCFG_Msk                       /*!<Wait timing configuration  */
+#define FMC_BCR2_WREN_Pos           (12U)                                      
+#define FMC_BCR2_WREN_Msk           (0x1U << FMC_BCR2_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCR2_WREN               FMC_BCR2_WREN_Msk                          /*!<Write enable bit           */
+#define FMC_BCR2_WAITEN_Pos         (13U)                                      
+#define FMC_BCR2_WAITEN_Msk         (0x1U << FMC_BCR2_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCR2_WAITEN             FMC_BCR2_WAITEN_Msk                        /*!<Wait enable bit            */
+#define FMC_BCR2_EXTMOD_Pos         (14U)                                      
+#define FMC_BCR2_EXTMOD_Msk         (0x1U << FMC_BCR2_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCR2_EXTMOD             FMC_BCR2_EXTMOD_Msk                        /*!<Extended mode enable       */
+#define FMC_BCR2_ASYNCWAIT_Pos      (15U)                                      
+#define FMC_BCR2_ASYNCWAIT_Msk      (0x1U << FMC_BCR2_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCR2_ASYNCWAIT          FMC_BCR2_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
+#define FMC_BCR2_CPSIZE_Pos         (16U)                                      
+#define FMC_BCR2_CPSIZE_Msk         (0x7U << FMC_BCR2_CPSIZE_Pos)              /*!< 0x00070000 */
+#define FMC_BCR2_CPSIZE             FMC_BCR2_CPSIZE_Msk                        /*!<CRAM page size */
+#define FMC_BCR2_CPSIZE_0           (0x1U << FMC_BCR2_CPSIZE_Pos)              /*!< 0x00010000 */
+#define FMC_BCR2_CPSIZE_1           (0x2U << FMC_BCR2_CPSIZE_Pos)              /*!< 0x00020000 */
+#define FMC_BCR2_CPSIZE_2           (0x4U << FMC_BCR2_CPSIZE_Pos)              /*!< 0x00040000 */
+#define FMC_BCR2_CBURSTRW_Pos       (19U)                                      
+#define FMC_BCR2_CBURSTRW_Msk       (0x1U << FMC_BCR2_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCR2_CBURSTRW           FMC_BCR2_CBURSTRW_Msk                      /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BCR3 register  *******************/
+#define FMC_BCR3_MBKEN_Pos          (0U)                                       
+#define FMC_BCR3_MBKEN_Msk          (0x1U << FMC_BCR3_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCR3_MBKEN              FMC_BCR3_MBKEN_Msk                         /*!<Memory bank enable bit                 */
+#define FMC_BCR3_MUXEN_Pos          (1U)                                       
+#define FMC_BCR3_MUXEN_Msk          (0x1U << FMC_BCR3_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCR3_MUXEN              FMC_BCR3_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCR3_MTYP_Pos           (2U)                                       
+#define FMC_BCR3_MTYP_Msk           (0x3U << FMC_BCR3_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCR3_MTYP               FMC_BCR3_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCR3_MTYP_0             (0x1U << FMC_BCR3_MTYP_Pos)                /*!< 0x00000004 */
+#define FMC_BCR3_MTYP_1             (0x2U << FMC_BCR3_MTYP_Pos)                /*!< 0x00000008 */
+
+#define FMC_BCR3_MWID_Pos           (4U)                                       
+#define FMC_BCR3_MWID_Msk           (0x3U << FMC_BCR3_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCR3_MWID               FMC_BCR3_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0             (0x1U << FMC_BCR3_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_BCR3_MWID_1             (0x2U << FMC_BCR3_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_BCR3_FACCEN_Pos         (6U)                                       
+#define FMC_BCR3_FACCEN_Msk         (0x1U << FMC_BCR3_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCR3_FACCEN             FMC_BCR3_FACCEN_Msk                        /*!<Flash access enable        */
+#define FMC_BCR3_BURSTEN_Pos        (8U)                                       
+#define FMC_BCR3_BURSTEN_Msk        (0x1U << FMC_BCR3_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCR3_BURSTEN            FMC_BCR3_BURSTEN_Msk                       /*!<Burst enable bit           */
+#define FMC_BCR3_WAITPOL_Pos        (9U)                                       
+#define FMC_BCR3_WAITPOL_Msk        (0x1U << FMC_BCR3_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCR3_WAITPOL            FMC_BCR3_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
+#define FMC_BCR3_WRAPMOD_Pos        (10U)                                      
+#define FMC_BCR3_WRAPMOD_Msk        (0x1U << FMC_BCR3_WRAPMOD_Pos)             /*!< 0x00000400 */
+#define FMC_BCR3_WRAPMOD            FMC_BCR3_WRAPMOD_Msk                       /*!<Wrapped burst mode support */
+#define FMC_BCR3_WAITCFG_Pos        (11U)                                      
+#define FMC_BCR3_WAITCFG_Msk        (0x1U << FMC_BCR3_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCR3_WAITCFG            FMC_BCR3_WAITCFG_Msk                       /*!<Wait timing configuration  */
+#define FMC_BCR3_WREN_Pos           (12U)                                      
+#define FMC_BCR3_WREN_Msk           (0x1U << FMC_BCR3_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCR3_WREN               FMC_BCR3_WREN_Msk                          /*!<Write enable bit           */
+#define FMC_BCR3_WAITEN_Pos         (13U)                                      
+#define FMC_BCR3_WAITEN_Msk         (0x1U << FMC_BCR3_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCR3_WAITEN             FMC_BCR3_WAITEN_Msk                        /*!<Wait enable bit            */
+#define FMC_BCR3_EXTMOD_Pos         (14U)                                      
+#define FMC_BCR3_EXTMOD_Msk         (0x1U << FMC_BCR3_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCR3_EXTMOD             FMC_BCR3_EXTMOD_Msk                        /*!<Extended mode enable       */
+#define FMC_BCR3_ASYNCWAIT_Pos      (15U)                                      
+#define FMC_BCR3_ASYNCWAIT_Msk      (0x1U << FMC_BCR3_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCR3_ASYNCWAIT          FMC_BCR3_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
+#define FMC_BCR3_CPSIZE_Pos         (16U)                                      
+#define FMC_BCR3_CPSIZE_Msk         (0x7U << FMC_BCR3_CPSIZE_Pos)              /*!< 0x00070000 */
+#define FMC_BCR3_CPSIZE             FMC_BCR3_CPSIZE_Msk                        /*!<CRAM page size */
+#define FMC_BCR3_CPSIZE_0           (0x1U << FMC_BCR3_CPSIZE_Pos)              /*!< 0x00010000 */
+#define FMC_BCR3_CPSIZE_1           (0x2U << FMC_BCR3_CPSIZE_Pos)              /*!< 0x00020000 */
+#define FMC_BCR3_CPSIZE_2           (0x4U << FMC_BCR3_CPSIZE_Pos)              /*!< 0x00040000 */
+#define FMC_BCR3_CBURSTRW_Pos       (19U)                                      
+#define FMC_BCR3_CBURSTRW_Msk       (0x1U << FMC_BCR3_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCR3_CBURSTRW           FMC_BCR3_CBURSTRW_Msk                      /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BCR4 register  *******************/
+#define FMC_BCR4_MBKEN_Pos          (0U)                                       
+#define FMC_BCR4_MBKEN_Msk          (0x1U << FMC_BCR4_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCR4_MBKEN              FMC_BCR4_MBKEN_Msk                         /*!<Memory bank enable bit                 */
+#define FMC_BCR4_MUXEN_Pos          (1U)                                       
+#define FMC_BCR4_MUXEN_Msk          (0x1U << FMC_BCR4_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCR4_MUXEN              FMC_BCR4_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCR4_MTYP_Pos           (2U)                                       
+#define FMC_BCR4_MTYP_Msk           (0x3U << FMC_BCR4_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCR4_MTYP               FMC_BCR4_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCR4_MTYP_0             (0x1U << FMC_BCR4_MTYP_Pos)                /*!< 0x00000004 */
+#define FMC_BCR4_MTYP_1             (0x2U << FMC_BCR4_MTYP_Pos)                /*!< 0x00000008 */
+
+#define FMC_BCR4_MWID_Pos           (4U)                                       
+#define FMC_BCR4_MWID_Msk           (0x3U << FMC_BCR4_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCR4_MWID               FMC_BCR4_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0             (0x1U << FMC_BCR4_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_BCR4_MWID_1             (0x2U << FMC_BCR4_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_BCR4_FACCEN_Pos         (6U)                                       
+#define FMC_BCR4_FACCEN_Msk         (0x1U << FMC_BCR4_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCR4_FACCEN             FMC_BCR4_FACCEN_Msk                        /*!<Flash access enable        */
+#define FMC_BCR4_BURSTEN_Pos        (8U)                                       
+#define FMC_BCR4_BURSTEN_Msk        (0x1U << FMC_BCR4_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCR4_BURSTEN            FMC_BCR4_BURSTEN_Msk                       /*!<Burst enable bit           */
+#define FMC_BCR4_WAITPOL_Pos        (9U)                                       
+#define FMC_BCR4_WAITPOL_Msk        (0x1U << FMC_BCR4_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCR4_WAITPOL            FMC_BCR4_WAITPOL_Msk                       /*!<Wait signal polarity bit   */
+#define FMC_BCR4_WRAPMOD_Pos        (10U)                                      
+#define FMC_BCR4_WRAPMOD_Msk        (0x1U << FMC_BCR4_WRAPMOD_Pos)             /*!< 0x00000400 */
+#define FMC_BCR4_WRAPMOD            FMC_BCR4_WRAPMOD_Msk                       /*!<Wrapped burst mode support */
+#define FMC_BCR4_WAITCFG_Pos        (11U)                                      
+#define FMC_BCR4_WAITCFG_Msk        (0x1U << FMC_BCR4_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCR4_WAITCFG            FMC_BCR4_WAITCFG_Msk                       /*!<Wait timing configuration  */
+#define FMC_BCR4_WREN_Pos           (12U)                                      
+#define FMC_BCR4_WREN_Msk           (0x1U << FMC_BCR4_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCR4_WREN               FMC_BCR4_WREN_Msk                          /*!<Write enable bit           */
+#define FMC_BCR4_WAITEN_Pos         (13U)                                      
+#define FMC_BCR4_WAITEN_Msk         (0x1U << FMC_BCR4_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCR4_WAITEN             FMC_BCR4_WAITEN_Msk                        /*!<Wait enable bit            */
+#define FMC_BCR4_EXTMOD_Pos         (14U)                                      
+#define FMC_BCR4_EXTMOD_Msk         (0x1U << FMC_BCR4_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCR4_EXTMOD             FMC_BCR4_EXTMOD_Msk                        /*!<Extended mode enable       */
+#define FMC_BCR4_ASYNCWAIT_Pos      (15U)                                      
+#define FMC_BCR4_ASYNCWAIT_Msk      (0x1U << FMC_BCR4_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCR4_ASYNCWAIT          FMC_BCR4_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */
+#define FMC_BCR4_CPSIZE_Pos         (16U)                                      
+#define FMC_BCR4_CPSIZE_Msk         (0x7U << FMC_BCR4_CPSIZE_Pos)              /*!< 0x00070000 */
+#define FMC_BCR4_CPSIZE             FMC_BCR4_CPSIZE_Msk                        /*!<CRAM page size */
+#define FMC_BCR4_CPSIZE_0           (0x1U << FMC_BCR4_CPSIZE_Pos)              /*!< 0x00010000 */
+#define FMC_BCR4_CPSIZE_1           (0x2U << FMC_BCR4_CPSIZE_Pos)              /*!< 0x00020000 */
+#define FMC_BCR4_CPSIZE_2           (0x4U << FMC_BCR4_CPSIZE_Pos)              /*!< 0x00040000 */
+#define FMC_BCR4_CBURSTRW_Pos       (19U)                                      
+#define FMC_BCR4_CBURSTRW_Msk       (0x1U << FMC_BCR4_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCR4_CBURSTRW           FMC_BCR4_CBURSTRW_Msk                      /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTR1 register  ******************/
+#define FMC_BTR1_ADDSET_Pos         (0U)                                       
+#define FMC_BTR1_ADDSET_Msk         (0xFU << FMC_BTR1_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTR1_ADDSET             FMC_BTR1_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0           (0x1U << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BTR1_ADDSET_1           (0x2U << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BTR1_ADDSET_2           (0x4U << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BTR1_ADDSET_3           (0x8U << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BTR1_ADDHLD_Pos         (4U)                                       
+#define FMC_BTR1_ADDHLD_Msk         (0xFU << FMC_BTR1_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTR1_ADDHLD             FMC_BTR1_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define FMC_BTR1_ADDHLD_0           (0x1U << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BTR1_ADDHLD_1           (0x2U << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BTR1_ADDHLD_2           (0x4U << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BTR1_ADDHLD_3           (0x8U << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BTR1_DATAST_Pos         (8U)                                       
+#define FMC_BTR1_DATAST_Msk         (0xFFU << FMC_BTR1_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTR1_DATAST             FMC_BTR1_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0           (0x01U << FMC_BTR1_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BTR1_DATAST_1           (0x02U << FMC_BTR1_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BTR1_DATAST_2           (0x04U << FMC_BTR1_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BTR1_DATAST_3           (0x08U << FMC_BTR1_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BTR1_DATAST_4           (0x10U << FMC_BTR1_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BTR1_DATAST_5           (0x20U << FMC_BTR1_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BTR1_DATAST_6           (0x40U << FMC_BTR1_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BTR1_DATAST_7           (0x80U << FMC_BTR1_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BTR1_BUSTURN_Pos        (16U)                                      
+#define FMC_BTR1_BUSTURN_Msk        (0xFU << FMC_BTR1_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTR1_BUSTURN            FMC_BTR1_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0          (0x1U << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BTR1_BUSTURN_1          (0x2U << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BTR1_BUSTURN_2          (0x4U << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BTR1_BUSTURN_3          (0x8U << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BTR1_CLKDIV_Pos         (20U)                                      
+#define FMC_BTR1_CLKDIV_Msk         (0xFU << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTR1_CLKDIV             FMC_BTR1_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0           (0x1U << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00100000 */
+#define FMC_BTR1_CLKDIV_1           (0x2U << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00200000 */
+#define FMC_BTR1_CLKDIV_2           (0x4U << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00400000 */
+#define FMC_BTR1_CLKDIV_3           (0x8U << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00800000 */
+
+#define FMC_BTR1_DATLAT_Pos         (24U)                                      
+#define FMC_BTR1_DATLAT_Msk         (0xFU << FMC_BTR1_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTR1_DATLAT             FMC_BTR1_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0           (0x1U << FMC_BTR1_DATLAT_Pos)              /*!< 0x01000000 */
+#define FMC_BTR1_DATLAT_1           (0x2U << FMC_BTR1_DATLAT_Pos)              /*!< 0x02000000 */
+#define FMC_BTR1_DATLAT_2           (0x4U << FMC_BTR1_DATLAT_Pos)              /*!< 0x04000000 */
+#define FMC_BTR1_DATLAT_3           (0x8U << FMC_BTR1_DATLAT_Pos)              /*!< 0x08000000 */
+
+#define FMC_BTR1_ACCMOD_Pos         (28U)                                      
+#define FMC_BTR1_ACCMOD_Msk         (0x3U << FMC_BTR1_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTR1_ACCMOD             FMC_BTR1_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0           (0x1U << FMC_BTR1_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BTR1_ACCMOD_1           (0x2U << FMC_BTR1_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BTR2 register  *******************/
+#define FMC_BTR2_ADDSET_Pos         (0U)                                       
+#define FMC_BTR2_ADDSET_Msk         (0xFU << FMC_BTR2_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTR2_ADDSET             FMC_BTR2_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0           (0x1U << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BTR2_ADDSET_1           (0x2U << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BTR2_ADDSET_2           (0x4U << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BTR2_ADDSET_3           (0x8U << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BTR2_ADDHLD_Pos         (4U)                                       
+#define FMC_BTR2_ADDHLD_Msk         (0xFU << FMC_BTR2_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTR2_ADDHLD             FMC_BTR2_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0           (0x1U << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BTR2_ADDHLD_1           (0x2U << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BTR2_ADDHLD_2           (0x4U << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BTR2_ADDHLD_3           (0x8U << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BTR2_DATAST_Pos         (8U)                                       
+#define FMC_BTR2_DATAST_Msk         (0xFFU << FMC_BTR2_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTR2_DATAST             FMC_BTR2_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0           (0x01U << FMC_BTR2_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BTR2_DATAST_1           (0x02U << FMC_BTR2_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BTR2_DATAST_2           (0x04U << FMC_BTR2_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BTR2_DATAST_3           (0x08U << FMC_BTR2_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BTR2_DATAST_4           (0x10U << FMC_BTR2_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BTR2_DATAST_5           (0x20U << FMC_BTR2_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BTR2_DATAST_6           (0x40U << FMC_BTR2_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BTR2_DATAST_7           (0x80U << FMC_BTR2_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BTR2_BUSTURN_Pos        (16U)                                      
+#define FMC_BTR2_BUSTURN_Msk        (0xFU << FMC_BTR2_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTR2_BUSTURN            FMC_BTR2_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0          (0x1U << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BTR2_BUSTURN_1          (0x2U << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BTR2_BUSTURN_2          (0x4U << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BTR2_BUSTURN_3          (0x8U << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BTR2_CLKDIV_Pos         (20U)                                      
+#define FMC_BTR2_CLKDIV_Msk         (0xFU << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTR2_CLKDIV             FMC_BTR2_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0           (0x1U << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00100000 */
+#define FMC_BTR2_CLKDIV_1           (0x2U << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00200000 */
+#define FMC_BTR2_CLKDIV_2           (0x4U << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00400000 */
+#define FMC_BTR2_CLKDIV_3           (0x8U << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00800000 */
+
+#define FMC_BTR2_DATLAT_Pos         (24U)                                      
+#define FMC_BTR2_DATLAT_Msk         (0xFU << FMC_BTR2_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTR2_DATLAT             FMC_BTR2_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0           (0x1U << FMC_BTR2_DATLAT_Pos)              /*!< 0x01000000 */
+#define FMC_BTR2_DATLAT_1           (0x2U << FMC_BTR2_DATLAT_Pos)              /*!< 0x02000000 */
+#define FMC_BTR2_DATLAT_2           (0x4U << FMC_BTR2_DATLAT_Pos)              /*!< 0x04000000 */
+#define FMC_BTR2_DATLAT_3           (0x8U << FMC_BTR2_DATLAT_Pos)              /*!< 0x08000000 */
+
+#define FMC_BTR2_ACCMOD_Pos         (28U)                                      
+#define FMC_BTR2_ACCMOD_Msk         (0x3U << FMC_BTR2_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTR2_ACCMOD             FMC_BTR2_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0           (0x1U << FMC_BTR2_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BTR2_ACCMOD_1           (0x2U << FMC_BTR2_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/*******************  Bit definition for FMC_BTR3 register  *******************/
+#define FMC_BTR3_ADDSET_Pos         (0U)                                       
+#define FMC_BTR3_ADDSET_Msk         (0xFU << FMC_BTR3_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTR3_ADDSET             FMC_BTR3_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0           (0x1U << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BTR3_ADDSET_1           (0x2U << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BTR3_ADDSET_2           (0x4U << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BTR3_ADDSET_3           (0x8U << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BTR3_ADDHLD_Pos         (4U)                                       
+#define FMC_BTR3_ADDHLD_Msk         (0xFU << FMC_BTR3_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTR3_ADDHLD             FMC_BTR3_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0           (0x1U << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BTR3_ADDHLD_1           (0x2U << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BTR3_ADDHLD_2           (0x4U << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BTR3_ADDHLD_3           (0x8U << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BTR3_DATAST_Pos         (8U)                                       
+#define FMC_BTR3_DATAST_Msk         (0xFFU << FMC_BTR3_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTR3_DATAST             FMC_BTR3_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0           (0x01U << FMC_BTR3_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BTR3_DATAST_1           (0x02U << FMC_BTR3_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BTR3_DATAST_2           (0x04U << FMC_BTR3_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BTR3_DATAST_3           (0x08U << FMC_BTR3_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BTR3_DATAST_4           (0x10U << FMC_BTR3_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BTR3_DATAST_5           (0x20U << FMC_BTR3_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BTR3_DATAST_6           (0x40U << FMC_BTR3_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BTR3_DATAST_7           (0x80U << FMC_BTR3_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BTR3_BUSTURN_Pos        (16U)                                      
+#define FMC_BTR3_BUSTURN_Msk        (0xFU << FMC_BTR3_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTR3_BUSTURN            FMC_BTR3_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0          (0x1U << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BTR3_BUSTURN_1          (0x2U << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BTR3_BUSTURN_2          (0x4U << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BTR3_BUSTURN_3          (0x8U << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BTR3_CLKDIV_Pos         (20U)                                      
+#define FMC_BTR3_CLKDIV_Msk         (0xFU << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTR3_CLKDIV             FMC_BTR3_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0           (0x1U << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00100000 */
+#define FMC_BTR3_CLKDIV_1           (0x2U << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00200000 */
+#define FMC_BTR3_CLKDIV_2           (0x4U << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00400000 */
+#define FMC_BTR3_CLKDIV_3           (0x8U << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00800000 */
+
+#define FMC_BTR3_DATLAT_Pos         (24U)                                      
+#define FMC_BTR3_DATLAT_Msk         (0xFU << FMC_BTR3_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTR3_DATLAT             FMC_BTR3_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0           (0x1U << FMC_BTR3_DATLAT_Pos)              /*!< 0x01000000 */
+#define FMC_BTR3_DATLAT_1           (0x2U << FMC_BTR3_DATLAT_Pos)              /*!< 0x02000000 */
+#define FMC_BTR3_DATLAT_2           (0x4U << FMC_BTR3_DATLAT_Pos)              /*!< 0x04000000 */
+#define FMC_BTR3_DATLAT_3           (0x8U << FMC_BTR3_DATLAT_Pos)              /*!< 0x08000000 */
+
+#define FMC_BTR3_ACCMOD_Pos         (28U)                                      
+#define FMC_BTR3_ACCMOD_Msk         (0x3U << FMC_BTR3_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTR3_ACCMOD             FMC_BTR3_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0           (0x1U << FMC_BTR3_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BTR3_ACCMOD_1           (0x2U << FMC_BTR3_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BTR4 register  *******************/
+#define FMC_BTR4_ADDSET_Pos         (0U)                                       
+#define FMC_BTR4_ADDSET_Msk         (0xFU << FMC_BTR4_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTR4_ADDSET             FMC_BTR4_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0           (0x1U << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BTR4_ADDSET_1           (0x2U << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BTR4_ADDSET_2           (0x4U << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BTR4_ADDSET_3           (0x8U << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BTR4_ADDHLD_Pos         (4U)                                       
+#define FMC_BTR4_ADDHLD_Msk         (0xFU << FMC_BTR4_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTR4_ADDHLD             FMC_BTR4_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0           (0x1U << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BTR4_ADDHLD_1           (0x2U << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BTR4_ADDHLD_2           (0x4U << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BTR4_ADDHLD_3           (0x8U << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BTR4_DATAST_Pos         (8U)                                       
+#define FMC_BTR4_DATAST_Msk         (0xFFU << FMC_BTR4_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTR4_DATAST             FMC_BTR4_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0           (0x01U << FMC_BTR4_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BTR4_DATAST_1           (0x02U << FMC_BTR4_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BTR4_DATAST_2           (0x04U << FMC_BTR4_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BTR4_DATAST_3           (0x08U << FMC_BTR4_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BTR4_DATAST_4           (0x10U << FMC_BTR4_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BTR4_DATAST_5           (0x20U << FMC_BTR4_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BTR4_DATAST_6           (0x40U << FMC_BTR4_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BTR4_DATAST_7           (0x80U << FMC_BTR4_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BTR4_BUSTURN_Pos        (16U)                                      
+#define FMC_BTR4_BUSTURN_Msk        (0xFU << FMC_BTR4_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTR4_BUSTURN            FMC_BTR4_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0          (0x1U << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BTR4_BUSTURN_1          (0x2U << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BTR4_BUSTURN_2          (0x4U << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BTR4_BUSTURN_3          (0x8U << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BTR4_CLKDIV_Pos         (20U)                                      
+#define FMC_BTR4_CLKDIV_Msk         (0xFU << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTR4_CLKDIV             FMC_BTR4_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0           (0x1U << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00100000 */
+#define FMC_BTR4_CLKDIV_1           (0x2U << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00200000 */
+#define FMC_BTR4_CLKDIV_2           (0x4U << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00400000 */
+#define FMC_BTR4_CLKDIV_3           (0x8U << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00800000 */
+
+#define FMC_BTR4_DATLAT_Pos         (24U)                                      
+#define FMC_BTR4_DATLAT_Msk         (0xFU << FMC_BTR4_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTR4_DATLAT             FMC_BTR4_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0           (0x1U << FMC_BTR4_DATLAT_Pos)              /*!< 0x01000000 */
+#define FMC_BTR4_DATLAT_1           (0x2U << FMC_BTR4_DATLAT_Pos)              /*!< 0x02000000 */
+#define FMC_BTR4_DATLAT_2           (0x4U << FMC_BTR4_DATLAT_Pos)              /*!< 0x04000000 */
+#define FMC_BTR4_DATLAT_3           (0x8U << FMC_BTR4_DATLAT_Pos)              /*!< 0x08000000 */
+
+#define FMC_BTR4_ACCMOD_Pos         (28U)                                      
+#define FMC_BTR4_ACCMOD_Msk         (0x3U << FMC_BTR4_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTR4_ACCMOD             FMC_BTR4_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0           (0x1U << FMC_BTR4_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BTR4_ACCMOD_1           (0x2U << FMC_BTR4_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTR1 register  ******************/
+#define FMC_BWTR1_ADDSET_Pos        (0U)                                       
+#define FMC_BWTR1_ADDSET_Msk        (0xFU << FMC_BWTR1_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTR1_ADDSET            FMC_BWTR1_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0          (0x1U << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000001 */
+#define FMC_BWTR1_ADDSET_1          (0x2U << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000002 */
+#define FMC_BWTR1_ADDSET_2          (0x4U << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000004 */
+#define FMC_BWTR1_ADDSET_3          (0x8U << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000008 */
+
+#define FMC_BWTR1_ADDHLD_Pos        (4U)                                       
+#define FMC_BWTR1_ADDHLD_Msk        (0xFU << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTR1_ADDHLD            FMC_BWTR1_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0          (0x1U << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000010 */
+#define FMC_BWTR1_ADDHLD_1          (0x2U << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000020 */
+#define FMC_BWTR1_ADDHLD_2          (0x4U << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000040 */
+#define FMC_BWTR1_ADDHLD_3          (0x8U << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000080 */
+
+#define FMC_BWTR1_DATAST_Pos        (8U)                                       
+#define FMC_BWTR1_DATAST_Msk        (0xFFU << FMC_BWTR1_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTR1_DATAST            FMC_BWTR1_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0          (0x01U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000100 */
+#define FMC_BWTR1_DATAST_1          (0x02U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000200 */
+#define FMC_BWTR1_DATAST_2          (0x04U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000400 */
+#define FMC_BWTR1_DATAST_3          (0x08U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000800 */
+#define FMC_BWTR1_DATAST_4          (0x10U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00001000 */
+#define FMC_BWTR1_DATAST_5          (0x20U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00002000 */
+#define FMC_BWTR1_DATAST_6          (0x40U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00004000 */
+#define FMC_BWTR1_DATAST_7          (0x80U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00008000 */
+
+#define FMC_BWTR1_BUSTURN_Pos       (16U)                                      
+#define FMC_BWTR1_BUSTURN_Msk       (0xFU << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x000F0000 */
+#define FMC_BWTR1_BUSTURN           FMC_BWTR1_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR1_BUSTURN_0         (0x1U << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00010000 */
+#define FMC_BWTR1_BUSTURN_1         (0x2U << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00020000 */
+#define FMC_BWTR1_BUSTURN_2         (0x4U << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00040000 */
+#define FMC_BWTR1_BUSTURN_3         (0x8U << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00080000 */
+
+#define FMC_BWTR1_ACCMOD_Pos        (28U)                                      
+#define FMC_BWTR1_ACCMOD_Msk        (0x3U << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTR1_ACCMOD            FMC_BWTR1_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0          (0x1U << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x10000000 */
+#define FMC_BWTR1_ACCMOD_1          (0x2U << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTR2 register  ******************/
+#define FMC_BWTR2_ADDSET_Pos        (0U)                                       
+#define FMC_BWTR2_ADDSET_Msk        (0xFU << FMC_BWTR2_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTR2_ADDSET            FMC_BWTR2_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0          (0x1U << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000001 */
+#define FMC_BWTR2_ADDSET_1          (0x2U << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000002 */
+#define FMC_BWTR2_ADDSET_2          (0x4U << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000004 */
+#define FMC_BWTR2_ADDSET_3          (0x8U << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000008 */
+
+#define FMC_BWTR2_ADDHLD_Pos        (4U)                                       
+#define FMC_BWTR2_ADDHLD_Msk        (0xFU << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTR2_ADDHLD            FMC_BWTR2_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0          (0x1U << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000010 */
+#define FMC_BWTR2_ADDHLD_1          (0x2U << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000020 */
+#define FMC_BWTR2_ADDHLD_2          (0x4U << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000040 */
+#define FMC_BWTR2_ADDHLD_3          (0x8U << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000080 */
+
+#define FMC_BWTR2_DATAST_Pos        (8U)                                       
+#define FMC_BWTR2_DATAST_Msk        (0xFFU << FMC_BWTR2_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTR2_DATAST            FMC_BWTR2_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0          (0x01U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000100 */
+#define FMC_BWTR2_DATAST_1          (0x02U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000200 */
+#define FMC_BWTR2_DATAST_2          (0x04U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000400 */
+#define FMC_BWTR2_DATAST_3          (0x08U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000800 */
+#define FMC_BWTR2_DATAST_4          (0x10U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00001000 */
+#define FMC_BWTR2_DATAST_5          (0x20U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00002000 */
+#define FMC_BWTR2_DATAST_6          (0x40U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00004000 */
+#define FMC_BWTR2_DATAST_7          (0x80U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00008000 */
+
+#define FMC_BWTR2_BUSTURN_Pos       (16U)                                      
+#define FMC_BWTR2_BUSTURN_Msk       (0xFU << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x000F0000 */
+#define FMC_BWTR2_BUSTURN           FMC_BWTR2_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR2_BUSTURN_0         (0x1U << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00010000 */
+#define FMC_BWTR2_BUSTURN_1         (0x2U << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00020000 */
+#define FMC_BWTR2_BUSTURN_2         (0x4U << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00040000 */
+#define FMC_BWTR2_BUSTURN_3         (0x8U << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00080000 */
+
+#define FMC_BWTR2_ACCMOD_Pos        (28U)                                      
+#define FMC_BWTR2_ACCMOD_Msk        (0x3U << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTR2_ACCMOD            FMC_BWTR2_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0          (0x1U << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x10000000 */
+#define FMC_BWTR2_ACCMOD_1          (0x2U << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTR3 register  ******************/
+#define FMC_BWTR3_ADDSET_Pos        (0U)                                       
+#define FMC_BWTR3_ADDSET_Msk        (0xFU << FMC_BWTR3_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTR3_ADDSET            FMC_BWTR3_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0          (0x1U << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000001 */
+#define FMC_BWTR3_ADDSET_1          (0x2U << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000002 */
+#define FMC_BWTR3_ADDSET_2          (0x4U << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000004 */
+#define FMC_BWTR3_ADDSET_3          (0x8U << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000008 */
+
+#define FMC_BWTR3_ADDHLD_Pos        (4U)                                       
+#define FMC_BWTR3_ADDHLD_Msk        (0xFU << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTR3_ADDHLD            FMC_BWTR3_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0          (0x1U << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000010 */
+#define FMC_BWTR3_ADDHLD_1          (0x2U << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000020 */
+#define FMC_BWTR3_ADDHLD_2          (0x4U << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000040 */
+#define FMC_BWTR3_ADDHLD_3          (0x8U << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000080 */
+
+#define FMC_BWTR3_DATAST_Pos        (8U)                                       
+#define FMC_BWTR3_DATAST_Msk        (0xFFU << FMC_BWTR3_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTR3_DATAST            FMC_BWTR3_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0          (0x01U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000100 */
+#define FMC_BWTR3_DATAST_1          (0x02U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000200 */
+#define FMC_BWTR3_DATAST_2          (0x04U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000400 */
+#define FMC_BWTR3_DATAST_3          (0x08U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000800 */
+#define FMC_BWTR3_DATAST_4          (0x10U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00001000 */
+#define FMC_BWTR3_DATAST_5          (0x20U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00002000 */
+#define FMC_BWTR3_DATAST_6          (0x40U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00004000 */
+#define FMC_BWTR3_DATAST_7          (0x80U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00008000 */
+
+#define FMC_BWTR3_BUSTURN_Pos       (16U)                                      
+#define FMC_BWTR3_BUSTURN_Msk       (0xFU << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x000F0000 */
+#define FMC_BWTR3_BUSTURN           FMC_BWTR3_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR3_BUSTURN_0         (0x1U << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00010000 */
+#define FMC_BWTR3_BUSTURN_1         (0x2U << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00020000 */
+#define FMC_BWTR3_BUSTURN_2         (0x4U << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00040000 */
+#define FMC_BWTR3_BUSTURN_3         (0x8U << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00080000 */
+
+#define FMC_BWTR3_ACCMOD_Pos        (28U)                                      
+#define FMC_BWTR3_ACCMOD_Msk        (0x3U << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTR3_ACCMOD            FMC_BWTR3_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0          (0x1U << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x10000000 */
+#define FMC_BWTR3_ACCMOD_1          (0x2U << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTR4 register  ******************/
+#define FMC_BWTR4_ADDSET_Pos        (0U)                                       
+#define FMC_BWTR4_ADDSET_Msk        (0xFU << FMC_BWTR4_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTR4_ADDSET            FMC_BWTR4_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0          (0x1U << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000001 */
+#define FMC_BWTR4_ADDSET_1          (0x2U << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000002 */
+#define FMC_BWTR4_ADDSET_2          (0x4U << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000004 */
+#define FMC_BWTR4_ADDSET_3          (0x8U << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000008 */
+
+#define FMC_BWTR4_ADDHLD_Pos        (4U)                                       
+#define FMC_BWTR4_ADDHLD_Msk        (0xFU << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTR4_ADDHLD            FMC_BWTR4_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0          (0x1U << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000010 */
+#define FMC_BWTR4_ADDHLD_1          (0x2U << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000020 */
+#define FMC_BWTR4_ADDHLD_2          (0x4U << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000040 */
+#define FMC_BWTR4_ADDHLD_3          (0x8U << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000080 */
+
+#define FMC_BWTR4_DATAST_Pos        (8U)                                       
+#define FMC_BWTR4_DATAST_Msk        (0xFFU << FMC_BWTR4_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTR4_DATAST            FMC_BWTR4_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0          (0x01U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000100 */
+#define FMC_BWTR4_DATAST_1          (0x02U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000200 */
+#define FMC_BWTR4_DATAST_2          (0x04U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000400 */
+#define FMC_BWTR4_DATAST_3          (0x08U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000800 */
+#define FMC_BWTR4_DATAST_4          (0x10U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00001000 */
+#define FMC_BWTR4_DATAST_5          (0x20U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00002000 */
+#define FMC_BWTR4_DATAST_6          (0x40U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00004000 */
+#define FMC_BWTR4_DATAST_7          (0x80U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00008000 */
+
+#define FMC_BWTR4_BUSTURN_Pos       (16U)                                      
+#define FMC_BWTR4_BUSTURN_Msk       (0xFU << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x000F0000 */
+#define FMC_BWTR4_BUSTURN           FMC_BWTR4_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FMC_BWTR4_BUSTURN_0         (0x1U << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00010000 */
+#define FMC_BWTR4_BUSTURN_1         (0x2U << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00020000 */
+#define FMC_BWTR4_BUSTURN_2         (0x4U << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00040000 */
+#define FMC_BWTR4_BUSTURN_3         (0x8U << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00080000 */
+
+#define FMC_BWTR4_ACCMOD_Pos        (28U)                                      
+#define FMC_BWTR4_ACCMOD_Msk        (0x3U << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTR4_ACCMOD            FMC_BWTR4_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0          (0x1U << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x10000000 */
+#define FMC_BWTR4_ACCMOD_1          (0x2U << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_PCR2 register  *******************/
+
+#define FMC_PCR2_PWAITEN_Pos        (1U)                                       
+#define FMC_PCR2_PWAITEN_Msk        (0x1U << FMC_PCR2_PWAITEN_Pos)             /*!< 0x00000002 */
+#define FMC_PCR2_PWAITEN            FMC_PCR2_PWAITEN_Msk                       /*!<Wait feature enable bit                   */
+#define FMC_PCR2_PBKEN_Pos          (2U)                                       
+#define FMC_PCR2_PBKEN_Msk          (0x1U << FMC_PCR2_PBKEN_Pos)               /*!< 0x00000004 */
+#define FMC_PCR2_PBKEN              FMC_PCR2_PBKEN_Msk                         /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR2_PTYP_Pos           (3U)                                       
+#define FMC_PCR2_PTYP_Msk           (0x1U << FMC_PCR2_PTYP_Pos)                /*!< 0x00000008 */
+#define FMC_PCR2_PTYP               FMC_PCR2_PTYP_Msk                          /*!<Memory type                               */
+
+#define FMC_PCR2_PWID_Pos           (4U)                                       
+#define FMC_PCR2_PWID_Msk           (0x3U << FMC_PCR2_PWID_Pos)                /*!< 0x00000030 */
+#define FMC_PCR2_PWID               FMC_PCR2_PWID_Msk                          /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR2_PWID_0             (0x1U << FMC_PCR2_PWID_Pos)                /*!< 0x00000010 */
+#define FMC_PCR2_PWID_1             (0x2U << FMC_PCR2_PWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_PCR2_ECCEN_Pos          (6U)                                       
+#define FMC_PCR2_ECCEN_Msk          (0x1U << FMC_PCR2_ECCEN_Pos)               /*!< 0x00000040 */
+#define FMC_PCR2_ECCEN              FMC_PCR2_ECCEN_Msk                         /*!<ECC computation logic enable bit          */
+
+#define FMC_PCR2_TCLR_Pos           (9U)                                       
+#define FMC_PCR2_TCLR_Msk           (0xFU << FMC_PCR2_TCLR_Pos)                /*!< 0x00001E00 */
+#define FMC_PCR2_TCLR               FMC_PCR2_TCLR_Msk                          /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCR2_TCLR_0             (0x1U << FMC_PCR2_TCLR_Pos)                /*!< 0x00000200 */
+#define FMC_PCR2_TCLR_1             (0x2U << FMC_PCR2_TCLR_Pos)                /*!< 0x00000400 */
+#define FMC_PCR2_TCLR_2             (0x4U << FMC_PCR2_TCLR_Pos)                /*!< 0x00000800 */
+#define FMC_PCR2_TCLR_3             (0x8U << FMC_PCR2_TCLR_Pos)                /*!< 0x00001000 */
+
+#define FMC_PCR2_TAR_Pos            (13U)                                      
+#define FMC_PCR2_TAR_Msk            (0xFU << FMC_PCR2_TAR_Pos)                 /*!< 0x0001E000 */
+#define FMC_PCR2_TAR                FMC_PCR2_TAR_Msk                           /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCR2_TAR_0              (0x1U << FMC_PCR2_TAR_Pos)                 /*!< 0x00002000 */
+#define FMC_PCR2_TAR_1              (0x2U << FMC_PCR2_TAR_Pos)                 /*!< 0x00004000 */
+#define FMC_PCR2_TAR_2              (0x4U << FMC_PCR2_TAR_Pos)                 /*!< 0x00008000 */
+#define FMC_PCR2_TAR_3              (0x8U << FMC_PCR2_TAR_Pos)                 /*!< 0x00010000 */
+
+#define FMC_PCR2_ECCPS_Pos          (17U)                                      
+#define FMC_PCR2_ECCPS_Msk          (0x7U << FMC_PCR2_ECCPS_Pos)               /*!< 0x000E0000 */
+#define FMC_PCR2_ECCPS              FMC_PCR2_ECCPS_Msk                         /*!<ECCPS[1:0] bits (ECC page size)           */
+#define FMC_PCR2_ECCPS_0            (0x1U << FMC_PCR2_ECCPS_Pos)               /*!< 0x00020000 */
+#define FMC_PCR2_ECCPS_1            (0x2U << FMC_PCR2_ECCPS_Pos)               /*!< 0x00040000 */
+#define FMC_PCR2_ECCPS_2            (0x4U << FMC_PCR2_ECCPS_Pos)               /*!< 0x00080000 */
+
+/******************  Bit definition for FMC_PCR3 register  *******************/
+#define FMC_PCR3_PWAITEN_Pos        (1U)                                       
+#define FMC_PCR3_PWAITEN_Msk        (0x1U << FMC_PCR3_PWAITEN_Pos)             /*!< 0x00000002 */
+#define FMC_PCR3_PWAITEN            FMC_PCR3_PWAITEN_Msk                       /*!<Wait feature enable bit                   */
+#define FMC_PCR3_PBKEN_Pos          (2U)                                       
+#define FMC_PCR3_PBKEN_Msk          (0x1U << FMC_PCR3_PBKEN_Pos)               /*!< 0x00000004 */
+#define FMC_PCR3_PBKEN              FMC_PCR3_PBKEN_Msk                         /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR3_PTYP_Pos           (3U)                                       
+#define FMC_PCR3_PTYP_Msk           (0x1U << FMC_PCR3_PTYP_Pos)                /*!< 0x00000008 */
+#define FMC_PCR3_PTYP               FMC_PCR3_PTYP_Msk                          /*!<Memory type                               */
+
+#define FMC_PCR3_PWID_Pos           (4U)                                       
+#define FMC_PCR3_PWID_Msk           (0x3U << FMC_PCR3_PWID_Pos)                /*!< 0x00000030 */
+#define FMC_PCR3_PWID               FMC_PCR3_PWID_Msk                          /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR3_PWID_0             (0x1U << FMC_PCR3_PWID_Pos)                /*!< 0x00000010 */
+#define FMC_PCR3_PWID_1             (0x2U << FMC_PCR3_PWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_PCR3_ECCEN_Pos          (6U)                                       
+#define FMC_PCR3_ECCEN_Msk          (0x1U << FMC_PCR3_ECCEN_Pos)               /*!< 0x00000040 */
+#define FMC_PCR3_ECCEN              FMC_PCR3_ECCEN_Msk                         /*!<ECC computation logic enable bit          */
+
+#define FMC_PCR3_TCLR_Pos           (9U)                                       
+#define FMC_PCR3_TCLR_Msk           (0xFU << FMC_PCR3_TCLR_Pos)                /*!< 0x00001E00 */
+#define FMC_PCR3_TCLR               FMC_PCR3_TCLR_Msk                          /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCR3_TCLR_0             (0x1U << FMC_PCR3_TCLR_Pos)                /*!< 0x00000200 */
+#define FMC_PCR3_TCLR_1             (0x2U << FMC_PCR3_TCLR_Pos)                /*!< 0x00000400 */
+#define FMC_PCR3_TCLR_2             (0x4U << FMC_PCR3_TCLR_Pos)                /*!< 0x00000800 */
+#define FMC_PCR3_TCLR_3             (0x8U << FMC_PCR3_TCLR_Pos)                /*!< 0x00001000 */
+
+#define FMC_PCR3_TAR_Pos            (13U)                                      
+#define FMC_PCR3_TAR_Msk            (0xFU << FMC_PCR3_TAR_Pos)                 /*!< 0x0001E000 */
+#define FMC_PCR3_TAR                FMC_PCR3_TAR_Msk                           /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCR3_TAR_0              (0x1U << FMC_PCR3_TAR_Pos)                 /*!< 0x00002000 */
+#define FMC_PCR3_TAR_1              (0x2U << FMC_PCR3_TAR_Pos)                 /*!< 0x00004000 */
+#define FMC_PCR3_TAR_2              (0x4U << FMC_PCR3_TAR_Pos)                 /*!< 0x00008000 */
+#define FMC_PCR3_TAR_3              (0x8U << FMC_PCR3_TAR_Pos)                 /*!< 0x00010000 */
+
+#define FMC_PCR3_ECCPS_Pos          (17U)                                      
+#define FMC_PCR3_ECCPS_Msk          (0x7U << FMC_PCR3_ECCPS_Pos)               /*!< 0x000E0000 */
+#define FMC_PCR3_ECCPS              FMC_PCR3_ECCPS_Msk                         /*!<ECCPS[2:0] bits (ECC page size)           */
+#define FMC_PCR3_ECCPS_0            (0x1U << FMC_PCR3_ECCPS_Pos)               /*!< 0x00020000 */
+#define FMC_PCR3_ECCPS_1            (0x2U << FMC_PCR3_ECCPS_Pos)               /*!< 0x00040000 */
+#define FMC_PCR3_ECCPS_2            (0x4U << FMC_PCR3_ECCPS_Pos)               /*!< 0x00080000 */
+
+/******************  Bit definition for FMC_PCR4 register  *******************/
+#define FMC_PCR4_PWAITEN_Pos        (1U)                                       
+#define FMC_PCR4_PWAITEN_Msk        (0x1U << FMC_PCR4_PWAITEN_Pos)             /*!< 0x00000002 */
+#define FMC_PCR4_PWAITEN            FMC_PCR4_PWAITEN_Msk                       /*!<Wait feature enable bit                   */
+#define FMC_PCR4_PBKEN_Pos          (2U)                                       
+#define FMC_PCR4_PBKEN_Msk          (0x1U << FMC_PCR4_PBKEN_Pos)               /*!< 0x00000004 */
+#define FMC_PCR4_PBKEN              FMC_PCR4_PBKEN_Msk                         /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR4_PTYP_Pos           (3U)                                       
+#define FMC_PCR4_PTYP_Msk           (0x1U << FMC_PCR4_PTYP_Pos)                /*!< 0x00000008 */
+#define FMC_PCR4_PTYP               FMC_PCR4_PTYP_Msk                          /*!<Memory type                               */
+
+#define FMC_PCR4_PWID_Pos           (4U)                                       
+#define FMC_PCR4_PWID_Msk           (0x3U << FMC_PCR4_PWID_Pos)                /*!< 0x00000030 */
+#define FMC_PCR4_PWID               FMC_PCR4_PWID_Msk                          /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR4_PWID_0             (0x1U << FMC_PCR4_PWID_Pos)                /*!< 0x00000010 */
+#define FMC_PCR4_PWID_1             (0x2U << FMC_PCR4_PWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_PCR4_ECCEN_Pos          (6U)                                       
+#define FMC_PCR4_ECCEN_Msk          (0x1U << FMC_PCR4_ECCEN_Pos)               /*!< 0x00000040 */
+#define FMC_PCR4_ECCEN              FMC_PCR4_ECCEN_Msk                         /*!<ECC computation logic enable bit          */
+
+#define FMC_PCR4_TCLR_Pos           (9U)                                       
+#define FMC_PCR4_TCLR_Msk           (0xFU << FMC_PCR4_TCLR_Pos)                /*!< 0x00001E00 */
+#define FMC_PCR4_TCLR               FMC_PCR4_TCLR_Msk                          /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCR4_TCLR_0             (0x1U << FMC_PCR4_TCLR_Pos)                /*!< 0x00000200 */
+#define FMC_PCR4_TCLR_1             (0x2U << FMC_PCR4_TCLR_Pos)                /*!< 0x00000400 */
+#define FMC_PCR4_TCLR_2             (0x4U << FMC_PCR4_TCLR_Pos)                /*!< 0x00000800 */
+#define FMC_PCR4_TCLR_3             (0x8U << FMC_PCR4_TCLR_Pos)                /*!< 0x00001000 */
+
+#define FMC_PCR4_TAR_Pos            (13U)                                      
+#define FMC_PCR4_TAR_Msk            (0xFU << FMC_PCR4_TAR_Pos)                 /*!< 0x0001E000 */
+#define FMC_PCR4_TAR                FMC_PCR4_TAR_Msk                           /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCR4_TAR_0              (0x1U << FMC_PCR4_TAR_Pos)                 /*!< 0x00002000 */
+#define FMC_PCR4_TAR_1              (0x2U << FMC_PCR4_TAR_Pos)                 /*!< 0x00004000 */
+#define FMC_PCR4_TAR_2              (0x4U << FMC_PCR4_TAR_Pos)                 /*!< 0x00008000 */
+#define FMC_PCR4_TAR_3              (0x8U << FMC_PCR4_TAR_Pos)                 /*!< 0x00010000 */
+
+#define FMC_PCR4_ECCPS_Pos          (17U)                                      
+#define FMC_PCR4_ECCPS_Msk          (0x7U << FMC_PCR4_ECCPS_Pos)               /*!< 0x000E0000 */
+#define FMC_PCR4_ECCPS              FMC_PCR4_ECCPS_Msk                         /*!<ECCPS[2:0] bits (ECC page size)           */
+#define FMC_PCR4_ECCPS_0            (0x1U << FMC_PCR4_ECCPS_Pos)               /*!< 0x00020000 */
+#define FMC_PCR4_ECCPS_1            (0x2U << FMC_PCR4_ECCPS_Pos)               /*!< 0x00040000 */
+#define FMC_PCR4_ECCPS_2            (0x4U << FMC_PCR4_ECCPS_Pos)               /*!< 0x00080000 */
+
+/*******************  Bit definition for FMC_SR2 register  *******************/
+#define FMC_SR2_IRS_Pos             (0U)                                       
+#define FMC_SR2_IRS_Msk             (0x1U << FMC_SR2_IRS_Pos)                  /*!< 0x00000001 */
+#define FMC_SR2_IRS                 FMC_SR2_IRS_Msk                            /*!<Interrupt Rising Edge status                */
+#define FMC_SR2_ILS_Pos             (1U)                                       
+#define FMC_SR2_ILS_Msk             (0x1U << FMC_SR2_ILS_Pos)                  /*!< 0x00000002 */
+#define FMC_SR2_ILS                 FMC_SR2_ILS_Msk                            /*!<Interrupt Level status                      */
+#define FMC_SR2_IFS_Pos             (2U)                                       
+#define FMC_SR2_IFS_Msk             (0x1U << FMC_SR2_IFS_Pos)                  /*!< 0x00000004 */
+#define FMC_SR2_IFS                 FMC_SR2_IFS_Msk                            /*!<Interrupt Falling Edge status               */
+#define FMC_SR2_IREN_Pos            (3U)                                       
+#define FMC_SR2_IREN_Msk            (0x1U << FMC_SR2_IREN_Pos)                 /*!< 0x00000008 */
+#define FMC_SR2_IREN                FMC_SR2_IREN_Msk                           /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SR2_ILEN_Pos            (4U)                                       
+#define FMC_SR2_ILEN_Msk            (0x1U << FMC_SR2_ILEN_Pos)                 /*!< 0x00000010 */
+#define FMC_SR2_ILEN                FMC_SR2_ILEN_Msk                           /*!<Interrupt Level detection Enable bit        */
+#define FMC_SR2_IFEN_Pos            (5U)                                       
+#define FMC_SR2_IFEN_Msk            (0x1U << FMC_SR2_IFEN_Pos)                 /*!< 0x00000020 */
+#define FMC_SR2_IFEN                FMC_SR2_IFEN_Msk                           /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR2_FEMPT_Pos           (6U)                                       
+#define FMC_SR2_FEMPT_Msk           (0x1U << FMC_SR2_FEMPT_Pos)                /*!< 0x00000040 */
+#define FMC_SR2_FEMPT               FMC_SR2_FEMPT_Msk                          /*!<FIFO empty                                  */
+
+/*******************  Bit definition for FMC_SR3 register  *******************/
+#define FMC_SR3_IRS_Pos             (0U)                                       
+#define FMC_SR3_IRS_Msk             (0x1U << FMC_SR3_IRS_Pos)                  /*!< 0x00000001 */
+#define FMC_SR3_IRS                 FMC_SR3_IRS_Msk                            /*!<Interrupt Rising Edge status                */
+#define FMC_SR3_ILS_Pos             (1U)                                       
+#define FMC_SR3_ILS_Msk             (0x1U << FMC_SR3_ILS_Pos)                  /*!< 0x00000002 */
+#define FMC_SR3_ILS                 FMC_SR3_ILS_Msk                            /*!<Interrupt Level status                      */
+#define FMC_SR3_IFS_Pos             (2U)                                       
+#define FMC_SR3_IFS_Msk             (0x1U << FMC_SR3_IFS_Pos)                  /*!< 0x00000004 */
+#define FMC_SR3_IFS                 FMC_SR3_IFS_Msk                            /*!<Interrupt Falling Edge status               */
+#define FMC_SR3_IREN_Pos            (3U)                                       
+#define FMC_SR3_IREN_Msk            (0x1U << FMC_SR3_IREN_Pos)                 /*!< 0x00000008 */
+#define FMC_SR3_IREN                FMC_SR3_IREN_Msk                           /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SR3_ILEN_Pos            (4U)                                       
+#define FMC_SR3_ILEN_Msk            (0x1U << FMC_SR3_ILEN_Pos)                 /*!< 0x00000010 */
+#define FMC_SR3_ILEN                FMC_SR3_ILEN_Msk                           /*!<Interrupt Level detection Enable bit        */
+#define FMC_SR3_IFEN_Pos            (5U)                                       
+#define FMC_SR3_IFEN_Msk            (0x1U << FMC_SR3_IFEN_Pos)                 /*!< 0x00000020 */
+#define FMC_SR3_IFEN                FMC_SR3_IFEN_Msk                           /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR3_FEMPT_Pos           (6U)                                       
+#define FMC_SR3_FEMPT_Msk           (0x1U << FMC_SR3_FEMPT_Pos)                /*!< 0x00000040 */
+#define FMC_SR3_FEMPT               FMC_SR3_FEMPT_Msk                          /*!<FIFO empty                                  */
+
+/*******************  Bit definition for FMC_SR4 register  *******************/
+#define FMC_SR4_IRS_Pos             (0U)                                       
+#define FMC_SR4_IRS_Msk             (0x1U << FMC_SR4_IRS_Pos)                  /*!< 0x00000001 */
+#define FMC_SR4_IRS                 FMC_SR4_IRS_Msk                            /*!<Interrupt Rising Edge status                */
+#define FMC_SR4_ILS_Pos             (1U)                                       
+#define FMC_SR4_ILS_Msk             (0x1U << FMC_SR4_ILS_Pos)                  /*!< 0x00000002 */
+#define FMC_SR4_ILS                 FMC_SR4_ILS_Msk                            /*!<Interrupt Level status                      */
+#define FMC_SR4_IFS_Pos             (2U)                                       
+#define FMC_SR4_IFS_Msk             (0x1U << FMC_SR4_IFS_Pos)                  /*!< 0x00000004 */
+#define FMC_SR4_IFS                 FMC_SR4_IFS_Msk                            /*!<Interrupt Falling Edge status               */
+#define FMC_SR4_IREN_Pos            (3U)                                       
+#define FMC_SR4_IREN_Msk            (0x1U << FMC_SR4_IREN_Pos)                 /*!< 0x00000008 */
+#define FMC_SR4_IREN                FMC_SR4_IREN_Msk                           /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SR4_ILEN_Pos            (4U)                                       
+#define FMC_SR4_ILEN_Msk            (0x1U << FMC_SR4_ILEN_Pos)                 /*!< 0x00000010 */
+#define FMC_SR4_ILEN                FMC_SR4_ILEN_Msk                           /*!<Interrupt Level detection Enable bit        */
+#define FMC_SR4_IFEN_Pos            (5U)                                       
+#define FMC_SR4_IFEN_Msk            (0x1U << FMC_SR4_IFEN_Pos)                 /*!< 0x00000020 */
+#define FMC_SR4_IFEN                FMC_SR4_IFEN_Msk                           /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR4_FEMPT_Pos           (6U)                                       
+#define FMC_SR4_FEMPT_Msk           (0x1U << FMC_SR4_FEMPT_Pos)                /*!< 0x00000040 */
+#define FMC_SR4_FEMPT               FMC_SR4_FEMPT_Msk                          /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEM2 register  ******************/
+#define FMC_PMEM2_MEMSET2_Pos       (0U)                                       
+#define FMC_PMEM2_MEMSET2_Msk       (0xFFU << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x000000FF */
+#define FMC_PMEM2_MEMSET2           FMC_PMEM2_MEMSET2_Msk                      /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM2_MEMSET2_0         (0x01U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000001 */
+#define FMC_PMEM2_MEMSET2_1         (0x02U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000002 */
+#define FMC_PMEM2_MEMSET2_2         (0x04U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000004 */
+#define FMC_PMEM2_MEMSET2_3         (0x08U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000008 */
+#define FMC_PMEM2_MEMSET2_4         (0x10U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000010 */
+#define FMC_PMEM2_MEMSET2_5         (0x20U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000020 */
+#define FMC_PMEM2_MEMSET2_6         (0x40U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000040 */
+#define FMC_PMEM2_MEMSET2_7         (0x80U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000080 */
+
+#define FMC_PMEM2_MEMWAIT2_Pos      (8U)                                       
+#define FMC_PMEM2_MEMWAIT2_Msk      (0xFFU << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x0000FF00 */
+#define FMC_PMEM2_MEMWAIT2          FMC_PMEM2_MEMWAIT2_Msk                     /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM2_MEMWAIT2_0        (0x01U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000100 */
+#define FMC_PMEM2_MEMWAIT2_1        (0x02U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000200 */
+#define FMC_PMEM2_MEMWAIT2_2        (0x04U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000400 */
+#define FMC_PMEM2_MEMWAIT2_3        (0x08U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000800 */
+#define FMC_PMEM2_MEMWAIT2_4        (0x10U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00001000 */
+#define FMC_PMEM2_MEMWAIT2_5        (0x20U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00002000 */
+#define FMC_PMEM2_MEMWAIT2_6        (0x40U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00004000 */
+#define FMC_PMEM2_MEMWAIT2_7        (0x80U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00008000 */
+
+#define FMC_PMEM2_MEMHOLD2_Pos      (16U)                                      
+#define FMC_PMEM2_MEMHOLD2_Msk      (0xFFU << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00FF0000 */
+#define FMC_PMEM2_MEMHOLD2          FMC_PMEM2_MEMHOLD2_Msk                     /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM2_MEMHOLD2_0        (0x01U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00010000 */
+#define FMC_PMEM2_MEMHOLD2_1        (0x02U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00020000 */
+#define FMC_PMEM2_MEMHOLD2_2        (0x04U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00040000 */
+#define FMC_PMEM2_MEMHOLD2_3        (0x08U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00080000 */
+#define FMC_PMEM2_MEMHOLD2_4        (0x10U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00100000 */
+#define FMC_PMEM2_MEMHOLD2_5        (0x20U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00200000 */
+#define FMC_PMEM2_MEMHOLD2_6        (0x40U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00400000 */
+#define FMC_PMEM2_MEMHOLD2_7        (0x80U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00800000 */
+
+#define FMC_PMEM2_MEMHIZ2_Pos       (24U)                                      
+#define FMC_PMEM2_MEMHIZ2_Msk       (0xFFU << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0xFF000000 */
+#define FMC_PMEM2_MEMHIZ2           FMC_PMEM2_MEMHIZ2_Msk                      /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM2_MEMHIZ2_0         (0x01U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x01000000 */
+#define FMC_PMEM2_MEMHIZ2_1         (0x02U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x02000000 */
+#define FMC_PMEM2_MEMHIZ2_2         (0x04U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x04000000 */
+#define FMC_PMEM2_MEMHIZ2_3         (0x08U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x08000000 */
+#define FMC_PMEM2_MEMHIZ2_4         (0x10U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x10000000 */
+#define FMC_PMEM2_MEMHIZ2_5         (0x20U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x20000000 */
+#define FMC_PMEM2_MEMHIZ2_6         (0x40U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x40000000 */
+#define FMC_PMEM2_MEMHIZ2_7         (0x80U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PMEM3 register  ******************/
+#define FMC_PMEM3_MEMSET3_Pos       (0U)                                       
+#define FMC_PMEM3_MEMSET3_Msk       (0xFFU << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x000000FF */
+#define FMC_PMEM3_MEMSET3           FMC_PMEM3_MEMSET3_Msk                      /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FMC_PMEM3_MEMSET3_0         (0x01U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000001 */
+#define FMC_PMEM3_MEMSET3_1         (0x02U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000002 */
+#define FMC_PMEM3_MEMSET3_2         (0x04U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000004 */
+#define FMC_PMEM3_MEMSET3_3         (0x08U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000008 */
+#define FMC_PMEM3_MEMSET3_4         (0x10U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000010 */
+#define FMC_PMEM3_MEMSET3_5         (0x20U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000020 */
+#define FMC_PMEM3_MEMSET3_6         (0x40U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000040 */
+#define FMC_PMEM3_MEMSET3_7         (0x80U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000080 */
+
+#define FMC_PMEM3_MEMWAIT3_Pos      (8U)                                       
+#define FMC_PMEM3_MEMWAIT3_Msk      (0xFFU << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x0000FF00 */
+#define FMC_PMEM3_MEMWAIT3          FMC_PMEM3_MEMWAIT3_Msk                     /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FMC_PMEM3_MEMWAIT3_0        (0x01U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000100 */
+#define FMC_PMEM3_MEMWAIT3_1        (0x02U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000200 */
+#define FMC_PMEM3_MEMWAIT3_2        (0x04U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000400 */
+#define FMC_PMEM3_MEMWAIT3_3        (0x08U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000800 */
+#define FMC_PMEM3_MEMWAIT3_4        (0x10U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00001000 */
+#define FMC_PMEM3_MEMWAIT3_5        (0x20U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00002000 */
+#define FMC_PMEM3_MEMWAIT3_6        (0x40U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00004000 */
+#define FMC_PMEM3_MEMWAIT3_7        (0x80U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00008000 */
+
+#define FMC_PMEM3_MEMHOLD3_Pos      (16U)                                      
+#define FMC_PMEM3_MEMHOLD3_Msk      (0xFFU << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00FF0000 */
+#define FMC_PMEM3_MEMHOLD3          FMC_PMEM3_MEMHOLD3_Msk                     /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FMC_PMEM3_MEMHOLD3_0        (0x01U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00010000 */
+#define FMC_PMEM3_MEMHOLD3_1        (0x02U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00020000 */
+#define FMC_PMEM3_MEMHOLD3_2        (0x04U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00040000 */
+#define FMC_PMEM3_MEMHOLD3_3        (0x08U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00080000 */
+#define FMC_PMEM3_MEMHOLD3_4        (0x10U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00100000 */
+#define FMC_PMEM3_MEMHOLD3_5        (0x20U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00200000 */
+#define FMC_PMEM3_MEMHOLD3_6        (0x40U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00400000 */
+#define FMC_PMEM3_MEMHOLD3_7        (0x80U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00800000 */
+
+#define FMC_PMEM3_MEMHIZ3_Pos       (24U)                                      
+#define FMC_PMEM3_MEMHIZ3_Msk       (0xFFU << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0xFF000000 */
+#define FMC_PMEM3_MEMHIZ3           FMC_PMEM3_MEMHIZ3_Msk                      /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FMC_PMEM3_MEMHIZ3_0         (0x01U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x01000000 */
+#define FMC_PMEM3_MEMHIZ3_1         (0x02U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x02000000 */
+#define FMC_PMEM3_MEMHIZ3_2         (0x04U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x04000000 */
+#define FMC_PMEM3_MEMHIZ3_3         (0x08U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x08000000 */
+#define FMC_PMEM3_MEMHIZ3_4         (0x10U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x10000000 */
+#define FMC_PMEM3_MEMHIZ3_5         (0x20U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x20000000 */
+#define FMC_PMEM3_MEMHIZ3_6         (0x40U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x40000000 */
+#define FMC_PMEM3_MEMHIZ3_7         (0x80U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PMEM4 register  ******************/
+#define FMC_PMEM4_MEMSET4_Pos       (0U)                                       
+#define FMC_PMEM4_MEMSET4_Msk       (0xFFU << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x000000FF */
+#define FMC_PMEM4_MEMSET4           FMC_PMEM4_MEMSET4_Msk                      /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FMC_PMEM4_MEMSET4_0         (0x01U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000001 */
+#define FMC_PMEM4_MEMSET4_1         (0x02U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000002 */
+#define FMC_PMEM4_MEMSET4_2         (0x04U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000004 */
+#define FMC_PMEM4_MEMSET4_3         (0x08U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000008 */
+#define FMC_PMEM4_MEMSET4_4         (0x10U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000010 */
+#define FMC_PMEM4_MEMSET4_5         (0x20U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000020 */
+#define FMC_PMEM4_MEMSET4_6         (0x40U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000040 */
+#define FMC_PMEM4_MEMSET4_7         (0x80U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000080 */
+
+#define FMC_PMEM4_MEMWAIT4_Pos      (8U)                                       
+#define FMC_PMEM4_MEMWAIT4_Msk      (0xFFU << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x0000FF00 */
+#define FMC_PMEM4_MEMWAIT4          FMC_PMEM4_MEMWAIT4_Msk                     /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FMC_PMEM4_MEMWAIT4_0        (0x01U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000100 */
+#define FMC_PMEM4_MEMWAIT4_1        (0x02U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000200 */
+#define FMC_PMEM4_MEMWAIT4_2        (0x04U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000400 */
+#define FMC_PMEM4_MEMWAIT4_3        (0x08U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000800 */
+#define FMC_PMEM4_MEMWAIT4_4        (0x10U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00001000 */
+#define FMC_PMEM4_MEMWAIT4_5        (0x20U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00002000 */
+#define FMC_PMEM4_MEMWAIT4_6        (0x40U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00004000 */
+#define FMC_PMEM4_MEMWAIT4_7        (0x80U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00008000 */
+
+#define FMC_PMEM4_MEMHOLD4_Pos      (16U)                                      
+#define FMC_PMEM4_MEMHOLD4_Msk      (0xFFU << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00FF0000 */
+#define FMC_PMEM4_MEMHOLD4          FMC_PMEM4_MEMHOLD4_Msk                     /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FMC_PMEM4_MEMHOLD4_0        (0x01U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00010000 */
+#define FMC_PMEM4_MEMHOLD4_1        (0x02U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00020000 */
+#define FMC_PMEM4_MEMHOLD4_2        (0x04U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00040000 */
+#define FMC_PMEM4_MEMHOLD4_3        (0x08U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00080000 */
+#define FMC_PMEM4_MEMHOLD4_4        (0x10U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00100000 */
+#define FMC_PMEM4_MEMHOLD4_5        (0x20U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00200000 */
+#define FMC_PMEM4_MEMHOLD4_6        (0x40U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00400000 */
+#define FMC_PMEM4_MEMHOLD4_7        (0x80U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00800000 */
+
+#define FMC_PMEM4_MEMHIZ4_Pos       (24U)                                      
+#define FMC_PMEM4_MEMHIZ4_Msk       (0xFFU << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0xFF000000 */
+#define FMC_PMEM4_MEMHIZ4           FMC_PMEM4_MEMHIZ4_Msk                      /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FMC_PMEM4_MEMHIZ4_0         (0x01U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x01000000 */
+#define FMC_PMEM4_MEMHIZ4_1         (0x02U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x02000000 */
+#define FMC_PMEM4_MEMHIZ4_2         (0x04U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x04000000 */
+#define FMC_PMEM4_MEMHIZ4_3         (0x08U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x08000000 */
+#define FMC_PMEM4_MEMHIZ4_4         (0x10U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x10000000 */
+#define FMC_PMEM4_MEMHIZ4_5         (0x20U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x20000000 */
+#define FMC_PMEM4_MEMHIZ4_6         (0x40U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x40000000 */
+#define FMC_PMEM4_MEMHIZ4_7         (0x80U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT2 register  ******************/
+#define FMC_PATT2_ATTSET2_Pos       (0U)                                       
+#define FMC_PATT2_ATTSET2_Msk       (0xFFU << FMC_PATT2_ATTSET2_Pos)           /*!< 0x000000FF */
+#define FMC_PATT2_ATTSET2           FMC_PATT2_ATTSET2_Msk                      /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT2_ATTSET2_0         (0x01U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000001 */
+#define FMC_PATT2_ATTSET2_1         (0x02U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000002 */
+#define FMC_PATT2_ATTSET2_2         (0x04U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000004 */
+#define FMC_PATT2_ATTSET2_3         (0x08U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000008 */
+#define FMC_PATT2_ATTSET2_4         (0x10U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000010 */
+#define FMC_PATT2_ATTSET2_5         (0x20U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000020 */
+#define FMC_PATT2_ATTSET2_6         (0x40U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000040 */
+#define FMC_PATT2_ATTSET2_7         (0x80U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000080 */
+
+#define FMC_PATT2_ATTWAIT2_Pos      (8U)                                       
+#define FMC_PATT2_ATTWAIT2_Msk      (0xFFU << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x0000FF00 */
+#define FMC_PATT2_ATTWAIT2          FMC_PATT2_ATTWAIT2_Msk                     /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT2_ATTWAIT2_0        (0x01U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000100 */
+#define FMC_PATT2_ATTWAIT2_1        (0x02U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000200 */
+#define FMC_PATT2_ATTWAIT2_2        (0x04U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000400 */
+#define FMC_PATT2_ATTWAIT2_3        (0x08U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000800 */
+#define FMC_PATT2_ATTWAIT2_4        (0x10U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00001000 */
+#define FMC_PATT2_ATTWAIT2_5        (0x20U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00002000 */
+#define FMC_PATT2_ATTWAIT2_6        (0x40U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00004000 */
+#define FMC_PATT2_ATTWAIT2_7        (0x80U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00008000 */
+
+#define FMC_PATT2_ATTHOLD2_Pos      (16U)                                      
+#define FMC_PATT2_ATTHOLD2_Msk      (0xFFU << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00FF0000 */
+#define FMC_PATT2_ATTHOLD2          FMC_PATT2_ATTHOLD2_Msk                     /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT2_ATTHOLD2_0        (0x01U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00010000 */
+#define FMC_PATT2_ATTHOLD2_1        (0x02U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00020000 */
+#define FMC_PATT2_ATTHOLD2_2        (0x04U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00040000 */
+#define FMC_PATT2_ATTHOLD2_3        (0x08U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00080000 */
+#define FMC_PATT2_ATTHOLD2_4        (0x10U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00100000 */
+#define FMC_PATT2_ATTHOLD2_5        (0x20U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00200000 */
+#define FMC_PATT2_ATTHOLD2_6        (0x40U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00400000 */
+#define FMC_PATT2_ATTHOLD2_7        (0x80U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00800000 */
+
+#define FMC_PATT2_ATTHIZ2_Pos       (24U)                                      
+#define FMC_PATT2_ATTHIZ2_Msk       (0xFFU << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0xFF000000 */
+#define FMC_PATT2_ATTHIZ2           FMC_PATT2_ATTHIZ2_Msk                      /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT2_ATTHIZ2_0         (0x01U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x01000000 */
+#define FMC_PATT2_ATTHIZ2_1         (0x02U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x02000000 */
+#define FMC_PATT2_ATTHIZ2_2         (0x04U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x04000000 */
+#define FMC_PATT2_ATTHIZ2_3         (0x08U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x08000000 */
+#define FMC_PATT2_ATTHIZ2_4         (0x10U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x10000000 */
+#define FMC_PATT2_ATTHIZ2_5         (0x20U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x20000000 */
+#define FMC_PATT2_ATTHIZ2_6         (0x40U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x40000000 */
+#define FMC_PATT2_ATTHIZ2_7         (0x80U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT3 register  ******************/
+#define FMC_PATT3_ATTSET3_Pos       (0U)                                       
+#define FMC_PATT3_ATTSET3_Msk       (0xFFU << FMC_PATT3_ATTSET3_Pos)           /*!< 0x000000FF */
+#define FMC_PATT3_ATTSET3           FMC_PATT3_ATTSET3_Msk                      /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FMC_PATT3_ATTSET3_0         (0x01U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000001 */
+#define FMC_PATT3_ATTSET3_1         (0x02U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000002 */
+#define FMC_PATT3_ATTSET3_2         (0x04U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000004 */
+#define FMC_PATT3_ATTSET3_3         (0x08U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000008 */
+#define FMC_PATT3_ATTSET3_4         (0x10U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000010 */
+#define FMC_PATT3_ATTSET3_5         (0x20U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000020 */
+#define FMC_PATT3_ATTSET3_6         (0x40U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000040 */
+#define FMC_PATT3_ATTSET3_7         (0x80U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000080 */
+
+#define FMC_PATT3_ATTWAIT3_Pos      (8U)                                       
+#define FMC_PATT3_ATTWAIT3_Msk      (0xFFU << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x0000FF00 */
+#define FMC_PATT3_ATTWAIT3          FMC_PATT3_ATTWAIT3_Msk                     /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FMC_PATT3_ATTWAIT3_0        (0x01U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000100 */
+#define FMC_PATT3_ATTWAIT3_1        (0x02U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000200 */
+#define FMC_PATT3_ATTWAIT3_2        (0x04U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000400 */
+#define FMC_PATT3_ATTWAIT3_3        (0x08U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000800 */
+#define FMC_PATT3_ATTWAIT3_4        (0x10U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00001000 */
+#define FMC_PATT3_ATTWAIT3_5        (0x20U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00002000 */
+#define FMC_PATT3_ATTWAIT3_6        (0x40U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00004000 */
+#define FMC_PATT3_ATTWAIT3_7        (0x80U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00008000 */
+
+#define FMC_PATT3_ATTHOLD3_Pos      (16U)                                      
+#define FMC_PATT3_ATTHOLD3_Msk      (0xFFU << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00FF0000 */
+#define FMC_PATT3_ATTHOLD3          FMC_PATT3_ATTHOLD3_Msk                     /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FMC_PATT3_ATTHOLD3_0        (0x01U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00010000 */
+#define FMC_PATT3_ATTHOLD3_1        (0x02U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00020000 */
+#define FMC_PATT3_ATTHOLD3_2        (0x04U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00040000 */
+#define FMC_PATT3_ATTHOLD3_3        (0x08U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00080000 */
+#define FMC_PATT3_ATTHOLD3_4        (0x10U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00100000 */
+#define FMC_PATT3_ATTHOLD3_5        (0x20U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00200000 */
+#define FMC_PATT3_ATTHOLD3_6        (0x40U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00400000 */
+#define FMC_PATT3_ATTHOLD3_7        (0x80U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00800000 */
+
+#define FMC_PATT3_ATTHIZ3_Pos       (24U)                                      
+#define FMC_PATT3_ATTHIZ3_Msk       (0xFFU << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0xFF000000 */
+#define FMC_PATT3_ATTHIZ3           FMC_PATT3_ATTHIZ3_Msk                      /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FMC_PATT3_ATTHIZ3_0         (0x01U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x01000000 */
+#define FMC_PATT3_ATTHIZ3_1         (0x02U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x02000000 */
+#define FMC_PATT3_ATTHIZ3_2         (0x04U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x04000000 */
+#define FMC_PATT3_ATTHIZ3_3         (0x08U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x08000000 */
+#define FMC_PATT3_ATTHIZ3_4         (0x10U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x10000000 */
+#define FMC_PATT3_ATTHIZ3_5         (0x20U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x20000000 */
+#define FMC_PATT3_ATTHIZ3_6         (0x40U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x40000000 */
+#define FMC_PATT3_ATTHIZ3_7         (0x80U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT4 register  ******************/
+#define FMC_PATT4_ATTSET4_Pos       (0U)                                       
+#define FMC_PATT4_ATTSET4_Msk       (0xFFU << FMC_PATT4_ATTSET4_Pos)           /*!< 0x000000FF */
+#define FMC_PATT4_ATTSET4           FMC_PATT4_ATTSET4_Msk                      /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FMC_PATT4_ATTSET4_0         (0x01U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000001 */
+#define FMC_PATT4_ATTSET4_1         (0x02U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000002 */
+#define FMC_PATT4_ATTSET4_2         (0x04U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000004 */
+#define FMC_PATT4_ATTSET4_3         (0x08U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000008 */
+#define FMC_PATT4_ATTSET4_4         (0x10U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000010 */
+#define FMC_PATT4_ATTSET4_5         (0x20U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000020 */
+#define FMC_PATT4_ATTSET4_6         (0x40U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000040 */
+#define FMC_PATT4_ATTSET4_7         (0x80U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000080 */
+
+#define FMC_PATT4_ATTWAIT4_Pos      (8U)                                       
+#define FMC_PATT4_ATTWAIT4_Msk      (0xFFU << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x0000FF00 */
+#define FMC_PATT4_ATTWAIT4          FMC_PATT4_ATTWAIT4_Msk                     /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FMC_PATT4_ATTWAIT4_0        (0x01U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000100 */
+#define FMC_PATT4_ATTWAIT4_1        (0x02U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000200 */
+#define FMC_PATT4_ATTWAIT4_2        (0x04U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000400 */
+#define FMC_PATT4_ATTWAIT4_3        (0x08U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000800 */
+#define FMC_PATT4_ATTWAIT4_4        (0x10U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00001000 */
+#define FMC_PATT4_ATTWAIT4_5        (0x20U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00002000 */
+#define FMC_PATT4_ATTWAIT4_6        (0x40U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00004000 */
+#define FMC_PATT4_ATTWAIT4_7        (0x80U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00008000 */
+
+#define FMC_PATT4_ATTHOLD4_Pos      (16U)                                      
+#define FMC_PATT4_ATTHOLD4_Msk      (0xFFU << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00FF0000 */
+#define FMC_PATT4_ATTHOLD4          FMC_PATT4_ATTHOLD4_Msk                     /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FMC_PATT4_ATTHOLD4_0        (0x01U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00010000 */
+#define FMC_PATT4_ATTHOLD4_1        (0x02U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00020000 */
+#define FMC_PATT4_ATTHOLD4_2        (0x04U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00040000 */
+#define FMC_PATT4_ATTHOLD4_3        (0x08U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00080000 */
+#define FMC_PATT4_ATTHOLD4_4        (0x10U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00100000 */
+#define FMC_PATT4_ATTHOLD4_5        (0x20U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00200000 */
+#define FMC_PATT4_ATTHOLD4_6        (0x40U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00400000 */
+#define FMC_PATT4_ATTHOLD4_7        (0x80U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00800000 */
+
+#define FMC_PATT4_ATTHIZ4_Pos       (24U)                                      
+#define FMC_PATT4_ATTHIZ4_Msk       (0xFFU << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0xFF000000 */
+#define FMC_PATT4_ATTHIZ4           FMC_PATT4_ATTHIZ4_Msk                      /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FMC_PATT4_ATTHIZ4_0         (0x01U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x01000000 */
+#define FMC_PATT4_ATTHIZ4_1         (0x02U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x02000000 */
+#define FMC_PATT4_ATTHIZ4_2         (0x04U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x04000000 */
+#define FMC_PATT4_ATTHIZ4_3         (0x08U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x08000000 */
+#define FMC_PATT4_ATTHIZ4_4         (0x10U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x10000000 */
+#define FMC_PATT4_ATTHIZ4_5         (0x20U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x20000000 */
+#define FMC_PATT4_ATTHIZ4_6         (0x40U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x40000000 */
+#define FMC_PATT4_ATTHIZ4_7         (0x80U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PIO4 register  *******************/
+#define FMC_PIO4_IOSET4_Pos         (0U)                                       
+#define FMC_PIO4_IOSET4_Msk         (0xFFU << FMC_PIO4_IOSET4_Pos)             /*!< 0x000000FF */
+#define FMC_PIO4_IOSET4             FMC_PIO4_IOSET4_Msk                        /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FMC_PIO4_IOSET4_0           (0x01U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000001 */
+#define FMC_PIO4_IOSET4_1           (0x02U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000002 */
+#define FMC_PIO4_IOSET4_2           (0x04U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000004 */
+#define FMC_PIO4_IOSET4_3           (0x08U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000008 */
+#define FMC_PIO4_IOSET4_4           (0x10U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000010 */
+#define FMC_PIO4_IOSET4_5           (0x20U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000020 */
+#define FMC_PIO4_IOSET4_6           (0x40U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000040 */
+#define FMC_PIO4_IOSET4_7           (0x80U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000080 */
+
+#define FMC_PIO4_IOWAIT4_Pos        (8U)                                       
+#define FMC_PIO4_IOWAIT4_Msk        (0xFFU << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x0000FF00 */
+#define FMC_PIO4_IOWAIT4            FMC_PIO4_IOWAIT4_Msk                       /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FMC_PIO4_IOWAIT4_0          (0x01U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000100 */
+#define FMC_PIO4_IOWAIT4_1          (0x02U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000200 */
+#define FMC_PIO4_IOWAIT4_2          (0x04U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000400 */
+#define FMC_PIO4_IOWAIT4_3          (0x08U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000800 */
+#define FMC_PIO4_IOWAIT4_4          (0x10U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00001000 */
+#define FMC_PIO4_IOWAIT4_5          (0x20U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00002000 */
+#define FMC_PIO4_IOWAIT4_6          (0x40U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00004000 */
+#define FMC_PIO4_IOWAIT4_7          (0x80U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00008000 */
+
+#define FMC_PIO4_IOHOLD4_Pos        (16U)                                      
+#define FMC_PIO4_IOHOLD4_Msk        (0xFFU << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00FF0000 */
+#define FMC_PIO4_IOHOLD4            FMC_PIO4_IOHOLD4_Msk                       /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FMC_PIO4_IOHOLD4_0          (0x01U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00010000 */
+#define FMC_PIO4_IOHOLD4_1          (0x02U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00020000 */
+#define FMC_PIO4_IOHOLD4_2          (0x04U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00040000 */
+#define FMC_PIO4_IOHOLD4_3          (0x08U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00080000 */
+#define FMC_PIO4_IOHOLD4_4          (0x10U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00100000 */
+#define FMC_PIO4_IOHOLD4_5          (0x20U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00200000 */
+#define FMC_PIO4_IOHOLD4_6          (0x40U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00400000 */
+#define FMC_PIO4_IOHOLD4_7          (0x80U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00800000 */
+
+#define FMC_PIO4_IOHIZ4_Pos         (24U)                                      
+#define FMC_PIO4_IOHIZ4_Msk         (0xFFU << FMC_PIO4_IOHIZ4_Pos)             /*!< 0xFF000000 */
+#define FMC_PIO4_IOHIZ4             FMC_PIO4_IOHIZ4_Msk                        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FMC_PIO4_IOHIZ4_0           (0x01U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x01000000 */
+#define FMC_PIO4_IOHIZ4_1           (0x02U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x02000000 */
+#define FMC_PIO4_IOHIZ4_2           (0x04U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x04000000 */
+#define FMC_PIO4_IOHIZ4_3           (0x08U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x08000000 */
+#define FMC_PIO4_IOHIZ4_4           (0x10U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x10000000 */
+#define FMC_PIO4_IOHIZ4_5           (0x20U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x20000000 */
+#define FMC_PIO4_IOHIZ4_6           (0x40U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x40000000 */
+#define FMC_PIO4_IOHIZ4_7           (0x80U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x80000000 */
+
+
+/******************  Bit definition for FMC_ECCR2 register  ******************/
+#define FMC_ECCR2_ECC2_Pos          (0U)                                       
+#define FMC_ECCR2_ECC2_Msk          (0xFFFFFFFFU << FMC_ECCR2_ECC2_Pos)        /*!< 0xFFFFFFFF */
+#define FMC_ECCR2_ECC2              FMC_ECCR2_ECC2_Msk                         /*!<ECC result */
+
+/******************  Bit definition for FMC_ECCR3 register  ******************/
+#define FMC_ECCR3_ECC3_Pos          (0U)                                       
+#define FMC_ECCR3_ECC3_Msk          (0xFFFFFFFFU << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */
+#define FMC_ECCR3_ECC3              FMC_ECCR3_ECC3_Msk                         /*!<ECC result */
+
+/******************  Bit definition for FMC_SDCR1 register  ******************/
+#define FMC_SDCR1_NC_Pos            (0U)                                       
+#define FMC_SDCR1_NC_Msk            (0x3U << FMC_SDCR1_NC_Pos)                 /*!< 0x00000003 */
+#define FMC_SDCR1_NC                FMC_SDCR1_NC_Msk                           /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR1_NC_0              (0x1U << FMC_SDCR1_NC_Pos)                 /*!< 0x00000001 */
+#define FMC_SDCR1_NC_1              (0x2U << FMC_SDCR1_NC_Pos)                 /*!< 0x00000002 */
+
+#define FMC_SDCR1_NR_Pos            (2U)                                       
+#define FMC_SDCR1_NR_Msk            (0x3U << FMC_SDCR1_NR_Pos)                 /*!< 0x0000000C */
+#define FMC_SDCR1_NR                FMC_SDCR1_NR_Msk                           /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_NR_0              (0x1U << FMC_SDCR1_NR_Pos)                 /*!< 0x00000004 */
+#define FMC_SDCR1_NR_1              (0x2U << FMC_SDCR1_NR_Pos)                 /*!< 0x00000008 */
+
+#define FMC_SDCR1_MWID_Pos          (4U)                                       
+#define FMC_SDCR1_MWID_Msk          (0x3U << FMC_SDCR1_MWID_Pos)               /*!< 0x00000030 */
+#define FMC_SDCR1_MWID              FMC_SDCR1_MWID_Msk                         /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR1_MWID_0            (0x1U << FMC_SDCR1_MWID_Pos)               /*!< 0x00000010 */
+#define FMC_SDCR1_MWID_1            (0x2U << FMC_SDCR1_MWID_Pos)               /*!< 0x00000020 */
+
+#define FMC_SDCR1_NB_Pos            (6U)                                       
+#define FMC_SDCR1_NB_Msk            (0x1U << FMC_SDCR1_NB_Pos)                 /*!< 0x00000040 */
+#define FMC_SDCR1_NB                FMC_SDCR1_NB_Msk                           /*!<Number of internal bank */
+
+#define FMC_SDCR1_CAS_Pos           (7U)                                       
+#define FMC_SDCR1_CAS_Msk           (0x3U << FMC_SDCR1_CAS_Pos)                /*!< 0x00000180 */
+#define FMC_SDCR1_CAS               FMC_SDCR1_CAS_Msk                          /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR1_CAS_0             (0x1U << FMC_SDCR1_CAS_Pos)                /*!< 0x00000080 */
+#define FMC_SDCR1_CAS_1             (0x2U << FMC_SDCR1_CAS_Pos)                /*!< 0x00000100 */
+
+#define FMC_SDCR1_WP_Pos            (9U)                                       
+#define FMC_SDCR1_WP_Msk            (0x1U << FMC_SDCR1_WP_Pos)                 /*!< 0x00000200 */
+#define FMC_SDCR1_WP                FMC_SDCR1_WP_Msk                           /*!<Write protection */
+
+#define FMC_SDCR1_SDCLK_Pos         (10U)                                      
+#define FMC_SDCR1_SDCLK_Msk         (0x3U << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000C00 */
+#define FMC_SDCR1_SDCLK             FMC_SDCR1_SDCLK_Msk                        /*!<SDRAM clock configuration */
+#define FMC_SDCR1_SDCLK_0           (0x1U << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000400 */
+#define FMC_SDCR1_SDCLK_1           (0x2U << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000800 */
+
+#define FMC_SDCR1_RBURST_Pos        (12U)                                      
+#define FMC_SDCR1_RBURST_Msk        (0x1U << FMC_SDCR1_RBURST_Pos)             /*!< 0x00001000 */
+#define FMC_SDCR1_RBURST            FMC_SDCR1_RBURST_Msk                       /*!<Read burst */
+
+#define FMC_SDCR1_RPIPE_Pos         (13U)                                      
+#define FMC_SDCR1_RPIPE_Msk         (0x3U << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00006000 */
+#define FMC_SDCR1_RPIPE             FMC_SDCR1_RPIPE_Msk                        /*!<Write protection */
+#define FMC_SDCR1_RPIPE_0           (0x1U << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00002000 */
+#define FMC_SDCR1_RPIPE_1           (0x2U << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00004000 */
+
+/******************  Bit definition for FMC_SDCR2 register  ******************/
+#define FMC_SDCR2_NC_Pos            (0U)                                       
+#define FMC_SDCR2_NC_Msk            (0x3U << FMC_SDCR2_NC_Pos)                 /*!< 0x00000003 */
+#define FMC_SDCR2_NC                FMC_SDCR2_NC_Msk                           /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCR2_NC_0              (0x1U << FMC_SDCR2_NC_Pos)                 /*!< 0x00000001 */
+#define FMC_SDCR2_NC_1              (0x2U << FMC_SDCR2_NC_Pos)                 /*!< 0x00000002 */
+
+#define FMC_SDCR2_NR_Pos            (2U)                                       
+#define FMC_SDCR2_NR_Msk            (0x3U << FMC_SDCR2_NR_Pos)                 /*!< 0x0000000C */
+#define FMC_SDCR2_NR                FMC_SDCR2_NR_Msk                           /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_NR_0              (0x1U << FMC_SDCR2_NR_Pos)                 /*!< 0x00000004 */
+#define FMC_SDCR2_NR_1              (0x2U << FMC_SDCR2_NR_Pos)                 /*!< 0x00000008 */
+
+#define FMC_SDCR2_MWID_Pos          (4U)                                       
+#define FMC_SDCR2_MWID_Msk          (0x3U << FMC_SDCR2_MWID_Pos)               /*!< 0x00000030 */
+#define FMC_SDCR2_MWID              FMC_SDCR2_MWID_Msk                         /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCR2_MWID_0            (0x1U << FMC_SDCR2_MWID_Pos)               /*!< 0x00000010 */
+#define FMC_SDCR2_MWID_1            (0x2U << FMC_SDCR2_MWID_Pos)               /*!< 0x00000020 */
+
+#define FMC_SDCR2_NB_Pos            (6U)                                       
+#define FMC_SDCR2_NB_Msk            (0x1U << FMC_SDCR2_NB_Pos)                 /*!< 0x00000040 */
+#define FMC_SDCR2_NB                FMC_SDCR2_NB_Msk                           /*!<Number of internal bank */
+
+#define FMC_SDCR2_CAS_Pos           (7U)                                       
+#define FMC_SDCR2_CAS_Msk           (0x3U << FMC_SDCR2_CAS_Pos)                /*!< 0x00000180 */
+#define FMC_SDCR2_CAS               FMC_SDCR2_CAS_Msk                          /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCR2_CAS_0             (0x1U << FMC_SDCR2_CAS_Pos)                /*!< 0x00000080 */
+#define FMC_SDCR2_CAS_1             (0x2U << FMC_SDCR2_CAS_Pos)                /*!< 0x00000100 */
+
+#define FMC_SDCR2_WP_Pos            (9U)                                       
+#define FMC_SDCR2_WP_Msk            (0x1U << FMC_SDCR2_WP_Pos)                 /*!< 0x00000200 */
+#define FMC_SDCR2_WP                FMC_SDCR2_WP_Msk                           /*!<Write protection */
+
+#define FMC_SDCR2_SDCLK_Pos         (10U)                                      
+#define FMC_SDCR2_SDCLK_Msk         (0x3U << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000C00 */
+#define FMC_SDCR2_SDCLK             FMC_SDCR2_SDCLK_Msk                        /*!<SDCLK[1:0] (SDRAM clock configuration) */
+#define FMC_SDCR2_SDCLK_0           (0x1U << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000400 */
+#define FMC_SDCR2_SDCLK_1           (0x2U << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000800 */
+
+#define FMC_SDCR2_RBURST_Pos        (12U)                                      
+#define FMC_SDCR2_RBURST_Msk        (0x1U << FMC_SDCR2_RBURST_Pos)             /*!< 0x00001000 */
+#define FMC_SDCR2_RBURST            FMC_SDCR2_RBURST_Msk                       /*!<Read burst */
+
+#define FMC_SDCR2_RPIPE_Pos         (13U)                                      
+#define FMC_SDCR2_RPIPE_Msk         (0x3U << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00006000 */
+#define FMC_SDCR2_RPIPE             FMC_SDCR2_RPIPE_Msk                        /*!<RPIPE[1:0](Read pipe) */
+#define FMC_SDCR2_RPIPE_0           (0x1U << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00002000 */
+#define FMC_SDCR2_RPIPE_1           (0x2U << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00004000 */
+
+/******************  Bit definition for FMC_SDTR1 register  ******************/
+#define FMC_SDTR1_TMRD_Pos          (0U)                                       
+#define FMC_SDTR1_TMRD_Msk          (0xFU << FMC_SDTR1_TMRD_Pos)               /*!< 0x0000000F */
+#define FMC_SDTR1_TMRD              FMC_SDTR1_TMRD_Msk                         /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR1_TMRD_0            (0x1U << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000001 */
+#define FMC_SDTR1_TMRD_1            (0x2U << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000002 */
+#define FMC_SDTR1_TMRD_2            (0x4U << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000004 */
+#define FMC_SDTR1_TMRD_3            (0x8U << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000008 */
+                                            
+#define FMC_SDTR1_TXSR_Pos          (4U)                                       
+#define FMC_SDTR1_TXSR_Msk          (0xFU << FMC_SDTR1_TXSR_Pos)               /*!< 0x000000F0 */
+#define FMC_SDTR1_TXSR              FMC_SDTR1_TXSR_Msk                         /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR1_TXSR_0            (0x1U << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000010 */
+#define FMC_SDTR1_TXSR_1            (0x2U << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000020 */
+#define FMC_SDTR1_TXSR_2            (0x4U << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000040 */
+#define FMC_SDTR1_TXSR_3            (0x8U << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000080 */
+
+#define FMC_SDTR1_TRAS_Pos          (8U)                                       
+#define FMC_SDTR1_TRAS_Msk          (0xFU << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000F00 */
+#define FMC_SDTR1_TRAS              FMC_SDTR1_TRAS_Msk                         /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR1_TRAS_0            (0x1U << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000100 */
+#define FMC_SDTR1_TRAS_1            (0x2U << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000200 */
+#define FMC_SDTR1_TRAS_2            (0x4U << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000400 */
+#define FMC_SDTR1_TRAS_3            (0x8U << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000800 */
+
+#define FMC_SDTR1_TRC_Pos           (12U)                                      
+#define FMC_SDTR1_TRC_Msk           (0xFU << FMC_SDTR1_TRC_Pos)                /*!< 0x0000F000 */
+#define FMC_SDTR1_TRC               FMC_SDTR1_TRC_Msk                          /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR1_TRC_0             (0x1U << FMC_SDTR1_TRC_Pos)                /*!< 0x00001000 */
+#define FMC_SDTR1_TRC_1             (0x2U << FMC_SDTR1_TRC_Pos)                /*!< 0x00002000 */
+#define FMC_SDTR1_TRC_2             (0x4U << FMC_SDTR1_TRC_Pos)                /*!< 0x00004000 */
+
+#define FMC_SDTR1_TWR_Pos           (16U)                                      
+#define FMC_SDTR1_TWR_Msk           (0xFU << FMC_SDTR1_TWR_Pos)                /*!< 0x000F0000 */
+#define FMC_SDTR1_TWR               FMC_SDTR1_TWR_Msk                          /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR1_TWR_0             (0x1U << FMC_SDTR1_TWR_Pos)                /*!< 0x00010000 */
+#define FMC_SDTR1_TWR_1             (0x2U << FMC_SDTR1_TWR_Pos)                /*!< 0x00020000 */
+#define FMC_SDTR1_TWR_2             (0x4U << FMC_SDTR1_TWR_Pos)                /*!< 0x00040000 */
+
+#define FMC_SDTR1_TRP_Pos           (20U)                                      
+#define FMC_SDTR1_TRP_Msk           (0xFU << FMC_SDTR1_TRP_Pos)                /*!< 0x00F00000 */
+#define FMC_SDTR1_TRP               FMC_SDTR1_TRP_Msk                          /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR1_TRP_0             (0x1U << FMC_SDTR1_TRP_Pos)                /*!< 0x00100000 */
+#define FMC_SDTR1_TRP_1             (0x2U << FMC_SDTR1_TRP_Pos)                /*!< 0x00200000 */
+#define FMC_SDTR1_TRP_2             (0x4U << FMC_SDTR1_TRP_Pos)                /*!< 0x00400000 */
+
+#define FMC_SDTR1_TRCD_Pos          (24U)                                      
+#define FMC_SDTR1_TRCD_Msk          (0xFU << FMC_SDTR1_TRCD_Pos)               /*!< 0x0F000000 */
+#define FMC_SDTR1_TRCD              FMC_SDTR1_TRCD_Msk                         /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR1_TRCD_0            (0x1U << FMC_SDTR1_TRCD_Pos)               /*!< 0x01000000 */
+#define FMC_SDTR1_TRCD_1            (0x2U << FMC_SDTR1_TRCD_Pos)               /*!< 0x02000000 */
+#define FMC_SDTR1_TRCD_2            (0x4U << FMC_SDTR1_TRCD_Pos)               /*!< 0x04000000 */
+
+/******************  Bit definition for FMC_SDTR2 register  ******************/
+#define FMC_SDTR2_TMRD_Pos          (0U)                                       
+#define FMC_SDTR2_TMRD_Msk          (0xFU << FMC_SDTR2_TMRD_Pos)               /*!< 0x0000000F */
+#define FMC_SDTR2_TMRD              FMC_SDTR2_TMRD_Msk                         /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTR2_TMRD_0            (0x1U << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000001 */
+#define FMC_SDTR2_TMRD_1            (0x2U << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000002 */
+#define FMC_SDTR2_TMRD_2            (0x4U << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000004 */
+#define FMC_SDTR2_TMRD_3            (0x8U << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000008 */
+                                            
+#define FMC_SDTR2_TXSR_Pos          (4U)                                       
+#define FMC_SDTR2_TXSR_Msk          (0xFU << FMC_SDTR2_TXSR_Pos)               /*!< 0x000000F0 */
+#define FMC_SDTR2_TXSR              FMC_SDTR2_TXSR_Msk                         /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTR2_TXSR_0            (0x1U << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000010 */
+#define FMC_SDTR2_TXSR_1            (0x2U << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000020 */
+#define FMC_SDTR2_TXSR_2            (0x4U << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000040 */
+#define FMC_SDTR2_TXSR_3            (0x8U << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000080 */
+
+#define FMC_SDTR2_TRAS_Pos          (8U)                                       
+#define FMC_SDTR2_TRAS_Msk          (0xFU << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000F00 */
+#define FMC_SDTR2_TRAS              FMC_SDTR2_TRAS_Msk                         /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTR2_TRAS_0            (0x1U << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000100 */
+#define FMC_SDTR2_TRAS_1            (0x2U << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000200 */
+#define FMC_SDTR2_TRAS_2            (0x4U << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000400 */
+#define FMC_SDTR2_TRAS_3            (0x8U << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000800 */
+
+#define FMC_SDTR2_TRC_Pos           (12U)                                      
+#define FMC_SDTR2_TRC_Msk           (0xFU << FMC_SDTR2_TRC_Pos)                /*!< 0x0000F000 */
+#define FMC_SDTR2_TRC               FMC_SDTR2_TRC_Msk                          /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTR2_TRC_0             (0x1U << FMC_SDTR2_TRC_Pos)                /*!< 0x00001000 */
+#define FMC_SDTR2_TRC_1             (0x2U << FMC_SDTR2_TRC_Pos)                /*!< 0x00002000 */
+#define FMC_SDTR2_TRC_2             (0x4U << FMC_SDTR2_TRC_Pos)                /*!< 0x00004000 */
+
+#define FMC_SDTR2_TWR_Pos           (16U)                                      
+#define FMC_SDTR2_TWR_Msk           (0xFU << FMC_SDTR2_TWR_Pos)                /*!< 0x000F0000 */
+#define FMC_SDTR2_TWR               FMC_SDTR2_TWR_Msk                          /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTR2_TWR_0             (0x1U << FMC_SDTR2_TWR_Pos)                /*!< 0x00010000 */
+#define FMC_SDTR2_TWR_1             (0x2U << FMC_SDTR2_TWR_Pos)                /*!< 0x00020000 */
+#define FMC_SDTR2_TWR_2             (0x4U << FMC_SDTR2_TWR_Pos)                /*!< 0x00040000 */
+
+#define FMC_SDTR2_TRP_Pos           (20U)                                      
+#define FMC_SDTR2_TRP_Msk           (0xFU << FMC_SDTR2_TRP_Pos)                /*!< 0x00F00000 */
+#define FMC_SDTR2_TRP               FMC_SDTR2_TRP_Msk                          /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTR2_TRP_0             (0x1U << FMC_SDTR2_TRP_Pos)                /*!< 0x00100000 */
+#define FMC_SDTR2_TRP_1             (0x2U << FMC_SDTR2_TRP_Pos)                /*!< 0x00200000 */
+#define FMC_SDTR2_TRP_2             (0x4U << FMC_SDTR2_TRP_Pos)                /*!< 0x00400000 */
+
+#define FMC_SDTR2_TRCD_Pos          (24U)                                      
+#define FMC_SDTR2_TRCD_Msk          (0xFU << FMC_SDTR2_TRCD_Pos)               /*!< 0x0F000000 */
+#define FMC_SDTR2_TRCD              FMC_SDTR2_TRCD_Msk                         /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTR2_TRCD_0            (0x1U << FMC_SDTR2_TRCD_Pos)               /*!< 0x01000000 */
+#define FMC_SDTR2_TRCD_1            (0x2U << FMC_SDTR2_TRCD_Pos)               /*!< 0x02000000 */
+#define FMC_SDTR2_TRCD_2            (0x4U << FMC_SDTR2_TRCD_Pos)               /*!< 0x04000000 */
+
+/******************  Bit definition for FMC_SDCMR register  ******************/
+#define FMC_SDCMR_MODE_Pos          (0U)                                       
+#define FMC_SDCMR_MODE_Msk          (0x7U << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
+#define FMC_SDCMR_MODE              FMC_SDCMR_MODE_Msk                         /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0            (0x1U << FMC_SDCMR_MODE_Pos)               /*!< 0x00000001 */
+#define FMC_SDCMR_MODE_1            (0x2U << FMC_SDCMR_MODE_Pos)               /*!< 0x00000002 */
+#define FMC_SDCMR_MODE_2            (0x4U << FMC_SDCMR_MODE_Pos)               /*!< 0x00000004 */
+                                            
+#define FMC_SDCMR_CTB2_Pos          (3U)                                       
+#define FMC_SDCMR_CTB2_Msk          (0x1U << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
+#define FMC_SDCMR_CTB2              FMC_SDCMR_CTB2_Msk                         /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1_Pos          (4U)                                       
+#define FMC_SDCMR_CTB1_Msk          (0x1U << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */
+#define FMC_SDCMR_CTB1              FMC_SDCMR_CTB1_Msk                         /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS_Pos          (5U)                                       
+#define FMC_SDCMR_NRFS_Msk          (0xFU << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
+#define FMC_SDCMR_NRFS              FMC_SDCMR_NRFS_Msk                         /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0            (0x1U << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000020 */
+#define FMC_SDCMR_NRFS_1            (0x2U << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000040 */
+#define FMC_SDCMR_NRFS_2            (0x4U << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000080 */
+#define FMC_SDCMR_NRFS_3            (0x8U << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000100 */
+
+#define FMC_SDCMR_MRD_Pos           (9U)                                       
+#define FMC_SDCMR_MRD_Msk           (0x1FFFU << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */
+#define FMC_SDCMR_MRD               FMC_SDCMR_MRD_Msk                          /*!<MRD[12:0] bits (Mode register definition) */
+
+/******************  Bit definition for FMC_SDRTR register  ******************/
+#define FMC_SDRTR_CRE_Pos           (0U)                                       
+#define FMC_SDRTR_CRE_Msk           (0x1U << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
+#define FMC_SDRTR_CRE               FMC_SDRTR_CRE_Msk                          /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT_Pos         (1U)                                       
+#define FMC_SDRTR_COUNT_Msk         (0x1FFFU << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */
+#define FMC_SDRTR_COUNT             FMC_SDRTR_COUNT_Msk                        /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE_Pos          (14U)                                      
+#define FMC_SDRTR_REIE_Msk          (0x1U << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
+#define FMC_SDRTR_REIE              FMC_SDRTR_REIE_Msk                         /*!<RES interupt enable */
+
+/******************  Bit definition for FMC_SDSR register  ******************/
+#define FMC_SDSR_RE_Pos             (0U)                                       
+#define FMC_SDSR_RE_Msk             (0x1U << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
+#define FMC_SDSR_RE                 FMC_SDSR_RE_Msk                            /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1_Pos         (1U)                                       
+#define FMC_SDSR_MODES1_Msk         (0x3U << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
+#define FMC_SDSR_MODES1             FMC_SDSR_MODES1_Msk                        /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0           (0x1U << FMC_SDSR_MODES1_Pos)              /*!< 0x00000002 */
+#define FMC_SDSR_MODES1_1           (0x2U << FMC_SDSR_MODES1_Pos)              /*!< 0x00000004 */
+
+#define FMC_SDSR_MODES2_Pos         (3U)                                       
+#define FMC_SDSR_MODES2_Msk         (0x3U << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
+#define FMC_SDSR_MODES2             FMC_SDSR_MODES2_Msk                        /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0           (0x1U << FMC_SDSR_MODES2_Pos)              /*!< 0x00000008 */
+#define FMC_SDSR_MODES2_1           (0x2U << FMC_SDSR_MODES2_Pos)              /*!< 0x00000010 */
+#define FMC_SDSR_BUSY_Pos           (5U)                                       
+#define FMC_SDSR_BUSY_Msk           (0x1U << FMC_SDSR_BUSY_Pos)                /*!< 0x00000020 */
+#define FMC_SDSR_BUSY               FMC_SDSR_BUSY_Msk                          /*!<Busy status */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos             (0U)                                  
+#define GPIO_MODER_MODE0_Msk             (0x3U << GPIO_MODER_MODE0_Pos)        /*!< 0x00000003 */
+#define GPIO_MODER_MODE0                 GPIO_MODER_MODE0_Msk                  
+#define GPIO_MODER_MODE0_0               (0x1U << GPIO_MODER_MODE0_Pos)        /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1               (0x2U << GPIO_MODER_MODE0_Pos)        /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos             (2U)                                  
+#define GPIO_MODER_MODE1_Msk             (0x3U << GPIO_MODER_MODE1_Pos)        /*!< 0x0000000C */
+#define GPIO_MODER_MODE1                 GPIO_MODER_MODE1_Msk                  
+#define GPIO_MODER_MODE1_0               (0x1U << GPIO_MODER_MODE1_Pos)        /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1               (0x2U << GPIO_MODER_MODE1_Pos)        /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos             (4U)                                  
+#define GPIO_MODER_MODE2_Msk             (0x3U << GPIO_MODER_MODE2_Pos)        /*!< 0x00000030 */
+#define GPIO_MODER_MODE2                 GPIO_MODER_MODE2_Msk                  
+#define GPIO_MODER_MODE2_0               (0x1U << GPIO_MODER_MODE2_Pos)        /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1               (0x2U << GPIO_MODER_MODE2_Pos)        /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos             (6U)                                  
+#define GPIO_MODER_MODE3_Msk             (0x3U << GPIO_MODER_MODE3_Pos)        /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3                 GPIO_MODER_MODE3_Msk                  
+#define GPIO_MODER_MODE3_0               (0x1U << GPIO_MODER_MODE3_Pos)        /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1               (0x2U << GPIO_MODER_MODE3_Pos)        /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos             (8U)                                  
+#define GPIO_MODER_MODE4_Msk             (0x3U << GPIO_MODER_MODE4_Pos)        /*!< 0x00000300 */
+#define GPIO_MODER_MODE4                 GPIO_MODER_MODE4_Msk                  
+#define GPIO_MODER_MODE4_0               (0x1U << GPIO_MODER_MODE4_Pos)        /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1               (0x2U << GPIO_MODER_MODE4_Pos)        /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos             (10U)                                 
+#define GPIO_MODER_MODE5_Msk             (0x3U << GPIO_MODER_MODE5_Pos)        /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5                 GPIO_MODER_MODE5_Msk                  
+#define GPIO_MODER_MODE5_0               (0x1U << GPIO_MODER_MODE5_Pos)        /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1               (0x2U << GPIO_MODER_MODE5_Pos)        /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos             (12U)                                 
+#define GPIO_MODER_MODE6_Msk             (0x3U << GPIO_MODER_MODE6_Pos)        /*!< 0x00003000 */
+#define GPIO_MODER_MODE6                 GPIO_MODER_MODE6_Msk                  
+#define GPIO_MODER_MODE6_0               (0x1U << GPIO_MODER_MODE6_Pos)        /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1               (0x2U << GPIO_MODER_MODE6_Pos)        /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos             (14U)                                 
+#define GPIO_MODER_MODE7_Msk             (0x3U << GPIO_MODER_MODE7_Pos)        /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7                 GPIO_MODER_MODE7_Msk                  
+#define GPIO_MODER_MODE7_0               (0x1U << GPIO_MODER_MODE7_Pos)        /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1               (0x2U << GPIO_MODER_MODE7_Pos)        /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos             (16U)                                 
+#define GPIO_MODER_MODE8_Msk             (0x3U << GPIO_MODER_MODE8_Pos)        /*!< 0x00030000 */
+#define GPIO_MODER_MODE8                 GPIO_MODER_MODE8_Msk                  
+#define GPIO_MODER_MODE8_0               (0x1U << GPIO_MODER_MODE8_Pos)        /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1               (0x2U << GPIO_MODER_MODE8_Pos)        /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos             (18U)                                 
+#define GPIO_MODER_MODE9_Msk             (0x3U << GPIO_MODER_MODE9_Pos)        /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9                 GPIO_MODER_MODE9_Msk                  
+#define GPIO_MODER_MODE9_0               (0x1U << GPIO_MODER_MODE9_Pos)        /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1               (0x2U << GPIO_MODER_MODE9_Pos)        /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos            (20U)                                 
+#define GPIO_MODER_MODE10_Msk            (0x3U << GPIO_MODER_MODE10_Pos)       /*!< 0x00300000 */
+#define GPIO_MODER_MODE10                GPIO_MODER_MODE10_Msk                 
+#define GPIO_MODER_MODE10_0              (0x1U << GPIO_MODER_MODE10_Pos)       /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1              (0x2U << GPIO_MODER_MODE10_Pos)       /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos            (22U)                                 
+#define GPIO_MODER_MODE11_Msk            (0x3U << GPIO_MODER_MODE11_Pos)       /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11                GPIO_MODER_MODE11_Msk                 
+#define GPIO_MODER_MODE11_0              (0x1U << GPIO_MODER_MODE11_Pos)       /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1              (0x2U << GPIO_MODER_MODE11_Pos)       /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos            (24U)                                 
+#define GPIO_MODER_MODE12_Msk            (0x3U << GPIO_MODER_MODE12_Pos)       /*!< 0x03000000 */
+#define GPIO_MODER_MODE12                GPIO_MODER_MODE12_Msk                 
+#define GPIO_MODER_MODE12_0              (0x1U << GPIO_MODER_MODE12_Pos)       /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1              (0x2U << GPIO_MODER_MODE12_Pos)       /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos            (26U)                                 
+#define GPIO_MODER_MODE13_Msk            (0x3U << GPIO_MODER_MODE13_Pos)       /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13                GPIO_MODER_MODE13_Msk                 
+#define GPIO_MODER_MODE13_0              (0x1U << GPIO_MODER_MODE13_Pos)       /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1              (0x2U << GPIO_MODER_MODE13_Pos)       /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos            (28U)                                 
+#define GPIO_MODER_MODE14_Msk            (0x3U << GPIO_MODER_MODE14_Pos)       /*!< 0x30000000 */
+#define GPIO_MODER_MODE14                GPIO_MODER_MODE14_Msk                 
+#define GPIO_MODER_MODE14_0              (0x1U << GPIO_MODER_MODE14_Pos)       /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1              (0x2U << GPIO_MODER_MODE14_Pos)       /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos            (30U)                                 
+#define GPIO_MODER_MODE15_Msk            (0x3U << GPIO_MODER_MODE15_Pos)       /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15                GPIO_MODER_MODE15_Msk                 
+#define GPIO_MODER_MODE15_0              (0x1U << GPIO_MODER_MODE15_Pos)       /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1              (0x2U << GPIO_MODER_MODE15_Pos)       /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODER0_Pos            (0U)                                  
+#define GPIO_MODER_MODER0_Msk            (0x3U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */
+#define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk                 
+#define GPIO_MODER_MODER0_0              (0x1U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1              (0x2U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos            (2U)                                  
+#define GPIO_MODER_MODER1_Msk            (0x3U << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */
+#define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk                 
+#define GPIO_MODER_MODER1_0              (0x1U << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1              (0x2U << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos            (4U)                                  
+#define GPIO_MODER_MODER2_Msk            (0x3U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */
+#define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk                 
+#define GPIO_MODER_MODER2_0              (0x1U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1              (0x2U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos            (6U)                                  
+#define GPIO_MODER_MODER3_Msk            (0x3U << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk                 
+#define GPIO_MODER_MODER3_0              (0x1U << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1              (0x2U << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos            (8U)                                  
+#define GPIO_MODER_MODER4_Msk            (0x3U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */
+#define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk                 
+#define GPIO_MODER_MODER4_0              (0x1U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1              (0x2U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos            (10U)                                 
+#define GPIO_MODER_MODER5_Msk            (0x3U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk                 
+#define GPIO_MODER_MODER5_0              (0x1U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1              (0x2U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos            (12U)                                 
+#define GPIO_MODER_MODER6_Msk            (0x3U << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */
+#define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk                 
+#define GPIO_MODER_MODER6_0              (0x1U << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1              (0x2U << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos            (14U)                                 
+#define GPIO_MODER_MODER7_Msk            (0x3U << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk                 
+#define GPIO_MODER_MODER7_0              (0x1U << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1              (0x2U << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos            (16U)                                 
+#define GPIO_MODER_MODER8_Msk            (0x3U << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */
+#define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk                 
+#define GPIO_MODER_MODER8_0              (0x1U << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1              (0x2U << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos            (18U)                                 
+#define GPIO_MODER_MODER9_Msk            (0x3U << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk                 
+#define GPIO_MODER_MODER9_0              (0x1U << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1              (0x2U << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos           (20U)                                 
+#define GPIO_MODER_MODER10_Msk           (0x3U << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */
+#define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk                
+#define GPIO_MODER_MODER10_0             (0x1U << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1             (0x2U << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos           (22U)                                 
+#define GPIO_MODER_MODER11_Msk           (0x3U << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk                
+#define GPIO_MODER_MODER11_0             (0x1U << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1             (0x2U << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos           (24U)                                 
+#define GPIO_MODER_MODER12_Msk           (0x3U << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */
+#define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk                
+#define GPIO_MODER_MODER12_0             (0x1U << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1             (0x2U << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos           (26U)                                 
+#define GPIO_MODER_MODER13_Msk           (0x3U << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk                
+#define GPIO_MODER_MODER13_0             (0x1U << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1             (0x2U << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos           (28U)                                 
+#define GPIO_MODER_MODER14_Msk           (0x3U << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */
+#define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk                
+#define GPIO_MODER_MODER14_0             (0x1U << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1             (0x2U << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos           (30U)                                 
+#define GPIO_MODER_MODER15_Msk           (0x3U << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk                
+#define GPIO_MODER_MODER15_0             (0x1U << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1             (0x2U << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos              (0U)                                  
+#define GPIO_OTYPER_OT0_Msk              (0x1U << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk                   
+#define GPIO_OTYPER_OT1_Pos              (1U)                                  
+#define GPIO_OTYPER_OT1_Msk              (0x1U << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk                   
+#define GPIO_OTYPER_OT2_Pos              (2U)                                  
+#define GPIO_OTYPER_OT2_Msk              (0x1U << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk                   
+#define GPIO_OTYPER_OT3_Pos              (3U)                                  
+#define GPIO_OTYPER_OT3_Msk              (0x1U << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk                   
+#define GPIO_OTYPER_OT4_Pos              (4U)                                  
+#define GPIO_OTYPER_OT4_Msk              (0x1U << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk                   
+#define GPIO_OTYPER_OT5_Pos              (5U)                                  
+#define GPIO_OTYPER_OT5_Msk              (0x1U << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk                   
+#define GPIO_OTYPER_OT6_Pos              (6U)                                  
+#define GPIO_OTYPER_OT6_Msk              (0x1U << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk                   
+#define GPIO_OTYPER_OT7_Pos              (7U)                                  
+#define GPIO_OTYPER_OT7_Msk              (0x1U << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk                   
+#define GPIO_OTYPER_OT8_Pos              (8U)                                  
+#define GPIO_OTYPER_OT8_Msk              (0x1U << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk                   
+#define GPIO_OTYPER_OT9_Pos              (9U)                                  
+#define GPIO_OTYPER_OT9_Msk              (0x1U << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk                   
+#define GPIO_OTYPER_OT10_Pos             (10U)                                 
+#define GPIO_OTYPER_OT10_Msk             (0x1U << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk                  
+#define GPIO_OTYPER_OT11_Pos             (11U)                                 
+#define GPIO_OTYPER_OT11_Msk             (0x1U << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk                  
+#define GPIO_OTYPER_OT12_Pos             (12U)                                 
+#define GPIO_OTYPER_OT12_Msk             (0x1U << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk                  
+#define GPIO_OTYPER_OT13_Pos             (13U)                                 
+#define GPIO_OTYPER_OT13_Msk             (0x1U << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk                  
+#define GPIO_OTYPER_OT14_Pos             (14U)                                 
+#define GPIO_OTYPER_OT14_Msk             (0x1U << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk                  
+#define GPIO_OTYPER_OT15_Pos             (15U)                                 
+#define GPIO_OTYPER_OT15_Msk             (0x1U << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk                  
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos         (0U)                                  
+#define GPIO_OSPEEDR_OSPEED0_Msk         (0x3U << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk              
+#define GPIO_OSPEEDR_OSPEED0_0           (0x1U << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1           (0x2U << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos         (2U)                                  
+#define GPIO_OSPEEDR_OSPEED1_Msk         (0x3U << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk              
+#define GPIO_OSPEEDR_OSPEED1_0           (0x1U << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1           (0x2U << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos         (4U)                                  
+#define GPIO_OSPEEDR_OSPEED2_Msk         (0x3U << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk              
+#define GPIO_OSPEEDR_OSPEED2_0           (0x1U << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1           (0x2U << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos         (6U)                                  
+#define GPIO_OSPEEDR_OSPEED3_Msk         (0x3U << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk              
+#define GPIO_OSPEEDR_OSPEED3_0           (0x1U << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1           (0x2U << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos         (8U)                                  
+#define GPIO_OSPEEDR_OSPEED4_Msk         (0x3U << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk              
+#define GPIO_OSPEEDR_OSPEED4_0           (0x1U << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1           (0x2U << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos         (10U)                                 
+#define GPIO_OSPEEDR_OSPEED5_Msk         (0x3U << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk              
+#define GPIO_OSPEEDR_OSPEED5_0           (0x1U << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1           (0x2U << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos         (12U)                                 
+#define GPIO_OSPEEDR_OSPEED6_Msk         (0x3U << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk              
+#define GPIO_OSPEEDR_OSPEED6_0           (0x1U << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1           (0x2U << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos         (14U)                                 
+#define GPIO_OSPEEDR_OSPEED7_Msk         (0x3U << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk              
+#define GPIO_OSPEEDR_OSPEED7_0           (0x1U << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1           (0x2U << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos         (16U)                                 
+#define GPIO_OSPEEDR_OSPEED8_Msk         (0x3U << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk              
+#define GPIO_OSPEEDR_OSPEED8_0           (0x1U << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1           (0x2U << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos         (18U)                                 
+#define GPIO_OSPEEDR_OSPEED9_Msk         (0x3U << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk              
+#define GPIO_OSPEEDR_OSPEED9_0           (0x1U << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1           (0x2U << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos        (20U)                                 
+#define GPIO_OSPEEDR_OSPEED10_Msk        (0x3U << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk             
+#define GPIO_OSPEEDR_OSPEED10_0          (0x1U << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1          (0x2U << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos        (22U)                                 
+#define GPIO_OSPEEDR_OSPEED11_Msk        (0x3U << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk             
+#define GPIO_OSPEEDR_OSPEED11_0          (0x1U << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1          (0x2U << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos        (24U)                                 
+#define GPIO_OSPEEDR_OSPEED12_Msk        (0x3U << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk             
+#define GPIO_OSPEEDR_OSPEED12_0          (0x1U << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1          (0x2U << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos        (26U)                                 
+#define GPIO_OSPEEDR_OSPEED13_Msk        (0x3U << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk             
+#define GPIO_OSPEEDR_OSPEED13_0          (0x1U << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1          (0x2U << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos        (28U)                                 
+#define GPIO_OSPEEDR_OSPEED14_Msk        (0x3U << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk             
+#define GPIO_OSPEEDR_OSPEED14_0          (0x1U << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1          (0x2U << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos        (30U)                                 
+#define GPIO_OSPEEDR_OSPEED15_Msk        (0x3U << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk             
+#define GPIO_OSPEEDR_OSPEED15_0          (0x1U << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1          (0x2U << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos             (0U)                                  
+#define GPIO_PUPDR_PUPD0_Msk             (0x3U << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk                  
+#define GPIO_PUPDR_PUPD0_0               (0x1U << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1               (0x2U << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos             (2U)                                  
+#define GPIO_PUPDR_PUPD1_Msk             (0x3U << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk                  
+#define GPIO_PUPDR_PUPD1_0               (0x1U << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1               (0x2U << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos             (4U)                                  
+#define GPIO_PUPDR_PUPD2_Msk             (0x3U << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk                  
+#define GPIO_PUPDR_PUPD2_0               (0x1U << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1               (0x2U << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos             (6U)                                  
+#define GPIO_PUPDR_PUPD3_Msk             (0x3U << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk                  
+#define GPIO_PUPDR_PUPD3_0               (0x1U << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1               (0x2U << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos             (8U)                                  
+#define GPIO_PUPDR_PUPD4_Msk             (0x3U << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk                  
+#define GPIO_PUPDR_PUPD4_0               (0x1U << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1               (0x2U << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos             (10U)                                 
+#define GPIO_PUPDR_PUPD5_Msk             (0x3U << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk                  
+#define GPIO_PUPDR_PUPD5_0               (0x1U << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1               (0x2U << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos             (12U)                                 
+#define GPIO_PUPDR_PUPD6_Msk             (0x3U << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk                  
+#define GPIO_PUPDR_PUPD6_0               (0x1U << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1               (0x2U << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos             (14U)                                 
+#define GPIO_PUPDR_PUPD7_Msk             (0x3U << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk                  
+#define GPIO_PUPDR_PUPD7_0               (0x1U << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1               (0x2U << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos             (16U)                                 
+#define GPIO_PUPDR_PUPD8_Msk             (0x3U << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk                  
+#define GPIO_PUPDR_PUPD8_0               (0x1U << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1               (0x2U << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos             (18U)                                 
+#define GPIO_PUPDR_PUPD9_Msk             (0x3U << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk                  
+#define GPIO_PUPDR_PUPD9_0               (0x1U << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1               (0x2U << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos            (20U)                                 
+#define GPIO_PUPDR_PUPD10_Msk            (0x3U << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk                 
+#define GPIO_PUPDR_PUPD10_0              (0x1U << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1              (0x2U << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos            (22U)                                 
+#define GPIO_PUPDR_PUPD11_Msk            (0x3U << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk                 
+#define GPIO_PUPDR_PUPD11_0              (0x1U << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1              (0x2U << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos            (24U)                                 
+#define GPIO_PUPDR_PUPD12_Msk            (0x3U << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk                 
+#define GPIO_PUPDR_PUPD12_0              (0x1U << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1              (0x2U << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos            (26U)                                 
+#define GPIO_PUPDR_PUPD13_Msk            (0x3U << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk                 
+#define GPIO_PUPDR_PUPD13_0              (0x1U << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1              (0x2U << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos            (28U)                                 
+#define GPIO_PUPDR_PUPD14_Msk            (0x3U << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk                 
+#define GPIO_PUPDR_PUPD14_0              (0x1U << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1              (0x2U << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos            (30U)                                 
+#define GPIO_PUPDR_PUPD15_Msk            (0x3U << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk                 
+#define GPIO_PUPDR_PUPD15_0              (0x1U << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1              (0x2U << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos                 (0U)                                  
+#define GPIO_IDR_ID0_Msk                 (0x1U << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */
+#define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk                      
+#define GPIO_IDR_ID1_Pos                 (1U)                                  
+#define GPIO_IDR_ID1_Msk                 (0x1U << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */
+#define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk                      
+#define GPIO_IDR_ID2_Pos                 (2U)                                  
+#define GPIO_IDR_ID2_Msk                 (0x1U << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */
+#define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk                      
+#define GPIO_IDR_ID3_Pos                 (3U)                                  
+#define GPIO_IDR_ID3_Msk                 (0x1U << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */
+#define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk                      
+#define GPIO_IDR_ID4_Pos                 (4U)                                  
+#define GPIO_IDR_ID4_Msk                 (0x1U << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */
+#define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk                      
+#define GPIO_IDR_ID5_Pos                 (5U)                                  
+#define GPIO_IDR_ID5_Msk                 (0x1U << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */
+#define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk                      
+#define GPIO_IDR_ID6_Pos                 (6U)                                  
+#define GPIO_IDR_ID6_Msk                 (0x1U << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */
+#define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk                      
+#define GPIO_IDR_ID7_Pos                 (7U)                                  
+#define GPIO_IDR_ID7_Msk                 (0x1U << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */
+#define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk                      
+#define GPIO_IDR_ID8_Pos                 (8U)                                  
+#define GPIO_IDR_ID8_Msk                 (0x1U << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */
+#define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk                      
+#define GPIO_IDR_ID9_Pos                 (9U)                                  
+#define GPIO_IDR_ID9_Msk                 (0x1U << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */
+#define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk                      
+#define GPIO_IDR_ID10_Pos                (10U)                                 
+#define GPIO_IDR_ID10_Msk                (0x1U << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */
+#define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk                     
+#define GPIO_IDR_ID11_Pos                (11U)                                 
+#define GPIO_IDR_ID11_Msk                (0x1U << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */
+#define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk                     
+#define GPIO_IDR_ID12_Pos                (12U)                                 
+#define GPIO_IDR_ID12_Msk                (0x1U << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */
+#define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk                     
+#define GPIO_IDR_ID13_Pos                (13U)                                 
+#define GPIO_IDR_ID13_Msk                (0x1U << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */
+#define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk                     
+#define GPIO_IDR_ID14_Pos                (14U)                                 
+#define GPIO_IDR_ID14_Msk                (0x1U << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */
+#define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk                     
+#define GPIO_IDR_ID15_Pos                (15U)                                 
+#define GPIO_IDR_ID15_Msk                (0x1U << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */
+#define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk                     
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos                 (0U)                                  
+#define GPIO_ODR_OD0_Msk                 (0x1U << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */
+#define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk                      
+#define GPIO_ODR_OD1_Pos                 (1U)                                  
+#define GPIO_ODR_OD1_Msk                 (0x1U << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */
+#define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk                      
+#define GPIO_ODR_OD2_Pos                 (2U)                                  
+#define GPIO_ODR_OD2_Msk                 (0x1U << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */
+#define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk                      
+#define GPIO_ODR_OD3_Pos                 (3U)                                  
+#define GPIO_ODR_OD3_Msk                 (0x1U << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */
+#define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk                      
+#define GPIO_ODR_OD4_Pos                 (4U)                                  
+#define GPIO_ODR_OD4_Msk                 (0x1U << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */
+#define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk                      
+#define GPIO_ODR_OD5_Pos                 (5U)                                  
+#define GPIO_ODR_OD5_Msk                 (0x1U << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */
+#define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk                      
+#define GPIO_ODR_OD6_Pos                 (6U)                                  
+#define GPIO_ODR_OD6_Msk                 (0x1U << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */
+#define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk                      
+#define GPIO_ODR_OD7_Pos                 (7U)                                  
+#define GPIO_ODR_OD7_Msk                 (0x1U << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */
+#define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk                      
+#define GPIO_ODR_OD8_Pos                 (8U)                                  
+#define GPIO_ODR_OD8_Msk                 (0x1U << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */
+#define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk                      
+#define GPIO_ODR_OD9_Pos                 (9U)                                  
+#define GPIO_ODR_OD9_Msk                 (0x1U << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */
+#define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk                      
+#define GPIO_ODR_OD10_Pos                (10U)                                 
+#define GPIO_ODR_OD10_Msk                (0x1U << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */
+#define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk                     
+#define GPIO_ODR_OD11_Pos                (11U)                                 
+#define GPIO_ODR_OD11_Msk                (0x1U << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */
+#define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk                     
+#define GPIO_ODR_OD12_Pos                (12U)                                 
+#define GPIO_ODR_OD12_Msk                (0x1U << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */
+#define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk                     
+#define GPIO_ODR_OD13_Pos                (13U)                                 
+#define GPIO_ODR_OD13_Msk                (0x1U << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */
+#define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk                     
+#define GPIO_ODR_OD14_Pos                (14U)                                 
+#define GPIO_ODR_OD14_Msk                (0x1U << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */
+#define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk                     
+#define GPIO_ODR_OD15_Pos                (15U)                                 
+#define GPIO_ODR_OD15_Msk                (0x1U << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */
+#define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk                     
+/* Legacy defines */
+#define GPIO_ODR_ODR_0                       GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1                       GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2                       GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3                       GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4                       GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5                       GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6                       GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7                       GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8                       GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9                       GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10                      GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11                      GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12                      GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13                      GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14                      GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15                      GPIO_ODR_OD15
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos                (0U)                                  
+#define GPIO_BSRR_BS0_Msk                (0x1U << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk                     
+#define GPIO_BSRR_BS1_Pos                (1U)                                  
+#define GPIO_BSRR_BS1_Msk                (0x1U << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk                     
+#define GPIO_BSRR_BS2_Pos                (2U)                                  
+#define GPIO_BSRR_BS2_Msk                (0x1U << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk                     
+#define GPIO_BSRR_BS3_Pos                (3U)                                  
+#define GPIO_BSRR_BS3_Msk                (0x1U << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk                     
+#define GPIO_BSRR_BS4_Pos                (4U)                                  
+#define GPIO_BSRR_BS4_Msk                (0x1U << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk                     
+#define GPIO_BSRR_BS5_Pos                (5U)                                  
+#define GPIO_BSRR_BS5_Msk                (0x1U << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk                     
+#define GPIO_BSRR_BS6_Pos                (6U)                                  
+#define GPIO_BSRR_BS6_Msk                (0x1U << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk                     
+#define GPIO_BSRR_BS7_Pos                (7U)                                  
+#define GPIO_BSRR_BS7_Msk                (0x1U << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk                     
+#define GPIO_BSRR_BS8_Pos                (8U)                                  
+#define GPIO_BSRR_BS8_Msk                (0x1U << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk                     
+#define GPIO_BSRR_BS9_Pos                (9U)                                  
+#define GPIO_BSRR_BS9_Msk                (0x1U << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk                     
+#define GPIO_BSRR_BS10_Pos               (10U)                                 
+#define GPIO_BSRR_BS10_Msk               (0x1U << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk                    
+#define GPIO_BSRR_BS11_Pos               (11U)                                 
+#define GPIO_BSRR_BS11_Msk               (0x1U << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk                    
+#define GPIO_BSRR_BS12_Pos               (12U)                                 
+#define GPIO_BSRR_BS12_Msk               (0x1U << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk                    
+#define GPIO_BSRR_BS13_Pos               (13U)                                 
+#define GPIO_BSRR_BS13_Msk               (0x1U << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk                    
+#define GPIO_BSRR_BS14_Pos               (14U)                                 
+#define GPIO_BSRR_BS14_Msk               (0x1U << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk                    
+#define GPIO_BSRR_BS15_Pos               (15U)                                 
+#define GPIO_BSRR_BS15_Msk               (0x1U << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk                    
+#define GPIO_BSRR_BR0_Pos                (16U)                                 
+#define GPIO_BSRR_BR0_Msk                (0x1U << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk                     
+#define GPIO_BSRR_BR1_Pos                (17U)                                 
+#define GPIO_BSRR_BR1_Msk                (0x1U << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk                     
+#define GPIO_BSRR_BR2_Pos                (18U)                                 
+#define GPIO_BSRR_BR2_Msk                (0x1U << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk                     
+#define GPIO_BSRR_BR3_Pos                (19U)                                 
+#define GPIO_BSRR_BR3_Msk                (0x1U << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk                     
+#define GPIO_BSRR_BR4_Pos                (20U)                                 
+#define GPIO_BSRR_BR4_Msk                (0x1U << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk                     
+#define GPIO_BSRR_BR5_Pos                (21U)                                 
+#define GPIO_BSRR_BR5_Msk                (0x1U << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk                     
+#define GPIO_BSRR_BR6_Pos                (22U)                                 
+#define GPIO_BSRR_BR6_Msk                (0x1U << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk                     
+#define GPIO_BSRR_BR7_Pos                (23U)                                 
+#define GPIO_BSRR_BR7_Msk                (0x1U << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk                     
+#define GPIO_BSRR_BR8_Pos                (24U)                                 
+#define GPIO_BSRR_BR8_Msk                (0x1U << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk                     
+#define GPIO_BSRR_BR9_Pos                (25U)                                 
+#define GPIO_BSRR_BR9_Msk                (0x1U << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk                     
+#define GPIO_BSRR_BR10_Pos               (26U)                                 
+#define GPIO_BSRR_BR10_Msk               (0x1U << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk                    
+#define GPIO_BSRR_BR11_Pos               (27U)                                 
+#define GPIO_BSRR_BR11_Msk               (0x1U << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk                    
+#define GPIO_BSRR_BR12_Pos               (28U)                                 
+#define GPIO_BSRR_BR12_Msk               (0x1U << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk                    
+#define GPIO_BSRR_BR13_Pos               (29U)                                 
+#define GPIO_BSRR_BR13_Msk               (0x1U << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk                    
+#define GPIO_BSRR_BR14_Pos               (30U)                                 
+#define GPIO_BSRR_BR14_Msk               (0x1U << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk                    
+#define GPIO_BSRR_BR15_Pos               (31U)                                 
+#define GPIO_BSRR_BR15_Msk               (0x1U << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk                    
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos               (0U)                                  
+#define GPIO_LCKR_LCK0_Msk               (0x1U << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk                    
+#define GPIO_LCKR_LCK1_Pos               (1U)                                  
+#define GPIO_LCKR_LCK1_Msk               (0x1U << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk                    
+#define GPIO_LCKR_LCK2_Pos               (2U)                                  
+#define GPIO_LCKR_LCK2_Msk               (0x1U << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk                    
+#define GPIO_LCKR_LCK3_Pos               (3U)                                  
+#define GPIO_LCKR_LCK3_Msk               (0x1U << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk                    
+#define GPIO_LCKR_LCK4_Pos               (4U)                                  
+#define GPIO_LCKR_LCK4_Msk               (0x1U << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk                    
+#define GPIO_LCKR_LCK5_Pos               (5U)                                  
+#define GPIO_LCKR_LCK5_Msk               (0x1U << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk                    
+#define GPIO_LCKR_LCK6_Pos               (6U)                                  
+#define GPIO_LCKR_LCK6_Msk               (0x1U << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk                    
+#define GPIO_LCKR_LCK7_Pos               (7U)                                  
+#define GPIO_LCKR_LCK7_Msk               (0x1U << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk                    
+#define GPIO_LCKR_LCK8_Pos               (8U)                                  
+#define GPIO_LCKR_LCK8_Msk               (0x1U << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk                    
+#define GPIO_LCKR_LCK9_Pos               (9U)                                  
+#define GPIO_LCKR_LCK9_Msk               (0x1U << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk                    
+#define GPIO_LCKR_LCK10_Pos              (10U)                                 
+#define GPIO_LCKR_LCK10_Msk              (0x1U << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk                   
+#define GPIO_LCKR_LCK11_Pos              (11U)                                 
+#define GPIO_LCKR_LCK11_Msk              (0x1U << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk                   
+#define GPIO_LCKR_LCK12_Pos              (12U)                                 
+#define GPIO_LCKR_LCK12_Msk              (0x1U << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk                   
+#define GPIO_LCKR_LCK13_Pos              (13U)                                 
+#define GPIO_LCKR_LCK13_Msk              (0x1U << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk                   
+#define GPIO_LCKR_LCK14_Pos              (14U)                                 
+#define GPIO_LCKR_LCK14_Msk              (0x1U << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk                   
+#define GPIO_LCKR_LCK15_Pos              (15U)                                 
+#define GPIO_LCKR_LCK15_Msk              (0x1U << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk                   
+#define GPIO_LCKR_LCKK_Pos               (16U)                                 
+#define GPIO_LCKR_LCKK_Msk               (0x1U << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk                    
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos             (0U)                                  
+#define GPIO_AFRL_AFSEL0_Msk             (0xFU << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                  
+#define GPIO_AFRL_AFSEL0_0               (0x1U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1               (0x2U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2               (0x4U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3               (0x8U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos             (4U)                                  
+#define GPIO_AFRL_AFSEL1_Msk             (0xFU << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                  
+#define GPIO_AFRL_AFSEL1_0               (0x1U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1               (0x2U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2               (0x4U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3               (0x8U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos             (8U)                                  
+#define GPIO_AFRL_AFSEL2_Msk             (0xFU << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                  
+#define GPIO_AFRL_AFSEL2_0               (0x1U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1               (0x2U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2               (0x4U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3               (0x8U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos             (12U)                                 
+#define GPIO_AFRL_AFSEL3_Msk             (0xFU << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                  
+#define GPIO_AFRL_AFSEL3_0               (0x1U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1               (0x2U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2               (0x4U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3               (0x8U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos             (16U)                                 
+#define GPIO_AFRL_AFSEL4_Msk             (0xFU << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                  
+#define GPIO_AFRL_AFSEL4_0               (0x1U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1               (0x2U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2               (0x4U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3               (0x8U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos             (20U)                                 
+#define GPIO_AFRL_AFSEL5_Msk             (0xFU << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                  
+#define GPIO_AFRL_AFSEL5_0               (0x1U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1               (0x2U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2               (0x4U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3               (0x8U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos             (24U)                                 
+#define GPIO_AFRL_AFSEL6_Msk             (0xFU << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                  
+#define GPIO_AFRL_AFSEL6_0               (0x1U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1               (0x2U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2               (0x4U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3               (0x8U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos             (28U)                                 
+#define GPIO_AFRL_AFSEL7_Msk             (0xFU << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                  
+#define GPIO_AFRL_AFSEL7_0               (0x1U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1               (0x2U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2               (0x4U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3               (0x8U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0                    GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1                    GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2                    GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3                    GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0                    GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1                    GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2                    GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3                    GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0                    GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1                    GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2                    GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3                    GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0                    GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1                    GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2                    GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3                    GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0                    GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1                    GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2                    GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3                    GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0                    GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1                    GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2                    GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3                    GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0                    GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1                    GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2                    GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3                    GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0                    GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1                    GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2                    GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3                    GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos             (0U)                                  
+#define GPIO_AFRH_AFSEL8_Msk             (0xFU << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                  
+#define GPIO_AFRH_AFSEL8_0               (0x1U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1               (0x2U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2               (0x4U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3               (0x8U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos             (4U)                                  
+#define GPIO_AFRH_AFSEL9_Msk             (0xFU << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                  
+#define GPIO_AFRH_AFSEL9_0               (0x1U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1               (0x2U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2               (0x4U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3               (0x8U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos            (8U)                                  
+#define GPIO_AFRH_AFSEL10_Msk            (0xFU << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk                 
+#define GPIO_AFRH_AFSEL10_0              (0x1U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1              (0x2U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2              (0x4U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3              (0x8U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos            (12U)                                 
+#define GPIO_AFRH_AFSEL11_Msk            (0xFU << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk                 
+#define GPIO_AFRH_AFSEL11_0              (0x1U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1              (0x2U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2              (0x4U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3              (0x8U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos            (16U)                                 
+#define GPIO_AFRH_AFSEL12_Msk            (0xFU << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk                 
+#define GPIO_AFRH_AFSEL12_0              (0x1U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1              (0x2U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2              (0x4U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3              (0x8U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos            (20U)                                 
+#define GPIO_AFRH_AFSEL13_Msk            (0xFU << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk                 
+#define GPIO_AFRH_AFSEL13_0              (0x1U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1              (0x2U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2              (0x4U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3              (0x8U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos            (24U)                                 
+#define GPIO_AFRH_AFSEL14_Msk            (0xFU << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk                 
+#define GPIO_AFRH_AFSEL14_0              (0x1U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1              (0x2U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2              (0x4U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3              (0x8U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos            (28U)                                 
+#define GPIO_AFRH_AFSEL15_Msk            (0xFU << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk                 
+#define GPIO_AFRH_AFSEL15_0              (0x1U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1              (0x2U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2              (0x4U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3              (0x8U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0                    GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1                    GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2                    GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3                    GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0                    GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1                    GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2                    GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3                    GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0                    GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1                    GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2                    GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3                    GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0                    GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1                    GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2                    GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3                    GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0                    GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1                    GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2                    GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3                    GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0                    GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1                    GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2                    GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3                    GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0                    GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1                    GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2                    GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3                    GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0                    GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1                    GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2                    GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3                    GPIO_AFRH_AFSEL15_3
+
+/******************  Bits definition for GPIO_BRR register  ******************/
+#define GPIO_BRR_BR0_Pos                 (0U)                                  
+#define GPIO_BRR_BR0_Msk                 (0x1U << GPIO_BRR_BR0_Pos)            /*!< 0x00000001 */
+#define GPIO_BRR_BR0                     GPIO_BRR_BR0_Msk                      
+#define GPIO_BRR_BR1_Pos                 (1U)                                  
+#define GPIO_BRR_BR1_Msk                 (0x1U << GPIO_BRR_BR1_Pos)            /*!< 0x00000002 */
+#define GPIO_BRR_BR1                     GPIO_BRR_BR1_Msk                      
+#define GPIO_BRR_BR2_Pos                 (2U)                                  
+#define GPIO_BRR_BR2_Msk                 (0x1U << GPIO_BRR_BR2_Pos)            /*!< 0x00000004 */
+#define GPIO_BRR_BR2                     GPIO_BRR_BR2_Msk                      
+#define GPIO_BRR_BR3_Pos                 (3U)                                  
+#define GPIO_BRR_BR3_Msk                 (0x1U << GPIO_BRR_BR3_Pos)            /*!< 0x00000008 */
+#define GPIO_BRR_BR3                     GPIO_BRR_BR3_Msk                      
+#define GPIO_BRR_BR4_Pos                 (4U)                                  
+#define GPIO_BRR_BR4_Msk                 (0x1U << GPIO_BRR_BR4_Pos)            /*!< 0x00000010 */
+#define GPIO_BRR_BR4                     GPIO_BRR_BR4_Msk                      
+#define GPIO_BRR_BR5_Pos                 (5U)                                  
+#define GPIO_BRR_BR5_Msk                 (0x1U << GPIO_BRR_BR5_Pos)            /*!< 0x00000020 */
+#define GPIO_BRR_BR5                     GPIO_BRR_BR5_Msk                      
+#define GPIO_BRR_BR6_Pos                 (6U)                                  
+#define GPIO_BRR_BR6_Msk                 (0x1U << GPIO_BRR_BR6_Pos)            /*!< 0x00000040 */
+#define GPIO_BRR_BR6                     GPIO_BRR_BR6_Msk                      
+#define GPIO_BRR_BR7_Pos                 (7U)                                  
+#define GPIO_BRR_BR7_Msk                 (0x1U << GPIO_BRR_BR7_Pos)            /*!< 0x00000080 */
+#define GPIO_BRR_BR7                     GPIO_BRR_BR7_Msk                      
+#define GPIO_BRR_BR8_Pos                 (8U)                                  
+#define GPIO_BRR_BR8_Msk                 (0x1U << GPIO_BRR_BR8_Pos)            /*!< 0x00000100 */
+#define GPIO_BRR_BR8                     GPIO_BRR_BR8_Msk                      
+#define GPIO_BRR_BR9_Pos                 (9U)                                  
+#define GPIO_BRR_BR9_Msk                 (0x1U << GPIO_BRR_BR9_Pos)            /*!< 0x00000200 */
+#define GPIO_BRR_BR9                     GPIO_BRR_BR9_Msk                      
+#define GPIO_BRR_BR10_Pos                (10U)                                 
+#define GPIO_BRR_BR10_Msk                (0x1U << GPIO_BRR_BR10_Pos)           /*!< 0x00000400 */
+#define GPIO_BRR_BR10                    GPIO_BRR_BR10_Msk                     
+#define GPIO_BRR_BR11_Pos                (11U)                                 
+#define GPIO_BRR_BR11_Msk                (0x1U << GPIO_BRR_BR11_Pos)           /*!< 0x00000800 */
+#define GPIO_BRR_BR11                    GPIO_BRR_BR11_Msk                     
+#define GPIO_BRR_BR12_Pos                (12U)                                 
+#define GPIO_BRR_BR12_Msk                (0x1U << GPIO_BRR_BR12_Pos)           /*!< 0x00001000 */
+#define GPIO_BRR_BR12                    GPIO_BRR_BR12_Msk                     
+#define GPIO_BRR_BR13_Pos                (13U)                                 
+#define GPIO_BRR_BR13_Msk                (0x1U << GPIO_BRR_BR13_Pos)           /*!< 0x00002000 */
+#define GPIO_BRR_BR13                    GPIO_BRR_BR13_Msk                     
+#define GPIO_BRR_BR14_Pos                (14U)                                 
+#define GPIO_BRR_BR14_Msk                (0x1U << GPIO_BRR_BR14_Pos)           /*!< 0x00004000 */
+#define GPIO_BRR_BR14                    GPIO_BRR_BR14_Msk                     
+#define GPIO_BRR_BR15_Pos                (15U)                                 
+#define GPIO_BRR_BR15_Msk                (0x1U << GPIO_BRR_BR15_Pos)           /*!< 0x00008000 */
+#define GPIO_BRR_BR15                    GPIO_BRR_BR15_Msk                     
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    HASH                                    */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for HASH_CR register  ********************/
+#define HASH_CR_INIT_Pos          (2U)                                         
+#define HASH_CR_INIT_Msk          (0x1U << HASH_CR_INIT_Pos)                   /*!< 0x00000004 */
+#define HASH_CR_INIT              HASH_CR_INIT_Msk                             
+#define HASH_CR_DMAE_Pos          (3U)                                         
+#define HASH_CR_DMAE_Msk          (0x1U << HASH_CR_DMAE_Pos)                   /*!< 0x00000008 */
+#define HASH_CR_DMAE              HASH_CR_DMAE_Msk                             
+#define HASH_CR_DATATYPE_Pos      (4U)                                         
+#define HASH_CR_DATATYPE_Msk      (0x3U << HASH_CR_DATATYPE_Pos)               /*!< 0x00000030 */
+#define HASH_CR_DATATYPE          HASH_CR_DATATYPE_Msk                         
+#define HASH_CR_DATATYPE_0        (0x1U << HASH_CR_DATATYPE_Pos)               /*!< 0x00000010 */
+#define HASH_CR_DATATYPE_1        (0x2U << HASH_CR_DATATYPE_Pos)               /*!< 0x00000020 */
+#define HASH_CR_MODE_Pos          (6U)                                         
+#define HASH_CR_MODE_Msk          (0x1U << HASH_CR_MODE_Pos)                   /*!< 0x00000040 */
+#define HASH_CR_MODE              HASH_CR_MODE_Msk                             
+#define HASH_CR_ALGO_Pos          (7U)                                         
+#define HASH_CR_ALGO_Msk          (0x801U << HASH_CR_ALGO_Pos)                 /*!< 0x00040080 */
+#define HASH_CR_ALGO              HASH_CR_ALGO_Msk                             
+#define HASH_CR_ALGO_0            (0x001U << HASH_CR_ALGO_Pos)                 /*!< 0x00000080 */
+#define HASH_CR_ALGO_1            (0x800U << HASH_CR_ALGO_Pos)                 /*!< 0x00040000 */
+#define HASH_CR_NBW_Pos           (8U)                                         
+#define HASH_CR_NBW_Msk           (0xFU << HASH_CR_NBW_Pos)                    /*!< 0x00000F00 */
+#define HASH_CR_NBW               HASH_CR_NBW_Msk                              
+#define HASH_CR_NBW_0             (0x1U << HASH_CR_NBW_Pos)                    /*!< 0x00000100 */
+#define HASH_CR_NBW_1             (0x2U << HASH_CR_NBW_Pos)                    /*!< 0x00000200 */
+#define HASH_CR_NBW_2             (0x4U << HASH_CR_NBW_Pos)                    /*!< 0x00000400 */
+#define HASH_CR_NBW_3             (0x8U << HASH_CR_NBW_Pos)                    /*!< 0x00000800 */
+#define HASH_CR_DINNE_Pos         (12U)                                        
+#define HASH_CR_DINNE_Msk         (0x1U << HASH_CR_DINNE_Pos)                  /*!< 0x00001000 */
+#define HASH_CR_DINNE             HASH_CR_DINNE_Msk                            
+#define HASH_CR_MDMAT_Pos         (13U)                                        
+#define HASH_CR_MDMAT_Msk         (0x1U << HASH_CR_MDMAT_Pos)                  /*!< 0x00002000 */
+#define HASH_CR_MDMAT             HASH_CR_MDMAT_Msk                            
+#define HASH_CR_LKEY_Pos          (16U)                                        
+#define HASH_CR_LKEY_Msk          (0x1U << HASH_CR_LKEY_Pos)                   /*!< 0x00010000 */
+#define HASH_CR_LKEY              HASH_CR_LKEY_Msk                             
+
+/******************  Bits definition for HASH_STR register  *******************/
+#define HASH_STR_NBLW_Pos         (0U)                                         
+#define HASH_STR_NBLW_Msk         (0x1FU << HASH_STR_NBLW_Pos)                 /*!< 0x0000001F */
+#define HASH_STR_NBLW             HASH_STR_NBLW_Msk                            
+#define HASH_STR_NBLW_0           (0x01U << HASH_STR_NBLW_Pos)                 /*!< 0x00000001 */
+#define HASH_STR_NBLW_1           (0x02U << HASH_STR_NBLW_Pos)                 /*!< 0x00000002 */
+#define HASH_STR_NBLW_2           (0x04U << HASH_STR_NBLW_Pos)                 /*!< 0x00000004 */
+#define HASH_STR_NBLW_3           (0x08U << HASH_STR_NBLW_Pos)                 /*!< 0x00000008 */
+#define HASH_STR_NBLW_4           (0x10U << HASH_STR_NBLW_Pos)                 /*!< 0x00000010 */
+#define HASH_STR_DCAL_Pos         (8U)                                         
+#define HASH_STR_DCAL_Msk         (0x1U << HASH_STR_DCAL_Pos)                  /*!< 0x00000100 */
+#define HASH_STR_DCAL             HASH_STR_DCAL_Msk                            
+/* Aliases for HASH_STR register */
+#define HASH_STR_NBW                         HASH_STR_NBLW
+#define HASH_STR_NBW_0                       HASH_STR_NBLW_0
+#define HASH_STR_NBW_1                       HASH_STR_NBLW_1
+#define HASH_STR_NBW_2                       HASH_STR_NBLW_2
+#define HASH_STR_NBW_3                       HASH_STR_NBLW_3
+#define HASH_STR_NBW_4                       HASH_STR_NBLW_4
+
+/******************  Bits definition for HASH_IMR register  *******************/
+#define HASH_IMR_DINIE_Pos        (0U)                                         
+#define HASH_IMR_DINIE_Msk        (0x1U << HASH_IMR_DINIE_Pos)                 /*!< 0x00000001 */
+#define HASH_IMR_DINIE            HASH_IMR_DINIE_Msk                           
+#define HASH_IMR_DCIE_Pos         (1U)                                         
+#define HASH_IMR_DCIE_Msk         (0x1U << HASH_IMR_DCIE_Pos)                  /*!< 0x00000002 */
+#define HASH_IMR_DCIE             HASH_IMR_DCIE_Msk                            
+/* Aliases for HASH_IMR register */
+#define HASH_IMR_DINIM                       HASH_IMR_DINIE
+#define HASH_IMR_DCIM                        HASH_IMR_DCIE
+
+/******************  Bits definition for HASH_SR register  ********************/
+#define HASH_SR_DINIS_Pos         (0U)                                         
+#define HASH_SR_DINIS_Msk         (0x1U << HASH_SR_DINIS_Pos)                  /*!< 0x00000001 */
+#define HASH_SR_DINIS             HASH_SR_DINIS_Msk                            
+#define HASH_SR_DCIS_Pos          (1U)                                         
+#define HASH_SR_DCIS_Msk          (0x1U << HASH_SR_DCIS_Pos)                   /*!< 0x00000002 */
+#define HASH_SR_DCIS              HASH_SR_DCIS_Msk                             
+#define HASH_SR_DMAS_Pos          (2U)                                         
+#define HASH_SR_DMAS_Msk          (0x1U << HASH_SR_DMAS_Pos)                   /*!< 0x00000004 */
+#define HASH_SR_DMAS              HASH_SR_DMAS_Msk                             
+#define HASH_SR_BUSY_Pos          (3U)                                         
+#define HASH_SR_BUSY_Msk          (0x1U << HASH_SR_BUSY_Pos)                   /*!< 0x00000008 */
+#define HASH_SR_BUSY              HASH_SR_BUSY_Msk                             
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  ********************/
+#define I2C_CR1_PE_Pos            (0U)                                         
+#define I2C_CR1_PE_Msk            (0x1U << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */
+#define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */
+#define I2C_CR1_SMBUS_Pos         (1U)                                         
+#define I2C_CR1_SMBUS_Msk         (0x1U << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */
+#define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */
+#define I2C_CR1_SMBTYPE_Pos       (3U)                                         
+#define I2C_CR1_SMBTYPE_Msk       (0x1U << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */
+#define I2C_CR1_ENARP_Pos         (4U)                                         
+#define I2C_CR1_ENARP_Msk         (0x1U << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */
+#define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */
+#define I2C_CR1_ENPEC_Pos         (5U)                                         
+#define I2C_CR1_ENPEC_Msk         (0x1U << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */
+#define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */
+#define I2C_CR1_ENGC_Pos          (6U)                                         
+#define I2C_CR1_ENGC_Msk          (0x1U << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */
+#define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */
+#define I2C_CR1_NOSTRETCH_Pos     (7U)                                         
+#define I2C_CR1_NOSTRETCH_Msk     (0x1U << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */
+#define I2C_CR1_START_Pos         (8U)                                         
+#define I2C_CR1_START_Msk         (0x1U << I2C_CR1_START_Pos)                  /*!< 0x00000100 */
+#define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */
+#define I2C_CR1_STOP_Pos          (9U)                                         
+#define I2C_CR1_STOP_Msk          (0x1U << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */
+#define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */
+#define I2C_CR1_ACK_Pos           (10U)                                        
+#define I2C_CR1_ACK_Msk           (0x1U << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */
+#define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */
+#define I2C_CR1_POS_Pos           (11U)                                        
+#define I2C_CR1_POS_Msk           (0x1U << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */
+#define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos           (12U)                                        
+#define I2C_CR1_PEC_Msk           (0x1U << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */
+#define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */
+#define I2C_CR1_ALERT_Pos         (13U)                                        
+#define I2C_CR1_ALERT_Msk         (0x1U << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */
+#define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */
+#define I2C_CR1_SWRST_Pos         (15U)                                        
+#define I2C_CR1_SWRST_Msk         (0x1U << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */
+#define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */
+
+/*******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_FREQ_Pos          (0U)                                         
+#define I2C_CR2_FREQ_Msk          (0x3FU << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */
+#define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define I2C_CR2_FREQ_0            (0x01U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1            (0x02U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2            (0x04U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3            (0x08U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4            (0x10U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5            (0x20U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos       (8U)                                         
+#define I2C_CR2_ITERREN_Msk       (0x1U << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */
+#define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */
+#define I2C_CR2_ITEVTEN_Pos       (9U)                                         
+#define I2C_CR2_ITEVTEN_Msk       (0x1U << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */
+#define I2C_CR2_ITBUFEN_Pos       (10U)                                        
+#define I2C_CR2_ITBUFEN_Msk       (0x1U << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos         (11U)                                        
+#define I2C_CR2_DMAEN_Msk         (0x1U << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */
+#define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */
+#define I2C_CR2_LAST_Pos          (12U)                                        
+#define I2C_CR2_LAST_Msk          (0x1U << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */
+#define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */
+
+/*******************  Bit definition for I2C_OAR1 register  *******************/
+#define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */
+#define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos         (0U)                                         
+#define I2C_OAR1_ADD0_Msk         (0x1U << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */
+#define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos         (1U)                                         
+#define I2C_OAR1_ADD1_Msk         (0x1U << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */
+#define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos         (2U)                                         
+#define I2C_OAR1_ADD2_Msk         (0x1U << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */
+#define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos         (3U)                                         
+#define I2C_OAR1_ADD3_Msk         (0x1U << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */
+#define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos         (4U)                                         
+#define I2C_OAR1_ADD4_Msk         (0x1U << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */
+#define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos         (5U)                                         
+#define I2C_OAR1_ADD5_Msk         (0x1U << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */
+#define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos         (6U)                                         
+#define I2C_OAR1_ADD6_Msk         (0x1U << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */
+#define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos         (7U)                                         
+#define I2C_OAR1_ADD7_Msk         (0x1U << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */
+#define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos         (8U)                                         
+#define I2C_OAR1_ADD8_Msk         (0x1U << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */
+#define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos         (9U)                                         
+#define I2C_OAR1_ADD9_Msk         (0x1U << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */
+#define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos      (15U)                                        
+#define I2C_OAR1_ADDMODE_Msk      (0x1U << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OAR2 register  *******************/
+#define I2C_OAR2_ENDUAL_Pos       (0U)                                         
+#define I2C_OAR2_ENDUAL_Msk       (0x1U << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos         (1U)                                         
+#define I2C_OAR2_ADD2_Msk         (0x7FU << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */
+#define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */
+
+/********************  Bit definition for I2C_DR register  ********************/
+#define I2C_DR_DR_Pos             (0U)                                         
+#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */
+#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */
+
+/*******************  Bit definition for I2C_SR1 register  ********************/
+#define I2C_SR1_SB_Pos            (0U)                                         
+#define I2C_SR1_SB_Msk            (0x1U << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */
+#define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */
+#define I2C_SR1_ADDR_Pos          (1U)                                         
+#define I2C_SR1_ADDR_Msk          (0x1U << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */
+#define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos           (2U)                                         
+#define I2C_SR1_BTF_Msk           (0x1U << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */
+#define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */
+#define I2C_SR1_ADD10_Pos         (3U)                                         
+#define I2C_SR1_ADD10_Msk         (0x1U << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */
+#define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */
+#define I2C_SR1_STOPF_Pos         (4U)                                         
+#define I2C_SR1_STOPF_Msk         (0x1U << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */
+#define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */
+#define I2C_SR1_RXNE_Pos          (6U)                                         
+#define I2C_SR1_RXNE_Msk          (0x1U << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */
+#define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */
+#define I2C_SR1_TXE_Pos           (7U)                                         
+#define I2C_SR1_TXE_Msk           (0x1U << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */
+#define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */
+#define I2C_SR1_BERR_Pos          (8U)                                         
+#define I2C_SR1_BERR_Msk          (0x1U << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */
+#define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */
+#define I2C_SR1_ARLO_Pos          (9U)                                         
+#define I2C_SR1_ARLO_Msk          (0x1U << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */
+#define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */
+#define I2C_SR1_AF_Pos            (10U)                                        
+#define I2C_SR1_AF_Msk            (0x1U << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */
+#define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */
+#define I2C_SR1_OVR_Pos           (11U)                                        
+#define I2C_SR1_OVR_Msk           (0x1U << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */
+#define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */
+#define I2C_SR1_PECERR_Pos        (12U)                                        
+#define I2C_SR1_PECERR_Msk        (0x1U << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */
+#define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */
+#define I2C_SR1_TIMEOUT_Pos       (14U)                                        
+#define I2C_SR1_TIMEOUT_Msk       (0x1U << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */
+#define I2C_SR1_SMBALERT_Pos      (15U)                                        
+#define I2C_SR1_SMBALERT_Msk      (0x1U << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */
+
+/*******************  Bit definition for I2C_SR2 register  ********************/
+#define I2C_SR2_MSL_Pos           (0U)                                         
+#define I2C_SR2_MSL_Msk           (0x1U << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */
+#define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */
+#define I2C_SR2_BUSY_Pos          (1U)                                         
+#define I2C_SR2_BUSY_Msk          (0x1U << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */
+#define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */
+#define I2C_SR2_TRA_Pos           (2U)                                         
+#define I2C_SR2_TRA_Msk           (0x1U << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */
+#define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */
+#define I2C_SR2_GENCALL_Pos       (4U)                                         
+#define I2C_SR2_GENCALL_Msk       (0x1U << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */
+#define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */
+#define I2C_SR2_SMBDEFAULT_Pos    (5U)                                         
+#define I2C_SR2_SMBDEFAULT_Msk    (0x1U << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */
+#define I2C_SR2_SMBHOST_Pos       (6U)                                         
+#define I2C_SR2_SMBHOST_Msk       (0x1U << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */
+#define I2C_SR2_DUALF_Pos         (7U)                                         
+#define I2C_SR2_DUALF_Msk         (0x1U << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */
+#define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */
+#define I2C_SR2_PEC_Pos           (8U)                                         
+#define I2C_SR2_PEC_Msk           (0xFFU << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */
+#define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */
+
+/*******************  Bit definition for I2C_CCR register  ********************/
+#define I2C_CCR_CCR_Pos           (0U)                                         
+#define I2C_CCR_CCR_Msk           (0xFFFU << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */
+#define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos          (14U)                                        
+#define I2C_CCR_DUTY_Msk          (0x1U << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */
+#define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */
+#define I2C_CCR_FS_Pos            (15U)                                        
+#define I2C_CCR_FS_Msk            (0x1U << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */
+#define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */
+
+/******************  Bit definition for I2C_TRISE register  *******************/
+#define I2C_TRISE_TRISE_Pos       (0U)                                         
+#define I2C_TRISE_TRISE_Msk       (0x3FU << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */
+#define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************  Bit definition for I2C_FLTR register  *******************/
+#define I2C_FLTR_DNF_Pos          (0U)                                         
+#define I2C_FLTR_DNF_Msk          (0xFU << I2C_FLTR_DNF_Pos)                   /*!< 0x0000000F */
+#define I2C_FLTR_DNF              I2C_FLTR_DNF_Msk                             /*!<Digital Noise Filter */
+#define I2C_FLTR_ANOFF_Pos        (4U)                                         
+#define I2C_FLTR_ANOFF_Msk        (0x1U << I2C_FLTR_ANOFF_Pos)                 /*!< 0x00000010 */
+#define I2C_FLTR_ANOFF            I2C_FLTR_ANOFF_Msk                           /*!<Analog Noise Filter OFF */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos     (0U)                                               
+#define IWDG_KR_KEY_Msk     (0xFFFFU << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */
+#define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos      (0U)                                               
+#define IWDG_PR_PR_Msk      (0x7U << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */
+#define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */
+#define IWDG_PR_PR_0        (0x1U << IWDG_PR_PR_Pos)                           /*!< 0x01 */
+#define IWDG_PR_PR_1        (0x2U << IWDG_PR_PR_Pos)                           /*!< 0x02 */
+#define IWDG_PR_PR_2        (0x4U << IWDG_PR_PR_Pos)                           /*!< 0x04 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos     (0U)                                               
+#define IWDG_RLR_RL_Msk     (0xFFFU << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */
+#define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos     (0U)                                               
+#define IWDG_SR_PVU_Msk     (0x1U << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */
+#define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */
+#define IWDG_SR_RVU_Pos     (1U)                                               
+#define IWDG_SR_RVU_Msk     (0x1U << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */
+#define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for PWR_CR register  ********************/
+#define PWR_CR_LPDS_Pos        (0U)                                            
+#define PWR_CR_LPDS_Msk        (0x1U << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */
+#define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */
+#define PWR_CR_PDDS_Pos        (1U)                                            
+#define PWR_CR_PDDS_Msk        (0x1U << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */
+#define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */
+#define PWR_CR_CWUF_Pos        (2U)                                            
+#define PWR_CR_CWUF_Msk        (0x1U << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */
+#define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */
+#define PWR_CR_CSBF_Pos        (3U)                                            
+#define PWR_CR_CSBF_Msk        (0x1U << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */
+#define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */
+#define PWR_CR_PVDE_Pos        (4U)                                            
+#define PWR_CR_PVDE_Msk        (0x1U << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */
+#define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */
+
+#define PWR_CR_PLS_Pos         (5U)                                            
+#define PWR_CR_PLS_Msk         (0x7U << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */
+#define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0           (0x1U << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */
+#define PWR_CR_PLS_1           (0x2U << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */
+#define PWR_CR_PLS_2           (0x4U << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos         (8U)                                            
+#define PWR_CR_DBP_Msk         (0x1U << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */
+#define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */
+#define PWR_CR_FPDS_Pos        (9U)                                            
+#define PWR_CR_FPDS_Msk        (0x1U << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */
+#define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */
+#define PWR_CR_LPLVDS_Pos      (10U)                                           
+#define PWR_CR_LPLVDS_Msk      (0x1U << PWR_CR_LPLVDS_Pos)                     /*!< 0x00000400 */
+#define PWR_CR_LPLVDS          PWR_CR_LPLVDS_Msk                               /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */
+#define PWR_CR_MRLVDS_Pos      (11U)                                           
+#define PWR_CR_MRLVDS_Msk      (0x1U << PWR_CR_MRLVDS_Pos)                     /*!< 0x00000800 */
+#define PWR_CR_MRLVDS          PWR_CR_MRLVDS_Msk                               /*!< Main regulator Low Voltage Scaling in Stop mode            */
+#define PWR_CR_ADCDC1_Pos      (13U)                                           
+#define PWR_CR_ADCDC1_Msk      (0x1U << PWR_CR_ADCDC1_Pos)                     /*!< 0x00002000 */
+#define PWR_CR_ADCDC1          PWR_CR_ADCDC1_Msk                               /*!< Refer to AN4073 on how to use this bit                     */ 
+#define PWR_CR_VOS_Pos         (14U)                                           
+#define PWR_CR_VOS_Msk         (0x3U << PWR_CR_VOS_Pos)                        /*!< 0x0000C000 */
+#define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
+#define PWR_CR_VOS_0           0x00004000U                                     /*!< Bit 0 */
+#define PWR_CR_VOS_1           0x00008000U                                     /*!< Bit 1 */
+#define PWR_CR_ODEN_Pos        (16U)                                           
+#define PWR_CR_ODEN_Msk        (0x1U << PWR_CR_ODEN_Pos)                       /*!< 0x00010000 */
+#define PWR_CR_ODEN            PWR_CR_ODEN_Msk                                 /*!< Over Drive enable                   */
+#define PWR_CR_ODSWEN_Pos      (17U)                                           
+#define PWR_CR_ODSWEN_Msk      (0x1U << PWR_CR_ODSWEN_Pos)                     /*!< 0x00020000 */
+#define PWR_CR_ODSWEN          PWR_CR_ODSWEN_Msk                               /*!< Over Drive switch enabled           */
+#define PWR_CR_UDEN_Pos        (18U)                                           
+#define PWR_CR_UDEN_Msk        (0x3U << PWR_CR_UDEN_Pos)                       /*!< 0x000C0000 */
+#define PWR_CR_UDEN            PWR_CR_UDEN_Msk                                 /*!< Under Drive enable in stop mode     */
+#define PWR_CR_UDEN_0          (0x1U << PWR_CR_UDEN_Pos)                       /*!< 0x00040000 */
+#define PWR_CR_UDEN_1          (0x2U << PWR_CR_UDEN_Pos)                       /*!< 0x00080000 */
+
+/* Legacy define */
+#define  PWR_CR_PMODE                        PWR_CR_VOS
+#define  PWR_CR_LPUDS                        PWR_CR_LPLVDS     /*!< Low-Power Regulator in deepsleep under-drive mode        */
+#define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode             */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define PWR_CSR_WUF_Pos        (0U)                                            
+#define PWR_CSR_WUF_Msk        (0x1U << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */
+#define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */
+#define PWR_CSR_SBF_Pos        (1U)                                            
+#define PWR_CSR_SBF_Msk        (0x1U << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */
+#define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */
+#define PWR_CSR_PVDO_Pos       (2U)                                            
+#define PWR_CSR_PVDO_Msk       (0x1U << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */
+#define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */
+#define PWR_CSR_BRR_Pos        (3U)                                            
+#define PWR_CSR_BRR_Msk        (0x1U << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */
+#define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */
+#define PWR_CSR_EWUP_Pos       (8U)                                            
+#define PWR_CSR_EWUP_Msk       (0x1U << PWR_CSR_EWUP_Pos)                      /*!< 0x00000100 */
+#define PWR_CSR_EWUP           PWR_CSR_EWUP_Msk                                /*!< Enable WKUP pin                                  */
+#define PWR_CSR_BRE_Pos        (9U)                                            
+#define PWR_CSR_BRE_Msk        (0x1U << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */
+#define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */
+#define PWR_CSR_VOSRDY_Pos     (14U)                                           
+#define PWR_CSR_VOSRDY_Msk     (0x1U << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */
+#define PWR_CSR_ODRDY_Pos      (16U)                                           
+#define PWR_CSR_ODRDY_Msk      (0x1U << PWR_CSR_ODRDY_Pos)                     /*!< 0x00010000 */
+#define PWR_CSR_ODRDY          PWR_CSR_ODRDY_Msk                               /*!< Over Drive generator ready                       */
+#define PWR_CSR_ODSWRDY_Pos    (17U)                                           
+#define PWR_CSR_ODSWRDY_Msk    (0x1U << PWR_CSR_ODSWRDY_Pos)                   /*!< 0x00020000 */
+#define PWR_CSR_ODSWRDY        PWR_CSR_ODSWRDY_Msk                             /*!< Over Drive Switch ready                          */
+#define PWR_CSR_UDRDY_Pos      (18U)                                           
+#define PWR_CSR_UDRDY_Msk      (0x3U << PWR_CSR_UDRDY_Pos)                     /*!< 0x000C0000 */
+#define PWR_CSR_UDRDY          PWR_CSR_UDRDY_Msk                               /*!< Under Drive ready                                */
+/* Legacy define */
+#define  PWR_CSR_UDSWRDY                     PWR_CSR_UDRDY
+
+/* Legacy define */
+#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_HSION_Pos                   (0U)                                
+#define RCC_CR_HSION_Msk                   (0x1U << RCC_CR_HSION_Pos)          /*!< 0x00000001 */
+#define RCC_CR_HSION                       RCC_CR_HSION_Msk                    
+#define RCC_CR_HSIRDY_Pos                  (1U)                                
+#define RCC_CR_HSIRDY_Msk                  (0x1U << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */
+#define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk                   
+
+#define RCC_CR_HSITRIM_Pos                 (3U)                                
+#define RCC_CR_HSITRIM_Msk                 (0x1FU << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk                  
+#define RCC_CR_HSITRIM_0                   (0x01U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1                   (0x02U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2                   (0x04U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3                   (0x08U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4                   (0x10U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos                  (8U)                                
+#define RCC_CR_HSICAL_Msk                  (0xFFU << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk                   
+#define RCC_CR_HSICAL_0                    (0x01U << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1                    (0x02U << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2                    (0x04U << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3                    (0x08U << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4                    (0x10U << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5                    (0x20U << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6                    (0x40U << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7                    (0x80U << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos                   (16U)                               
+#define RCC_CR_HSEON_Msk                   (0x1U << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */
+#define RCC_CR_HSEON                       RCC_CR_HSEON_Msk                    
+#define RCC_CR_HSERDY_Pos                  (17U)                               
+#define RCC_CR_HSERDY_Msk                  (0x1U << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */
+#define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk                   
+#define RCC_CR_HSEBYP_Pos                  (18U)                               
+#define RCC_CR_HSEBYP_Msk                  (0x1U << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk                   
+#define RCC_CR_CSSON_Pos                   (19U)                               
+#define RCC_CR_CSSON_Msk                   (0x1U << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */
+#define RCC_CR_CSSON                       RCC_CR_CSSON_Msk                    
+#define RCC_CR_PLLON_Pos                   (24U)                               
+#define RCC_CR_PLLON_Msk                   (0x1U << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */
+#define RCC_CR_PLLON                       RCC_CR_PLLON_Msk                    
+#define RCC_CR_PLLRDY_Pos                  (25U)                               
+#define RCC_CR_PLLRDY_Msk                  (0x1U << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk                   
+#define RCC_CR_PLLI2SON_Pos                (26U)                               
+#define RCC_CR_PLLI2SON_Msk                (0x1U << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */
+#define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk                 
+#define RCC_CR_PLLI2SRDY_Pos               (27U)                               
+#define RCC_CR_PLLI2SRDY_Msk               (0x1U << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */
+#define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk                
+#define RCC_CR_PLLSAION_Pos                (28U)                               
+#define RCC_CR_PLLSAION_Msk                (0x1U << RCC_CR_PLLSAION_Pos)       /*!< 0x10000000 */
+#define RCC_CR_PLLSAION                    RCC_CR_PLLSAION_Msk                 
+#define RCC_CR_PLLSAIRDY_Pos               (29U)                               
+#define RCC_CR_PLLSAIRDY_Msk               (0x1U << RCC_CR_PLLSAIRDY_Pos)      /*!< 0x20000000 */
+#define RCC_CR_PLLSAIRDY                   RCC_CR_PLLSAIRDY_Msk                
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+#define RCC_PLLCFGR_PLLM_Pos               (0U)                                
+#define RCC_PLLCFGR_PLLM_Msk               (0x3FU << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk                
+#define RCC_PLLCFGR_PLLM_0                 (0x01U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1                 (0x02U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2                 (0x04U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3                 (0x08U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4                 (0x10U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5                 (0x20U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos               (6U)                                
+#define RCC_PLLCFGR_PLLN_Msk               (0x1FFU << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk                
+#define RCC_PLLCFGR_PLLN_0                 (0x001U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1                 (0x002U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2                 (0x004U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3                 (0x008U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4                 (0x010U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5                 (0x020U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6                 (0x040U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7                 (0x080U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8                 (0x100U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos               (16U)                               
+#define RCC_PLLCFGR_PLLP_Msk               (0x3U << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk                
+#define RCC_PLLCFGR_PLLP_0                 (0x1U << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1                 (0x2U << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos             (22U)                               
+#define RCC_PLLCFGR_PLLSRC_Msk             (0x1U << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk              
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)                               
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk          
+#define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U                         
+
+#define RCC_PLLCFGR_PLLQ_Pos               (24U)                               
+#define RCC_PLLCFGR_PLLQ_Msk               (0xFU << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk                
+#define RCC_PLLCFGR_PLLQ_0                 (0x1U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1                 (0x2U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2                 (0x4U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3                 (0x8U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                    (0U)                                
+#define RCC_CFGR_SW_Msk                    (0x3U << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */
+#define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                      (0x1U << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                      (0x2U << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                   (2U)                                
+#define RCC_CFGR_SWS_Msk                   (0x3U << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */
+#define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                     (0x1U << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1                     (0x2U << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */
+#define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */
+#define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos                  (4U)                                
+#define RCC_CFGR_HPRE_Msk                  (0xFU << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0                    (0x1U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1                    (0x2U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2                    (0x4U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3                    (0x8U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */
+#define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */
+#define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */
+#define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */
+#define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */
+#define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */
+#define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos                 (10U)                               
+#define RCC_CFGR_PPRE1_Msk                 (0x7U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0                   (0x1U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1                   (0x2U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2                   (0x4U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */
+#define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */
+#define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */
+#define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */
+#define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos                 (13U)                               
+#define RCC_CFGR_PPRE2_Msk                 (0x7U << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0                   (0x1U << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1                   (0x2U << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2                   (0x4U << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */
+#define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */
+#define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */
+#define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */
+#define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos                (16U)                               
+#define RCC_CFGR_RTCPRE_Msk                (0x1FU << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk                 
+#define RCC_CFGR_RTCPRE_0                  (0x01U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1                  (0x02U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2                  (0x04U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3                  (0x08U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4                  (0x10U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos                  (21U)                               
+#define RCC_CFGR_MCO1_Msk                  (0x3U << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */
+#define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk                   
+#define RCC_CFGR_MCO1_0                    (0x1U << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1                    (0x2U << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */
+
+#define RCC_CFGR_I2SSRC_Pos                (23U)                               
+#define RCC_CFGR_I2SSRC_Msk                (0x1U << RCC_CFGR_I2SSRC_Pos)       /*!< 0x00800000 */
+#define RCC_CFGR_I2SSRC                    RCC_CFGR_I2SSRC_Msk                 
+
+#define RCC_CFGR_MCO1PRE_Pos               (24U)                               
+#define RCC_CFGR_MCO1PRE_Msk               (0x7U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk                
+#define RCC_CFGR_MCO1PRE_0                 (0x1U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1                 (0x2U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2                 (0x4U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos               (27U)                               
+#define RCC_CFGR_MCO2PRE_Msk               (0x7U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk                
+#define RCC_CFGR_MCO2PRE_0                 (0x1U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1                 (0x2U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2                 (0x4U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos                  (30U)                               
+#define RCC_CFGR_MCO2_Msk                  (0x3U << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk                   
+#define RCC_CFGR_MCO2_0                    (0x1U << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1                    (0x2U << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */
+
+/********************  Bit definition for RCC_CIR register  *******************/
+#define RCC_CIR_LSIRDYF_Pos                (0U)                                
+#define RCC_CIR_LSIRDYF_Msk                (0x1U << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk                 
+#define RCC_CIR_LSERDYF_Pos                (1U)                                
+#define RCC_CIR_LSERDYF_Msk                (0x1U << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk                 
+#define RCC_CIR_HSIRDYF_Pos                (2U)                                
+#define RCC_CIR_HSIRDYF_Msk                (0x1U << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk                 
+#define RCC_CIR_HSERDYF_Pos                (3U)                                
+#define RCC_CIR_HSERDYF_Msk                (0x1U << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk                 
+#define RCC_CIR_PLLRDYF_Pos                (4U)                                
+#define RCC_CIR_PLLRDYF_Msk                (0x1U << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk                 
+#define RCC_CIR_PLLI2SRDYF_Pos             (5U)                                
+#define RCC_CIR_PLLI2SRDYF_Msk             (0x1U << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */
+#define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk              
+
+#define RCC_CIR_PLLSAIRDYF_Pos             (6U)                                
+#define RCC_CIR_PLLSAIRDYF_Msk             (0x1U << RCC_CIR_PLLSAIRDYF_Pos)    /*!< 0x00000040 */
+#define RCC_CIR_PLLSAIRDYF                 RCC_CIR_PLLSAIRDYF_Msk              
+#define RCC_CIR_CSSF_Pos                   (7U)                                
+#define RCC_CIR_CSSF_Msk                   (0x1U << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */
+#define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk                    
+#define RCC_CIR_LSIRDYIE_Pos               (8U)                                
+#define RCC_CIR_LSIRDYIE_Msk               (0x1U << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk                
+#define RCC_CIR_LSERDYIE_Pos               (9U)                                
+#define RCC_CIR_LSERDYIE_Msk               (0x1U << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk                
+#define RCC_CIR_HSIRDYIE_Pos               (10U)                               
+#define RCC_CIR_HSIRDYIE_Msk               (0x1U << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk                
+#define RCC_CIR_HSERDYIE_Pos               (11U)                               
+#define RCC_CIR_HSERDYIE_Msk               (0x1U << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk                
+#define RCC_CIR_PLLRDYIE_Pos               (12U)                               
+#define RCC_CIR_PLLRDYIE_Msk               (0x1U << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk                
+#define RCC_CIR_PLLI2SRDYIE_Pos            (13U)                               
+#define RCC_CIR_PLLI2SRDYIE_Msk            (0x1U << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */
+#define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk             
+
+#define RCC_CIR_PLLSAIRDYIE_Pos            (14U)                               
+#define RCC_CIR_PLLSAIRDYIE_Msk            (0x1U << RCC_CIR_PLLSAIRDYIE_Pos)   /*!< 0x00004000 */
+#define RCC_CIR_PLLSAIRDYIE                RCC_CIR_PLLSAIRDYIE_Msk             
+#define RCC_CIR_LSIRDYC_Pos                (16U)                               
+#define RCC_CIR_LSIRDYC_Msk                (0x1U << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk                 
+#define RCC_CIR_LSERDYC_Pos                (17U)                               
+#define RCC_CIR_LSERDYC_Msk                (0x1U << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk                 
+#define RCC_CIR_HSIRDYC_Pos                (18U)                               
+#define RCC_CIR_HSIRDYC_Msk                (0x1U << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk                 
+#define RCC_CIR_HSERDYC_Pos                (19U)                               
+#define RCC_CIR_HSERDYC_Msk                (0x1U << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk                 
+#define RCC_CIR_PLLRDYC_Pos                (20U)                               
+#define RCC_CIR_PLLRDYC_Msk                (0x1U << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk                 
+#define RCC_CIR_PLLI2SRDYC_Pos             (21U)                               
+#define RCC_CIR_PLLI2SRDYC_Msk             (0x1U << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */
+#define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk              
+#define RCC_CIR_PLLSAIRDYC_Pos             (22U)                               
+#define RCC_CIR_PLLSAIRDYC_Msk             (0x1U << RCC_CIR_PLLSAIRDYC_Pos)    /*!< 0x00400000 */
+#define RCC_CIR_PLLSAIRDYC                 RCC_CIR_PLLSAIRDYC_Msk              
+
+#define RCC_CIR_CSSC_Pos                   (23U)                               
+#define RCC_CIR_CSSC_Msk                   (0x1U << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */
+#define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk                    
+
+/********************  Bit definition for RCC_AHB1RSTR register  **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos          (0U)                                
+#define RCC_AHB1RSTR_GPIOARST_Msk          (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk           
+#define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)                                
+#define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk           
+#define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)                                
+#define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk           
+#define RCC_AHB1RSTR_GPIODRST_Pos          (3U)                                
+#define RCC_AHB1RSTR_GPIODRST_Msk          (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk           
+#define RCC_AHB1RSTR_GPIOERST_Pos          (4U)                                
+#define RCC_AHB1RSTR_GPIOERST_Msk          (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk           
+#define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)                                
+#define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk           
+#define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)                                
+#define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk           
+#define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)                                
+#define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk           
+#define RCC_AHB1RSTR_GPIOIRST_Pos          (8U)                                
+#define RCC_AHB1RSTR_GPIOIRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB1RSTR_GPIOIRST              RCC_AHB1RSTR_GPIOIRST_Msk           
+#define RCC_AHB1RSTR_GPIOJRST_Pos          (9U)                                
+#define RCC_AHB1RSTR_GPIOJRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
+#define RCC_AHB1RSTR_GPIOJRST              RCC_AHB1RSTR_GPIOJRST_Msk           
+#define RCC_AHB1RSTR_GPIOKRST_Pos          (10U)                               
+#define RCC_AHB1RSTR_GPIOKRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
+#define RCC_AHB1RSTR_GPIOKRST              RCC_AHB1RSTR_GPIOKRST_Msk           
+#define RCC_AHB1RSTR_CRCRST_Pos            (12U)                               
+#define RCC_AHB1RSTR_CRCRST_Msk            (0x1U << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk             
+#define RCC_AHB1RSTR_DMA1RST_Pos           (21U)                               
+#define RCC_AHB1RSTR_DMA1RST_Msk           (0x1U << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk            
+#define RCC_AHB1RSTR_DMA2RST_Pos           (22U)                               
+#define RCC_AHB1RSTR_DMA2RST_Msk           (0x1U << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk            
+#define RCC_AHB1RSTR_DMA2DRST_Pos          (23U)                               
+#define RCC_AHB1RSTR_DMA2DRST_Msk          (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
+#define RCC_AHB1RSTR_DMA2DRST              RCC_AHB1RSTR_DMA2DRST_Msk           
+#define RCC_AHB1RSTR_ETHMACRST_Pos         (25U)                               
+#define RCC_AHB1RSTR_ETHMACRST_Msk         (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
+#define RCC_AHB1RSTR_ETHMACRST             RCC_AHB1RSTR_ETHMACRST_Msk          
+#define RCC_AHB1RSTR_OTGHRST_Pos           (29U)                               
+#define RCC_AHB1RSTR_OTGHRST_Msk           (0x1U << RCC_AHB1RSTR_OTGHRST_Pos)  /*!< 0x20000000 */
+#define RCC_AHB1RSTR_OTGHRST               RCC_AHB1RSTR_OTGHRST_Msk            
+
+/********************  Bit definition for RCC_AHB2RSTR register  **************/
+#define RCC_AHB2RSTR_DCMIRST_Pos           (0U)                                
+#define RCC_AHB2RSTR_DCMIRST_Msk           (0x1U << RCC_AHB2RSTR_DCMIRST_Pos)  /*!< 0x00000001 */
+#define RCC_AHB2RSTR_DCMIRST               RCC_AHB2RSTR_DCMIRST_Msk            
+#define RCC_AHB2RSTR_CRYPRST_Pos           (4U)                                
+#define RCC_AHB2RSTR_CRYPRST_Msk           (0x1U << RCC_AHB2RSTR_CRYPRST_Pos)  /*!< 0x00000010 */
+#define RCC_AHB2RSTR_CRYPRST               RCC_AHB2RSTR_CRYPRST_Msk            
+#define RCC_AHB2RSTR_HASHRST_Pos           (5U)                                
+#define RCC_AHB2RSTR_HASHRST_Msk           (0x1U << RCC_AHB2RSTR_HASHRST_Pos)  /*!< 0x00000020 */
+#define RCC_AHB2RSTR_HASHRST               RCC_AHB2RSTR_HASHRST_Msk            
+ /* maintained for legacy purpose */
+#define  RCC_AHB2RSTR_HSAHRST                RCC_AHB2RSTR_HASHRST
+#define RCC_AHB2RSTR_RNGRST_Pos            (6U)                                
+#define RCC_AHB2RSTR_RNGRST_Msk            (0x1U << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */
+#define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk             
+#define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)                                
+#define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk           
+/********************  Bit definition for RCC_AHB3RSTR register  **************/
+#define RCC_AHB3RSTR_FMCRST_Pos            (0U)                                
+#define RCC_AHB3RSTR_FMCRST_Msk            (0x1U << RCC_AHB3RSTR_FMCRST_Pos)   /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FMCRST                RCC_AHB3RSTR_FMCRST_Msk             
+
+
+/********************  Bit definition for RCC_APB1RSTR register  **************/
+#define RCC_APB1RSTR_TIM2RST_Pos           (0U)                                
+#define RCC_APB1RSTR_TIM2RST_Msk           (0x1U << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk            
+#define RCC_APB1RSTR_TIM3RST_Pos           (1U)                                
+#define RCC_APB1RSTR_TIM3RST_Msk           (0x1U << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk            
+#define RCC_APB1RSTR_TIM4RST_Pos           (2U)                                
+#define RCC_APB1RSTR_TIM4RST_Msk           (0x1U << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk            
+#define RCC_APB1RSTR_TIM5RST_Pos           (3U)                                
+#define RCC_APB1RSTR_TIM5RST_Msk           (0x1U << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk            
+#define RCC_APB1RSTR_TIM6RST_Pos           (4U)                                
+#define RCC_APB1RSTR_TIM6RST_Msk           (0x1U << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk            
+#define RCC_APB1RSTR_TIM7RST_Pos           (5U)                                
+#define RCC_APB1RSTR_TIM7RST_Msk           (0x1U << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk            
+#define RCC_APB1RSTR_TIM12RST_Pos          (6U)                                
+#define RCC_APB1RSTR_TIM12RST_Msk          (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk           
+#define RCC_APB1RSTR_TIM13RST_Pos          (7U)                                
+#define RCC_APB1RSTR_TIM13RST_Msk          (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk           
+#define RCC_APB1RSTR_TIM14RST_Pos          (8U)                                
+#define RCC_APB1RSTR_TIM14RST_Msk          (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk           
+#define RCC_APB1RSTR_WWDGRST_Pos           (11U)                               
+#define RCC_APB1RSTR_WWDGRST_Msk           (0x1U << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk            
+#define RCC_APB1RSTR_SPI2RST_Pos           (14U)                               
+#define RCC_APB1RSTR_SPI2RST_Msk           (0x1U << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk            
+#define RCC_APB1RSTR_SPI3RST_Pos           (15U)                               
+#define RCC_APB1RSTR_SPI3RST_Msk           (0x1U << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk            
+#define RCC_APB1RSTR_USART2RST_Pos         (17U)                               
+#define RCC_APB1RSTR_USART2RST_Msk         (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk          
+#define RCC_APB1RSTR_USART3RST_Pos         (18U)                               
+#define RCC_APB1RSTR_USART3RST_Msk         (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk          
+#define RCC_APB1RSTR_UART4RST_Pos          (19U)                               
+#define RCC_APB1RSTR_UART4RST_Msk          (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk           
+#define RCC_APB1RSTR_UART5RST_Pos          (20U)                               
+#define RCC_APB1RSTR_UART5RST_Msk          (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk           
+#define RCC_APB1RSTR_I2C1RST_Pos           (21U)                               
+#define RCC_APB1RSTR_I2C1RST_Msk           (0x1U << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk            
+#define RCC_APB1RSTR_I2C2RST_Pos           (22U)                               
+#define RCC_APB1RSTR_I2C2RST_Msk           (0x1U << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk            
+#define RCC_APB1RSTR_I2C3RST_Pos           (23U)                               
+#define RCC_APB1RSTR_I2C3RST_Msk           (0x1U << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */
+#define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk            
+#define RCC_APB1RSTR_CAN1RST_Pos           (25U)                               
+#define RCC_APB1RSTR_CAN1RST_Msk           (0x1U << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk            
+#define RCC_APB1RSTR_CAN2RST_Pos           (26U)                               
+#define RCC_APB1RSTR_CAN2RST_Msk           (0x1U << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */
+#define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk            
+#define RCC_APB1RSTR_PWRRST_Pos            (28U)                               
+#define RCC_APB1RSTR_PWRRST_Msk            (0x1U << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk             
+#define RCC_APB1RSTR_DACRST_Pos            (29U)                               
+#define RCC_APB1RSTR_DACRST_Msk            (0x1U << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk             
+#define RCC_APB1RSTR_UART7RST_Pos          (30U)                               
+#define RCC_APB1RSTR_UART7RST_Msk          (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR_UART7RST              RCC_APB1RSTR_UART7RST_Msk           
+#define RCC_APB1RSTR_UART8RST_Pos          (31U)                               
+#define RCC_APB1RSTR_UART8RST_Msk          (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_UART8RST              RCC_APB1RSTR_UART8RST_Msk           
+
+/********************  Bit definition for RCC_APB2RSTR register  **************/
+#define RCC_APB2RSTR_TIM1RST_Pos           (0U)                                
+#define RCC_APB2RSTR_TIM1RST_Msk           (0x1U << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk            
+#define RCC_APB2RSTR_TIM8RST_Pos           (1U)                                
+#define RCC_APB2RSTR_TIM8RST_Msk           (0x1U << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk            
+#define RCC_APB2RSTR_USART1RST_Pos         (4U)                                
+#define RCC_APB2RSTR_USART1RST_Msk         (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk          
+#define RCC_APB2RSTR_USART6RST_Pos         (5U)                                
+#define RCC_APB2RSTR_USART6RST_Msk         (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk          
+#define RCC_APB2RSTR_ADCRST_Pos            (8U)                                
+#define RCC_APB2RSTR_ADCRST_Msk            (0x1U << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk             
+#define RCC_APB2RSTR_SDIORST_Pos           (11U)                               
+#define RCC_APB2RSTR_SDIORST_Msk           (0x1U << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */
+#define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk            
+#define RCC_APB2RSTR_SPI1RST_Pos           (12U)                               
+#define RCC_APB2RSTR_SPI1RST_Msk           (0x1U << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk            
+#define RCC_APB2RSTR_SPI4RST_Pos           (13U)                               
+#define RCC_APB2RSTR_SPI4RST_Msk           (0x1U << RCC_APB2RSTR_SPI4RST_Pos)  /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST               RCC_APB2RSTR_SPI4RST_Msk            
+#define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)                               
+#define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk          
+#define RCC_APB2RSTR_TIM9RST_Pos           (16U)                               
+#define RCC_APB2RSTR_TIM9RST_Msk           (0x1U << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk            
+#define RCC_APB2RSTR_TIM10RST_Pos          (17U)                               
+#define RCC_APB2RSTR_TIM10RST_Msk          (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk           
+#define RCC_APB2RSTR_TIM11RST_Pos          (18U)                               
+#define RCC_APB2RSTR_TIM11RST_Msk          (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk           
+#define RCC_APB2RSTR_SPI5RST_Pos           (20U)                               
+#define RCC_APB2RSTR_SPI5RST_Msk           (0x1U << RCC_APB2RSTR_SPI5RST_Pos)  /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST               RCC_APB2RSTR_SPI5RST_Msk            
+#define RCC_APB2RSTR_SPI6RST_Pos           (21U)                               
+#define RCC_APB2RSTR_SPI6RST_Msk           (0x1U << RCC_APB2RSTR_SPI6RST_Pos)  /*!< 0x00200000 */
+#define RCC_APB2RSTR_SPI6RST               RCC_APB2RSTR_SPI6RST_Msk            
+#define RCC_APB2RSTR_SAI1RST_Pos           (22U)                               
+#define RCC_APB2RSTR_SAI1RST_Msk           (0x1U << RCC_APB2RSTR_SAI1RST_Pos)  /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI1RST               RCC_APB2RSTR_SAI1RST_Msk            
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos            (0U)                                
+#define RCC_AHB1ENR_GPIOAEN_Msk            (0x1U << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk             
+#define RCC_AHB1ENR_GPIOBEN_Pos            (1U)                                
+#define RCC_AHB1ENR_GPIOBEN_Msk            (0x1U << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk             
+#define RCC_AHB1ENR_GPIOCEN_Pos            (2U)                                
+#define RCC_AHB1ENR_GPIOCEN_Msk            (0x1U << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk             
+#define RCC_AHB1ENR_GPIODEN_Pos            (3U)                                
+#define RCC_AHB1ENR_GPIODEN_Msk            (0x1U << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */
+#define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk             
+#define RCC_AHB1ENR_GPIOEEN_Pos            (4U)                                
+#define RCC_AHB1ENR_GPIOEEN_Msk            (0x1U << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk             
+#define RCC_AHB1ENR_GPIOFEN_Pos            (5U)                                
+#define RCC_AHB1ENR_GPIOFEN_Msk            (0x1U << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */
+#define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk             
+#define RCC_AHB1ENR_GPIOGEN_Pos            (6U)                                
+#define RCC_AHB1ENR_GPIOGEN_Msk            (0x1U << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */
+#define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk             
+#define RCC_AHB1ENR_GPIOHEN_Pos            (7U)                                
+#define RCC_AHB1ENR_GPIOHEN_Msk            (0x1U << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk             
+#define RCC_AHB1ENR_GPIOIEN_Pos            (8U)                                
+#define RCC_AHB1ENR_GPIOIEN_Msk            (0x1U << RCC_AHB1ENR_GPIOIEN_Pos)   /*!< 0x00000100 */
+#define RCC_AHB1ENR_GPIOIEN                RCC_AHB1ENR_GPIOIEN_Msk             
+#define RCC_AHB1ENR_GPIOJEN_Pos            (9U)                                
+#define RCC_AHB1ENR_GPIOJEN_Msk            (0x1U << RCC_AHB1ENR_GPIOJEN_Pos)   /*!< 0x00000200 */
+#define RCC_AHB1ENR_GPIOJEN                RCC_AHB1ENR_GPIOJEN_Msk             
+#define RCC_AHB1ENR_GPIOKEN_Pos            (10U)                               
+#define RCC_AHB1ENR_GPIOKEN_Msk            (0x1U << RCC_AHB1ENR_GPIOKEN_Pos)   /*!< 0x00000400 */
+#define RCC_AHB1ENR_GPIOKEN                RCC_AHB1ENR_GPIOKEN_Msk             
+#define RCC_AHB1ENR_CRCEN_Pos              (12U)                               
+#define RCC_AHB1ENR_CRCEN_Msk              (0x1U << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk               
+#define RCC_AHB1ENR_BKPSRAMEN_Pos          (18U)                               
+#define RCC_AHB1ENR_BKPSRAMEN_Msk          (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1ENR_BKPSRAMEN              RCC_AHB1ENR_BKPSRAMEN_Msk           
+#define RCC_AHB1ENR_CCMDATARAMEN_Pos       (20U)                               
+#define RCC_AHB1ENR_CCMDATARAMEN_Msk       (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
+#define RCC_AHB1ENR_CCMDATARAMEN           RCC_AHB1ENR_CCMDATARAMEN_Msk        
+#define RCC_AHB1ENR_DMA1EN_Pos             (21U)                               
+#define RCC_AHB1ENR_DMA1EN_Msk             (0x1U << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk              
+#define RCC_AHB1ENR_DMA2EN_Pos             (22U)                               
+#define RCC_AHB1ENR_DMA2EN_Msk             (0x1U << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk              
+#define RCC_AHB1ENR_DMA2DEN_Pos            (23U)                               
+#define RCC_AHB1ENR_DMA2DEN_Msk            (0x1U << RCC_AHB1ENR_DMA2DEN_Pos)   /*!< 0x00800000 */
+#define RCC_AHB1ENR_DMA2DEN                RCC_AHB1ENR_DMA2DEN_Msk             
+#define RCC_AHB1ENR_ETHMACEN_Pos           (25U)                               
+#define RCC_AHB1ENR_ETHMACEN_Msk           (0x1U << RCC_AHB1ENR_ETHMACEN_Pos)  /*!< 0x02000000 */
+#define RCC_AHB1ENR_ETHMACEN               RCC_AHB1ENR_ETHMACEN_Msk            
+#define RCC_AHB1ENR_ETHMACTXEN_Pos         (26U)                               
+#define RCC_AHB1ENR_ETHMACTXEN_Msk         (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1ENR_ETHMACTXEN             RCC_AHB1ENR_ETHMACTXEN_Msk          
+#define RCC_AHB1ENR_ETHMACRXEN_Pos         (27U)                               
+#define RCC_AHB1ENR_ETHMACRXEN_Msk         (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1ENR_ETHMACRXEN             RCC_AHB1ENR_ETHMACRXEN_Msk          
+#define RCC_AHB1ENR_ETHMACPTPEN_Pos        (28U)                               
+#define RCC_AHB1ENR_ETHMACPTPEN_Msk        (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1ENR_ETHMACPTPEN            RCC_AHB1ENR_ETHMACPTPEN_Msk         
+#define RCC_AHB1ENR_OTGHSEN_Pos            (29U)                               
+#define RCC_AHB1ENR_OTGHSEN_Msk            (0x1U << RCC_AHB1ENR_OTGHSEN_Pos)   /*!< 0x20000000 */
+#define RCC_AHB1ENR_OTGHSEN                RCC_AHB1ENR_OTGHSEN_Msk             
+#define RCC_AHB1ENR_OTGHSULPIEN_Pos        (30U)                               
+#define RCC_AHB1ENR_OTGHSULPIEN_Msk        (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1ENR_OTGHSULPIEN            RCC_AHB1ENR_OTGHSULPIEN_Msk         
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define RCC_AHB2ENR_DCMIEN_Pos             (0U)                                
+#define RCC_AHB2ENR_DCMIEN_Msk             (0x1U << RCC_AHB2ENR_DCMIEN_Pos)    /*!< 0x00000001 */
+#define RCC_AHB2ENR_DCMIEN                 RCC_AHB2ENR_DCMIEN_Msk              
+#define RCC_AHB2ENR_CRYPEN_Pos             (4U)                                
+#define RCC_AHB2ENR_CRYPEN_Msk             (0x1U << RCC_AHB2ENR_CRYPEN_Pos)    /*!< 0x00000010 */
+#define RCC_AHB2ENR_CRYPEN                 RCC_AHB2ENR_CRYPEN_Msk              
+#define RCC_AHB2ENR_HASHEN_Pos             (5U)                                
+#define RCC_AHB2ENR_HASHEN_Msk             (0x1U << RCC_AHB2ENR_HASHEN_Pos)    /*!< 0x00000020 */
+#define RCC_AHB2ENR_HASHEN                 RCC_AHB2ENR_HASHEN_Msk              
+#define RCC_AHB2ENR_RNGEN_Pos              (6U)                                
+#define RCC_AHB2ENR_RNGEN_Msk              (0x1U << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */
+#define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk               
+#define RCC_AHB2ENR_OTGFSEN_Pos            (7U)                                
+#define RCC_AHB2ENR_OTGFSEN_Msk            (0x1U << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */
+#define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk             
+
+/********************  Bit definition for RCC_AHB3ENR register  ***************/
+#define RCC_AHB3ENR_FMCEN_Pos              (0U)                                
+#define RCC_AHB3ENR_FMCEN_Msk              (0x1U << RCC_AHB3ENR_FMCEN_Pos)     /*!< 0x00000001 */
+#define RCC_AHB3ENR_FMCEN                  RCC_AHB3ENR_FMCEN_Msk               
+
+/********************  Bit definition for RCC_APB1ENR register  ***************/
+#define RCC_APB1ENR_TIM2EN_Pos             (0U)                                
+#define RCC_APB1ENR_TIM2EN_Msk             (0x1U << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk              
+#define RCC_APB1ENR_TIM3EN_Pos             (1U)                                
+#define RCC_APB1ENR_TIM3EN_Msk             (0x1U << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk              
+#define RCC_APB1ENR_TIM4EN_Pos             (2U)                                
+#define RCC_APB1ENR_TIM4EN_Msk             (0x1U << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk              
+#define RCC_APB1ENR_TIM5EN_Pos             (3U)                                
+#define RCC_APB1ENR_TIM5EN_Msk             (0x1U << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk              
+#define RCC_APB1ENR_TIM6EN_Pos             (4U)                                
+#define RCC_APB1ENR_TIM6EN_Msk             (0x1U << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk              
+#define RCC_APB1ENR_TIM7EN_Pos             (5U)                                
+#define RCC_APB1ENR_TIM7EN_Msk             (0x1U << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk              
+#define RCC_APB1ENR_TIM12EN_Pos            (6U)                                
+#define RCC_APB1ENR_TIM12EN_Msk            (0x1U << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */
+#define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk             
+#define RCC_APB1ENR_TIM13EN_Pos            (7U)                                
+#define RCC_APB1ENR_TIM13EN_Msk            (0x1U << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */
+#define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk             
+#define RCC_APB1ENR_TIM14EN_Pos            (8U)                                
+#define RCC_APB1ENR_TIM14EN_Msk            (0x1U << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */
+#define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk             
+#define RCC_APB1ENR_WWDGEN_Pos             (11U)                               
+#define RCC_APB1ENR_WWDGEN_Msk             (0x1U << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk              
+#define RCC_APB1ENR_SPI2EN_Pos             (14U)                               
+#define RCC_APB1ENR_SPI2EN_Msk             (0x1U << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk              
+#define RCC_APB1ENR_SPI3EN_Pos             (15U)                               
+#define RCC_APB1ENR_SPI3EN_Msk             (0x1U << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk              
+#define RCC_APB1ENR_USART2EN_Pos           (17U)                               
+#define RCC_APB1ENR_USART2EN_Msk           (0x1U << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk            
+#define RCC_APB1ENR_USART3EN_Pos           (18U)                               
+#define RCC_APB1ENR_USART3EN_Msk           (0x1U << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk            
+#define RCC_APB1ENR_UART4EN_Pos            (19U)                               
+#define RCC_APB1ENR_UART4EN_Msk            (0x1U << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk             
+#define RCC_APB1ENR_UART5EN_Pos            (20U)                               
+#define RCC_APB1ENR_UART5EN_Msk            (0x1U << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk             
+#define RCC_APB1ENR_I2C1EN_Pos             (21U)                               
+#define RCC_APB1ENR_I2C1EN_Msk             (0x1U << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk              
+#define RCC_APB1ENR_I2C2EN_Pos             (22U)                               
+#define RCC_APB1ENR_I2C2EN_Msk             (0x1U << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk              
+#define RCC_APB1ENR_I2C3EN_Pos             (23U)                               
+#define RCC_APB1ENR_I2C3EN_Msk             (0x1U << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */
+#define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk              
+#define RCC_APB1ENR_CAN1EN_Pos             (25U)                               
+#define RCC_APB1ENR_CAN1EN_Msk             (0x1U << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk              
+#define RCC_APB1ENR_CAN2EN_Pos             (26U)                               
+#define RCC_APB1ENR_CAN2EN_Msk             (0x1U << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */
+#define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk              
+#define RCC_APB1ENR_PWREN_Pos              (28U)                               
+#define RCC_APB1ENR_PWREN_Msk              (0x1U << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk               
+#define RCC_APB1ENR_DACEN_Pos              (29U)                               
+#define RCC_APB1ENR_DACEN_Msk              (0x1U << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk               
+#define RCC_APB1ENR_UART7EN_Pos            (30U)                               
+#define RCC_APB1ENR_UART7EN_Msk            (0x1U << RCC_APB1ENR_UART7EN_Pos)   /*!< 0x40000000 */
+#define RCC_APB1ENR_UART7EN                RCC_APB1ENR_UART7EN_Msk             
+#define RCC_APB1ENR_UART8EN_Pos            (31U)                               
+#define RCC_APB1ENR_UART8EN_Msk            (0x1U << RCC_APB1ENR_UART8EN_Pos)   /*!< 0x80000000 */
+#define RCC_APB1ENR_UART8EN                RCC_APB1ENR_UART8EN_Msk             
+
+/********************  Bit definition for RCC_APB2ENR register  ***************/
+#define RCC_APB2ENR_TIM1EN_Pos             (0U)                                
+#define RCC_APB2ENR_TIM1EN_Msk             (0x1U << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk              
+#define RCC_APB2ENR_TIM8EN_Pos             (1U)                                
+#define RCC_APB2ENR_TIM8EN_Msk             (0x1U << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk              
+#define RCC_APB2ENR_USART1EN_Pos           (4U)                                
+#define RCC_APB2ENR_USART1EN_Msk           (0x1U << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk            
+#define RCC_APB2ENR_USART6EN_Pos           (5U)                                
+#define RCC_APB2ENR_USART6EN_Msk           (0x1U << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk            
+#define RCC_APB2ENR_ADC1EN_Pos             (8U)                                
+#define RCC_APB2ENR_ADC1EN_Msk             (0x1U << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk              
+#define RCC_APB2ENR_ADC2EN_Pos             (9U)                                
+#define RCC_APB2ENR_ADC2EN_Msk             (0x1U << RCC_APB2ENR_ADC2EN_Pos)    /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC2EN                 RCC_APB2ENR_ADC2EN_Msk              
+#define RCC_APB2ENR_ADC3EN_Pos             (10U)                               
+#define RCC_APB2ENR_ADC3EN_Msk             (0x1U << RCC_APB2ENR_ADC3EN_Pos)    /*!< 0x00000400 */
+#define RCC_APB2ENR_ADC3EN                 RCC_APB2ENR_ADC3EN_Msk              
+#define RCC_APB2ENR_SDIOEN_Pos             (11U)                               
+#define RCC_APB2ENR_SDIOEN_Msk             (0x1U << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */
+#define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk              
+#define RCC_APB2ENR_SPI1EN_Pos             (12U)                               
+#define RCC_APB2ENR_SPI1EN_Msk             (0x1U << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk              
+#define RCC_APB2ENR_SPI4EN_Pos             (13U)                               
+#define RCC_APB2ENR_SPI4EN_Msk             (0x1U << RCC_APB2ENR_SPI4EN_Pos)    /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN                 RCC_APB2ENR_SPI4EN_Msk              
+#define RCC_APB2ENR_SYSCFGEN_Pos           (14U)                               
+#define RCC_APB2ENR_SYSCFGEN_Msk           (0x1U << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk            
+#define RCC_APB2ENR_TIM9EN_Pos             (16U)                               
+#define RCC_APB2ENR_TIM9EN_Msk             (0x1U << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk              
+#define RCC_APB2ENR_TIM10EN_Pos            (17U)                               
+#define RCC_APB2ENR_TIM10EN_Msk            (0x1U << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk             
+#define RCC_APB2ENR_TIM11EN_Pos            (18U)                               
+#define RCC_APB2ENR_TIM11EN_Msk            (0x1U << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk             
+#define RCC_APB2ENR_SPI5EN_Pos             (20U)                               
+#define RCC_APB2ENR_SPI5EN_Msk             (0x1U << RCC_APB2ENR_SPI5EN_Pos)    /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN                 RCC_APB2ENR_SPI5EN_Msk              
+#define RCC_APB2ENR_SPI6EN_Pos             (21U)                               
+#define RCC_APB2ENR_SPI6EN_Msk             (0x1U << RCC_APB2ENR_SPI6EN_Pos)    /*!< 0x00200000 */
+#define RCC_APB2ENR_SPI6EN                 RCC_APB2ENR_SPI6EN_Msk              
+#define RCC_APB2ENR_SAI1EN_Pos             (22U)                               
+#define RCC_APB2ENR_SAI1EN_Msk             (0x1U << RCC_APB2ENR_SAI1EN_Pos)    /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI1EN                 RCC_APB2ENR_SAI1EN_Msk              
+
+/********************  Bit definition for RCC_AHB1LPENR register  *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)                                
+#define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk         
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)                                
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk         
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)                                
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk         
+#define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)                                
+#define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk         
+#define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)                                
+#define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk         
+#define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)                                
+#define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk         
+#define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)                                
+#define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk         
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)                                
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk         
+#define RCC_AHB1LPENR_GPIOILPEN_Pos        (8U)                                
+#define RCC_AHB1LPENR_GPIOILPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1LPENR_GPIOILPEN            RCC_AHB1LPENR_GPIOILPEN_Msk         
+#define RCC_AHB1LPENR_GPIOJLPEN_Pos        (9U)                                
+#define RCC_AHB1LPENR_GPIOJLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB1LPENR_GPIOJLPEN            RCC_AHB1LPENR_GPIOJLPEN_Msk         
+#define RCC_AHB1LPENR_GPIOKLPEN_Pos        (10U)                               
+#define RCC_AHB1LPENR_GPIOKLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
+#define RCC_AHB1LPENR_GPIOKLPEN            RCC_AHB1LPENR_GPIOKLPEN_Msk         
+#define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)                               
+#define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk           
+#define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)                               
+#define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk         
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)                               
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk         
+#define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)                               
+#define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk         
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos      (18U)                               
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk      (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1LPENR_BKPSRAMLPEN          RCC_AHB1LPENR_BKPSRAMLPEN_Msk       
+#define RCC_AHB1LPENR_SRAM3LPEN_Pos        (19U)                               
+#define RCC_AHB1LPENR_SRAM3LPEN_Msk        (0x1U << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */
+#define RCC_AHB1LPENR_SRAM3LPEN            RCC_AHB1LPENR_SRAM3LPEN_Msk         
+#define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)                               
+#define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk          
+#define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)                               
+#define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk          
+#define RCC_AHB1LPENR_DMA2DLPEN_Pos        (23U)                               
+#define RCC_AHB1LPENR_DMA2DLPEN_Msk        (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
+#define RCC_AHB1LPENR_DMA2DLPEN            RCC_AHB1LPENR_DMA2DLPEN_Msk         
+
+#define RCC_AHB1LPENR_ETHMACLPEN_Pos       (25U)                               
+#define RCC_AHB1LPENR_ETHMACLPEN_Msk       (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1LPENR_ETHMACLPEN           RCC_AHB1LPENR_ETHMACLPEN_Msk        
+#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos     (26U)                               
+#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk     (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1LPENR_ETHMACTXLPEN         RCC_AHB1LPENR_ETHMACTXLPEN_Msk      
+#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos     (27U)                               
+#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk     (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1LPENR_ETHMACRXLPEN         RCC_AHB1LPENR_ETHMACRXLPEN_Msk      
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos    (28U)                               
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk    (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1LPENR_ETHMACPTPLPEN        RCC_AHB1LPENR_ETHMACPTPLPEN_Msk     
+#define RCC_AHB1LPENR_OTGHSLPEN_Pos        (29U)                               
+#define RCC_AHB1LPENR_OTGHSLPEN_Msk        (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB1LPENR_OTGHSLPEN            RCC_AHB1LPENR_OTGHSLPEN_Msk         
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos    (30U)                               
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk    (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1LPENR_OTGHSULPILPEN        RCC_AHB1LPENR_OTGHSULPILPEN_Msk     
+
+/********************  Bit definition for RCC_AHB2LPENR register  *************/
+#define RCC_AHB2LPENR_DCMILPEN_Pos         (0U)                                
+#define RCC_AHB2LPENR_DCMILPEN_Msk         (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2LPENR_DCMILPEN             RCC_AHB2LPENR_DCMILPEN_Msk          
+#define RCC_AHB2LPENR_CRYPLPEN_Pos         (4U)                                
+#define RCC_AHB2LPENR_CRYPLPEN_Msk         (0x1U << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB2LPENR_CRYPLPEN             RCC_AHB2LPENR_CRYPLPEN_Msk          
+#define RCC_AHB2LPENR_HASHLPEN_Pos         (5U)                                
+#define RCC_AHB2LPENR_HASHLPEN_Msk         (0x1U << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB2LPENR_HASHLPEN             RCC_AHB2LPENR_HASHLPEN_Msk          
+#define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)                                
+#define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk           
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)                                
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk         
+
+/********************  Bit definition for RCC_AHB3LPENR register  *************/
+#define RCC_AHB3LPENR_FMCLPEN_Pos          (0U)                                
+#define RCC_AHB3LPENR_FMCLPEN_Msk          (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3LPENR_FMCLPEN              RCC_AHB3LPENR_FMCLPEN_Msk           
+
+/********************  Bit definition for RCC_APB1LPENR register  *************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)                                
+#define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk          
+#define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)                                
+#define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk          
+#define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)                                
+#define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk          
+#define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)                                
+#define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk          
+#define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)                                
+#define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk          
+#define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)                                
+#define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk          
+#define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)                                
+#define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk         
+#define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)                                
+#define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk         
+#define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)                                
+#define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk         
+#define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)                               
+#define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk          
+#define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)                               
+#define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk          
+#define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)                               
+#define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk          
+#define RCC_APB1LPENR_USART2LPEN_Pos       (17U)                               
+#define RCC_APB1LPENR_USART2LPEN_Msk       (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk        
+#define RCC_APB1LPENR_USART3LPEN_Pos       (18U)                               
+#define RCC_APB1LPENR_USART3LPEN_Msk       (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk        
+#define RCC_APB1LPENR_UART4LPEN_Pos        (19U)                               
+#define RCC_APB1LPENR_UART4LPEN_Msk        (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk         
+#define RCC_APB1LPENR_UART5LPEN_Pos        (20U)                               
+#define RCC_APB1LPENR_UART5LPEN_Msk        (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk         
+#define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)                               
+#define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk          
+#define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)                               
+#define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk          
+#define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)                               
+#define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk          
+#define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)                               
+#define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk          
+#define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)                               
+#define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
+#define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk          
+#define RCC_APB1LPENR_PWRLPEN_Pos          (28U)                               
+#define RCC_APB1LPENR_PWRLPEN_Msk          (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk           
+#define RCC_APB1LPENR_DACLPEN_Pos          (29U)                               
+#define RCC_APB1LPENR_DACLPEN_Msk          (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk           
+#define RCC_APB1LPENR_UART7LPEN_Pos        (30U)                               
+#define RCC_APB1LPENR_UART7LPEN_Msk        (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LPENR_UART7LPEN            RCC_APB1LPENR_UART7LPEN_Msk         
+#define RCC_APB1LPENR_UART8LPEN_Pos        (31U)                               
+#define RCC_APB1LPENR_UART8LPEN_Msk        (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LPENR_UART8LPEN            RCC_APB1LPENR_UART8LPEN_Msk         
+
+/********************  Bit definition for RCC_APB2LPENR register  *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)                                
+#define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk          
+#define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)                                
+#define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk          
+#define RCC_APB2LPENR_USART1LPEN_Pos       (4U)                                
+#define RCC_APB2LPENR_USART1LPEN_Msk       (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk        
+#define RCC_APB2LPENR_USART6LPEN_Pos       (5U)                                
+#define RCC_APB2LPENR_USART6LPEN_Msk       (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk        
+#define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)                                
+#define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk          
+#define RCC_APB2LPENR_ADC2LPEN_Pos         (9U)                                
+#define RCC_APB2LPENR_ADC2LPEN_Msk         (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2LPENR_ADC2LPEN             RCC_APB2LPENR_ADC2LPEN_Msk          
+#define RCC_APB2LPENR_ADC3LPEN_Pos         (10U)                               
+#define RCC_APB2LPENR_ADC3LPEN_Msk         (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB2LPENR_ADC3LPEN             RCC_APB2LPENR_ADC3LPEN_Msk          
+#define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)                               
+#define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk          
+#define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)                               
+#define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk          
+#define RCC_APB2LPENR_SPI4LPEN_Pos         (13U)                               
+#define RCC_APB2LPENR_SPI4LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN             RCC_APB2LPENR_SPI4LPEN_Msk          
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)                               
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk        
+#define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)                               
+#define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk          
+#define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)                               
+#define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk         
+#define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)                               
+#define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk         
+#define RCC_APB2LPENR_SPI5LPEN_Pos         (20U)                               
+#define RCC_APB2LPENR_SPI5LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN             RCC_APB2LPENR_SPI5LPEN_Msk          
+#define RCC_APB2LPENR_SPI6LPEN_Pos         (21U)                               
+#define RCC_APB2LPENR_SPI6LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB2LPENR_SPI6LPEN             RCC_APB2LPENR_SPI6LPEN_Msk          
+#define RCC_APB2LPENR_SAI1LPEN_Pos         (22U)                               
+#define RCC_APB2LPENR_SAI1LPEN_Msk         (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENR_SAI1LPEN             RCC_APB2LPENR_SAI1LPEN_Msk          
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define RCC_BDCR_LSEON_Pos                 (0U)                                
+#define RCC_BDCR_LSEON_Msk                 (0x1U << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */
+#define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk                  
+#define RCC_BDCR_LSERDY_Pos                (1U)                                
+#define RCC_BDCR_LSERDY_Msk                (0x1U << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk                 
+#define RCC_BDCR_LSEBYP_Pos                (2U)                                
+#define RCC_BDCR_LSEBYP_Msk                (0x1U << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk                 
+
+#define RCC_BDCR_RTCSEL_Pos                (8U)                                
+#define RCC_BDCR_RTCSEL_Msk                (0x3U << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk                 
+#define RCC_BDCR_RTCSEL_0                  (0x1U << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1                  (0x2U << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos                 (15U)                               
+#define RCC_BDCR_RTCEN_Msk                 (0x1U << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk                  
+#define RCC_BDCR_BDRST_Pos                 (16U)                               
+#define RCC_BDCR_BDRST_Msk                 (0x1U << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */
+#define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk                  
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                  (0U)                                
+#define RCC_CSR_LSION_Msk                  (0x1U << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */
+#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk                   
+#define RCC_CSR_LSIRDY_Pos                 (1U)                                
+#define RCC_CSR_LSIRDY_Msk                 (0x1U << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk                  
+#define RCC_CSR_RMVF_Pos                   (24U)                               
+#define RCC_CSR_RMVF_Msk                   (0x1U << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */
+#define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk                    
+#define RCC_CSR_BORRSTF_Pos                (25U)                               
+#define RCC_CSR_BORRSTF_Msk                (0x1U << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */
+#define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk                 
+#define RCC_CSR_PADRSTF_Pos                (26U)                               
+#define RCC_CSR_PADRSTF_Msk                (0x1U << RCC_CSR_PADRSTF_Pos)       /*!< 0x04000000 */
+#define RCC_CSR_PADRSTF                    RCC_CSR_PADRSTF_Msk                 
+#define RCC_CSR_PORRSTF_Pos                (27U)                               
+#define RCC_CSR_PORRSTF_Msk                (0x1U << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk                 
+#define RCC_CSR_SFTRSTF_Pos                (28U)                               
+#define RCC_CSR_SFTRSTF_Msk                (0x1U << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk                 
+#define RCC_CSR_WDGRSTF_Pos                (29U)                               
+#define RCC_CSR_WDGRSTF_Msk                (0x1U << RCC_CSR_WDGRSTF_Pos)       /*!< 0x20000000 */
+#define RCC_CSR_WDGRSTF                    RCC_CSR_WDGRSTF_Msk                 
+#define RCC_CSR_WWDGRSTF_Pos               (30U)                               
+#define RCC_CSR_WWDGRSTF_Msk               (0x1U << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk                
+#define RCC_CSR_LPWRRSTF_Pos               (31U)                               
+#define RCC_CSR_LPWRRSTF_Msk               (0x1U << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk                
+
+/********************  Bit definition for RCC_SSCGR register  *****************/
+#define RCC_SSCGR_MODPER_Pos               (0U)                                
+#define RCC_SSCGR_MODPER_Msk               (0x1FFFU << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk                
+#define RCC_SSCGR_INCSTEP_Pos              (13U)                               
+#define RCC_SSCGR_INCSTEP_Msk              (0x7FFFU << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk               
+#define RCC_SSCGR_SPREADSEL_Pos            (30U)                               
+#define RCC_SSCGR_SPREADSEL_Msk            (0x1U << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk             
+#define RCC_SSCGR_SSCGEN_Pos               (31U)                               
+#define RCC_SSCGR_SSCGEN_Msk               (0x1U << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk                
+
+/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)                                
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk          
+#define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
+#define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
+#define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
+#define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
+#define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
+#define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
+#define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLI2SCFGR_PLLI2SQ_Pos         (24U)                               
+#define RCC_PLLI2SCFGR_PLLI2SQ_Msk         (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ             RCC_PLLI2SCFGR_PLLI2SQ_Msk          
+#define RCC_PLLI2SCFGR_PLLI2SQ_0           (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_1           (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_2           (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLI2SCFGR_PLLI2SQ_3           (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)                               
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk          
+#define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for RCC_PLLSAICFGR register  ************/
+#define RCC_PLLSAICFGR_PLLSAIN_Pos         (6U)                                
+#define RCC_PLLSAICFGR_PLLSAIN_Msk         (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLSAICFGR_PLLSAIN             RCC_PLLSAICFGR_PLLSAIN_Msk          
+#define RCC_PLLSAICFGR_PLLSAIN_0           (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
+#define RCC_PLLSAICFGR_PLLSAIN_1           (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
+#define RCC_PLLSAICFGR_PLLSAIN_2           (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
+#define RCC_PLLSAICFGR_PLLSAIN_3           (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
+#define RCC_PLLSAICFGR_PLLSAIN_4           (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
+#define RCC_PLLSAICFGR_PLLSAIN_5           (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
+#define RCC_PLLSAICFGR_PLLSAIN_6           (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
+#define RCC_PLLSAICFGR_PLLSAIN_7           (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
+#define RCC_PLLSAICFGR_PLLSAIN_8           (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
+
+
+#define RCC_PLLSAICFGR_PLLSAIQ_Pos         (24U)                               
+#define RCC_PLLSAICFGR_PLLSAIQ_Msk         (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ             RCC_PLLSAICFGR_PLLSAIQ_Msk          
+#define RCC_PLLSAICFGR_PLLSAIQ_0           (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_1           (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_2           (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
+#define RCC_PLLSAICFGR_PLLSAIQ_3           (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
+
+#define RCC_PLLSAICFGR_PLLSAIR_Pos         (28U)                               
+#define RCC_PLLSAICFGR_PLLSAIR_Msk         (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
+#define RCC_PLLSAICFGR_PLLSAIR             RCC_PLLSAICFGR_PLLSAIR_Msk          
+#define RCC_PLLSAICFGR_PLLSAIR_0           (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
+#define RCC_PLLSAICFGR_PLLSAIR_1           (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
+#define RCC_PLLSAICFGR_PLLSAIR_2           (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for RCC_DCKCFGR register  ***************/
+#define RCC_DCKCFGR_PLLI2SDIVQ_Pos         (0U)                                
+#define RCC_DCKCFGR_PLLI2SDIVQ_Msk         (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
+#define RCC_DCKCFGR_PLLI2SDIVQ             RCC_DCKCFGR_PLLI2SDIVQ_Msk          
+#define RCC_DCKCFGR_PLLSAIDIVQ_Pos         (8U)                                
+#define RCC_DCKCFGR_PLLSAIDIVQ_Msk         (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
+#define RCC_DCKCFGR_PLLSAIDIVQ             RCC_DCKCFGR_PLLSAIDIVQ_Msk          
+#define RCC_DCKCFGR_PLLSAIDIVR_Pos         (16U)                               
+#define RCC_DCKCFGR_PLLSAIDIVR_Msk         (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
+#define RCC_DCKCFGR_PLLSAIDIVR             RCC_DCKCFGR_PLLSAIDIVR_Msk          
+#define RCC_DCKCFGR_SAI1ASRC_Pos           (20U)                               
+#define RCC_DCKCFGR_SAI1ASRC_Msk           (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00300000 */
+#define RCC_DCKCFGR_SAI1ASRC               RCC_DCKCFGR_SAI1ASRC_Msk            
+#define RCC_DCKCFGR_SAI1ASRC_0             (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00100000 */
+#define RCC_DCKCFGR_SAI1ASRC_1             (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00200000 */
+#define RCC_DCKCFGR_SAI1BSRC_Pos           (22U)                               
+#define RCC_DCKCFGR_SAI1BSRC_Msk           (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00C00000 */
+#define RCC_DCKCFGR_SAI1BSRC               RCC_DCKCFGR_SAI1BSRC_Msk            
+#define RCC_DCKCFGR_SAI1BSRC_0             (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00400000 */
+#define RCC_DCKCFGR_SAI1BSRC_1             (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00800000 */
+#define RCC_DCKCFGR_TIMPRE_Pos             (24U)                               
+#define RCC_DCKCFGR_TIMPRE_Msk             (0x1U << RCC_DCKCFGR_TIMPRE_Pos)    /*!< 0x01000000 */
+#define RCC_DCKCFGR_TIMPRE                 RCC_DCKCFGR_TIMPRE_Msk              
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos    (2U)                                               
+#define RNG_CR_RNGEN_Msk    (0x1U << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
+#define RNG_CR_IE_Pos       (3U)                                               
+#define RNG_CR_IE_Msk       (0x1U << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
+#define RNG_CR_IE           RNG_CR_IE_Msk                                      
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos     (0U)                                               
+#define RNG_SR_DRDY_Msk     (0x1U << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
+#define RNG_SR_CECS_Pos     (1U)                                               
+#define RNG_SR_CECS_Msk     (0x1U << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
+#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
+#define RNG_SR_SECS_Pos     (2U)                                               
+#define RNG_SR_SECS_Msk     (0x1U << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
+#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
+#define RNG_SR_CEIS_Pos     (5U)                                               
+#define RNG_SR_CEIS_Msk     (0x1U << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
+#define RNG_SR_SEIS_Pos     (6U)                                               
+#define RNG_SR_SEIS_Msk     (0x1U << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                 (22U)                                    
+#define RTC_TR_PM_Msk                 (0x1U << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
+#define RTC_TR_PM                     RTC_TR_PM_Msk                            
+#define RTC_TR_HT_Pos                 (20U)                                    
+#define RTC_TR_HT_Msk                 (0x3U << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
+#define RTC_TR_HT                     RTC_TR_HT_Msk                            
+#define RTC_TR_HT_0                   (0x1U << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
+#define RTC_TR_HT_1                   (0x2U << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                 (16U)                                    
+#define RTC_TR_HU_Msk                 (0xFU << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
+#define RTC_TR_HU                     RTC_TR_HU_Msk                            
+#define RTC_TR_HU_0                   (0x1U << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
+#define RTC_TR_HU_1                   (0x2U << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
+#define RTC_TR_HU_2                   (0x4U << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
+#define RTC_TR_HU_3                   (0x8U << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos                (12U)                                    
+#define RTC_TR_MNT_Msk                (0x7U << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
+#define RTC_TR_MNT                    RTC_TR_MNT_Msk                           
+#define RTC_TR_MNT_0                  (0x1U << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
+#define RTC_TR_MNT_1                  (0x2U << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
+#define RTC_TR_MNT_2                  (0x4U << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos                (8U)                                     
+#define RTC_TR_MNU_Msk                (0xFU << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
+#define RTC_TR_MNU                    RTC_TR_MNU_Msk                           
+#define RTC_TR_MNU_0                  (0x1U << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
+#define RTC_TR_MNU_1                  (0x2U << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
+#define RTC_TR_MNU_2                  (0x4U << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
+#define RTC_TR_MNU_3                  (0x8U << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                 (4U)                                     
+#define RTC_TR_ST_Msk                 (0x7U << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
+#define RTC_TR_ST                     RTC_TR_ST_Msk                            
+#define RTC_TR_ST_0                   (0x1U << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
+#define RTC_TR_ST_1                   (0x2U << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
+#define RTC_TR_ST_2                   (0x4U << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                 (0U)                                     
+#define RTC_TR_SU_Msk                 (0xFU << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
+#define RTC_TR_SU                     RTC_TR_SU_Msk                            
+#define RTC_TR_SU_0                   (0x1U << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
+#define RTC_TR_SU_1                   (0x2U << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
+#define RTC_TR_SU_2                   (0x4U << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
+#define RTC_TR_SU_3                   (0x8U << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                 (20U)                                    
+#define RTC_DR_YT_Msk                 (0xFU << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
+#define RTC_DR_YT                     RTC_DR_YT_Msk                            
+#define RTC_DR_YT_0                   (0x1U << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
+#define RTC_DR_YT_1                   (0x2U << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
+#define RTC_DR_YT_2                   (0x4U << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
+#define RTC_DR_YT_3                   (0x8U << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                 (16U)                                    
+#define RTC_DR_YU_Msk                 (0xFU << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
+#define RTC_DR_YU                     RTC_DR_YU_Msk                            
+#define RTC_DR_YU_0                   (0x1U << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
+#define RTC_DR_YU_1                   (0x2U << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
+#define RTC_DR_YU_2                   (0x4U << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
+#define RTC_DR_YU_3                   (0x8U << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos                (13U)                                    
+#define RTC_DR_WDU_Msk                (0x7U << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
+#define RTC_DR_WDU                    RTC_DR_WDU_Msk                           
+#define RTC_DR_WDU_0                  (0x1U << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
+#define RTC_DR_WDU_1                  (0x2U << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
+#define RTC_DR_WDU_2                  (0x4U << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                 (12U)                                    
+#define RTC_DR_MT_Msk                 (0x1U << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
+#define RTC_DR_MT                     RTC_DR_MT_Msk                            
+#define RTC_DR_MU_Pos                 (8U)                                     
+#define RTC_DR_MU_Msk                 (0xFU << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
+#define RTC_DR_MU                     RTC_DR_MU_Msk                            
+#define RTC_DR_MU_0                   (0x1U << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
+#define RTC_DR_MU_1                   (0x2U << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
+#define RTC_DR_MU_2                   (0x4U << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
+#define RTC_DR_MU_3                   (0x8U << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                 (4U)                                     
+#define RTC_DR_DT_Msk                 (0x3U << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
+#define RTC_DR_DT                     RTC_DR_DT_Msk                            
+#define RTC_DR_DT_0                   (0x1U << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
+#define RTC_DR_DT_1                   (0x2U << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                 (0U)                                     
+#define RTC_DR_DU_Msk                 (0xFU << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
+#define RTC_DR_DU                     RTC_DR_DU_Msk                            
+#define RTC_DR_DU_0                   (0x1U << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
+#define RTC_DR_DU_1                   (0x2U << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
+#define RTC_DR_DU_2                   (0x4U << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
+#define RTC_DR_DU_3                   (0x8U << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_COE_Pos                (23U)                                    
+#define RTC_CR_COE_Msk                (0x1U << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
+#define RTC_CR_COE                    RTC_CR_COE_Msk                           
+#define RTC_CR_OSEL_Pos               (21U)                                    
+#define RTC_CR_OSEL_Msk               (0x3U << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
+#define RTC_CR_OSEL                   RTC_CR_OSEL_Msk                          
+#define RTC_CR_OSEL_0                 (0x1U << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                 (0x2U << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
+#define RTC_CR_POL_Pos                (20U)                                    
+#define RTC_CR_POL_Msk                (0x1U << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
+#define RTC_CR_POL                    RTC_CR_POL_Msk                           
+#define RTC_CR_COSEL_Pos              (19U)                                    
+#define RTC_CR_COSEL_Msk              (0x1U << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
+#define RTC_CR_COSEL                  RTC_CR_COSEL_Msk                         
+#define RTC_CR_BCK_Pos                (18U)                                    
+#define RTC_CR_BCK_Msk                (0x1U << RTC_CR_BCK_Pos)                 /*!< 0x00040000 */
+#define RTC_CR_BCK                    RTC_CR_BCK_Msk                           
+#define RTC_CR_SUB1H_Pos              (17U)                                    
+#define RTC_CR_SUB1H_Msk              (0x1U << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
+#define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk                         
+#define RTC_CR_ADD1H_Pos              (16U)                                    
+#define RTC_CR_ADD1H_Msk              (0x1U << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
+#define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk                         
+#define RTC_CR_TSIE_Pos               (15U)                                    
+#define RTC_CR_TSIE_Msk               (0x1U << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
+#define RTC_CR_TSIE                   RTC_CR_TSIE_Msk                          
+#define RTC_CR_WUTIE_Pos              (14U)                                    
+#define RTC_CR_WUTIE_Msk              (0x1U << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
+#define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk                         
+#define RTC_CR_ALRBIE_Pos             (13U)                                    
+#define RTC_CR_ALRBIE_Msk             (0x1U << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk                        
+#define RTC_CR_ALRAIE_Pos             (12U)                                    
+#define RTC_CR_ALRAIE_Msk             (0x1U << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk                        
+#define RTC_CR_TSE_Pos                (11U)                                    
+#define RTC_CR_TSE_Msk                (0x1U << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
+#define RTC_CR_TSE                    RTC_CR_TSE_Msk                           
+#define RTC_CR_WUTE_Pos               (10U)                                    
+#define RTC_CR_WUTE_Msk               (0x1U << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
+#define RTC_CR_WUTE                   RTC_CR_WUTE_Msk                          
+#define RTC_CR_ALRBE_Pos              (9U)                                     
+#define RTC_CR_ALRBE_Msk              (0x1U << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
+#define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk                         
+#define RTC_CR_ALRAE_Pos              (8U)                                     
+#define RTC_CR_ALRAE_Msk              (0x1U << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
+#define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk                         
+#define RTC_CR_DCE_Pos                (7U)                                     
+#define RTC_CR_DCE_Msk                (0x1U << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */
+#define RTC_CR_DCE                    RTC_CR_DCE_Msk                           
+#define RTC_CR_FMT_Pos                (6U)                                     
+#define RTC_CR_FMT_Msk                (0x1U << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
+#define RTC_CR_FMT                    RTC_CR_FMT_Msk                           
+#define RTC_CR_BYPSHAD_Pos            (5U)                                     
+#define RTC_CR_BYPSHAD_Msk            (0x1U << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk                       
+#define RTC_CR_REFCKON_Pos            (4U)                                     
+#define RTC_CR_REFCKON_Msk            (0x1U << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
+#define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk                       
+#define RTC_CR_TSEDGE_Pos             (3U)                                     
+#define RTC_CR_TSEDGE_Msk             (0x1U << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk                        
+#define RTC_CR_WUCKSEL_Pos            (0U)                                     
+#define RTC_CR_WUCKSEL_Msk            (0x7U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk                       
+#define RTC_CR_WUCKSEL_0              (0x1U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1              (0x2U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2              (0x4U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF_Pos           (16U)                                    
+#define RTC_ISR_RECALPF_Msk           (0x1U << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */
+#define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk                      
+#define RTC_ISR_TAMP1F_Pos            (13U)                                    
+#define RTC_ISR_TAMP1F_Msk            (0x1U << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk                       
+#define RTC_ISR_TAMP2F_Pos            (14U)                                    
+#define RTC_ISR_TAMP2F_Msk            (0x1U << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk                       
+#define RTC_ISR_TSOVF_Pos             (12U)                                    
+#define RTC_ISR_TSOVF_Msk             (0x1U << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk                        
+#define RTC_ISR_TSF_Pos               (11U)                                    
+#define RTC_ISR_TSF_Msk               (0x1U << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */
+#define RTC_ISR_TSF                   RTC_ISR_TSF_Msk                          
+#define RTC_ISR_WUTF_Pos              (10U)                                    
+#define RTC_ISR_WUTF_Msk              (0x1U << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */
+#define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk                         
+#define RTC_ISR_ALRBF_Pos             (9U)                                     
+#define RTC_ISR_ALRBF_Msk             (0x1U << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk                        
+#define RTC_ISR_ALRAF_Pos             (8U)                                     
+#define RTC_ISR_ALRAF_Msk             (0x1U << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk                        
+#define RTC_ISR_INIT_Pos              (7U)                                     
+#define RTC_ISR_INIT_Msk              (0x1U << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */
+#define RTC_ISR_INIT                  RTC_ISR_INIT_Msk                         
+#define RTC_ISR_INITF_Pos             (6U)                                     
+#define RTC_ISR_INITF_Msk             (0x1U << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */
+#define RTC_ISR_INITF                 RTC_ISR_INITF_Msk                        
+#define RTC_ISR_RSF_Pos               (5U)                                     
+#define RTC_ISR_RSF_Msk               (0x1U << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */
+#define RTC_ISR_RSF                   RTC_ISR_RSF_Msk                          
+#define RTC_ISR_INITS_Pos             (4U)                                     
+#define RTC_ISR_INITS_Msk             (0x1U << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */
+#define RTC_ISR_INITS                 RTC_ISR_INITS_Msk                        
+#define RTC_ISR_SHPF_Pos              (3U)                                     
+#define RTC_ISR_SHPF_Msk              (0x1U << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */
+#define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk                         
+#define RTC_ISR_WUTWF_Pos             (2U)                                     
+#define RTC_ISR_WUTWF_Msk             (0x1U << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk                        
+#define RTC_ISR_ALRBWF_Pos            (1U)                                     
+#define RTC_ISR_ALRBWF_Msk            (0x1U << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk                       
+#define RTC_ISR_ALRAWF_Pos            (0U)                                     
+#define RTC_ISR_ALRAWF_Msk            (0x1U << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk                       
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos         (16U)                                    
+#define RTC_PRER_PREDIV_A_Msk         (0x7FU << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk                    
+#define RTC_PRER_PREDIV_S_Pos         (0U)                                     
+#define RTC_PRER_PREDIV_S_Msk         (0x7FFFU << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk                    
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos              (0U)                                     
+#define RTC_WUTR_WUT_Msk              (0xFFFFU << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk                         
+
+/********************  Bits definition for RTC_CALIBR register  ***************/
+#define RTC_CALIBR_DCS_Pos            (7U)                                     
+#define RTC_CALIBR_DCS_Msk            (0x1U << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */
+#define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk                       
+#define RTC_CALIBR_DC_Pos             (0U)                                     
+#define RTC_CALIBR_DC_Msk             (0x1FU << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */
+#define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk                        
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos           (31U)                                    
+#define RTC_ALRMAR_MSK4_Msk           (0x1U << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk                      
+#define RTC_ALRMAR_WDSEL_Pos          (30U)                                    
+#define RTC_ALRMAR_WDSEL_Msk          (0x1U << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk                     
+#define RTC_ALRMAR_DT_Pos             (28U)                                    
+#define RTC_ALRMAR_DT_Msk             (0x3U << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk                        
+#define RTC_ALRMAR_DT_0               (0x1U << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1               (0x2U << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos             (24U)                                    
+#define RTC_ALRMAR_DU_Msk             (0xFU << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk                        
+#define RTC_ALRMAR_DU_0               (0x1U << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1               (0x2U << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2               (0x4U << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3               (0x8U << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos           (23U)                                    
+#define RTC_ALRMAR_MSK3_Msk           (0x1U << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk                      
+#define RTC_ALRMAR_PM_Pos             (22U)                                    
+#define RTC_ALRMAR_PM_Msk             (0x1U << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk                        
+#define RTC_ALRMAR_HT_Pos             (20U)                                    
+#define RTC_ALRMAR_HT_Msk             (0x3U << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk                        
+#define RTC_ALRMAR_HT_0               (0x1U << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1               (0x2U << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos             (16U)                                    
+#define RTC_ALRMAR_HU_Msk             (0xFU << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk                        
+#define RTC_ALRMAR_HU_0               (0x1U << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1               (0x2U << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2               (0x4U << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3               (0x8U << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos           (15U)                                    
+#define RTC_ALRMAR_MSK2_Msk           (0x1U << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk                      
+#define RTC_ALRMAR_MNT_Pos            (12U)                                    
+#define RTC_ALRMAR_MNT_Msk            (0x7U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk                       
+#define RTC_ALRMAR_MNT_0              (0x1U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1              (0x2U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2              (0x4U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos            (8U)                                     
+#define RTC_ALRMAR_MNU_Msk            (0xFU << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk                       
+#define RTC_ALRMAR_MNU_0              (0x1U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1              (0x2U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2              (0x4U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3              (0x8U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos           (7U)                                     
+#define RTC_ALRMAR_MSK1_Msk           (0x1U << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk                      
+#define RTC_ALRMAR_ST_Pos             (4U)                                     
+#define RTC_ALRMAR_ST_Msk             (0x7U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk                        
+#define RTC_ALRMAR_ST_0               (0x1U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1               (0x2U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2               (0x4U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos             (0U)                                     
+#define RTC_ALRMAR_SU_Msk             (0xFU << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk                        
+#define RTC_ALRMAR_SU_0               (0x1U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1               (0x2U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2               (0x4U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3               (0x8U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos           (31U)                                    
+#define RTC_ALRMBR_MSK4_Msk           (0x1U << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk                      
+#define RTC_ALRMBR_WDSEL_Pos          (30U)                                    
+#define RTC_ALRMBR_WDSEL_Msk          (0x1U << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk                     
+#define RTC_ALRMBR_DT_Pos             (28U)                                    
+#define RTC_ALRMBR_DT_Msk             (0x3U << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk                        
+#define RTC_ALRMBR_DT_0               (0x1U << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1               (0x2U << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos             (24U)                                    
+#define RTC_ALRMBR_DU_Msk             (0xFU << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk                        
+#define RTC_ALRMBR_DU_0               (0x1U << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1               (0x2U << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2               (0x4U << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3               (0x8U << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos           (23U)                                    
+#define RTC_ALRMBR_MSK3_Msk           (0x1U << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk                      
+#define RTC_ALRMBR_PM_Pos             (22U)                                    
+#define RTC_ALRMBR_PM_Msk             (0x1U << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk                        
+#define RTC_ALRMBR_HT_Pos             (20U)                                    
+#define RTC_ALRMBR_HT_Msk             (0x3U << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk                        
+#define RTC_ALRMBR_HT_0               (0x1U << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1               (0x2U << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos             (16U)                                    
+#define RTC_ALRMBR_HU_Msk             (0xFU << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk                        
+#define RTC_ALRMBR_HU_0               (0x1U << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1               (0x2U << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2               (0x4U << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3               (0x8U << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos           (15U)                                    
+#define RTC_ALRMBR_MSK2_Msk           (0x1U << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk                      
+#define RTC_ALRMBR_MNT_Pos            (12U)                                    
+#define RTC_ALRMBR_MNT_Msk            (0x7U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk                       
+#define RTC_ALRMBR_MNT_0              (0x1U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1              (0x2U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2              (0x4U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos            (8U)                                     
+#define RTC_ALRMBR_MNU_Msk            (0xFU << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk                       
+#define RTC_ALRMBR_MNU_0              (0x1U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1              (0x2U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2              (0x4U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3              (0x8U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos           (7U)                                     
+#define RTC_ALRMBR_MSK1_Msk           (0x1U << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk                      
+#define RTC_ALRMBR_ST_Pos             (4U)                                     
+#define RTC_ALRMBR_ST_Msk             (0x7U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk                        
+#define RTC_ALRMBR_ST_0               (0x1U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1               (0x2U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2               (0x4U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos             (0U)                                     
+#define RTC_ALRMBR_SU_Msk             (0xFU << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk                        
+#define RTC_ALRMBR_SU_0               (0x1U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1               (0x2U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2               (0x4U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3               (0x8U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos               (0U)                                     
+#define RTC_WPR_KEY_Msk               (0xFFU << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
+#define RTC_WPR_KEY                   RTC_WPR_KEY_Msk                          
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                (0U)                                     
+#define RTC_SSR_SS_Msk                (0xFFFFU << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */
+#define RTC_SSR_SS                    RTC_SSR_SS_Msk                           
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos          (0U)                                     
+#define RTC_SHIFTR_SUBFS_Msk          (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk                     
+#define RTC_SHIFTR_ADD1S_Pos          (31U)                                    
+#define RTC_SHIFTR_ADD1S_Msk          (0x1U << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk                     
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos               (22U)                                    
+#define RTC_TSTR_PM_Msk               (0x1U << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
+#define RTC_TSTR_PM                   RTC_TSTR_PM_Msk                          
+#define RTC_TSTR_HT_Pos               (20U)                                    
+#define RTC_TSTR_HT_Msk               (0x3U << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
+#define RTC_TSTR_HT                   RTC_TSTR_HT_Msk                          
+#define RTC_TSTR_HT_0                 (0x1U << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                 (0x2U << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos               (16U)                                    
+#define RTC_TSTR_HU_Msk               (0xFU << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
+#define RTC_TSTR_HU                   RTC_TSTR_HU_Msk                          
+#define RTC_TSTR_HU_0                 (0x1U << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                 (0x2U << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                 (0x4U << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                 (0x8U << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos              (12U)                                    
+#define RTC_TSTR_MNT_Msk              (0x7U << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
+#define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk                         
+#define RTC_TSTR_MNT_0                (0x1U << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                (0x2U << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                (0x4U << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos              (8U)                                     
+#define RTC_TSTR_MNU_Msk              (0xFU << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk                         
+#define RTC_TSTR_MNU_0                (0x1U << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                (0x2U << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                (0x4U << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                (0x8U << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos               (4U)                                     
+#define RTC_TSTR_ST_Msk               (0x7U << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
+#define RTC_TSTR_ST                   RTC_TSTR_ST_Msk                          
+#define RTC_TSTR_ST_0                 (0x1U << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                 (0x2U << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                 (0x4U << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos               (0U)                                     
+#define RTC_TSTR_SU_Msk               (0xFU << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
+#define RTC_TSTR_SU                   RTC_TSTR_SU_Msk                          
+#define RTC_TSTR_SU_0                 (0x1U << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                 (0x2U << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                 (0x4U << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                 (0x8U << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos              (13U)                                    
+#define RTC_TSDR_WDU_Msk              (0x7U << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk                         
+#define RTC_TSDR_WDU_0                (0x1U << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                (0x2U << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                (0x4U << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos               (12U)                                    
+#define RTC_TSDR_MT_Msk               (0x1U << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
+#define RTC_TSDR_MT                   RTC_TSDR_MT_Msk                          
+#define RTC_TSDR_MU_Pos               (8U)                                     
+#define RTC_TSDR_MU_Msk               (0xFU << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
+#define RTC_TSDR_MU                   RTC_TSDR_MU_Msk                          
+#define RTC_TSDR_MU_0                 (0x1U << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                 (0x2U << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                 (0x4U << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                 (0x8U << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos               (4U)                                     
+#define RTC_TSDR_DT_Msk               (0x3U << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
+#define RTC_TSDR_DT                   RTC_TSDR_DT_Msk                          
+#define RTC_TSDR_DT_0                 (0x1U << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                 (0x2U << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos               (0U)                                     
+#define RTC_TSDR_DU_Msk               (0xFU << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
+#define RTC_TSDR_DU                   RTC_TSDR_DU_Msk                          
+#define RTC_TSDR_DU_0                 (0x1U << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                 (0x2U << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                 (0x4U << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                 (0x8U << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos              (0U)                                     
+#define RTC_TSSSR_SS_Msk              (0xFFFFU << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk                         
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP_Pos             (15U)                                    
+#define RTC_CALR_CALP_Msk             (0x1U << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
+#define RTC_CALR_CALP                 RTC_CALR_CALP_Msk                        
+#define RTC_CALR_CALW8_Pos            (14U)                                    
+#define RTC_CALR_CALW8_Msk            (0x1U << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
+#define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk                       
+#define RTC_CALR_CALW16_Pos           (13U)                                    
+#define RTC_CALR_CALW16_Msk           (0x1U << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
+#define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk                      
+#define RTC_CALR_CALM_Pos             (0U)                                     
+#define RTC_CALR_CALM_Msk             (0x1FFU << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
+#define RTC_CALR_CALM                 RTC_CALR_CALM_Msk                        
+#define RTC_CALR_CALM_0               (0x001U << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
+#define RTC_CALR_CALM_1               (0x002U << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
+#define RTC_CALR_CALM_2               (0x004U << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
+#define RTC_CALR_CALM_3               (0x008U << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
+#define RTC_CALR_CALM_4               (0x010U << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
+#define RTC_CALR_CALM_5               (0x020U << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
+#define RTC_CALR_CALM_6               (0x040U << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
+#define RTC_CALR_CALM_7               (0x080U << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
+#define RTC_CALR_CALM_8               (0x100U << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)                                    
+#define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk               
+#define RTC_TAFCR_TSINSEL_Pos         (17U)                                    
+#define RTC_TAFCR_TSINSEL_Msk         (0x1U << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk                    
+#define RTC_TAFCR_TAMPINSEL_Pos       (16U)                                    
+#define RTC_TAFCR_TAMPINSEL_Msk       (0x1U << RTC_TAFCR_TAMPINSEL_Pos)        /*!< 0x00010000 */
+#define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMPINSEL_Msk                  
+#define RTC_TAFCR_TAMPPUDIS_Pos       (15U)                                    
+#define RTC_TAFCR_TAMPPUDIS_Msk       (0x1U << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk                  
+#define RTC_TAFCR_TAMPPRCH_Pos        (13U)                                    
+#define RTC_TAFCR_TAMPPRCH_Msk        (0x3U << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk                   
+#define RTC_TAFCR_TAMPPRCH_0          (0x1U << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1          (0x2U << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos         (11U)                                    
+#define RTC_TAFCR_TAMPFLT_Msk         (0x3U << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk                    
+#define RTC_TAFCR_TAMPFLT_0           (0x1U << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1           (0x2U << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos        (8U)                                     
+#define RTC_TAFCR_TAMPFREQ_Msk        (0x7U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk                   
+#define RTC_TAFCR_TAMPFREQ_0          (0x1U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1          (0x2U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2          (0x4U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos          (7U)                                     
+#define RTC_TAFCR_TAMPTS_Msk          (0x1U << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk                     
+#define RTC_TAFCR_TAMP2TRG_Pos        (4U)                                     
+#define RTC_TAFCR_TAMP2TRG_Msk        (0x1U << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk                   
+#define RTC_TAFCR_TAMP2E_Pos          (3U)                                     
+#define RTC_TAFCR_TAMP2E_Msk          (0x1U << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk                     
+#define RTC_TAFCR_TAMPIE_Pos          (2U)                                     
+#define RTC_TAFCR_TAMPIE_Msk          (0x1U << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk                     
+#define RTC_TAFCR_TAMP1TRG_Pos        (1U)                                     
+#define RTC_TAFCR_TAMP1TRG_Msk        (0x1U << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk                   
+#define RTC_TAFCR_TAMP1E_Pos          (0U)                                     
+#define RTC_TAFCR_TAMP1E_Msk          (0x1U << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk                     
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos       (24U)                                    
+#define RTC_ALRMASSR_MASKSS_Msk       (0xFU << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk                  
+#define RTC_ALRMASSR_MASKSS_0         (0x1U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1         (0x2U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2         (0x4U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3         (0x8U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos           (0U)                                     
+#define RTC_ALRMASSR_SS_Msk           (0x7FFFU << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk                      
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos       (24U)                                    
+#define RTC_ALRMBSSR_MASKSS_Msk       (0xFU << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk                  
+#define RTC_ALRMBSSR_MASKSS_0         (0x1U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1         (0x2U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2         (0x4U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3         (0x8U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos           (0U)                                     
+#define RTC_ALRMBSSR_SS_Msk           (0x7FFFU << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk                      
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                 (0U)                                     
+#define RTC_BKP0R_Msk                 (0xFFFFFFFFU << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                     RTC_BKP0R_Msk                            
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                 (0U)                                     
+#define RTC_BKP1R_Msk                 (0xFFFFFFFFU << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                     RTC_BKP1R_Msk                            
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                 (0U)                                     
+#define RTC_BKP2R_Msk                 (0xFFFFFFFFU << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                     RTC_BKP2R_Msk                            
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                 (0U)                                     
+#define RTC_BKP3R_Msk                 (0xFFFFFFFFU << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                     RTC_BKP3R_Msk                            
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                 (0U)                                     
+#define RTC_BKP4R_Msk                 (0xFFFFFFFFU << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                     RTC_BKP4R_Msk                            
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R_Pos                 (0U)                                     
+#define RTC_BKP5R_Msk                 (0xFFFFFFFFU << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP5R                     RTC_BKP5R_Msk                            
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R_Pos                 (0U)                                     
+#define RTC_BKP6R_Msk                 (0xFFFFFFFFU << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP6R                     RTC_BKP6R_Msk                            
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R_Pos                 (0U)                                     
+#define RTC_BKP7R_Msk                 (0xFFFFFFFFU << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP7R                     RTC_BKP7R_Msk                            
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R_Pos                 (0U)                                     
+#define RTC_BKP8R_Msk                 (0xFFFFFFFFU << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP8R                     RTC_BKP8R_Msk                            
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R_Pos                 (0U)                                     
+#define RTC_BKP9R_Msk                 (0xFFFFFFFFU << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP9R                     RTC_BKP9R_Msk                            
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R_Pos                (0U)                                     
+#define RTC_BKP10R_Msk                (0xFFFFFFFFU << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP10R                    RTC_BKP10R_Msk                           
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R_Pos                (0U)                                     
+#define RTC_BKP11R_Msk                (0xFFFFFFFFU << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP11R                    RTC_BKP11R_Msk                           
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R_Pos                (0U)                                     
+#define RTC_BKP12R_Msk                (0xFFFFFFFFU << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP12R                    RTC_BKP12R_Msk                           
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R_Pos                (0U)                                     
+#define RTC_BKP13R_Msk                (0xFFFFFFFFU << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP13R                    RTC_BKP13R_Msk                           
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R_Pos                (0U)                                     
+#define RTC_BKP14R_Msk                (0xFFFFFFFFU << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP14R                    RTC_BKP14R_Msk                           
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R_Pos                (0U)                                     
+#define RTC_BKP15R_Msk                (0xFFFFFFFFU << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP15R                    RTC_BKP15R_Msk                           
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R_Pos                (0U)                                     
+#define RTC_BKP16R_Msk                (0xFFFFFFFFU << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP16R                    RTC_BKP16R_Msk                           
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R_Pos                (0U)                                     
+#define RTC_BKP17R_Msk                (0xFFFFFFFFU << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP17R                    RTC_BKP17R_Msk                           
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R_Pos                (0U)                                     
+#define RTC_BKP18R_Msk                (0xFFFFFFFFU << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP18R                    RTC_BKP18R_Msk                           
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R_Pos                (0U)                                     
+#define RTC_BKP19R_Msk                (0xFFFFFFFFU << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP19R                    RTC_BKP19R_Msk                           
+    
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos         (0U)                                        
+#define SAI_GCR_SYNCIN_Msk         (0x3U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0           (0x1U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1           (0x2U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos        (4U)                                        
+#define SAI_GCR_SYNCOUT_Msk        (0x3U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0          (0x1U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1          (0x2U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos          (0U)                                        
+#define SAI_xCR1_MODE_Msk          (0x3U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */
+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0            (0x1U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1            (0x2U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos        (2U)                                        
+#define SAI_xCR1_PRTCFG_Msk        (0x3U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0          (0x1U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1          (0x2U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos            (5U)                                        
+#define SAI_xCR1_DS_Msk            (0x7U << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */
+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0              (0x1U << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
+#define SAI_xCR1_DS_1              (0x2U << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
+#define SAI_xCR1_DS_2              (0x4U << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos      (8U)                                        
+#define SAI_xCR1_LSBFIRST_Msk      (0x1U << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos         (9U)                                        
+#define SAI_xCR1_CKSTR_Msk         (0x1U << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
+
+#define SAI_xCR1_SYNCEN_Pos        (10U)                                       
+#define SAI_xCR1_SYNCEN_Msk        (0x3U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0          (0x1U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1          (0x2U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos          (12U)                                       
+#define SAI_xCR1_MONO_Msk          (0x1U << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */
+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos       (13U)                                       
+#define SAI_xCR1_OUTDRIV_Msk       (0x1U << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos         (16U)                                       
+#define SAI_xCR1_SAIEN_Msk         (0x1U << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos         (17U)                                       
+#define SAI_xCR1_DMAEN_Msk         (0x1U << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos         (19U)                                       
+#define SAI_xCR1_NODIV_Msk         (0x1U << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */
+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
+
+#define SAI_xCR1_MCKDIV_Pos        (20U)                                       
+#define SAI_xCR1_MCKDIV_Msk        (0xFU << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */
+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0          (0x1U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00100000 */
+#define SAI_xCR1_MCKDIV_1          (0x2U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00200000 */
+#define SAI_xCR1_MCKDIV_2          (0x4U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00400000 */
+#define SAI_xCR1_MCKDIV_3          (0x8U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00800000 */
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos           (0U)                                        
+#define SAI_xCR2_FTH_Msk           (0x7U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */
+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0             (0x1U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1             (0x2U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2             (0x4U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos        (3U)                                        
+#define SAI_xCR2_FFLUSH_Msk        (0x1U << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos          (4U)                                        
+#define SAI_xCR2_TRIS_Msk          (0x1U << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */
+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos          (5U)                                        
+#define SAI_xCR2_MUTE_Msk          (0x1U << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */
+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos       (6U)                                        
+#define SAI_xCR2_MUTEVAL_Msk       (0x1U << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
+
+#define SAI_xCR2_MUTECNT_Pos       (7U)                                        
+#define SAI_xCR2_MUTECNT_Msk       (0x3FU << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0         (0x01U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1         (0x02U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2         (0x04U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3         (0x08U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4         (0x10U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5         (0x20U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos           (13U)                                       
+#define SAI_xCR2_CPL_Msk           (0x1U << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */
+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */
+
+#define SAI_xCR2_COMP_Pos          (14U)                                       
+#define SAI_xCR2_COMP_Msk          (0x3U << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */
+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0            (0x1U << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1            (0x2U << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos          (0U)                                        
+#define SAI_xFRCR_FRL_Msk          (0xFFU << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */
+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[1:0](Frame length)  */
+#define SAI_xFRCR_FRL_0            (0x01U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1            (0x02U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2            (0x04U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3            (0x08U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4            (0x10U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5            (0x20U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6            (0x40U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7            (0x80U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos        (8U)                                        
+#define SAI_xFRCR_FSALL_Msk        (0x7FU << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[1:0] (Frame synchronization active level length)  */
+#define SAI_xFRCR_FSALL_0          (0x01U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1          (0x02U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2          (0x04U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3          (0x08U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4          (0x10U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5          (0x20U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6          (0x40U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos        (16U)                                       
+#define SAI_xFRCR_FSDEF_Msk        (0x1U << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
+#define SAI_xFRCR_FSPOL_Pos        (17U)                                       
+#define SAI_xFRCR_FSPOL_Msk        (0x1U << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos        (18U)                                       
+#define SAI_xFRCR_FSOFF_Msk        (0x1U << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
+/* Legacy defines */
+#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos       (0U)                                        
+#define SAI_xSLOTR_FBOFF_Msk       (0x1FU << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0         (0x01U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1         (0x02U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2         (0x04U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3         (0x08U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4         (0x10U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)                                        
+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0        (0x1U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1        (0x2U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos      (8U)                                        
+#define SAI_xSLOTR_NBSLOT_Msk      (0xFU << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0        (0x1U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1        (0x2U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2        (0x4U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3        (0x8U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos      (16U)                                       
+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos      (0U)                                        
+#define SAI_xIMR_OVRUDRIE_Msk      (0x1U << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos     (1U)                                        
+#define SAI_xIMR_MUTEDETIE_Msk     (0x1U << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos      (2U)                                        
+#define SAI_xIMR_WCKCFGIE_Msk      (0x1U << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos        (3U)                                        
+#define SAI_xIMR_FREQIE_Msk        (0x1U << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos       (4U)                                        
+#define SAI_xIMR_CNRDYIE_Msk       (0x1U << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos      (5U)                                        
+#define SAI_xIMR_AFSDETIE_Msk      (0x1U << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos      (6U)                                        
+#define SAI_xIMR_LFSDETIE_Msk      (0x1U << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos         (0U)                                        
+#define SAI_xSR_OVRUDR_Msk         (0x1U << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos        (1U)                                        
+#define SAI_xSR_MUTEDET_Msk        (0x1U << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos         (2U)                                        
+#define SAI_xSR_WCKCFG_Msk         (0x1U << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos           (3U)                                        
+#define SAI_xSR_FREQ_Msk           (0x1U << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */
+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos          (4U)                                        
+#define SAI_xSR_CNRDY_Msk          (0x1U << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */
+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos         (5U)                                        
+#define SAI_xSR_AFSDET_Msk         (0x1U << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */
+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos         (6U)                                        
+#define SAI_xSR_LFSDET_Msk         (0x1U << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */
+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
+
+#define SAI_xSR_FLVL_Pos           (16U)                                       
+#define SAI_xSR_FLVL_Msk           (0x7U << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */
+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0             (0x1U << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1             (0x2U << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2             (0x4U << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos     (0U)                                        
+#define SAI_xCLRFR_COVRUDR_Msk     (0x1U << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)                                        
+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1U << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)                                        
+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1U << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos       (3U)                                        
+#define SAI_xCLRFR_CFREQ_Msk       (0x1U << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos      (4U)                                        
+#define SAI_xCLRFR_CCNRDY_Msk      (0x1U << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos     (5U)                                        
+#define SAI_xCLRFR_CAFSDET_Msk     (0x1U << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos     (6U)                                        
+#define SAI_xCLRFR_CLFSDET_Msk     (0x1U << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  ******************/
+#define SAI_xDR_DATA_Pos           (0U)                                        
+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFU << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk                            
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          SD host Interface                                 */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDIO_POWER register  ******************/
+#define SDIO_POWER_PWRCTRL_Pos         (0U)                                    
+#define SDIO_POWER_PWRCTRL_Msk         (0x3U << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0           (0x1U << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1           (0x2U << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */
+
+/******************  Bit definition for SDIO_CLKCR register  ******************/
+#define SDIO_CLKCR_CLKDIV_Pos          (0U)                                    
+#define SDIO_CLKCR_CLKDIV_Msk          (0xFFU << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */
+#define SDIO_CLKCR_CLKEN_Pos           (8U)                                    
+#define SDIO_CLKCR_CLKEN_Msk           (0x1U << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */
+#define SDIO_CLKCR_PWRSAV_Pos          (9U)                                    
+#define SDIO_CLKCR_PWRSAV_Msk          (0x1U << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */
+#define SDIO_CLKCR_BYPASS_Pos          (10U)                                   
+#define SDIO_CLKCR_BYPASS_Msk          (0x1U << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos          (11U)                                   
+#define SDIO_CLKCR_WIDBUS_Msk          (0x3U << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0            (0x1U << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1            (0x2U << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos         (13U)                                   
+#define SDIO_CLKCR_NEGEDGE_Msk         (0x1U << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos         (14U)                                   
+#define SDIO_CLKCR_HWFC_EN_Msk         (0x1U << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */
+
+/*******************  Bit definition for SDIO_ARG register  *******************/
+#define SDIO_ARG_CMDARG_Pos            (0U)                                    
+#define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */
+
+/*******************  Bit definition for SDIO_CMD register  *******************/
+#define SDIO_CMD_CMDINDEX_Pos          (0U)                                    
+#define SDIO_CMD_CMDINDEX_Msk          (0x3FU << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */
+
+#define SDIO_CMD_WAITRESP_Pos          (6U)                                    
+#define SDIO_CMD_WAITRESP_Msk          (0x3U << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0            (0x1U << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1            (0x2U << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos           (8U)                                    
+#define SDIO_CMD_WAITINT_Msk           (0x1U << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */
+#define SDIO_CMD_WAITPEND_Pos          (9U)                                    
+#define SDIO_CMD_WAITPEND_Msk          (0x1U << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos            (10U)                                   
+#define SDIO_CMD_CPSMEN_Msk            (0x1U << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDIO_CMD_SDIOSUSPEND_Pos       (11U)                                   
+#define SDIO_CMD_SDIOSUSPEND_Msk       (0x1U << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */
+#define SDIO_CMD_ENCMDCOMPL_Pos        (12U)                                   
+#define SDIO_CMD_ENCMDCOMPL_Msk        (0x1U << SDIO_CMD_ENCMDCOMPL_Pos)       /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL            SDIO_CMD_ENCMDCOMPL_Msk                 /*!<Enable CMD completion                                          */
+#define SDIO_CMD_NIEN_Pos              (13U)                                   
+#define SDIO_CMD_NIEN_Msk              (0x1U << SDIO_CMD_NIEN_Pos)             /*!< 0x00002000 */
+#define SDIO_CMD_NIEN                  SDIO_CMD_NIEN_Msk                       /*!<Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD_Pos          (14U)                                   
+#define SDIO_CMD_CEATACMD_Msk          (0x1U << SDIO_CMD_CEATACMD_Pos)         /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD              SDIO_CMD_CEATACMD_Msk                   /*!<CE-ATA command       */
+
+/*****************  Bit definition for SDIO_RESPCMD register  *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos       (0U)                                    
+#define SDIO_RESPCMD_RESPCMD_Msk       (0x3FU << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */
+
+/******************  Bit definition for SDIO_RESP0 register  ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos     (0U)                                    
+#define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP1 register  ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos     (0U)                                    
+#define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP2 register  ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos     (0U)                                    
+#define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP3 register  ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos     (0U)                                    
+#define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP4 register  ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos     (0U)                                    
+#define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */
+
+/******************  Bit definition for SDIO_DTIMER register  *****************/
+#define SDIO_DTIMER_DATATIME_Pos       (0U)                                    
+#define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */
+
+/******************  Bit definition for SDIO_DLEN register  *******************/
+#define SDIO_DLEN_DATALENGTH_Pos       (0U)                                    
+#define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */
+
+/******************  Bit definition for SDIO_DCTRL register  ******************/
+#define SDIO_DCTRL_DTEN_Pos            (0U)                                    
+#define SDIO_DCTRL_DTEN_Msk            (0x1U << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */
+#define SDIO_DCTRL_DTDIR_Pos           (1U)                                    
+#define SDIO_DCTRL_DTDIR_Msk           (0x1U << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos          (2U)                                    
+#define SDIO_DCTRL_DTMODE_Msk          (0x1U << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */
+#define SDIO_DCTRL_DMAEN_Pos           (3U)                                    
+#define SDIO_DCTRL_DMAEN_Msk           (0x1U << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)                                    
+#define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0        (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1        (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2        (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3        (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos         (8U)                                    
+#define SDIO_DCTRL_RWSTART_Msk         (0x1U << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */
+#define SDIO_DCTRL_RWSTOP_Pos          (9U)                                    
+#define SDIO_DCTRL_RWSTOP_Msk          (0x1U << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */
+#define SDIO_DCTRL_RWMOD_Pos           (10U)                                   
+#define SDIO_DCTRL_RWMOD_Msk           (0x1U << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */
+#define SDIO_DCTRL_SDIOEN_Pos          (11U)                                   
+#define SDIO_DCTRL_SDIOEN_Msk          (0x1U << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */
+
+/******************  Bit definition for SDIO_DCOUNT register  *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos      (0U)                                    
+#define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */
+
+/******************  Bit definition for SDIO_STA register  ********************/
+#define SDIO_STA_CCRCFAIL_Pos          (0U)                                    
+#define SDIO_STA_CCRCFAIL_Msk          (0x1U << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */
+#define SDIO_STA_DCRCFAIL_Pos          (1U)                                    
+#define SDIO_STA_DCRCFAIL_Msk          (0x1U << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */
+#define SDIO_STA_CTIMEOUT_Pos          (2U)                                    
+#define SDIO_STA_CTIMEOUT_Msk          (0x1U << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */
+#define SDIO_STA_DTIMEOUT_Pos          (3U)                                    
+#define SDIO_STA_DTIMEOUT_Msk          (0x1U << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */
+#define SDIO_STA_TXUNDERR_Pos          (4U)                                    
+#define SDIO_STA_TXUNDERR_Msk          (0x1U << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */
+#define SDIO_STA_RXOVERR_Pos           (5U)                                    
+#define SDIO_STA_RXOVERR_Msk           (0x1U << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */
+#define SDIO_STA_CMDREND_Pos           (6U)                                    
+#define SDIO_STA_CMDREND_Msk           (0x1U << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */
+#define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */
+#define SDIO_STA_CMDSENT_Pos           (7U)                                    
+#define SDIO_STA_CMDSENT_Msk           (0x1U << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */
+#define SDIO_STA_DATAEND_Pos           (8U)                                    
+#define SDIO_STA_DATAEND_Msk           (0x1U << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */
+#define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDIO_STA_STBITERR_Pos          (9U)                                    
+#define SDIO_STA_STBITERR_Msk          (0x1U << SDIO_STA_STBITERR_Pos)         /*!< 0x00000200 */
+#define SDIO_STA_STBITERR              SDIO_STA_STBITERR_Msk                   /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos           (10U)                                   
+#define SDIO_STA_DBCKEND_Msk           (0x1U << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */
+#define SDIO_STA_CMDACT_Pos            (11U)                                   
+#define SDIO_STA_CMDACT_Msk            (0x1U << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */
+#define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */
+#define SDIO_STA_TXACT_Pos             (12U)                                   
+#define SDIO_STA_TXACT_Msk             (0x1U << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */
+#define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */
+#define SDIO_STA_RXACT_Pos             (13U)                                   
+#define SDIO_STA_RXACT_Msk             (0x1U << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */
+#define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */
+#define SDIO_STA_TXFIFOHE_Pos          (14U)                                   
+#define SDIO_STA_TXFIFOHE_Msk          (0x1U << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos          (15U)                                   
+#define SDIO_STA_RXFIFOHF_Msk          (0x1U << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos           (16U)                                   
+#define SDIO_STA_TXFIFOF_Msk           (0x1U << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */
+#define SDIO_STA_RXFIFOF_Pos           (17U)                                   
+#define SDIO_STA_RXFIFOF_Msk           (0x1U << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */
+#define SDIO_STA_TXFIFOE_Pos           (18U)                                   
+#define SDIO_STA_TXFIFOE_Msk           (0x1U << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */
+#define SDIO_STA_RXFIFOE_Pos           (19U)                                   
+#define SDIO_STA_RXFIFOE_Msk           (0x1U << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */
+#define SDIO_STA_TXDAVL_Pos            (20U)                                   
+#define SDIO_STA_TXDAVL_Msk            (0x1U << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */
+#define SDIO_STA_RXDAVL_Pos            (21U)                                   
+#define SDIO_STA_RXDAVL_Msk            (0x1U << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */
+#define SDIO_STA_SDIOIT_Pos            (22U)                                   
+#define SDIO_STA_SDIOIT_Msk            (0x1U << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */
+#define SDIO_STA_CEATAEND_Pos          (23U)                                   
+#define SDIO_STA_CEATAEND_Msk          (0x1U << SDIO_STA_CEATAEND_Pos)         /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND              SDIO_STA_CEATAEND_Msk                   /*!<CE-ATA command completion signal received for CMD61 */
+
+/*******************  Bit definition for SDIO_ICR register  *******************/
+#define SDIO_ICR_CCRCFAILC_Pos         (0U)                                    
+#define SDIO_ICR_CCRCFAILC_Msk         (0x1U << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos         (1U)                                    
+#define SDIO_ICR_DCRCFAILC_Msk         (0x1U << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos         (2U)                                    
+#define SDIO_ICR_CTIMEOUTC_Msk         (0x1U << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos         (3U)                                    
+#define SDIO_ICR_DTIMEOUTC_Msk         (0x1U << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos         (4U)                                    
+#define SDIO_ICR_TXUNDERRC_Msk         (0x1U << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos          (5U)                                    
+#define SDIO_ICR_RXOVERRC_Msk          (0x1U << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */
+#define SDIO_ICR_CMDRENDC_Pos          (6U)                                    
+#define SDIO_ICR_CMDRENDC_Msk          (0x1U << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */
+#define SDIO_ICR_CMDSENTC_Pos          (7U)                                    
+#define SDIO_ICR_CMDSENTC_Msk          (0x1U << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */
+#define SDIO_ICR_DATAENDC_Pos          (8U)                                    
+#define SDIO_ICR_DATAENDC_Msk          (0x1U << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */
+#define SDIO_ICR_STBITERRC_Pos         (9U)                                    
+#define SDIO_ICR_STBITERRC_Msk         (0x1U << SDIO_ICR_STBITERRC_Pos)        /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC             SDIO_ICR_STBITERRC_Msk                  /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos          (10U)                                   
+#define SDIO_ICR_DBCKENDC_Msk          (0x1U << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */
+#define SDIO_ICR_SDIOITC_Pos           (22U)                                   
+#define SDIO_ICR_SDIOITC_Msk           (0x1U << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */
+#define SDIO_ICR_CEATAENDC_Pos         (23U)                                   
+#define SDIO_ICR_CEATAENDC_Msk         (0x1U << SDIO_ICR_CEATAENDC_Pos)        /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC             SDIO_ICR_CEATAENDC_Msk                  /*!<CEATAEND flag clear bit */
+
+/******************  Bit definition for SDIO_MASK register  *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos       (0U)                                    
+#define SDIO_MASK_CCRCFAILIE_Msk       (0x1U << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */
+#define SDIO_MASK_DCRCFAILIE_Pos       (1U)                                    
+#define SDIO_MASK_DCRCFAILIE_Msk       (0x1U << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */
+#define SDIO_MASK_CTIMEOUTIE_Pos       (2U)                                    
+#define SDIO_MASK_CTIMEOUTIE_Msk       (0x1U << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */
+#define SDIO_MASK_DTIMEOUTIE_Pos       (3U)                                    
+#define SDIO_MASK_DTIMEOUTIE_Msk       (0x1U << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */
+#define SDIO_MASK_TXUNDERRIE_Pos       (4U)                                    
+#define SDIO_MASK_TXUNDERRIE_Msk       (0x1U << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDIO_MASK_RXOVERRIE_Pos        (5U)                                    
+#define SDIO_MASK_RXOVERRIE_Msk        (0x1U << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDIO_MASK_CMDRENDIE_Pos        (6U)                                    
+#define SDIO_MASK_CMDRENDIE_Msk        (0x1U << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos        (7U)                                    
+#define SDIO_MASK_CMDSENTIE_Msk        (0x1U << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */
+#define SDIO_MASK_DATAENDIE_Pos        (8U)                                    
+#define SDIO_MASK_DATAENDIE_Msk        (0x1U << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */
+#define SDIO_MASK_STBITERRIE_Pos       (9U)                                    
+#define SDIO_MASK_STBITERRIE_Msk       (0x1U << SDIO_MASK_STBITERRIE_Pos)      /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE           SDIO_MASK_STBITERRIE_Msk                /*!<Start Bit Error Interrupt Enable           */
+#define SDIO_MASK_DBCKENDIE_Pos        (10U)                                   
+#define SDIO_MASK_DBCKENDIE_Msk        (0x1U << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */
+#define SDIO_MASK_CMDACTIE_Pos         (11U)                                   
+#define SDIO_MASK_CMDACTIE_Msk         (0x1U << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */
+#define SDIO_MASK_TXACTIE_Pos          (12U)                                   
+#define SDIO_MASK_TXACTIE_Msk          (0x1U << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */
+#define SDIO_MASK_RXACTIE_Pos          (13U)                                   
+#define SDIO_MASK_RXACTIE_Msk          (0x1U << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */
+#define SDIO_MASK_TXFIFOHEIE_Pos       (14U)                                   
+#define SDIO_MASK_TXFIFOHEIE_Msk       (0x1U << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDIO_MASK_RXFIFOHFIE_Pos       (15U)                                   
+#define SDIO_MASK_RXFIFOHFIE_Msk       (0x1U << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */
+#define SDIO_MASK_TXFIFOFIE_Pos        (16U)                                   
+#define SDIO_MASK_TXFIFOFIE_Msk        (0x1U << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */
+#define SDIO_MASK_RXFIFOFIE_Pos        (17U)                                   
+#define SDIO_MASK_RXFIFOFIE_Msk        (0x1U << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */
+#define SDIO_MASK_TXFIFOEIE_Pos        (18U)                                   
+#define SDIO_MASK_TXFIFOEIE_Msk        (0x1U << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */
+#define SDIO_MASK_RXFIFOEIE_Pos        (19U)                                   
+#define SDIO_MASK_RXFIFOEIE_Msk        (0x1U << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */
+#define SDIO_MASK_TXDAVLIE_Pos         (20U)                                   
+#define SDIO_MASK_TXDAVLIE_Msk         (0x1U << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos         (21U)                                   
+#define SDIO_MASK_RXDAVLIE_Msk         (0x1U << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos         (22U)                                   
+#define SDIO_MASK_SDIOITIE_Msk         (0x1U << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos       (23U)                                   
+#define SDIO_MASK_CEATAENDIE_Msk       (0x1U << SDIO_MASK_CEATAENDIE_Pos)      /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE           SDIO_MASK_CEATAENDIE_Msk                /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)                                    
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDIO_FIFO register  *******************/
+#define SDIO_FIFO_FIFODATA_Pos         (0U)                                    
+#define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface                         */
+/*                                                                            */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define  SPI_I2S_SUPPORT                                            /*!< I2S support             */
+#define  SPI_I2S_FULLDUPLEX_SUPPORT                                 /*!< I2S Full-Duplex support */
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_CPHA_Pos            (0U)                                       
+#define SPI_CR1_CPHA_Msk            (0x1U << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
+#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
+#define SPI_CR1_CPOL_Pos            (1U)                                       
+#define SPI_CR1_CPOL_Msk            (0x1U << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
+#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
+#define SPI_CR1_MSTR_Pos            (2U)                                       
+#define SPI_CR1_MSTR_Msk            (0x1U << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
+#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos              (3U)                                       
+#define SPI_CR1_BR_Msk              (0x7U << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
+#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0                (0x1U << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
+#define SPI_CR1_BR_1                (0x2U << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
+#define SPI_CR1_BR_2                (0x4U << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos             (6U)                                       
+#define SPI_CR1_SPE_Msk             (0x1U << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
+#define SPI_CR1_LSBFIRST_Pos        (7U)                                       
+#define SPI_CR1_LSBFIRST_Msk        (0x1U << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
+#define SPI_CR1_SSI_Pos             (8U)                                       
+#define SPI_CR1_SSI_Msk             (0x1U << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
+#define SPI_CR1_SSM_Pos             (9U)                                       
+#define SPI_CR1_SSM_Msk             (0x1U << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
+#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
+#define SPI_CR1_RXONLY_Pos          (10U)                                      
+#define SPI_CR1_RXONLY_Msk          (0x1U << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
+#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
+#define SPI_CR1_DFF_Pos             (11U)                                      
+#define SPI_CR1_DFF_Msk             (0x1U << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
+#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */
+#define SPI_CR1_CRCNEXT_Pos         (12U)                                      
+#define SPI_CR1_CRCNEXT_Msk         (0x1U << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
+#define SPI_CR1_CRCEN_Pos           (13U)                                      
+#define SPI_CR1_CRCEN_Msk           (0x1U << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
+#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
+#define SPI_CR1_BIDIOE_Pos          (14U)                                      
+#define SPI_CR1_BIDIOE_Msk          (0x1U << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos        (15U)                                      
+#define SPI_CR1_BIDIMODE_Msk        (0x1U << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_RXDMAEN_Pos         (0U)                                       
+#define SPI_CR2_RXDMAEN_Msk         (0x1U << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */
+#define SPI_CR2_TXDMAEN_Pos         (1U)                                       
+#define SPI_CR2_TXDMAEN_Msk         (0x1U << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */
+#define SPI_CR2_SSOE_Pos            (2U)                                       
+#define SPI_CR2_SSOE_Msk            (0x1U << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
+#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */
+#define SPI_CR2_FRF_Pos             (4U)                                       
+#define SPI_CR2_FRF_Msk             (0x1U << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
+#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */
+#define SPI_CR2_ERRIE_Pos           (5U)                                       
+#define SPI_CR2_ERRIE_Msk           (0x1U << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
+#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */
+#define SPI_CR2_RXNEIE_Pos          (6U)                                       
+#define SPI_CR2_RXNEIE_Msk          (0x1U << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos           (7U)                                       
+#define SPI_CR2_TXEIE_Msk           (0x1U << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
+#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXNE_Pos             (0U)                                       
+#define SPI_SR_RXNE_Msk             (0x1U << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
+#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos              (1U)                                       
+#define SPI_SR_TXE_Msk              (0x1U << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
+#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */
+#define SPI_SR_CHSIDE_Pos           (2U)                                       
+#define SPI_SR_CHSIDE_Msk           (0x1U << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
+#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */
+#define SPI_SR_UDR_Pos              (3U)                                       
+#define SPI_SR_UDR_Msk              (0x1U << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */
+#define SPI_SR_CRCERR_Pos           (4U)                                       
+#define SPI_SR_CRCERR_Msk           (0x1U << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
+#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */
+#define SPI_SR_MODF_Pos             (5U)                                       
+#define SPI_SR_MODF_Msk             (0x1U << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */
+#define SPI_SR_OVR_Pos              (6U)                                       
+#define SPI_SR_OVR_Msk              (0x1U << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */
+#define SPI_SR_BSY_Pos              (7U)                                       
+#define SPI_SR_BSY_Msk              (0x1U << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
+#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */
+#define SPI_SR_FRE_Pos              (8U)                                       
+#define SPI_SR_FRE_Msk              (0x1U << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
+#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define SPI_DR_DR_Pos               (0U)                                       
+#define SPI_DR_DR_Msk               (0xFFFFU << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
+#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define SPI_CRCPR_CRCPOLY_Pos       (0U)                                       
+#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define SPI_RXCRCR_RXCRC_Pos        (0U)                                       
+#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define SPI_TXCRCR_TXCRC_Pos        (0U)                                       
+#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define SPI_I2SCFGR_CHLEN_Pos       (0U)                                       
+#define SPI_I2SCFGR_CHLEN_Msk       (0x1U << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos      (1U)                                       
+#define SPI_I2SCFGR_DATLEN_Msk      (0x3U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define SPI_I2SCFGR_DATLEN_0        (0x1U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1        (0x2U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos       (3U)                                       
+#define SPI_I2SCFGR_CKPOL_Msk       (0x1U << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */
+
+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)                                       
+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0        (0x1U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1        (0x2U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)                                       
+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1U << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */
+
+#define SPI_I2SCFGR_I2SCFG_Pos      (8U)                                       
+#define SPI_I2SCFGR_I2SCFG_Msk      (0x3U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0        (0x1U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1        (0x2U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos        (10U)                                      
+#define SPI_I2SCFGR_I2SE_Msk        (0x1U << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */
+#define SPI_I2SCFGR_I2SMOD_Pos      (11U)                                      
+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1U << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define SPI_I2SPR_I2SDIV_Pos        (0U)                                       
+#define SPI_I2SPR_I2SDIV_Msk        (0xFFU << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */
+#define SPI_I2SPR_ODD_Pos           (8U)                                       
+#define SPI_I2SPR_ODD_Msk           (0x1U << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
+#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos         (9U)                                       
+#define SPI_I2SPR_MCKOE_Msk         (0x1U << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)                              
+#define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
+#define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0             (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1             (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_MEMRMP_MEM_MODE_2             (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
+#define SYSCFG_MEMRMP_UFB_MODE_Pos           (8U)                              
+#define SYSCFG_MEMRMP_UFB_MODE_Msk           (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_MEMRMP_UFB_MODE               SYSCFG_MEMRMP_UFB_MODE_Msk        /*!< User Flash Bank mode    */
+#define SYSCFG_MEMRMP_SWP_FMC_Pos            (10U)                             
+#define SYSCFG_MEMRMP_SWP_FMC_Msk            (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
+#define SYSCFG_MEMRMP_SWP_FMC                SYSCFG_MEMRMP_SWP_FMC_Msk         /*!< FMC memory mapping swap */
+#define SYSCFG_MEMRMP_SWP_FMC_0              (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
+/* Legacy Defines */
+#define SYSCFG_SWP_FMC                  SYSCFG_MEMRMP_SWP_FMC
+/******************  Bit definition for SYSCFG_PMC register  ******************/
+#define SYSCFG_PMC_ADCxDC2_Pos               (16U)                             
+#define SYSCFG_PMC_ADCxDC2_Msk               (0x7U << SYSCFG_PMC_ADCxDC2_Pos)  /*!< 0x00070000 */
+#define SYSCFG_PMC_ADCxDC2                   SYSCFG_PMC_ADCxDC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC1DC2_Pos               (16U)                             
+#define SYSCFG_PMC_ADC1DC2_Msk               (0x1U << SYSCFG_PMC_ADC1DC2_Pos)  /*!< 0x00010000 */
+#define SYSCFG_PMC_ADC1DC2                   SYSCFG_PMC_ADC1DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC2DC2_Pos               (17U)                             
+#define SYSCFG_PMC_ADC2DC2_Msk               (0x1U << SYSCFG_PMC_ADC2DC2_Pos)  /*!< 0x00020000 */
+#define SYSCFG_PMC_ADC2DC2                   SYSCFG_PMC_ADC2DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_ADC3DC2_Pos               (18U)                             
+#define SYSCFG_PMC_ADC3DC2_Msk               (0x1U << SYSCFG_PMC_ADC3DC2_Pos)  /*!< 0x00040000 */
+#define SYSCFG_PMC_ADC3DC2                   SYSCFG_PMC_ADC3DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */
+#define SYSCFG_PMC_MII_RMII_SEL_Pos          (23U)                             
+#define SYSCFG_PMC_MII_RMII_SEL_Msk          (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
+#define SYSCFG_PMC_MII_RMII_SEL              SYSCFG_PMC_MII_RMII_SEL_Msk       /*!<Ethernet PHY interface selection */
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL    
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos             (0U)                              
+#define SYSCFG_EXTICR1_EXTI0_Msk             (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos             (4U)                              
+#define SYSCFG_EXTICR1_EXTI1_Msk             (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos             (8U)                              
+#define SYSCFG_EXTICR1_EXTI2_Msk             (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos             (12U)                             
+#define SYSCFG_EXTICR1_EXTI3_Msk             (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */
+/**
+  * @brief   EXTI0 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI              0x0008U                           /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ              0x0009U                           /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK              0x000AU                           /*!<PK[0] pin */
+
+/**
+  * @brief   EXTI1 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI              0x0080U                           /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ              0x0090U                           /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK              0x00A0U                           /*!<PK[1] pin */
+
+/**
+  * @brief   EXTI2 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI              0x0800U                           /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ              0x0900U                           /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK              0x0A00U                           /*!<PK[2] pin */
+
+/**
+  * @brief   EXTI3 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI              0x8000U                           /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ              0x9000U                           /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK              0xA000U                           /*!<PK[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos             (0U)                              
+#define SYSCFG_EXTICR2_EXTI4_Msk             (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos             (4U)                              
+#define SYSCFG_EXTICR2_EXTI5_Msk             (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos             (8U)                              
+#define SYSCFG_EXTICR2_EXTI6_Msk             (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos             (12U)                             
+#define SYSCFG_EXTICR2_EXTI7_Msk             (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */
+
+/**
+  * @brief   EXTI4 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI              0x0008U                           /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ              0x0009U                           /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK              0x000AU                           /*!<PK[4] pin */
+
+/**
+  * @brief   EXTI5 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI              0x0080U                           /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ              0x0090U                           /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK              0x00A0U                           /*!<PK[5] pin */
+
+/**
+  * @brief   EXTI6 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI              0x0800U                           /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ              0x0900U                           /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK              0x0A00U                           /*!<PK[6] pin */
+
+/**
+  * @brief   EXTI7 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI              0x8000U                           /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ              0x9000U                           /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK              0xA000U                           /*!<PK[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos             (0U)                              
+#define SYSCFG_EXTICR3_EXTI8_Msk             (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos             (4U)                              
+#define SYSCFG_EXTICR3_EXTI9_Msk             (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos            (8U)                              
+#define SYSCFG_EXTICR3_EXTI10_Msk            (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos            (12U)                             
+#define SYSCFG_EXTICR3_EXTI11_Msk            (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */
+
+/**
+  * @brief   EXTI8 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI              0x0008U                           /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ              0x0009U                           /*!<PJ[8] pin */
+
+/**
+  * @brief   EXTI9 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI              0x0080U                           /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ              0x0090U                           /*!<PJ[9] pin */
+
+/**
+  * @brief   EXTI10 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI             0x0800U                           /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ             0x0900U                           /*!<PJ[10] pin */
+
+/**
+  * @brief   EXTI11 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI             0x8000U                           /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ             0x9000U                           /*!<PJ[11] pin */
+
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos            (0U)                              
+#define SYSCFG_EXTICR4_EXTI12_Msk            (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos            (4U)                              
+#define SYSCFG_EXTICR4_EXTI13_Msk            (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos            (8U)                              
+#define SYSCFG_EXTICR4_EXTI14_Msk            (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos            (12U)                             
+#define SYSCFG_EXTICR4_EXTI15_Msk            (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */
+
+/**
+  * @brief   EXTI12 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI             0x0008U                           /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ             0x0009U                           /*!<PJ[12] pin */
+
+/**
+  * @brief   EXTI13 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI             0x0008U                           /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ             0x0009U                           /*!<PJ[13] pin */
+
+/**
+  * @brief   EXTI14 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI             0x0800U                           /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ             0x0900U                           /*!<PJ[14] pin */
+
+/**
+  * @brief   EXTI15 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI             0x8000U                           /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ             0x9000U                           /*!<PJ[15] pin */
+
+/******************  Bit definition for SYSCFG_CMPCR register  ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos              (0U)                              
+#define SYSCFG_CMPCR_CMP_PD_Msk              (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos               (8U)                              
+#define SYSCFG_CMPCR_READY_Msk               (0x1U << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)                                         
+#define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */
+#define TIM_CR1_UDIS_Pos          (1U)                                         
+#define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */
+#define TIM_CR1_URS_Pos           (2U)                                         
+#define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)                                         
+#define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */
+#define TIM_CR1_DIR_Pos           (4U)                                         
+#define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */
+
+#define TIM_CR1_CMS_Pos           (5U)                                         
+#define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */
+#define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)                                         
+#define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */
+
+#define TIM_CR1_CKD_Pos           (8U)                                         
+#define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */
+#define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)                                         
+#define TIM_CR2_CCPC_Msk          (0x1U << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */
+#define TIM_CR2_CCUS_Pos          (2U)                                         
+#define TIM_CR2_CCUS_Msk          (0x1U << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)                                         
+#define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */
+
+#define TIM_CR2_MMS_Pos           (4U)                                         
+#define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */
+#define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */
+#define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos          (7U)                                         
+#define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)                                         
+#define TIM_CR2_OIS1_Msk          (0x1U << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */
+#define TIM_CR2_OIS1N_Pos         (9U)                                         
+#define TIM_CR2_OIS1N_Msk         (0x1U << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)                                        
+#define TIM_CR2_OIS2_Msk          (0x1U << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */
+#define TIM_CR2_OIS2N_Pos         (11U)                                        
+#define TIM_CR2_OIS2N_Msk         (0x1U << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)                                        
+#define TIM_CR2_OIS3_Msk          (0x1U << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */
+#define TIM_CR2_OIS3N_Pos         (13U)                                        
+#define TIM_CR2_OIS3N_Msk         (0x1U << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)                                        
+#define TIM_CR2_OIS4_Msk          (0x1U << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)                                         
+#define TIM_SMCR_SMS_Msk          (0x7U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */
+#define TIM_SMCR_SMS_0            (0x1U << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */
+#define TIM_SMCR_SMS_1            (0x2U << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */
+#define TIM_SMCR_SMS_2            (0x4U << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos           (4U)                                         
+#define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */
+#define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */
+#define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */
+#define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos          (7U)                                         
+#define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */
+
+#define TIM_SMCR_ETF_Pos          (8U)                                         
+#define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */
+#define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */
+#define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */
+#define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)                                        
+#define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)                                        
+#define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */
+#define TIM_SMCR_ETP_Pos          (15U)                                        
+#define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)                                         
+#define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)                                         
+#define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */
+#define TIM_DIER_CC2IE_Pos        (2U)                                         
+#define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */
+#define TIM_DIER_CC3IE_Pos        (3U)                                         
+#define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */
+#define TIM_DIER_CC4IE_Pos        (4U)                                         
+#define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */
+#define TIM_DIER_COMIE_Pos        (5U)                                         
+#define TIM_DIER_COMIE_Msk        (0x1U << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */
+#define TIM_DIER_TIE_Pos          (6U)                                         
+#define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */
+#define TIM_DIER_BIE_Pos          (7U)                                         
+#define TIM_DIER_BIE_Msk          (0x1U << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */
+#define TIM_DIER_UDE_Pos          (8U)                                         
+#define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */
+#define TIM_DIER_CC1DE_Pos        (9U)                                         
+#define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)                                        
+#define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)                                        
+#define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)                                        
+#define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)                                        
+#define TIM_DIER_COMDE_Msk        (0x1U << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */
+#define TIM_DIER_TDE_Pos          (14U)                                        
+#define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)                                         
+#define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */
+#define TIM_SR_CC1IF_Pos          (1U)                                         
+#define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */
+#define TIM_SR_CC2IF_Pos          (2U)                                         
+#define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */
+#define TIM_SR_CC3IF_Pos          (3U)                                         
+#define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */
+#define TIM_SR_CC4IF_Pos          (4U)                                         
+#define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */
+#define TIM_SR_COMIF_Pos          (5U)                                         
+#define TIM_SR_COMIF_Msk          (0x1U << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */
+#define TIM_SR_TIF_Pos            (6U)                                         
+#define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */
+#define TIM_SR_BIF_Pos            (7U)                                         
+#define TIM_SR_BIF_Msk            (0x1U << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */
+#define TIM_SR_CC1OF_Pos          (9U)                                         
+#define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)                                        
+#define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)                                        
+#define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)                                        
+#define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)                                         
+#define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */
+#define TIM_EGR_CC1G_Pos          (1U)                                         
+#define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */
+#define TIM_EGR_CC2G_Pos          (2U)                                         
+#define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */
+#define TIM_EGR_CC3G_Pos          (3U)                                         
+#define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */
+#define TIM_EGR_CC4G_Pos          (4U)                                         
+#define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */
+#define TIM_EGR_COMG_Pos          (5U)                                         
+#define TIM_EGR_COMG_Msk          (0x1U << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)                                         
+#define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */
+#define TIM_EGR_BG_Pos            (7U)                                         
+#define TIM_EGR_BG_Msk            (0x1U << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)                                         
+#define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)                                         
+#define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */
+#define TIM_CCMR1_OC1PE_Pos       (3U)                                         
+#define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)                                         
+#define TIM_CCMR1_OC1M_Msk        (0x7U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define TIM_CCMR1_OC1M_0          (0x1U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1          (0x2U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2          (0x4U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)                                         
+#define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)                                         
+#define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)                                        
+#define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */
+#define TIM_CCMR1_OC2PE_Pos       (11U)                                        
+#define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)                                        
+#define TIM_CCMR1_OC2M_Msk        (0x7U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define TIM_CCMR1_OC2M_0          (0x1U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1          (0x2U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2          (0x4U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)                                        
+#define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos      (2U)                                         
+#define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)                                         
+#define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)                                        
+#define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)                                        
+#define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)                                         
+#define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)                                         
+#define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */
+#define TIM_CCMR2_OC3PE_Pos       (3U)                                         
+#define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)                                         
+#define TIM_CCMR2_OC3M_Msk        (0x7U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x1U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1          (0x2U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2          (0x4U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)                                         
+#define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)                                         
+#define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)                                        
+#define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */
+#define TIM_CCMR2_OC4PE_Pos       (11U)                                        
+#define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)                                        
+#define TIM_CCMR2_OC4M_Msk        (0x7U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x1U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1          (0x2U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2          (0x4U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)                                        
+#define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos      (2U)                                         
+#define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)                                         
+#define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)                                        
+#define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)                                        
+#define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)                                         
+#define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */
+#define TIM_CCER_CC1P_Pos         (1U)                                         
+#define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */
+#define TIM_CCER_CC1NE_Pos        (2U)                                         
+#define TIM_CCER_CC1NE_Msk        (0x1U << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */
+#define TIM_CCER_CC1NP_Pos        (3U)                                         
+#define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)                                         
+#define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */
+#define TIM_CCER_CC2P_Pos         (5U)                                         
+#define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */
+#define TIM_CCER_CC2NE_Pos        (6U)                                         
+#define TIM_CCER_CC2NE_Msk        (0x1U << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */
+#define TIM_CCER_CC2NP_Pos        (7U)                                         
+#define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)                                         
+#define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */
+#define TIM_CCER_CC3P_Pos         (9U)                                         
+#define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */
+#define TIM_CCER_CC3NE_Pos        (10U)                                        
+#define TIM_CCER_CC3NE_Msk        (0x1U << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */
+#define TIM_CCER_CC3NP_Pos        (11U)                                        
+#define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)                                        
+#define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */
+#define TIM_CCER_CC4P_Pos         (13U)                                        
+#define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */
+#define TIM_CCER_CC4NP_Pos        (15U)                                        
+#define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)                                         
+#define TIM_CNT_CNT_Msk           (0xFFFFU << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value            */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)                                         
+#define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)                                         
+#define TIM_ARR_ARR_Msk           (0xFFFFU << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)                                         
+#define TIM_RCR_REP_Msk           (0xFFU << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)                                         
+#define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)                                         
+#define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)                                         
+#define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)                                         
+#define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)                                         
+#define TIM_BDTR_DTG_Msk          (0xFFU << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */
+#define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */
+#define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */
+#define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */
+#define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */
+#define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */
+#define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */
+#define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos         (8U)                                         
+#define TIM_BDTR_LOCK_Msk         (0x3U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos         (10U)                                        
+#define TIM_BDTR_OSSI_Msk         (0x1U << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)                                        
+#define TIM_BDTR_OSSR_Msk         (0x1U << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */
+#define TIM_BDTR_BKE_Pos          (12U)                                        
+#define TIM_BDTR_BKE_Msk          (0x1U << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */
+#define TIM_BDTR_BKP_Pos          (13U)                                        
+#define TIM_BDTR_BKP_Msk          (0x1U << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */
+#define TIM_BDTR_AOE_Pos          (14U)                                        
+#define TIM_BDTR_AOE_Msk          (0x1U << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */
+#define TIM_BDTR_MOE_Pos          (15U)                                        
+#define TIM_BDTR_MOE_Msk          (0x1U << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)                                         
+#define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */
+#define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */
+#define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */
+#define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */
+#define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos           (8U)                                         
+#define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */
+#define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */
+#define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */
+#define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */
+#define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)                                         
+#define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM_OR_TI4_RMP_Pos        (6U)                                         
+#define TIM_OR_TI4_RMP_Msk        (0x3U << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0          (0x1U << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1          (0x2U << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */
+#define TIM_OR_ITR1_RMP_Pos       (10U)                                        
+#define TIM_OR_ITR1_RMP_Msk       (0x3U << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */
+#define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0         (0x1U << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */
+#define TIM_OR_ITR1_RMP_1         (0x2U << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for USART_SR register  *******************/
+#define USART_SR_PE_Pos               (0U)                                     
+#define USART_SR_PE_Msk               (0x1U << USART_SR_PE_Pos)                /*!< 0x00000001 */
+#define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */
+#define USART_SR_FE_Pos               (1U)                                     
+#define USART_SR_FE_Msk               (0x1U << USART_SR_FE_Pos)                /*!< 0x00000002 */
+#define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */
+#define USART_SR_NE_Pos               (2U)                                     
+#define USART_SR_NE_Msk               (0x1U << USART_SR_NE_Pos)                /*!< 0x00000004 */
+#define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */
+#define USART_SR_ORE_Pos              (3U)                                     
+#define USART_SR_ORE_Msk              (0x1U << USART_SR_ORE_Pos)               /*!< 0x00000008 */
+#define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */
+#define USART_SR_IDLE_Pos             (4U)                                     
+#define USART_SR_IDLE_Msk             (0x1U << USART_SR_IDLE_Pos)              /*!< 0x00000010 */
+#define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */
+#define USART_SR_RXNE_Pos             (5U)                                     
+#define USART_SR_RXNE_Msk             (0x1U << USART_SR_RXNE_Pos)              /*!< 0x00000020 */
+#define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos               (6U)                                     
+#define USART_SR_TC_Msk               (0x1U << USART_SR_TC_Pos)                /*!< 0x00000040 */
+#define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */
+#define USART_SR_TXE_Pos              (7U)                                     
+#define USART_SR_TXE_Msk              (0x1U << USART_SR_TXE_Pos)               /*!< 0x00000080 */
+#define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos              (8U)                                     
+#define USART_SR_LBD_Msk              (0x1U << USART_SR_LBD_Pos)               /*!< 0x00000100 */
+#define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */
+#define USART_SR_CTS_Pos              (9U)                                     
+#define USART_SR_CTS_Msk              (0x1U << USART_SR_CTS_Pos)               /*!< 0x00000200 */
+#define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */
+
+/*******************  Bit definition for USART_DR register  *******************/
+#define USART_DR_DR_Pos               (0U)                                     
+#define USART_DR_DR_Msk               (0x1FFU << USART_DR_DR_Pos)              /*!< 0x000001FF */
+#define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_Fraction_Pos    (0U)                                     
+#define USART_BRR_DIV_Fraction_Msk    (0xFU << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos    (4U)                                     
+#define USART_BRR_DIV_Mantissa_Msk    (0xFFFU << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_SBK_Pos             (0U)                                     
+#define USART_CR1_SBK_Msk             (0x1U << USART_CR1_SBK_Pos)              /*!< 0x00000001 */
+#define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */
+#define USART_CR1_RWU_Pos             (1U)                                     
+#define USART_CR1_RWU_Msk             (0x1U << USART_CR1_RWU_Pos)              /*!< 0x00000002 */
+#define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */
+#define USART_CR1_RE_Pos              (2U)                                     
+#define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */
+#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */
+#define USART_CR1_TE_Pos              (3U)                                     
+#define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */
+#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */
+#define USART_CR1_IDLEIE_Pos          (4U)                                     
+#define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
+#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */
+#define USART_CR1_RXNEIE_Pos          (5U)                                     
+#define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
+#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */
+#define USART_CR1_TCIE_Pos            (6U)                                     
+#define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
+#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos           (7U)                                     
+#define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
+#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<PE Interrupt Enable                    */
+#define USART_CR1_PEIE_Pos            (8U)                                     
+#define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
+#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */
+#define USART_CR1_PS_Pos              (9U)                                     
+#define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */
+#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */
+#define USART_CR1_PCE_Pos             (10U)                                    
+#define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
+#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */
+#define USART_CR1_WAKE_Pos            (11U)                                    
+#define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
+#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */
+#define USART_CR1_M_Pos               (12U)                                    
+#define USART_CR1_M_Msk               (0x1U << USART_CR1_M_Pos)                /*!< 0x00001000 */
+#define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */
+#define USART_CR1_UE_Pos              (13U)                                    
+#define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00002000 */
+#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */
+#define USART_CR1_OVER8_Pos           (15U)                                    
+#define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
+#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_ADD_Pos             (0U)                                     
+#define USART_CR2_ADD_Msk             (0xFU << USART_CR2_ADD_Pos)              /*!< 0x0000000F */
+#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */
+#define USART_CR2_LBDL_Pos            (5U)                                     
+#define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
+#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */
+#define USART_CR2_LBDIE_Pos           (6U)                                     
+#define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
+#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos            (8U)                                     
+#define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
+#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */
+#define USART_CR2_CPHA_Pos            (9U)                                     
+#define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
+#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */
+#define USART_CR2_CPOL_Pos            (10U)                                    
+#define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
+#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */
+#define USART_CR2_CLKEN_Pos           (11U)                                    
+#define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
+#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */
+
+#define USART_CR2_STOP_Pos            (12U)                                    
+#define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
+#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x1000 */
+#define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos           (14U)                                    
+#define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
+#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos             (0U)                                     
+#define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
+#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */
+#define USART_CR3_IREN_Pos            (1U)                                     
+#define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
+#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */
+#define USART_CR3_IRLP_Pos            (2U)                                     
+#define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
+#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */
+#define USART_CR3_HDSEL_Pos           (3U)                                     
+#define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
+#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */
+#define USART_CR3_NACK_Pos            (4U)                                     
+#define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
+#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */
+#define USART_CR3_SCEN_Pos            (5U)                                     
+#define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
+#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */
+#define USART_CR3_DMAR_Pos            (6U)                                     
+#define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
+#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */
+#define USART_CR3_DMAT_Pos            (7U)                                     
+#define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
+#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */
+#define USART_CR3_RTSE_Pos            (8U)                                     
+#define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
+#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */
+#define USART_CR3_CTSE_Pos            (9U)                                     
+#define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
+#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */
+#define USART_CR3_CTSIE_Pos           (10U)                                    
+#define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
+#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */
+#define USART_CR3_ONEBIT_Pos          (11U)                                    
+#define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
+#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos            (0U)                                     
+#define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
+#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0              (0x01U << USART_GTPR_PSC_Pos)            /*!< 0x0001 */
+#define USART_GTPR_PSC_1              (0x02U << USART_GTPR_PSC_Pos)            /*!< 0x0002 */
+#define USART_GTPR_PSC_2              (0x04U << USART_GTPR_PSC_Pos)            /*!< 0x0004 */
+#define USART_GTPR_PSC_3              (0x08U << USART_GTPR_PSC_Pos)            /*!< 0x0008 */
+#define USART_GTPR_PSC_4              (0x10U << USART_GTPR_PSC_Pos)            /*!< 0x0010 */
+#define USART_GTPR_PSC_5              (0x20U << USART_GTPR_PSC_Pos)            /*!< 0x0020 */
+#define USART_GTPR_PSC_6              (0x40U << USART_GTPR_PSC_Pos)            /*!< 0x0040 */
+#define USART_GTPR_PSC_7              (0x80U << USART_GTPR_PSC_Pos)            /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos             (8U)                                     
+#define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
+#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos           (0U)                                           
+#define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x01 */
+#define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x02 */
+#define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x04 */
+#define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x08 */
+#define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x10 */
+#define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x20 */
+#define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x40 */
+/* Legacy defines */
+#define  WWDG_CR_T0                          WWDG_CR_T_0
+#define  WWDG_CR_T1                          WWDG_CR_T_1
+#define  WWDG_CR_T2                          WWDG_CR_T_2
+#define  WWDG_CR_T3                          WWDG_CR_T_3
+#define  WWDG_CR_T4                          WWDG_CR_T_4
+#define  WWDG_CR_T5                          WWDG_CR_T_5
+#define  WWDG_CR_T6                          WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos        (7U)                                           
+#define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos          (0U)                                           
+#define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x0001 */
+#define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x0002 */
+#define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x0004 */
+#define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x0008 */
+#define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x0010 */
+#define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x0020 */
+#define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x0040 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos      (7U)                                           
+#define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos        (9U)                                           
+#define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos        (0U)                                           
+#define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                DBG                                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)                      
+#define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk  
+#define DBGMCU_IDCODE_REV_ID_Pos                     (16U)                     
+#define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk  
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)                      
+#define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk   
+#define DBGMCU_CR_DBG_STOP_Pos                       (1U)                      
+#define DBGMCU_CR_DBG_STOP_Msk                       (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk    
+#define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)                      
+#define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk 
+#define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)                      
+#define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk  
+
+#define DBGMCU_CR_TRACE_MODE_Pos                     (6U)                      
+#define DBGMCU_CR_TRACE_MODE_Msk                     (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk  
+#define DBGMCU_CR_TRACE_MODE_0                       (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1                       (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)                     
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)                     
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)                     
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)                     
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk 
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)                     
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk 
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)                     
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk 
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)                     
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)                     
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk 
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)                      
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk 
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)                      
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk 
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)                     
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk 
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)                     
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk 
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)                     
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk 
+
+/******************************************************************************/
+/*                                                                            */
+/*                Ethernet MAC Registers bits definitions                     */
+/*                                                                            */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD_Pos                              (23U)                    
+#define ETH_MACCR_WD_Msk                              (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
+#define ETH_MACCR_JD_Pos                              (22U)                    
+#define ETH_MACCR_JD_Msk                              (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
+#define ETH_MACCR_IFG_Pos                             (17U)                    
+#define ETH_MACCR_IFG_Msk                             (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
+#define ETH_MACCR_IFG                                 ETH_MACCR_IFG_Msk        /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit                           0x00000000U              /* Minimum IFG between frames during transmission is 96Bit */
+#define ETH_MACCR_IFG_88Bit                           0x00020000U              /* Minimum IFG between frames during transmission is 88Bit */
+#define ETH_MACCR_IFG_80Bit                           0x00040000U              /* Minimum IFG between frames during transmission is 80Bit */
+#define ETH_MACCR_IFG_72Bit                           0x00060000U              /* Minimum IFG between frames during transmission is 72Bit */
+#define ETH_MACCR_IFG_64Bit                           0x00080000U              /* Minimum IFG between frames during transmission is 64Bit */
+#define ETH_MACCR_IFG_56Bit                           0x000A0000U              /* Minimum IFG between frames during transmission is 56Bit */
+#define ETH_MACCR_IFG_48Bit                           0x000C0000U              /* Minimum IFG between frames during transmission is 48Bit */
+#define ETH_MACCR_IFG_40Bit                           0x000E0000U              /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD_Pos                             (16U)                    
+#define ETH_MACCR_CSD_Msk                             (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_CSD                                 ETH_MACCR_CSD_Msk        /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES_Pos                             (14U)                    
+#define ETH_MACCR_FES_Msk                             (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */
+#define ETH_MACCR_ROD_Pos                             (13U)                    
+#define ETH_MACCR_ROD_Msk                             (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_ROD                                 ETH_MACCR_ROD_Msk        /* Receive own disable */
+#define ETH_MACCR_LM_Pos                              (12U)                    
+#define ETH_MACCR_LM_Msk                              (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
+#define ETH_MACCR_DM_Pos                              (11U)                    
+#define ETH_MACCR_DM_Msk                              (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
+#define ETH_MACCR_IPCO_Pos                            (10U)                    
+#define ETH_MACCR_IPCO_Msk                            (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_IPCO                                ETH_MACCR_IPCO_Msk       /* IP Checksum offload */
+#define ETH_MACCR_RD_Pos                              (9U)                     
+#define ETH_MACCR_RD_Msk                              (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_RD                                  ETH_MACCR_RD_Msk         /* Retry disable */
+#define ETH_MACCR_APCS_Pos                            (7U)                     
+#define ETH_MACCR_APCS_Msk                            (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
+#define ETH_MACCR_APCS                                ETH_MACCR_APCS_Msk       /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL_Pos                              (5U)                     
+#define ETH_MACCR_BL_Msk                              (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
+#define ETH_MACCR_BL_10                               0x00000000U              /* k = min (n, 10) */
+#define ETH_MACCR_BL_8                                0x00000020U              /* k = min (n, 8) */
+#define ETH_MACCR_BL_4                                0x00000040U              /* k = min (n, 4) */
+#define ETH_MACCR_BL_1                                0x00000060U              /* k = min (n, 1) */ 
+#define ETH_MACCR_DC_Pos                              (4U)                     
+#define ETH_MACCR_DC_Msk                              (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
+#define ETH_MACCR_TE_Pos                              (3U)                     
+#define ETH_MACCR_TE_Msk                              (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
+#define ETH_MACCR_RE_Pos                              (2U)                     
+#define ETH_MACCR_RE_Msk                              (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA_Pos                             (31U)                    
+#define ETH_MACFFR_RA_Msk                             (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACFFR_RA                                 ETH_MACFFR_RA_Msk        /* Receive all */
+#define ETH_MACFFR_HPF_Pos                            (10U)                    
+#define ETH_MACFFR_HPF_Msk                            (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACFFR_HPF                                ETH_MACFFR_HPF_Msk       /* Hash or perfect filter */
+#define ETH_MACFFR_SAF_Pos                            (9U)                     
+#define ETH_MACFFR_SAF_Msk                            (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACFFR_SAF                                ETH_MACFFR_SAF_Msk       /* Source address filter enable */
+#define ETH_MACFFR_SAIF_Pos                           (8U)                     
+#define ETH_MACFFR_SAIF_Msk                           (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACFFR_SAIF                               ETH_MACFFR_SAIF_Msk      /* SA inverse filtering */ 
+#define ETH_MACFFR_PCF_Pos                            (6U)                     
+#define ETH_MACFFR_PCF_Msk                            (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACFFR_PCF                                ETH_MACFFR_PCF_Msk       /* Pass control frames: 3 cases */
+#define ETH_MACFFR_PCF_BlockAll_Pos                   (6U)                     
+#define ETH_MACFFR_PCF_BlockAll_Msk                   (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
+#define ETH_MACFFR_PCF_BlockAll                       ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
+#define ETH_MACFFR_PCF_ForwardAll_Pos                 (7U)                     
+#define ETH_MACFFR_PCF_ForwardAll_Msk                 (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
+#define ETH_MACFFR_PCF_ForwardAll                     ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos    (6U)                     
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk    (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter        ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */ 
+#define ETH_MACFFR_BFD_Pos                            (5U)                     
+#define ETH_MACFFR_BFD_Msk                            (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
+#define ETH_MACFFR_BFD                                ETH_MACFFR_BFD_Msk       /* Broadcast frame disable */ 
+#define ETH_MACFFR_PAM_Pos                            (4U)                     
+#define ETH_MACFFR_PAM_Msk                            (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
+#define ETH_MACFFR_PAM                                ETH_MACFFR_PAM_Msk       /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF_Pos                           (3U)                     
+#define ETH_MACFFR_DAIF_Msk                           (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACFFR_DAIF                               ETH_MACFFR_DAIF_Msk      /* DA Inverse filtering */
+#define ETH_MACFFR_HM_Pos                             (2U)                     
+#define ETH_MACFFR_HM_Msk                             (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
+#define ETH_MACFFR_HM                                 ETH_MACFFR_HM_Msk        /* Hash multicast */ 
+#define ETH_MACFFR_HU_Pos                             (1U)                     
+#define ETH_MACFFR_HU_Msk                             (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
+#define ETH_MACFFR_HU                                 ETH_MACFFR_HU_Msk        /* Hash unicast */
+#define ETH_MACFFR_PM_Pos                             (0U)                     
+#define ETH_MACFFR_PM_Msk                             (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
+#define ETH_MACFFR_PM                                 ETH_MACFFR_PM_Msk        /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH_Pos                           (0U)                     
+#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL_Pos                           (0U)                     
+#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA_Pos                           (11U)                    
+#define ETH_MACMIIAR_PA_Msk                           (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
+#define ETH_MACMIIAR_PA                               ETH_MACMIIAR_PA_Msk      /* Physical layer address */
+#define ETH_MACMIIAR_MR_Pos                           (6U)                     
+#define ETH_MACMIIAR_MR_Msk                           (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
+#define ETH_MACMIIAR_MR                               ETH_MACMIIAR_MR_Msk      /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR_Pos                           (2U)                     
+#define ETH_MACMIIAR_CR_Msk                           (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
+#define ETH_MACMIIAR_CR                               ETH_MACMIIAR_CR_Msk      /* CR clock range: 6 cases */
+#define ETH_MACMIIAR_CR_Div42                         0x00000000U              /* HCLK:60-100 MHz; MDC clock= HCLK/42   */
+#define ETH_MACMIIAR_CR_Div62_Pos                     (2U)                     
+#define ETH_MACMIIAR_CR_Div62_Msk                     (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
+#define ETH_MACMIIAR_CR_Div62                         ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62  */
+#define ETH_MACMIIAR_CR_Div16_Pos                     (3U)                     
+#define ETH_MACMIIAR_CR_Div16_Msk                     (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
+#define ETH_MACMIIAR_CR_Div16                         ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16    */
+#define ETH_MACMIIAR_CR_Div26_Pos                     (2U)                     
+#define ETH_MACMIIAR_CR_Div26_Msk                     (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
+#define ETH_MACMIIAR_CR_Div26                         ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26    */
+#define ETH_MACMIIAR_CR_Div102_Pos                    (4U)                     
+#define ETH_MACMIIAR_CR_Div102_Msk                    (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
+#define ETH_MACMIIAR_CR_Div102                        ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW_Pos                           (1U)                     
+#define ETH_MACMIIAR_MW_Msk                           (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
+#define ETH_MACMIIAR_MW                               ETH_MACMIIAR_MW_Msk      /* MII write */
+#define ETH_MACMIIAR_MB_Pos                           (0U)                     
+#define ETH_MACMIIAR_MB_Msk                           (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
+#define ETH_MACMIIAR_MB                               ETH_MACMIIAR_MB_Msk      /* MII busy  */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD_Pos                           (0U)                     
+#define ETH_MACMIIDR_MD_Msk                           (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMIIDR_MD                               ETH_MACMIIDR_MD_Msk      /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT_Pos                             (16U)                    
+#define ETH_MACFCR_PT_Msk                             (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACFCR_PT                                 ETH_MACFCR_PT_Msk        /* Pause time */
+#define ETH_MACFCR_ZQPD_Pos                           (7U)                     
+#define ETH_MACFCR_ZQPD_Msk                           (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
+#define ETH_MACFCR_ZQPD                               ETH_MACFCR_ZQPD_Msk      /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT_Pos                            (4U)                     
+#define ETH_MACFCR_PLT_Msk                            (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
+#define ETH_MACFCR_PLT                                ETH_MACFCR_PLT_Msk       /* Pause low threshold: 4 cases */
+#define ETH_MACFCR_PLT_Minus4                         0x00000000U              /* Pause time minus 4 slot times   */
+#define ETH_MACFCR_PLT_Minus28_Pos                    (4U)                     
+#define ETH_MACFCR_PLT_Minus28_Msk                    (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
+#define ETH_MACFCR_PLT_Minus28                        ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times  */
+#define ETH_MACFCR_PLT_Minus144_Pos                   (5U)                     
+#define ETH_MACFCR_PLT_Minus144_Msk                   (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
+#define ETH_MACFCR_PLT_Minus144                       ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACFCR_PLT_Minus256_Pos                   (4U)                     
+#define ETH_MACFCR_PLT_Minus256_Msk                   (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
+#define ETH_MACFCR_PLT_Minus256                       ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD_Pos                           (3U)                     
+#define ETH_MACFCR_UPFD_Msk                           (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
+#define ETH_MACFCR_UPFD                               ETH_MACFCR_UPFD_Msk      /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE_Pos                           (2U)                     
+#define ETH_MACFCR_RFCE_Msk                           (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
+#define ETH_MACFCR_RFCE                               ETH_MACFCR_RFCE_Msk      /* Receive flow control enable */
+#define ETH_MACFCR_TFCE_Pos                           (1U)                     
+#define ETH_MACFCR_TFCE_Msk                           (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
+#define ETH_MACFCR_TFCE                               ETH_MACFCR_TFCE_Msk      /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA_Pos                         (0U)                     
+#define ETH_MACFCR_FCBBPA_Msk                         (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
+#define ETH_MACFCR_FCBBPA                             ETH_MACFCR_FCBBPA_Msk    /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC_Pos                      (16U)                    
+#define ETH_MACVLANTR_VLANTC_Msk                      (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
+#define ETH_MACVLANTR_VLANTC                          ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI_Pos                      (0U)                     
+#define ETH_MACVLANTR_VLANTI_Msk                      (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVLANTR_VLANTI                          ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
+#define ETH_MACRWUFFR_D_Pos                           (0U)                     
+#define ETH_MACRWUFFR_D_Msk                           (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWUFFR_D                               ETH_MACRWUFFR_D_Msk      /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
+                              RSVD - Filter1 Command - RSVD - Filter0 Command
+   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
+#define ETH_MACPMTCSR_WFFRPR_Pos                      (31U)                    
+#define ETH_MACPMTCSR_WFFRPR_Msk                      (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
+#define ETH_MACPMTCSR_WFFRPR                          ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU_Pos                          (9U)                     
+#define ETH_MACPMTCSR_GU_Msk                          (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
+#define ETH_MACPMTCSR_GU                              ETH_MACPMTCSR_GU_Msk     /* Global Unicast                              */
+#define ETH_MACPMTCSR_WFR_Pos                         (6U)                     
+#define ETH_MACPMTCSR_WFR_Msk                         (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
+#define ETH_MACPMTCSR_WFR                             ETH_MACPMTCSR_WFR_Msk    /* Wake-Up Frame Received                      */
+#define ETH_MACPMTCSR_MPR_Pos                         (5U)                     
+#define ETH_MACPMTCSR_MPR_Msk                         (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
+#define ETH_MACPMTCSR_MPR                             ETH_MACPMTCSR_MPR_Msk    /* Magic Packet Received                       */
+#define ETH_MACPMTCSR_WFE_Pos                         (2U)                     
+#define ETH_MACPMTCSR_WFE_Msk                         (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
+#define ETH_MACPMTCSR_WFE                             ETH_MACPMTCSR_WFE_Msk    /* Wake-Up Frame Enable                        */
+#define ETH_MACPMTCSR_MPE_Pos                         (1U)                     
+#define ETH_MACPMTCSR_MPE_Msk                         (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
+#define ETH_MACPMTCSR_MPE                             ETH_MACPMTCSR_MPE_Msk    /* Magic Packet Enable                         */
+#define ETH_MACPMTCSR_PD_Pos                          (0U)                     
+#define ETH_MACPMTCSR_PD_Msk                          (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
+#define ETH_MACPMTCSR_PD                              ETH_MACPMTCSR_PD_Msk     /* Power Down                                  */
+
+/* Bit definition for Ethernet MAC debug Register */
+#define ETH_MACDBGR_TFF_Pos                           (25U)                    
+#define ETH_MACDBGR_TFF_Msk                           (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
+#define ETH_MACDBGR_TFF                               ETH_MACDBGR_TFF_Msk      /* Tx FIFO full                                                            */
+#define ETH_MACDBGR_TFNE_Pos                          (24U)                    
+#define ETH_MACDBGR_TFNE_Msk                          (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
+#define ETH_MACDBGR_TFNE                              ETH_MACDBGR_TFNE_Msk     /* Tx FIFO not empty                                                       */
+#define ETH_MACDBGR_TPWA_Pos                          (22U)                    
+#define ETH_MACDBGR_TPWA_Msk                          (0x1U << ETH_MACDBGR_TPWA_Pos) /*!< 0x00400000 */
+#define ETH_MACDBGR_TPWA                              ETH_MACDBGR_TPWA_Msk     /* Tx FIFO write active                                                    */
+#define ETH_MACDBGR_TFRS_Pos                          (20U)                    
+#define ETH_MACDBGR_TFRS_Msk                          (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
+#define ETH_MACDBGR_TFRS                              ETH_MACDBGR_TFRS_Msk     /* Tx FIFO read status mask                                                */
+#define ETH_MACDBGR_TFRS_WRITING_Pos                  (20U)                    
+#define ETH_MACDBGR_TFRS_WRITING_Msk                  (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
+#define ETH_MACDBGR_TFRS_WRITING                      ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO                    */
+#define ETH_MACDBGR_TFRS_WAITING_Pos                  (21U)                    
+#define ETH_MACDBGR_TFRS_WAITING_Msk                  (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
+#define ETH_MACDBGR_TFRS_WAITING                      ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter                               */
+#define ETH_MACDBGR_TFRS_READ_Pos                     (20U)                    
+#define ETH_MACDBGR_TFRS_READ_Msk                     (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
+#define ETH_MACDBGR_TFRS_READ                         ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter)                   */
+#define ETH_MACDBGR_TFRS_IDLE                         0x00000000U              /* Idle state                                                              */
+#define ETH_MACDBGR_MTP_Pos                           (19U)                    
+#define ETH_MACDBGR_MTP_Msk                           (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
+#define ETH_MACDBGR_MTP                               ETH_MACDBGR_MTP_Msk      /* MAC transmitter in pause                                                */
+#define ETH_MACDBGR_MTFCS_Pos                         (17U)                    
+#define ETH_MACDBGR_MTFCS_Msk                         (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
+#define ETH_MACDBGR_MTFCS                             ETH_MACDBGR_MTFCS_Msk    /* MAC transmit frame controller status mask                               */
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos            (17U)                    
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk            (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
+#define ETH_MACDBGR_MTFCS_TRANSFERRING                ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission                               */
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos           (18U)                    
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk           (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF               ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MACDBGR_MTFCS_WAITING_Pos                 (17U)                    
+#define ETH_MACDBGR_MTFCS_WAITING_Msk                 (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
+#define ETH_MACDBGR_MTFCS_WAITING                     ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over   */
+#define ETH_MACDBGR_MTFCS_IDLE                        0x00000000U              /* Idle                                                                    */
+#define ETH_MACDBGR_MMTEA_Pos                         (16U)                    
+#define ETH_MACDBGR_MMTEA_Msk                         (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
+#define ETH_MACDBGR_MMTEA                             ETH_MACDBGR_MMTEA_Msk    /* MAC MII transmit engine active                                          */
+#define ETH_MACDBGR_RFFL_Pos                          (8U)                     
+#define ETH_MACDBGR_RFFL_Msk                          (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
+#define ETH_MACDBGR_RFFL                              ETH_MACDBGR_RFFL_Msk     /* Rx FIFO fill level mask                                                 */
+#define ETH_MACDBGR_RFFL_FULL_Pos                     (8U)                     
+#define ETH_MACDBGR_RFFL_FULL_Msk                     (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
+#define ETH_MACDBGR_RFFL_FULL                         ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full                                                             */
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos                 (9U)                     
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk                 (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
+#define ETH_MACDBGR_RFFL_ABOVEFCT                     ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold                 */
+#define ETH_MACDBGR_RFFL_BELOWFCT_Pos                 (8U)                     
+#define ETH_MACDBGR_RFFL_BELOWFCT_Msk                 (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
+#define ETH_MACDBGR_RFFL_BELOWFCT                     ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold              */
+#define ETH_MACDBGR_RFFL_EMPTY                        0x00000000U              /* RxFIFO empty                                                            */
+#define ETH_MACDBGR_RFRCS_Pos                         (5U)                     
+#define ETH_MACDBGR_RFRCS_Msk                         (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
+#define ETH_MACDBGR_RFRCS                             ETH_MACDBGR_RFRCS_Msk    /* Rx FIFO read controller status mask                                     */
+#define ETH_MACDBGR_RFRCS_FLUSHING_Pos                (5U)                     
+#define ETH_MACDBGR_RFRCS_FLUSHING_Msk                (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
+#define ETH_MACDBGR_RFRCS_FLUSHING                    ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status                                      */
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos           (6U)                     
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk           (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
+#define ETH_MACDBGR_RFRCS_STATUSREADING               ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp)                                    */
+#define ETH_MACDBGR_RFRCS_DATAREADING_Pos             (5U)                     
+#define ETH_MACDBGR_RFRCS_DATAREADING_Msk             (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
+#define ETH_MACDBGR_RFRCS_DATAREADING                 ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data                                                      */
+#define ETH_MACDBGR_RFRCS_IDLE                        0x00000000U              /* IDLE state                                                              */
+#define ETH_MACDBGR_RFWRA_Pos                         (4U)                     
+#define ETH_MACDBGR_RFWRA_Msk                         (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
+#define ETH_MACDBGR_RFWRA                             ETH_MACDBGR_RFWRA_Msk    /* Rx FIFO write controller active                                         */
+#define ETH_MACDBGR_MSFRWCS_Pos                       (1U)                     
+#define ETH_MACDBGR_MSFRWCS_Msk                       (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
+#define ETH_MACDBGR_MSFRWCS                           ETH_MACDBGR_MSFRWCS_Msk  /* MAC small FIFO read / write controllers status  mask                    */
+#define ETH_MACDBGR_MSFRWCS_1                         (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
+#define ETH_MACDBGR_MSFRWCS_0                         (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
+#define ETH_MACDBGR_MMRPEA_Pos                        (0U)                     
+#define ETH_MACDBGR_MMRPEA_Msk                        (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
+#define ETH_MACDBGR_MMRPEA                            ETH_MACDBGR_MMRPEA_Msk   /* MAC MII receive protocol engine active                                  */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS_Pos                            (9U)                     
+#define ETH_MACSR_TSTS_Msk                            (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
+#define ETH_MACSR_TSTS                                ETH_MACSR_TSTS_Msk       /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS_Pos                           (6U)                     
+#define ETH_MACSR_MMCTS_Msk                           (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
+#define ETH_MACSR_MMCTS                               ETH_MACSR_MMCTS_Msk      /* MMC transmit status       */
+#define ETH_MACSR_MMMCRS_Pos                          (5U)                     
+#define ETH_MACSR_MMMCRS_Msk                          (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
+#define ETH_MACSR_MMMCRS                              ETH_MACSR_MMMCRS_Msk     /* MMC receive status        */
+#define ETH_MACSR_MMCS_Pos                            (4U)                     
+#define ETH_MACSR_MMCS_Msk                            (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
+#define ETH_MACSR_MMCS                                ETH_MACSR_MMCS_Msk       /* MMC status                */
+#define ETH_MACSR_PMTS_Pos                            (3U)                     
+#define ETH_MACSR_PMTS_Msk                            (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
+#define ETH_MACSR_PMTS                                ETH_MACSR_PMTS_Msk       /* PMT status                */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM_Pos                          (9U)                     
+#define ETH_MACIMR_TSTIM_Msk                          (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
+#define ETH_MACIMR_TSTIM                              ETH_MACIMR_TSTIM_Msk     /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM_Pos                          (3U)                     
+#define ETH_MACIMR_PMTIM_Msk                          (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
+#define ETH_MACIMR_PMTIM                              ETH_MACIMR_PMTIM_Msk     /* PMT interrupt mask                */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H_Pos                        (0U)                     
+#define ETH_MACA0HR_MACA0H_Msk                        (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_MACA0H                            ETH_MACA0HR_MACA0H_Msk   /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L_Pos                        (0U)                     
+#define ETH_MACA0LR_MACA0L_Msk                        (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA0LR_MACA0L                            ETH_MACA0LR_MACA0L_Msk   /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE_Pos                            (31U)                    
+#define ETH_MACA1HR_AE_Msk                            (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk       /* Address enable */
+#define ETH_MACA1HR_SA_Pos                            (30U)                    
+#define ETH_MACA1HR_SA_Msk                            (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk       /* Source address */
+#define ETH_MACA1HR_MBC_Pos                           (24U)                    
+#define ETH_MACA1HR_MBC_Msk                           (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk      /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+#define ETH_MACA1HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA1HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
+#define ETH_MACA1HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA1HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA1HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
+#define ETH_MACA1HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [7:0]   */
+#define ETH_MACA1HR_MACA1H_Pos                        (0U)                     
+#define ETH_MACA1HR_MACA1H_Msk                        (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA1HR_MACA1H                            ETH_MACA1HR_MACA1H_Msk   /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L_Pos                        (0U)                     
+#define ETH_MACA1LR_MACA1L_Msk                        (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA1LR_MACA1L                            ETH_MACA1LR_MACA1L_Msk   /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE_Pos                            (31U)                    
+#define ETH_MACA2HR_AE_Msk                            (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk       /* Address enable */
+#define ETH_MACA2HR_SA_Pos                            (30U)                    
+#define ETH_MACA2HR_SA_Msk                            (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk       /* Source address */
+#define ETH_MACA2HR_MBC_Pos                           (24U)                    
+#define ETH_MACA2HR_MBC_Msk                           (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk      /* Mask byte control */
+#define ETH_MACA2HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA2HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
+#define ETH_MACA2HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA2HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA2HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
+#define ETH_MACA2HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */
+#define ETH_MACA2HR_MACA2H_Pos                        (0U)                     
+#define ETH_MACA2HR_MACA2H_Msk                        (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA2HR_MACA2H                            ETH_MACA2HR_MACA2H_Msk   /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L_Pos                        (0U)                     
+#define ETH_MACA2LR_MACA2L_Msk                        (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA2LR_MACA2L                            ETH_MACA2LR_MACA2L_Msk   /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE_Pos                            (31U)                    
+#define ETH_MACA3HR_AE_Msk                            (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk       /* Address enable */
+#define ETH_MACA3HR_SA_Pos                            (30U)                    
+#define ETH_MACA3HR_SA_Msk                            (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk       /* Source address */
+#define ETH_MACA3HR_MBC_Pos                           (24U)                    
+#define ETH_MACA3HR_MBC_Msk                           (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk      /* Mask byte control */
+#define ETH_MACA3HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA3HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
+#define ETH_MACA3HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA3HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA3HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
+#define ETH_MACA3HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */
+#define ETH_MACA3HR_MACA3H_Pos                        (0U)                     
+#define ETH_MACA3HR_MACA3H_Msk                        (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA3HR_MACA3H                            ETH_MACA3HR_MACA3H_Msk   /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L_Pos                        (0U)                     
+#define ETH_MACA3LR_MACA3L_Msk                        (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA3LR_MACA3L                            ETH_MACA3LR_MACA3L_Msk   /* MAC address3 low */
+
+/******************************************************************************/
+/*                Ethernet MMC Registers bits definition                      */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCFHP_Pos                           (5U)                     
+#define ETH_MMCCR_MCFHP_Msk                           (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_MCFHP                               ETH_MMCCR_MCFHP_Msk      /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP_Pos                             (4U)                     
+#define ETH_MMCCR_MCP_Msk                             (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_MCP                                 ETH_MMCCR_MCP_Msk        /* MMC counter preset           */
+#define ETH_MMCCR_MCF_Pos                             (3U)                     
+#define ETH_MMCCR_MCF_Msk                             (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_MCF                                 ETH_MMCCR_MCF_Msk        /* MMC Counter Freeze           */
+#define ETH_MMCCR_ROR_Pos                             (2U)                     
+#define ETH_MMCCR_ROR_Msk                             (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_ROR                                 ETH_MMCCR_ROR_Msk        /* Reset on Read                */
+#define ETH_MMCCR_CSR_Pos                             (1U)                     
+#define ETH_MMCCR_CSR_Msk                             (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CSR                                 ETH_MMCCR_CSR_Msk        /* Counter Stop Rollover        */
+#define ETH_MMCCR_CR_Pos                              (0U)                     
+#define ETH_MMCCR_CR_Msk                              (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CR                                  ETH_MMCCR_CR_Msk         /* Counters Reset               */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS_Pos                          (17U)                    
+#define ETH_MMCRIR_RGUFS_Msk                          (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RGUFS                              ETH_MMCRIR_RGUFS_Msk     /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES_Pos                          (6U)                     
+#define ETH_MMCRIR_RFAES_Msk                          (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RFAES                              ETH_MMCRIR_RFAES_Msk     /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES_Pos                          (5U)                     
+#define ETH_MMCRIR_RFCES_Msk                          (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RFCES                              ETH_MMCRIR_RFCES_Msk     /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS_Pos                           (21U)                    
+#define ETH_MMCTIR_TGFS_Msk                           (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TGFS                               ETH_MMCTIR_TGFS_Msk      /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS_Pos                        (15U)                    
+#define ETH_MMCTIR_TGFMSCS_Msk                        (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TGFMSCS                            ETH_MMCTIR_TGFMSCS_Msk   /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS_Pos                         (14U)                    
+#define ETH_MMCTIR_TGFSCS_Msk                         (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TGFSCS                             ETH_MMCTIR_TGFSCS_Msk    /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM_Pos                         (17U)                    
+#define ETH_MMCRIMR_RGUFM_Msk                         (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RGUFM                             ETH_MMCRIMR_RGUFM_Msk    /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM_Pos                         (6U)                     
+#define ETH_MMCRIMR_RFAEM_Msk                         (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RFAEM                             ETH_MMCRIMR_RFAEM_Msk    /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM_Pos                         (5U)                     
+#define ETH_MMCRIMR_RFCEM_Msk                         (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RFCEM                             ETH_MMCRIMR_RFCEM_Msk    /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM_Pos                          (21U)                    
+#define ETH_MMCTIMR_TGFM_Msk                          (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TGFM                              ETH_MMCTIMR_TGFM_Msk     /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM_Pos                       (15U)                    
+#define ETH_MMCTIMR_TGFMSCM_Msk                       (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TGFMSCM                           ETH_MMCTIMR_TGFMSCM_Msk  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM_Pos                        (14U)                    
+#define ETH_MMCTIMR_TGFSCM_Msk                        (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TGFSCM                            ETH_MMCTIMR_TGFSCM_Msk   /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC_Pos                     (0U)                     
+#define ETH_MMCTGFSCCR_TGFSCC_Msk                     (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFSCCR_TGFSCC                         ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC_Pos                   (0U)                     
+#define ETH_MMCTGFMSCCR_TGFMSCC_Msk                   (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFMSCCR_TGFMSCC                       ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC_Pos                         (0U)                     
+#define ETH_MMCTGFCR_TGFC_Msk                         (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFCR_TGFC                             ETH_MMCTGFCR_TGFC_Msk    /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC_Pos                       (0U)                     
+#define ETH_MMCRFCECR_RFCEC_Msk                       (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRFCECR_RFCEC                           ETH_MMCRFCECR_RFCEC_Msk  /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC_Pos                       (0U)                     
+#define ETH_MMCRFAECR_RFAEC_Msk                       (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRFAECR_RFAEC                           ETH_MMCRFAECR_RFAEC_Msk  /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC_Pos                       (0U)                     
+#define ETH_MMCRGUFCR_RGUFC_Msk                       (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRGUFCR_RGUFC                           ETH_MMCRGUFCR_RGUFC_Msk  /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/*               Ethernet PTP Registers bits definition                       */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSCNT_Pos                         (16U)                    
+#define ETH_PTPTSCR_TSCNT_Msk                         (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
+#define ETH_PTPTSCR_TSCNT                             ETH_PTPTSCR_TSCNT_Msk    /* Time stamp clock node type */
+#define ETH_PTPTSSR_TSSMRME_Pos                       (15U)                    
+#define ETH_PTPTSSR_TSSMRME_Msk                       (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
+#define ETH_PTPTSSR_TSSMRME                           ETH_PTPTSSR_TSSMRME_Msk  /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSSR_TSSEME_Pos                        (14U)                    
+#define ETH_PTPTSSR_TSSEME_Msk                        (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
+#define ETH_PTPTSSR_TSSEME                            ETH_PTPTSSR_TSSEME_Msk   /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSSR_TSSIPV4FE_Pos                     (13U)                    
+#define ETH_PTPTSSR_TSSIPV4FE_Msk                     (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
+#define ETH_PTPTSSR_TSSIPV4FE                         ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSSR_TSSIPV6FE_Pos                     (12U)                    
+#define ETH_PTPTSSR_TSSIPV6FE_Msk                     (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
+#define ETH_PTPTSSR_TSSIPV6FE                         ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSSR_TSSPTPOEFE_Pos                    (11U)                    
+#define ETH_PTPTSSR_TSSPTPOEFE_Msk                    (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
+#define ETH_PTPTSSR_TSSPTPOEFE                        ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSSR_TSPTPPSV2E_Pos                    (10U)                    
+#define ETH_PTPTSSR_TSPTPPSV2E_Msk                    (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
+#define ETH_PTPTSSR_TSPTPPSV2E                        ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSSR_TSSSR_Pos                         (9U)                     
+#define ETH_PTPTSSR_TSSSR_Msk                         (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
+#define ETH_PTPTSSR_TSSSR                             ETH_PTPTSSR_TSSSR_Msk    /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSSR_TSSARFE_Pos                       (8U)                     
+#define ETH_PTPTSSR_TSSARFE_Msk                       (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
+#define ETH_PTPTSSR_TSSARFE                           ETH_PTPTSSR_TSSARFE_Msk  /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU_Pos                         (5U)                     
+#define ETH_PTPTSCR_TSARU_Msk                         (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
+#define ETH_PTPTSCR_TSARU                             ETH_PTPTSCR_TSARU_Msk    /* Addend register update */
+#define ETH_PTPTSCR_TSITE_Pos                         (4U)                     
+#define ETH_PTPTSCR_TSITE_Msk                         (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
+#define ETH_PTPTSCR_TSITE                             ETH_PTPTSCR_TSITE_Msk    /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU_Pos                         (3U)                     
+#define ETH_PTPTSCR_TSSTU_Msk                         (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
+#define ETH_PTPTSCR_TSSTU                             ETH_PTPTSCR_TSSTU_Msk    /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI_Pos                         (2U)                     
+#define ETH_PTPTSCR_TSSTI_Msk                         (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
+#define ETH_PTPTSCR_TSSTI                             ETH_PTPTSCR_TSSTI_Msk    /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU_Pos                         (1U)                     
+#define ETH_PTPTSCR_TSFCU_Msk                         (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
+#define ETH_PTPTSCR_TSFCU                             ETH_PTPTSCR_TSFCU_Msk    /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE_Pos                           (0U)                     
+#define ETH_PTPTSCR_TSE_Msk                           (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
+#define ETH_PTPTSCR_TSE                               ETH_PTPTSCR_TSE_Msk      /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI_Pos                         (0U)                     
+#define ETH_PTPSSIR_STSSI_Msk                         (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
+#define ETH_PTPSSIR_STSSI                             ETH_PTPSSIR_STSSI_Msk    /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS_Pos                           (0U)                     
+#define ETH_PTPTSHR_STS_Msk                           (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSHR_STS                               ETH_PTPTSHR_STS_Msk      /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS_Pos                         (31U)                    
+#define ETH_PTPTSLR_STPNS_Msk                         (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
+#define ETH_PTPTSLR_STPNS                             ETH_PTPTSLR_STPNS_Msk    /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS_Pos                          (0U)                     
+#define ETH_PTPTSLR_STSS_Msk                          (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_PTPTSLR_STSS                              ETH_PTPTSLR_STSS_Msk     /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS_Pos                         (0U)                     
+#define ETH_PTPTSHUR_TSUS_Msk                         (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSHUR_TSUS                             ETH_PTPTSHUR_TSUS_Msk    /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS_Pos                       (31U)                    
+#define ETH_PTPTSLUR_TSUPNS_Msk                       (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
+#define ETH_PTPTSLUR_TSUPNS                           ETH_PTPTSLUR_TSUPNS_Msk  /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS_Pos                        (0U)                     
+#define ETH_PTPTSLUR_TSUSS_Msk                        (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_PTPTSLUR_TSUSS                            ETH_PTPTSLUR_TSUSS_Msk   /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA_Pos                           (0U)                     
+#define ETH_PTPTSAR_TSA_Msk                           (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSAR_TSA                               ETH_PTPTSAR_TSA_Msk      /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH_Pos                          (0U)                     
+#define ETH_PTPTTHR_TTSH_Msk                          (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTTHR_TTSH                              ETH_PTPTTHR_TTSH_Msk     /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL_Pos                          (0U)                     
+#define ETH_PTPTTLR_TTSL_Msk                          (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTTLR_TTSL                              ETH_PTPTTLR_TTSL_Msk     /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR_Pos                         (5U)                     
+#define ETH_PTPTSSR_TSTTR_Msk                         (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
+#define ETH_PTPTSSR_TSTTR                             ETH_PTPTSSR_TSTTR_Msk    /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO_Pos                          (4U)                     
+#define ETH_PTPTSSR_TSSO_Msk                          (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
+#define ETH_PTPTSSR_TSSO                              ETH_PTPTSSR_TSSO_Msk     /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/*                 Ethernet DMA Registers bits definition                     */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB_Pos                            (25U)                    
+#define ETH_DMABMR_AAB_Msk                            (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
+#define ETH_DMABMR_AAB                                ETH_DMABMR_AAB_Msk       /* Address-Aligned beats */
+#define ETH_DMABMR_FPM_Pos                            (24U)                    
+#define ETH_DMABMR_FPM_Msk                            (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
+#define ETH_DMABMR_FPM                                ETH_DMABMR_FPM_Msk       /* 4xPBL mode */
+#define ETH_DMABMR_USP_Pos                            (23U)                    
+#define ETH_DMABMR_USP_Msk                            (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
+#define ETH_DMABMR_USP                                ETH_DMABMR_USP_Msk       /* Use separate PBL */
+#define ETH_DMABMR_RDP_Pos                            (17U)                    
+#define ETH_DMABMR_RDP_Msk                            (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
+#define ETH_DMABMR_RDP                                ETH_DMABMR_RDP_Msk       /* RxDMA PBL */
+#define ETH_DMABMR_RDP_1Beat                          0x00020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_DMABMR_RDP_2Beat                          0x00040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_DMABMR_RDP_4Beat                          0x00080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_8Beat                          0x00100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_16Beat                         0x00200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_32Beat                         0x00400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+#define ETH_DMABMR_RDP_4xPBL_4Beat                    0x01020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_4xPBL_8Beat                    0x01040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_4xPBL_16Beat                   0x01080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_4xPBL_32Beat                   0x01100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABMR_RDP_4xPBL_64Beat                   0x01200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_DMABMR_RDP_4xPBL_128Beat                  0x01400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
+#define ETH_DMABMR_FB_Pos                             (16U)                    
+#define ETH_DMABMR_FB_Msk                             (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
+#define ETH_DMABMR_FB                                 ETH_DMABMR_FB_Msk        /* Fixed Burst */
+#define ETH_DMABMR_RTPR_Pos                           (14U)                    
+#define ETH_DMABMR_RTPR_Msk                           (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
+#define ETH_DMABMR_RTPR                               ETH_DMABMR_RTPR_Msk      /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_1_1                           0x00000000U              /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_2_1                           0x00004000U              /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_3_1                           0x00008000U              /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_4_1                           0x0000C000U              /* Rx Tx priority ratio */  
+#define ETH_DMABMR_PBL_Pos                            (8U)                     
+#define ETH_DMABMR_PBL_Msk                            (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
+#define ETH_DMABMR_PBL                                ETH_DMABMR_PBL_Msk       /* Programmable burst length */
+#define ETH_DMABMR_PBL_1Beat                          0x00000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_DMABMR_PBL_2Beat                          0x00000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_DMABMR_PBL_4Beat                          0x00000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_8Beat                          0x00000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_16Beat                         0x00001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_32Beat                         0x00002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+#define ETH_DMABMR_PBL_4xPBL_4Beat                    0x01000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_4xPBL_8Beat                    0x01000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_4xPBL_16Beat                   0x01000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_4xPBL_32Beat                   0x01000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABMR_PBL_4xPBL_64Beat                   0x01001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_DMABMR_PBL_4xPBL_128Beat                  0x01002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE_Pos                            (7U)                     
+#define ETH_DMABMR_EDE_Msk                            (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
+#define ETH_DMABMR_EDE                                ETH_DMABMR_EDE_Msk       /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL_Pos                            (2U)                     
+#define ETH_DMABMR_DSL_Msk                            (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
+#define ETH_DMABMR_DSL                                ETH_DMABMR_DSL_Msk       /* Descriptor Skip Length */
+#define ETH_DMABMR_DA_Pos                             (1U)                     
+#define ETH_DMABMR_DA_Msk                             (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
+#define ETH_DMABMR_DA                                 ETH_DMABMR_DA_Msk        /* DMA arbitration scheme */
+#define ETH_DMABMR_SR_Pos                             (0U)                     
+#define ETH_DMABMR_SR_Msk                             (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMABMR_SR                                 ETH_DMABMR_SR_Msk        /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD_Pos                           (0U)                     
+#define ETH_DMATPDR_TPD_Msk                           (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMATPDR_TPD                               ETH_DMATPDR_TPD_Msk      /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD_Pos                           (0U)                     
+#define ETH_DMARPDR_RPD_Msk                           (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMARPDR_RPD                               ETH_DMARPDR_RPD_Msk      /* Receive poll demand  */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL_Pos                          (0U)                     
+#define ETH_DMARDLAR_SRL_Msk                          (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMARDLAR_SRL                              ETH_DMARDLAR_SRL_Msk     /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL_Pos                          (0U)                     
+#define ETH_DMATDLAR_STL_Msk                          (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMATDLAR_STL                              ETH_DMATDLAR_STL_Msk     /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS_Pos                            (29U)                    
+#define ETH_DMASR_TSTS_Msk                            (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
+#define ETH_DMASR_TSTS                                ETH_DMASR_TSTS_Msk       /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS_Pos                            (28U)                    
+#define ETH_DMASR_PMTS_Msk                            (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
+#define ETH_DMASR_PMTS                                ETH_DMASR_PMTS_Msk       /* PMT status */
+#define ETH_DMASR_MMCS_Pos                            (27U)                    
+#define ETH_DMASR_MMCS_Msk                            (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
+#define ETH_DMASR_MMCS                                ETH_DMASR_MMCS_Msk       /* MMC status */
+#define ETH_DMASR_EBS_Pos                             (23U)                    
+#define ETH_DMASR_EBS_Msk                             (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
+#define ETH_DMASR_EBS                                 ETH_DMASR_EBS_Msk        /* Error bits status */
+  /* combination with EBS[2:0] for GetFlagStatus function */
+#define ETH_DMASR_EBS_DescAccess_Pos                  (25U)                    
+#define ETH_DMASR_EBS_DescAccess_Msk                  (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
+#define ETH_DMASR_EBS_DescAccess                      ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMASR_EBS_ReadTransf_Pos                  (24U)                    
+#define ETH_DMASR_EBS_ReadTransf_Msk                  (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
+#define ETH_DMASR_EBS_ReadTransf                      ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMASR_EBS_DataTransfTx_Pos                (23U)                    
+#define ETH_DMASR_EBS_DataTransfTx_Msk                (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
+#define ETH_DMASR_EBS_DataTransfTx                    ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS_Pos                             (20U)                    
+#define ETH_DMASR_TPS_Msk                             (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
+#define ETH_DMASR_TPS                                 ETH_DMASR_TPS_Msk        /* Transmit process state */
+#define ETH_DMASR_TPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Tx Command issued  */
+#define ETH_DMASR_TPS_Fetching_Pos                    (20U)                    
+#define ETH_DMASR_TPS_Fetching_Msk                    (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
+#define ETH_DMASR_TPS_Fetching                        ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
+#define ETH_DMASR_TPS_Waiting_Pos                     (21U)                    
+#define ETH_DMASR_TPS_Waiting_Msk                     (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
+#define ETH_DMASR_TPS_Waiting                         ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
+#define ETH_DMASR_TPS_Reading_Pos                     (20U)                    
+#define ETH_DMASR_TPS_Reading_Msk                     (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
+#define ETH_DMASR_TPS_Reading                         ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
+#define ETH_DMASR_TPS_Suspended_Pos                   (21U)                    
+#define ETH_DMASR_TPS_Suspended_Msk                   (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
+#define ETH_DMASR_TPS_Suspended                       ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
+#define ETH_DMASR_TPS_Closing_Pos                     (20U)                    
+#define ETH_DMASR_TPS_Closing_Msk                     (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
+#define ETH_DMASR_TPS_Closing                         ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS_Pos                             (17U)                    
+#define ETH_DMASR_RPS_Msk                             (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
+#define ETH_DMASR_RPS                                 ETH_DMASR_RPS_Msk        /* Receive process state */
+#define ETH_DMASR_RPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMASR_RPS_Fetching_Pos                    (17U)                    
+#define ETH_DMASR_RPS_Fetching_Msk                    (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
+#define ETH_DMASR_RPS_Fetching                        ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
+#define ETH_DMASR_RPS_Waiting_Pos                     (17U)                    
+#define ETH_DMASR_RPS_Waiting_Msk                     (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
+#define ETH_DMASR_RPS_Waiting                         ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
+#define ETH_DMASR_RPS_Suspended_Pos                   (19U)                    
+#define ETH_DMASR_RPS_Suspended_Msk                   (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
+#define ETH_DMASR_RPS_Suspended                       ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
+#define ETH_DMASR_RPS_Closing_Pos                     (17U)                    
+#define ETH_DMASR_RPS_Closing_Msk                     (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
+#define ETH_DMASR_RPS_Closing                         ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
+#define ETH_DMASR_RPS_Queuing_Pos                     (17U)                    
+#define ETH_DMASR_RPS_Queuing_Msk                     (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
+#define ETH_DMASR_RPS_Queuing                         ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS_Pos                             (16U)                    
+#define ETH_DMASR_NIS_Msk                             (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
+#define ETH_DMASR_NIS                                 ETH_DMASR_NIS_Msk        /* Normal interrupt summary */
+#define ETH_DMASR_AIS_Pos                             (15U)                    
+#define ETH_DMASR_AIS_Msk                             (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
+#define ETH_DMASR_AIS                                 ETH_DMASR_AIS_Msk        /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS_Pos                             (14U)                    
+#define ETH_DMASR_ERS_Msk                             (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
+#define ETH_DMASR_ERS                                 ETH_DMASR_ERS_Msk        /* Early receive status */
+#define ETH_DMASR_FBES_Pos                            (13U)                    
+#define ETH_DMASR_FBES_Msk                            (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
+#define ETH_DMASR_FBES                                ETH_DMASR_FBES_Msk       /* Fatal bus error status */
+#define ETH_DMASR_ETS_Pos                             (10U)                    
+#define ETH_DMASR_ETS_Msk                             (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
+#define ETH_DMASR_ETS                                 ETH_DMASR_ETS_Msk        /* Early transmit status */
+#define ETH_DMASR_RWTS_Pos                            (9U)                     
+#define ETH_DMASR_RWTS_Msk                            (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
+#define ETH_DMASR_RWTS                                ETH_DMASR_RWTS_Msk       /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS_Pos                            (8U)                     
+#define ETH_DMASR_RPSS_Msk                            (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
+#define ETH_DMASR_RPSS                                ETH_DMASR_RPSS_Msk       /* Receive process stopped status */
+#define ETH_DMASR_RBUS_Pos                            (7U)                     
+#define ETH_DMASR_RBUS_Msk                            (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
+#define ETH_DMASR_RBUS                                ETH_DMASR_RBUS_Msk       /* Receive buffer unavailable status */
+#define ETH_DMASR_RS_Pos                              (6U)                     
+#define ETH_DMASR_RS_Msk                              (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
+#define ETH_DMASR_RS                                  ETH_DMASR_RS_Msk         /* Receive status */
+#define ETH_DMASR_TUS_Pos                             (5U)                     
+#define ETH_DMASR_TUS_Msk                             (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
+#define ETH_DMASR_TUS                                 ETH_DMASR_TUS_Msk        /* Transmit underflow status */
+#define ETH_DMASR_ROS_Pos                             (4U)                     
+#define ETH_DMASR_ROS_Msk                             (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
+#define ETH_DMASR_ROS                                 ETH_DMASR_ROS_Msk        /* Receive overflow status */
+#define ETH_DMASR_TJTS_Pos                            (3U)                     
+#define ETH_DMASR_TJTS_Msk                            (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
+#define ETH_DMASR_TJTS                                ETH_DMASR_TJTS_Msk       /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS_Pos                            (2U)                     
+#define ETH_DMASR_TBUS_Msk                            (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
+#define ETH_DMASR_TBUS                                ETH_DMASR_TBUS_Msk       /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS_Pos                            (1U)                     
+#define ETH_DMASR_TPSS_Msk                            (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
+#define ETH_DMASR_TPSS                                ETH_DMASR_TPSS_Msk       /* Transmit process stopped status */
+#define ETH_DMASR_TS_Pos                              (0U)                     
+#define ETH_DMASR_TS_Msk                              (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
+#define ETH_DMASR_TS                                  ETH_DMASR_TS_Msk         /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD_Pos                         (26U)                    
+#define ETH_DMAOMR_DTCEFD_Msk                         (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
+#define ETH_DMAOMR_DTCEFD                             ETH_DMAOMR_DTCEFD_Msk    /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF_Pos                            (25U)                    
+#define ETH_DMAOMR_RSF_Msk                            (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
+#define ETH_DMAOMR_RSF                                ETH_DMAOMR_RSF_Msk       /* Receive store and forward */
+#define ETH_DMAOMR_DFRF_Pos                           (24U)                    
+#define ETH_DMAOMR_DFRF_Msk                           (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
+#define ETH_DMAOMR_DFRF                               ETH_DMAOMR_DFRF_Msk      /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF_Pos                            (21U)                    
+#define ETH_DMAOMR_TSF_Msk                            (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
+#define ETH_DMAOMR_TSF                                ETH_DMAOMR_TSF_Msk       /* Transmit store and forward */
+#define ETH_DMAOMR_FTF_Pos                            (20U)                    
+#define ETH_DMAOMR_FTF_Msk                            (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
+#define ETH_DMAOMR_FTF                                ETH_DMAOMR_FTF_Msk       /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC_Pos                            (14U)                    
+#define ETH_DMAOMR_TTC_Msk                            (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
+#define ETH_DMAOMR_TTC                                ETH_DMAOMR_TTC_Msk       /* Transmit threshold control */
+#define ETH_DMAOMR_TTC_64Bytes                        0x00000000U              /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_DMAOMR_TTC_128Bytes                       0x00004000U              /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_DMAOMR_TTC_192Bytes                       0x00008000U              /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_DMAOMR_TTC_256Bytes                       0x0000C000U              /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_DMAOMR_TTC_40Bytes                        0x00010000U              /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_DMAOMR_TTC_32Bytes                        0x00014000U              /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_DMAOMR_TTC_24Bytes                        0x00018000U              /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_DMAOMR_TTC_16Bytes                        0x0001C000U              /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST_Pos                             (13U)                    
+#define ETH_DMAOMR_ST_Msk                             (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
+#define ETH_DMAOMR_ST                                 ETH_DMAOMR_ST_Msk        /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF_Pos                            (7U)                     
+#define ETH_DMAOMR_FEF_Msk                            (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
+#define ETH_DMAOMR_FEF                                ETH_DMAOMR_FEF_Msk       /* Forward error frames */
+#define ETH_DMAOMR_FUGF_Pos                           (6U)                     
+#define ETH_DMAOMR_FUGF_Msk                           (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
+#define ETH_DMAOMR_FUGF                               ETH_DMAOMR_FUGF_Msk      /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC_Pos                            (3U)                     
+#define ETH_DMAOMR_RTC_Msk                            (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
+#define ETH_DMAOMR_RTC                                ETH_DMAOMR_RTC_Msk       /* receive threshold control */
+#define ETH_DMAOMR_RTC_64Bytes                        0x00000000U              /* threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_DMAOMR_RTC_32Bytes                        0x00000008U              /* threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_DMAOMR_RTC_96Bytes                        0x00000010U              /* threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_DMAOMR_RTC_128Bytes                       0x00000018U              /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF_Pos                            (2U)                     
+#define ETH_DMAOMR_OSF_Msk                            (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
+#define ETH_DMAOMR_OSF                                ETH_DMAOMR_OSF_Msk       /* operate on second frame */
+#define ETH_DMAOMR_SR_Pos                             (1U)                     
+#define ETH_DMAOMR_SR_Msk                             (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
+#define ETH_DMAOMR_SR                                 ETH_DMAOMR_SR_Msk        /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE_Pos                           (16U)                    
+#define ETH_DMAIER_NISE_Msk                           (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
+#define ETH_DMAIER_NISE                               ETH_DMAIER_NISE_Msk      /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE_Pos                           (15U)                    
+#define ETH_DMAIER_AISE_Msk                           (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
+#define ETH_DMAIER_AISE                               ETH_DMAIER_AISE_Msk      /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE_Pos                           (14U)                    
+#define ETH_DMAIER_ERIE_Msk                           (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
+#define ETH_DMAIER_ERIE                               ETH_DMAIER_ERIE_Msk      /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE_Pos                          (13U)                    
+#define ETH_DMAIER_FBEIE_Msk                          (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
+#define ETH_DMAIER_FBEIE                              ETH_DMAIER_FBEIE_Msk     /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE_Pos                           (10U)                    
+#define ETH_DMAIER_ETIE_Msk                           (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMAIER_ETIE                               ETH_DMAIER_ETIE_Msk      /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE_Pos                          (9U)                     
+#define ETH_DMAIER_RWTIE_Msk                          (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
+#define ETH_DMAIER_RWTIE                              ETH_DMAIER_RWTIE_Msk     /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE_Pos                          (8U)                     
+#define ETH_DMAIER_RPSIE_Msk                          (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
+#define ETH_DMAIER_RPSIE                              ETH_DMAIER_RPSIE_Msk     /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE_Pos                          (7U)                     
+#define ETH_DMAIER_RBUIE_Msk                          (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
+#define ETH_DMAIER_RBUIE                              ETH_DMAIER_RBUIE_Msk     /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE_Pos                            (6U)                     
+#define ETH_DMAIER_RIE_Msk                            (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMAIER_RIE                                ETH_DMAIER_RIE_Msk       /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE_Pos                           (5U)                     
+#define ETH_DMAIER_TUIE_Msk                           (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
+#define ETH_DMAIER_TUIE                               ETH_DMAIER_TUIE_Msk      /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE_Pos                           (4U)                     
+#define ETH_DMAIER_ROIE_Msk                           (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
+#define ETH_DMAIER_ROIE                               ETH_DMAIER_ROIE_Msk      /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE_Pos                          (3U)                     
+#define ETH_DMAIER_TJTIE_Msk                          (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
+#define ETH_DMAIER_TJTIE                              ETH_DMAIER_TJTIE_Msk     /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE_Pos                          (2U)                     
+#define ETH_DMAIER_TBUIE_Msk                          (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
+#define ETH_DMAIER_TBUIE                              ETH_DMAIER_TBUIE_Msk     /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE_Pos                          (1U)                     
+#define ETH_DMAIER_TPSIE_Msk                          (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
+#define ETH_DMAIER_TPSIE                              ETH_DMAIER_TPSIE_Msk     /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE_Pos                            (0U)                     
+#define ETH_DMAIER_TIE_Msk                            (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMAIER_TIE                                ETH_DMAIER_TIE_Msk       /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC_Pos                        (28U)                    
+#define ETH_DMAMFBOCR_OFOC_Msk                        (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
+#define ETH_DMAMFBOCR_OFOC                            ETH_DMAMFBOCR_OFOC_Msk   /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA_Pos                         (17U)                    
+#define ETH_DMAMFBOCR_MFA_Msk                         (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
+#define ETH_DMAMFBOCR_MFA                             ETH_DMAMFBOCR_MFA_Msk    /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC_Pos                        (16U)                    
+#define ETH_DMAMFBOCR_OMFC_Msk                        (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
+#define ETH_DMAMFBOCR_OMFC                            ETH_DMAMFBOCR_OMFC_Msk   /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC_Pos                         (0U)                     
+#define ETH_DMAMFBOCR_MFC_Msk                         (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
+#define ETH_DMAMFBOCR_MFC                             ETH_DMAMFBOCR_MFC_Msk    /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP_Pos                        (0U)                     
+#define ETH_DMACHTDR_HTDAP_Msk                        (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHTDR_HTDAP                            ETH_DMACHTDR_HTDAP_Msk   /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP_Pos                        (0U)                     
+#define ETH_DMACHRDR_HRDAP_Msk                        (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHRDR_HRDAP                            ETH_DMACHRDR_HRDAP_Msk   /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP_Pos                       (0U)                     
+#define ETH_DMACHTBAR_HTBAP_Msk                       (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHTBAR_HTBAP                           ETH_DMACHTBAR_HTBAP_Msk  /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP_Pos                       (0U)                     
+#define ETH_DMACHRBAR_HRBAP_Msk                       (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHRBAR_HRBAP                           ETH_DMACHRBAR_HRBAP_Msk  /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)                          
+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)                          
+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)                          
+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)                          
+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)                         
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)                         
+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)                         
+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)                         
+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)                         
+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSVLD_Pos                (19U)                         
+#define USB_OTG_GOTGCTL_BSVLD_Msk                (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSVLD                    USB_OTG_GOTGCTL_BSVLD_Msk     /*!< B-session valid */
+
+/********************  Bit definition forUSB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)                          
+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)                          
+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
+
+/********************  Bit definition for USB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                    (0U)                          
+#define USB_OTG_DCFG_DSPD_Msk                    (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                      (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                      (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)                          
+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos                     (4U)                          
+#define USB_OTG_DCFG_DAD_Msk                     (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                       (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                       (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                       (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                       (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                       (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                       (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                       (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)                         
+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                     (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                     (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)                         
+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for USB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)                          
+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)                          
+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)                          
+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
+
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)                          
+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)                          
+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)                          
+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)                         
+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)                         
+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)                         
+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
+
+/********************  Bit definition for USB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)                          
+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                    (1U)                          
+#define USB_OTG_DCTL_SDIS_Msk                    (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)                          
+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)                          
+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
+
+#define USB_OTG_DCTL_TCTL_Pos                    (4U)                          
+#define USB_OTG_DCTL_TCTL_Msk                    (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                      (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                      (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                      (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)                          
+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)                          
+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)                          
+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)                         
+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)                         
+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+
+/********************  Bit definition for USB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)                          
+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
+
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)                          
+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)                         
+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
+
+/********************  Bit definition for USB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)                          
+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)                          
+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                    (3U)                          
+#define USB_OTG_DSTS_EERR_Msk                    (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)                          
+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
+
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)                          
+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)                          
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)                          
+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)                          
+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)                          
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)                          
+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)                          
+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)                          
+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)                          
+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)                         
+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)                         
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)                         
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)                         
+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)                         
+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)                         
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)                         
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)                         
+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)                         
+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)                         
+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)                         
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)                         
+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)                         
+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)                         
+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)                          
+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)                          
+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)                          
+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)                          
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)                          
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)                          
+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)                         
+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)                         
+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
+
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)                          
+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)                          
+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)                          
+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)                          
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)                          
+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)                          
+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)                          
+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)                          
+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
+
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)                          
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)                         
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)                         
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for USB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                  (0U)                          
+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
+
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)                          
+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)                          
+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)                          
+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)                          
+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)                          
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask */
+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)                          
+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)                          
+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
+
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)                          
+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)                          
+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)                          
+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)                          
+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)                          
+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)                          
+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)                          
+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)                          
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)                         
+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)                         
+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)                         
+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)                         
+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)                         
+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)                         
+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)                         
+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)                         
+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)                         
+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)                         
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)                         
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)                         
+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)                         
+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)                         
+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)                         
+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)                         
+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)                         
+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)                         
+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
+
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)                          
+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)                          
+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)                          
+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)                          
+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)                          
+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)                          
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)                          
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)                         
+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)                         
+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)                         
+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)                         
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)                         
+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)                         
+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)                         
+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)                         
+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)                         
+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)                         
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)                         
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)                         
+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)                         
+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)                         
+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)                         
+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)                         
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)                         
+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)                         
+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)                         
+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
+
+/********************  Bit definition for USB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)                          
+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)                         
+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)                          
+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)                          
+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)                          
+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)                         
+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)                         
+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)                          
+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)                         
+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM_Pos                        (0U)                          
+#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)                          
+#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
+
+#define USB_OTG_DPID_Pos                         (15U)                         
+#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos                       (17U)                         
+#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos                        (0U)                          
+#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos                       (21U)                         
+#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM_Pos                        (0U)                          
+#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)                          
+#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
+
+#define USB_OTG_DPID_Pos                         (15U)                         
+#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos                       (17U)                         
+#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos                        (0U)                          
+#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos                       (21U)                         
+#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)                          
+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)                          
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                      (0U)                          
+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                       (16U)                         
+#define USB_OTG_NPTXFD_Msk                       (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA_Pos                       (0U)                          
+#define USB_OTG_TX0FSA_Msk                       (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD_Pos                        (16U)                         
+#define USB_OTG_TX0FD_Msk                        (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
+
+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)                          
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)                          
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)                         
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)                         
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)                          
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)                          
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)                          
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)                         
+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)                         
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)                         
+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
+
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)                          
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)                          
+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)                         
+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition for USB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)                         
+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN_Pos               (17U)                         
+#define USB_OTG_GCCFG_I2CPADEN_Msk               (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_I2CPADEN                   USB_OTG_GCCFG_I2CPADEN_Msk    /*!< Enable I2C bus connection for the external I2C PHY interface*/ 
+#define USB_OTG_GCCFG_VBUSASEN_Pos               (18U)                         
+#define USB_OTG_GCCFG_VBUSASEN_Msk               (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_VBUSASEN                   USB_OTG_GCCFG_VBUSASEN_Msk    /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN_Pos               (19U)                         
+#define USB_OTG_GCCFG_VBUSBSEN_Msk               (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_VBUSBSEN                   USB_OTG_GCCFG_VBUSBSEN_Msk    /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN_Pos               (20U)                         
+#define USB_OTG_GCCFG_SOFOUTEN_Msk               (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SOFOUTEN                   USB_OTG_GCCFG_SOFOUTEN_Msk    /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS_Pos             (21U)                         
+#define USB_OTG_GCCFG_NOVBUSSENS_Msk             (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_NOVBUSSENS                 USB_OTG_GCCFG_NOVBUSSENS_Msk  /*!< VBUS sensing disable option*/ 
+
+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)                          
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)                         
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition for USB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)                          
+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)                          
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)                          
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)                          
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)                          
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)                          
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)                          
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)                          
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)                         
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */
+
+/********************  Bit definition for USB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)                          
+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET_Pos                   (1U)                          
+#define USB_OTG_HPRT_PCDET_Msk                   (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA_Pos                    (2U)                          
+#define USB_OTG_HPRT_PENA_Msk                    (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)                          
+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                    (4U)                          
+#define USB_OTG_HPRT_POCA_Msk                    (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)                          
+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES_Pos                    (6U)                          
+#define USB_OTG_HPRT_PRES_Msk                    (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */
+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)                          
+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */
+#define USB_OTG_HPRT_PRST_Pos                    (8U)                          
+#define USB_OTG_HPRT_PRST_Msk                    (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */
+
+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)                         
+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */
+#define USB_OTG_HPRT_PLSTS_0                     (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                     (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                    (12U)                         
+#define USB_OTG_HPRT_PPWR_Msk                    (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */
+
+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)                         
+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */
+#define USB_OTG_HPRT_PTCTL_0                     (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                     (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                     (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                     (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                    (17U)                         
+#define USB_OTG_HPRT_PSPD_Msk                    (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */
+#define USB_OTG_HPRT_PSPD_0                      (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                      (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)                          
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)                          
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)                          
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)                          
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)                          
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)                          
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)                          
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)                         
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)                         
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)                         
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */
+
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)                          
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)                         
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */
+
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)                          
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */
+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)                         
+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)                         
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)                         
+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)                         
+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */
+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)                         
+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)                         
+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */
+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)                         
+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */
+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)                         
+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)                         
+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */
+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)                         
+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */
+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)                         
+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */
+
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)                          
+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)                         
+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)                         
+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)                         
+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)                         
+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos                    (20U)                         
+#define USB_OTG_HCCHAR_MC_Msk                    (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                      (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                      (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)                         
+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                     (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                     (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                     (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                     (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                     (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                     (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                     (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)                         
+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)                         
+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)                         
+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
+
+/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)                          
+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)                          
+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)                         
+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)                         
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)                         
+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
+
+/********************  Bit definition for USB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                   (0U)                          
+#define USB_OTG_HCINT_XFRC_Msk                   (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                    (1U)                          
+#define USB_OTG_HCINT_CHH_Msk                    (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)                          
+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                  (3U)                          
+#define USB_OTG_HCINT_STALL_Msk                  (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                    (4U)                          
+#define USB_OTG_HCINT_NAK_Msk                    (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                    (5U)                          
+#define USB_OTG_HCINT_ACK_Msk                    (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                   (6U)                          
+#define USB_OTG_HCINT_NYET_Msk                   (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                  (7U)                          
+#define USB_OTG_HCINT_TXERR_Msk                  (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                  (8U)                          
+#define USB_OTG_HCINT_BBERR_Msk                  (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)                          
+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                  (10U)                         
+#define USB_OTG_HCINT_DTERR_Msk                  (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
+
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)                          
+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)                          
+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)                          
+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)                          
+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)                          
+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)                          
+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)                          
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)                          
+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)                         
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)                         
+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)                         
+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
+
+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)                          
+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)                          
+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)                          
+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)                          
+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)                          
+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)                          
+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)                          
+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)                          
+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)                          
+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)                          
+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)                         
+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)                          
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)                         
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)                         
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)                          
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)                         
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)                         
+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)                         
+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                    (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)                          
+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)                          
+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)                          
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)                          
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)                         
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)                          
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)                         
+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)                         
+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)                         
+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)                         
+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)                         
+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)                         
+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)                         
+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)                         
+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)                         
+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)                         
+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)                          
+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)                          
+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)                          
+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)                          
+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)                          
+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)                         
+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
+
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)                          
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)                         
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)                         
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)                          
+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)                          
+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)                          
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+                                       ((INSTANCE) == ADC2) || \
+                                       ((INSTANCE) == ADC3))
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+                                       ((INSTANCE) == CAN2))
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+                                              ((INSTANCE) == DMA1_Stream1) || \
+                                              ((INSTANCE) == DMA1_Stream2) || \
+                                              ((INSTANCE) == DMA1_Stream3) || \
+                                              ((INSTANCE) == DMA1_Stream4) || \
+                                              ((INSTANCE) == DMA1_Stream5) || \
+                                              ((INSTANCE) == DMA1_Stream6) || \
+                                              ((INSTANCE) == DMA1_Stream7) || \
+                                              ((INSTANCE) == DMA2_Stream0) || \
+                                              ((INSTANCE) == DMA2_Stream1) || \
+                                              ((INSTANCE) == DMA2_Stream2) || \
+                                              ((INSTANCE) == DMA2_Stream3) || \
+                                              ((INSTANCE) == DMA2_Stream4) || \
+                                              ((INSTANCE) == DMA2_Stream5) || \
+                                              ((INSTANCE) == DMA2_Stream6) || \
+                                              ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOF) || \
+                                        ((INSTANCE) == GPIOG) || \
+                                        ((INSTANCE) == GPIOH) || \
+                                        ((INSTANCE) == GPIOI) || \
+                                        ((INSTANCE) == GPIOJ) || \
+                                        ((INSTANCE) == GPIOK))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3))
+
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == I2S2ext)|| \
+                                           ((INSTANCE) == I2S3ext))
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/******************************* SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+                                     ((PERIPH) == SAI1_Block_B))
+/* Legacy define */
+
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1)  || \
+                                       ((INSTANCE) == SPI2)  || \
+                                       ((INSTANCE) == SPI3)  || \
+                                       ((INSTANCE) == SPI4)  || \
+                                       ((INSTANCE) == SPI5)  || \
+                                       ((INSTANCE) == SPI6))
+
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
+                                    ((INSTANCE) == TIM2) || \
+                                    ((INSTANCE) == TIM3) || \
+                                    ((INSTANCE) == TIM4) || \
+                                    ((INSTANCE) == TIM5) || \
+                                    ((INSTANCE) == TIM6) || \
+                                    ((INSTANCE) == TIM7) || \
+                                    ((INSTANCE) == TIM8) || \
+                                    ((INSTANCE) == TIM9) || \
+                                    ((INSTANCE) == TIM10)|| \
+                                    ((INSTANCE) == TIM11)|| \
+                                    ((INSTANCE) == TIM12)|| \
+                                    ((INSTANCE) == TIM13)|| \
+                                    ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
+                                         ((INSTANCE) == TIM2)  || \
+                                         ((INSTANCE) == TIM3)  || \
+                                         ((INSTANCE) == TIM4)  || \
+                                         ((INSTANCE) == TIM5)  || \
+                                         ((INSTANCE) == TIM8)  || \
+                                         ((INSTANCE) == TIM9)  || \
+                                         ((INSTANCE) == TIM10) || \
+                                         ((INSTANCE) == TIM11) || \
+                                         ((INSTANCE) == TIM12) || \
+                                         ((INSTANCE) == TIM13) || \
+                                         ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                       ((INSTANCE) == TIM2) || \
+                                       ((INSTANCE) == TIM3) || \
+                                       ((INSTANCE) == TIM4) || \
+                                       ((INSTANCE) == TIM5) || \
+                                       ((INSTANCE) == TIM8) || \
+                                       ((INSTANCE) == TIM9) || \
+                                       ((INSTANCE) == TIM12)) 
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
+                                         ((INSTANCE) == TIM2) || \
+                                         ((INSTANCE) == TIM3) || \
+                                         ((INSTANCE) == TIM4) || \
+                                         ((INSTANCE) == TIM5) || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                       ((INSTANCE) == TIM2) || \
+                                       ((INSTANCE) == TIM3) || \
+                                       ((INSTANCE) == TIM4) || \
+                                       ((INSTANCE) == TIM5) || \
+                                       ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                           ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
+                                         ((INSTANCE) == TIM2) || \
+                                         ((INSTANCE) == TIM3) || \
+                                         ((INSTANCE) == TIM4) || \
+                                         ((INSTANCE) == TIM5) || \
+                                         ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                       ((INSTANCE) == TIM2) || \
+                                       ((INSTANCE) == TIM3) || \
+                                       ((INSTANCE) == TIM4) || \
+                                       ((INSTANCE) == TIM5) || \
+                                       ((INSTANCE) == TIM6) || \
+                                       ((INSTANCE) == TIM7) || \
+                                       ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                          ((INSTANCE) == TIM2) || \
+                                          ((INSTANCE) == TIM3) || \
+                                          ((INSTANCE) == TIM4) || \
+                                          ((INSTANCE) == TIM5) || \
+                                          ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                          ((INSTANCE) == TIM2) || \
+                                          ((INSTANCE) == TIM3) || \
+                                          ((INSTANCE) == TIM4) || \
+                                          ((INSTANCE) == TIM5) || \
+                                          ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                             ((INSTANCE) == TIM2) || \
+                                             ((INSTANCE) == TIM3) || \
+                                             ((INSTANCE) == TIM4) || \
+                                             ((INSTANCE) == TIM5) || \
+                                             ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM6)   || \
+                                         ((INSTANCE) == TIM7)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM9)   || \
+                                         ((INSTANCE) == TIM12))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                         ((INSTANCE) == TIM2) || \
+                                         ((INSTANCE) == TIM3) || \
+                                         ((INSTANCE) == TIM4) || \
+                                         ((INSTANCE) == TIM5) || \
+                                         ((INSTANCE) == TIM8) || \
+                                         ((INSTANCE) == TIM9) || \
+                                         ((INSTANCE) == TIM12))
+
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+                                              ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                        ((INSTANCE) == TIM2) || \
+                                        ((INSTANCE) == TIM3) || \
+                                        ((INSTANCE) == TIM4) || \
+                                        ((INSTANCE) == TIM5) || \
+                                        ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                         ((INSTANCE) == TIM5)  || \
+                                         ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM2) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM3) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM4) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM5) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM8) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM9) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+    ||                                         \
+    (((INSTANCE) == TIM10) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((INSTANCE) == TIM11) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((INSTANCE) == TIM12) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+    ||                                         \
+    (((INSTANCE) == TIM13) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((INSTANCE) == TIM14) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM8) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3))))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3) || \
+                                     ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5)  || \
+                                    ((INSTANCE) == USART6) || \
+                                    ((INSTANCE) == UART7)  || \
+                                    ((INSTANCE) == UART8))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3) || \
+                                           ((INSTANCE) == USART6))
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3) || \
+                                         ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5)  || \
+                                    ((INSTANCE) == USART6) || \
+                                    ((INSTANCE) == UART7)  || \
+                                    ((INSTANCE) == UART8))                                     
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                       ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                       ((INSTANCE) == USB_OTG_HS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
+
+
+#define RCC_MAX_FREQUENCY           180000000U         /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2    168000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE3    120000000U         /*!< Maximum frequency for system clock at power scale3, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */
+#define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */
+#define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE                 50U
+#define RCC_PLLN_MAX_VALUE                432U
+
+#define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
+#define FLASH_SCALE1_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
+#define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
+#define FLASH_SCALE1_LATENCY4_FREQ   120000000U     /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */
+#define FLASH_SCALE1_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */
+
+#define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
+#define FLASH_SCALE2_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
+#define FLASH_SCALE2_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */
+#define FLASH_SCALE2_LATENCY4_FREQ   12000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */
+#define FLASH_SCALE2_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 2  */
+
+#define FLASH_SCALE3_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */
+#define FLASH_SCALE3_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */
+#define FLASH_SCALE3_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 3  */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32F4xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */
+/*  product lines within the same STM32F4 Family                              */
+/******************************************************************************/
+/* Aliases for __IRQn */
+#define FSMC_IRQn              FMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FSMC_IRQHandler        FMC_IRQHandler
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F437xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f4xx.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,271 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx.h
+  * @author  MCD Application Team
+  * @version V2.6.0
+  * @date    04-November-2016
+  * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32F4xx device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral’s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_HAL_DRIVER"
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx
+  * @{
+  */
+    
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+   
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+  
+/**
+  * @brief STM32 Family
+  */
+#if !defined  (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+    !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+    !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+    !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+    !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+  /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+  /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+  /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
+  /* #define STM32F417xx */   /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+  /* #define STM32F427xx */   /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+   #define STM32F437xx    /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+  /* #define STM32F429xx */   /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, 
+                                   STM32F439NI, STM32F429IG  and STM32F429II Devices */
+  /* #define STM32F439xx */   /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, 
+                                   STM32F439NI, STM32F439IG and STM32F439II Devices */
+  /* #define STM32F401xC */   /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+  /* #define STM32F401xE */   /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+  /* #define STM32F410Tx */   /*!< STM32F410T8 and STM32F410TB Devices */
+  /* #define STM32F410Cx */   /*!< STM32F410C8 and STM32F410CB Devices */
+  /* #define STM32F410Rx */   /*!< STM32F410R8 and STM32F410RB Devices */
+  /* #define STM32F411xE */   /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+  /* #define STM32F446xx */   /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, 
+                                   and STM32F446ZE Devices */
+  /* #define STM32F469xx */   /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG, 
+                                   STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+  /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
+                                   and STM32F479NG Devices */
+  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
+  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+  /* #define STM32F413xx */   /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+                                   STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+  /* #define STM32F423xx */   /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+   
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  #define USE_HAL_DRIVER 
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS version number V2.5.0
+  */
+#define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+                                         |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+                                         |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+                                         |(__STM32F4xx_CMSIS_VERSION))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32F405xx)
+  #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+  #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+  #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+  #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+  #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+  #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+  #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+  #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+  #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+  #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+  #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+  #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+  #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+  #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+  #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+  #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+  #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+  #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+  #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+  #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+  #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+  #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+  #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */ 
+typedef enum 
+{
+  RESET = 0U, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum 
+{
+  DISABLE = 0U, 
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum 
+{
+  ERROR = 0U, 
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/system_stm32f4xx.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,123 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.h
+  * @author  MCD Application Team
+  * @version V2.5.0
+  * @date    22-April-2016
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */ 
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F4xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/objects.h	Wed Apr 12 16:21:43 2017 +0100
@@ -0,0 +1,84 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    IRQn_Type irq_n;
+    uint32_t irq_index;
+    uint32_t event;
+    PinName pin;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+    PinDirection direction;
+    __IO uint32_t *reg_in;
+    __IO uint32_t *reg_out;
+};
+
+struct analogin_s {
+    ADCName adc;
+    PinName pin;
+    uint8_t channel;
+};
+
+struct trng_s {
+    RNG_HandleTypeDef handle;
+};
+
+struct dac_s {
+    DACName dac;
+    uint8_t channel;
+};
+
+#include "common_objects.h"
+struct can_s {
+    CANName can;
+    int index;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/TOOLCHAIN_IAR/stm32l053xx.icf	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/TOOLCHAIN_IAR/stm32l053xx.icf	Wed Apr 12 16:21:43 2017 +0100
@@ -15,8 +15,8 @@
 define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
 
 /* Stack and Heap */
-define symbol __size_cstack__ = 0x500;
-define symbol __size_heap__   = 0x1000;
+define symbol __size_cstack__ = 0x400;
+define symbol __size_heap__   = 0x800;
 define block CSTACK    with alignment = 8, size = __size_cstack__   { };
 define block HEAP      with alignment = 8, size = __size_heap__     { };
 define block STACKHEAP with fixed order { block HEAP, block CSTACK };

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/TOOLCHAIN_ARM_STD/startup_stm32l011xx.S	Thu Mar 30 13:45:57 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,195 +0,0 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32l011xx.s
-;* Author             : MCD Application Team
-;* Version            : V1.5.0
-;* Date               : 8-January-2016
-;* Description        : STM32l011xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-
-__initial_sp    EQU     0x20000800 ; Top of RAM
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     0                              ; Reserved
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     LPUART1_IRQHandler             ; LPUART1
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_IRQHandler                 [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  LPUART1_IRQHandler             [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM21_IRQHandler
-I2C1_IRQHandler
-SPI1_IRQHandler
-USART2_IRQHandler
-LPUART1_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/TOOLCHAIN_ARM_STD/stm32l011k4.sct	Thu Mar 30 13:45:57 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,44 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2014, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32L053C8: 16KB FLASH (0x4000) + 2KB RAM (0x800)
-LR_IROM1 0x08000000 0x4000  {    ; load region size_region
-
-  ER_IROM1 0x08000000 0x4000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-
-  ; Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0xC0) (0x800-0xC0)  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-
-}

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/TOOLCHAIN_ARM_STD/sys.cpp	Thu Mar 30 13:45:57 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model, 
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/TOOLCHAIN_GCC_ARM/STM32L011K4.ld	Thu Mar 30 13:45:57 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,153 +0,0 @@
-/* Linker script to configure memory regions. */
-MEMORY
-{
-  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 16k
-  RAM (rwx) : ORIGIN = 0x200000C0, LENGTH = 2K - 0xC0
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   _estack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    .text :
-    {
-        KEEP(*(.isr_vector))
-        *(.text*)
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        *(.rodata*)
-
-        KEEP(*(.eh_frame*))
-    } > FLASH
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > FLASH
-
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > FLASH
-    __exidx_end = .;
-
-    __etext = .;
-    _sidata = .;
-
-    .data : AT (__etext)
-    {
-        __data_start__ = .;
-        _sdata = .;
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        KEEP(*(.jcr*))
-        . = ALIGN(4);
-        /* All data end */
-        __data_end__ = .;
-        _edata = .;
-
-    } > RAM
-
-    .bss :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        _sbss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-        _ebss = .;
-    } > RAM
-
-    .heap (COPY):
-    {
-        __end__ = .;
-        end = __end__;
-        *(.heap*)
-        __HeapLimit = .;
-    } > RAM
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (COPY):
-    {
-        *(.stack*)
-    } > RAM
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    _estack = __StackTop;
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/TOOLCHAIN_GCC_ARM/startup_stm32l011xx.s	Thu Mar 30 13:45:57 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,256 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l011xx.s
-  * @author    MCD Application Team
-  * @version   V1.5.0
-  * @date      8-January-2016
-  * @brief     STM32L011xx Devices vector table for gcc.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * 
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-   ldr   r0, =_estack
-   mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs  r1, #0
-  b  LoopCopyDataInit
-
-CopyDataInit:
-  ldr  r3, =_sidata
-  ldr  r3, [r3, r1]
-  str  r3, [r0, r1]
-  adds  r1, r1, #4
-
-LoopCopyDataInit:
-  ldr  r0, =_sdata
-  ldr  r3, =_edata
-  adds  r2, r0, r1
-  cmp  r2, r3
-  bcc  CopyDataInit
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-  //bl __libc_init_array
-/* Call the application's entry point.*/
-  //bl  main
-  bl _start
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  0
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_IRQHandler                    /* RCC                          */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     0                                 /* Reserved                     */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     0                                 /* Reserved                     */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     0                                 /* Reserved                     */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     LPUART1_IRQHandler                /* LPUART1                      */
-  .word     0                                 /* Reserved                     */
-  .word     0                                 /* Reserved                     */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_IRQHandler
-   .thumb_set RCC_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      LPUART1_IRQHandler
-   .thumb_set LPUART1_IRQHandler,Default_Handler
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/TOOLCHAIN_IAR/startup_stm32l011xx.s	Thu Mar 30 13:45:57 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,281 +0,0 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32l011xx.s
-;* Author             : MCD Application Team
-;* Version            : V1.5.0
-;* Date               : 8-January-2016
-;* Description        : STM32L011xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     0                              ; Reserved
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     0                              ; Reserved    
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     LPUART1_IRQHandler             ; LPUART1
-                DCD     0                              ; Reserved    
-                DCD     0                              ; Reserved  
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler  
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-            
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-                
-        PUBWEAK LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
-        B LPUART1_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/TOOLCHAIN_IAR/stm32l011xx.icf	Thu Mar 30 13:45:57 2017 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-/* [ROM = 16kb = 0x4000] */
-define symbol __intvec_start__     = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__   = 0x08003FFF;
-
-/* [RAM = 2kb = 0x800] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */
-define symbol __NVIC_start__          = 0x20000000;
-define symbol __NVIC_end__            = 0x200000BF; /* Aligned on 8 bytes */
-define symbol __region_RAM_start__    = 0x200000C0;
-define symbol __region_RAM_end__      = 0x200007FF;
-
-/* Memory regions */
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
-define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
-
-/* Stack and Heap */
-define symbol __size_cstack__ = 0x400;
-define symbol __size_heap__   = 0x200;
-define block CSTACK    with alignment = 8, size = __size_cstack__   { };
-define block HEAP      with alignment = 8, size = __size_heap__     { };
-define block STACKHEAP with fixed order { block HEAP, block CSTACK };
-
-initialize by copy with packing = zeros { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite, block STACKHEAP };

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_IAR/stm32l031xx.icf	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_IAR/stm32l031xx.icf	Wed Apr 12 16:21:43 2017 +0100
@@ -15,8 +15,8 @@
 define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
 
 /* Stack and Heap */
-define symbol __size_cstack__ = 0x500;
-define symbol __size_heap__   = 0x1000;
+define symbol __size_cstack__ = 0x400;
+define symbol __size_heap__   = 0x800;
 define block CSTACK    with alignment = 8, size = __size_cstack__   { };
 define block HEAP      with alignment = 8, size = __size_heap__     { };
 define block STACKHEAP with fixed order { block HEAP, block CSTACK };

--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/TOOLCHAIN_IAR/stm32l053xx.icf	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device/TOOLCHAIN_IAR/stm32l053xx.icf	Wed Apr 12 16:21:43 2017 +0100
@@ -15,8 +15,8 @@
 define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
 
 /* Stack and Heap */
-define symbol __size_cstack__ = 0x500;
-define symbol __size_heap__   = 0x1000;
+define symbol __size_cstack__ = 0x400;
+define symbol __size_heap__   = 0x800;
 define block CSTACK    with alignment = 8, size = __size_cstack__   { };
 define block HEAP      with alignment = 8, size = __size_heap__     { };
 define block STACKHEAP with fixed order { block HEAP, block CSTACK };

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralPins.c	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_NUCLEO_L476RG/PeripheralPins.c	Wed Apr 12 16:21:43 2017 +0100
@@ -41,8 +41,8 @@
 const PinMap PinMap_ADC[] = {
     {PA_0,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  5, 0)}, // IN5 - ARDUINO A0
     {PA_1,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  6, 0)}, // IN6 - ARDUINO A1
-    {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  7, 0)}, // IN7
-    {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  8, 0)}, // IN8
+//  {PA_2,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  7, 0)}, // IN7 // PA_2 is used as SERIAL_TX
+//  {PA_3,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  8, 0)}, // IN8 // PA_3 is used as SERIAL_RX
     {PA_4,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0,  9, 0)}, // IN9 - ARDUINO A2
     {PA_5,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // IN10
     {PA_6,  ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // IN11
@@ -98,10 +98,10 @@
     {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)},  // TIM2_CH2
 //  {PA_1,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)},  // TIM5_CH2 (used by us_ticker)
 //  {PA_1,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N
-    {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3
+//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3 // PA_2 is used as SERIAL_TX
 //  {PA_2,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)},  // TIM5_CH3 (used by us_ticker)
 //  {PA_2,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1
-    {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4
+//  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4 // PA_3 is used as SERIAL_RX
 //  {PA_3,  PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)},  // TIM5_CH4 (used by us_ticker)
 //  {PA_3,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2
     {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)},  // TIM2_CH1
@@ -159,11 +159,11 @@
 
 const PinMap PinMap_UART_TX[] = {
     {PA_0,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
-    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_TX
     {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-//  {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Already used by UART_RX
+    {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
     {PC_1,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
     {PC_4,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
@@ -174,10 +174,10 @@
 
 const PinMap PinMap_UART_RX[] = {
     {PA_1,  UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
-    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_RX
     {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
     {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-//  {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Already used by UART_TX
+    {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
     {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
     {PC_0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
     {PC_5,  UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},

--- a/targets/TARGET_STM/i2c_api.c	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_STM/i2c_api.c	Wed Apr 12 16:21:43 2017 +0100
@@ -904,7 +904,10 @@
 
 #if DEVICE_I2CSLAVE
     /*  restore slave address */
-    i2c_slave_address(obj, 0, address, 0);
+    if (address != 0) {
+        obj_s->slave = 1;
+        i2c_slave_address(obj, 0, address, 0);
+    }
 #endif
 
     /* Keep Set event flag */

--- a/targets/TARGET_STM/mbed_rtx.h	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/TARGET_STM/mbed_rtx.h	Wed Apr 12 16:21:43 2017 +0100
@@ -302,6 +302,21 @@
 #define OS_CLOCK                168000000
 #endif
 
+#elif defined(TARGET_UBLOX_C030)
+
+#ifndef INITIAL_SP
+#define INITIAL_SP              (0x20030000UL)
+#endif
+#ifndef OS_TASKCNT
+#define OS_TASKCNT              14
+#endif
+#ifndef OS_MAINSTKSIZE
+#define OS_MAINSTKSIZE          512
+#endif
+#ifndef OS_CLOCK
+#define OS_CLOCK                168000000
+#endif
+
 #elif defined(TARGET_STM32F469NI)
 
 #ifndef INITIAL_SP

--- a/targets/targets.json	Thu Mar 30 13:45:57 2017 +0100
+++ b/targets/targets.json	Wed Apr 12 16:21:43 2017 +0100
@@ -1334,6 +1334,19 @@
         "device_name": "STM32F439ZI",
         "bootloader_supported": true
     },
+    "UBLOX_C030": {
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "default_toolchain": "ARM",
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "extra_labels": ["STM", "STM32F4", "STM32F437", "STM32F437VG", "STM32F437xx", "STM32F437xG"],
+        "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2", "RTC_LSI=1"],
+        "inherits": ["Target"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "RTC", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"],
+        "features": ["LWIP"],        
+        "release_versions": ["5"],
+        "device_name": "STM32F437VG"
+        },
     "NZ32_SC151": {
         "inherits": ["Target"],
         "core": "Cortex-M3",
@@ -2654,6 +2667,52 @@
         },
         "device_name": "nRF52832_xxAA"
     },
+    "MCU_NRF52840": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4F",
+        "macros": ["TARGET_NRF52840", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S140", "NRF_SD_BLE_API_VERSION=5", "NRF52840_XXAA", "NRF_DFU_SETTINGS_VERSION=1", "NRF_SD_BLE_API_VERSION=5"],
+        "extra_labels": ["NORDIC", "MCU_NRF52840", "NRF5_SDK13"],
+        "OUTPUT_EXT": "hex",
+        "is_disk_virtual": true,
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "public": false,
+        "detect_code": ["1101"],
+        "program_cycle_s": 6,
+        "MERGE_SOFT_DEVICE": true,
+        "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
+            {
+                "boot": "",
+                "name": "s140_nrf52840_5.0.0-1.alpha_softdevice.hex",
+                "offset": 135168
+            }
+        ],
+        "bootloader_select_index": 0,
+        "post_binary_hook": {
+            "function": "MCU_NRF51Code.binary_hook",
+            "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
+        },
+        "MERGE_BOOTLOADER": false,
+        "features": ["BLE"],
+        "config": {
+            "lf_clock_src": {
+                "value": "NRF_LF_SRC_XTAL",
+                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC"
+            },
+            "uart_hwfc": {
+                "help": "Value: 1 for enable, 0 for disable",
+                "value": 1,
+                "macro_name": "MBED_CONF_NORDIC_UART_HWFC"
+            }
+        }
+    },
+    "NRF52840_DK": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF52840"],
+        "macros_add": ["BOARD_PCA10056", "CONFIG_GPIO_AS_PINRESET", "SWI_DISABLE0", "NRF52_ERRATA_20"],
+        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "release_versions": ["2", "5"],
+        "device_name": "nRF52840_xxAA"
+    },
     "BLUEPILL_F103C8": {
         "core": "Cortex-M3",
         "default_toolchain": "GCC_ARM",